LLVM 19.0.0git
AArch64StackTagging.cpp
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1//===- AArch64StackTagging.cpp - Stack tagging in IR --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//===----------------------------------------------------------------------===//
9
10#include "AArch64.h"
11#include "AArch64InstrInfo.h"
12#include "AArch64Subtarget.h"
14#include "llvm/ADT/MapVector.h"
16#include "llvm/ADT/Statistic.h"
18#include "llvm/Analysis/CFG.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Dominators.h"
37#include "llvm/IR/Function.h"
39#include "llvm/IR/IRBuilder.h"
41#include "llvm/IR/Instruction.h"
44#include "llvm/IR/IntrinsicsAArch64.h"
45#include "llvm/IR/Metadata.h"
46#include "llvm/IR/ValueHandle.h"
48#include "llvm/Pass.h"
50#include "llvm/Support/Debug.h"
54#include <cassert>
55#include <iterator>
56#include <memory>
57#include <utility>
58
59using namespace llvm;
60
61#define DEBUG_TYPE "aarch64-stack-tagging"
62
64 "stack-tagging-merge-init", cl::Hidden, cl::init(true),
65 cl::desc("merge stack variable initializers with tagging when possible"));
66
67static cl::opt<bool>
68 ClUseStackSafety("stack-tagging-use-stack-safety", cl::Hidden,
69 cl::init(true),
70 cl::desc("Use Stack Safety analysis results"));
71
72static cl::opt<unsigned> ClScanLimit("stack-tagging-merge-init-scan-limit",
73 cl::init(40), cl::Hidden);
74
76 ClMergeInitSizeLimit("stack-tagging-merge-init-size-limit", cl::init(272),
78
80 "stack-tagging-max-lifetimes-for-alloca", cl::Hidden, cl::init(3),
82 cl::desc("How many lifetime ends to handle for a single alloca."),
84
85static const Align kTagGranuleSize = Align(16);
86
87namespace {
88
89class InitializerBuilder {
90 uint64_t Size;
91 const DataLayout *DL;
92 Value *BasePtr;
93 Function *SetTagFn;
94 Function *SetTagZeroFn;
95 Function *StgpFn;
96
97 // List of initializers sorted by start offset.
98 struct Range {
99 uint64_t Start, End;
100 Instruction *Inst;
101 };
103 // 8-aligned offset => 8-byte initializer
104 // Missing keys are zero initialized.
105 std::map<uint64_t, Value *> Out;
106
107public:
108 InitializerBuilder(uint64_t Size, const DataLayout *DL, Value *BasePtr,
109 Function *SetTagFn, Function *SetTagZeroFn,
110 Function *StgpFn)
111 : Size(Size), DL(DL), BasePtr(BasePtr), SetTagFn(SetTagFn),
112 SetTagZeroFn(SetTagZeroFn), StgpFn(StgpFn) {}
113
114 bool addRange(uint64_t Start, uint64_t End, Instruction *Inst) {
115 auto I =
116 llvm::lower_bound(Ranges, Start, [](const Range &LHS, uint64_t RHS) {
117 return LHS.End <= RHS;
118 });
119 if (I != Ranges.end() && End > I->Start) {
120 // Overlap - bail.
121 return false;
122 }
123 Ranges.insert(I, {Start, End, Inst});
124 return true;
125 }
126
127 bool addStore(uint64_t Offset, StoreInst *SI, const DataLayout *DL) {
128 int64_t StoreSize = DL->getTypeStoreSize(SI->getOperand(0)->getType());
129 if (!addRange(Offset, Offset + StoreSize, SI))
130 return false;
131 IRBuilder<> IRB(SI);
132 applyStore(IRB, Offset, Offset + StoreSize, SI->getOperand(0));
133 return true;
134 }
135
136 bool addMemSet(uint64_t Offset, MemSetInst *MSI) {
137 uint64_t StoreSize = cast<ConstantInt>(MSI->getLength())->getZExtValue();
138 if (!addRange(Offset, Offset + StoreSize, MSI))
139 return false;
140 IRBuilder<> IRB(MSI);
141 applyMemSet(IRB, Offset, Offset + StoreSize,
142 cast<ConstantInt>(MSI->getValue()));
143 return true;
144 }
145
146 void applyMemSet(IRBuilder<> &IRB, int64_t Start, int64_t End,
147 ConstantInt *V) {
148 // Out[] does not distinguish between zero and undef, and we already know
149 // that this memset does not overlap with any other initializer. Nothing to
150 // do for memset(0).
151 if (V->isZero())
152 return;
153 for (int64_t Offset = Start - Start % 8; Offset < End; Offset += 8) {
154 uint64_t Cst = 0x0101010101010101UL;
155 int LowBits = Offset < Start ? (Start - Offset) * 8 : 0;
156 if (LowBits)
157 Cst = (Cst >> LowBits) << LowBits;
158 int HighBits = End - Offset < 8 ? (8 - (End - Offset)) * 8 : 0;
159 if (HighBits)
160 Cst = (Cst << HighBits) >> HighBits;
161 ConstantInt *C =
162 ConstantInt::get(IRB.getInt64Ty(), Cst * V->getZExtValue());
163
164 Value *&CurrentV = Out[Offset];
165 if (!CurrentV) {
166 CurrentV = C;
167 } else {
168 CurrentV = IRB.CreateOr(CurrentV, C);
169 }
170 }
171 }
172
173 // Take a 64-bit slice of the value starting at the given offset (in bytes).
174 // Offset can be negative. Pad with zeroes on both sides when necessary.
175 Value *sliceValue(IRBuilder<> &IRB, Value *V, int64_t Offset) {
176 if (Offset > 0) {
177 V = IRB.CreateLShr(V, Offset * 8);
178 V = IRB.CreateZExtOrTrunc(V, IRB.getInt64Ty());
179 } else if (Offset < 0) {
180 V = IRB.CreateZExtOrTrunc(V, IRB.getInt64Ty());
181 V = IRB.CreateShl(V, -Offset * 8);
182 } else {
183 V = IRB.CreateZExtOrTrunc(V, IRB.getInt64Ty());
184 }
185 return V;
186 }
187
188 void applyStore(IRBuilder<> &IRB, int64_t Start, int64_t End,
189 Value *StoredValue) {
190 StoredValue = flatten(IRB, StoredValue);
191 for (int64_t Offset = Start - Start % 8; Offset < End; Offset += 8) {
192 Value *V = sliceValue(IRB, StoredValue, Offset - Start);
193 Value *&CurrentV = Out[Offset];
194 if (!CurrentV) {
195 CurrentV = V;
196 } else {
197 CurrentV = IRB.CreateOr(CurrentV, V);
198 }
199 }
200 }
201
202 void generate(IRBuilder<> &IRB) {
203 LLVM_DEBUG(dbgs() << "Combined initializer\n");
204 // No initializers => the entire allocation is undef.
205 if (Ranges.empty()) {
206 emitUndef(IRB, 0, Size);
207 return;
208 }
209
210 // Look through 8-byte initializer list 16 bytes at a time;
211 // If one of the two 8-byte halfs is non-zero non-undef, emit STGP.
212 // Otherwise, emit zeroes up to next available item.
213 uint64_t LastOffset = 0;
214 for (uint64_t Offset = 0; Offset < Size; Offset += 16) {
215 auto I1 = Out.find(Offset);
216 auto I2 = Out.find(Offset + 8);
217 if (I1 == Out.end() && I2 == Out.end())
218 continue;
219
220 if (Offset > LastOffset)
221 emitZeroes(IRB, LastOffset, Offset - LastOffset);
222
223 Value *Store1 = I1 == Out.end() ? Constant::getNullValue(IRB.getInt64Ty())
224 : I1->second;
225 Value *Store2 = I2 == Out.end() ? Constant::getNullValue(IRB.getInt64Ty())
226 : I2->second;
227 emitPair(IRB, Offset, Store1, Store2);
228 LastOffset = Offset + 16;
229 }
230
231 // memset(0) does not update Out[], therefore the tail can be either undef
232 // or zero.
233 if (LastOffset < Size)
234 emitZeroes(IRB, LastOffset, Size - LastOffset);
235
236 for (const auto &R : Ranges) {
237 R.Inst->eraseFromParent();
238 }
239 }
240
241 void emitZeroes(IRBuilder<> &IRB, uint64_t Offset, uint64_t Size) {
242 LLVM_DEBUG(dbgs() << " [" << Offset << ", " << Offset + Size
243 << ") zero\n");
244 Value *Ptr = BasePtr;
245 if (Offset)
247 IRB.CreateCall(SetTagZeroFn,
248 {Ptr, ConstantInt::get(IRB.getInt64Ty(), Size)});
249 }
250
251 void emitUndef(IRBuilder<> &IRB, uint64_t Offset, uint64_t Size) {
252 LLVM_DEBUG(dbgs() << " [" << Offset << ", " << Offset + Size
253 << ") undef\n");
254 Value *Ptr = BasePtr;
255 if (Offset)
257 IRB.CreateCall(SetTagFn, {Ptr, ConstantInt::get(IRB.getInt64Ty(), Size)});
258 }
259
260 void emitPair(IRBuilder<> &IRB, uint64_t Offset, Value *A, Value *B) {
261 LLVM_DEBUG(dbgs() << " [" << Offset << ", " << Offset + 16 << "):\n");
262 LLVM_DEBUG(dbgs() << " " << *A << "\n " << *B << "\n");
263 Value *Ptr = BasePtr;
264 if (Offset)
266 IRB.CreateCall(StgpFn, {Ptr, A, B});
267 }
268
269 Value *flatten(IRBuilder<> &IRB, Value *V) {
270 if (V->getType()->isIntegerTy())
271 return V;
272 // vector of pointers -> vector of ints
273 if (VectorType *VecTy = dyn_cast<VectorType>(V->getType())) {
274 LLVMContext &Ctx = IRB.getContext();
275 Type *EltTy = VecTy->getElementType();
276 if (EltTy->isPointerTy()) {
277 uint32_t EltSize = DL->getTypeSizeInBits(EltTy);
278 auto *NewTy = FixedVectorType::get(
279 IntegerType::get(Ctx, EltSize),
280 cast<FixedVectorType>(VecTy)->getNumElements());
281 V = IRB.CreatePointerCast(V, NewTy);
282 }
283 }
284 return IRB.CreateBitOrPointerCast(
285 V, IRB.getIntNTy(DL->getTypeStoreSize(V->getType()) * 8));
286 }
287};
288
289class AArch64StackTagging : public FunctionPass {
290 const bool MergeInit;
291 const bool UseStackSafety;
292
293public:
294 static char ID; // Pass ID, replacement for typeid
295
296 AArch64StackTagging(bool IsOptNone = false)
297 : FunctionPass(ID),
298 MergeInit(ClMergeInit.getNumOccurrences() ? ClMergeInit : !IsOptNone),
299 UseStackSafety(ClUseStackSafety.getNumOccurrences() ? ClUseStackSafety
300 : !IsOptNone) {
302 }
303
304 void tagAlloca(AllocaInst *AI, Instruction *InsertBefore, Value *Ptr,
305 uint64_t Size);
306 void untagAlloca(AllocaInst *AI, Instruction *InsertBefore, uint64_t Size);
307
308 Instruction *collectInitializers(Instruction *StartInst, Value *StartPtr,
309 uint64_t Size, InitializerBuilder &IB);
310
311 Instruction *insertBaseTaggedPointer(
313 const DominatorTree *DT);
314 bool runOnFunction(Function &F) override;
315
316 StringRef getPassName() const override { return "AArch64 Stack Tagging"; }
317
318private:
319 Function *F = nullptr;
320 Function *SetTagFunc = nullptr;
321 const DataLayout *DL = nullptr;
322 AAResults *AA = nullptr;
323 const StackSafetyGlobalInfo *SSI = nullptr;
324
325 void getAnalysisUsage(AnalysisUsage &AU) const override {
326 AU.setPreservesCFG();
327 if (UseStackSafety)
329 if (MergeInit)
331 }
332};
333
334} // end anonymous namespace
335
336char AArch64StackTagging::ID = 0;
337
338INITIALIZE_PASS_BEGIN(AArch64StackTagging, DEBUG_TYPE, "AArch64 Stack Tagging",
339 false, false)
342INITIALIZE_PASS_END(AArch64StackTagging, DEBUG_TYPE, "AArch64 Stack Tagging",
344
346 return new AArch64StackTagging(IsOptNone);
347}
348
349Instruction *AArch64StackTagging::collectInitializers(Instruction *StartInst,
350 Value *StartPtr,
352 InitializerBuilder &IB) {
353 MemoryLocation AllocaLoc{StartPtr, Size};
354 Instruction *LastInst = StartInst;
355 BasicBlock::iterator BI(StartInst);
356
357 unsigned Count = 0;
358 for (; Count < ClScanLimit && !BI->isTerminator(); ++BI) {
359 if (!isa<DbgInfoIntrinsic>(*BI))
360 ++Count;
361
362 if (isNoModRef(AA->getModRefInfo(&*BI, AllocaLoc)))
363 continue;
364
365 if (!isa<StoreInst>(BI) && !isa<MemSetInst>(BI)) {
366 // If the instruction is readnone, ignore it, otherwise bail out. We
367 // don't even allow readonly here because we don't want something like:
368 // A[1] = 2; strlen(A); A[2] = 2; -> memcpy(A, ...); strlen(A).
369 if (BI->mayWriteToMemory() || BI->mayReadFromMemory())
370 break;
371 continue;
372 }
373
374 if (StoreInst *NextStore = dyn_cast<StoreInst>(BI)) {
375 if (!NextStore->isSimple())
376 break;
377
378 // Check to see if this store is to a constant offset from the start ptr.
379 std::optional<int64_t> Offset =
380 NextStore->getPointerOperand()->getPointerOffsetFrom(StartPtr, *DL);
381 if (!Offset)
382 break;
383
384 if (!IB.addStore(*Offset, NextStore, DL))
385 break;
386 LastInst = NextStore;
387 } else {
388 MemSetInst *MSI = cast<MemSetInst>(BI);
389
390 if (MSI->isVolatile() || !isa<ConstantInt>(MSI->getLength()))
391 break;
392
393 if (!isa<ConstantInt>(MSI->getValue()))
394 break;
395
396 // Check to see if this store is to a constant offset from the start ptr.
397 std::optional<int64_t> Offset =
398 MSI->getDest()->getPointerOffsetFrom(StartPtr, *DL);
399 if (!Offset)
400 break;
401
402 if (!IB.addMemSet(*Offset, MSI))
403 break;
404 LastInst = MSI;
405 }
406 }
407 return LastInst;
408}
409
410void AArch64StackTagging::tagAlloca(AllocaInst *AI, Instruction *InsertBefore,
412 auto SetTagZeroFunc =
413 Intrinsic::getDeclaration(F->getParent(), Intrinsic::aarch64_settag_zero);
414 auto StgpFunc =
415 Intrinsic::getDeclaration(F->getParent(), Intrinsic::aarch64_stgp);
416
417 InitializerBuilder IB(Size, DL, Ptr, SetTagFunc, SetTagZeroFunc, StgpFunc);
418 bool LittleEndian =
420 // Current implementation of initializer merging assumes little endianness.
421 if (MergeInit && !F->hasOptNone() && LittleEndian &&
423 LLVM_DEBUG(dbgs() << "collecting initializers for " << *AI
424 << ", size = " << Size << "\n");
425 InsertBefore = collectInitializers(InsertBefore, Ptr, Size, IB);
426 }
427
428 IRBuilder<> IRB(InsertBefore);
429 IB.generate(IRB);
430}
431
432void AArch64StackTagging::untagAlloca(AllocaInst *AI, Instruction *InsertBefore,
433 uint64_t Size) {
434 IRBuilder<> IRB(InsertBefore);
435 IRB.CreateCall(SetTagFunc, {IRB.CreatePointerCast(AI, IRB.getPtrTy()),
436 ConstantInt::get(IRB.getInt64Ty(), Size)});
437}
438
439Instruction *AArch64StackTagging::insertBaseTaggedPointer(
440 const MapVector<AllocaInst *, memtag::AllocaInfo> &AllocasToInstrument,
441 const DominatorTree *DT) {
442 BasicBlock *PrologueBB = nullptr;
443 // Try sinking IRG as deep as possible to avoid hurting shrink wrap.
444 for (auto &I : AllocasToInstrument) {
445 const memtag::AllocaInfo &Info = I.second;
446 AllocaInst *AI = Info.AI;
447 if (!PrologueBB) {
448 PrologueBB = AI->getParent();
449 continue;
450 }
451 PrologueBB = DT->findNearestCommonDominator(PrologueBB, AI->getParent());
452 }
453 assert(PrologueBB);
454
455 IRBuilder<> IRB(&PrologueBB->front());
456 Function *IRG_SP =
457 Intrinsic::getDeclaration(F->getParent(), Intrinsic::aarch64_irg_sp);
459 IRB.CreateCall(IRG_SP, {Constant::getNullValue(IRB.getInt64Ty())});
460 Base->setName("basetag");
461 return Base;
462}
463
464// FIXME: check for MTE extension
465bool AArch64StackTagging::runOnFunction(Function &Fn) {
466 if (!Fn.hasFnAttribute(Attribute::SanitizeMemTag))
467 return false;
468
469 if (UseStackSafety)
470 SSI = &getAnalysis<StackSafetyGlobalInfoWrapperPass>().getResult();
471 F = &Fn;
472 DL = &Fn.getParent()->getDataLayout();
473 if (MergeInit)
474 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
475
477 for (Instruction &I : instructions(F))
478 SIB.visit(I);
479 memtag::StackInfo &SInfo = SIB.get();
480
481 if (SInfo.AllocasToInstrument.empty())
482 return false;
483
484 std::unique_ptr<DominatorTree> DeleteDT;
485 DominatorTree *DT = nullptr;
486 if (auto *P = getAnalysisIfAvailable<DominatorTreeWrapperPass>())
487 DT = &P->getDomTree();
488
489 if (DT == nullptr) {
490 DeleteDT = std::make_unique<DominatorTree>(*F);
491 DT = DeleteDT.get();
492 }
493
494 std::unique_ptr<PostDominatorTree> DeletePDT;
495 PostDominatorTree *PDT = nullptr;
496 if (auto *P = getAnalysisIfAvailable<PostDominatorTreeWrapperPass>())
497 PDT = &P->getPostDomTree();
498
499 if (PDT == nullptr) {
500 DeletePDT = std::make_unique<PostDominatorTree>(*F);
501 PDT = DeletePDT.get();
502 }
503
504 std::unique_ptr<LoopInfo> DeleteLI;
505 LoopInfo *LI = nullptr;
506 if (auto *LIWP = getAnalysisIfAvailable<LoopInfoWrapperPass>()) {
507 LI = &LIWP->getLoopInfo();
508 } else {
509 DeleteLI = std::make_unique<LoopInfo>(*DT);
510 LI = DeleteLI.get();
511 }
512
513 SetTagFunc =
514 Intrinsic::getDeclaration(F->getParent(), Intrinsic::aarch64_settag);
515
516 Instruction *Base = insertBaseTaggedPointer(SInfo.AllocasToInstrument, DT);
517
518 int NextTag = 0;
519 for (auto &I : SInfo.AllocasToInstrument) {
520 memtag::AllocaInfo &Info = I.second;
521 assert(Info.AI && SIB.isInterestingAlloca(*Info.AI));
523 AllocaInst *AI = Info.AI;
524 int Tag = NextTag;
525 NextTag = (NextTag + 1) % 16;
526 // Replace alloca with tagp(alloca).
527 IRBuilder<> IRB(Info.AI->getNextNode());
529 F->getParent(), Intrinsic::aarch64_tagp, {Info.AI->getType()});
530 Instruction *TagPCall =
531 IRB.CreateCall(TagP, {Constant::getNullValue(Info.AI->getType()), Base,
532 ConstantInt::get(IRB.getInt64Ty(), Tag)});
533 if (Info.AI->hasName())
534 TagPCall->setName(Info.AI->getName() + ".tag");
535 // Does not replace metadata, so we don't have to handle DbgVariableRecords.
536 Info.AI->replaceUsesWithIf(TagPCall, [&](const Use &U) {
537 return !memtag::isLifetimeIntrinsic(U.getUser());
538 });
539 TagPCall->setOperand(0, Info.AI);
540
541 // Calls to functions that may return twice (e.g. setjmp) confuse the
542 // postdominator analysis, and will leave us to keep memory tagged after
543 // function return. Work around this by always untagging at every return
544 // statement if return_twice functions are called.
545 bool StandardLifetime =
546 !SInfo.CallsReturnTwice &&
547 SInfo.UnrecognizedLifetimes.empty() &&
548 memtag::isStandardLifetime(Info.LifetimeStart, Info.LifetimeEnd, DT, LI,
550 if (StandardLifetime) {
551 IntrinsicInst *Start = Info.LifetimeStart[0];
552 uint64_t Size =
553 cast<ConstantInt>(Start->getArgOperand(0))->getZExtValue();
555 tagAlloca(AI, Start->getNextNode(), TagPCall, Size);
556
557 auto TagEnd = [&](Instruction *Node) { untagAlloca(AI, Node, Size); };
558 if (!DT || !PDT ||
559 !memtag::forAllReachableExits(*DT, *PDT, *LI, Start, Info.LifetimeEnd,
560 SInfo.RetVec, TagEnd)) {
561 for (auto *End : Info.LifetimeEnd)
562 End->eraseFromParent();
563 }
564 } else {
565 uint64_t Size = *Info.AI->getAllocationSize(*DL);
566 Value *Ptr = IRB.CreatePointerCast(TagPCall, IRB.getPtrTy());
567 tagAlloca(AI, &*IRB.GetInsertPoint(), Ptr, Size);
568 for (auto *RI : SInfo.RetVec) {
569 untagAlloca(AI, RI, Size);
570 }
571 // We may have inserted tag/untag outside of any lifetime interval.
572 // Remove all lifetime intrinsics for this alloca.
573 for (auto *II : Info.LifetimeStart)
574 II->eraseFromParent();
575 for (auto *II : Info.LifetimeEnd)
576 II->eraseFromParent();
577 }
578 }
579
580 // If we have instrumented at least one alloca, all unrecognized lifetime
581 // intrinsics have to go.
582 for (auto *I : SInfo.UnrecognizedLifetimes)
583 I->eraseFromParent();
584
585 return true;
586}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static cl::opt< bool > ClMergeInit("stack-tagging-merge-init", cl::Hidden, cl::init(true), cl::desc("merge stack variable initializers with tagging when possible"))
static cl::opt< unsigned > ClMergeInitSizeLimit("stack-tagging-merge-init-size-limit", cl::init(272), cl::Hidden)
static cl::opt< unsigned > ClScanLimit("stack-tagging-merge-init-scan-limit", cl::init(40), cl::Hidden)
static cl::opt< bool > ClUseStackSafety("stack-tagging-use-stack-safety", cl::Hidden, cl::init(true), cl::desc("Use Stack Safety analysis results"))
static cl::opt< size_t > ClMaxLifetimes("stack-tagging-max-lifetimes-for-alloca", cl::Hidden, cl::init(3), cl::ReallyHidden, cl::desc("How many lifetime ends to handle for a single alloca."), cl::Optional)
AArch64 Stack Tagging
#define DEBUG_TYPE
static const Align kTagGranuleSize
Expand Atomic instructions
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_DEBUG(X)
Definition: Debug.h:101
uint64_t Size
bool End
Definition: ELF_riscv.cpp:480
A set of register units.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file implements a map that provides insertion order iteration.
static void addRange(SmallVectorImpl< ConstantInt * > &EndPoints, ConstantInt *Low, ConstantInt *High)
Definition: Metadata.cpp:1269
This file contains the declarations for metadata subclasses.
#define P(N)
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
This file defines the 'Statistic' class, which is designed to be an easy way to expose various metric...
Target-Independent Code Generator Pass Configuration Options pass.
Value * RHS
Value * LHS
A wrapper pass to provide the legacy pass manager access to a suitably prepared AAResults object.
ModRefInfo getModRefInfo(const Instruction *I, const std::optional< MemoryLocation > &OptLoc)
Check whether or not an instruction may read or write the optionally specified memory location.
an instruction to allocate memory on the stack
Definition: Instructions.h:59
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:269
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
const Instruction & front() const
Definition: BasicBlock.h:453
InstListType::iterator iterator
Instruction iterators...
Definition: BasicBlock.h:165
This is the shared class of boolean and integer constants.
Definition: Constants.h:80
static Constant * getNullValue(Type *Ty)
Constructor to create a '0' constant of arbitrary type.
Definition: Constants.cpp:370
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:162
Instruction * findNearestCommonDominator(Instruction *I1, Instruction *I2) const
Find the nearest instruction I that dominates both I1 and I2, in the sense that a result produced bef...
Definition: Dominators.cpp:344
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:692
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
virtual bool runOnFunction(Function &F)=0
runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.cpp:675
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:656
Value * CreateConstGEP1_32(Type *Ty, Value *Ptr, unsigned Idx0, const Twine &Name="")
Definition: IRBuilder.h:1881
IntegerType * getIntNTy(unsigned N)
Fetch the type representing an N-bit integer.
Definition: IRBuilder.h:539
Value * CreateZExtOrTrunc(Value *V, Type *DestTy, const Twine &Name="")
Create a ZExt or Trunc from the integer value V to DestTy.
Definition: IRBuilder.h:2039
Value * CreatePointerCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:2170
BasicBlock::iterator GetInsertPoint() const
Definition: IRBuilder.h:175
Value * CreateLShr(Value *LHS, Value *RHS, const Twine &Name="", bool isExact=false)
Definition: IRBuilder.h:1437
IntegerType * getInt64Ty()
Fetch the type representing a 64-bit integer.
Definition: IRBuilder.h:531
Value * CreateBitOrPointerCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:2205
Value * CreateShl(Value *LHS, Value *RHS, const Twine &Name="", bool HasNUW=false, bool HasNSW=false)
Definition: IRBuilder.h:1416
LLVMContext & getContext() const
Definition: IRBuilder.h:176
Value * CreateOr(Value *LHS, Value *RHS, const Twine &Name="")
Definition: IRBuilder.h:1497
PointerType * getPtrTy(unsigned AddrSpace=0)
Fetch the type representing a pointer.
Definition: IRBuilder.h:569
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=std::nullopt, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2412
IntegerType * getInt8Ty()
Fetch the type representing an 8-bit integer.
Definition: IRBuilder.h:516
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:2666
const Module * getModule() const
Return the module owning the function this instruction belongs to or nullptr it the function does not...
Definition: Instruction.cpp:82
const BasicBlock * getParent() const
Definition: Instruction.h:152
static IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
Definition: Type.cpp:278
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
This class implements a map that also provides access to all stored values in a deterministic order.
Definition: MapVector.h:36
Value * getLength() const
Value * getDest() const
This is just like getRawDest, but it strips off any cast instructions (including addrspacecast) that ...
bool isVolatile() const
Value * getValue() const
This class wraps the llvm.memset and llvm.memset.inline intrinsics.
Representation for a specific memory location.
const std::string & getTargetTriple() const
Get the target triple which is a string describing the target host.
Definition: Module.h:297
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Definition: Module.h:293
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual void getAnalysisUsage(AnalysisUsage &) const
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: Pass.cpp:98
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
PostDominatorTree Class - Concrete subclass of DominatorTree that is used to compute the post-dominat...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
This pass performs the global (interprocedural) stack safety analysis (legacy pass manager).
An instruction for storing to memory.
Definition: Instructions.h:317
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isLittleEndian() const
Tests whether the target triple is little endian.
Definition: Triple.cpp:1818
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isPointerTy() const
True if this is an instance of PointerType.
Definition: Type.h:255
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
void setOperand(unsigned i, Value *Val)
Definition: User.h:174
LLVM Value Representation.
Definition: Value.h:74
void setName(const Twine &Name)
Change the name of the value.
Definition: Value.cpp:377
std::optional< int64_t > getPointerOffsetFrom(const Value *Other, const DataLayout &DL) const
If this ptr is provably equal to Other plus a constant offset, return that offset in bytes.
Definition: Value.cpp:1027
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=std::nullopt)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
Definition: Function.cpp:1461
@ ReallyHidden
Definition: CommandLine.h:139
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
bool isStandardLifetime(const SmallVectorImpl< IntrinsicInst * > &LifetimeStart, const SmallVectorImpl< IntrinsicInst * > &LifetimeEnd, const DominatorTree *DT, const LoopInfo *LI, size_t MaxLifetimes)
bool forAllReachableExits(const DominatorTree &DT, const PostDominatorTree &PDT, const LoopInfo &LI, const Instruction *Start, const SmallVectorImpl< IntrinsicInst * > &Ends, const SmallVectorImpl< Instruction * > &RetVec, llvm::function_ref< void(Instruction *)> Callback)
void alignAndPadAlloca(memtag::AllocaInfo &Info, llvm::Align Align)
bool isLifetimeIntrinsic(Value *V)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
void initializeAArch64StackTaggingPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1954
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
FunctionPass * createAArch64StackTaggingPass(bool IsOptNone)
bool isNoModRef(const ModRefInfo MRI)
Definition: ModRef.h:39
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
MapVector< AllocaInst *, AllocaInfo > AllocasToInstrument
SmallVector< Instruction *, 4 > UnrecognizedLifetimes
SmallVector< Instruction *, 8 > RetVec