LLVM 17.0.0git
SIDefines.h
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1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInstrDesc.h"
14
15namespace llvm {
16
17// This needs to be kept in sync with the field bits in SIRegisterClass.
18enum SIRCFlags : uint8_t {
19 // For vector registers.
20 HasVGPR = 1 << 0,
21 HasAGPR = 1 << 1,
22 HasSGPR = 1 << 2
23}; // enum SIRCFlags
24
25namespace SIInstrFlags {
26// This needs to be kept in sync with the field bits in InstSI.
27enum : uint64_t {
28 // Low bits - basic encoding information.
29 SALU = 1 << 0,
30 VALU = 1 << 1,
31
32 // SALU instruction formats.
33 SOP1 = 1 << 2,
34 SOP2 = 1 << 3,
35 SOPC = 1 << 4,
36 SOPK = 1 << 5,
37 SOPP = 1 << 6,
38
39 // VALU instruction formats.
40 VOP1 = 1 << 7,
41 VOP2 = 1 << 8,
42 VOPC = 1 << 9,
43
44 // TODO: Should this be spilt into VOP3 a and b?
45 VOP3 = 1 << 10,
46 VOP3P = 1 << 12,
47
48 VINTRP = 1 << 13,
49 SDWA = 1 << 14,
50 DPP = 1 << 15,
51 TRANS = 1 << 16,
52
53 // Memory instruction formats.
54 MUBUF = 1 << 17,
55 MTBUF = 1 << 18,
56 SMRD = 1 << 19,
57 MIMG = 1 << 20,
58 EXP = 1 << 21,
59 FLAT = 1 << 22,
60 DS = 1 << 23,
61
62 // Pseudo instruction formats.
63 VGPRSpill = 1 << 24,
64 SGPRSpill = 1 << 25,
65
66 // LDSDIR instruction format.
67 LDSDIR = 1 << 26,
68
69 // VINTERP instruction format.
70 VINTERP = 1 << 27,
71
72 // High bits - other information.
73 VM_CNT = UINT64_C(1) << 32,
74 EXP_CNT = UINT64_C(1) << 33,
75 LGKM_CNT = UINT64_C(1) << 34,
76
77 WQM = UINT64_C(1) << 35,
78 DisableWQM = UINT64_C(1) << 36,
79 Gather4 = UINT64_C(1) << 37,
80 SOPK_ZEXT = UINT64_C(1) << 38,
81 SCALAR_STORE = UINT64_C(1) << 39,
82 FIXED_SIZE = UINT64_C(1) << 40,
83 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
84 VOP3_OPSEL = UINT64_C(1) << 42,
85 maybeAtomic = UINT64_C(1) << 43,
86 renamedInGFX9 = UINT64_C(1) << 44,
87
88 // Is a clamp on FP type.
89 FPClamp = UINT64_C(1) << 45,
90
91 // Is an integer clamp
92 IntClamp = UINT64_C(1) << 46,
93
94 // Clamps lo component of register.
95 ClampLo = UINT64_C(1) << 47,
96
97 // Clamps hi component of register.
98 // ClampLo and ClampHi set for packed clamp.
99 ClampHi = UINT64_C(1) << 48,
100
101 // Is a packed VOP3P instruction.
102 IsPacked = UINT64_C(1) << 49,
103
104 // Is a D16 buffer instruction.
105 D16Buf = UINT64_C(1) << 50,
106
107 // FLAT instruction accesses FLAT_GLBL segment.
108 FlatGlobal = UINT64_C(1) << 51,
109
110 // Uses floating point double precision rounding mode
111 FPDPRounding = UINT64_C(1) << 52,
112
113 // Instruction is FP atomic.
114 FPAtomic = UINT64_C(1) << 53,
115
116 // Is a MFMA instruction.
117 IsMAI = UINT64_C(1) << 54,
118
119 // Is a DOT instruction.
120 IsDOT = UINT64_C(1) << 55,
121
122 // FLAT instruction accesses FLAT_SCRATCH segment.
123 FlatScratch = UINT64_C(1) << 56,
124
125 // Atomic without return.
126 IsAtomicNoRet = UINT64_C(1) << 57,
127
128 // Atomic with return.
129 IsAtomicRet = UINT64_C(1) << 58,
130
131 // Is a WMMA instruction.
132 IsWMMA = UINT64_C(1) << 59,
133
134 // Whether tied sources will be read.
135 TiedSourceNotRead = UINT64_C(1) << 60,
136};
137
138// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
139// The result is true if any of these tests are true.
140enum ClassFlags : unsigned {
141 S_NAN = 1 << 0, // Signaling NaN
142 Q_NAN = 1 << 1, // Quiet NaN
143 N_INFINITY = 1 << 2, // Negative infinity
144 N_NORMAL = 1 << 3, // Negative normal
145 N_SUBNORMAL = 1 << 4, // Negative subnormal
146 N_ZERO = 1 << 5, // Negative zero
147 P_ZERO = 1 << 6, // Positive zero
148 P_SUBNORMAL = 1 << 7, // Positive subnormal
149 P_NORMAL = 1 << 8, // Positive normal
150 P_INFINITY = 1 << 9 // Positive infinity
152}
153
154namespace AMDGPU {
155enum OperandType : unsigned {
156 /// Operands with register or 32-bit immediate
169
170 /// Operands with register or inline constant
181
182 /// Operand with 32-bit immediate that uses the constant bus.
185
186 /// Operands with an AccVGPR register or inline constant
196
197 // Operand for source modifiers for VOP instructions
199
200 // Operand for SDWA instructions
202
205
208
211
214
217
219}
220
221// Input operand modifiers bit-masks
222// NEG and SEXT share same bit-mask because they can't be set simultaneously.
223namespace SISrcMods {
224 enum : unsigned {
225 NEG = 1 << 0, // Floating-point negate modifier
226 ABS = 1 << 1, // Floating-point absolute modifier
227 SEXT = 1 << 0, // Integer sign-extend modifier
228 NEG_HI = ABS, // Floating-point negate high packed component modifier.
229 OP_SEL_0 = 1 << 2,
230 OP_SEL_1 = 1 << 3,
231 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
232 };
233}
234
235namespace SIOutMods {
236 enum : unsigned {
237 NONE = 0,
238 MUL2 = 1,
239 MUL4 = 2,
240 DIV2 = 3
241 };
242}
243
244namespace AMDGPU {
245namespace VGPRIndexMode {
246
247enum Id : unsigned { // id of symbolic names
252
254 ID_MAX = ID_DST
256
257enum EncBits : unsigned {
258 OFF = 0,
264 UNDEF = 0xFFFF
266
267} // namespace VGPRIndexMode
268} // namespace AMDGPU
269
270namespace AMDGPUAsmVariants {
271 enum : unsigned {
273 VOP3 = 1,
274 SDWA = 2,
275 SDWA9 = 3,
276 DPP = 4,
277 VOP3_DPP = 5
278 };
279} // namespace AMDGPUAsmVariants
280
281namespace AMDGPU {
282namespace EncValues { // Encoding values of enum9/8/7 operands
283
284enum : unsigned {
298 VGPR_MIN = 256,
299 VGPR_MAX = 511,
300 IS_VGPR = 256 // Indicates VGPR or AGPR
302
303} // namespace EncValues
304} // namespace AMDGPU
305
306namespace AMDGPU {
307namespace CPol {
308
309enum CPol {
310 GLC = 1,
311 SLC = 2,
312 DLC = 4,
313 SCC = 16,
317 ALL = GLC | SLC | DLC | SCC
319
320} // namespace CPol
321
322namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
323
324enum Id { // Message ID, width(4) [3:0].
326
327 ID_GS_PreGFX11 = 2, // replaced in GFX11
328 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
329
330 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
331 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
332
333 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
334 ID_STALL_WAVE_GEN = 5, // added in GFX9
335 ID_HALT_WAVES = 6, // added in GFX9
336 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
337 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
338 ID_GS_ALLOC_REQ = 9, // added in GFX9
339 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
340 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
342
349
351 ID_MASK_GFX11Plus_ = 0xFF
353
354enum Op { // Both GS and SYS operation IDs.
358 // Bits used for operation encoding
360 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
361 // GS operations are encoded in bits 5:4
368 // SYS operations are encoded in bits 6:4
375};
376
377enum StreamId : unsigned { // Stream ID, (2) [9:8].
386
387} // namespace SendMsg
388
389namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
390
391enum Id { // HwRegCode, (6) [5:0]
416
419 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
421
422enum Offset : unsigned { // Offset, (5) [10:6]
427
429};
430
431enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
436};
437
438// Some values from WidthMinusOne mapped into Width domain.
439enum Width : unsigned {
441};
442
444 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
445 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
448 LOD_CLAMP_MASK = 1 << 10,
449 DEBUG_MASK = 1 << 11,
450
451 // EXCP_EN fields.
459
461 VSKIP_MASK = 1 << 28,
462 CSP_MASK = 0x7u << 29 // Bits 29..31
464
465} // namespace Hwreg
466
467namespace MTBUFFormat {
468
469enum DataFormat : int64_t {
486
489
492
494 DFMT_MASK = 0xF
496
497enum NumFormat : int64_t {
504 NFMT_RESERVED_6, // VI and GFX9
505 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
507
510
513
515 NFMT_MASK = 7
517
518enum MergedFormat : int64_t {
522
523
525
528
529enum UnifiedFormatCommon : int64_t {
530 UFMT_MAX = 127,
532 UFMT_DEFAULT = 1
534
535} // namespace MTBUFFormat
536
537namespace UfmtGFX10 {
538enum UnifiedFormat : int64_t {
540
547
555
562
566
574
582
590
597
604
611
615
623
630
633};
634
635} // namespace UfmtGFX10
636
637namespace UfmtGFX11 {
638enum UnifiedFormat : int64_t {
640
647
655
662
666
674
676
678
683
690
697
701
709
716
719};
720
721} // namespace UfmtGFX11
722
723namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
724
725enum Id : unsigned { // id of symbolic names
732
733enum EncBits : unsigned {
734
735 // swizzle mode encodings
736
739
742
743 // QUAD_PERM encodings
744
749
750 // BITMASK_PERM encodings
751
755
760
761} // namespace Swizzle
762
763namespace SDWA {
764
765enum SdwaSel : unsigned {
772 DWORD = 6,
773};
774
775enum DstUnused : unsigned {
779};
780
781enum SDWA9EncValues : unsigned {
786
794};
795
796} // namespace SDWA
797
798namespace DPP {
799
800// clang-format off
801enum DppCtrl : unsigned {
803 QUAD_PERM_ID = 0xE4, // identity permutation
805 DPP_UNUSED1 = 0x100,
806 ROW_SHL0 = 0x100,
809 DPP_UNUSED2 = 0x110,
810 ROW_SHR0 = 0x110,
813 DPP_UNUSED3 = 0x120,
814 ROW_ROR0 = 0x120,
817 WAVE_SHL1 = 0x130,
820 WAVE_ROL1 = 0x134,
823 WAVE_SHR1 = 0x138,
826 WAVE_ROR1 = 0x13C,
829 ROW_MIRROR = 0x140,
831 BCAST15 = 0x142,
832 BCAST31 = 0x143,
837 ROW_SHARE0 = 0x150,
840 ROW_XMASK0 = 0x160,
845// clang-format on
846
850 DPP8_FI_0 = 0xE9,
851 DPP8_FI_1 = 0xEA,
852};
853
854} // namespace DPP
855
856namespace Exp {
857
858enum Target : unsigned {
862 ET_NULL = 9, // Pre-GFX11
865 ET_POS4 = 16, // GFX10+
866 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
867 ET_PRIM = 20, // GFX10+
868 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
869 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
870 ET_PARAM0 = 32, // Pre-GFX11
871 ET_PARAM31 = 63, // Pre-GFX11
872
880
882};
883
884} // namespace Exp
885
886namespace VOP3PEncoding {
887
889 OP_SEL_HI_0 = UINT64_C(1) << 59,
890 OP_SEL_HI_1 = UINT64_C(1) << 60,
891 OP_SEL_HI_2 = UINT64_C(1) << 14,
892};
893
894} // namespace VOP3PEncoding
895
896namespace ImplicitArg {
897// Implicit kernel argument offset for code object version 5.
898enum Offset_COV5 : unsigned {
902
905
909};
910
911} // namespace ImplicitArg
912} // namespace AMDGPU
913
914#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
915#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
916#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
917#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
918#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
919#define C_00B028_MEM_ORDERED 0xFDFFFFFF
920
921#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
922#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
923#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
924#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
925#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
926#define C_00B128_MEM_ORDERED 0xF7FFFFFF
927
928#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
929#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
930#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
931#define C_00B228_WGP_MODE 0xF7FFFFFF
932#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
933#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
934#define C_00B228_MEM_ORDERED 0xFDFFFFFF
935
936#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
937#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
938#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
939#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
940#define C_00B428_WGP_MODE 0xFBFFFFFF
941#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
942#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
943#define C_00B428_MEM_ORDERED 0xFEFFFFFF
944
945#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
946
947#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
948#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
949#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
950#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
951#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
952#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
953#define C_00B84C_USER_SGPR 0xFFFFFFC1
954#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
955#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
956#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
957#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
958#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
959#define C_00B84C_TGID_X_EN 0xFFFFFF7F
960#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
961#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
962#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
963#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
964#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
965#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
966#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
967#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
968#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
969#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
970#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
971#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
972/* CIK */
973#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
974#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
975#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
976/* */
977#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
978#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
979#define C_00B84C_LDS_SIZE 0xFF007FFF
980#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
981#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
982#define C_00B84C_EXCP_EN
983
984#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
985#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
986
987#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
988#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
989#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
990#define C_00B848_VGPRS 0xFFFFFFC0
991#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
992#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
993#define C_00B848_SGPRS 0xFFFFFC3F
994#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
995#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
996#define C_00B848_PRIORITY 0xFFFFF3FF
997#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
998#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
999#define C_00B848_FLOAT_MODE 0xFFF00FFF
1000#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1001#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1002#define C_00B848_PRIV 0xFFEFFFFF
1003#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1004#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1005#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1006#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1007#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1008#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1009#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1010#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1011#define C_00B848_IEEE_MODE 0xFF7FFFFF
1012#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1013#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1014#define C_00B848_WGP_MODE 0xDFFFFFFF
1015#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1016#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1017#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1018#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1019#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1020#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1021
1022
1023// Helpers for setting FLOAT_MODE
1024#define FP_ROUND_ROUND_TO_NEAREST 0
1025#define FP_ROUND_ROUND_TO_INF 1
1026#define FP_ROUND_ROUND_TO_NEGINF 2
1027#define FP_ROUND_ROUND_TO_ZERO 3
1028
1029// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1030// precision.
1031#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1032#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1033
1034#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1035#define FP_DENORM_FLUSH_OUT 1
1036#define FP_DENORM_FLUSH_IN 2
1037#define FP_DENORM_FLUSH_NONE 3
1038
1039
1040// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1041// precision.
1042#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1043#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1044
1045#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1046#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1047#define S_00B860_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1048
1049#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1050#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1051#define S_0286E8_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1052
1053#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1054#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1055#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1056#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1057#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1058#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1059#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1060#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1061
1062#define R_SPILLED_SGPRS 0x4
1063#define R_SPILLED_VGPRS 0x8
1064} // End namespace llvm
1065
1066#endif
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
@ SDWA
@ OPERAND_KIMM_LAST
Definition: SIDefines.h:216
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:183
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:207
@ OPERAND_REG_INLINE_AC_V2FP32
Definition: SIDefines.h:195
@ OPERAND_REG_INLINE_AC_V2INT32
Definition: SIDefines.h:194
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:158
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:165
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:179
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:176
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:203
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:166
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:193
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:157
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:212
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:209
@ OPERAND_KIMM_FIRST
Definition: SIDefines.h:215
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:162
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:173
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:171
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:187
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:161
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:178
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:192
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:189
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:188
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:190
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:167
@ OPERAND_SDWA_VOPC_DST
Definition: SIDefines.h:201
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:160
@ OPERAND_INPUT_MODS
Definition: SIDefines.h:198
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:206
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:175
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:210
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:172
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:177
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:168
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:191
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:174
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:159
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:180
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:164
@ OPERAND_SRC_LAST
Definition: SIDefines.h:213
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:163
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
SIRCFlags
Definition: SIDefines.h:18
@ HasSGPR
Definition: SIDefines.h:22
@ HasVGPR
Definition: SIDefines.h:20
@ HasAGPR
Definition: SIDefines.h:21