LLVM 19.0.0git
SIDefines.h
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1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInstrDesc.h"
14
15namespace llvm {
16
17// This needs to be kept in sync with the field bits in SIRegisterClass.
18enum SIRCFlags : uint8_t {
23
27
30}; // enum SIRCFlagsr
31
32namespace SIEncodingFamily {
33// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
34// and the columns of the getMCOpcodeGen table.
35enum {
36 SI = 0,
37 VI = 1,
38 SDWA = 2,
39 SDWA9 = 3,
40 GFX80 = 4,
41 GFX9 = 5,
42 GFX10 = 6,
43 SDWA10 = 7,
44 GFX90A = 8,
45 GFX940 = 9,
46 GFX11 = 10,
47 GFX12 = 11,
48};
49}
50
51namespace SIInstrFlags {
52// This needs to be kept in sync with the field bits in InstSI.
53enum : uint64_t {
54 // Low bits - basic encoding information.
55 SALU = 1 << 0,
56 VALU = 1 << 1,
57
58 // SALU instruction formats.
59 SOP1 = 1 << 2,
60 SOP2 = 1 << 3,
61 SOPC = 1 << 4,
62 SOPK = 1 << 5,
63 SOPP = 1 << 6,
64
65 // VALU instruction formats.
66 VOP1 = 1 << 7,
67 VOP2 = 1 << 8,
68 VOPC = 1 << 9,
69
70 // TODO: Should this be spilt into VOP3 a and b?
71 VOP3 = 1 << 10,
72 VOP3P = 1 << 12,
73
74 VINTRP = 1 << 13,
75 SDWA = 1 << 14,
76 DPP = 1 << 15,
77 TRANS = 1 << 16,
78
79 // Memory instruction formats.
80 MUBUF = 1 << 17,
81 MTBUF = 1 << 18,
82 SMRD = 1 << 19,
83 MIMG = 1 << 20,
84 VIMAGE = 1 << 21,
85 VSAMPLE = 1 << 22,
86 EXP = 1 << 23,
87 FLAT = 1 << 24,
88 DS = 1 << 25,
89
90 // Combined SGPR/VGPR Spill bit
91 // Logic to separate them out is done in isSGPRSpill and isVGPRSpill
92 Spill = 1 << 26,
93
94 // LDSDIR instruction format.
95 LDSDIR = 1 << 28,
96
97 // VINTERP instruction format.
98 VINTERP = 1 << 29,
99
100 // High bits - other information.
101 VM_CNT = UINT64_C(1) << 32,
102 EXP_CNT = UINT64_C(1) << 33,
103 LGKM_CNT = UINT64_C(1) << 34,
104
105 WQM = UINT64_C(1) << 35,
106 DisableWQM = UINT64_C(1) << 36,
107 Gather4 = UINT64_C(1) << 37,
108
109 // Reserved, must be 0.
110 Reserved0 = UINT64_C(1) << 38,
111
112 SCALAR_STORE = UINT64_C(1) << 39,
113 FIXED_SIZE = UINT64_C(1) << 40,
114
115 // Reserved, must be 0.
116 Reserved1 = UINT64_C(1) << 41,
117
118 VOP3_OPSEL = UINT64_C(1) << 42,
119 maybeAtomic = UINT64_C(1) << 43,
120 renamedInGFX9 = UINT64_C(1) << 44,
121
122 // Is a clamp on FP type.
123 FPClamp = UINT64_C(1) << 45,
124
125 // Is an integer clamp
126 IntClamp = UINT64_C(1) << 46,
127
128 // Clamps lo component of register.
129 ClampLo = UINT64_C(1) << 47,
130
131 // Clamps hi component of register.
132 // ClampLo and ClampHi set for packed clamp.
133 ClampHi = UINT64_C(1) << 48,
134
135 // Is a packed VOP3P instruction.
136 IsPacked = UINT64_C(1) << 49,
137
138 // Is a D16 buffer instruction.
139 D16Buf = UINT64_C(1) << 50,
140
141 // FLAT instruction accesses FLAT_GLBL segment.
142 FlatGlobal = UINT64_C(1) << 51,
143
144 // Uses floating point double precision rounding mode
145 FPDPRounding = UINT64_C(1) << 52,
146
147 // Instruction is FP atomic.
148 FPAtomic = UINT64_C(1) << 53,
149
150 // Is a MFMA instruction.
151 IsMAI = UINT64_C(1) << 54,
152
153 // Is a DOT instruction.
154 IsDOT = UINT64_C(1) << 55,
155
156 // FLAT instruction accesses FLAT_SCRATCH segment.
157 FlatScratch = UINT64_C(1) << 56,
158
159 // Atomic without return.
160 IsAtomicNoRet = UINT64_C(1) << 57,
161
162 // Atomic with return.
163 IsAtomicRet = UINT64_C(1) << 58,
164
165 // Is a WMMA instruction.
166 IsWMMA = UINT64_C(1) << 59,
167
168 // Whether tied sources will be read.
169 TiedSourceNotRead = UINT64_C(1) << 60,
170
171 // Is never uniform.
172 IsNeverUniform = UINT64_C(1) << 61,
173
174 // ds_gws_* instructions.
175 GWS = UINT64_C(1) << 62,
176
177 // Is a SWMMAC instruction.
178 IsSWMMAC = UINT64_C(1) << 63,
179};
180
181// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
182// The result is true if any of these tests are true.
183enum ClassFlags : unsigned {
184 S_NAN = 1 << 0, // Signaling NaN
185 Q_NAN = 1 << 1, // Quiet NaN
186 N_INFINITY = 1 << 2, // Negative infinity
187 N_NORMAL = 1 << 3, // Negative normal
188 N_SUBNORMAL = 1 << 4, // Negative subnormal
189 N_ZERO = 1 << 5, // Negative zero
190 P_ZERO = 1 << 6, // Positive zero
191 P_SUBNORMAL = 1 << 7, // Positive subnormal
192 P_NORMAL = 1 << 8, // Positive normal
193 P_INFINITY = 1 << 9 // Positive infinity
195}
196
197namespace AMDGPU {
198enum OperandType : unsigned {
199 /// Operands with register or 32-bit immediate
215
216 /// Operands with register or inline constant
229
230 // Operand for split barrier inline constant
232
233 /// Operand with 32-bit immediate that uses the constant bus.
236
237 /// Operands with an AccVGPR register or inline constant
249
250 // Operand for source modifiers for VOP instructions
252
253 // Operand for SDWA instructions
255
258
261
264
267
270
272
273// Should be in sync with the OperandSemantics defined in SIRegisterInfo.td
274enum OperandSemantics : unsigned {
275 INT = 0,
276 FP16 = 1,
277 BF16 = 2,
278 FP32 = 3,
279 FP64 = 4,
280};
281}
282
283// Input operand modifiers bit-masks
284// NEG and SEXT share same bit-mask because they can't be set simultaneously.
285namespace SISrcMods {
286 enum : unsigned {
287 NONE = 0,
288 NEG = 1 << 0, // Floating-point negate modifier
289 ABS = 1 << 1, // Floating-point absolute modifier
290 SEXT = 1 << 0, // Integer sign-extend modifier
291 NEG_HI = ABS, // Floating-point negate high packed component modifier.
292 OP_SEL_0 = 1 << 2,
293 OP_SEL_1 = 1 << 3,
294 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
295 };
296}
297
298namespace SIOutMods {
299 enum : unsigned {
300 NONE = 0,
301 MUL2 = 1,
302 MUL4 = 2,
303 DIV2 = 3
304 };
305}
306
307namespace AMDGPU {
308namespace VGPRIndexMode {
309
310enum Id : unsigned { // id of symbolic names
315
317 ID_MAX = ID_DST
319
320enum EncBits : unsigned {
321 OFF = 0,
327 UNDEF = 0xFFFF
329
330} // namespace VGPRIndexMode
331} // namespace AMDGPU
332
333namespace AMDGPUAsmVariants {
334 enum : unsigned {
336 VOP3 = 1,
337 SDWA = 2,
338 SDWA9 = 3,
339 DPP = 4,
340 VOP3_DPP = 5
341 };
342} // namespace AMDGPUAsmVariants
343
344namespace AMDGPU {
345namespace EncValues { // Encoding values of enum9/8/7 operands
346
347enum : unsigned {
361 VGPR_MIN = 256,
362 VGPR_MAX = 511,
363 IS_VGPR = 256, // Indicates VGPR or AGPR
364};
365
366} // namespace EncValues
367
368// Register codes as defined in the TableGen's HWEncoding field.
369namespace HWEncoding {
370enum : unsigned {
373 IS_HI = 1 << 9, // High 16-bit register.
374};
375} // namespace HWEncoding
376
377namespace CPol {
378
379enum CPol {
380 GLC = 1,
381 SLC = 2,
382 DLC = 4,
383 SCC = 16,
389
390 // Below are GFX12+ cache policy bits
391
392 // Temporal hint
393 TH = 0x7, // All TH bits
394 TH_RT = 0, // regular
395 TH_NT = 1, // non-temporal
396 TH_HT = 2, // high-temporal
397 TH_LU = 3, // last use
398 TH_RT_WB = 3, // regular (CU, SE), high-temporal with write-back (MALL)
399 TH_NT_RT = 4, // non-temporal (CU, SE), regular (MALL)
400 TH_RT_NT = 5, // regular (CU, SE), non-temporal (MALL)
401 TH_NT_HT = 6, // non-temporal (CU, SE), high-temporal (MALL)
402 TH_NT_WB = 7, // non-temporal (CU, SE), high-temporal with write-back (MALL)
403 TH_BYPASS = 3, // only to be used with scope = 3
404
405 TH_RESERVED = 7, // unused value for load insts
406
407 // Bits of TH for atomics
408 TH_ATOMIC_RETURN = GLC, // Returning vs non-returning
409 TH_ATOMIC_NT = SLC, // Non-temporal vs regular
410 TH_ATOMIC_CASCADE = 4, // Cascading vs regular
411
412 // Scope
413 SCOPE = 0x3 << 3, // All Scope bits
414 SCOPE_CU = 0 << 3,
415 SCOPE_SE = 1 << 3,
416 SCOPE_DEV = 2 << 3,
417 SCOPE_SYS = 3 << 3,
418
419 SWZ = 1 << 6, // Swizzle bit
420
422
423 // Helper bits
424 TH_TYPE_LOAD = 1 << 7, // TH_LOAD policy
425 TH_TYPE_STORE = 1 << 8, // TH_STORE policy
426 TH_TYPE_ATOMIC = 1 << 9, // TH_ATOMIC policy
427 TH_REAL_BYPASS = 1 << 10, // is TH=3 bypass policy or not
428
429 // Volatile (used to preserve/signal operation volatility for buffer
430 // operations not a real instruction bit)
431 VOLATILE = 1 << 31,
432};
433
434} // namespace CPol
435
436namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
437
438enum Id { // Message ID, width(4) [3:0].
440
441 ID_GS_PreGFX11 = 2, // replaced in GFX11
442 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
443
444 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
445 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
446
447 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
448 ID_STALL_WAVE_GEN = 5, // added in GFX9, removed in GFX12
449 ID_HALT_WAVES = 6, // added in GFX9, removed in GFX12
450 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
451 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
452 ID_GS_ALLOC_REQ = 9, // added in GFX9
453 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
454 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
456
464
466 ID_MASK_GFX11Plus_ = 0xFF
468
469enum Op { // Both GS and SYS operation IDs.
473 // Bits used for operation encoding
475 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
476 // GS operations are encoded in bits 5:4
483 // SYS operations are encoded in bits 6:4
490};
491
492enum StreamId : unsigned { // Stream ID, (2) [9:8].
501
502} // namespace SendMsg
503
504namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
505
506enum Id { // HwRegCode, (6) [5:0]
533
534 // Register numbers reused in GFX11
537
538 // Register numbers reused in GFX12+
545
546 // GFX940 specific registers
552};
553
554enum Offset : unsigned { // Offset, (5) [10:6]
556};
557
559 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
560 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
563 LOD_CLAMP_MASK = 1 << 10,
564 DEBUG_MASK = 1 << 11,
565
566 // EXCP_EN fields.
574
576 VSKIP_MASK = 1 << 28,
577 CSP_MASK = 0x7u << 29 // Bits 29..31
579
580} // namespace Hwreg
581
582namespace MTBUFFormat {
583
584enum DataFormat : int64_t {
601
604
607
609 DFMT_MASK = 0xF
611
612enum NumFormat : int64_t {
619 NFMT_RESERVED_6, // VI and GFX9
620 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
622
625
628
630 NFMT_MASK = 7
632
633enum MergedFormat : int64_t {
637
638
640
643
644enum UnifiedFormatCommon : int64_t {
645 UFMT_MAX = 127,
647 UFMT_DEFAULT = 1
649
650} // namespace MTBUFFormat
651
652namespace UfmtGFX10 {
653enum UnifiedFormat : int64_t {
655
662
670
677
681
689
697
705
712
719
726
730
738
745
748};
749
750} // namespace UfmtGFX10
751
752namespace UfmtGFX11 {
753enum UnifiedFormat : int64_t {
755
762
770
777
781
789
791
793
798
805
812
816
824
831
834};
835
836} // namespace UfmtGFX11
837
838namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
839
840enum Id : unsigned { // id of symbolic names
847
848enum EncBits : unsigned {
849
850 // swizzle mode encodings
851
854
857
858 // QUAD_PERM encodings
859
864
865 // BITMASK_PERM encodings
866
870
875
876} // namespace Swizzle
877
878namespace SDWA {
879
880enum SdwaSel : unsigned {
887 DWORD = 6,
888};
889
890enum DstUnused : unsigned {
894};
895
896enum SDWA9EncValues : unsigned {
901
909};
910
911} // namespace SDWA
912
913namespace DPP {
914
915// clang-format off
916enum DppCtrl : unsigned {
918 QUAD_PERM_ID = 0xE4, // identity permutation
920 DPP_UNUSED1 = 0x100,
921 ROW_SHL0 = 0x100,
924 DPP_UNUSED2 = 0x110,
925 ROW_SHR0 = 0x110,
928 DPP_UNUSED3 = 0x120,
929 ROW_ROR0 = 0x120,
932 WAVE_SHL1 = 0x130,
935 WAVE_ROL1 = 0x134,
938 WAVE_SHR1 = 0x138,
941 WAVE_ROR1 = 0x13C,
944 ROW_MIRROR = 0x140,
946 BCAST15 = 0x142,
947 BCAST31 = 0x143,
952 ROW_SHARE0 = 0x150,
955 ROW_XMASK0 = 0x160,
960// clang-format on
961
965 DPP8_FI_0 = 0xE9,
966 DPP8_FI_1 = 0xEA,
967};
968
969} // namespace DPP
970
971namespace Exp {
972
973enum Target : unsigned {
977 ET_NULL = 9, // Pre-GFX11
980 ET_POS4 = 16, // GFX10+
981 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
982 ET_PRIM = 20, // GFX10+
983 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
984 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
985 ET_PARAM0 = 32, // Pre-GFX11
986 ET_PARAM31 = 63, // Pre-GFX11
987
995
997};
998
999} // namespace Exp
1000
1001namespace VOP3PEncoding {
1002
1004 OP_SEL_HI_0 = UINT64_C(1) << 59,
1005 OP_SEL_HI_1 = UINT64_C(1) << 60,
1006 OP_SEL_HI_2 = UINT64_C(1) << 14,
1007};
1008
1009} // namespace VOP3PEncoding
1010
1011namespace ImplicitArg {
1012// Implicit kernel argument offset for code object version 5.
1013enum Offset_COV5 : unsigned {
1017
1020
1024};
1025
1026} // namespace ImplicitArg
1027
1028namespace VirtRegFlag {
1029// Virtual register flags used for various target specific handlings during
1030// codegen.
1031enum Register_Flag : uint8_t {
1032 // Register operand in a whole-wave mode operation.
1033 WWM_REG = 1 << 0,
1034};
1035
1036} // namespace VirtRegFlag
1037
1038} // namespace AMDGPU
1039
1040namespace AMDGPU {
1041namespace Barrier {
1042enum Type { TRAP = -2, WORKGROUP = -1 };
1043} // namespace Barrier
1044} // namespace AMDGPU
1045
1046// clang-format off
1047
1048#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
1049#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
1050#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
1051#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
1052#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1053#define C_00B028_MEM_ORDERED 0xFDFFFFFF
1054
1055#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
1056#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
1057#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
1058#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
1059#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
1060#define C_00B128_MEM_ORDERED 0xF7FFFFFF
1061
1062#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
1063#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
1064#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
1065#define C_00B228_WGP_MODE 0xF7FFFFFF
1066#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
1067#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
1068#define C_00B228_MEM_ORDERED 0xFDFFFFFF
1069
1070#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
1071#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
1072#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
1073#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
1074#define C_00B428_WGP_MODE 0xFBFFFFFF
1075#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
1076#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
1077#define C_00B428_MEM_ORDERED 0xFEFFFFFF
1078
1079#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
1080
1081#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1082#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1083#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1084#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1085#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1086#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1087#define C_00B84C_USER_SGPR 0xFFFFFFC1
1088#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1089#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1090#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1091#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1092#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1093#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1094#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1095#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1096#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1097#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1098#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1099#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1100#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1101#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1102#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1103#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1104#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1105#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1106/* CIK */
1107#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1108#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1109#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1110/* */
1111#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1112#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1113#define C_00B84C_LDS_SIZE 0xFF007FFF
1114#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1115#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1116#define C_00B84C_EXCP_EN
1117
1118#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1119#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1120
1121#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1122#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1123#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1124#define C_00B848_VGPRS 0xFFFFFFC0
1125#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1126#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1127#define C_00B848_SGPRS 0xFFFFFC3F
1128#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1129#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1130#define C_00B848_PRIORITY 0xFFFFF3FF
1131#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1132#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1133#define C_00B848_FLOAT_MODE 0xFFF00FFF
1134#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1135#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1136#define C_00B848_PRIV 0xFFEFFFFF
1137#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1138#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1139#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1140#define S_00B848_RR_WG_MODE(x) (((x) & 0x1) << 21)
1141#define G_00B848_RR_WG_MODE(x) (((x) >> 21) & 0x1)
1142#define C_00B848_RR_WG_MODE 0xFFDFFFFF
1143#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1144#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1145#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1146#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1147#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1148#define C_00B848_IEEE_MODE 0xFF7FFFFF
1149#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1150#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1151#define C_00B848_WGP_MODE 0xDFFFFFFF
1152#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1153#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1154#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1155#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1156#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1157#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1158
1159// Helpers for setting FLOAT_MODE
1160#define FP_ROUND_ROUND_TO_NEAREST 0
1161#define FP_ROUND_ROUND_TO_INF 1
1162#define FP_ROUND_ROUND_TO_NEGINF 2
1163#define FP_ROUND_ROUND_TO_ZERO 3
1164
1165// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1166// precision.
1167#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1168#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1169
1170#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1171#define FP_DENORM_FLUSH_OUT 1
1172#define FP_DENORM_FLUSH_IN 2
1173#define FP_DENORM_FLUSH_NONE 3
1174
1175
1176// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1177// precision.
1178#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1179#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1180
1181#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1182#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1183#define S_00B860_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1184#define S_00B860_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1185
1186#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1187#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1188#define S_0286E8_WAVESIZE_GFX11(x) (((x) & 0x7FFF) << 12)
1189#define S_0286E8_WAVESIZE_GFX12Plus(x) (((x) & 0x3FFFF) << 12)
1190
1191#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1192#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1193#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1194#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1195#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1196#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1197#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1198#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1199
1200#define R_SPILLED_SGPRS 0x4
1201#define R_SPILLED_VGPRS 0x8
1202
1203// clang-format on
1204
1205} // End namespace llvm
1206
1207#endif
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
@ OPERAND_KIMM_LAST
Definition: SIDefines.h:269
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:234
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:260
@ OPERAND_REG_INLINE_AC_V2FP32
Definition: SIDefines.h:248
@ OPERAND_REG_INLINE_AC_V2INT32
Definition: SIDefines.h:247
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:201
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:211
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:227
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:223
@ OPERAND_REG_INLINE_C_BF16
Definition: SIDefines.h:220
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:256
@ OPERAND_REG_INLINE_C_V2BF16
Definition: SIDefines.h:225
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:212
@ OPERAND_REG_IMM_BF16
Definition: SIDefines.h:205
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:246
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:200
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:265
@ OPERAND_REG_IMM_V2BF16
Definition: SIDefines.h:210
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:262
@ OPERAND_KIMM_FIRST
Definition: SIDefines.h:268
@ OPERAND_REG_IMM_BF16_DEFERRED
Definition: SIDefines.h:207
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:206
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:219
@ OPERAND_REG_INLINE_AC_BF16
Definition: SIDefines.h:240
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:217
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:238
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:226
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:244
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:241
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:239
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:242
@ OPERAND_REG_INLINE_AC_V2BF16
Definition: SIDefines.h:245
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:213
@ OPERAND_SDWA_VOPC_DST
Definition: SIDefines.h:254
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:203
@ OPERAND_INPUT_MODS
Definition: SIDefines.h:251
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:259
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:263
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:257
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:218
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:224
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:214
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:243
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:221
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:202
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:228
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
Definition: SIDefines.h:231
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:209
@ OPERAND_SRC_LAST
Definition: SIDefines.h:266
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:208
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
SIRCFlags
Definition: SIDefines.h:18
@ HasSGPR
Definition: SIDefines.h:26
@ HasAGPRBit
Definition: SIDefines.h:21
@ HasSGPRbit
Definition: SIDefines.h:22
@ RegTupleAlignUnitsWidth
Definition: SIDefines.h:19
@ RegTupleAlignUnitsMask
Definition: SIDefines.h:28
@ HasVGPRBit
Definition: SIDefines.h:20
@ HasVGPR
Definition: SIDefines.h:24
@ RegKindMask
Definition: SIDefines.h:29
@ HasAGPR
Definition: SIDefines.h:25