LLVM 17.0.0git
SIDefines.h
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1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInstrDesc.h"
14
15namespace llvm {
16
17// This needs to be kept in sync with the field bits in SIRegisterClass.
18enum SIRCFlags : uint8_t {
23
27
30}; // enum SIRCFlagsr
31
32namespace SIInstrFlags {
33// This needs to be kept in sync with the field bits in InstSI.
34enum : uint64_t {
35 // Low bits - basic encoding information.
36 SALU = 1 << 0,
37 VALU = 1 << 1,
38
39 // SALU instruction formats.
40 SOP1 = 1 << 2,
41 SOP2 = 1 << 3,
42 SOPC = 1 << 4,
43 SOPK = 1 << 5,
44 SOPP = 1 << 6,
45
46 // VALU instruction formats.
47 VOP1 = 1 << 7,
48 VOP2 = 1 << 8,
49 VOPC = 1 << 9,
50
51 // TODO: Should this be spilt into VOP3 a and b?
52 VOP3 = 1 << 10,
53 VOP3P = 1 << 12,
54
55 VINTRP = 1 << 13,
56 SDWA = 1 << 14,
57 DPP = 1 << 15,
58 TRANS = 1 << 16,
59
60 // Memory instruction formats.
61 MUBUF = 1 << 17,
62 MTBUF = 1 << 18,
63 SMRD = 1 << 19,
64 MIMG = 1 << 20,
65 EXP = 1 << 21,
66 FLAT = 1 << 22,
67 DS = 1 << 23,
68
69 // Pseudo instruction formats.
70 VGPRSpill = 1 << 24,
71 SGPRSpill = 1 << 25,
72
73 // LDSDIR instruction format.
74 LDSDIR = 1 << 26,
75
76 // VINTERP instruction format.
77 VINTERP = 1 << 27,
78
79 // High bits - other information.
80 VM_CNT = UINT64_C(1) << 32,
81 EXP_CNT = UINT64_C(1) << 33,
82 LGKM_CNT = UINT64_C(1) << 34,
83
84 WQM = UINT64_C(1) << 35,
85 DisableWQM = UINT64_C(1) << 36,
86 Gather4 = UINT64_C(1) << 37,
87 SOPK_ZEXT = UINT64_C(1) << 38,
88 SCALAR_STORE = UINT64_C(1) << 39,
89 FIXED_SIZE = UINT64_C(1) << 40,
90 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
91 VOP3_OPSEL = UINT64_C(1) << 42,
92 maybeAtomic = UINT64_C(1) << 43,
93 renamedInGFX9 = UINT64_C(1) << 44,
94
95 // Is a clamp on FP type.
96 FPClamp = UINT64_C(1) << 45,
97
98 // Is an integer clamp
99 IntClamp = UINT64_C(1) << 46,
100
101 // Clamps lo component of register.
102 ClampLo = UINT64_C(1) << 47,
103
104 // Clamps hi component of register.
105 // ClampLo and ClampHi set for packed clamp.
106 ClampHi = UINT64_C(1) << 48,
107
108 // Is a packed VOP3P instruction.
109 IsPacked = UINT64_C(1) << 49,
110
111 // Is a D16 buffer instruction.
112 D16Buf = UINT64_C(1) << 50,
113
114 // FLAT instruction accesses FLAT_GLBL segment.
115 FlatGlobal = UINT64_C(1) << 51,
116
117 // Uses floating point double precision rounding mode
118 FPDPRounding = UINT64_C(1) << 52,
119
120 // Instruction is FP atomic.
121 FPAtomic = UINT64_C(1) << 53,
122
123 // Is a MFMA instruction.
124 IsMAI = UINT64_C(1) << 54,
125
126 // Is a DOT instruction.
127 IsDOT = UINT64_C(1) << 55,
128
129 // FLAT instruction accesses FLAT_SCRATCH segment.
130 FlatScratch = UINT64_C(1) << 56,
131
132 // Atomic without return.
133 IsAtomicNoRet = UINT64_C(1) << 57,
134
135 // Atomic with return.
136 IsAtomicRet = UINT64_C(1) << 58,
137
138 // Is a WMMA instruction.
139 IsWMMA = UINT64_C(1) << 59,
140
141 // Whether tied sources will be read.
142 TiedSourceNotRead = UINT64_C(1) << 60,
143
144 // Is never uniform.
145 IsNeverUniform = UINT64_C(1) << 61,
146};
147
148// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
149// The result is true if any of these tests are true.
150enum ClassFlags : unsigned {
151 S_NAN = 1 << 0, // Signaling NaN
152 Q_NAN = 1 << 1, // Quiet NaN
153 N_INFINITY = 1 << 2, // Negative infinity
154 N_NORMAL = 1 << 3, // Negative normal
155 N_SUBNORMAL = 1 << 4, // Negative subnormal
156 N_ZERO = 1 << 5, // Negative zero
157 P_ZERO = 1 << 6, // Positive zero
158 P_SUBNORMAL = 1 << 7, // Positive subnormal
159 P_NORMAL = 1 << 8, // Positive normal
160 P_INFINITY = 1 << 9 // Positive infinity
162}
163
164namespace AMDGPU {
165enum OperandType : unsigned {
166 /// Operands with register or 32-bit immediate
179
180 /// Operands with register or inline constant
191
192 /// Operand with 32-bit immediate that uses the constant bus.
195
196 /// Operands with an AccVGPR register or inline constant
206
207 // Operand for source modifiers for VOP instructions
209
210 // Operand for SDWA instructions
212
215
218
221
224
227
229}
230
231// Input operand modifiers bit-masks
232// NEG and SEXT share same bit-mask because they can't be set simultaneously.
233namespace SISrcMods {
234 enum : unsigned {
235 NEG = 1 << 0, // Floating-point negate modifier
236 ABS = 1 << 1, // Floating-point absolute modifier
237 SEXT = 1 << 0, // Integer sign-extend modifier
238 NEG_HI = ABS, // Floating-point negate high packed component modifier.
239 OP_SEL_0 = 1 << 2,
240 OP_SEL_1 = 1 << 3,
241 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
242 };
243}
244
245namespace SIOutMods {
246 enum : unsigned {
247 NONE = 0,
248 MUL2 = 1,
249 MUL4 = 2,
250 DIV2 = 3
251 };
252}
253
254namespace AMDGPU {
255namespace VGPRIndexMode {
256
257enum Id : unsigned { // id of symbolic names
262
264 ID_MAX = ID_DST
266
267enum EncBits : unsigned {
268 OFF = 0,
274 UNDEF = 0xFFFF
276
277} // namespace VGPRIndexMode
278} // namespace AMDGPU
279
280namespace AMDGPUAsmVariants {
281 enum : unsigned {
283 VOP3 = 1,
284 SDWA = 2,
285 SDWA9 = 3,
286 DPP = 4,
287 VOP3_DPP = 5
288 };
289} // namespace AMDGPUAsmVariants
290
291namespace AMDGPU {
292namespace EncValues { // Encoding values of enum9/8/7 operands
293
294enum : unsigned {
308 VGPR_MIN = 256,
309 VGPR_MAX = 511,
310 IS_VGPR = 256 // Indicates VGPR or AGPR
312
313} // namespace EncValues
314} // namespace AMDGPU
315
316namespace AMDGPU {
317namespace CPol {
318
319enum CPol {
320 GLC = 1,
321 SLC = 2,
322 DLC = 4,
323 SCC = 16,
327 ALL = GLC | SLC | DLC | SCC
329
330} // namespace CPol
331
332namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
333
334enum Id { // Message ID, width(4) [3:0].
336
337 ID_GS_PreGFX11 = 2, // replaced in GFX11
338 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
339
340 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
341 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
342
343 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
344 ID_STALL_WAVE_GEN = 5, // added in GFX9
345 ID_HALT_WAVES = 6, // added in GFX9
346 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
347 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
348 ID_GS_ALLOC_REQ = 9, // added in GFX9
349 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
350 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
352
359
361 ID_MASK_GFX11Plus_ = 0xFF
363
364enum Op { // Both GS and SYS operation IDs.
368 // Bits used for operation encoding
370 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
371 // GS operations are encoded in bits 5:4
378 // SYS operations are encoded in bits 6:4
385};
386
387enum StreamId : unsigned { // Stream ID, (2) [9:8].
396
397} // namespace SendMsg
398
399namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
400
401enum Id { // HwRegCode, (6) [5:0]
422
423 // Register numbers reused in GFX11+
426
427 // GFX940 specific registers
433
436 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
438
439enum Offset : unsigned { // Offset, (5) [10:6]
444
446};
447
448enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
453};
454
455// Some values from WidthMinusOne mapped into Width domain.
456enum Width : unsigned {
458};
459
461 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
462 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
465 LOD_CLAMP_MASK = 1 << 10,
466 DEBUG_MASK = 1 << 11,
467
468 // EXCP_EN fields.
476
478 VSKIP_MASK = 1 << 28,
479 CSP_MASK = 0x7u << 29 // Bits 29..31
481
482} // namespace Hwreg
483
484namespace MTBUFFormat {
485
486enum DataFormat : int64_t {
503
506
509
511 DFMT_MASK = 0xF
513
514enum NumFormat : int64_t {
521 NFMT_RESERVED_6, // VI and GFX9
522 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
524
527
530
532 NFMT_MASK = 7
534
535enum MergedFormat : int64_t {
539
540
542
545
546enum UnifiedFormatCommon : int64_t {
547 UFMT_MAX = 127,
549 UFMT_DEFAULT = 1
551
552} // namespace MTBUFFormat
553
554namespace UfmtGFX10 {
555enum UnifiedFormat : int64_t {
557
564
572
579
583
591
599
607
614
621
628
632
640
647
650};
651
652} // namespace UfmtGFX10
653
654namespace UfmtGFX11 {
655enum UnifiedFormat : int64_t {
657
664
672
679
683
691
693
695
700
707
714
718
726
733
736};
737
738} // namespace UfmtGFX11
739
740namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
741
742enum Id : unsigned { // id of symbolic names
749
750enum EncBits : unsigned {
751
752 // swizzle mode encodings
753
756
759
760 // QUAD_PERM encodings
761
766
767 // BITMASK_PERM encodings
768
772
777
778} // namespace Swizzle
779
780namespace SDWA {
781
782enum SdwaSel : unsigned {
789 DWORD = 6,
790};
791
792enum DstUnused : unsigned {
796};
797
798enum SDWA9EncValues : unsigned {
803
811};
812
813} // namespace SDWA
814
815namespace DPP {
816
817// clang-format off
818enum DppCtrl : unsigned {
820 QUAD_PERM_ID = 0xE4, // identity permutation
822 DPP_UNUSED1 = 0x100,
823 ROW_SHL0 = 0x100,
826 DPP_UNUSED2 = 0x110,
827 ROW_SHR0 = 0x110,
830 DPP_UNUSED3 = 0x120,
831 ROW_ROR0 = 0x120,
834 WAVE_SHL1 = 0x130,
837 WAVE_ROL1 = 0x134,
840 WAVE_SHR1 = 0x138,
843 WAVE_ROR1 = 0x13C,
846 ROW_MIRROR = 0x140,
848 BCAST15 = 0x142,
849 BCAST31 = 0x143,
854 ROW_SHARE0 = 0x150,
857 ROW_XMASK0 = 0x160,
862// clang-format on
863
867 DPP8_FI_0 = 0xE9,
868 DPP8_FI_1 = 0xEA,
869};
870
871} // namespace DPP
872
873namespace Exp {
874
875enum Target : unsigned {
879 ET_NULL = 9, // Pre-GFX11
882 ET_POS4 = 16, // GFX10+
883 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
884 ET_PRIM = 20, // GFX10+
885 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
886 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
887 ET_PARAM0 = 32, // Pre-GFX11
888 ET_PARAM31 = 63, // Pre-GFX11
889
897
899};
900
901} // namespace Exp
902
903namespace VOP3PEncoding {
904
906 OP_SEL_HI_0 = UINT64_C(1) << 59,
907 OP_SEL_HI_1 = UINT64_C(1) << 60,
908 OP_SEL_HI_2 = UINT64_C(1) << 14,
909};
910
911} // namespace VOP3PEncoding
912
913namespace ImplicitArg {
914// Implicit kernel argument offset for code object version 5.
915enum Offset_COV5 : unsigned {
919
922
926};
927
928} // namespace ImplicitArg
929} // namespace AMDGPU
930
931#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
932#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
933#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
934#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
935#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
936#define C_00B028_MEM_ORDERED 0xFDFFFFFF
937
938#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
939#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
940#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
941#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
942#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
943#define C_00B128_MEM_ORDERED 0xF7FFFFFF
944
945#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
946#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
947#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
948#define C_00B228_WGP_MODE 0xF7FFFFFF
949#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
950#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
951#define C_00B228_MEM_ORDERED 0xFDFFFFFF
952
953#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
954#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
955#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
956#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
957#define C_00B428_WGP_MODE 0xFBFFFFFF
958#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
959#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
960#define C_00B428_MEM_ORDERED 0xFEFFFFFF
961
962#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
963
964#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
965#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
966#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
967#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
968#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
969#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
970#define C_00B84C_USER_SGPR 0xFFFFFFC1
971#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
972#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
973#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
974#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
975#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
976#define C_00B84C_TGID_X_EN 0xFFFFFF7F
977#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
978#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
979#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
980#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
981#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
982#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
983#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
984#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
985#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
986#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
987#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
988#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
989/* CIK */
990#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
991#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
992#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
993/* */
994#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
995#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
996#define C_00B84C_LDS_SIZE 0xFF007FFF
997#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
998#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
999#define C_00B84C_EXCP_EN
1000
1001#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1002#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1003
1004#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1005#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1006#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1007#define C_00B848_VGPRS 0xFFFFFFC0
1008#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1009#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1010#define C_00B848_SGPRS 0xFFFFFC3F
1011#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1012#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1013#define C_00B848_PRIORITY 0xFFFFF3FF
1014#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1015#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1016#define C_00B848_FLOAT_MODE 0xFFF00FFF
1017#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1018#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1019#define C_00B848_PRIV 0xFFEFFFFF
1020#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1021#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1022#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1023#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1024#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1025#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1026#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1027#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1028#define C_00B848_IEEE_MODE 0xFF7FFFFF
1029#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1030#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1031#define C_00B848_WGP_MODE 0xDFFFFFFF
1032#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1033#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1034#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1035#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1036#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1037#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1038
1039
1040// Helpers for setting FLOAT_MODE
1041#define FP_ROUND_ROUND_TO_NEAREST 0
1042#define FP_ROUND_ROUND_TO_INF 1
1043#define FP_ROUND_ROUND_TO_NEGINF 2
1044#define FP_ROUND_ROUND_TO_ZERO 3
1045
1046// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1047// precision.
1048#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1049#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1050
1051#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1052#define FP_DENORM_FLUSH_OUT 1
1053#define FP_DENORM_FLUSH_IN 2
1054#define FP_DENORM_FLUSH_NONE 3
1055
1056
1057// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1058// precision.
1059#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1060#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1061
1062#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1063#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1064#define S_00B860_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1065
1066#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1067#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1068#define S_0286E8_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1069
1070#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1071#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1072#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1073#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1074#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1075#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1076#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1077#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1078
1079#define R_SPILLED_SGPRS 0x4
1080#define R_SPILLED_VGPRS 0x8
1081} // End namespace llvm
1082
1083#endif
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
@ SDWA
@ OPERAND_KIMM_LAST
Definition: SIDefines.h:226
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:193
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:217
@ OPERAND_REG_INLINE_AC_V2FP32
Definition: SIDefines.h:205
@ OPERAND_REG_INLINE_AC_V2INT32
Definition: SIDefines.h:204
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:168
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:175
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:189
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:186
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:213
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:176
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:203
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:167
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:219
@ OPERAND_KIMM_FIRST
Definition: SIDefines.h:225
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:172
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:183
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:181
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:197
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:171
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:188
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:202
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:199
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:198
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:200
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:177
@ OPERAND_SDWA_VOPC_DST
Definition: SIDefines.h:211
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:170
@ OPERAND_INPUT_MODS
Definition: SIDefines.h:208
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:216
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:185
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:220
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:214
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:182
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:187
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:178
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:201
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:184
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:169
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:190
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:174
@ OPERAND_SRC_LAST
Definition: SIDefines.h:223
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:173
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
SIRCFlags
Definition: SIDefines.h:18
@ HasSGPR
Definition: SIDefines.h:26
@ HasAGPRBit
Definition: SIDefines.h:21
@ HasSGPRbit
Definition: SIDefines.h:22
@ RegTupleAlignUnitsWidth
Definition: SIDefines.h:19
@ RegTupleAlignUnitsMask
Definition: SIDefines.h:28
@ HasVGPRBit
Definition: SIDefines.h:20
@ HasVGPR
Definition: SIDefines.h:24
@ RegKindMask
Definition: SIDefines.h:29
@ HasAGPR
Definition: SIDefines.h:25