LLVM 18.0.0git
SIDefines.h
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1//===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
12
13#include "llvm/MC/MCInstrDesc.h"
14
15namespace llvm {
16
17// This needs to be kept in sync with the field bits in SIRegisterClass.
18enum SIRCFlags : uint8_t {
23
27
30}; // enum SIRCFlagsr
31
32namespace SIEncodingFamily {
33// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
34// and the columns of the getMCOpcodeGen table.
35enum {
36 SI = 0,
37 VI = 1,
38 SDWA = 2,
39 SDWA9 = 3,
40 GFX80 = 4,
41 GFX9 = 5,
42 GFX10 = 6,
43 SDWA10 = 7,
44 GFX90A = 8,
45 GFX940 = 9,
46 GFX11 = 10,
47};
48}
49
50namespace SIInstrFlags {
51// This needs to be kept in sync with the field bits in InstSI.
52enum : uint64_t {
53 // Low bits - basic encoding information.
54 SALU = 1 << 0,
55 VALU = 1 << 1,
56
57 // SALU instruction formats.
58 SOP1 = 1 << 2,
59 SOP2 = 1 << 3,
60 SOPC = 1 << 4,
61 SOPK = 1 << 5,
62 SOPP = 1 << 6,
63
64 // VALU instruction formats.
65 VOP1 = 1 << 7,
66 VOP2 = 1 << 8,
67 VOPC = 1 << 9,
68
69 // TODO: Should this be spilt into VOP3 a and b?
70 VOP3 = 1 << 10,
71 VOP3P = 1 << 12,
72
73 VINTRP = 1 << 13,
74 SDWA = 1 << 14,
75 DPP = 1 << 15,
76 TRANS = 1 << 16,
77
78 // Memory instruction formats.
79 MUBUF = 1 << 17,
80 MTBUF = 1 << 18,
81 SMRD = 1 << 19,
82 MIMG = 1 << 20,
83 EXP = 1 << 21,
84 FLAT = 1 << 22,
85 DS = 1 << 23,
86
87 // Pseudo instruction formats.
88 VGPRSpill = 1 << 24,
89 SGPRSpill = 1 << 25,
90
91 // LDSDIR instruction format.
92 LDSDIR = 1 << 26,
93
94 // VINTERP instruction format.
95 VINTERP = 1 << 27,
96
97 // High bits - other information.
98 VM_CNT = UINT64_C(1) << 32,
99 EXP_CNT = UINT64_C(1) << 33,
100 LGKM_CNT = UINT64_C(1) << 34,
101
102 WQM = UINT64_C(1) << 35,
103 DisableWQM = UINT64_C(1) << 36,
104 Gather4 = UINT64_C(1) << 37,
105 SOPK_ZEXT = UINT64_C(1) << 38,
106 SCALAR_STORE = UINT64_C(1) << 39,
107 FIXED_SIZE = UINT64_C(1) << 40,
108 VOPAsmPrefer32Bit = UINT64_C(1) << 41,
109 VOP3_OPSEL = UINT64_C(1) << 42,
110 maybeAtomic = UINT64_C(1) << 43,
111 renamedInGFX9 = UINT64_C(1) << 44,
112
113 // Is a clamp on FP type.
114 FPClamp = UINT64_C(1) << 45,
115
116 // Is an integer clamp
117 IntClamp = UINT64_C(1) << 46,
118
119 // Clamps lo component of register.
120 ClampLo = UINT64_C(1) << 47,
121
122 // Clamps hi component of register.
123 // ClampLo and ClampHi set for packed clamp.
124 ClampHi = UINT64_C(1) << 48,
125
126 // Is a packed VOP3P instruction.
127 IsPacked = UINT64_C(1) << 49,
128
129 // Is a D16 buffer instruction.
130 D16Buf = UINT64_C(1) << 50,
131
132 // FLAT instruction accesses FLAT_GLBL segment.
133 FlatGlobal = UINT64_C(1) << 51,
134
135 // Uses floating point double precision rounding mode
136 FPDPRounding = UINT64_C(1) << 52,
137
138 // Instruction is FP atomic.
139 FPAtomic = UINT64_C(1) << 53,
140
141 // Is a MFMA instruction.
142 IsMAI = UINT64_C(1) << 54,
143
144 // Is a DOT instruction.
145 IsDOT = UINT64_C(1) << 55,
146
147 // FLAT instruction accesses FLAT_SCRATCH segment.
148 FlatScratch = UINT64_C(1) << 56,
149
150 // Atomic without return.
151 IsAtomicNoRet = UINT64_C(1) << 57,
152
153 // Atomic with return.
154 IsAtomicRet = UINT64_C(1) << 58,
155
156 // Is a WMMA instruction.
157 IsWMMA = UINT64_C(1) << 59,
158
159 // Whether tied sources will be read.
160 TiedSourceNotRead = UINT64_C(1) << 60,
161
162 // Is never uniform.
163 IsNeverUniform = UINT64_C(1) << 61,
164
165 // ds_gws_* instructions.
166 GWS = UINT64_C(1) << 62,
167};
168
169// v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
170// The result is true if any of these tests are true.
171enum ClassFlags : unsigned {
172 S_NAN = 1 << 0, // Signaling NaN
173 Q_NAN = 1 << 1, // Quiet NaN
174 N_INFINITY = 1 << 2, // Negative infinity
175 N_NORMAL = 1 << 3, // Negative normal
176 N_SUBNORMAL = 1 << 4, // Negative subnormal
177 N_ZERO = 1 << 5, // Negative zero
178 P_ZERO = 1 << 6, // Positive zero
179 P_SUBNORMAL = 1 << 7, // Positive subnormal
180 P_NORMAL = 1 << 8, // Positive normal
181 P_INFINITY = 1 << 9 // Positive infinity
183}
184
185namespace AMDGPU {
186enum OperandType : unsigned {
187 /// Operands with register or 32-bit immediate
200
201 /// Operands with register or inline constant
212
213 /// Operand with 32-bit immediate that uses the constant bus.
216
217 /// Operands with an AccVGPR register or inline constant
227
228 // Operand for source modifiers for VOP instructions
230
231 // Operand for SDWA instructions
233
236
239
242
245
248
250}
251
252// Input operand modifiers bit-masks
253// NEG and SEXT share same bit-mask because they can't be set simultaneously.
254namespace SISrcMods {
255 enum : unsigned {
256 NONE = 0,
257 NEG = 1 << 0, // Floating-point negate modifier
258 ABS = 1 << 1, // Floating-point absolute modifier
259 SEXT = 1 << 0, // Integer sign-extend modifier
260 NEG_HI = ABS, // Floating-point negate high packed component modifier.
261 OP_SEL_0 = 1 << 2,
262 OP_SEL_1 = 1 << 3,
263 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1)
264 };
265}
266
267namespace SIOutMods {
268 enum : unsigned {
269 NONE = 0,
270 MUL2 = 1,
271 MUL4 = 2,
272 DIV2 = 3
273 };
274}
275
276namespace AMDGPU {
277namespace VGPRIndexMode {
278
279enum Id : unsigned { // id of symbolic names
284
286 ID_MAX = ID_DST
288
289enum EncBits : unsigned {
290 OFF = 0,
296 UNDEF = 0xFFFF
298
299} // namespace VGPRIndexMode
300} // namespace AMDGPU
301
302namespace AMDGPUAsmVariants {
303 enum : unsigned {
305 VOP3 = 1,
306 SDWA = 2,
307 SDWA9 = 3,
308 DPP = 4,
309 VOP3_DPP = 5
310 };
311} // namespace AMDGPUAsmVariants
312
313namespace AMDGPU {
314namespace EncValues { // Encoding values of enum9/8/7 operands
315
316enum : unsigned {
331 VGPR_MIN = 256,
332 VGPR_MAX = 511,
333 IS_VGPR = 256, // Indicates VGPR or AGPR
334 IS_HI = 512, // High 16-bit register.
335};
336
337} // namespace EncValues
338} // namespace AMDGPU
339
340namespace AMDGPU {
341namespace CPol {
342
343enum CPol {
344 GLC = 1,
345 SLC = 2,
346 DLC = 4,
347 SCC = 16,
351 ALL = GLC | SLC | DLC | SCC
353
354} // namespace CPol
355
356namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns.
357
358enum Id { // Message ID, width(4) [3:0].
360
361 ID_GS_PreGFX11 = 2, // replaced in GFX11
362 ID_GS_DONE_PreGFX11 = 3, // replaced in GFX11
363
364 ID_HS_TESSFACTOR_GFX11Plus = 2, // reused in GFX11
365 ID_DEALLOC_VGPRS_GFX11Plus = 3, // reused in GFX11
366
367 ID_SAVEWAVE = 4, // added in GFX8, removed in GFX11
368 ID_STALL_WAVE_GEN = 5, // added in GFX9
369 ID_HALT_WAVES = 6, // added in GFX9
370 ID_ORDERED_PS_DONE = 7, // added in GFX9, removed in GFX11
371 ID_EARLY_PRIM_DEALLOC = 8, // added in GFX9, removed in GFX10
372 ID_GS_ALLOC_REQ = 9, // added in GFX9
373 ID_GET_DOORBELL = 10, // added in GFX9, removed in GFX11
374 ID_GET_DDID = 11, // added in GFX10, removed in GFX11
376
383
385 ID_MASK_GFX11Plus_ = 0xFF
387
388enum Op { // Both GS and SYS operation IDs.
392 // Bits used for operation encoding
394 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_),
395 // GS operations are encoded in bits 5:4
402 // SYS operations are encoded in bits 6:4
409};
410
411enum StreamId : unsigned { // Stream ID, (2) [9:8].
420
421} // namespace SendMsg
422
423namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns.
424
425enum Id { // HwRegCode, (6) [5:0]
446
447 // Register numbers reused in GFX11+
450
451 // GFX940 specific registers
457
460 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
462
463enum Offset : unsigned { // Offset, (5) [10:6]
468
470};
471
472enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11]
477};
478
479// Some values from WidthMinusOne mapped into Width domain.
480enum Width : unsigned {
482};
483
485 FP_ROUND_MASK = 0xf << 0, // Bits 0..3
486 FP_DENORM_MASK = 0xf << 4, // Bits 4..7
489 LOD_CLAMP_MASK = 1 << 10,
490 DEBUG_MASK = 1 << 11,
491
492 // EXCP_EN fields.
500
502 VSKIP_MASK = 1 << 28,
503 CSP_MASK = 0x7u << 29 // Bits 29..31
505
506} // namespace Hwreg
507
508namespace MTBUFFormat {
509
510enum DataFormat : int64_t {
527
530
533
535 DFMT_MASK = 0xF
537
538enum NumFormat : int64_t {
545 NFMT_RESERVED_6, // VI and GFX9
546 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only
548
551
554
556 NFMT_MASK = 7
558
559enum MergedFormat : int64_t {
563
564
566
569
570enum UnifiedFormatCommon : int64_t {
571 UFMT_MAX = 127,
573 UFMT_DEFAULT = 1
575
576} // namespace MTBUFFormat
577
578namespace UfmtGFX10 {
579enum UnifiedFormat : int64_t {
581
588
596
603
607
615
623
631
638
645
652
656
664
671
674};
675
676} // namespace UfmtGFX10
677
678namespace UfmtGFX11 {
679enum UnifiedFormat : int64_t {
681
688
696
703
707
715
717
719
724
731
738
742
750
757
760};
761
762} // namespace UfmtGFX11
763
764namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32.
765
766enum Id : unsigned { // id of symbolic names
773
774enum EncBits : unsigned {
775
776 // swizzle mode encodings
777
780
783
784 // QUAD_PERM encodings
785
790
791 // BITMASK_PERM encodings
792
796
801
802} // namespace Swizzle
803
804namespace SDWA {
805
806enum SdwaSel : unsigned {
813 DWORD = 6,
814};
815
816enum DstUnused : unsigned {
820};
821
822enum SDWA9EncValues : unsigned {
827
835};
836
837} // namespace SDWA
838
839namespace DPP {
840
841// clang-format off
842enum DppCtrl : unsigned {
844 QUAD_PERM_ID = 0xE4, // identity permutation
846 DPP_UNUSED1 = 0x100,
847 ROW_SHL0 = 0x100,
850 DPP_UNUSED2 = 0x110,
851 ROW_SHR0 = 0x110,
854 DPP_UNUSED3 = 0x120,
855 ROW_ROR0 = 0x120,
858 WAVE_SHL1 = 0x130,
861 WAVE_ROL1 = 0x134,
864 WAVE_SHR1 = 0x138,
867 WAVE_ROR1 = 0x13C,
870 ROW_MIRROR = 0x140,
872 BCAST15 = 0x142,
873 BCAST31 = 0x143,
878 ROW_SHARE0 = 0x150,
881 ROW_XMASK0 = 0x160,
886// clang-format on
887
891 DPP8_FI_0 = 0xE9,
892 DPP8_FI_1 = 0xEA,
893};
894
895} // namespace DPP
896
897namespace Exp {
898
899enum Target : unsigned {
903 ET_NULL = 9, // Pre-GFX11
906 ET_POS4 = 16, // GFX10+
907 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget
908 ET_PRIM = 20, // GFX10+
909 ET_DUAL_SRC_BLEND0 = 21, // GFX11+
910 ET_DUAL_SRC_BLEND1 = 22, // GFX11+
911 ET_PARAM0 = 32, // Pre-GFX11
912 ET_PARAM31 = 63, // Pre-GFX11
913
921
923};
924
925} // namespace Exp
926
927namespace VOP3PEncoding {
928
930 OP_SEL_HI_0 = UINT64_C(1) << 59,
931 OP_SEL_HI_1 = UINT64_C(1) << 60,
932 OP_SEL_HI_2 = UINT64_C(1) << 14,
933};
934
935} // namespace VOP3PEncoding
936
937namespace ImplicitArg {
938// Implicit kernel argument offset for code object version 5.
939enum Offset_COV5 : unsigned {
943
946
950};
951
952} // namespace ImplicitArg
953
954namespace VirtRegFlag {
955// Virtual register flags used for various target specific handlings during
956// codegen.
957enum Register_Flag : uint8_t {
958 // Register operand in a whole-wave mode operation.
959 WWM_REG = 1 << 0,
960};
961
962} // namespace VirtRegFlag
963
964} // namespace AMDGPU
965
966#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
967#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
968#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
969#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
970#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
971#define C_00B028_MEM_ORDERED 0xFDFFFFFF
972
973#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
974#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
975#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
976#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
977#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
978#define C_00B128_MEM_ORDERED 0xF7FFFFFF
979
980#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
981#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
982#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
983#define C_00B228_WGP_MODE 0xF7FFFFFF
984#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
985#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
986#define C_00B228_MEM_ORDERED 0xFDFFFFFF
987
988#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
989#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
990#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
991#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
992#define C_00B428_WGP_MODE 0xFBFFFFFF
993#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
994#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
995#define C_00B428_MEM_ORDERED 0xFEFFFFFF
996
997#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
998
999#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
1000#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
1001#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
1002#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
1003#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
1004#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
1005#define C_00B84C_USER_SGPR 0xFFFFFFC1
1006#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
1007#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
1008#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
1009#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
1010#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
1011#define C_00B84C_TGID_X_EN 0xFFFFFF7F
1012#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
1013#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
1014#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
1015#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
1016#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
1017#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
1018#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
1019#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
1020#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
1021#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
1022#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
1023#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
1024/* CIK */
1025#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
1026#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
1027#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
1028/* */
1029#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
1030#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
1031#define C_00B84C_LDS_SIZE 0xFF007FFF
1032#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
1033#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
1034#define C_00B84C_EXCP_EN
1035
1036#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
1037#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
1038
1039#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
1040#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
1041#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
1042#define C_00B848_VGPRS 0xFFFFFFC0
1043#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
1044#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
1045#define C_00B848_SGPRS 0xFFFFFC3F
1046#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
1047#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
1048#define C_00B848_PRIORITY 0xFFFFF3FF
1049#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
1050#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
1051#define C_00B848_FLOAT_MODE 0xFFF00FFF
1052#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1053#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1054#define C_00B848_PRIV 0xFFEFFFFF
1055#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1056#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1057#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1058#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1059#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1060#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1061#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1062#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1063#define C_00B848_IEEE_MODE 0xFF7FFFFF
1064#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1065#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1066#define C_00B848_WGP_MODE 0xDFFFFFFF
1067#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1068#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1069#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1070#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1071#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1072#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1073
1074
1075// Helpers for setting FLOAT_MODE
1076#define FP_ROUND_ROUND_TO_NEAREST 0
1077#define FP_ROUND_ROUND_TO_INF 1
1078#define FP_ROUND_ROUND_TO_NEGINF 2
1079#define FP_ROUND_ROUND_TO_ZERO 3
1080
1081// Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double
1082// precision.
1083#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1084#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1085
1086#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1087#define FP_DENORM_FLUSH_OUT 1
1088#define FP_DENORM_FLUSH_IN 2
1089#define FP_DENORM_FLUSH_NONE 3
1090
1091
1092// Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double
1093// precision.
1094#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1095#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1096
1097#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1098#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1099#define S_00B860_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1100
1101#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1102#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1103#define S_0286E8_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1104
1105#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1106#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1107#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1108#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1109#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1110#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1111#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1112#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1113
1114#define R_SPILLED_SGPRS 0x4
1115#define R_SPILLED_VGPRS 0x8
1116} // End namespace llvm
1117
1118#endif
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
@ OPERAND_KIMM_LAST
Definition: SIDefines.h:247
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:214
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:238
@ OPERAND_REG_INLINE_AC_V2FP32
Definition: SIDefines.h:226
@ OPERAND_REG_INLINE_AC_V2INT32
Definition: SIDefines.h:225
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:189
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:196
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:210
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:207
@ OPERAND_REG_IMM_FIRST
Definition: SIDefines.h:234
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:197
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:224
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:188
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:243
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:240
@ OPERAND_KIMM_FIRST
Definition: SIDefines.h:246
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:193
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:202
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:218
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:192
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:209
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:223
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:220
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:219
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:221
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:198
@ OPERAND_SDWA_VOPC_DST
Definition: SIDefines.h:232
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:191
@ OPERAND_INPUT_MODS
Definition: SIDefines.h:229
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:237
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:206
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:241
@ OPERAND_REG_IMM_LAST
Definition: SIDefines.h:235
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:203
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:208
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:199
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:205
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:190
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:211
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:195
@ OPERAND_SRC_LAST
Definition: SIDefines.h:244
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:194
@ OPERAND_FIRST_TARGET
Definition: MCInstrDesc.h:78
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
SIRCFlags
Definition: SIDefines.h:18
@ HasSGPR
Definition: SIDefines.h:26
@ HasAGPRBit
Definition: SIDefines.h:21
@ HasSGPRbit
Definition: SIDefines.h:22
@ RegTupleAlignUnitsWidth
Definition: SIDefines.h:19
@ RegTupleAlignUnitsMask
Definition: SIDefines.h:28
@ HasVGPRBit
Definition: SIDefines.h:20
@ HasVGPR
Definition: SIDefines.h:24
@ RegKindMask
Definition: SIDefines.h:29
@ HasAGPR
Definition: SIDefines.h:25