10#ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
11#define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H
25namespace SIInstrFlags {
77 WQM = UINT64_C(1) << 35,
245namespace VGPRIndexMode {
270namespace AMDGPUAsmVariants {
467namespace MTBUFFormat {
886namespace VOP3PEncoding {
896namespace ImplicitArg {
914#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
915#define S_00B028_VGPRS(x) (((x) & 0x3F) << 0)
916#define S_00B028_SGPRS(x) (((x) & 0x0F) << 6)
917#define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25)
918#define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1)
919#define C_00B028_MEM_ORDERED 0xFDFFFFFF
921#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C
922#define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8)
923#define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128
924#define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27)
925#define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1)
926#define C_00B128_MEM_ORDERED 0xF7FFFFFF
928#define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228
929#define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27)
930#define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1)
931#define C_00B228_WGP_MODE 0xF7FFFFFF
932#define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25)
933#define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1)
934#define C_00B228_MEM_ORDERED 0xFDFFFFFF
936#define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328
937#define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428
938#define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26)
939#define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1)
940#define C_00B428_WGP_MODE 0xFBFFFFFF
941#define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24)
942#define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1)
943#define C_00B428_MEM_ORDERED 0xFEFFFFFF
945#define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528
947#define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C
948#define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0)
949#define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1)
950#define C_00B84C_SCRATCH_EN 0xFFFFFFFE
951#define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1)
952#define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F)
953#define C_00B84C_USER_SGPR 0xFFFFFFC1
954#define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6)
955#define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1)
956#define C_00B84C_TRAP_HANDLER 0xFFFFFFBF
957#define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7)
958#define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1)
959#define C_00B84C_TGID_X_EN 0xFFFFFF7F
960#define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8)
961#define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1)
962#define C_00B84C_TGID_Y_EN 0xFFFFFEFF
963#define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9)
964#define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1)
965#define C_00B84C_TGID_Z_EN 0xFFFFFDFF
966#define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10)
967#define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1)
968#define C_00B84C_TG_SIZE_EN 0xFFFFFBFF
969#define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11)
970#define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03)
971#define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF
973#define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13)
974#define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03)
975#define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF
977#define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15)
978#define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF)
979#define C_00B84C_LDS_SIZE 0xFF007FFF
980#define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
981#define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
982#define C_00B84C_EXCP_EN
984#define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
985#define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
987#define R_00B848_COMPUTE_PGM_RSRC1 0x00B848
988#define S_00B848_VGPRS(x) (((x) & 0x3F) << 0)
989#define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F)
990#define C_00B848_VGPRS 0xFFFFFFC0
991#define S_00B848_SGPRS(x) (((x) & 0x0F) << 6)
992#define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F)
993#define C_00B848_SGPRS 0xFFFFFC3F
994#define S_00B848_PRIORITY(x) (((x) & 0x03) << 10)
995#define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03)
996#define C_00B848_PRIORITY 0xFFFFF3FF
997#define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12)
998#define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF)
999#define C_00B848_FLOAT_MODE 0xFFF00FFF
1000#define S_00B848_PRIV(x) (((x) & 0x1) << 20)
1001#define G_00B848_PRIV(x) (((x) >> 20) & 0x1)
1002#define C_00B848_PRIV 0xFFEFFFFF
1003#define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21)
1004#define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1)
1005#define C_00B848_DX10_CLAMP 0xFFDFFFFF
1006#define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22)
1007#define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1)
1008#define C_00B848_DEBUG_MODE 0xFFBFFFFF
1009#define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23)
1010#define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1)
1011#define C_00B848_IEEE_MODE 0xFF7FFFFF
1012#define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29)
1013#define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1)
1014#define C_00B848_WGP_MODE 0xDFFFFFFF
1015#define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30)
1016#define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1)
1017#define C_00B848_MEM_ORDERED 0xBFFFFFFF
1018#define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31)
1019#define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1)
1020#define C_00B848_FWD_PROGRESS 0x7FFFFFFF
1024#define FP_ROUND_ROUND_TO_NEAREST 0
1025#define FP_ROUND_ROUND_TO_INF 1
1026#define FP_ROUND_ROUND_TO_NEGINF 2
1027#define FP_ROUND_ROUND_TO_ZERO 3
1031#define FP_ROUND_MODE_SP(x) ((x) & 0x3)
1032#define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2)
1034#define FP_DENORM_FLUSH_IN_FLUSH_OUT 0
1035#define FP_DENORM_FLUSH_OUT 1
1036#define FP_DENORM_FLUSH_IN 2
1037#define FP_DENORM_FLUSH_NONE 3
1042#define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4)
1043#define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6)
1045#define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860
1046#define S_00B860_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1047#define S_00B860_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1049#define R_0286E8_SPI_TMPRING_SIZE 0x0286E8
1050#define S_0286E8_WAVESIZE_PreGFX11(x) (((x) & 0x1FFF) << 12)
1051#define S_0286E8_WAVESIZE_GFX11Plus(x) (((x) & 0x7FFF) << 12)
1053#define R_028B54_VGT_SHADER_STAGES_EN 0x028B54
1054#define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21)
1055#define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22)
1056#define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23)
1057#define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8
1058#define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15)
1059#define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800
1060#define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15)
1062#define R_SPILLED_SGPRS 0x4
1063#define R_SPILLED_VGPRS 0x8
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned > > Src, R600InstrInfo::BankSwizzle Swz)
@ INLINE_INTEGER_C_POSITIVE_MAX
@ ET_DUAL_SRC_BLEND_MAX_IDX
@ ID_SQ_PERF_SNAPSHOT_PC_LO
@ ID_SQ_PERF_SNAPSHOT_DATA1
@ ID_SQ_PERF_SNAPSHOT_DATA
@ ID_SQ_PERF_SNAPSHOT_PC_HI
@ EXCP_EN_FLOAT_DIV0_MASK
@ EXCP_EN_INPUT_DENORMAL_MASK
@ COMPLETION_ACTION_OFFSET
@ MULTIGRID_SYNC_ARG_OFFSET
@ ID_DEALLOC_VGPRS_GFX11Plus
@ ID_HS_TESSFACTOR_GFX11Plus
@ OP_SYS_ECC_ERR_INTERRUPT
@ UFMT_16_16_16_16_USCALED
@ UFMT_10_10_10_2_USCALED
@ UFMT_2_10_10_10_USCALED
@ UFMT_2_10_10_10_SSCALED
@ UFMT_16_16_16_16_SSCALED
@ UFMT_10_10_10_2_SSCALED
@ UFMT_16_16_16_16_USCALED
@ UFMT_2_10_10_10_SSCALED
@ UFMT_2_10_10_10_USCALED
@ UFMT_16_16_16_16_SSCALED
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_AC_V2FP32
@ OPERAND_REG_INLINE_AC_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
@ OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_IMM_V2INT32
@ OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
This is an optimization pass for GlobalISel generic memory operations.