llvm::AMDGPU::Hwreg Namespace Reference

Enumerations
enum	Id {   ID_UNKNOWN_ = -1, ID_SYMBOLIC_FIRST_ = 1, ID_MODE = 1, ID_STATUS = 2,   ID_TRAPSTS = 3, ID_HW_ID = 4, ID_GPR_ALLOC = 5, ID_LDS_ALLOC = 6,   ID_IB_STS = 7, ID_MEM_BASES = 15, ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, ID_TBA_LO = 16,   ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO, ID_TBA_HI = 17, ID_TMA_LO = 18, ID_TMA_HI = 19,   ID_FLAT_SCR_LO = 20, ID_FLAT_SCR_HI = 21, ID_XNACK_MASK = 22, ID_POPS_PACKER = 25,   ID_SYMBOLIC_LAST_ = 26, ID_SHIFT_ = 0, ID_WIDTH_ = 6, ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) }
enum	Offset : unsigned {   OFFSET_DEFAULT_ = 0, OFFSET_SHIFT_ = 6, OFFSET_WIDTH_ = 5, OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_),   OFFSET_MEM_VIOL = 8, OFFSET_SRC_SHARED_BASE = 16, OFFSET_SRC_PRIVATE_BASE = 0 }
enum	WidthMinusOne : unsigned {   WIDTH_M1_DEFAULT_ = 31, WIDTH_M1_SHIFT_ = 11, WIDTH_M1_WIDTH_ = 5, WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_),   WIDTH_M1_SRC_SHARED_BASE = 15, WIDTH_M1_SRC_PRIVATE_BASE = 15 }
enum	Width : unsigned { WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1 }

Functions
int64_t	getHwregId (const StringRef Name)
static unsigned	getLastSymbolicHwreg (const MCSubtargetInfo &STI)
bool	isValidHwreg (int64_t Id, const MCSubtargetInfo &STI)
bool	isValidHwreg (int64_t Id)
bool	isValidHwregOffset (int64_t Offset)
bool	isValidHwregWidth (int64_t Width)
uint64_t	encodeHwreg (uint64_t Id, uint64_t Offset, uint64_t Width)
StringRef	getHwreg (unsigned Id, const MCSubtargetInfo &STI)
void	decodeHwreg (unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)

Variables
const char *const	IdSymbolic []

Enumeration Type Documentation

Id

enum llvm::AMDGPU::Hwreg::Id

Enumerator
ID_UNKNOWN_
ID_SYMBOLIC_FIRST_
ID_MODE
ID_STATUS
ID_TRAPSTS
ID_HW_ID
ID_GPR_ALLOC
ID_LDS_ALLOC
ID_IB_STS
ID_MEM_BASES
ID_SYMBOLIC_FIRST_GFX9_
ID_TBA_LO
ID_SYMBOLIC_FIRST_GFX10_
ID_TBA_HI
ID_TMA_LO
ID_TMA_HI
ID_FLAT_SCR_LO
ID_FLAT_SCR_HI
ID_XNACK_MASK
ID_POPS_PACKER
ID_SYMBOLIC_LAST_
ID_SHIFT_
ID_WIDTH_
ID_MASK_

Definition at line 312 of file SIDefines.h.

Offset

enum llvm::AMDGPU::Hwreg::Offset : unsigned

Enumerator
OFFSET_DEFAULT_
OFFSET_SHIFT_
OFFSET_WIDTH_
OFFSET_MASK_
OFFSET_MEM_VIOL
OFFSET_SRC_SHARED_BASE
OFFSET_SRC_PRIVATE_BASE

Definition at line 339 of file SIDefines.h.

Width

enum llvm::AMDGPU::Hwreg::Width : unsigned

Enumerator
WIDTH_DEFAULT_

Definition at line 362 of file SIDefines.h.

WidthMinusOne

enum llvm::AMDGPU::Hwreg::WidthMinusOne : unsigned

Enumerator
WIDTH_M1_DEFAULT_
WIDTH_M1_SHIFT_
WIDTH_M1_WIDTH_
WIDTH_M1_MASK_
WIDTH_M1_SRC_SHARED_BASE
WIDTH_M1_SRC_PRIVATE_BASE

Definition at line 351 of file SIDefines.h.

Function Documentation

decodeHwreg()

void llvm::AMDGPU::Hwreg::decodeHwreg	(	unsigned	Val,
		unsigned &	Id,
		unsigned &	Offset,
		unsigned &	Width
	)

Definition at line 711 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::SendMsg::ID_MASK_, llvm::AMDGPU::SendMsg::ID_SHIFT_, OFFSET_MASK_, OFFSET_SHIFT_, WIDTH_M1_MASK_, and WIDTH_M1_SHIFT_.

Referenced by llvm::AMDGPU::Waitcnt::combined(), and llvm::AMDGPUInstPrinter::printHwreg().

encodeHwreg()

LLVM_READNONE uint64_t llvm::AMDGPU::Hwreg::encodeHwreg	(	uint64_t	Id,
		uint64_t	Offset,
		uint64_t	Width
	)

Definition at line 701 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::SendMsg::ID_SHIFT_, OFFSET_SHIFT_, and WIDTH_M1_SHIFT_.

Referenced by llvm::AMDGPU::Waitcnt::combined(), llvm::SITargetLowering::emitGWSMemViolTestLoop(), and encodeCnt().

getHwreg()

LLVM_READNONE StringRef llvm::AMDGPU::Hwreg::getHwreg	(	unsigned	Id,
		const MCSubtargetInfo &	STI
	)

Definition at line 707 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::SendMsg::IdSymbolic, and isValidHwreg().

Referenced by llvm::AMDGPU::Waitcnt::combined(), and llvm::AMDGPUInstPrinter::printHwreg().

getHwregId()

LLVM_READONLY int64_t llvm::AMDGPU::Hwreg::getHwregId

(

const StringRef

Name

)

Definition at line 667 of file AMDGPUBaseInfo.cpp.

References ID_SYMBOLIC_FIRST_, ID_SYMBOLIC_LAST_, llvm::AMDGPU::SendMsg::ID_UNKNOWN_, and llvm::AMDGPU::SendMsg::IdSymbolic.

Referenced by llvm::AMDGPU::Waitcnt::combined(), and encodeCnt().

getLastSymbolicHwreg()

static unsigned llvm::AMDGPU::Hwreg::getLastSymbolicHwreg ( const MCSubtargetInfo &  STI )

static

Definition at line 675 of file AMDGPUBaseInfo.cpp.

References ID_SYMBOLIC_FIRST_GFX10_, ID_SYMBOLIC_FIRST_GFX9_, ID_SYMBOLIC_LAST_, llvm::AMDGPU::isCI(), llvm::AMDGPU::isGFX9(), llvm::AMDGPU::isSI(), and llvm::AMDGPU::isVI().

Referenced by isValidHwreg().

isValidHwreg() [1/2]

LLVM_READNONE bool llvm::AMDGPU::Hwreg::isValidHwreg	(	int64_t	Id,
		const MCSubtargetInfo &	STI
	)

Definition at line 684 of file AMDGPUBaseInfo.cpp.

References getLastSymbolicHwreg(), ID_SYMBOLIC_FIRST_, and llvm::AMDGPU::SendMsg::IdSymbolic.

Referenced by llvm::AMDGPU::Waitcnt::combined(), and encodeCnt().

isValidHwreg() [2/2]

LLVM_READNONE bool llvm::AMDGPU::Hwreg::isValidHwreg

(

int64_t

Id

)

Definition at line 689 of file AMDGPUBaseInfo.cpp.

Referenced by getHwreg().

isValidHwregOffset()

LLVM_READNONE bool llvm::AMDGPU::Hwreg::isValidHwregOffset

(

int64_t

Offset

)

Definition at line 693 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPU::Waitcnt::combined(), and encodeCnt().

isValidHwregWidth()

LLVM_READNONE bool llvm::AMDGPU::Hwreg::isValidHwregWidth

(

int64_t

Width

)

Definition at line 697 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPU::Waitcnt::combined(), and encodeCnt().

Variable Documentation

IdSymbolic

const char *const llvm::AMDGPU::Hwreg::IdSymbolic

Initial value:

= {
  nullptr,
  "HW_REG_MODE",
  "HW_REG_STATUS",
  "HW_REG_TRAPSTS",
  "HW_REG_HW_ID",
  "HW_REG_GPR_ALLOC",
  "HW_REG_LDS_ALLOC",
  "HW_REG_IB_STS",
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  nullptr,
  "HW_REG_SH_MEM_BASES",
  "HW_REG_TBA_LO",
  "HW_REG_TBA_HI",
  "HW_REG_TMA_LO",
  "HW_REG_TMA_HI",
  "HW_REG_FLAT_SCR_LO",
  "HW_REG_FLAT_SCR_HI",
  "HW_REG_XNACK_MASK",
  nullptr, 
  nullptr, 
  "HW_REG_POPS_PACKER"
}

Definition at line 55 of file AMDGPUAsmUtils.cpp.