LLVM 17.0.0git
Enumerations | Functions | Variables
llvm::AMDGPU::Hwreg Namespace Reference

Enumerations

enum  Id {
  ID_MODE = 1 , ID_STATUS = 2 , ID_TRAPSTS = 3 , ID_HW_ID = 4 ,
  ID_GPR_ALLOC = 5 , ID_LDS_ALLOC = 6 , ID_IB_STS = 7 , ID_MEM_BASES = 15 ,
  ID_TBA_LO = 16 , ID_TBA_HI = 17 , ID_TMA_LO = 18 , ID_TMA_HI = 19 ,
  ID_XCC_ID = 20 , ID_SQ_PERF_SNAPSHOT_DATA = 21 , ID_SQ_PERF_SNAPSHOT_DATA1 = 22 , ID_SQ_PERF_SNAPSHOT_PC_LO = 23 ,
  ID_SQ_PERF_SNAPSHOT_PC_HI = 24 , ID_FLAT_SCR_LO = 20 , ID_FLAT_SCR_HI = 21 , ID_XNACK_MASK = 22 ,
  ID_HW_ID1 = 23 , ID_HW_ID2 = 24 , ID_POPS_PACKER = 25 , ID_SHADER_CYCLES = 29 ,
  ID_SHIFT_ = 0 , ID_WIDTH_ = 6 , ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_)
}
 
enum  Offset : unsigned {
  OFFSET_DEFAULT_ = 0 , OFFSET_SHIFT_ = 6 , OFFSET_WIDTH_ = 5 , OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_) ,
  OFFSET_MEM_VIOL = 8
}
 
enum  WidthMinusOne : unsigned { WIDTH_M1_DEFAULT_ = 31 , WIDTH_M1_SHIFT_ = 11 , WIDTH_M1_WIDTH_ = 5 , WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_) }
 
enum  Width : unsigned { WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1 }
 
enum  ModeRegisterMasks : uint32_t {
  FP_ROUND_MASK = 0xf << 0 , FP_DENORM_MASK = 0xf << 4 , DX10_CLAMP_MASK = 1 << 8 , IEEE_MODE_MASK = 1 << 9 ,
  LOD_CLAMP_MASK = 1 << 10 , DEBUG_MASK = 1 << 11 , EXCP_EN_INVALID_MASK = 1 << 12 , EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13 ,
  EXCP_EN_FLOAT_DIV0_MASK = 1 << 14 , EXCP_EN_OVERFLOW_MASK = 1 << 15 , EXCP_EN_UNDERFLOW_MASK = 1 << 16 , EXCP_EN_INEXACT_MASK = 1 << 17 ,
  EXCP_EN_INT_DIV0_MASK = 1 << 18 , GPR_IDX_EN_MASK = 1 << 27 , VSKIP_MASK = 1 << 28 , CSP_MASK = 0x7u << 29
}
 

Functions

int64_t getHwregId (const StringRef Name, const MCSubtargetInfo &STI)
 
bool isValidHwreg (int64_t Id)
 
bool isValidHwregOffset (int64_t Offset)
 
bool isValidHwregWidth (int64_t Width)
 
uint64_t encodeHwreg (uint64_t Id, uint64_t Offset, uint64_t Width)
 
StringRef getHwreg (unsigned Id, const MCSubtargetInfo &STI)
 
void decodeHwreg (unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
 

Variables

const CustomOperand< const MCSubtargetInfo & > Opr []
 
const int OPR_SIZE
 

Enumeration Type Documentation

◆ Id

Enumerator
ID_MODE 
ID_STATUS 
ID_TRAPSTS 
ID_HW_ID 
ID_GPR_ALLOC 
ID_LDS_ALLOC 
ID_IB_STS 
ID_MEM_BASES 
ID_TBA_LO 
ID_TBA_HI 
ID_TMA_LO 
ID_TMA_HI 
ID_XCC_ID 
ID_SQ_PERF_SNAPSHOT_DATA 
ID_SQ_PERF_SNAPSHOT_DATA1 
ID_SQ_PERF_SNAPSHOT_PC_LO 
ID_SQ_PERF_SNAPSHOT_PC_HI 
ID_FLAT_SCR_LO 
ID_FLAT_SCR_HI 
ID_XNACK_MASK 
ID_HW_ID1 
ID_HW_ID2 
ID_POPS_PACKER 
ID_SHADER_CYCLES 
ID_SHIFT_ 
ID_WIDTH_ 
ID_MASK_ 

Definition at line 391 of file SIDefines.h.

◆ ModeRegisterMasks

Enumerator
FP_ROUND_MASK 
FP_DENORM_MASK 
DX10_CLAMP_MASK 
IEEE_MODE_MASK 
LOD_CLAMP_MASK 
DEBUG_MASK 
EXCP_EN_INVALID_MASK 
EXCP_EN_INPUT_DENORMAL_MASK 
EXCP_EN_FLOAT_DIV0_MASK 
EXCP_EN_OVERFLOW_MASK 
EXCP_EN_UNDERFLOW_MASK 
EXCP_EN_INEXACT_MASK 
EXCP_EN_INT_DIV0_MASK 
GPR_IDX_EN_MASK 
VSKIP_MASK 
CSP_MASK 

Definition at line 443 of file SIDefines.h.

◆ Offset

Enumerator
OFFSET_DEFAULT_ 
OFFSET_SHIFT_ 
OFFSET_WIDTH_ 
OFFSET_MASK_ 
OFFSET_MEM_VIOL 

Definition at line 422 of file SIDefines.h.

◆ Width

Enumerator
WIDTH_DEFAULT_ 

Definition at line 439 of file SIDefines.h.

◆ WidthMinusOne

Enumerator
WIDTH_M1_DEFAULT_ 
WIDTH_M1_SHIFT_ 
WIDTH_M1_WIDTH_ 
WIDTH_M1_MASK_ 

Definition at line 431 of file SIDefines.h.

Function Documentation

◆ decodeHwreg()

void llvm::AMDGPU::Hwreg::decodeHwreg ( unsigned  Val,
unsigned Id,
unsigned Offset,
unsigned Width 
)

◆ encodeHwreg()

LLVM_READNONE uint64_t llvm::AMDGPU::Hwreg::encodeHwreg ( uint64_t  Id,
uint64_t  Offset,
uint64_t  Width 
)

◆ getHwreg()

LLVM_READNONE StringRef llvm::AMDGPU::Hwreg::getHwreg ( unsigned  Id,
const MCSubtargetInfo STI 
)

Definition at line 1535 of file AMDGPUBaseInfo.cpp.

References Idx, Opr, and OPR_SIZE.

◆ getHwregId()

LLVM_READONLY int64_t llvm::AMDGPU::Hwreg::getHwregId ( const StringRef  Name,
const MCSubtargetInfo STI 
)

Definition at line 1512 of file AMDGPUBaseInfo.cpp.

References Idx, Name, Opr, and OPR_SIZE.

◆ isValidHwreg()

LLVM_READNONE bool llvm::AMDGPU::Hwreg::isValidHwreg ( int64_t  Id)

Definition at line 1517 of file AMDGPUBaseInfo.cpp.

◆ isValidHwregOffset()

LLVM_READNONE bool llvm::AMDGPU::Hwreg::isValidHwregOffset ( int64_t  Offset)

Definition at line 1521 of file AMDGPUBaseInfo.cpp.

◆ isValidHwregWidth()

LLVM_READNONE bool llvm::AMDGPU::Hwreg::isValidHwregWidth ( int64_t  Width)

Definition at line 1525 of file AMDGPUBaseInfo.cpp.

Variable Documentation

◆ Opr

const CustomOperand< const MCSubtargetInfo & > llvm::AMDGPU::Hwreg::Opr

Definition at line 90 of file AMDGPUAsmUtils.cpp.

Referenced by getHwreg(), and getHwregId().

◆ OPR_SIZE

const int llvm::AMDGPU::Hwreg::OPR_SIZE
Initial value:
= static_cast<int>(
sizeof(Opr) / sizeof(CustomOperand<const MCSubtargetInfo &>))
const CustomOperand< const MCSubtargetInfo & > Opr[]

Definition at line 134 of file AMDGPUAsmUtils.cpp.

Referenced by getHwreg(), and getHwregId().