Namespaces
namespace	Barrier

namespace	CPol

namespace	DepCtr

namespace	DPP

namespace	ElfNote

namespace	EncValues

namespace	Exp

namespace	GenericVersion
	Generic target versions emitted by this version of LLVM.

namespace	HSAMD

namespace	HWEncoding

namespace	Hwreg

namespace	ImplicitArg

namespace	IsaInfo

namespace	MTBUFFormat

namespace	PALMD

namespace	SDWA

namespace	SendMsg

namespace	Swizzle

namespace	UCVersion

namespace	UfmtGFX10

namespace	UfmtGFX11

namespace	VGPRIndexMode

namespace	VirtRegFlag

namespace	VOP3PEncoding

namespace	VOPD

Classes
struct	AMDGPUMCKernelCodeT

struct	CanBeVOPD

struct	CustomOperand

struct	CustomOperandVal

struct	D16ImageDimIntrinsic

struct	EncodingField

struct	EncodingFields

struct	GcnBufferFormatInfo

struct	ImageDimIntrinsicInfo

struct	IsaVersion
	Instruction set architecture version. More...

struct	LDSUsesInfoTy

struct	MAIInstInfo

struct	MCKernelDescriptor

struct	MIMGBaseOpcodeInfo

struct	MIMGBiasMappingInfo

struct	MIMGDimInfo

struct	MIMGG16MappingInfo

struct	MIMGInfo

struct	MIMGLZMappingInfo

struct	MIMGMIPMappingInfo

struct	MIMGOffsetMappingInfo

struct	MTBUFInfo

struct	MUBUFInfo

struct	RsrcIntrinsic

struct	SingleUseExceptionInfo

struct	SMInfo

struct	VOP3CDPPAsmOnlyInfo

struct	VOPC64DPPInfo

struct	VOPCDPPAsmOnlyInfo

struct	VOPDComponentInfo

struct	VOPDInfo

struct	VOPInfo

struct	VOPTrue16Info

struct	Waitcnt
	Represents the counter values to wait for in an s_waitcnt instruction. More...

struct	WMMAOpcodeMappingInfo

Typedefs
using	FunctionVariableMap = DenseMap< Function , DenseSet< GlobalVariable > >

using	VariableFunctionMap = DenseMap< GlobalVariable , DenseSet< Function > >

template<unsigned Bit, unsigned D = 0>
using	EncodingBit = EncodingField< Bit, Bit, D >

Enumerations
enum	GPUKind : uint32_t { GK_NONE = 0 , GK_R600 = 1 , GK_R630 = 2 , GK_RS880 = 3 , GK_RV670 = 4 , GK_RV710 = 5 , GK_RV730 = 6 , GK_RV770 = 7 , GK_CEDAR = 8 , GK_CYPRESS = 9 , GK_JUNIPER = 10 , GK_REDWOOD = 11 , GK_SUMO = 12 , GK_BARTS = 13 , GK_CAICOS = 14 , GK_CAYMAN = 15 , GK_TURKS = 16 , GK_R600_FIRST = GK_R600 , GK_R600_LAST = GK_TURKS , GK_GFX600 = 32 , GK_GFX601 = 33 , GK_GFX602 = 34 , GK_GFX700 = 40 , GK_GFX701 = 41 , GK_GFX702 = 42 , GK_GFX703 = 43 , GK_GFX704 = 44 , GK_GFX705 = 45 , GK_GFX801 = 50 , GK_GFX802 = 51 , GK_GFX803 = 52 , GK_GFX805 = 53 , GK_GFX810 = 54 , GK_GFX900 = 60 , GK_GFX902 = 61 , GK_GFX904 = 62 , GK_GFX906 = 63 , GK_GFX908 = 64 , GK_GFX909 = 65 , GK_GFX90A = 66 , GK_GFX90C = 67 , GK_GFX940 = 68 , GK_GFX941 = 69 , GK_GFX942 = 70 , GK_GFX1010 = 71 , GK_GFX1011 = 72 , GK_GFX1012 = 73 , GK_GFX1013 = 74 , GK_GFX1030 = 75 , GK_GFX1031 = 76 , GK_GFX1032 = 77 , GK_GFX1033 = 78 , GK_GFX1034 = 79 , GK_GFX1035 = 80 , GK_GFX1036 = 81 , GK_GFX1100 = 90 , GK_GFX1101 = 91 , GK_GFX1102 = 92 , GK_GFX1103 = 93 , GK_GFX1150 = 94 , GK_GFX1151 = 95 , GK_GFX1152 = 96 , GK_GFX1200 = 100 , GK_GFX1201 = 101 , GK_AMDGCN_FIRST = GK_GFX600 , GK_AMDGCN_LAST = GK_GFX1201 , GK_GFX9_GENERIC = 192 , GK_GFX10_1_GENERIC = 193 , GK_GFX10_3_GENERIC = 194 , GK_GFX11_GENERIC = 195 , GK_GFX12_GENERIC = 196 , GK_AMDGCN_GENERIC_FIRST = GK_GFX9_GENERIC , GK_AMDGCN_GENERIC_LAST = GK_GFX12_GENERIC }
	GPU kinds supported by the AMDGPU target. More...

enum	ArchFeatureKind : uint32_t { FEATURE_NONE = 0 , FEATURE_FMA = 1 << 1 , FEATURE_LDEXP = 1 << 2 , FEATURE_FP64 = 1 << 3 , FEATURE_FAST_FMA_F32 = 1 << 4 , FEATURE_FAST_DENORMAL_F32 = 1 << 5 , FEATURE_WAVE32 = 1 << 6 , FEATURE_XNACK = 1 << 7 , FEATURE_SRAMECC = 1 << 8 , FEATURE_WGP = 1 << 9 }

enum	FeatureError : uint32_t { NO_ERROR = 0 , INVALID_FEATURE_COMBINATION , UNSUPPORTED_TARGET_FEATURE }

enum	TargetIndex { TI_CONSTDATA_START , TI_SCRATCH_RSRC_DWORD0 , TI_SCRATCH_RSRC_DWORD1 , TI_SCRATCH_RSRC_DWORD2 , TI_SCRATCH_RSRC_DWORD3 }

enum class	SchedulingPhase { Initial , PreRAReentry , PostRA }

enum	Fixups { fixup_si_sopp_br = FirstTargetFixupKind , LastTargetFixupKind , NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }

enum	OperandType : unsigned { OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET , OPERAND_REG_IMM_INT64 , OPERAND_REG_IMM_INT16 , OPERAND_REG_IMM_FP32 , OPERAND_REG_IMM_FP64 , OPERAND_REG_IMM_BF16 , OPERAND_REG_IMM_FP16 , OPERAND_REG_IMM_BF16_DEFERRED , OPERAND_REG_IMM_FP16_DEFERRED , OPERAND_REG_IMM_FP32_DEFERRED , OPERAND_REG_IMM_V2BF16 , OPERAND_REG_IMM_V2FP16 , OPERAND_REG_IMM_V2INT16 , OPERAND_REG_IMM_V2INT32 , OPERAND_REG_IMM_V2FP32 , OPERAND_REG_INLINE_C_INT16 , OPERAND_REG_INLINE_C_INT32 , OPERAND_REG_INLINE_C_INT64 , OPERAND_REG_INLINE_C_BF16 , OPERAND_REG_INLINE_C_FP16 , OPERAND_REG_INLINE_C_FP32 , OPERAND_REG_INLINE_C_FP64 , OPERAND_REG_INLINE_C_V2INT16 , OPERAND_REG_INLINE_C_V2BF16 , OPERAND_REG_INLINE_C_V2FP16 , OPERAND_REG_INLINE_C_V2INT32 , OPERAND_REG_INLINE_C_V2FP32 , OPERAND_INLINE_SPLIT_BARRIER_INT32 , OPERAND_KIMM32 , OPERAND_KIMM16 , OPERAND_REG_INLINE_AC_INT16 , OPERAND_REG_INLINE_AC_INT32 , OPERAND_REG_INLINE_AC_BF16 , OPERAND_REG_INLINE_AC_FP16 , OPERAND_REG_INLINE_AC_FP32 , OPERAND_REG_INLINE_AC_FP64 , OPERAND_REG_INLINE_AC_V2INT16 , OPERAND_REG_INLINE_AC_V2BF16 , OPERAND_REG_INLINE_AC_V2FP16 , OPERAND_REG_INLINE_AC_V2INT32 , OPERAND_REG_INLINE_AC_V2FP32 , OPERAND_INPUT_MODS , OPERAND_SDWA_VOPC_DST , OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32 , OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2FP32 , OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16 , OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2FP32 , OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16 , OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2FP32 , OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32 , OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST , OPERAND_KIMM_FIRST = OPERAND_KIMM32 , OPERAND_KIMM_LAST = OPERAND_KIMM16 }

enum	OperandSemantics : unsigned { INT = 0 , FP16 = 1 , BF16 = 2 , FP32 = 3 , FP64 = 4 }

enum	AsmComments { SGPR_SPILL = MachineInstr::TAsmComments }

enum	AMDGPUFltRounds : int8_t { TowardZero = static_cast<int8_t>(RoundingMode::TowardZero) , NearestTiesToEven = static_cast<int8_t>(RoundingMode::NearestTiesToEven) , TowardPositive = static_cast<int8_t>(RoundingMode::TowardPositive) , TowardNegative = static_cast<int8_t>(RoundingMode::TowardNegative) , NearestTiesToAwayUnsupported , Dynamic = static_cast<int8_t>(RoundingMode::Dynamic) , NearestTiesToEvenF32_NearestTiesToEvenF64 = NearestTiesToEven , NearestTiesToEvenF32_TowardPositiveF64 = 8 , NearestTiesToEvenF32_TowardNegativeF64 = 9 , NearestTiesToEvenF32_TowardZeroF64 = 10 , TowardPositiveF32_NearestTiesToEvenF64 = 11 , TowardPositiveF32_TowardPositiveF64 = TowardPositive , TowardPositiveF32_TowardNegativeF64 = 12 , TowardPositiveF32_TowardZeroF64 = 13 , TowardNegativeF32_NearestTiesToEvenF64 = 14 , TowardNegativeF32_TowardPositiveF64 = 15 , TowardNegativeF32_TowardNegativeF64 = TowardNegative , TowardNegativeF32_TowardZeroF64 = 16 , TowardZeroF32_NearestTiesToEvenF64 = 17 , TowardZeroF32_TowardPositiveF64 = 18 , TowardZeroF32_TowardNegativeF64 = 19 , TowardZeroF32_TowardZeroF64 = TowardZero , Invalid = static_cast<int8_t>(RoundingMode::Invalid) }
	Return values used for llvm.get.rounding. More...

enum	{ AMDHSA_COV4 = 4 , AMDHSA_COV5 = 5 , AMDHSA_COV6 = 6 }

Functions
StringRef	getArchFamilyNameAMDGCN (GPUKind AK)

StringRef	getArchNameAMDGCN (GPUKind AK)

StringRef	getArchNameR600 (GPUKind AK)

StringRef	getCanonicalArchName (const Triple &T, StringRef Arch)

GPUKind	parseArchAMDGCN (StringRef CPU)

GPUKind	parseArchR600 (StringRef CPU)

unsigned	getArchAttrAMDGCN (GPUKind AK)

unsigned	getArchAttrR600 (GPUKind AK)

void	fillValidArchListAMDGCN (SmallVectorImpl< StringRef > &Values)

void	fillValidArchListR600 (SmallVectorImpl< StringRef > &Values)

IsaVersion	getIsaVersion (StringRef GPU)

void	fillAMDGPUFeatureMap (StringRef GPU, const Triple &T, StringMap< bool > &Features)
	Fills Features map with default values for given target GPU.

std::pair< FeatureError, StringRef >	insertWaveSizeFeature (StringRef GPU, const Triple &T, StringMap< bool > &Features)
	Inserts wave size feature for given GPU into features map.

bool	isFlatGlobalAddrSpace (unsigned AS)

bool	isExtendedGlobalAddrSpace (unsigned AS)

static bool	addrspacesMayAlias (unsigned AS1, unsigned AS2)

static uint64_t	getRedzoneSizeForScale (int AsanScale)

static uint64_t	getMinRedzoneSizeForGlobal (int AsanScale)

uint64_t	getRedzoneSizeForGlobal (int Scale, uint64_t SizeInBytes)
	Given SizeInBytes of the Value to be instrunmented, Returns the redzone size corresponding to it.

static size_t	TypeStoreSizeToSizeIndex (uint32_t TypeSize)

static Instruction *	genAMDGPUReportBlock (Module &M, IRBuilder<> &IRB, Value *Cond, bool Recover)

static Value *	createSlowPathCmp (Module &M, IRBuilder<> &IRB, Type IntptrTy, Value AddrLong, Value *ShadowValue, uint32_t TypeStoreSize, int AsanScale)

static Instruction *	generateCrashCode (Module &M, IRBuilder<> &IRB, Type IntptrTy, Instruction InsertBefore, Value Addr, bool IsWrite, size_t AccessSizeIndex, Value SizeArgument, bool Recover)

static Value *	memToShadow (Module &M, IRBuilder<> &IRB, Type IntptrTy, Value Shadow, int AsanScale, uint32_t AsanOffset)

static void	instrumentAddressImpl (Module &M, IRBuilder<> &IRB, Instruction OrigIns, Instruction InsertBefore, Value Addr, Align Alignment, uint32_t TypeStoreSize, bool IsWrite, Value SizeArgument, bool UseCalls, bool Recover, int AsanScale, int AsanOffset)

void	instrumentAddress (Module &M, IRBuilder<> &IRB, Instruction OrigIns, Instruction InsertBefore, Value Addr, Align Alignment, TypeSize TypeStoreSize, bool IsWrite, Value SizeArgument, bool UseCalls, bool Recover, int Scale, int Offset)
	Instrument the memory operand Addr.

void	getInterestingMemoryOperands (Module &M, Instruction *I, SmallVectorImpl< InterestingMemoryOperand > &Interesting)
	Get all the memory operands from the instruction that needs to be instrumented.

std::pair< Register, unsigned >	getBaseWithConstantOffset (MachineRegisterInfo &MRI, Register Reg, GISelKnownBits *KnownBits=nullptr, bool CheckNUW=false)
	Returns base register and constant offset.

Intrinsic::ID	getIntrinsicID (const MachineInstr &I)
	Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.

const RsrcIntrinsic *	lookupRsrcIntrinsic (unsigned Intr)

const D16ImageDimIntrinsic *	lookupD16ImageDimIntrinsic (unsigned Intr)

const ImageDimIntrinsicInfo *	getImageDimIntrinsicInfo (unsigned Intr)

const ImageDimIntrinsicInfo *	getImageDimIntrinsicByBaseOpcode (unsigned BaseOpcode, unsigned Dim)

Align	getAlign (const DataLayout &DL, const GlobalVariable *GV)

bool	isDynamicLDS (const GlobalVariable &GV)

bool	isLDSVariableToLower (const GlobalVariable &GV)

bool	eliminateConstantExprUsesOfLDSFromAllInstructions (Module &M)

void	getUsesOfLDSByFunction (const CallGraph &CG, Module &M, FunctionVariableMap &kernels, FunctionVariableMap &Functions)

bool	isKernelLDS (const Function *F)

LDSUsesInfoTy	getTransitiveUsesOfLDS (const CallGraph &CG, Module &M)

void	removeFnAttrFromReachable (CallGraph &CG, Function *KernelRoot, ArrayRef< StringRef > FnAttrs)
	Strip FnAttr attribute from any functions where we may have introduced its use.

bool	isReallyAClobber (const Value Ptr, MemoryDef Def, AAResults *AA)
	Given a `Def` clobbering a load from `Ptr` according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.

bool	isClobberedInFunction (const LoadInst Load, MemorySSA MSSA, AAResults *AA)
	Check is a `Load` is clobbered in its function.

void	printAMDGPUMCExpr (const MCExpr Expr, raw_ostream &OS, const MCAsmInfo MAI)

const MCExpr *	foldAMDGPUMCExpr (const MCExpr *Expr, MCContext &Ctx)

LLVM_READONLY int	getVOPe64 (uint16_t Opcode)

LLVM_READONLY int	getVOPe32 (uint16_t Opcode)

LLVM_READONLY int	getSDWAOp (uint16_t Opcode)

LLVM_READONLY int	getDPPOp32 (uint16_t Opcode)

LLVM_READONLY int	getDPPOp64 (uint16_t Opcode)

LLVM_READONLY int	getBasicFromSDWAOp (uint16_t Opcode)

LLVM_READONLY int	getCommuteRev (uint16_t Opcode)

LLVM_READONLY int	getCommuteOrig (uint16_t Opcode)

LLVM_READONLY int	getAddr64Inst (uint16_t Opcode)

LLVM_READONLY int	getIfAddr64Inst (uint16_t Opcode)
	Check if `Opcode` is an Addr64 opcode.

LLVM_READONLY int	getSOPKOp (uint16_t Opcode)

LLVM_READONLY int	getGlobalSaddrOp (uint16_t Opcode)

LLVM_READONLY int	getGlobalVaddrOp (uint16_t Opcode)

LLVM_READONLY int	getVCMPXNoSDstOp (uint16_t Opcode)

LLVM_READONLY int	getFlatScratchInstSTfromSS (uint16_t Opcode)

LLVM_READONLY int	getFlatScratchInstSVfromSVS (uint16_t Opcode)

LLVM_READONLY int	getFlatScratchInstSSfromSV (uint16_t Opcode)

LLVM_READONLY int	getFlatScratchInstSVfromSS (uint16_t Opcode)

LLVM_READONLY int	getMFMAEarlyClobberOp (uint16_t Opcode)

LLVM_READONLY int	getVCMPXOpFromVCMP (uint16_t Opcode)

uint32_t	decodeFltRoundToHWConversionTable (uint32_t FltRounds)
	Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.

unsigned	getRegBitWidth (const TargetRegisterClass &RC)
	Get the size in bits of a register from the register class `RC`.

template<size_t N>
static StringRef	getNameFromOperandTable (const CustomOperand(&Table)[N], unsigned Encoding, const MCSubtargetInfo &STI)
	Map from the encoding of a sendmsg/hwreg asm operand to it's name.

template<size_t N>
static int64_t	getEncodingFromOperandTable (const CustomOperand(&Table)[N], StringRef Name, const MCSubtargetInfo &STI)
	Map from a symbolic name for a sendmsg/hwreg asm operand to it's encoding.

bool	hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)

bool	isHsaAbi (const MCSubtargetInfo &STI)

unsigned	getAMDHSACodeObjectVersion (const Module &M)

unsigned	getDefaultAMDHSACodeObjectVersion ()

unsigned	getAMDHSACodeObjectVersion (unsigned ABIVersion)

uint8_t	getELFABIVersion (const Triple &T, unsigned CodeObjectVersion)

unsigned	getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)

unsigned	getHostcallImplicitArgPosition (unsigned CodeObjectVersion)

unsigned	getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)

unsigned	getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)

int	getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)

const MIMGBaseOpcodeInfo *	getMIMGBaseOpcode (unsigned Opc)

int	getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)

unsigned	getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo BaseOpcode, const MIMGDimInfo Dim, bool IsA16, bool IsG16Supported)

int	getMTBUFBaseOpcode (unsigned Opc)

int	getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)

int	getMTBUFElements (unsigned Opc)

bool	getMTBUFHasVAddr (unsigned Opc)

bool	getMTBUFHasSrsrc (unsigned Opc)

bool	getMTBUFHasSoffset (unsigned Opc)

int	getMUBUFBaseOpcode (unsigned Opc)

int	getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)

int	getMUBUFElements (unsigned Opc)

bool	getMUBUFHasVAddr (unsigned Opc)

bool	getMUBUFHasSrsrc (unsigned Opc)

bool	getMUBUFHasSoffset (unsigned Opc)

bool	getMUBUFIsBufferInv (unsigned Opc)

bool	getMUBUFTfe (unsigned Opc)

bool	getSMEMIsBuffer (unsigned Opc)

bool	getVOP1IsSingle (unsigned Opc)

bool	getVOP2IsSingle (unsigned Opc)

bool	getVOP3IsSingle (unsigned Opc)

bool	isVOPC64DPP (unsigned Opc)

bool	isVOPCAsmOnly (unsigned Opc)

bool	getMAIIsDGEMM (unsigned Opc)
	Returns true if MAI operation is a double precision GEMM.

bool	getMAIIsGFX940XDL (unsigned Opc)

unsigned	getVOPDEncodingFamily (const MCSubtargetInfo &ST)

CanBeVOPD	getCanBeVOPD (unsigned Opc)

unsigned	getVOPDOpcode (unsigned Opc)

bool	isVOPD (unsigned Opc)

bool	isMAC (unsigned Opc)

bool	isPermlane16 (unsigned Opc)

bool	isCvt_F32_Fp8_Bf8_e64 (unsigned Opc)

bool	isGenericAtomic (unsigned Opc)

bool	isTrue16Inst (unsigned Opc)

bool	isInvalidSingleUseConsumerInst (unsigned Opc)

bool	isInvalidSingleUseProducerInst (unsigned Opc)

unsigned	mapWMMA2AddrTo3AddrOpcode (unsigned Opc)

unsigned	mapWMMA3AddrTo2AddrOpcode (unsigned Opc)

int	getMCOpcode (uint16_t Opcode, unsigned Gen)

int	getVOPDFull (unsigned OpX, unsigned OpY, unsigned EncodingFamily)

std::pair< unsigned, unsigned >	getVOPDComponents (unsigned VOPDOpcode)

VOPD::InstInfo	getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY)

VOPD::InstInfo	getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo)

void	initDefaultAMDKernelCodeT (AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI)

bool	isGroupSegment (const GlobalValue *GV)

bool	isGlobalSegment (const GlobalValue *GV)

bool	isReadOnlySegment (const GlobalValue *GV)

bool	shouldEmitConstantsToTextSection (const Triple &TT)

std::pair< unsigned, unsigned >	getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)

SmallVector< unsigned >	getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size)

unsigned	getVmcntBitMask (const IsaVersion &Version)

unsigned	getLoadcntBitMask (const IsaVersion &Version)

unsigned	getSamplecntBitMask (const IsaVersion &Version)

unsigned	getBvhcntBitMask (const IsaVersion &Version)

unsigned	getExpcntBitMask (const IsaVersion &Version)

unsigned	getLgkmcntBitMask (const IsaVersion &Version)

unsigned	getDscntBitMask (const IsaVersion &Version)

unsigned	getKmcntBitMask (const IsaVersion &Version)

unsigned	getStorecntBitMask (const IsaVersion &Version)

unsigned	getWaitcntBitMask (const IsaVersion &Version)

unsigned	decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)

unsigned	decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)

unsigned	decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)

void	decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
	Decodes Vmcnt, Expcnt and Lgkmcnt from given `Waitcnt` for given isa `Version`, and writes decoded values into `Vmcnt`, `Expcnt` and `Lgkmcnt` respectively.

Waitcnt	decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)

unsigned	encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)

unsigned	encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)

unsigned	encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)

unsigned	encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
	Encodes `Vmcnt`, `Expcnt` and `Lgkmcnt` into Waitcnt for given isa `Version`.

unsigned	encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)

static unsigned	getCombinedCountBitMask (const IsaVersion &Version, bool IsStore)

Waitcnt	decodeLoadcntDscnt (const IsaVersion &Version, unsigned LoadcntDscnt)

Waitcnt	decodeStorecntDscnt (const IsaVersion &Version, unsigned StorecntDscnt)

static unsigned	encodeLoadcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)

static unsigned	encodeStorecnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)

static unsigned	encodeDscnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)

static unsigned	encodeLoadcntDscnt (const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)

unsigned	encodeLoadcntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)

static unsigned	encodeStorecntDscnt (const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)

unsigned	encodeStorecntDscnt (const IsaVersion &Version, const Waitcnt &Decoded)

static unsigned	getDefaultCustomOperandEncoding (const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)

static bool	isSymbolicCustomOperandEncoding (const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)

static bool	decodeCustomOperand (const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)

static int	encodeCustomOperandVal (const CustomOperandVal &Op, int64_t InputVal)

static int	encodeCustomOperand (const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)

unsigned	getInitialPSInputAddr (const Function &F)

bool	getHasColorExport (const Function &F)

bool	getHasDepthExport (const Function &F)

bool	isShader (CallingConv::ID cc)

bool	isGraphics (CallingConv::ID cc)

bool	isCompute (CallingConv::ID cc)

bool	isEntryFunctionCC (CallingConv::ID CC)

bool	isModuleEntryFunctionCC (CallingConv::ID CC)

bool	isChainCC (CallingConv::ID CC)

bool	isKernelCC (const Function *Func)

bool	hasXNACK (const MCSubtargetInfo &STI)

bool	hasSRAMECC (const MCSubtargetInfo &STI)

bool	hasMIMG_R128 (const MCSubtargetInfo &STI)

bool	hasA16 (const MCSubtargetInfo &STI)

bool	hasG16 (const MCSubtargetInfo &STI)

bool	hasPackedD16 (const MCSubtargetInfo &STI)

bool	hasGDS (const MCSubtargetInfo &STI)

unsigned	getNSAMaxSize (const MCSubtargetInfo &STI, bool HasSampler)

unsigned	getMaxNumUserSGPRs (const MCSubtargetInfo &STI)

bool	isSI (const MCSubtargetInfo &STI)

bool	isCI (const MCSubtargetInfo &STI)

bool	isVI (const MCSubtargetInfo &STI)

bool	isGFX9 (const MCSubtargetInfo &STI)

bool	isGFX9_GFX10 (const MCSubtargetInfo &STI)

bool	isGFX9_GFX10_GFX11 (const MCSubtargetInfo &STI)

bool	isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)

bool	isGFX8Plus (const MCSubtargetInfo &STI)

bool	isGFX9Plus (const MCSubtargetInfo &STI)

bool	isNotGFX9Plus (const MCSubtargetInfo &STI)

bool	isGFX10 (const MCSubtargetInfo &STI)

bool	isGFX10_GFX11 (const MCSubtargetInfo &STI)

bool	isGFX10Plus (const MCSubtargetInfo &STI)

bool	isGFX11 (const MCSubtargetInfo &STI)

bool	isGFX11Plus (const MCSubtargetInfo &STI)

bool	isGFX12 (const MCSubtargetInfo &STI)

bool	isGFX12Plus (const MCSubtargetInfo &STI)

bool	isNotGFX12Plus (const MCSubtargetInfo &STI)

bool	isNotGFX11Plus (const MCSubtargetInfo &STI)

bool	isNotGFX10Plus (const MCSubtargetInfo &STI)

bool	isGFX10Before1030 (const MCSubtargetInfo &STI)

bool	isGCN3Encoding (const MCSubtargetInfo &STI)

bool	isGFX10_AEncoding (const MCSubtargetInfo &STI)

bool	isGFX10_BEncoding (const MCSubtargetInfo &STI)

bool	hasGFX10_3Insts (const MCSubtargetInfo &STI)

bool	isGFX10_3_GFX11 (const MCSubtargetInfo &STI)

bool	isGFX90A (const MCSubtargetInfo &STI)

bool	isGFX940 (const MCSubtargetInfo &STI)

bool	hasArchitectedFlatScratch (const MCSubtargetInfo &STI)

bool	hasMAIInsts (const MCSubtargetInfo &STI)

bool	hasVOPD (const MCSubtargetInfo &STI)

bool	hasDPPSrc1SGPR (const MCSubtargetInfo &STI)

unsigned	hasKernargPreload (const MCSubtargetInfo &STI)

int32_t	getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)

bool	isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
	Is Reg - scalar register.

bool	isHi16Reg (MCRegister Reg, const MCRegisterInfo &MRI)

unsigned	getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
	If `Reg` is a pseudo reg, return the correct hardware register given `STI` otherwise return `Reg`.

unsigned	mc2PseudoReg (unsigned Reg)
	Convert hardware register `Reg` to a pseudo register.

bool	isInlineValue (unsigned Reg)

bool	isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).

bool	isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this a KImm operand?

bool	isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Is this floating-point operand?

bool	isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
	Does this operand support only inlinable literals?

unsigned	getRegBitWidth (unsigned RCID)
	Get the size in bits of a register from the register class `RC`.

unsigned	getRegBitWidth (const MCRegisterClass &RC)
	Get the size in bits of a register from the register class `RC`.

unsigned	getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
	Get size of register operand.

bool	isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
	Is this literal inlinable.

bool	isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)

bool	isInlinableLiteralBF16 (int16_t Literal, bool HasInv2Pi)

bool	isInlinableLiteralI16 (int32_t Literal, bool HasInv2Pi)

bool	isInlinableLiteralFP16 (int16_t Literal, bool HasInv2Pi)

std::optional< unsigned >	getInlineEncodingV216 (bool IsFloat, uint32_t Literal)

std::optional< unsigned >	getInlineEncodingV2I16 (uint32_t Literal)

std::optional< unsigned >	getInlineEncodingV2BF16 (uint32_t Literal)

std::optional< unsigned >	getInlineEncodingV2F16 (uint32_t Literal)

bool	isInlinableLiteralV216 (uint32_t Literal, uint8_t OpType)

bool	isInlinableLiteralV2I16 (uint32_t Literal)

bool	isInlinableLiteralV2BF16 (uint32_t Literal)

bool	isInlinableLiteralV2F16 (uint32_t Literal)

bool	isValid32BitLiteral (uint64_t Val, bool IsFP64)

bool	isArgPassedInSGPR (const Argument *A)

bool	isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo)

static bool	hasSMEMByteOffset (const MCSubtargetInfo &ST)

bool	isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)

bool	isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)

static bool	isDwordAligned (uint64_t ByteOffset)

uint64_t	convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
	Convert `ByteOffset` to dwords if the subtarget uses dword SMRD immediate offsets.

std::optional< int64_t >	getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)

std::optional< int64_t >	getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)

unsigned	getNumFlatOffsetBits (const MCSubtargetInfo &ST)
	For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.

bool	isIntrinsicSourceOfDivergence (unsigned IntrID)

bool	isIntrinsicAlwaysUniform (unsigned IntrID)

const GcnBufferFormatInfo *	getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)

const GcnBufferFormatInfo *	getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)

bool	hasAny64BitVGPROperands (const MCInstrDesc &OpDesc)

bool	isDPALU_DPP (const MCInstrDesc &OpDesc)

unsigned	getLdsDwGranularity (const MCSubtargetInfo &ST)

LLVM_READONLY int16_t	getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)

LLVM_READONLY bool	hasNamedOperand (uint64_t Opcode, uint64_t NamedIdx)

LLVM_READONLY int	getSOPPWithRelaxation (uint16_t Opcode)

LLVM_READONLY const MIMGBaseOpcodeInfo *	getMIMGBaseOpcodeInfo (unsigned BaseOpcode)

LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfo (unsigned DimEnum)

LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfoByEncoding (uint8_t DimEnc)

LLVM_READONLY const MIMGDimInfo *	getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)

LLVM_READONLY const MIMGLZMappingInfo *	getMIMGLZMappingInfo (unsigned L)

LLVM_READONLY const MIMGMIPMappingInfo *	getMIMGMIPMappingInfo (unsigned MIP)

LLVM_READONLY const MIMGBiasMappingInfo *	getMIMGBiasMappingInfo (unsigned Bias)

LLVM_READONLY const MIMGOffsetMappingInfo *	getMIMGOffsetMappingInfo (unsigned Offset)

LLVM_READONLY const MIMGG16MappingInfo *	getMIMGG16MappingInfo (unsigned G)

LLVM_READONLY const MIMGInfo *	getMIMGInfo (unsigned Opc)

int	getIntegerAttribute (const Function &F, StringRef Name, int Default)

LLVM_READNONE bool	isKernel (CallingConv::ID CC)

LLVM_READNONE unsigned	getOperandSize (const MCOperandInfo &OpInfo)

LLVM_READNONE unsigned	getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)

LLVM_READNONE bool	isInlinableIntLiteral (int64_t Literal)
	Is this literal inlinable, and not one of the values intended for floating point values.

bool	isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)

LLVM_READNONE bool	isLegalDPALU_DPPControl (unsigned DC)

constexpr std::pair< unsigned, unsigned >	getShiftMask (unsigned Value)
	Deduce the least significant bit aligned shift and mask values for a binary Complement `Value` (as they're defined in SIDefines.h as C_*) as a returned pair<shift, mask>.

const MCExpr *	maskShiftSet (const MCExpr *Val, uint32_t Mask, uint32_t Shift, MCContext &Ctx)
	Provided with the MCExpr * `Val`, uint32 `Mask` and `Shift`, will return the masked and left shifted, in said order of operations, MCExpr * created within the MCContext `Ctx`.

const MCExpr *	maskShiftGet (const MCExpr *Val, uint32_t Mask, uint32_t Shift, MCContext &Ctx)
	Provided with the MCExpr * `Val`, uint32 `Mask` and `Shift`, will return the right shifted and masked, in said order of operations, MCExpr * created within the MCContext `Ctx`.

Variables
const uint64_t	RSRC_DATA_FORMAT = 0xf00000000000LL

const uint64_t	RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

const uint64_t	RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

const uint64_t	RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

static constexpr uint32_t	ExtendedFltRoundOffset = 4
	Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.

static constexpr uint32_t	F32FltRoundOffset = 0
	Offset in mode register of f32 rounding mode.

static constexpr uint32_t	F64FltRoundOffset = 2
	Offset in mode register of f64/f16 rounding mode.

const uint64_t	FltRoundConversionTable

const uint64_t	FltRoundToHWConversionTable

const int	OPR_ID_UNKNOWN = -1

const int	OPR_ID_UNSUPPORTED = -2

const int	OPR_ID_DUPLICATE = -3

const int	OPR_VAL_INVALID = -4

Typedef Documentation

◆ EncodingBit

template<unsigned Bit, unsigned D = 0>

using llvm::AMDGPU::EncodingBit = typedef EncodingField<Bit, Bit, D>

Definition at line 365 of file AMDGPUBaseInfo.h.

◆ FunctionVariableMap

using llvm::AMDGPU::FunctionVariableMap = typedef DenseMap<Function *, DenseSet<GlobalVariable *> >

Definition at line 32 of file AMDGPUMemoryUtils.h.

◆ VariableFunctionMap

using llvm::AMDGPU::VariableFunctionMap = typedef DenseMap<GlobalVariable *, DenseSet<Function *> >

Definition at line 33 of file AMDGPUMemoryUtils.h.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
AMDHSA_COV4
AMDHSA_COV5
AMDHSA_COV6

Definition at line 55 of file AMDGPUBaseInfo.h.

◆ AMDGPUFltRounds

enum llvm::AMDGPU::AMDGPUFltRounds : int8_t

Return values used for llvm.get.rounding.

When both the F32 and F64/F16 modes are the same, returns the standard values. If they differ, returns an extended mode starting at 8.

Enumerator
TowardZero
NearestTiesToEven
TowardPositive
TowardNegative
NearestTiesToAwayUnsupported
Dynamic
NearestTiesToEvenF32_NearestTiesToEvenF64
NearestTiesToEvenF32_TowardPositiveF64
NearestTiesToEvenF32_TowardNegativeF64
NearestTiesToEvenF32_TowardZeroF64
TowardPositiveF32_NearestTiesToEvenF64
TowardPositiveF32_TowardPositiveF64
TowardPositiveF32_TowardNegativeF64
TowardPositiveF32_TowardZeroF64
TowardNegativeF32_NearestTiesToEvenF64
TowardNegativeF32_TowardPositiveF64
TowardNegativeF32_TowardNegativeF64
TowardNegativeF32_TowardZeroF64
TowardZeroF32_NearestTiesToEvenF64
TowardZeroF32_TowardPositiveF64
TowardZeroF32_TowardNegativeF64
TowardZeroF32_TowardZeroF64
Invalid

Definition at line 96 of file SIModeRegisterDefaults.h.

◆ ArchFeatureKind

enum llvm::AMDGPU::ArchFeatureKind : uint32_t

Enumerator
FEATURE_NONE
FEATURE_FMA
FEATURE_LDEXP
FEATURE_FP64
FEATURE_FAST_FMA_F32
FEATURE_FAST_DENORMAL_F32
FEATURE_WAVE32
FEATURE_XNACK
FEATURE_SRAMECC
FEATURE_WGP

Definition at line 135 of file TargetParser.h.

◆ AsmComments

enum llvm::AMDGPU::AsmComments

Enumerator
SGPR_SPILL

Definition at line 1579 of file SIInstrInfo.h.

◆ FeatureError

enum llvm::AMDGPU::FeatureError : uint32_t

Enumerator
NO_ERROR
INVALID_FEATURE_COMBINATION
UNSUPPORTED_TARGET_FEATURE

Definition at line 160 of file TargetParser.h.

◆ Fixups

enum llvm::AMDGPU::Fixups

Enumerator
fixup_si_sopp_br	16-bit PC relative fixup for SOPP branch instructions.
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 16 of file AMDGPUFixupKinds.h.

◆ GPUKind

enum llvm::AMDGPU::GPUKind : uint32_t

GPU kinds supported by the AMDGPU target.

Enumerator
GK_NONE
GK_R600
GK_R630
GK_RS880
GK_RV670
GK_RV710
GK_RV730
GK_RV770
GK_CEDAR
GK_CYPRESS
GK_JUNIPER
GK_REDWOOD
GK_SUMO
GK_BARTS
GK_CAICOS
GK_CAYMAN
GK_TURKS
GK_R600_FIRST
GK_R600_LAST
GK_GFX600
GK_GFX601
GK_GFX602
GK_GFX700
GK_GFX701
GK_GFX702
GK_GFX703
GK_GFX704
GK_GFX705
GK_GFX801
GK_GFX802
GK_GFX803
GK_GFX805
GK_GFX810
GK_GFX900
GK_GFX902
GK_GFX904
GK_GFX906
GK_GFX908
GK_GFX909
GK_GFX90A
GK_GFX90C
GK_GFX940
GK_GFX941
GK_GFX942
GK_GFX1010
GK_GFX1011
GK_GFX1012
GK_GFX1013
GK_GFX1030
GK_GFX1031
GK_GFX1032
GK_GFX1033
GK_GFX1034
GK_GFX1035
GK_GFX1036
GK_GFX1100
GK_GFX1101
GK_GFX1102
GK_GFX1103
GK_GFX1150
GK_GFX1151
GK_GFX1152
GK_GFX1200
GK_GFX1201
GK_AMDGCN_FIRST
GK_AMDGCN_LAST
GK_GFX9_GENERIC
GK_GFX10_1_GENERIC
GK_GFX10_3_GENERIC
GK_GFX11_GENERIC
GK_GFX12_GENERIC
GK_AMDGCN_GENERIC_FIRST
GK_AMDGCN_GENERIC_LAST

Definition at line 35 of file TargetParser.h.

◆ OperandSemantics

enum llvm::AMDGPU::OperandSemantics : unsigned

Enumerator
INT
FP16
BF16
FP32
FP64

Definition at line 274 of file SIDefines.h.

◆ OperandType

enum llvm::AMDGPU::OperandType : unsigned

Enumerator
OPERAND_REG_IMM_INT32	Operands with register or 32-bit immediate.
OPERAND_REG_IMM_INT64
OPERAND_REG_IMM_INT16
OPERAND_REG_IMM_FP32
OPERAND_REG_IMM_FP64
OPERAND_REG_IMM_BF16
OPERAND_REG_IMM_FP16
OPERAND_REG_IMM_BF16_DEFERRED
OPERAND_REG_IMM_FP16_DEFERRED
OPERAND_REG_IMM_FP32_DEFERRED
OPERAND_REG_IMM_V2BF16
OPERAND_REG_IMM_V2FP16
OPERAND_REG_IMM_V2INT16
OPERAND_REG_IMM_V2INT32
OPERAND_REG_IMM_V2FP32
OPERAND_REG_INLINE_C_INT16	Operands with register or inline constant.
OPERAND_REG_INLINE_C_INT32
OPERAND_REG_INLINE_C_INT64
OPERAND_REG_INLINE_C_BF16
OPERAND_REG_INLINE_C_FP16
OPERAND_REG_INLINE_C_FP32
OPERAND_REG_INLINE_C_FP64
OPERAND_REG_INLINE_C_V2INT16
OPERAND_REG_INLINE_C_V2BF16
OPERAND_REG_INLINE_C_V2FP16
OPERAND_REG_INLINE_C_V2INT32
OPERAND_REG_INLINE_C_V2FP32
OPERAND_INLINE_SPLIT_BARRIER_INT32
OPERAND_KIMM32	Operand with 32-bit immediate that uses the constant bus.
OPERAND_KIMM16
OPERAND_REG_INLINE_AC_INT16	Operands with an AccVGPR register or inline constant.
OPERAND_REG_INLINE_AC_INT32
OPERAND_REG_INLINE_AC_BF16
OPERAND_REG_INLINE_AC_FP16
OPERAND_REG_INLINE_AC_FP32
OPERAND_REG_INLINE_AC_FP64
OPERAND_REG_INLINE_AC_V2INT16
OPERAND_REG_INLINE_AC_V2BF16
OPERAND_REG_INLINE_AC_V2FP16
OPERAND_REG_INLINE_AC_V2INT32
OPERAND_REG_INLINE_AC_V2FP32
OPERAND_INPUT_MODS
OPERAND_SDWA_VOPC_DST
OPERAND_REG_IMM_FIRST
OPERAND_REG_IMM_LAST
OPERAND_REG_INLINE_C_FIRST
OPERAND_REG_INLINE_C_LAST
OPERAND_REG_INLINE_AC_FIRST
OPERAND_REG_INLINE_AC_LAST
OPERAND_SRC_FIRST
OPERAND_SRC_LAST
OPERAND_KIMM_FIRST
OPERAND_KIMM_LAST

Definition at line 198 of file SIDefines.h.

◆ SchedulingPhase

enum class llvm::AMDGPU::SchedulingPhase

strong

Enumerator
Initial
PreRAReentry
PostRA

Definition at line 20 of file AMDGPUIGroupLP.h.

◆ TargetIndex

enum llvm::AMDGPU::TargetIndex

Enumerator
TI_CONSTDATA_START
TI_SCRATCH_RSRC_DWORD0
TI_SCRATCH_RSRC_DWORD1
TI_SCRATCH_RSRC_DWORD2
TI_SCRATCH_RSRC_DWORD3

Definition at line 449 of file AMDGPU.h.

Function Documentation

◆ addrspacesMayAlias()

static bool llvm::AMDGPU::addrspacesMayAlias	(	unsigned	AS1,
		unsigned	AS2
	)

inlinestatic

Definition at line 471 of file AMDGPU.h.

References llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::GCNTTIImpl::addrspacesMayAlias(), and llvm::AMDGPUAAResult::alias().

◆ convertSMRDOffsetUnits()

uint64_t llvm::AMDGPU::convertSMRDOffsetUnits	(	const MCSubtargetInfo &	ST,
		uint64_t	ByteOffset
	)

Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.

Definition at line 2846 of file AMDGPUBaseInfo.cpp.

References assert(), hasSMEMByteOffset(), and isDwordAligned().

Referenced by getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ createSlowPathCmp()

static Value * llvm::AMDGPU::createSlowPathCmp	(	Module &	M,
		IRBuilder<> &	IRB,
		Type *	IntptrTy,
		Value *	AddrLong,
		Value *	ShadowValue,
		uint32_t	TypeStoreSize,
		int	AsanScale
	)

static

Definition at line 79 of file AMDGPUAsanInstrumentation.cpp.

References llvm::IRBuilderBase::CreateAdd(), llvm::IRBuilderBase::CreateAnd(), llvm::IRBuilderBase::CreateICmpSGE(), llvm::IRBuilderBase::CreateIntCast(), and llvm::Value::getType().

Referenced by instrumentAddressImpl().

◆ decodeCustomOperand()

static bool llvm::AMDGPU::decodeCustomOperand	(	const CustomOperandVal *	Opr,
		int	Size,
		unsigned	Code,
		int &	Idx,
		StringRef &	Name,
		unsigned &	Val,
		bool &	IsDefault,
		const MCSubtargetInfo &	STI
	)

static

Definition at line 1581 of file AMDGPUBaseInfo.cpp.

References Idx, Name, and Size.

Referenced by llvm::AMDGPU::DepCtr::decodeDepCtr().

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt
	)

Returns: Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 1410 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt().

◆ decodeFltRoundToHWConversionTable()

uint32_t llvm::AMDGPU::decodeFltRoundToHWConversionTable ( uint32_t FltRounds )

Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.

Definition at line 247 of file SIModeRegisterDefaults.cpp.

References FltRoundToHWConversionTable.

Referenced by llvm::SITargetLowering::lowerSET_ROUNDING().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt
	)

Returns: Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 1415 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt().

◆ decodeLoadcntDscnt()

Waitcnt llvm::AMDGPU::decodeLoadcntDscnt	(	const IsaVersion &	Version,
		unsigned	LoadcntDscnt
	)

Returns: Decoded Waitcnt structure from given LoadcntDscnt for given isa Version.

Definition at line 1483 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::Waitcnt::DsCnt, llvm::AMDGPU::Waitcnt::LoadCnt, and llvm::Version.

◆ decodeStorecntDscnt()

Waitcnt llvm::AMDGPU::decodeStorecntDscnt	(	const IsaVersion &	Version,
		unsigned	StorecntDscnt
	)

Returns: Decoded Waitcnt structure from given StorecntDscnt for given isa Version.

Definition at line 1493 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::Waitcnt::DsCnt, llvm::AMDGPU::Waitcnt::StoreCnt, and llvm::Version.

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt
	)

Returns: Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 1402 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by decodeWaitcnt().

◆ decodeWaitcnt() [1/2]

Waitcnt llvm::AMDGPU::decodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Encoded
	)

Definition at line 1427 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), llvm::AMDGPU::Waitcnt::DsCnt, llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LoadCnt, and llvm::Version.

◆ decodeWaitcnt() [2/2]

void llvm::AMDGPU::decodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned &	Vmcnt,
		unsigned &	Expcnt,
		unsigned &	Lgkmcnt
	)

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Should not be used on gfx12+, the instruction which needs it is deprecated

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9) Vmcnt = Waitcnt[15:14,3:0] (gfx9,10) Vmcnt = Waitcnt[15:10] (gfx11) Expcnt = Waitcnt[6:4] (pre-gfx11) Expcnt = Waitcnt[2:0] (gfx11) Lgkmcnt = Waitcnt[11:8] (pre-gfx10) Lgkmcnt = Waitcnt[13:8] (gfx10) Lgkmcnt = Waitcnt[9:4] (gfx11)

Definition at line 1420 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), and llvm::Version.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ eliminateConstantExprUsesOfLDSFromAllInstructions()

bool llvm::AMDGPU::eliminateConstantExprUsesOfLDSFromAllInstructions ( Module & M )

Definition at line 65 of file AMDGPUMemoryUtils.cpp.

References llvm::convertUsersOfConstantsToInstructions(), isLDSVariableToLower(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ encodeCustomOperand()

static int llvm::AMDGPU::encodeCustomOperand	(	const CustomOperandVal *	Opr,
		int	Size,
		const StringRef	Name,
		int64_t	InputVal,
		unsigned &	UsedOprMask,
		const MCSubtargetInfo &	STI
	)

static

Definition at line 1605 of file AMDGPUBaseInfo.cpp.

References encodeCustomOperandVal(), Idx, Name, OPR_ID_DUPLICATE, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and Size.

Referenced by llvm::AMDGPU::DepCtr::encodeDepCtr().

◆ encodeCustomOperandVal()

static int llvm::AMDGPU::encodeCustomOperandVal	(	const CustomOperandVal &	Op,
		int64_t	InputVal
	)

static

Definition at line 1598 of file AMDGPUBaseInfo.cpp.

References OPR_VAL_INVALID.

Referenced by encodeCustomOperand().

◆ encodeDscnt()

static unsigned llvm::AMDGPU::encodeDscnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Dscnt
	)

static

Definition at line 1515 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt(), and encodeStorecntDscnt().

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Expcnt
	)

Returns: Waitcnt with encoded Expcnt for given isa Version.

Definition at line 1444 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Lgkmcnt
	)

Returns: Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 1450 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeLoadcnt()

static unsigned llvm::AMDGPU::encodeLoadcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Loadcnt
	)

static

Definition at line 1503 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt().

◆ encodeLoadcntDscnt() [1/2]

unsigned llvm::AMDGPU::encodeLoadcntDscnt	(	const IsaVersion &	Version,
		const Waitcnt &	Decoded
	)

Returns: Loadcnt and Dscnt components of Decoded encoded as an immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa Version.

Definition at line 1529 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::Waitcnt::DsCnt, encodeLoadcntDscnt(), llvm::AMDGPU::Waitcnt::LoadCnt, and llvm::Version.

◆ encodeLoadcntDscnt() [2/2]

static unsigned llvm::AMDGPU::encodeLoadcntDscnt	(	const IsaVersion &	Version,
		unsigned	Loadcnt,
		unsigned	Dscnt
	)

static

Definition at line 1521 of file AMDGPUBaseInfo.cpp.

References encodeDscnt(), encodeLoadcnt(), getCombinedCountBitMask(), and llvm::Version.

Referenced by encodeLoadcntDscnt().

◆ encodeStorecnt()

static unsigned llvm::AMDGPU::encodeStorecnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Storecnt
	)

static

Definition at line 1509 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeStorecntDscnt().

◆ encodeStorecntDscnt() [1/2]

unsigned llvm::AMDGPU::encodeStorecntDscnt	(	const IsaVersion &	Version,
		const Waitcnt &	Decoded
	)

Returns: Storecnt and Dscnt components of Decoded encoded as an immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa Version.

Definition at line 1541 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::Waitcnt::DsCnt, encodeStorecntDscnt(), llvm::AMDGPU::Waitcnt::StoreCnt, and llvm::Version.

◆ encodeStorecntDscnt() [2/2]

static unsigned llvm::AMDGPU::encodeStorecntDscnt	(	const IsaVersion &	Version,
		unsigned	Storecnt,
		unsigned	Dscnt
	)

static

Definition at line 1533 of file AMDGPUBaseInfo.cpp.

References encodeDscnt(), encodeStorecnt(), getCombinedCountBitMask(), and llvm::Version.

Referenced by encodeStorecntDscnt().

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt	(	const IsaVersion &	Version,
		unsigned	Waitcnt,
		unsigned	Vmcnt
	)

Returns: Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 1435 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ encodeWaitcnt() [1/2]

unsigned llvm::AMDGPU::encodeWaitcnt	(	const IsaVersion &	Version,
		const Waitcnt &	Decoded
	)

Definition at line 1465 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::Waitcnt::DsCnt, encodeWaitcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LoadCnt, and llvm::Version.

◆ encodeWaitcnt() [2/2]

unsigned llvm::AMDGPU::encodeWaitcnt	(	const IsaVersion &	Version,
		unsigned	Vmcnt,
		unsigned	Expcnt,
		unsigned	Lgkmcnt
	)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Should not be used on gfx12+, the instruction which needs it is deprecated

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[2:0] = Expcnt (gfx11+) Waitcnt[3:0] = Vmcnt (pre-gfx9) Waitcnt[3:0] = Vmcnt[3:0] (gfx9,10) Waitcnt[6:4] = Expcnt (pre-gfx11) Waitcnt[9:4] = Lgkmcnt (gfx11) Waitcnt[11:8] = Lgkmcnt (pre-gfx10) Waitcnt[13:8] = Lgkmcnt (gfx10) Waitcnt[15:10] = Vmcnt (gfx11) Waitcnt[15:14] = Vmcnt[5:4] (gfx9,10)

Returns: Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 1456 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), getWaitcntBitMask(), and llvm::Version.

Referenced by encodeWaitcnt().

◆ fillAMDGPUFeatureMap()

void llvm::AMDGPU::fillAMDGPUFeatureMap	(	StringRef	GPU,
		const Triple &	T,
		StringMap< bool > &	Features
	)

Fills Features map with default values for given target GPU.

Definition at line 315 of file TargetParser.cpp.

References llvm::StringRef::empty(), GK_BARTS, GK_CAICOS, GK_CAYMAN, GK_CEDAR, GK_CYPRESS, GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX1013, GK_GFX1030, GK_GFX1031, GK_GFX1032, GK_GFX1033, GK_GFX1034, GK_GFX1035, GK_GFX1036, GK_GFX10_1_GENERIC, GK_GFX10_3_GENERIC, GK_GFX1100, GK_GFX1101, GK_GFX1102, GK_GFX1103, GK_GFX1150, GK_GFX1151, GK_GFX1152, GK_GFX11_GENERIC, GK_GFX1200, GK_GFX1201, GK_GFX12_GENERIC, GK_GFX600, GK_GFX601, GK_GFX602, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX705, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX805, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_GFX90A, GK_GFX90C, GK_GFX940, GK_GFX941, GK_GFX942, GK_GFX9_GENERIC, GK_JUNIPER, GK_NONE, GK_R600, GK_R630, GK_REDWOOD, GK_RS880, GK_RV670, GK_RV710, GK_RV730, GK_RV770, GK_SUMO, GK_TURKS, llvm_unreachable, parseArchAMDGCN(), and parseArchR600().

◆ fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN ( SmallVectorImpl< StringRef > & Values )

Definition at line 214 of file TargetParser.cpp.

References llvm::CallingConv::C, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600 ( SmallVectorImpl< StringRef > & Values )

Definition at line 220 of file TargetParser.cpp.

References llvm::CallingConv::C, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ foldAMDGPUMCExpr()

const MCExpr * llvm::AMDGPU::foldAMDGPUMCExpr	(	const MCExpr *	Expr,
		MCContext &	Ctx
	)

Definition at line 661 of file AMDGPUMCExpr.cpp.

References knownBitsMapHelper(), and tryFoldHelper().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), and llvm::AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT().

◆ genAMDGPUReportBlock()

static Instruction * llvm::AMDGPU::genAMDGPUReportBlock	(	Module &	M,
		IRBuilder<> &	IRB,
		Value *	Cond,
		bool	Recover
	)

static

Definition at line 57 of file AMDGPUAsanInstrumentation.cpp.

References Cond, llvm::IRBuilderBase::CreateIntrinsic(), llvm::IRBuilderBase::CreateIsNotNull(), llvm::MDBuilder::createUnlikelyBranchWeights(), llvm::IRBuilderBase::GetInsertPoint(), llvm::IRBuilderBase::getInt64Ty(), llvm::IRBuilderBase::SetInsertPoint(), and llvm::SplitBlockAndInsertIfThen().

Referenced by instrumentAddressImpl().

◆ generateCrashCode()

static Instruction * llvm::AMDGPU::generateCrashCode	(	Module &	M,
		IRBuilder<> &	IRB,
		Type *	IntptrTy,
		Instruction *	InsertBefore,
		Value *	Addr,
		bool	IsWrite,
		size_t	AccessSizeIndex,
		Value *	SizeArgument,
		bool	Recover
	)

static

Definition at line 97 of file AMDGPUAsanInstrumentation.cpp.

References Addr, llvm::IRBuilderBase::CreateCall(), llvm::FunctionType::get(), llvm::IRBuilderBase::getVoidTy(), kAsanReportErrorTemplate, llvm::IRBuilderBase::SetInsertPoint(), and llvm::raw_svector_ostream::str().

Referenced by instrumentAddressImpl().

◆ getAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst ( uint16_t Opcode )

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ getAddrSizeMIMGOp()

LLVM_READONLY unsigned llvm::AMDGPU::getAddrSizeMIMGOp	(	const MIMGBaseOpcodeInfo *	BaseOpcode,
		const MIMGDimInfo *	Dim,
		bool	IsA16,
		bool	IsG16Supported
	)

Definition at line 294 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates, llvm::divideCeil(), llvm::AMDGPU::MIMGBaseOpcodeInfo::G16, llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip, llvm::AMDGPU::MIMGDimInfo::NumCoords, llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs, and llvm::AMDGPU::MIMGDimInfo::NumGradients.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getAlign()

Align llvm::AMDGPU::getAlign	(	const DataLayout &	DL,
		const GlobalVariable *	GV
	)

Definition at line 30 of file AMDGPUMemoryUtils.cpp.

References DL, llvm::Value::getPointerAlignment(), and llvm::GlobalValue::getValueType().

◆ getAMDHSACodeObjectVersion() [1/2]

unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion ( const Module & M )

Returns: Code object version from the IR module flag.

Definition at line 173 of file AMDGPUBaseInfo.cpp.

References getDefaultAMDHSACodeObjectVersion().

Referenced by llvm::SITargetLowering::allocateHSAUserSGPRs(), allocateHSAUserSGPRs(), llvm::SITargetLowering::allocateSpecialInputSGPRs(), llvm::AMDGPUAsmPrinter::doInitialization(), llvm::AMDGPU::HSAMD::MetadataStreamerMsgPackV4::emitKernel(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::AMDGPULowerKernelAttributesPass::run(), llvm::AMDGPUResourceUsageAnalysis::runOnModule(), and llvm::AMDGPUDisassembler::setABIVersion().

◆ getAMDHSACodeObjectVersion() [2/2]

unsigned llvm::AMDGPU::getAMDHSACodeObjectVersion ( unsigned ABIVersion )

Returns: Code object version from ELF's e_ident[EI_ABIVERSION].

Definition at line 186 of file AMDGPUBaseInfo.cpp.

References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, and getDefaultAMDHSACodeObjectVersion().

◆ getArchAttrAMDGCN()

unsigned llvm::AMDGPU::getArchAttrAMDGCN ( GPUKind AK )

Definition at line 202 of file TargetParser.cpp.

References FEATURE_NONE.

◆ getArchAttrR600()

unsigned llvm::AMDGPU::getArchAttrR600 ( GPUKind AK )

Definition at line 208 of file TargetParser.cpp.

References FEATURE_NONE.

◆ getArchFamilyNameAMDGCN()

StringRef llvm::AMDGPU::getArchFamilyNameAMDGCN ( GPUKind AK )

Definition at line 154 of file TargetParser.cpp.

References llvm::StringRef::drop_back(), llvm::StringRef::empty(), getArchNameAMDGCN(), GK_GFX10_1_GENERIC, GK_GFX10_3_GENERIC, GK_GFX11_GENERIC, GK_GFX12_GENERIC, and GK_GFX9_GENERIC.

◆ getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN ( GPUKind AK )

Definition at line 172 of file TargetParser.cpp.

Referenced by getArchFamilyNameAMDGCN(), llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().

◆ getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600 ( GPUKind AK )

Definition at line 178 of file TargetParser.cpp.

Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().

◆ getBaseWithConstantOffset()

std::pair< Register, unsigned > llvm::AMDGPU::getBaseWithConstantOffset	(	MachineRegisterInfo &	MRI,
		Register	Reg,
		GISelKnownBits *	KnownBits = `nullptr`,
		bool	CheckNUW = `false`
	)

Returns base register and constant offset.

Definition at line 20 of file AMDGPUGlobalISelUtils.cpp.

References assert(), llvm::sampleprof::Base, llvm::getDefIgnoringCopies(), llvm::MIPatternMatch::m_Copy(), llvm::MIPatternMatch::m_GOr(), llvm::MIPatternMatch::m_GPtrAdd(), llvm::MIPatternMatch::m_ICst(), llvm::MIPatternMatch::m_MInstr(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), MRI, llvm::MachineInstr::NoUWrap, and llvm::Offset.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), computeIndirectRegIndex(), llvm::AMDGPURegisterBankInfo::setBufferOffsets(), and llvm::AMDGPULegalizerInfo::splitBufferOffsets().

◆ getBasicFromSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp ( uint16_t Opcode )

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ getBvhcntBitMask()

unsigned llvm::AMDGPU::getBvhcntBitMask ( const IsaVersion & Version )

Returns: Bvhcnt bit mask for given isa Version. Returns 0 for versions that do not support BVHcnt

Definition at line 1366 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

◆ getCanBeVOPD()

LLVM_READONLY CanBeVOPD llvm::AMDGPU::getCanBeVOPD ( unsigned Opc )

Definition at line 536 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by shouldScheduleVOPDAdjacent().

◆ getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName	(	const Triple &	T,
		StringRef	Arch
	)

Definition at line 306 of file TargetParser.cpp.

References assert(), getArchNameAMDGCN(), getArchNameR600(), GK_NONE, parseArchAMDGCN(), and parseArchR600().

◆ getCombinedCountBitMask()

static unsigned llvm::AMDGPU::getCombinedCountBitMask	(	const IsaVersion &	Version,
		bool	IsStore
	)

static

Definition at line 1469 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeLoadcntDscnt(), and encodeStorecntDscnt().

◆ getCommuteOrig()

LLVM_READONLY int llvm::AMDGPU::getCommuteOrig ( uint16_t Opcode )

Referenced by llvm::SIInstrInfo::commuteOpcode().

◆ getCommuteRev()

LLVM_READONLY int llvm::AMDGPU::getCommuteRev ( uint16_t Opcode )

Referenced by llvm::SIInstrInfo::commuteOpcode().

◆ getCompletionActionImplicitArgPosition()

unsigned llvm::AMDGPU::getCompletionActionImplicitArgPosition ( unsigned CodeObjectVersion )

Definition at line 252 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET.

◆ getDefaultAMDHSACodeObjectVersion()

unsigned llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion ( )

Returns: The default HSA code object version. This should only be used when we lack a more accurate CodeObjectVersion value (e.g. from the IR module flag or a .amdhsa_code_object_version directive)

Definition at line 182 of file AMDGPUBaseInfo.cpp.

References DefaultAMDHSACodeObjectVersion.

Referenced by getAMDHSACodeObjectVersion().

◆ getDefaultCustomOperandEncoding()

static unsigned llvm::AMDGPU::getDefaultCustomOperandEncoding	(	const CustomOperandVal *	Opr,
		int	Size,
		const MCSubtargetInfo &	STI
	)

static

Definition at line 1550 of file AMDGPUBaseInfo.cpp.

References Idx, and Size.

Referenced by llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding().

◆ getDefaultQueueImplicitArgPosition()

unsigned llvm::AMDGPU::getDefaultQueueImplicitArgPosition ( unsigned CodeObjectVersion )

Definition at line 241 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET.

◆ getDPPOp32()

LLVM_READONLY int llvm::AMDGPU::getDPPOp32 ( uint16_t Opcode )

◆ getDPPOp64()

LLVM_READONLY int llvm::AMDGPU::getDPPOp64 ( uint16_t Opcode )

◆ getDscntBitMask()

unsigned llvm::AMDGPU::getDscntBitMask ( const IsaVersion & Version )

Returns: Dscnt bit mask for given isa Version. Returns 0 for versions that do not support DScnt

Definition at line 1378 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

◆ getELFABIVersion()

uint8_t llvm::AMDGPU::getELFABIVersion	(	const Triple &	OS,
		unsigned	CodeObjectVersion
	)

Returns: ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION].

Parameters

CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().

Definition at line 199 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, and llvm::report_fatal_error().

Referenced by llvm::AMDGPUTargetELFStreamer::finish().

◆ getEncodingFromOperandTable()

template<size_t N>

static int64_t llvm::AMDGPU::getEncodingFromOperandTable	(	const CustomOperand(&)	Table[N],
		StringRef	Name,
		const MCSubtargetInfo &	STI
	)

static

Map from a symbolic name for a sendmsg/hwreg asm operand to it's encoding.

Definition at line 51 of file AMDGPUAsmUtils.cpp.

References Name, OPR_ID_UNKNOWN, and OPR_ID_UNSUPPORTED.

Referenced by llvm::AMDGPU::Hwreg::getHwregId(), llvm::AMDGPU::SendMsg::getMsgId(), and llvm::AMDGPU::SendMsg::getMsgOpId().

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask ( const IsaVersion & Version )

Returns: Expcnt bit mask for given isa Version.

Definition at line 1370 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getFlatScratchInstSSfromSV()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSSfromSV ( uint16_t Opcode )

Returns: SS (SADDR) form of a FLAT Scratch instruction given an Opcode of an SV (VADDR) form.

◆ getFlatScratchInstSTfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSTfromSS ( uint16_t Opcode )

Returns: ST form with only immediate offset of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), and getFlatScratchSpillOpcode().

◆ getFlatScratchInstSVfromSS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSS ( uint16_t Opcode )

Returns: SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SS (SADDR) form.

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), getFlatScratchSpillOpcode(), and llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getFlatScratchInstSVfromSVS()

LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSVS ( uint16_t Opcode )

Returns: SV (VADDR) form of a FLAT Scratch instruction given an Opcode of an SVS (SADDR + VADDR) form.

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().

◆ getGcnBufferFormatInfo() [1/2]

LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo	(	uint8_t	BitsPerComp,
		uint8_t	NumComponents,
		uint8_t	NumFormat,
		const MCSubtargetInfo &	STI
	)

Definition at line 2932 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by getBufferFormatWithCompCount().

◆ getGcnBufferFormatInfo() [2/2]

LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo	(	uint8_t	Format,
		const MCSubtargetInfo &	STI
	)

Definition at line 2945 of file AMDGPUBaseInfo.cpp.

References llvm::Format, isGFX10(), and isGFX11Plus().

◆ getGlobalSaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp ( uint16_t Opcode )

Returns: SADDR form of a FLAT Global instruction given an Opcode of a VADDR form.

◆ getGlobalVaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalVaddrOp ( uint16_t Opcode )

Returns: VADDR form of a FLAT Global instruction given an Opcode of a SADDR form.

Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().

◆ getHasColorExport()

bool llvm::AMDGPU::getHasColorExport ( const Function & F )

Definition at line 1978 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_PS, and F.

Referenced by generateEndPgm().

◆ getHasDepthExport()

bool llvm::AMDGPU::getHasDepthExport ( const Function & F )

Definition at line 1985 of file AMDGPUBaseInfo.cpp.

References F.

Referenced by generateEndPgm().

◆ getHostcallImplicitArgPosition()

unsigned llvm::AMDGPU::getHostcallImplicitArgPosition ( unsigned COV )

Returns: The offset of the hostcall pointer argument from implicitarg_ptr

Definition at line 230 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET.

◆ getIfAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst ( uint16_t Opcode )

Check if Opcode is an Addr64 opcode.

Returns: Opcode if it is an Addr64 opcode, otherwise -1.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ getImageDimIntrinsicByBaseOpcode()

const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode	(	unsigned	BaseOpcode,
		unsigned	Dim
	)

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getImageDimIntrinsicInfo()

const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicInfo ( unsigned Intr )

Referenced by collectMergeableInsts(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::GCNTTIImpl::instCombineIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), optimizeSection(), and llvm::AMDGPUInstructionSelector::select().

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function & F )

Definition at line 1974 of file AMDGPUBaseInfo.cpp.

References F.

Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getInlineEncodingV216()

std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV216	(	bool	IsFloat,
		uint32_t	Literal
	)

Definition at line 2628 of file AMDGPUBaseInfo.cpp.

References llvm::Literal, and Signed.

Referenced by getInlineEncodingV2F16(), getInlineEncodingV2I16(), and isInlinableLiteralV216().

◆ getInlineEncodingV2BF16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2BF16 ( uint32_t Literal )

Definition at line 2689 of file AMDGPUBaseInfo.cpp.

References llvm::Literal, and Signed.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2BF16().

◆ getInlineEncodingV2F16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2F16 ( uint32_t Literal )

Definition at line 2717 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2F16().

◆ getInlineEncodingV2I16()

LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2I16 ( uint32_t Literal )

Definition at line 2683 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2I16().

◆ getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute	(	const Function &	F,
		StringRef	Name,
		int	Default
	)

Returns: Integer value requested using F's Name attribute.; Default if attribute is not present.; Default and emits error if requested value cannot be converted to integer.

◆ getIntegerPairAttribute()

std::pair< unsigned, unsigned > llvm::AMDGPU::getIntegerPairAttribute	(	const Function &	F,
		StringRef	Name,
		std::pair< unsigned, unsigned >	Default,
		bool	OnlyFirstRequired = `false`
	)

Returns: A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).; Default if attribute is not present.; Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 1292 of file AMDGPUBaseInfo.cpp.

References A, llvm::Default, llvm::LLVMContext::emitError(), F, and Name.

Referenced by llvm::AMDGPUMachineFunction::AMDGPUMachineFunction(), llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().

◆ getIntegerVecAttribute()

SmallVector< unsigned > llvm::AMDGPU::getIntegerVecAttribute	(	const Function &	F,
		StringRef	Name,
		unsigned	Size
	)

Returns: Generate a vector of integer values requested using F's Name attribute.; true if exactly Size (>2) number of integers are found in the attribute.; false if any error occurs.

Definition at line 1316 of file AMDGPUBaseInfo.cpp.

References A, assert(), llvm::Default, llvm::LLVMContext::emitError(), llvm::StringRef::empty(), F, Name, Size, and llvm::StringRef::split().

Referenced by llvm::AMDGPUSubtarget::getMaxNumWorkGroups().

◆ getInterestingMemoryOperands()

void llvm::AMDGPU::getInterestingMemoryOperands	(	Module &	M,
		Instruction *	I,
		SmallVectorImpl< InterestingMemoryOperand > &	Interesting
	)

Get all the memory operands from the instruction that needs to be instrumented.

Definition at line 221 of file AMDGPUAsanInstrumentation.cpp.

References DL, llvm::SmallVectorImpl< T >::emplace_back(), llvm::VectorType::get(), I, Ptr, llvm::Align::value(), and llvm::MaybeAlign::valueOrOne().

◆ getIntrinsicID()

Intrinsic::ID llvm::AMDGPU::getIntrinsicID ( const MachineInstr & I )

Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.

These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But they are not actual instances of GIntrinsics, so we cannot use GIntrinsic::getIntrinsicID() on them.

Definition at line 30 of file AMDGPUInstrInfo.cpp.

References I.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::AMDGPUInstructionSelector::select().

◆ getIsaVersion()

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion ( StringRef GPU )

Definition at line 225 of file TargetParser.cpp.

References GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX1013, GK_GFX1030, GK_GFX1031, GK_GFX1032, GK_GFX1033, GK_GFX1034, GK_GFX1035, GK_GFX1036, GK_GFX10_1_GENERIC, GK_GFX10_3_GENERIC, GK_GFX1100, GK_GFX1101, GK_GFX1102, GK_GFX1103, GK_GFX1150, GK_GFX1151, GK_GFX1152, GK_GFX11_GENERIC, GK_GFX1200, GK_GFX1201, GK_GFX12_GENERIC, GK_GFX600, GK_GFX601, GK_GFX602, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX705, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX805, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_GFX90A, GK_GFX90C, GK_GFX940, GK_GFX941, GK_GFX942, GK_GFX9_GENERIC, and parseArchAMDGCN().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), getNSAMaxSize(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), initDefaultAMDKernelCodeT(), llvm::AMDGPUInstPrinter::printSWaitCnt(), and llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().

◆ getKmcntBitMask()

unsigned llvm::AMDGPU::getKmcntBitMask ( const IsaVersion & Version )

Returns: Dscnt bit mask for given isa Version. Returns 0 for versions that do not support KMcnt

Definition at line 1382 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

◆ getLdsDwGranularity()

unsigned llvm::AMDGPU::getLdsDwGranularity ( const MCSubtargetInfo & ST )

Returns: lds block size in terms of dwords. This is used to calculate the lds size encoded for PAL metadata 3.0+ which must be defined in terms of bytes.

Definition at line 2971 of file AMDGPUBaseInfo.cpp.

Referenced by EmitPALMetadataCommon().

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask ( const IsaVersion & Version )

Returns: Lgkmcnt bit mask for given isa Version.

Definition at line 1374 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getLoadcntBitMask()

unsigned llvm::AMDGPU::getLoadcntBitMask ( const IsaVersion & Version )

Returns: Loadcnt bit mask for given isa Version. Returns 0 for versions that do not support LOADcnt

Definition at line 1358 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

◆ getMAIIsDGEMM()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsDGEMM ( unsigned Opc )

Returns true if MAI operation is a double precision GEMM.

Definition at line 518 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by isDGEMM().

◆ getMAIIsGFX940XDL()

LLVM_READONLY bool llvm::AMDGPU::getMAIIsGFX940XDL ( unsigned Opc )

Definition at line 523 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by isXDL().

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp	(	unsigned	Opc,
		unsigned	NewChannels
	)

Definition at line 286 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGInfo(), llvm::AMDGPU::MIMGInfo::MIMGEncoding, llvm::AMDGPU::MIMGInfo::Opcode, and llvm::AMDGPU::MIMGInfo::VAddrDwords.

◆ getMaxNumUserSGPRs()

unsigned llvm::AMDGPU::getMaxNumUserSGPRs ( const MCSubtargetInfo & STI )

Definition at line 2094 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::GCNUserSGPRUsageInfo::allocKernargPreloadSGPRs(), llvm::GCNSubtarget::getMaxNumUserSGPRs(), and llvm::GCNUserSGPRUsageInfo::getNumFreeUserSGPRs().

◆ getMCOpcode()

LLVM_READONLY int llvm::AMDGPU::getMCOpcode	(	uint16_t	Opcode,
		unsigned	Gen
	)

Definition at line 645 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

unsigned llvm::AMDGPU::getMCReg	(	unsigned	Reg,
		const MCSubtargetInfo &	STI
	)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 2297 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, llvm::Triple::r600, and Reg.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), and AMDGPUMCInstLower::lowerOperand().

◆ getMFMAEarlyClobberOp()

LLVM_READONLY int llvm::AMDGPU::getMFMAEarlyClobberOp ( uint16_t Opcode )

Returns: earlyclobber version of a MAC MFMA is exists.

Referenced by llvm::SIInstrInfo::convertToThreeAddress(), and llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMIMGBaseOpcode()

LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode ( unsigned Opc )

Definition at line 281 of file AMDGPUBaseInfo.cpp.

References getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Info.

◆ getMIMGBaseOpcodeInfo()

LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcodeInfo ( unsigned BaseOpcode )

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMIMGBaseOpcode(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), simplifyAMDGCNImageIntrinsic(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGBiasMappingInfo()

LLVM_READONLY const MIMGBiasMappingInfo * llvm::AMDGPU::getMIMGBiasMappingInfo ( unsigned Bias )

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGDimInfo()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfo ( unsigned DimEnum )

◆ getMIMGDimInfoByAsmSuffix()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByAsmSuffix ( StringRef AsmSuffix )

◆ getMIMGDimInfoByEncoding()

LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByEncoding ( uint8_t DimEnc )

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGG16MappingInfo()

LLVM_READONLY const MIMGG16MappingInfo * llvm::AMDGPU::getMIMGG16MappingInfo ( unsigned G )

◆ getMIMGInfo()

LLVM_READONLY const MIMGInfo * llvm::AMDGPU::getMIMGInfo ( unsigned Opc )

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMaskedMIMGOp(), getMIMGBaseOpcode(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGLZMappingInfo()

LLVM_READONLY const MIMGLZMappingInfo * llvm::AMDGPU::getMIMGLZMappingInfo ( unsigned L )

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGMIPMappingInfo()

LLVM_READONLY const MIMGMIPMappingInfo * llvm::AMDGPU::getMIMGMIPMappingInfo ( unsigned MIP )

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGOffsetMappingInfo()

LLVM_READONLY const MIMGOffsetMappingInfo * llvm::AMDGPU::getMIMGOffsetMappingInfo ( unsigned Offset )

Referenced by simplifyAMDGCNImageIntrinsic().

◆ getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode	(	unsigned	BaseOpcode,
		unsigned	MIMGEncoding,
		unsigned	VDataDwords,
		unsigned	VAddrDwords
	)

Definition at line 274 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().

◆ getMinRedzoneSizeForGlobal()

static uint64_t llvm::AMDGPU::getMinRedzoneSizeForGlobal ( int AsanScale )

static

Definition at line 24 of file AMDGPUAsanInstrumentation.cpp.

References getRedzoneSizeForScale().

Referenced by getRedzoneSizeForGlobal().

◆ getMTBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode ( unsigned Opc )

Definition at line 422 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMTBUFElements ( unsigned Opc )

Definition at line 432 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSoffset ( unsigned Opc )

Definition at line 447 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSrsrc ( unsigned Opc )

Definition at line 442 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasVAddr ( unsigned Opc )

Definition at line 437 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMTBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode	(	unsigned	BaseOpc,
		unsigned	Elements
	)

Definition at line 427 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode ( unsigned Opc )

Definition at line 452 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFElements()

LLVM_READONLY int llvm::AMDGPU::getMUBUFElements ( unsigned Opc )

Definition at line 462 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset ( unsigned Opc )

Definition at line 477 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc ( unsigned Opc )

Definition at line 472 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr ( unsigned Opc )

Definition at line 467 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFIsBufferInv()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFIsBufferInv ( unsigned Opc )

Definition at line 482 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode	(	unsigned	BaseOpc,
		unsigned	Elements
	)

Definition at line 457 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getMUBUFTfe()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFTfe ( unsigned Opc )

Definition at line 487 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by llvm::SITargetLowering::AddMemOpInit().

◆ getMultigridSyncArgImplicitArgPosition()

unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition ( unsigned COV )

Returns: The offset of the multigrid_sync_arg argument from implicitarg_ptr

Definition at line 216 of file AMDGPUBaseInfo.cpp.

References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET.

◆ getNamedOperandIdx()

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx	(	uint16_t	Opcode,
		uint16_t	NamedIdx
	)

◆ getNameFromOperandTable()

template<size_t N>

static StringRef llvm::AMDGPU::getNameFromOperandTable	(	const CustomOperand(&)	Table[N],
		unsigned	Encoding,
		const MCSubtargetInfo &	STI
	)

static

Map from the encoding of a sendmsg/hwreg asm operand to it's name.

Definition at line 27 of file AMDGPUAsmUtils.cpp.

References Idx, N, and Name.

Referenced by llvm::AMDGPU::Hwreg::getHwreg(), llvm::AMDGPU::SendMsg::getMsgName(), and llvm::AMDGPU::SendMsg::getMsgOpName().

◆ getNSAMaxSize()

unsigned llvm::AMDGPU::getNSAMaxSize	(	const MCSubtargetInfo &	STI,
		bool	HasSampler
	)

Definition at line 2083 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getCPU(), getIsaVersion(), and llvm::Version.

Referenced by llvm::GCNSubtarget::getNSAMaxSize().

◆ getNumFlatOffsetBits()

unsigned llvm::AMDGPU::getNumFlatOffsetBits ( const MCSubtargetInfo & ST )

For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.

Returns: The number of bits available for the signed offset field in flat instructions. Note that some forms of the instruction disallow negative offsets.

Definition at line 2894 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX12().

Referenced by llvm::SIInstrInfo::isLegalFLATOffset(), and llvm::SIInstrInfo::splitFlatOffset().

◆ getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

inline

Definition at line 1407 of file AMDGPUBaseInfo.h.

References getOperandSize().

◆ getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo & OpInfo )

inline

Definition at line 1354 of file AMDGPUBaseInfo.h.

Referenced by getOperandSize().

◆ getRedzoneSizeForGlobal()

uint64_t llvm::AMDGPU::getRedzoneSizeForGlobal	(	int	AsanScale,
		uint64_t	SizeInBytes
	)

Given SizeInBytes of the Value to be instrunmented, Returns the redzone size corresponding to it.

Definition at line 28 of file AMDGPUAsanInstrumentation.cpp.

References assert(), and getMinRedzoneSizeForGlobal().

◆ getRedzoneSizeForScale()

static uint64_t llvm::AMDGPU::getRedzoneSizeForScale ( int AsanScale )

static

Definition at line 18 of file AMDGPUAsanInstrumentation.cpp.

Referenced by getMinRedzoneSizeForGlobal().

◆ getRegBitWidth() [1/3]

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass & RC )

Get the size in bits of a register from the register class RC.

Definition at line 2536 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

◆ getRegBitWidth() [2/3]

unsigned llvm::AMDGPU::getRegBitWidth ( const TargetRegisterClass & RC )

Get the size in bits of a register from the register class RC.

Definition at line 2849 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::getID(), and getRegBitWidth().

Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::canInsertSelect(), getRegBitWidth(), getRegOperandSize(), and llvm::SIRegisterInfo::getRegSplitParts().

◆ getRegBitWidth() [3/3]

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned RCID )

Get the size in bits of a register from the register class RC.

Definition at line 2397 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

◆ getRegOperandSize()

unsigned llvm::AMDGPU::getRegOperandSize	(	const MCRegisterInfo *	MRI,
		const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Get size of register operand.

Definition at line 2540 of file AMDGPUBaseInfo.cpp.

References assert(), and getRegBitWidth().

◆ getSamplecntBitMask()

unsigned llvm::AMDGPU::getSamplecntBitMask ( const IsaVersion & Version )

Returns: Samplecnt bit mask for given isa Version. Returns 0 for versions that do not support SAMPLEcnt

Definition at line 1362 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

◆ getSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getSDWAOp ( uint16_t Opcode )

◆ getShiftMask()

constexpr std::pair< unsigned, unsigned > llvm::AMDGPU::getShiftMask ( unsigned Value )

constexpr

Deduce the least significant bit aligned shift and mask values for a binary Complement Value (as they're defined in SIDefines.h as C_*) as a returned pair<shift, mask>.

That is to say Value == ~(mask << shift)

For example, given C_00B848_FWD_PROGRESS (i.e., 0x7FFFFFFF) from SIDefines.h, this will return the pair as (31,1).

Definition at line 27 of file SIDefinesUtils.h.

◆ getSMEMIsBuffer()

LLVM_READONLY bool llvm::AMDGPU::getSMEMIsBuffer ( unsigned Opc )

Definition at line 492 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getSMRDEncodedLiteralOffset32()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32	(	const MCSubtargetInfo &	ST,
		int64_t	ByteOffset
	)

Returns: The encoding that can be used for a 32-bit literal offset in an SMRD instruction. This is only useful on CI.s

Definition at line 2884 of file AMDGPUBaseInfo.cpp.

References convertSMRDOffsetUnits(), isCI(), and isDwordAligned().

◆ getSMRDEncodedOffset()

std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	ByteOffset,
		bool	IsBuffer,
		bool	HasSOffset = `false`
	)

Returns: The encoding that will be used for ByteOffset in the SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets.

Definition at line 2855 of file AMDGPUBaseInfo.cpp.

References assert(), convertSMRDOffsetUnits(), hasSMEMByteOffset(), hasSMRDSignedImmOffset(), isDwordAligned(), isGFX12Plus(), and isLegalSMRDEncodedUnsignedOffset().

◆ getSOPKOp()

LLVM_READONLY int llvm::AMDGPU::getSOPKOp ( uint16_t Opcode )

◆ getSOPPWithRelaxation()

LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation ( uint16_t Opcode )

◆ getStorecntBitMask()

unsigned llvm::AMDGPU::getStorecntBitMask ( const IsaVersion & Version )

Returns: STOREcnt or VScnt bit mask for given isa Version. returns 0 for versions that do not support STOREcnt or VScnt. STOREcnt and VScnt are the same counter, the name used depends on the ISA version.

Definition at line 1386 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

◆ getTotalNumVGPRs()

int llvm::AMDGPU::getTotalNumVGPRs	(	bool	has90AInsts,
		int32_t	ArgNumAGPR,
		int32_t	ArgNumVGPR
	)

Definition at line 2222 of file AMDGPUBaseInfo.cpp.

References llvm::alignTo().

Referenced by llvm::AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs().

◆ getTransitiveUsesOfLDS()

LDSUsesInfoTy llvm::AMDGPU::getTransitiveUsesOfLDS	(	const CallGraph &	CG,
		Module &	M
	)

Definition at line 117 of file AMDGPUMemoryUtils.cpp.

References assert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::contains(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::contains(), llvm::SmallVectorBase< Size_T >::empty(), F, getUsesOfLDSByFunction(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), isDynamicLDS(), isKernelLDS(), llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::report_fatal_error(), and llvm::set_union().

◆ getUsesOfLDSByFunction()

void llvm::AMDGPU::getUsesOfLDSByFunction	(	const CallGraph &	CG,
		Module &	M,
		FunctionVariableMap &	kernels,
		FunctionVariableMap &	Functions
	)

Definition at line 86 of file AMDGPUMemoryUtils.cpp.

References F, I, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::insert(), isKernelLDS(), and isLDSVariableToLower().

Referenced by getTransitiveUsesOfLDS().

◆ getVCMPXNoSDstOp()

LLVM_READONLY int llvm::AMDGPU::getVCMPXNoSDstOp ( uint16_t Opcode )

◆ getVCMPXOpFromVCMP()

LLVM_READONLY int llvm::AMDGPU::getVCMPXOpFromVCMP ( uint16_t Opcode )

Returns: v_cmpx version of a v_cmp instruction.

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask ( const IsaVersion & Version )

Returns: Vmcnt bit mask for given isa Version.

Definition at line 1352 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().

◆ getVOP1IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP1IsSingle ( unsigned Opc )

Definition at line 497 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOP2IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP2IsSingle ( unsigned Opc )

Definition at line 502 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOP3IsSingle()

LLVM_READONLY bool llvm::AMDGPU::getVOP3IsSingle ( unsigned Opc )

Definition at line 507 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOPDComponents()

LLVM_READONLY std::pair< unsigned, unsigned > llvm::AMDGPU::getVOPDComponents ( unsigned VOPDOpcode )

Definition at line 655 of file AMDGPUBaseInfo.cpp.

References assert(), and Info.

Referenced by getVOPDInstInfo().

◆ getVOPDEncodingFamily()

LLVM_READONLY unsigned llvm::AMDGPU::getVOPDEncodingFamily ( const MCSubtargetInfo & ST )

Returns: SIEncodingFamily used for VOPD encoding on a ST.

Definition at line 528 of file AMDGPUBaseInfo.cpp.

References llvm::SIEncodingFamily::GFX11, llvm::SIEncodingFamily::GFX12, and llvm_unreachable.

◆ getVOPDFull()

LLVM_READONLY int llvm::AMDGPU::getVOPDFull	(	unsigned	OpX,
		unsigned	OpY,
		unsigned	EncodingFamily
	)

Definition at line 649 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOPDInstInfo() [1/2]

LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo	(	const MCInstrDesc &	OpX,
		const MCInstrDesc &	OpY
	)

Definition at line 751 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::checkVOPDRegConstraints().

◆ getVOPDInstInfo() [2/2]

LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo	(	unsigned	VOPDOpcode,
		const MCInstrInfo *	InstrInfo
	)

Definition at line 755 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::VOPD::COMPONENT_X, llvm::MCInstrInfo::get(), and getVOPDComponents().

◆ getVOPDOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::getVOPDOpcode ( unsigned Opc )

Definition at line 543 of file AMDGPUBaseInfo.cpp.

References Info.

◆ getVOPe32()

LLVM_READONLY int llvm::AMDGPU::getVOPe32 ( uint16_t Opcode )

Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding().

◆ getVOPe64()

LLVM_READONLY int llvm::AMDGPU::getVOPe64 ( uint16_t Opcode )

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask ( const IsaVersion & Version )

Returns: Waitcnt bit mask for given isa Version.

Definition at line 1390 of file AMDGPUBaseInfo.cpp.

References llvm::Version.

Referenced by encodeWaitcnt().

◆ hasA16()

bool llvm::AMDGPU::hasA16 ( const MCSubtargetInfo & STI )

Definition at line 2066 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasAny64BitVGPROperands()

bool llvm::AMDGPU::hasAny64BitVGPROperands ( const MCInstrDesc & OpDesc )

Returns: true if an instruction may have a 64-bit VGPR operand.

Definition at line 2952 of file AMDGPUBaseInfo.cpp.

References getNamedOperandIdx(), llvm::MCInstrDesc::getOpcode(), Idx, and llvm::MCInstrDesc::operands().

Referenced by isDPALU_DPP().

◆ hasArchitectedFlatScratch()

bool llvm::AMDGPU::hasArchitectedFlatScratch ( const MCSubtargetInfo & STI )

Definition at line 2202 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().

◆ hasDPPSrc1SGPR()

bool llvm::AMDGPU::hasDPPSrc1SGPR ( const MCSubtargetInfo & STI )

Definition at line 2214 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasG16()

bool llvm::AMDGPU::hasG16 ( const MCSubtargetInfo & STI )

Definition at line 2070 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasGDS()

bool llvm::AMDGPU::hasGDS ( const MCSubtargetInfo & STI )

Definition at line 2079 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ hasGFX10_3Insts()

bool llvm::AMDGPU::hasGFX10_3Insts ( const MCSubtargetInfo & STI )

Definition at line 2186 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), and llvm::AMDGPU::IsaInfo::getVGPRAllocGranule().

◆ hasKernargPreload()

unsigned llvm::AMDGPU::hasKernargPreload ( const MCSubtargetInfo & STI )

Definition at line 2218 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUAsmPrinter::emitFunctionBodyStart(), and llvm::AMDGPUDisassembler::hasKernargPreload().

◆ hasMAIInsts()

bool llvm::AMDGPU::hasMAIInsts ( const MCSubtargetInfo & STI )

Definition at line 2206 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128 ( const MCSubtargetInfo & STI )

Definition at line 2062 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasNamedOperand()

LLVM_READONLY bool llvm::AMDGPU::hasNamedOperand	(	uint64_t	Opcode,
		uint64_t	NamedIdx
	)

inline

Definition at line 383 of file AMDGPUBaseInfo.h.

References getNamedOperandIdx().

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), cvtVOP3DstOpSelOnly(), llvm::SIRegisterInfo::eliminateFrameIndex(), getFlatScratchSpillOpcode(), llvm::SIInstrInfo::getRegClass(), llvm::SIInstrInfo::hasModifiers(), llvm::AMDGPUDisassembler::isMacDPP(), isVOPD(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SITargetLowering::PostISelFolding().

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16 ( const MCSubtargetInfo & STI )

Definition at line 2074 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature(), isCI(), and isSI().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().

◆ hasSMEMByteOffset()

static bool llvm::AMDGPU::hasSMEMByteOffset ( const MCSubtargetInfo & ST )

static

Definition at line 2818 of file AMDGPUBaseInfo.cpp.

References isGCN3Encoding(), and isGFX10Plus().

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedOffset(), and isLegalSMRDEncodedUnsignedOffset().

◆ hasSMRDSignedImmOffset()

bool llvm::AMDGPU::hasSMRDSignedImmOffset ( const MCSubtargetInfo & ST )

Returns: true if the target supports signed immediate offset for SMRD instructions.

Definition at line 164 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus().

Referenced by getSMRDEncodedOffset(), and isLegalSMRDEncodedSignedOffset().

◆ hasSRAMECC()

bool llvm::AMDGPU::hasSRAMECC ( const MCSubtargetInfo & STI )

Definition at line 2058 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ hasVOPD()

bool llvm::AMDGPU::hasVOPD ( const MCSubtargetInfo & STI )

Definition at line 2210 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant().

◆ hasXNACK()

bool llvm::AMDGPU::hasXNACK ( const MCSubtargetInfo & STI )

Definition at line 2054 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT	(	AMDGPUMCKernelCodeT &	KernelCode,
		const MCSubtargetInfo *	STI
	)

Definition at line 1239 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPU::AMDGPUMCKernelCodeT::initDefault().

◆ insertWaveSizeFeature()

std::pair< FeatureError, StringRef > llvm::AMDGPU::insertWaveSizeFeature	(	StringRef	GPU,
		const Triple &	T,
		StringMap< bool > &	Features
	)

Inserts wave size feature for given GPU into features map.

Definition at line 620 of file TargetParser.cpp.

References llvm::StringMap< ValueTy, AllocatorTy >::count(), llvm::StringRef::empty(), llvm::StringMap< ValueTy, AllocatorTy >::insert(), INVALID_FEATURE_COMBINATION, isWave32Capable(), NO_ERROR, and UNSUPPORTED_TARGET_FEATURE.

◆ instrumentAddress()

void llvm::AMDGPU::instrumentAddress	(	Module &	M,
		IRBuilder<> &	IRB,
		Instruction *	OrigIns,
		Instruction *	InsertBefore,
		Value *	Addr,
		Align	Alignment,
		TypeSize	TypeStoreSize,
		bool	IsWrite,
		Value *	SizeArgument,
		bool	UseCalls,
		bool	Recover,
		int	Scale,
		int	Offset
	)

Instrument the memory operand Addr.

Generates report blocks that catch the addressing errors.

Definition at line 184 of file AMDGPUAsanInstrumentation.cpp.

References Addr, llvm::IRBuilderBase::CreateAdd(), llvm::IRBuilderBase::CreateIntToPtr(), llvm::IRBuilderBase::CreateLShr(), llvm::IRBuilderBase::CreatePtrToInt(), llvm::IRBuilderBase::CreateTypeSize(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), instrumentAddressImpl(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), llvm::IRBuilderBase::SetInsertPoint(), Size, and llvm::Align::value().

◆ instrumentAddressImpl()

static void llvm::AMDGPU::instrumentAddressImpl	(	Module &	M,
		IRBuilder<> &	IRB,
		Instruction *	OrigIns,
		Instruction *	InsertBefore,
		Value *	Addr,
		Align	Alignment,
		uint32_t	TypeStoreSize,
		bool	IsWrite,
		Value *	SizeArgument,
		bool	UseCalls,
		bool	Recover,
		int	AsanScale,
		int	AsanOffset
	)

static

◆ isArgPassedInSGPR() [1/2]

bool llvm::AMDGPU::isArgPassedInSGPR ( const Argument * A )

◆ isArgPassedInSGPR() [2/2]

bool llvm::AMDGPU::isArgPassedInSGPR	(	const CallBase *	CB,
		unsigned	ArgNo
	)

Definition at line 2792 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, CC, llvm::CallBase::getCallingConv(), llvm::CallBase::paramHasAttr(), and llvm::CallingConv::SPIR_KERNEL.

◆ isChainCC()

LLVM_READNONE bool llvm::AMDGPU::isChainCC ( CallingConv::ID CC )

Definition at line 2040 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, and CC.

Referenced by getCallOpcode(), llvm::AMDGPUCallLowering::handleImplicitCallArguments(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isModuleEntryFunctionCC(), llvm::SITargetLowering::LowerCall(), llvm::AMDGPUCallLowering::lowerTailCall(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isCI()

bool llvm::AMDGPU::isCI ( const MCSubtargetInfo & STI )

Definition at line 2100 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), getSMRDEncodedLiteralOffset32(), hasPackedD16(), and isNotGFX10Plus().

◆ isClobberedInFunction()

bool llvm::AMDGPU::isClobberedInFunction	(	const LoadInst *	Load,
		MemorySSA *	MSSA,
		AAResults *	AA
	)

Check is a Load is clobbered in its function.

Definition at line 326 of file AMDGPUMemoryUtils.cpp.

References llvm::dbgs(), llvm::MemoryLocation::get(), llvm::MemorySSAWalker::getClobberingMemoryAccess(), llvm::MemorySSA::getWalker(), llvm::SmallSet< T, N, C >::insert(), llvm::MemorySSA::isLiveOnEntryDef(), isReallyAClobber(), and LLVM_DEBUG.

◆ isCompute()

LLVM_READNONE bool llvm::AMDGPU::isCompute ( CallingConv::ID cc )

Definition at line 2010 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, and isGraphics().

Referenced by EmitPALMetadataCommon(), llvm::SIProgramInfo::getPGMRSrc1(), llvm::SIProgramInfo::getPGMRSrc2(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().

◆ isCvt_F32_Fp8_Bf8_e64()

LLVM_READNONE bool llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64 ( unsigned Opc )

Definition at line 586 of file AMDGPUBaseInfo.cpp.

◆ isDPALU_DPP()

bool llvm::AMDGPU::isDPALU_DPP ( const MCInstrDesc & OpDesc )

Returns: true if an instruction is a DP ALU DPP.

Definition at line 2967 of file AMDGPUBaseInfo.cpp.

References hasAny64BitVGPROperands().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ isDwordAligned()

static bool llvm::AMDGPU::isDwordAligned ( uint64_t ByteOffset )

static

Definition at line 2842 of file AMDGPUBaseInfo.cpp.

Referenced by convertSMRDOffsetUnits(), getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().

◆ isDynamicLDS()

bool llvm::AMDGPU::isDynamicLDS ( const GlobalVariable & GV )

Definition at line 35 of file AMDGPUMemoryUtils.cpp.

References DL, llvm::GlobalValue::getParent(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), llvm::GlobalValue::getValueType(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced by getTransitiveUsesOfLDS(), and isLDSVariableToLower().

◆ isEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC ( CallingConv::ID CC )

◆ isExtendedGlobalAddrSpace()

bool llvm::AMDGPU::isExtendedGlobalAddrSpace ( unsigned AS )

inline

Definition at line 465 of file AMDGPU.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), llvm::AMDGPURegisterBankInfo::applyMappingLoad(), llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace(), and llvm::SITargetLowering::shouldExpandAtomicRMWInIR().

◆ isFlatGlobalAddrSpace()

bool llvm::AMDGPU::isFlatGlobalAddrSpace ( unsigned AS )

inline

Definition at line 458 of file AMDGPU.h.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::SITargetLowering::shouldExpandAtomicRMWInIR(), and llvm::GCNTTIImpl::shouldPrefetchAddressSpace().

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding ( const MCSubtargetInfo & STI )

Definition at line 2174 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by hasSMEMByteOffset().

◆ isGenericAtomic()

LLVM_READNONE bool llvm::AMDGPU::isGenericAtomic ( unsigned Opc )

Definition at line 597 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity().

◆ isGFX10()

bool llvm::AMDGPU::isGFX10 ( const MCSubtargetInfo & STI )

Definition at line 2134 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by getGcnBufferFormatInfo(), getNumFlatOffsetBits(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName(), llvm::AMDGPUDisassembler::isGFX10(), isGFX10_GFX11(), isGFX10Before1030(), isGFX10Plus(), isGFX8_GFX9_GFX10(), isGFX9_GFX10(), isGFX9_GFX10_GFX11(), and llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat().

◆ isGFX10_3_GFX11()

bool llvm::AMDGPU::isGFX10_3_GFX11 ( const MCSubtargetInfo & STI )

Definition at line 2190 of file AMDGPUBaseInfo.cpp.

References isGFX10_BEncoding(), and isGFX12Plus().

◆ isGFX10_AEncoding()

bool llvm::AMDGPU::isGFX10_AEncoding ( const MCSubtargetInfo & STI )

Definition at line 2178 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ isGFX10_BEncoding()

bool llvm::AMDGPU::isGFX10_BEncoding ( const MCSubtargetInfo & STI )

Definition at line 2182 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by isGFX10_3_GFX11(), and isGFX10Before1030().

◆ isGFX10_GFX11()

bool llvm::AMDGPU::isGFX10_GFX11 ( const MCSubtargetInfo & STI )

Definition at line 2138 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11().

◆ isGFX10Before1030()

bool llvm::AMDGPU::isGFX10Before1030 ( const MCSubtargetInfo & STI )

Definition at line 2170 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX10_BEncoding().

◆ isGFX10Plus()

bool llvm::AMDGPU::isGFX10Plus ( const MCSubtargetInfo & STI )

Definition at line 2142 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX11Plus().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), generateEndPgm(), llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), hasSMEMByteOffset(), llvm::GCNSubtarget::initializeSubtargetDependencies(), llvm::AMDGPUDisassembler::isGFX10Plus(), isGFX9Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding(), and llvm::AMDGPU::AMDGPUMCKernelCodeT::validate().

◆ isGFX11()

bool llvm::AMDGPU::isGFX11 ( const MCSubtargetInfo & STI )

Definition at line 2146 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by isGFX10_GFX11(), isGFX11Plus(), isGFX9_GFX10_GFX11(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().

◆ isGFX11Plus()

bool llvm::AMDGPU::isGFX11Plus ( const MCSubtargetInfo & STI )

◆ isGFX12()

bool llvm::AMDGPU::isGFX12 ( const MCSubtargetInfo & STI )

Definition at line 2154 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by getNumFlatOffsetBits(), and isGFX12Plus().

◆ isGFX12Plus()

bool llvm::AMDGPU::isGFX12Plus ( const MCSubtargetInfo & STI )

Definition at line 2158 of file AMDGPUBaseInfo.cpp.

References isGFX12().

Referenced by llvm::SIInstrInfo::allowNegativeFlatOffset(), getSMRDEncodedOffset(), isGFX10_3_GFX11(), isGFX11Plus(), llvm::AMDGPUDisassembler::isGFX12Plus(), isLegalSMRDEncodedSignedOffset(), isLegalSMRDEncodedUnsignedOffset(), isNotGFX12Plus(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), and llvm::AMDGPU::AMDGPUMCKernelCodeT::validate().

◆ isGFX8_GFX9_GFX10()

bool llvm::AMDGPU::isGFX8_GFX9_GFX10 ( const MCSubtargetInfo & STI )

Definition at line 2120 of file AMDGPUBaseInfo.cpp.

References isGFX10(), isGFX9(), and isVI().

◆ isGFX8Plus()

bool llvm::AMDGPU::isGFX8Plus ( const MCSubtargetInfo & STI )

Definition at line 2124 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus(), and isVI().

◆ isGFX9()

bool llvm::AMDGPU::isGFX9 ( const MCSubtargetInfo & STI )

Definition at line 2108 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), llvm::AMDGPUDisassembler::isGFX9(), isGFX9_GFX10(), isGFX9_GFX10_GFX11(), isGFX9Plus(), and isNotGFX10Plus().

◆ isGFX90A()

bool llvm::AMDGPU::isGFX90A ( const MCSubtargetInfo & STI )

Definition at line 2194 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), and llvm::AMDGPU::IsaInfo::getMaxWavesPerEU().

◆ isGFX940()

bool llvm::AMDGPU::isGFX940 ( const MCSubtargetInfo & STI )

Definition at line 2198 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

◆ isGFX9_GFX10()

bool llvm::AMDGPU::isGFX9_GFX10 ( const MCSubtargetInfo & STI )

Definition at line 2112 of file AMDGPUBaseInfo.cpp.

References isGFX10(), and isGFX9().

◆ isGFX9_GFX10_GFX11()

bool llvm::AMDGPU::isGFX9_GFX10_GFX11 ( const MCSubtargetInfo & STI )

Definition at line 2116 of file AMDGPUBaseInfo.cpp.

References isGFX10(), isGFX11(), and isGFX9().

◆ isGFX9Plus()

bool llvm::AMDGPU::isGFX9Plus ( const MCSubtargetInfo & STI )

Definition at line 2128 of file AMDGPUBaseInfo.cpp.

References isGFX10Plus(), and isGFX9().

Referenced by hasSMRDSignedImmOffset(), isGFX8Plus(), llvm::AMDGPUDisassembler::isGFX9Plus(), and isNotGFX9Plus().

◆ isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment ( const GlobalValue * GV )

Definition at line 1277 of file AMDGPUBaseInfo.cpp.

References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::GLOBAL_ADDRESS.

◆ isGraphics()

LLVM_READNONE bool llvm::AMDGPU::isGraphics ( CallingConv::ID cc )

Definition at line 2006 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, and isShader().

Referenced by llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), isCompute(), llvm::SIInstrInfo::legalizeOperands(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ isGroupSegment()

bool llvm::AMDGPU::isGroupSegment ( const GlobalValue * GV )

Definition at line 1273 of file AMDGPUBaseInfo.cpp.

References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

◆ isHi16Reg()

bool llvm::AMDGPU::isHi16Reg	(	MCRegister	Reg,
		const MCRegisterInfo &	MRI
	)

Returns: if Reg occupies the high 16-bits of a 32-bit register.

Definition at line 2236 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::HWEncoding::IS_HI16, MRI, and Reg.

Referenced by llvm::SIInstrInfo::copyPhysReg(), cvtVOP3DstOpSelOnly(), and llvm::SIRegisterInfo::SIRegisterInfo().

◆ isHsaAbi()

bool llvm::AMDGPU::isHsaAbi ( const MCSubtargetInfo & STI )

Returns: True if STI is AMDHSA.

Definition at line 169 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, llvm::Triple::getOS(), and llvm::MCSubtargetInfo::getTargetTriple().

◆ isInlinableIntLiteral()

LLVM_READNONE bool llvm::AMDGPU::isInlinableIntLiteral ( int64_t Literal )

inline

Is this literal inlinable, and not one of the values intended for floating point values.

Definition at line 1414 of file AMDGPUBaseInfo.h.

References llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintVal(), clearUnusedBits(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isInlinableLiteral32(), isInlinableLiteral64(), isInlinableLiteralBF16(), isInlinableLiteralFP16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::AMDGPUAsmPrinter::PrintAsmOperand().

◆ isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32	(	int32_t	Literal,
		bool	HasInv2Pi
	)

Definition at line 2564 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::SIRegisterInfo::eliminateFrameIndex(), isInlinableLiteralI16(), isInlineableLiteralOp16(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64	(	int64_t	Literal,
		bool	HasInv2Pi
	)

Is this literal inlinable.

Definition at line 2547 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isOperandLegal().

◆ isInlinableLiteralBF16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralBF16	(	int16_t	Literal,
		bool	HasInv2Pi
	)

Definition at line 2590 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), isInlineableLiteralOp16(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralFP16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralFP16	(	int16_t	Literal,
		bool	HasInv2Pi
	)

Definition at line 2611 of file AMDGPUBaseInfo.cpp.

References isInlinableIntLiteral(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), isInlineableLiteralOp16(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralI16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralI16	(	int32_t	Literal,
		bool	HasInv2Pi
	)

Definition at line 2607 of file AMDGPUBaseInfo.cpp.

References isInlinableLiteral32(), and llvm::Literal.

Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216	(	uint32_t	Literal,
		uint8_t	OpType
	)

Definition at line 2722 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV216(), isInlinableLiteralV2BF16(), llvm::Literal, llvm_unreachable, OPERAND_REG_IMM_V2BF16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2INT16, OPERAND_REG_INLINE_AC_V2BF16, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_V2BF16, OPERAND_REG_INLINE_C_V2FP16, and OPERAND_REG_INLINE_C_V2INT16.

◆ isInlinableLiteralV2BF16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2BF16 ( uint32_t Literal )

Definition at line 2747 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2BF16(), and llvm::Literal.

Referenced by isInlinableLiteralV216(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV2F16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2F16 ( uint32_t Literal )

Definition at line 2752 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2F16(), and llvm::Literal.

Referenced by llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV2I16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2I16 ( uint32_t Literal )

Definition at line 2742 of file AMDGPUBaseInfo.cpp.

References getInlineEncodingV2I16(), and llvm::Literal.

Referenced by llvm::SIInstrInfo::isInlineConstant().

◆ isInlineValue()

LLVM_READNONE bool llvm::AMDGPU::isInlineValue ( unsigned Reg )

Definition at line 2317 of file AMDGPUBaseInfo.cpp.

References Reg.

◆ isIntrinsicAlwaysUniform()

bool llvm::AMDGPU::isIntrinsicAlwaysUniform ( unsigned IntrID )

Returns: true if the intrinsic is uniform

Definition at line 2928 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity(), llvm::GCNTTIImpl::isAlwaysUniform(), and llvm::AMDGPUTargetLowering::isSDNodeAlwaysUniform().

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence ( unsigned IntrID )

Returns: true if the intrinsic is divergent

Definition at line 2924 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().

◆ isInvalidSingleUseConsumerInst()

LLVM_READONLY bool llvm::AMDGPU::isInvalidSingleUseConsumerInst ( unsigned Opc )

Definition at line 622 of file AMDGPUBaseInfo.cpp.

References Info.

◆ isInvalidSingleUseProducerInst()

LLVM_READONLY bool llvm::AMDGPU::isInvalidSingleUseProducerInst ( unsigned Opc )

Definition at line 627 of file AMDGPUBaseInfo.cpp.

References Info.

◆ isKernel()

LLVM_READNONE bool llvm::AMDGPU::isKernel ( CallingConv::ID CC )

inline

Definition at line 1257 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_KERNEL, CC, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), isKernelLDS(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), and llvm::SITargetLowering::LowerReturn().

◆ isKernelCC()

bool llvm::AMDGPU::isKernelCC ( const Function * Func )

Definition at line 2050 of file AMDGPUBaseInfo.cpp.

References isModuleEntryFunctionCC().

◆ isKernelLDS()

bool llvm::AMDGPU::isKernelLDS ( const Function * F )

Definition at line 106 of file AMDGPUMemoryUtils.cpp.

References F, and isKernel().

Referenced by getTransitiveUsesOfLDS(), getUsesOfLDSByFunction(), and removeFnAttrFromReachable().

◆ isKImmOperand()

bool llvm::AMDGPU::isKImmOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Is this a KImm operand?

Definition at line 2353 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_KIMM_FIRST, and OPERAND_KIMM_LAST.

◆ isLDSVariableToLower()

bool llvm::AMDGPU::isLDSVariableToLower ( const GlobalVariable & GV )

Definition at line 44 of file AMDGPUMemoryUtils.cpp.

References llvm::GlobalVariable::getInitializer(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), llvm::GlobalVariable::hasInitializer(), llvm::GlobalVariable::isConstant(), isDynamicLDS(), and llvm::AMDGPUAS::LOCAL_ADDRESS.

Referenced by eliminateConstantExprUsesOfLDSFromAllInstructions(), and getUsesOfLDSByFunction().

◆ isLegalDPALU_DPPControl()

LLVM_READNONE bool llvm::AMDGPU::isLegalDPALU_DPPControl ( unsigned DC )

inline

Definition at line 1505 of file AMDGPUBaseInfo.h.

References llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, and llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST.

Referenced by llvm::SIInstrInfo::expandMovDPP64(), and llvm::SIInstrInfo::verifyInstruction().

◆ isLegalSMRDEncodedSignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	EncodedOffset,
		bool	IsBuffer
	)

Definition at line 2831 of file AMDGPUBaseInfo.cpp.

References hasSMRDSignedImmOffset(), and isGFX12Plus().

◆ isLegalSMRDEncodedUnsignedOffset()

LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset	(	const MCSubtargetInfo &	ST,
		int64_t	EncodedOffset
	)

Definition at line 2822 of file AMDGPUBaseInfo.cpp.

References hasSMEMByteOffset(), and isGFX12Plus().

Referenced by getSMRDEncodedOffset().

◆ isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset	(	const MCSubtargetInfo &	ST,
		int64_t	ByteOffset
	)

Returns: true if this offset is small enough to fit in the SMRD offset field. ByteOffset should be the offset in bytes and not the encoded offset.

◆ isMAC()

LLVM_READNONE bool llvm::AMDGPU::isMAC ( unsigned Opc )

Definition at line 552 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ isModuleEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isModuleEntryFunctionCC ( CallingConv::ID CC )

Definition at line 2031 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, CC, isChainCC(), and isEntryFunctionCC().

Referenced by isKernelCC().

◆ isNotGFX10Plus()

bool llvm::AMDGPU::isNotGFX10Plus ( const MCSubtargetInfo & STI )

Definition at line 2166 of file AMDGPUBaseInfo.cpp.

References isCI(), isGFX9(), isSI(), and isVI().

◆ isNotGFX11Plus()

bool llvm::AMDGPU::isNotGFX11Plus ( const MCSubtargetInfo & STI )

Definition at line 2162 of file AMDGPUBaseInfo.cpp.

References isGFX11Plus().

◆ isNotGFX12Plus()

bool llvm::AMDGPU::isNotGFX12Plus ( const MCSubtargetInfo & STI )

Definition at line 2160 of file AMDGPUBaseInfo.cpp.

References isGFX12Plus().

◆ isNotGFX9Plus()

bool llvm::AMDGPU::isNotGFX9Plus ( const MCSubtargetInfo & STI )

Definition at line 2132 of file AMDGPUBaseInfo.cpp.

References isGFX9Plus().

◆ isPermlane16()

LLVM_READNONE bool llvm::AMDGPU::isPermlane16 ( unsigned Opc )

Definition at line 575 of file AMDGPUBaseInfo.cpp.

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue * GV )

Definition at line 1281 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, and llvm::GlobalValue::getAddressSpace().

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

◆ isReallyAClobber()

bool llvm::AMDGPU::isReallyAClobber	(	const Value *	Ptr,
		MemoryDef *	Def,
		AAResults *	AA
	)

Given a Def clobbering a load from Ptr according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.

Definition at line 285 of file AMDGPUMemoryUtils.cpp.

References I, II, llvm::AAResults::isNoAlias(), and Ptr.

Referenced by isClobberedInFunction().

◆ isSGPR()

bool llvm::AMDGPU::isSGPR	(	unsigned	Reg,
		const MCRegisterInfo *	TRI
	)

Is Reg - scalar register.

Definition at line 2229 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), Reg, and TRI.

◆ isShader()

LLVM_READNONE bool llvm::AMDGPU::isShader ( CallingConv::ID cc )

Definition at line 1989 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, and llvm::CallingConv::AMDGPU_VS.

Referenced by llvm::SIModeRegisterDefaults::getDefaultForCallingConv(), isGraphics(), llvm::GCNSubtarget::isMesaGfxShader(), llvm::AMDGPUSubtarget::isMesaKernel(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::SITargetLowering::LowerReturn(), and reservePrivateMemoryRegs().

◆ isSI()

bool llvm::AMDGPU::isSI ( const MCSubtargetInfo & STI )

Definition at line 2096 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), hasPackedD16(), and isNotGFX10Plus().

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Is this floating-point operand?

Definition at line 2360 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2FP16, and OPERAND_REG_INLINE_C_V2FP32.

◆ isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Does this operand support only inlinable literals?

Definition at line 2386 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_REG_INLINE_AC_FIRST, OPERAND_REG_INLINE_AC_LAST, OPERAND_REG_INLINE_C_FIRST, and OPERAND_REG_INLINE_C_LAST.

◆ isSISrcOperand()

bool llvm::AMDGPU::isSISrcOperand	(	const MCInstrDesc &	Desc,
		unsigned	OpNo
	)

Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).

Definition at line 2346 of file AMDGPUBaseInfo.cpp.

References assert(), OPERAND_SRC_FIRST, and OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and llvm::SIInstrInfo::isOperandLegal().

◆ isSymbolicCustomOperandEncoding()

static bool llvm::AMDGPU::isSymbolicCustomOperandEncoding	(	const CustomOperandVal *	Opr,
		int	Size,
		unsigned	Code,
		bool &	HasNonDefaultVal,
		const MCSubtargetInfo &	STI
	)

static

Definition at line 1562 of file AMDGPUBaseInfo.cpp.

References Idx, and Size.

Referenced by llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding().

◆ isTrue16Inst()

LLVM_READONLY bool llvm::AMDGPU::isTrue16Inst ( unsigned Opc )

Definition at line 617 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by llvm::SIInstrInfo::moveToVALUImpl().

◆ isValid32BitLiteral()

LLVM_READNONE bool llvm::AMDGPU::isValid32BitLiteral	(	uint64_t	Val,
		bool	IsFP64
	)

Definition at line 2756 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::isOperandLegal(), and llvm::AMDGPUDAGToDAGISel::Select().

◆ isVI()

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo & STI )

Definition at line 2104 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::hasFeature().

Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), isGFX8Plus(), and isNotGFX10Plus().

◆ isVOPC64DPP()

LLVM_READONLY bool llvm::AMDGPU::isVOPC64DPP ( unsigned Opc )

Definition at line 512 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPUDisassembler::getInstruction().

◆ isVOPCAsmOnly()

LLVM_READONLY bool llvm::AMDGPU::isVOPCAsmOnly ( unsigned Opc )

Definition at line 516 of file AMDGPUBaseInfo.cpp.

◆ isVOPD()

LLVM_READONLY bool llvm::AMDGPU::isVOPD ( unsigned Opc )

Definition at line 548 of file AMDGPUBaseInfo.cpp.

References hasNamedOperand().

Referenced by getSrcOperandIndices().

◆ lookupD16ImageDimIntrinsic()

const D16ImageDimIntrinsic * llvm::AMDGPU::lookupD16ImageDimIntrinsic ( unsigned Intr )

◆ lookupRsrcIntrinsic()

const RsrcIntrinsic * llvm::AMDGPU::lookupRsrcIntrinsic ( unsigned Intr )

Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::SITargetLowering::getTgtMemIntrinsic().

◆ mapWMMA2AddrTo3AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode ( unsigned Opc )

Definition at line 632 of file AMDGPUBaseInfo.cpp.

References Info.

Referenced by llvm::SIInstrInfo::convertToThreeAddress().

◆ mapWMMA3AddrTo2AddrOpcode()

LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode ( unsigned Opc )

Definition at line 637 of file AMDGPUBaseInfo.cpp.

References Info.

◆ maskShiftGet()

const MCExpr * llvm::AMDGPU::maskShiftGet	(	const MCExpr *	Val,
		uint32_t	Mask,
		uint32_t	Shift,
		MCContext &	Ctx
	)

inline

Provided with the MCExpr * Val, uint32 Mask and Shift, will return the right shifted and masked, in said order of operations, MCExpr * created within the MCContext Ctx.

For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr

will be the equivalent of (Val >> 6) & 0xf

Definition at line 63 of file SIDefinesUtils.h.

References llvm::MCConstantExpr::create(), llvm::MCBinaryExpr::createAnd(), and llvm::MCBinaryExpr::createLShr().

◆ maskShiftSet()

const MCExpr * llvm::AMDGPU::maskShiftSet	(	const MCExpr *	Val,
		uint32_t	Mask,
		uint32_t	Shift,
		MCContext &	Ctx
	)

inline

Provided with the MCExpr * Val, uint32 Mask and Shift, will return the masked and left shifted, in said order of operations, MCExpr * created within the MCContext Ctx.

For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr