LLVM  9.0.0svn
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llvm::AMDGPU Namespace Reference

Namespaces

 DPP
 
 EncValues
 
 HSAMD
 
 Hwreg
 
 IsaInfo
 
 PALMD
 
 SDWA
 
 SendMsg
 
 Swizzle
 
 VGPRIndexMode
 

Classes

struct  D16ImageDimIntrinsic
 
struct  ImageDimIntrinsicInfo
 
struct  IsaVersion
 Instruction set architecture version. More...
 
struct  MIMGBaseOpcodeInfo
 
struct  MIMGDimInfo
 
struct  MIMGInfo
 
struct  MIMGLZMappingInfo
 
struct  MIMGMIPMappingInfo
 
struct  MUBUFInfo
 
struct  RsrcIntrinsic
 
struct  SIModeRegisterDefaults
 
struct  Waitcnt
 Represents the counter values to wait for in an s_waitcnt instruction. More...
 

Enumerations

enum  GPUKind : uint32_t {
  GK_NONE = 0, GK_R600 = 1, GK_R630 = 2, GK_RS880 = 3,
  GK_RV670 = 4, GK_RV710 = 5, GK_RV730 = 6, GK_RV770 = 7,
  GK_CEDAR = 8, GK_CYPRESS = 9, GK_JUNIPER = 10, GK_REDWOOD = 11,
  GK_SUMO = 12, GK_BARTS = 13, GK_CAICOS = 14, GK_CAYMAN = 15,
  GK_TURKS = 16, GK_R600_FIRST = GK_R600, GK_R600_LAST = GK_TURKS, GK_GFX600 = 32,
  GK_GFX601 = 33, GK_GFX700 = 40, GK_GFX701 = 41, GK_GFX702 = 42,
  GK_GFX703 = 43, GK_GFX704 = 44, GK_GFX801 = 50, GK_GFX802 = 51,
  GK_GFX803 = 52, GK_GFX810 = 53, GK_GFX900 = 60, GK_GFX902 = 61,
  GK_GFX904 = 62, GK_GFX906 = 63, GK_GFX908 = 64, GK_GFX909 = 65,
  GK_GFX1010 = 71, GK_GFX1011 = 72, GK_GFX1012 = 73, GK_AMDGCN_FIRST = GK_GFX600,
  GK_AMDGCN_LAST = GK_GFX1012
}
 GPU kinds supported by the AMDGPU target. More...
 
enum  ArchFeatureKind : uint32_t {
  FEATURE_NONE = 0, FEATURE_FMA = 1 << 1, FEATURE_LDEXP = 1 << 2, FEATURE_FP64 = 1 << 3,
  FEATURE_FAST_FMA_F32 = 1 << 4, FEATURE_FAST_DENORMAL_F32 = 1 << 5
}
 
enum  TargetIndex {
  TI_CONSTDATA_START, TI_SCRATCH_RSRC_DWORD0, TI_SCRATCH_RSRC_DWORD1, TI_SCRATCH_RSRC_DWORD2,
  TI_SCRATCH_RSRC_DWORD3
}
 
enum  Fixups { fixup_si_sopp_br = FirstTargetFixupKind, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
 
enum  OperandType : unsigned {
  OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_FP32,
  OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2INT16,
  OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_FP16,
  OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2INT16,
  OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32,
  OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2INT16,
  OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2INT16,
  OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, OPERAND_INPUT_MODS, OPERAND_SDWA_VOPC_DST,
  OPERAND_KIMM32, OPERAND_KIMM16
}
 

Functions

StringRef getArchNameAMDGCN (GPUKind AK)
 
StringRef getArchNameR600 (GPUKind AK)
 
StringRef getCanonicalArchName (StringRef Arch)
 
GPUKind parseArchAMDGCN (StringRef CPU)
 
GPUKind parseArchR600 (StringRef CPU)
 
unsigned getArchAttrAMDGCN (GPUKind AK)
 
unsigned getArchAttrR600 (GPUKind AK)
 
void fillValidArchListAMDGCN (SmallVectorImpl< StringRef > &Values)
 
void fillValidArchListR600 (SmallVectorImpl< StringRef > &Values)
 
IsaVersion getIsaVersion (StringRef GPU)
 
const RsrcIntrinsic * lookupRsrcIntrinsic (unsigned Intr)
 
const D16ImageDimIntrinsic * lookupD16ImageDimIntrinsic (unsigned Intr)
 
const ImageDimIntrinsicInfo * getImageDimIntrinsicInfo (unsigned Intr)
 
LLVM_READONLY int getVOPe64 (uint16_t Opcode)
 
LLVM_READONLY int getVOPe32 (uint16_t Opcode)
 
LLVM_READONLY int getSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getDPPOp32 (uint16_t Opcode)
 
LLVM_READONLY int getBasicFromSDWAOp (uint16_t Opcode)
 
LLVM_READONLY int getCommuteRev (uint16_t Opcode)
 
LLVM_READONLY int getCommuteOrig (uint16_t Opcode)
 
LLVM_READONLY int getAddr64Inst (uint16_t Opcode)
 
LLVM_READONLY int getIfAddr64Inst (uint16_t Opcode)
 Check if Opcode is an Addr64 opcode. More...
 
LLVM_READONLY int getMUBUFNoLdsInst (uint16_t Opcode)
 
LLVM_READONLY int getAtomicRetOp (uint16_t Opcode)
 
LLVM_READONLY int getAtomicNoRetOp (uint16_t Opcode)
 
LLVM_READONLY int getSOPKOp (uint16_t Opcode)
 
LLVM_READONLY int getGlobalSaddrOp (uint16_t Opcode)
 
LLVM_READONLY int getVCMPXNoSDstOp (uint16_t Opcode)
 
int getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
 
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode (unsigned Opc)
 
int getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
 
int getMUBUFBaseOpcode (unsigned Opc)
 
int getMUBUFOpcode (unsigned BaseOpc, unsigned Dwords)
 
int getMUBUFDwords (unsigned Opc)
 
bool getMUBUFHasVAddr (unsigned Opc)
 
bool getMUBUFHasSrsrc (unsigned Opc)
 
bool getMUBUFHasSoffset (unsigned Opc)
 
int getMCOpcode (uint16_t Opcode, unsigned Gen)
 
void initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
 
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor (const MCSubtargetInfo *STI)
 
bool isGroupSegment (const GlobalValue *GV)
 
bool isGlobalSegment (const GlobalValue *GV)
 
bool isReadOnlySegment (const GlobalValue *GV)
 
bool shouldEmitConstantsToTextSection (const Triple &TT)
 
int getIntegerAttribute (const Function &F, StringRef Name, int Default)
 
std::pair< int, int > getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned getVmcntBitMask (const IsaVersion &Version)
 
unsigned getExpcntBitMask (const IsaVersion &Version)
 
unsigned getLgkmcntBitMask (const IsaVersion &Version)
 
unsigned getWaitcntBitMask (const IsaVersion &Version)
 
unsigned decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
void decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively. More...
 
Waitcnt decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
 
unsigned encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version. More...
 
unsigned encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
 
unsigned getInitialPSInputAddr (const Function &F)
 
bool isShader (CallingConv::ID cc)
 
bool isCompute (CallingConv::ID cc)
 
bool isEntryFunctionCC (CallingConv::ID CC)
 
bool hasXNACK (const MCSubtargetInfo &STI)
 
bool hasSRAMECC (const MCSubtargetInfo &STI)
 
bool hasMIMG_R128 (const MCSubtargetInfo &STI)
 
bool hasPackedD16 (const MCSubtargetInfo &STI)
 
bool isSI (const MCSubtargetInfo &STI)
 
bool isCI (const MCSubtargetInfo &STI)
 
bool isVI (const MCSubtargetInfo &STI)
 
bool isGFX9 (const MCSubtargetInfo &STI)
 
bool isGFX10 (const MCSubtargetInfo &STI)
 
bool isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register. More...
 
bool isRegIntersect (unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
 Is there any intersection between registers. More...
 
unsigned getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg. More...
 
unsigned mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register. More...
 
bool isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Can this operand also contain immediate values? More...
 
bool isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand? More...
 
bool isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this opearnd support only inlinable literals? More...
 
unsigned getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC. More...
 
unsigned getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand. More...
 
bool isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable. More...
 
bool isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool isArgPassedInSGPR (const Argument *A)
 
static bool hasSMEMByteOffset (const MCSubtargetInfo &ST)
 
int64_t getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
bool splitMUBUFOffset (uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, uint32_t Align)
 
bool isIntrinsicSourceOfDivergence (unsigned IntrID)
 
LLVM_READONLY int16_t getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx)
 
LLVM_READONLY int getSOPPWithRelaxation (uint16_t Opcode)
 
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo (unsigned BaseOpcode)
 
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo (unsigned DimEnum)
 
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding (uint8_t DimEnc)
 
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix)
 
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo (unsigned L)
 
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo (unsigned L)
 
LLVM_READONLY const MIMGInfo * getMIMGInfo (unsigned Opc)
 
LLVM_READNONE bool isKernel (CallingConv::ID CC)
 
LLVM_READNONE unsigned getOperandSize (const MCOperandInfo &OpInfo)
 
LLVM_READNONE unsigned getOperandSize (const MCInstrDesc &Desc, unsigned OpNo)
 

Variables

const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL
 
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)
 
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21)
 
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)
 

Enumeration Type Documentation

◆ ArchFeatureKind

enum llvm::AMDGPU::ArchFeatureKind : uint32_t
Enumerator
FEATURE_NONE 
FEATURE_FMA 
FEATURE_LDEXP 
FEATURE_FP64 
FEATURE_FAST_FMA_F32 
FEATURE_FAST_DENORMAL_F32 

Definition at line 144 of file TargetParser.h.

◆ Fixups

enum llvm::AMDGPU::Fixups
Enumerator
fixup_si_sopp_br 

16-bit PC relative fixup for SOPP branch instructions.

LastTargetFixupKind 
NumTargetFixupKinds 

Definition at line 16 of file AMDGPUFixupKinds.h.

◆ GPUKind

enum llvm::AMDGPU::GPUKind : uint32_t

GPU kinds supported by the AMDGPU target.

Enumerator
GK_NONE 
GK_R600 
GK_R630 
GK_RS880 
GK_RV670 
GK_RV710 
GK_RV730 
GK_RV770 
GK_CEDAR 
GK_CYPRESS 
GK_JUNIPER 
GK_REDWOOD 
GK_SUMO 
GK_BARTS 
GK_CAICOS 
GK_CAYMAN 
GK_TURKS 
GK_R600_FIRST 
GK_R600_LAST 
GK_GFX600 
GK_GFX601 
GK_GFX700 
GK_GFX701 
GK_GFX702 
GK_GFX703 
GK_GFX704 
GK_GFX801 
GK_GFX802 
GK_GFX803 
GK_GFX810 
GK_GFX900 
GK_GFX902 
GK_GFX904 
GK_GFX906 
GK_GFX908 
GK_GFX909 
GK_GFX1010 
GK_GFX1011 
GK_GFX1012 
GK_AMDGCN_FIRST 
GK_AMDGCN_LAST 

Definition at line 80 of file TargetParser.h.

◆ OperandType

enum llvm::AMDGPU::OperandType : unsigned
Enumerator
OPERAND_REG_IMM_INT32 

Operands with register or 32-bit immediate.

OPERAND_REG_IMM_INT64 
OPERAND_REG_IMM_INT16 
OPERAND_REG_IMM_FP32 
OPERAND_REG_IMM_FP64 
OPERAND_REG_IMM_FP16 
OPERAND_REG_IMM_V2FP16 
OPERAND_REG_IMM_V2INT16 
OPERAND_REG_INLINE_C_INT16 

Operands with register or inline constant.

OPERAND_REG_INLINE_C_INT32 
OPERAND_REG_INLINE_C_INT64 
OPERAND_REG_INLINE_C_FP16 
OPERAND_REG_INLINE_C_FP32 
OPERAND_REG_INLINE_C_FP64 
OPERAND_REG_INLINE_C_V2FP16 
OPERAND_REG_INLINE_C_V2INT16 
OPERAND_REG_INLINE_AC_INT16 

Operands with an AccVGPR register or inline constant.

OPERAND_REG_INLINE_AC_INT32 
OPERAND_REG_INLINE_AC_FP16 
OPERAND_REG_INLINE_AC_FP32 
OPERAND_REG_INLINE_AC_V2FP16 
OPERAND_REG_INLINE_AC_V2INT16 
OPERAND_REG_IMM_FIRST 
OPERAND_REG_IMM_LAST 
OPERAND_REG_INLINE_C_FIRST 
OPERAND_REG_INLINE_C_LAST 
OPERAND_REG_INLINE_AC_FIRST 
OPERAND_REG_INLINE_AC_LAST 
OPERAND_SRC_FIRST 
OPERAND_SRC_LAST 
OPERAND_INPUT_MODS 
OPERAND_SDWA_VOPC_DST 
OPERAND_KIMM32 

Operand with 32-bit immediate that uses the constant bus.

OPERAND_KIMM16 

Definition at line 122 of file SIDefines.h.

◆ TargetIndex

enum llvm::AMDGPU::TargetIndex
Enumerator
TI_CONSTDATA_START 
TI_SCRATCH_RSRC_DWORD0 
TI_SCRATCH_RSRC_DWORD1 
TI_SCRATCH_RSRC_DWORD2 
TI_SCRATCH_RSRC_DWORD3 

Definition at line 243 of file AMDGPU.h.

Function Documentation

◆ decodeExpcnt()

unsigned llvm::AMDGPU::decodeExpcnt ( const IsaVersion &  Version,
unsigned  Waitcnt 
)
Returns
Decoded Expcnt from given Waitcnt for given isa Version.

Definition at line 598 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPU::Waitcnt::combined(), decodeWaitcnt(), and encodeCnt().

◆ decodeLgkmcnt()

unsigned llvm::AMDGPU::decodeLgkmcnt ( const IsaVersion &  Version,
unsigned  Waitcnt 
)
Returns
Decoded Lgkmcnt from given Waitcnt for given isa Version.

Definition at line 602 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by llvm::AMDGPU::Waitcnt::combined(), decodeWaitcnt(), and encodeCnt().

◆ decodeVmcnt()

unsigned llvm::AMDGPU::decodeVmcnt ( const IsaVersion &  Version,
unsigned  Waitcnt 
)
Returns
Decoded Vmcnt from given Waitcnt for given isa Version.

Definition at line 586 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by llvm::AMDGPU::Waitcnt::combined(), decodeWaitcnt(), and encodeCnt().

◆ decodeWaitcnt() [1/2]

void llvm::AMDGPU::decodeWaitcnt ( const IsaVersion &  Version,
unsigned  Waitcnt,
unsigned &  Vmcnt,
unsigned &  Expcnt,
unsigned &  Lgkmcnt 
)

Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.

Vmcnt, Expcnt and Lgkmcnt are decoded as follows: Vmcnt = Waitcnt[3:0] (pre-gfx9 only) Vmcnt = Waitcnt[3:0] | Waitcnt[15:14] (gfx9+ only) Expcnt = Waitcnt[6:4] Lgkmcnt = Waitcnt[11:8] (pre-gfx10 only) Lgkmcnt = Waitcnt[13:8] (gfx10+ only)

Definition at line 607 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), and decodeVmcnt().

Referenced by addRegsToSet(), callWaitsOnFunctionReturn(), llvm::AMDGPU::Waitcnt::combined(), and llvm::AMDGPUInstPrinter::printWaitFlag().

◆ decodeWaitcnt() [2/2]

Waitcnt llvm::AMDGPU::decodeWaitcnt ( const IsaVersion &  Version,
unsigned  Encoded 
)

Definition at line 614 of file AMDGPUBaseInfo.cpp.

References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LgkmCnt, and llvm::AMDGPU::Waitcnt::VmCnt.

◆ encodeExpcnt()

unsigned llvm::AMDGPU::encodeExpcnt ( const IsaVersion &  Version,
unsigned  Waitcnt,
unsigned  Expcnt 
)
Returns
Waitcnt with encoded Expcnt for given isa Version.

Definition at line 633 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::AMDGPU::Waitcnt::combined(), encodeCnt(), and encodeWaitcnt().

◆ encodeLgkmcnt()

unsigned llvm::AMDGPU::encodeLgkmcnt ( const IsaVersion &  Version,
unsigned  Waitcnt,
unsigned  Lgkmcnt 
)
Returns
Waitcnt with encoded Lgkmcnt for given isa Version.

Definition at line 638 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by llvm::AMDGPU::Waitcnt::combined(), encodeCnt(), and encodeWaitcnt().

◆ encodeVmcnt()

unsigned llvm::AMDGPU::encodeVmcnt ( const IsaVersion &  Version,
unsigned  Waitcnt,
unsigned  Vmcnt 
)
Returns
Waitcnt with encoded Vmcnt for given isa Version.

Definition at line 622 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by llvm::AMDGPU::Waitcnt::combined(), encodeCnt(), and encodeWaitcnt().

◆ encodeWaitcnt() [1/2]

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion &  Version,
unsigned  Vmcnt,
unsigned  Expcnt,
unsigned  Lgkmcnt 
)

Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.

Vmcnt, Expcnt and Lgkmcnt are encoded as follows: Waitcnt[3:0] = Vmcnt (pre-gfx9 only) Waitcnt[3:0] = Vmcnt[3:0] (gfx9+ only) Waitcnt[6:4] = Expcnt Waitcnt[11:8] = Lgkmcnt (pre-gfx10 only) Waitcnt[13:8] = Lgkmcnt (gfx10+ only) Waitcnt[15:14] = Vmcnt[5:4] (gfx9+ only)

Returns
Waitcnt with encoded Vmcnt, Expcnt and Lgkmcnt for given isa Version.

Definition at line 644 of file AMDGPUBaseInfo.cpp.

References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), and getWaitcntBitMask().

Referenced by callWaitsOnFunctionReturn(), llvm::AMDGPU::Waitcnt::combined(), and encodeWaitcnt().

◆ encodeWaitcnt() [2/2]

unsigned llvm::AMDGPU::encodeWaitcnt ( const IsaVersion &  Version,
const Waitcnt &  Decoded 
)

Definition at line 653 of file AMDGPUBaseInfo.cpp.

References encodeWaitcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, llvm::AMDGPU::Waitcnt::LgkmCnt, and llvm::AMDGPU::Waitcnt::VmCnt.

◆ fillValidArchListAMDGCN()

void llvm::AMDGPU::fillValidArchListAMDGCN ( SmallVectorImpl< StringRef > &  Values)

Definition at line 164 of file TargetParser.cpp.

References C, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ fillValidArchListR600()

void llvm::AMDGPU::fillValidArchListR600 ( SmallVectorImpl< StringRef > &  Values)

Definition at line 170 of file TargetParser.cpp.

References C, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

◆ getAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getAddr64Inst ( uint16_t  Opcode)

Referenced by llvm::getRegSubRegPair(), and llvm::SIInstrInfo::legalizeOperands().

◆ getArchAttrAMDGCN()

unsigned llvm::AMDGPU::getArchAttrAMDGCN ( GPUKind  AK)

Definition at line 152 of file TargetParser.cpp.

References FEATURE_NONE.

◆ getArchAttrR600()

unsigned llvm::AMDGPU::getArchAttrR600 ( GPUKind  AK)

Definition at line 158 of file TargetParser.cpp.

References FEATURE_NONE.

◆ getArchNameAMDGCN()

StringRef llvm::AMDGPU::getArchNameAMDGCN ( GPUKind  AK)

Definition at line 122 of file TargetParser.cpp.

Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach().

◆ getArchNameR600()

StringRef llvm::AMDGPU::getArchNameR600 ( GPUKind  AK)

Definition at line 128 of file TargetParser.cpp.

Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach().

◆ getAtomicNoRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicNoRetOp ( uint16_t  Opcode)

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), callWaitsOnFunctionReturn(), llvm::getRegSubRegPair(), and isValidClauseInst().

◆ getAtomicRetOp()

LLVM_READONLY int llvm::AMDGPU::getAtomicRetOp ( uint16_t  Opcode)

Referenced by callWaitsOnFunctionReturn(), llvm::getRegSubRegPair(), and isValidClauseInst().

◆ getBasicFromSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp ( uint16_t  Opcode)

Referenced by llvm::getRegSubRegPair(), and llvm::SIInstrInfo::verifyInstruction().

◆ getCanonicalArchName()

StringRef llvm::AMDGPU::getCanonicalArchName ( StringRef  Arch)

◆ getCommuteOrig()

LLVM_READONLY int llvm::AMDGPU::getCommuteOrig ( uint16_t  Opcode)

Referenced by llvm::SIInstrInfo::commuteOpcode(), and llvm::getRegSubRegPair().

◆ getCommuteRev()

LLVM_READONLY int llvm::AMDGPU::getCommuteRev ( uint16_t  Opcode)

Referenced by llvm::SIInstrInfo::commuteOpcode(), and llvm::getRegSubRegPair().

◆ getDefaultAmdhsaKernelDescriptor()

amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor ( const MCSubtargetInfo *  STI)

Definition at line 470 of file AMDGPUBaseInfo.cpp.

References AMDHSA_BITS_SET, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), llvm::AMDGPU::IsaVersion::Major, and llvm::IndexedInstrProf::Version.

Referenced by IsRevOpcode().

◆ getDPPOp32()

LLVM_READONLY int llvm::AMDGPU::getDPPOp32 ( uint16_t  Opcode)

Referenced by getDPPOp(), and llvm::getRegSubRegPair().

◆ getExpcntBitMask()

unsigned llvm::AMDGPU::getExpcntBitMask ( const IsaVersion &  Version)
Returns
Expcnt bit mask for given isa Version.

Definition at line 565 of file AMDGPUBaseInfo.cpp.

Referenced by callWaitsOnFunctionReturn(), llvm::AMDGPU::Waitcnt::combined(), and llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getGlobalSaddrOp()

LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp ( uint16_t  Opcode)

Referenced by canMoveInstsAcrossMemOp(), fixupGlobalSaddr(), and llvm::getRegSubRegPair().

◆ getIfAddr64Inst()

LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst ( uint16_t  Opcode)

Check if Opcode is an Addr64 opcode.

Returns
Opcode if it is an Addr64 opcode, otherwise -1.

Referenced by llvm::getRegSubRegPair(), and llvm::SIInstrInfo::legalizeOperands().

◆ getImageDimIntrinsicInfo()

const ImageDimIntrinsicInfo* llvm::AMDGPU::getImageDimIntrinsicInfo ( unsigned  Intr)

◆ getInitialPSInputAddr()

unsigned llvm::AMDGPU::getInitialPSInputAddr ( const Function &  F)

Definition at line 832 of file AMDGPUBaseInfo.cpp.

References getIntegerAttribute().

Referenced by llvm::AMDGPU::Waitcnt::combined(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().

◆ getIntegerAttribute()

int llvm::AMDGPU::getIntegerAttribute ( const Function &  F,
StringRef  Name,
int  Default 
)
Returns
Integer value requested using F's Name attribute.
Default if attribute is not present.
Default and emits error if requested value cannot be converted to integer.

Definition at line 516 of file AMDGPUBaseInfo.cpp.

References llvm::LLVMContext::emitError(), llvm::StringRef::getAsInteger(), llvm::Function::getContext(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), and llvm::Attribute::isStringAttribute().

Referenced by llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), getInitialPSInputAddr(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), and getMopState().

◆ getIntegerPairAttribute()

std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute ( const Function &  F,
StringRef  Name,
std::pair< int, int >  Default,
bool  OnlyFirstRequired = false 
)
Returns
A pair of integer values requested using F's Name attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired is false).
Default if attribute is not present.
Default and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired is false and "second" value is not present.

Definition at line 531 of file AMDGPUBaseInfo.cpp.

References llvm::LLVMContext::emitError(), llvm::Function::getContext(), llvm::Function::getFnAttribute(), llvm::Attribute::getValueAsString(), llvm::Attribute::isStringAttribute(), and llvm::StringRef::split().

Referenced by llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().

◆ getIsaVersion()

AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion ( StringRef  GPU)

Definition at line 175 of file TargetParser.cpp.

References GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX600, GK_GFX601, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_NONE, and parseArchAMDGCN().

Referenced by addRegsToSet(), callWaitsOnFunctionReturn(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUAsmPrinter::EmitStartOfAsmFile(), encodeCnt(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), hasAnyNonFlatUseOfReg(), initDefaultAMDKernelCodeT(), IsRevOpcode(), llvm::AMDGPUInstPrinter::printWaitFlag(), and llvm::AMDGPU::IsaInfo::streamIsaVersion().

◆ getLgkmcntBitMask()

unsigned llvm::AMDGPU::getLgkmcntBitMask ( const IsaVersion &  Version)
Returns
Lgkmcnt bit mask for given isa Version.

Definition at line 569 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by callWaitsOnFunctionReturn(), llvm::AMDGPU::Waitcnt::combined(), and llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getMaskedMIMGOp()

LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp ( unsigned  Opc,
unsigned  NewChannels 
)

Definition at line 123 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGInfo(), llvm::AMDGPU::MIMGInfo::MIMGEncoding, llvm::AMDGPU::MIMGInfo::Opcode, and llvm::AMDGPU::MIMGInfo::VAddrDwords.

◆ getMCOpcode()

LLVM_READONLY int llvm::AMDGPU::getMCOpcode ( uint16_t  Opcode,
unsigned  Gen 
)

Definition at line 177 of file AMDGPUBaseInfo.cpp.

Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().

◆ getMCReg()

unsigned llvm::AMDGPU::getMCReg ( unsigned  Reg,
const MCSubtargetInfo &  STI 
)

If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.

Definition at line 974 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, and llvm::Triple::r600.

Referenced by llvm::AMDGPUDisassembler::createRegOperand(), getVariantKind(), and isKernel().

◆ getMIMGBaseOpcode()

const MIMGBaseOpcodeInfo* llvm::AMDGPU::getMIMGBaseOpcode ( unsigned  Opc)

Definition at line 118 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Info.

◆ getMIMGBaseOpcodeInfo()

LLVM_READONLY const MIMGBaseOpcodeInfo* llvm::AMDGPU::getMIMGBaseOpcodeInfo ( unsigned  BaseOpcode)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), getMIMGBaseOpcode(), parseTexFail(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGDimInfo()

LLVM_READONLY const MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfo ( unsigned  DimEnum)

Referenced by parseTexFail().

◆ getMIMGDimInfoByAsmSuffix()

LLVM_READONLY const MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfoByAsmSuffix ( StringRef  AsmSuffix)

Referenced by isRegOrImmWithInputMods().

◆ getMIMGDimInfoByEncoding()

LLVM_READONLY const MIMGDimInfo* llvm::AMDGPU::getMIMGDimInfoByEncoding ( uint8_t  DimEnc)

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUInstPrinter::printInst(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGInfo()

LLVM_READONLY const MIMGInfo* llvm::AMDGPU::getMIMGInfo ( unsigned  Opc)

Referenced by addRegsToSet(), llvm::AMDGPUDisassembler::convertMIMGInst(), getMaskedMIMGOp(), getMIMGBaseOpcode(), shrinkScalarCompare(), and llvm::SIInstrInfo::verifyInstruction().

◆ getMIMGLZMappingInfo()

LLVM_READONLY const MIMGLZMappingInfo* llvm::AMDGPU::getMIMGLZMappingInfo ( unsigned  L)

Referenced by parseTexFail().

◆ getMIMGMIPMappingInfo()

LLVM_READONLY const MIMGMIPMappingInfo* llvm::AMDGPU::getMIMGMIPMappingInfo ( unsigned  L)

Referenced by parseTexFail().

◆ getMIMGOpcode()

LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode ( unsigned  BaseOpcode,
unsigned  MIMGEncoding,
unsigned  VDataDwords,
unsigned  VAddrDwords 
)

Definition at line 111 of file AMDGPUBaseInfo.cpp.

References Info, and llvm::AMDGPU::MIMGInfo::Opcode.

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), parseTexFail(), and shrinkScalarCompare().

◆ getMUBUFBaseOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode ( unsigned  Opc)

Definition at line 144 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MUBUFInfo::BaseOpcode, and Info.

Referenced by canMoveInstsAcrossMemOp().

◆ getMUBUFDwords()

LLVM_READONLY int llvm::AMDGPU::getMUBUFDwords ( unsigned  Opc)

Definition at line 154 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MUBUFInfo::dwords, and Info.

Referenced by canMoveInstsAcrossMemOp().

◆ getMUBUFHasSoffset()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset ( unsigned  Opc)

Definition at line 169 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MUBUFInfo::has_soffset, and Info.

Referenced by canMoveInstsAcrossMemOp().

◆ getMUBUFHasSrsrc()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc ( unsigned  Opc)

Definition at line 164 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MUBUFInfo::has_srsrc, and Info.

Referenced by canMoveInstsAcrossMemOp().

◆ getMUBUFHasVAddr()

LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr ( unsigned  Opc)

Definition at line 159 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::MUBUFInfo::has_vaddr, and Info.

Referenced by canMoveInstsAcrossMemOp().

◆ getMUBUFNoLdsInst()

LLVM_READONLY int llvm::AMDGPU::getMUBUFNoLdsInst ( uint16_t  Opcode)

Referenced by encodeBitmaskPerm(), and llvm::getRegSubRegPair().

◆ getMUBUFOpcode()

LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode ( unsigned  BaseOpc,
unsigned  Dwords 
)

Definition at line 149 of file AMDGPUBaseInfo.cpp.

References Info, and llvm::AMDGPU::MUBUFInfo::Opcode.

Referenced by canMoveInstsAcrossMemOp().

◆ getNamedOperandIdx()

LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx ( uint16_t  Opcode,
uint16_t  NamedIdx 
)

Referenced by addRegsToSet(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), allOpsDefaultValue(), llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::buildShrunkInst(), callWaitsOnFunctionReturn(), canMoveInstsAcrossMemOp(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::createSIAddIMGInitPass(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::R600InstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::findCommutedOpIndices(), findSingleRegDef(), llvm::SIInstrInfo::FoldImmediate(), foldImmediates(), frameIndexMayFold(), getDPPOp(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::AMDGPUDisassembler::getInstruction(), llvm::SIInstrInfo::getInstSizeInBytes(), getLit64Encoding(), llvm::SIInstrInfo::getMemOperandWithOffset(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::R600InstrInfo::getOperandIdx(), llvm::SIInstrInfo::hasModifiers(), insertCSRRestores(), insertNamedMCOperand(), llvm::SIInstrInfo::isBufferSMRD(), isInlineConstantIfFolded(), isRegOrImmWithInputMods(), IsRevOpcode(), isSendMsgTraceDataOrGDS(), isValidDPP8(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), nodesHaveSameOperandValue(), llvm::AMDGPUInstPrinter::printRegOperand(), removeModOperands(), shrinkScalarCompare(), tryAddToFoldList(), tryConstantFoldOp(), tryFoldInst(), tryToFoldACImm(), updateOperand(), and llvm::SIInstrInfo::verifyInstruction().

◆ getOperandSize() [1/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCOperandInfo &  OpInfo)
inline

Definition at line 561 of file AMDGPUBaseInfo.h.

References LLVM_READNONE, llvm_unreachable, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2INT16, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2INT16, and llvm::MCOperandInfo::OperandType.

Referenced by getOperandSize().

◆ getOperandSize() [2/2]

LLVM_READNONE unsigned llvm::AMDGPU::getOperandSize ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)
inline

Definition at line 597 of file AMDGPUBaseInfo.h.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, Arg, getOperandSize(), getSMRDEncodedOffset(), isArgPassedInSGPR(), isInlinableLiteral16(), isInlinableLiteral32(), isInlinableLiteral64(), isInlinableLiteralV216(), isIntrinsicSourceOfDivergence(), isLegalSMRDImmOffset(), llvm::Literal, LLVM_READNONE, llvm::MCInstrDesc::OpInfo, splitMUBUFOffset(), and llvm::ARM_MB::ST.

◆ getRegBitWidth() [1/2]

unsigned llvm::AMDGPU::getRegBitWidth ( unsigned  RCID)

Get the size in bits of a register from the register class RC.

Definition at line 1034 of file AMDGPUBaseInfo.cpp.

References llvm_unreachable.

Referenced by addRegsToSet(), buildMUBUFOffsetLoadStore(), llvm::SIInstrInfo::canInsertSelect(), findSRegBaseAndIndex(), getRegBitWidth(), getRegOperandSize(), llvm::SIRegisterInfo::getRegSplitParts(), INITIALIZE_PASS(), isKernel(), llvm::BitTracker::MachineEvaluator::MachineEvaluator(), llvm::AMDGPUInstPrinter::printRegOperand(), and tryToFoldACImm().

◆ getRegBitWidth() [2/2]

unsigned llvm::AMDGPU::getRegBitWidth ( const MCRegisterClass &  RC)

Get the size in bits of a register from the register class RC.

Definition at line 1083 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::getID(), and getRegBitWidth().

◆ getRegOperandSize()

unsigned llvm::AMDGPU::getRegOperandSize ( const MCRegisterInfo *  MRI,
const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Get size of register operand.

Definition at line 1087 of file AMDGPUBaseInfo.cpp.

References assert(), getRegBitWidth(), llvm::MCRegisterInfo::getRegClass(), llvm::MCInstrDesc::NumOperands, llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by isKernel().

◆ getSDWAOp()

LLVM_READONLY int llvm::AMDGPU::getSDWAOp ( uint16_t  Opcode)

Referenced by findSingleRegDef(), and llvm::getRegSubRegPair().

◆ getSMRDEncodedOffset()

int64_t llvm::AMDGPU::getSMRDEncodedOffset ( const MCSubtargetInfo &  ST,
int64_t  ByteOffset 
)
Returns
The encoding that will be used for ByteOffset in the SMRD offset field.

Definition at line 1201 of file AMDGPUBaseInfo.cpp.

References hasSMEMByteOffset().

Referenced by canMoveInstsAcrossMemOp(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), getOperandSize(), isLegalSMRDImmOffset(), isStackPtrRelative(), and llvm::AMDGPUInstructionSelector::select().

◆ getSOPKOp()

LLVM_READONLY int llvm::AMDGPU::getSOPKOp ( uint16_t  Opcode)

Referenced by llvm::getRegSubRegPair(), and shrinkScalarCompare().

◆ getSOPPWithRelaxation()

LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation ( uint16_t  Opcode)

◆ getVCMPXNoSDstOp()

LLVM_READONLY int llvm::AMDGPU::getVCMPXNoSDstOp ( uint16_t  Opcode)

Referenced by llvm::getRegSubRegPair().

◆ getVmcntBitMask()

unsigned llvm::AMDGPU::getVmcntBitMask ( const IsaVersion &  Version)
Returns
Vmcnt bit mask for given isa Version.

Definition at line 556 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by callWaitsOnFunctionReturn(), llvm::AMDGPU::Waitcnt::combined(), and llvm::AMDGPUInstPrinter::printWaitFlag().

◆ getVOPe32()

LLVM_READONLY int llvm::AMDGPU::getVOPe32 ( uint16_t  Opcode)

Referenced by findSingleRegDef(), getDPPOp(), llvm::getRegSubRegPair(), llvm::SIInstrInfo::hasVALU32BitEncoding(), matchSwap(), and tryAddToFoldList().

◆ getVOPe64()

LLVM_READONLY int llvm::AMDGPU::getVOPe64 ( uint16_t  Opcode)

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter(), and llvm::getRegSubRegPair().

◆ getWaitcntBitMask()

unsigned llvm::AMDGPU::getWaitcntBitMask ( const IsaVersion &  Version)
Returns
Waitcnt bit mask for given isa Version.

Definition at line 573 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::IsaVersion::Major.

Referenced by llvm::AMDGPU::Waitcnt::combined(), encodeCnt(), and encodeWaitcnt().

◆ hasMIMG_R128()

bool llvm::AMDGPU::hasMIMG_R128 ( const MCSubtargetInfo &  STI)

Definition at line 880 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by isKernel().

◆ hasPackedD16()

bool llvm::AMDGPU::hasPackedD16 ( const MCSubtargetInfo &  STI)

Definition at line 884 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and isKernel().

◆ hasSMEMByteOffset()

static bool llvm::AMDGPU::hasSMEMByteOffset ( const MCSubtargetInfo &  ST)
static

Definition at line 1197 of file AMDGPUBaseInfo.cpp.

References isGCN3Encoding(), and isGFX10().

Referenced by getSMRDEncodedOffset(), and isLegalSMRDImmOffset().

◆ hasSRAMECC()

bool llvm::AMDGPU::hasSRAMECC ( const MCSubtargetInfo &  STI)

Definition at line 876 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(), isKernel(), and llvm::AMDGPU::IsaInfo::streamIsaVersion().

◆ hasXNACK()

bool llvm::AMDGPU::hasXNACK ( const MCSubtargetInfo &  STI)

Definition at line 872 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUAsmPrinter::EmitFunctionBodyEnd(), isKernel(), IsRevOpcode(), and llvm::AMDGPU::IsaInfo::streamIsaVersion().

◆ initDefaultAMDKernelCodeT()

void llvm::AMDGPU::initDefaultAMDKernelCodeT ( amd_kernel_code_t &  Header,
const MCSubtargetInfo *  STI 
)

Definition at line 434 of file AMDGPUBaseInfo.cpp.

References AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, amd_kernel_code_s::amd_kernel_code_version_major, amd_kernel_code_s::amd_kernel_code_version_minor, amd_kernel_code_s::amd_machine_kind, amd_kernel_code_s::amd_machine_version_major, amd_kernel_code_s::amd_machine_version_minor, amd_kernel_code_s::amd_machine_version_stepping, amd_kernel_code_s::call_convention, amd_kernel_code_s::code_properties, amd_kernel_code_s::compute_pgm_resource_registers, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), amd_kernel_code_s::group_segment_alignment, amd_kernel_code_s::kernarg_segment_alignment, amd_kernel_code_s::kernel_code_entry_byte_offset, llvm::AMDGPU::IsaVersion::Major, llvm::AMDGPU::IsaVersion::Minor, amd_kernel_code_s::private_segment_alignment, S_00B848_MEM_ORDERED, S_00B848_WGP_MODE, llvm::AMDGPU::IsaVersion::Stepping, llvm::IndexedInstrProf::Version, and amd_kernel_code_s::wavefront_size.

Referenced by getElementByteSizeValue().

◆ isArgPassedInSGPR()

bool llvm::AMDGPU::isArgPassedInSGPR ( const Argument *  A)

Definition at line 1171 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, F(), llvm::Argument::getArgNo(), llvm::Function::getAttributes(), llvm::Function::getCallingConv(), llvm::Argument::getParent(), llvm::AttributeList::hasParamAttribute(), and llvm::CallingConv::SPIR_KERNEL.

Referenced by getOperandSize(), and llvm::AMDGPUInstrInfo::isUniformMMO().

◆ isCI()

bool llvm::AMDGPU::isCI ( const MCSubtargetInfo &  STI)

Definition at line 892 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), isKernel(), and llvm::AMDGPUInstPrinter::printRegOperand().

◆ isCompute()

LLVM_READNONE bool llvm::AMDGPU::isCompute ( CallingConv::ID  cc)

Definition at line 851 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, and isShader().

Referenced by llvm::AMDGPU::Waitcnt::combined(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv(), llvm::R600AsmPrinter::getPassName(), getRsrcReg(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().

◆ isEntryFunctionCC()

LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC ( CallingConv::ID  CC)

Definition at line 855 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, and llvm::CallingConv::SPIR_KERNEL.

Referenced by llvm::SITargetLowering::CanLowerReturn(), llvm::AMDGPU::Waitcnt::combined(), hasAnyNonFlatUseOfReg(), INITIALIZE_PASS(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SITargetLowering::mayBeEmittedAsTailCall(), and mustPreserveGV().

◆ isGCN3Encoding()

bool llvm::AMDGPU::isGCN3Encoding ( const MCSubtargetInfo &  STI)

Definition at line 908 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by hasSMEMByteOffset().

◆ isGFX10()

bool llvm::AMDGPU::isGFX10 ( const MCSubtargetInfo &  STI)

Definition at line 904 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), encodeBitmaskPerm(), encodeCnt(), getLit64Encoding(), hasSMEMByteOffset(), isKernel(), isRegOrImmWithInputMods(), llvm::AMDGPU::SendMsg::isValidMsgId(), llvm::AMDGPUInstPrinter::printInst(), and llvm::AMDGPUInstPrinter::printRegOperand().

◆ isGFX9()

bool llvm::AMDGPU::isGFX9 ( const MCSubtargetInfo &  STI)

Definition at line 900 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), isKernel(), isRegOrImmWithInputMods(), IsRevOpcode(), llvm::AMDGPU::SendMsg::isValidMsgId(), and llvm::AMDGPUInstPrinter::printRegOperand().

◆ isGlobalSegment()

bool llvm::AMDGPU::isGlobalSegment ( const GlobalValue *  GV)

Definition at line 503 of file AMDGPUBaseInfo.cpp.

References llvm::PointerType::getAddressSpace(), llvm::GlobalValue::getType(), and AMDGPUAS::GLOBAL_ADDRESS.

◆ isGroupSegment()

bool llvm::AMDGPU::isGroupSegment ( const GlobalValue *  GV)

Definition at line 499 of file AMDGPUBaseInfo.cpp.

References llvm::PointerType::getAddressSpace(), llvm::GlobalValue::getType(), and AMDGPUAS::LOCAL_ADDRESS.

◆ isInlinableLiteral16()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral16 ( int16_t  Literal,
bool  HasInv2Pi 
)

Definition at line 1137 of file AMDGPUBaseInfo.cpp.

Referenced by getOperandSize(), isInlinableLiteralV216(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteral32()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 ( int32_t  Literal,
bool  HasInv2Pi 
)

Definition at line 1111 of file AMDGPUBaseInfo.cpp.

References llvm::FloatToBits().

Referenced by llvm::SIRegisterInfo::eliminateFrameIndex(), getOperandSize(), llvm::SIInstrInfo::isInlineConstant(), and shrinkScalarLogicOp().

◆ isInlinableLiteral64()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 ( int64_t  Literal,
bool  HasInv2Pi 
)

Is this literal inlinable.

Definition at line 1094 of file AMDGPUBaseInfo.cpp.

References llvm::DoubleToBits().

Referenced by getOperandSize(), and llvm::SIInstrInfo::isInlineConstant().

◆ isInlinableLiteralV216()

LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216 ( int32_t  Literal,
bool  HasInv2Pi 
)

Definition at line 1156 of file AMDGPUBaseInfo.cpp.

References assert(), isInlinableLiteral16(), llvm::isInt< 16 >(), and llvm::isUInt< 16 >().

Referenced by getOperandSize(), llvm::SIInstrInfo::isInlineConstant(), and updateOperand().

◆ isIntrinsicSourceOfDivergence()

bool llvm::AMDGPU::isIntrinsicSourceOfDivergence ( unsigned  IntrID)
Returns
true if the intrinsic is divergent

Definition at line 1284 of file AMDGPUBaseInfo.cpp.

Referenced by getOperandSize(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().

◆ isKernel()

LLVM_READNONE bool llvm::AMDGPU::isKernel ( CallingConv::ID  CC)
inline

Definition at line 506 of file AMDGPUBaseInfo.h.

References llvm::CallingConv::AMDGPU_KERNEL, getMCReg(), getRegBitWidth(), getRegOperandSize(), hasMIMG_R128(), hasPackedD16(), hasSRAMECC(), hasXNACK(), isCI(), isGFX10(), isGFX9(), isRegIntersect(), isSGPR(), isSI(), isSISrcFPOperand(), isSISrcInlinableOperand(), isSISrcOperand(), isVI(), LLVM_READNONE, mc2PseudoReg(), MRI, Reg, llvm::CallingConv::SPIR_KERNEL, and TRI.

Referenced by llvm::SITargetLowering::LowerFormalArguments(), and llvm::SITargetLowering::LowerReturn().

◆ isLegalSMRDImmOffset()

bool llvm::AMDGPU::isLegalSMRDImmOffset ( const MCSubtargetInfo &  ST,
int64_t  ByteOffset 
)
Returns
true if this offset is small enough to fit in the SMRD offset field. ByteOffset should be the offset in bytes and not the encoded offset.

Definition at line 1207 of file AMDGPUBaseInfo.cpp.

References getSMRDEncodedOffset(), hasSMEMByteOffset(), and llvm::isUInt< 8 >().

Referenced by getOperandSize(), isStackPtrRelative(), and llvm::AMDGPUInstructionSelector::select().

◆ isReadOnlySegment()

bool llvm::AMDGPU::isReadOnlySegment ( const GlobalValue *  GV)

Definition at line 507 of file AMDGPUBaseInfo.cpp.

References AMDGPUAS::CONSTANT_ADDRESS, AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::PointerType::getAddressSpace(), and llvm::GlobalValue::getType().

Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

◆ isRegIntersect()

bool llvm::AMDGPU::isRegIntersect ( unsigned  Reg0,
unsigned  Reg1,
const MCRegisterInfo *  TRI 
)

Is there any intersection between registers.

Definition at line 919 of file AMDGPUBaseInfo.cpp.

Referenced by isKernel().

◆ isSGPR()

bool llvm::AMDGPU::isSGPR ( unsigned  Reg,
const MCRegisterInfo *  TRI 
)

Is Reg - scalar register.

Definition at line 912 of file AMDGPUBaseInfo.cpp.

References llvm::MCRegisterClass::contains(), llvm::MCRegisterInfo::getRegClass(), and llvm::MCRegisterInfo::getSubReg().

Referenced by getLit64Encoding(), and isKernel().

◆ isShader()

LLVM_READNONE bool llvm::AMDGPU::isShader ( CallingConv::ID  cc)

Definition at line 836 of file AMDGPUBaseInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, and llvm::CallingConv::AMDGPU_VS.

Referenced by llvm::SIInstrInfo::calculateLDSSpillAddress(), llvm::AMDGPU::Waitcnt::combined(), isCompute(), llvm::GCNSubtarget::isMesaGfxShader(), llvm::AMDGPUSubtarget::isMesaKernel(), llvm::SIInstrInfo::legalizeOperands(), llvm::SITargetLowering::LowerCall(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::SITargetLowering::LowerReturn(), and reservePrivateMemoryRegs().

◆ isSI()

bool llvm::AMDGPU::isSI ( const MCSubtargetInfo &  STI)

Definition at line 888 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), isKernel(), and llvm::AMDGPUInstPrinter::printRegOperand().

◆ isSISrcFPOperand()

bool llvm::AMDGPU::isSISrcFPOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Is this floating-point operand?

Definition at line 1001 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2INT16, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2INT16, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

Referenced by isKernel().

◆ isSISrcInlinableOperand()

bool llvm::AMDGPU::isSISrcInlinableOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Does this opearnd support only inlinable literals?

Definition at line 1025 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_REG_INLINE_C_FIRST, OPERAND_REG_INLINE_C_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

Referenced by isKernel().

◆ isSISrcOperand()

bool llvm::AMDGPU::isSISrcOperand ( const MCInstrDesc &  Desc,
unsigned  OpNo 
)

Can this operand also contain immediate values?

Definition at line 994 of file AMDGPUBaseInfo.cpp.

References assert(), llvm::MCInstrDesc::NumOperands, OPERAND_SRC_FIRST, OPERAND_SRC_LAST, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

Referenced by getLit64Encoding(), llvm::SIInstrInfo::isImmOperandLegal(), isKernel(), llvm::SIInstrInfo::isOperandLegal(), IsRevOpcode(), and needsPCRel().

◆ isVI()

bool llvm::AMDGPU::isVI ( const MCSubtargetInfo &  STI)

Definition at line 896 of file AMDGPUBaseInfo.cpp.

References llvm::MCSubtargetInfo::getFeatureBits().

Referenced by llvm::AMDGPU::Hwreg::getLastSymbolicHwreg(), isKernel(), isRegOrImmWithInputMods(), and llvm::AMDGPUInstPrinter::printRegOperand().

◆ lookupD16ImageDimIntrinsic()

const D16ImageDimIntrinsic* llvm::AMDGPU::lookupD16ImageDimIntrinsic ( unsigned  Intr)

◆ lookupRsrcIntrinsic()

const RsrcIntrinsic* llvm::AMDGPU::lookupRsrcIntrinsic ( unsigned  Intr)

Referenced by llvm::SITargetLowering::getTgtMemIntrinsic().

◆ mc2PseudoReg()

LLVM_READNONE unsigned llvm::AMDGPU::mc2PseudoReg ( unsigned  Reg)

Convert hardware register Reg to a pseudo register.

Definition at line 986 of file AMDGPUBaseInfo.cpp.

References MAP_REG2REG.

Referenced by getLit64Encoding(), and isKernel().

◆ parseArchAMDGCN()

AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN ( StringRef  CPU)

Definition at line 134 of file TargetParser.cpp.

References C, and GK_NONE.

Referenced by llvm::AMDGPUTargetStreamer::getElfMach(), and getIsaVersion().

◆ parseArchR600()

AMDGPU::GPUKind llvm::AMDGPU::parseArchR600 ( StringRef  CPU)

Definition at line 143 of file TargetParser.cpp.

References C, and GK_NONE.

Referenced by llvm::AMDGPUTargetStreamer::getElfMach().

◆ shouldEmitConstantsToTextSection()

bool llvm::AMDGPU::shouldEmitConstantsToTextSection ( const Triple &  TT)
Returns
True if constants should be emitted to .text section for given target triple TT, false otherwise.

Definition at line 512 of file AMDGPUBaseInfo.cpp.

References llvm::Triple::AMDHSA, and llvm::Triple::getOS().

Referenced by findUser(), and llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().

◆ splitMUBUFOffset()

bool llvm::AMDGPU::splitMUBUFOffset ( uint32_t  Imm,
uint32_t &  SOffset,
uint32_t &  ImmOffset,
const GCNSubtarget *  Subtarget,
uint32_t  Align 
)

Definition at line 1220 of file AMDGPUBaseInfo.cpp.

References llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::alignDown(), llvm::GCNSubtarget::getGeneration(), High, and llvm::AMDGPUSubtarget::SEA_ISLANDS.

Referenced by getOperandSize().

Variable Documentation

◆ RSRC_DATA_FORMAT

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

Definition at line 1089 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat(), and llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_ELEMENT_SIZE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT = (32 + 19)

Definition at line 1090 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_INDEX_STRIDE_SHIFT

const uint64_t llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT = (32 + 21)

Definition at line 1091 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

◆ RSRC_TID_ENABLE

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23)

Definition at line 1092 of file SIInstrInfo.h.

Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().

Generated on Thu Jul 18 2019 00:52:30 for LLVM by   doxygen 1.8.13