18 if (ST.hasIEEEMode()) {
19 StringRef IEEEAttr =
F.getFnAttribute(
"amdgpu-ieee").getValueAsString();
20 if (!IEEEAttr.
empty())
21 IEEE = IEEEAttr ==
"true";
24 if (ST.hasDX10ClampMode()) {
26 F.getFnAttribute(
"amdgpu-dx10-clamp").getValueAsString();
27 if (!DX10ClampAttr.
empty())
52 return static_cast<uint64_t>(FltRoundsVal) << BitIndex;
57static constexpr uint64_t
176 << (FltRoundsVal << 2);
187 << (FltRoundsVal << 2);
AMD GCN specific subclass of TargetSubtarget.
#define FP_ROUND_ROUND_TO_INF
#define FP_ROUND_ROUND_TO_NEAREST
#define FP_ROUND_ROUND_TO_ZERO
#define FP_ROUND_ROUND_TO_NEGINF
static constexpr uint64_t encodeFltRoundsToHWTable(uint32_t HWF32Val, uint32_t HWF64Val, uint32_t FltRoundsVal)
Decode FLT_ROUNDS into the hardware value where the two rounding modes different and use an extended ...
static constexpr uint32_t decodeFltRoundToHW(uint32_t FltRounds)
static constexpr AMDGPUFltRounds decodeIndexFltRoundConversionTable(uint32_t HWMode)
static constexpr uint32_t HWTowardNegative
static constexpr uint64_t encodeFltRoundsTableSame(AMDGPUFltRounds FltRoundsMode, uint32_t HWVal)
static constexpr uint32_t HWTowardPositive
static constexpr uint32_t HWTowardZero
static constexpr uint64_t encodeFltRoundsToHWTableSame(uint32_t HWVal, uint32_t FltRoundsVal)
static constexpr uint64_t encodeFltRoundsTable(uint32_t FltRoundsVal, uint32_t HWF32Val, uint32_t HWF64Val)
static constexpr uint32_t decodeFltRoundToHWConversionTable(uint64_t FltRoundToHWConversionTable, uint32_t FltRounds)
Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.
static constexpr uint32_t HWNearestTiesToEven
static constexpr uint32_t getModeRegisterRoundMode(uint32_t HWFP32Val, uint32_t HWFP64Val)
Combine f32 and f64 rounding modes into a combined rounding mode value.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
const uint64_t FltRoundToHWConversionTable
static constexpr uint32_t F64FltRoundOffset
Offset in mode register of f64/f16 rounding mode.
static constexpr uint32_t ExtendedFltRoundOffset
Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
AMDGPUFltRounds
Return values used for llvm.get.rounding.
@ NearestTiesToEvenF32_NearestTiesToEvenF64
@ TowardZeroF32_NearestTiesToEvenF64
@ TowardNegativeF32_NearestTiesToEvenF64
@ TowardPositiveF32_NearestTiesToEvenF64
@ TowardPositiveF32_TowardZeroF64
@ TowardNegativeF32_TowardZeroF64
@ NearestTiesToEvenF32_TowardNegativeF64
@ NearestTiesToEvenF32_TowardZeroF64
@ TowardPositiveF32_TowardPositiveF64
@ TowardNegativeF32_TowardPositiveF64
@ NearestTiesToEvenF32_TowardPositiveF64
@ TowardZeroF32_TowardNegativeF64
@ TowardZeroF32_TowardZeroF64
@ TowardZeroF32_TowardPositiveF64
@ TowardNegativeF32_TowardNegativeF64
@ TowardPositiveF32_TowardNegativeF64
uint32_t decodeFltRoundToHWConversionTable(uint32_t FltRounds)
Read the hardware rounding mode equivalent of a AMDGPUFltRounds value.
static constexpr uint32_t F32FltRoundOffset
Offset in mode register of f32 rounding mode.
const uint64_t FltRoundConversionTable
This is an optimization pass for GlobalISel generic memory operations.
Represents the full denormal controls for a function, including the default mode and the f32 specific...
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
DenormalMode FP64FP16Denormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
DenormalMode FP32Denormals
If this is set, neither input or output denormals are flushed for most f32 instructions.