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14 #ifndef LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
15 #define LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
24 #define GET_SUBTARGETINFO_HEADER
25 #include "AMDGPUGenSubtargetInfo.inc"
29 class GCNTargetMachine;
51 std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
52 std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
53 std::unique_ptr<InstructionSelector> InstSelector;
55 std::unique_ptr<RegisterBankInfo> RegBankInfo;
219 return &FrameLowering;
231 return CallLoweringInfo.get();
235 return InlineAsmLoweringInfo.get();
239 return InstSelector.get();
247 return RegBankInfo.get();
776 bool useAA()
const override;
794 unsigned NumRegionInstrs)
const override;
1129 std::pair<unsigned, unsigned> WavesPerEU,
1130 unsigned PreloadedSGPRs,
1131 unsigned ReservedNumSGPRs)
const;
1188 std::pair<unsigned, unsigned> WavesPerEU)
const;
1214 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
1217 std::unique_ptr<ScheduleDAGMutation>
1262 SDep &Dep)
const override;
1271 #endif // LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H
bool shouldClusterStores() const
bool hasScalarMulHiInsts() const
bool hasReadM0LdsDmaHazard() const
bool hasVDecCoExecHazard() const
bool hasPermLane64() const
bool hasDot2Insts() const
This is an optimization pass for GlobalISel generic memory operations.
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
bool hasGWSAutoReplay() const
bool hasFlatLgkmVMemCountInOrder() const
const RegisterBankInfo * getRegBankInfo() const override
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
bool hasDstSelForwardingHazard() const
bool hasVGPRIndexMode() const
const SIFrameLowering * getFrameLowering() const override
GCNSubtarget & initializeSubtargetDependencies(const Triple &TT, StringRef GPU, StringRef FS)
bool hasD16Images() const
bool hasImageInsts() const
bool hasVALUPartialForwardingHazard() const
bool isSramEccOnOrAny() const
bool hasNSAClauseBug() const
unsigned getNSAMaxSize() const
bool hasVMEMReadSGPRVALUDefHazard() const
A read of an SGPR by a VMEM instruction requires 5 wait states when the SGPR was written by a VALU In...
bool hasPermLaneX16() const
bool hasShaderCyclesRegister() const
bool needsAlignedVGPRs() const
Return if operations acting on VGPR tuples require even alignment.
bool hasFlatScratchInsts() const
InstrItineraryData InstrItins
bool hasAutoWaitcntBeforeBarrier() const
bool supportsMinMaxDenormModes() const
bool hasFlatSegmentOffsetBug() const
bool hasDS96AndDS128() const
bool HasVcmpxPermlaneHazard
bool hasSPackHL() const
Return true if the target has the S_PACK_HL_B32_B16 instruction.
unsigned getSetRegWaitStates() const
Number of hazard wait states for s_setreg_b32/s_setreg_imm32_b32.
Triple - Helper class for working with autoconf configuration names.
bool hasVOPDInsts() const
bool HasExtendedImageInsts
bool hasFlatGlobalInsts() const
unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override
unsigned getMaxFlatWorkGroupSize() const override
bool isTrapHandlerEnabled() const
bool hasDot3Insts() const
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
bool hasDwordx3LoadStores() const
bool hasNSAEncoding() const
unsigned getMaxWavesPerEU() const
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
Align getStackAlignment() const
bool hasUnalignedDSAccessEnabled() const
bool partialVCCWritesUpdateVCCZ() const
Writes to VCC_LO/VCC_HI update the VCCZ flag.
bool HasFlatSegmentOffsetBug
bool loadStoreOptEnabled() const
AMDGPU::IsaInfo::AMDGPUTargetID TargetID
bool UnalignedBufferAccess
bool hasGetWaveIdInst() const
bool ScalarFlatScratchInsts
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
bool hasPackedFP32Ops() const
bool NegativeScratchOffsetBug
bool hasScalarCompareEq64() const
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
const SIRegisterInfo * getRegisterInfo() const override
bool hasCompressedExport() const
Return true if the target's EXP instruction has the COMPR flag, which affects the meaning of the EN (...
bool hasLDSFPAtomicAdd() const
bool hasLdsDirect() const
const SIInstrInfo * getInstrInfo() const override
bool unsafeDSOffsetFoldingEnabled() const
bool hasUnalignedBufferAccessEnabled() const
bool hasHalfRate64Ops() const
bool hasGFX10_AEncoding() const
bool hasGWSSemaReleaseAll() const
unsigned getMaxNumAGPRs(const Function &F) const
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
TargetInstrInfo - Interface to description of machine instruction set.
unsigned getKnownHighZeroBitsForFrameIndex() const
Return the number of high bits known to be zero for a frame index.
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
bool hasFlatScrRegister() const
bool isShader(CallingConv::ID cc)
bool hasFastFMAF32() const
bool enableMachineScheduler() const override
unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const
bool useVGPRIndexMode() const
bool useFlatForGlobal() const
bool hasFmaMixInsts() const
bool hasUnalignedAccessMode() const
bool hasScalarFlatScratchInsts() const
const SITargetLowering * getTargetLowering() const override
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
bool hasSMRDReadVALUDefHazard() const
A read of an SGPR by SMRD instruction requires 4 wait states when the SGPR was written by a VALU inst...
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const
Return the maximum number of waves per SIMD for kernels using SGPRs SGPRs.
const InlineAsmLowering * getInlineAsmLowering() const override
bool HasArchitectedFlatScratch
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int b
unsigned getBaseMaxNumSGPRs(const Function &F, std::pair< unsigned, unsigned > WavesPerEU, unsigned PreloadedSGPRs, unsigned ReservedNumSGPRs) const
unsigned getMinFlatWorkGroupSize() const override
bool isXnackOnOrAny() const
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
unsigned getMaxPrivateElementSize(bool ForBufferRSrc=false) const
bool hasGFX940Insts() const
bool hasVOP3Literal() const
const HexagonInstrInfo * TII
bool hasSMemTimeInst() const
bool hasReadVCCZBug() const
Extra wait hazard is needed in some cases before s_cbranch_vccnz/s_cbranch_vccz.
bool hasSGPRInitBug() const
bool AutoWaitcntBeforeBarrier
bool hasSMemRealTime() const
InstructionSelector * getInstructionSelector() const override
bool isMesaGfxShader(const Function &F) const
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
bool hasGFX10_BEncoding() const
bool hasPkFmacF16Inst() const
bool isTgSplitEnabled() const
This struct is a compact representation of a valid (non-zero power of two) alignment.
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const
bool hasDot6Insts() const
bool hasScalarAtomics() const
bool hasUnalignedDSAccess() const
bool getScalarizeGlobalBehavior() const
bool hasTransForwardingHazard() const
bool hasExtendedImageInsts() const
bool hasDot1Insts() const
bool hasOffset3fBug() const
bool hasVcmpxExecWARHazard() const
unsigned getWavefrontSize() const
unsigned getVGPREncodingGranule() const
bool HasLdsBranchVmemWARHazard
bool EnableUnsafeDSOffsetFolding
static const unsigned MaxWaveScratchSize
const LegalizerInfo * getLegalizerInfo() const override
bool hasNegativeUnalignedScratchOffsetBug() const
bool usePRTStrictNull() const
bool hasAtomicPkFaddNoRtnInsts() const
bool hasInstFwdPrefetchBug() const
Holds all the information related to register banks.
Provides the logic to select generic machine instructions.
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getSGPRAllocGranule() const
bool hasImageGather4D16Bug() const
bool hasPackedTID() const
TrapHandlerAbi getTrapHandlerAbi() const
bool HasAtomicPkFaddNoRtnInsts
bool hasNegativeScratchOffsetBug() const
bool hasVMEMtoScalarWriteHazard() const
bool hasAddNoCarry() const
bool HasShaderCyclesRegister
bool hasUnalignedBufferAccess() const
unsigned getTotalNumVGPRs() const
GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS, const GCNTargetMachine &TM)
bool privateMemoryResourceIsRangeChecked() const
bool HasVMEMtoScalarWriteHazard
bool hasLDSMisalignedBug() const
bool hasMFMAInlineLiteralBug() const
bool HasImageGather4D16Bug
bool hasImageStoreD16Bug() const
bool hasGlobalAddTidInsts() const
bool hasSDWAScalar() const
bool HasAtomicFaddNoRtnInsts
const TargetRegisterClass * getBoolRC() const
bool hasFlatScratchSVSMode() const
bool hasFmaakFmamkF32Insts() const
bool hasAtomicFaddNoRtnInsts() const
bool hasNullExportTarget() const
Return true if the target's EXP instruction supports the NULL export target.
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
bool hasReadM0MovRelInterpHazard() const
unsigned getAddressableNumSGPRs() const
bool hasUnalignedScratchAccess() const
bool hasDot7Insts() const
SelectionDAGTargetInfo TSInfo
bool hasRFEHazards() const
bool HasVcmpxExecWARHazard
bool hasGFX90AInsts() const
unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const
Return the maximum number of waves per SIMD for kernels using VGPRs VGPRs.
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
bool hasNoDataDepHazard() const
bool enableEarlyIfConversion() const override
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(unsigned FlatWorkGroupSize) const override
int getLDSBankCount() const
unsigned MaxPrivateElementSize
bool hasDOTOpSelHazard() const
bool hasLdsBranchVmemWARHazard() const
bool hasMultiDwordFlatScratchAddressing() const
bool hasDenormModeInst() const
bool hasAtomicFaddInsts() const
StringRef - Represent a constant reference to a string, i.e.
bool hasFlatInstOffsets() const
bool hasDot5Insts() const
bool hasScalarStores() const
bool hasGFX10_3Insts() const
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
bool flatScratchIsPointer() const
bool supportsGetDoorbellID() const
bool hasDPPBroadcasts() const
bool hasVALUTransUseHazard() const
bool hasDPPWavefrontShifts() const
bool NegativeUnalignedScratchOffsetBug
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
bool hasScalarPackInsts() const
bool hasD16LoadStore() const
const TargetRegisterClass * getBoolRC() const
void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx, SDep &Dep) const override
bool hasDot4Insts() const
bool hasNoSdstCMPX() const
TargetSubtargetInfo - Generic base class for all target subtargets.
unsigned getMinNumSGPRs(unsigned WavesPerEU) const
void getPostRAMutations(std::vector< std::unique_ptr< ScheduleDAGMutation >> &Mutations) const override
bool hasFlatScratchSTMode() const
bool hasFlatAddressSpace() const
unsigned getReservedNumSGPRs(const MachineFunction &MF) const
bool hasAtomicFaddRtnInsts() const
unsigned getVGPRAllocGranule() const
bool hasNSAtoVMEMBug() const
bool enableSubRegLiveness() const override
unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount, const Function &) const
Return the amount of LDS that can be used that will not restrict the occupancy lower than WaveCount.
void setScalarizeGlobalBehavior(bool b)
bool hasFullRate64Ops() const
bool hasDot8Insts() const
bool hasUnpackedD16VMem() const
bool flatScratchIsArchitected() const
const AMDGPU::IsaInfo::AMDGPUTargetID & getTargetID() const
unsigned getMinWavesPerEU() const override
bool useAA() const override
bool HasInstFwdPrefetchBug
bool HasSMEMtoVectorWriteHazard
bool hasHardClauses() const
bool hasBCNT(unsigned Size) const
bool haveRoundOpsF64() const
Have v_trunc_f64, v_ceil_f64, v_rndne_f64.
bool ldsRequiresM0Init() const
Return if most LDS instructions have an m0 use that require m0 to be initialized.
const SIRegisterInfo & getRegisterInfo() const
unsigned getMaxNumUserSGPRs() const
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
bool zeroesHigh16BitsOfDest(unsigned Opcode) const
Returns if the result of this instruction with a 16-bit result returned in a 32-bit register implicit...
bool HasMFMAInlineLiteralBug
unsigned countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the most significant bit to the least stopping at the first 1.
bool hasOnlyRevVALUShifts() const
bool UnalignedScratchAccess
Generation getGeneration() const
unsigned getAddressableNumVGPRs() const
bool hasLegacyGeometry() const
bool enableFlatScratch() const
bool isXNACKEnabled() const
bool isCuModeEnabled() const
unsigned getConstantBusLimit(unsigned Opcode) const
bool hasMergedShaders() const
unsigned getBaseReservedNumSGPRs(const bool HasFlatScratch) const
const SelectionDAGTargetInfo * getSelectionDAGInfo() const override
bool hasApertureRegs() const
unsigned getSGPREncodingGranule() const
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
bool d16PreservesUnusedBits() const
bool enableSIScheduler() const
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
const InstrItineraryData * getInstrItineraryData() const override
bool vmemWriteNeedsExpWaitcnt() const
bool hasDelayAlu() const
Return true if the target has the S_DELAY_ALU instruction.
bool hasReadM0SendMsgHazard() const
bool hasMIMG_R128() const
const char LLVMTargetMachineRef TM
constexpr char NumVGPRs[]
Key for Kernel::CodeProps::Metadata::mNumVGPRs.
Scheduling unit. This is a node in the scheduling DAG.
bool hasSMEMtoVectorWriteHazard() const
bool hasMin3Max3_16() const
std::unique_ptr< ScheduleDAGMutation > createFillMFMAShadowMutation(const TargetInstrInfo *TII) const
bool HasAtomicFaddRtnInsts
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
unsigned getTotalNumSGPRs() const
bool has12DWordStoreHazard() const
unsigned getWavefrontSizeLog2() const
bool hasVcmpxPermlaneHazard() const
bool hasSDWAOutModsVOPC() const
unsigned computeOccupancy(const Function &F, unsigned LDSSize=0, unsigned NumSGPRs=0, unsigned NumVGPRs=0) const
Return occupancy for the given function.
bool hasUsableDSOffset() const
True if the offset field of DS instructions works as expected.
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Itinerary data supplied by a subtarget to be used by a target.
unsigned getBaseMaxNumVGPRs(const Function &F, std::pair< unsigned, unsigned > WavesPerEU) const
A Use represents the edge between a Value definition and its users.
bool hasUsableDivScaleConditionOutput() const
Condition output from div_scale is usable.
bool hasLshlAddB64() const
bool hasAtomicCSub() const
const CallLowering * getCallLowering() const override
bool hasReadM0LdsDirectHazard() const