LLVM 19.0.0git
Classes | Public Member Functions | Static Public Member Functions | List of all members
llvm::SIRegisterInfo Class Referencefinal

#include "Target/AMDGPU/SIRegisterInfo.h"

Inheritance diagram for llvm::SIRegisterInfo:
Inheritance graph
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Classes

struct  SpilledReg
 

Public Member Functions

 SIRegisterInfo (const GCNSubtarget &ST)
 
bool spillSGPRToVGPR () const
 
MCRegister getAlignedHighSGPRForRC (const MachineFunction &MF, const unsigned Align, const TargetRegisterClass *RC) const
 Return the largest available SGPR aligned to Align for the register class RC.
 
MCRegister reservedPrivateSegmentBufferReg (const MachineFunction &MF) const
 Return the end register initially reserved for the scratch buffer in case spilling is needed.
 
BitVector getReservedRegs (const MachineFunction &MF) const override
 
bool isAsmClobberable (const MachineFunction &MF, MCRegister PhysReg) const override
 
const MCPhysReggetCalleeSavedRegs (const MachineFunction *MF) const override
 
const MCPhysReggetCalleeSavedRegsViaCopy (const MachineFunction *MF) const
 
const uint32_tgetCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override
 
const uint32_tgetNoPreservedMask () const override
 
unsigned getCSRFirstUseCost () const override
 
const TargetRegisterClassgetLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &MF) const override
 
Register getFrameRegister (const MachineFunction &MF) const override
 
bool hasBasePointer (const MachineFunction &MF) const
 
Register getBaseRegister () const
 
bool shouldRealignStack (const MachineFunction &MF) const override
 
bool requiresRegisterScavenging (const MachineFunction &Fn) const override
 
bool requiresFrameIndexScavenging (const MachineFunction &MF) const override
 
bool requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const override
 
bool requiresVirtualBaseRegisters (const MachineFunction &Fn) const override
 
int64_t getScratchInstrOffset (const MachineInstr *MI) const
 
int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override
 
bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
 
Register materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
 
void resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const override
 
bool isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
 
const TargetRegisterClassgetPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override
 
const TargetRegisterClassgetCrossCopyRegClass (const TargetRegisterClass *RC) const override
 Returns a legal register class to copy a register in the specified class to or from.
 
void buildVGPRSpillLoadStore (SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
 
bool spillSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
 If OnlyToVGPR is true, this will only succeed if this manages to find a free VGPR lane to spill.
 
bool restoreSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
 
bool spillEmergencySGPR (MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
 
bool eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
 
bool eliminateSGPRToVGPRSpillFrameIndex (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool SpillToPhysVGPRLane=false) const
 Special case of eliminateFrameIndex.
 
StringRef getRegAsmName (MCRegister Reg) const override
 
unsigned getHWRegIndex (MCRegister Reg) const
 
LLVM_READONLY const TargetRegisterClassgetVGPRClassForBitWidth (unsigned BitWidth) const
 
LLVM_READONLY const TargetRegisterClassgetAGPRClassForBitWidth (unsigned BitWidth) const
 
LLVM_READONLY const TargetRegisterClassgetVectorSuperClassForBitWidth (unsigned BitWidth) const
 
bool isSGPRClassID (unsigned RCID) const
 
bool isSGPRReg (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isVectorSuperClass (const TargetRegisterClass *RC) const
 
bool isVSSuperClass (const TargetRegisterClass *RC) const
 
const TargetRegisterClassgetEquivalentVGPRClass (const TargetRegisterClass *SRC) const
 
const TargetRegisterClassgetEquivalentAGPRClass (const TargetRegisterClass *SRC) const
 
const TargetRegisterClassgetEquivalentSGPRClass (const TargetRegisterClass *VRC) const
 
const TargetRegisterClassgetCompatibleSubRegClass (const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
 Returns a register class which is compatible with SuperRC, such that a subregister exists with class SubRC with subregister index SubIdx.
 
bool shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
 
bool opCanUseLiteralConstant (unsigned OpType) const
 
bool opCanUseInlineConstant (unsigned OpType) const
 
MCRegister findUnusedRegister (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
 Returns a lowest register that is not used at any point in the function.
 
const TargetRegisterClassgetRegClassForReg (const MachineRegisterInfo &MRI, Register Reg) const
 
const TargetRegisterClassgetRegClassForOperandReg (const MachineRegisterInfo &MRI, const MachineOperand &MO) const
 
bool isVGPR (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isAGPR (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isVectorRegister (const MachineRegisterInfo &MRI, Register Reg) const
 
bool isDivergentRegClass (const TargetRegisterClass *RC) const override
 
bool isUniformReg (const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const override
 
ArrayRef< int16_t > getRegSplitParts (const TargetRegisterClass *RC, unsigned EltSize) const
 
bool shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
 
unsigned getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override
 
unsigned getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const override
 
const int * getRegUnitPressureSets (unsigned RegUnit) const override
 
MCRegister getReturnAddressReg (const MachineFunction &MF) const
 
const TargetRegisterClassgetRegClassForSizeOnBank (unsigned Size, const RegisterBank &Bank) const
 
const TargetRegisterClassgetRegClassForTypeOnBank (LLT Ty, const RegisterBank &Bank) const
 
const TargetRegisterClassgetConstrainedRegClassForOperand (const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
 
const TargetRegisterClassgetBoolRC () const
 
const TargetRegisterClassgetWaveMaskRegClass () const
 
const TargetRegisterClassgetVGPR64Class () const
 
MCRegister getVCC () const
 
MCRegister getExec () const
 
const TargetRegisterClassgetRegClass (unsigned RCID) const
 
MachineInstrfindReachingDef (Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
 
const uint32_tgetAllVGPRRegMask () const
 
const uint32_tgetAllAGPRRegMask () const
 
const uint32_tgetAllVectorRegMask () const
 
const uint32_tgetAllAllocatableSRegMask () const
 
unsigned getChannelFromSubReg (unsigned SubReg) const
 
unsigned getNumChannelsFromSubReg (unsigned SubReg) const
 
MCPhysReg get32BitRegister (MCPhysReg Reg) const
 
bool isProperlyAlignedRC (const TargetRegisterClass &RC) const
 
const TargetRegisterClassgetProperlyAlignedRC (const TargetRegisterClass *RC) const
 
ArrayRef< MCPhysReggetAllSGPR128 (const MachineFunction &MF) const
 Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
 
ArrayRef< MCPhysReggetAllSGPR64 (const MachineFunction &MF) const
 Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
 
ArrayRef< MCPhysReggetAllSGPR32 (const MachineFunction &MF) const
 Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
 
void buildSpillLoadStore (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LiveRegUnits *LiveUnits=nullptr) const
 
unsigned getRegClassAlignmentNumBits (const TargetRegisterClass *RC) const
 
bool isRegClassAligned (const TargetRegisterClass *RC, unsigned AlignNumBits) const
 
unsigned getSubRegAlignmentNumBits (const TargetRegisterClass *RC, unsigned SubReg) const
 

Static Public Member Functions

static unsigned getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1)
 
static bool isChainScratchRegister (Register VGPR)
 
static LLVM_READONLY const TargetRegisterClassgetSGPRClassForBitWidth (unsigned BitWidth)
 
static bool isSGPRClass (const TargetRegisterClass *RC)
 
static bool isVGPRClass (const TargetRegisterClass *RC)
 
static bool isAGPRClass (const TargetRegisterClass *RC)
 
static bool hasVGPRs (const TargetRegisterClass *RC)
 
static bool hasAGPRs (const TargetRegisterClass *RC)
 
static bool hasSGPRs (const TargetRegisterClass *RC)
 
static bool hasVectorRegisters (const TargetRegisterClass *RC)
 
static unsigned getNumCoveredRegs (LaneBitmask LM)
 

Detailed Description

Definition at line 32 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

◆ SIRegisterInfo()

SIRegisterInfo::SIRegisterInfo ( const GCNSubtarget ST)

Member Function Documentation

◆ buildSpillLoadStore()

void SIRegisterInfo::buildSpillLoadStore ( MachineBasicBlock MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc DL,
unsigned  LoadStoreOp,
int  Index,
Register  ValueReg,
bool  ValueIsKill,
MCRegister  ScratchOffsetReg,
int64_t  InstrOffset,
MachineMemOperand MMO,
RegScavenger RS,
LiveRegUnits LiveUnits = nullptr 
) const

Definition at line 1329 of file SIRegisterInfo.cpp.

References llvm::Add, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LiveRegUnits::available(), llvm::BuildMI(), llvm::commonAlignment(), DL, llvm::MachineBasicBlock::end(), llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getConstantBusLimit(), llvm::getDefRegState(), llvm::MachineMemOperand::getFlags(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), getFlatScratchSpillOpcode(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), getOffenMUBUFLoad(), getOffenMUBUFStore(), llvm::MachineBasicBlock::getParent(), llvm::MachineMemOperand::getPointerInfo(), llvm::AMDGPU::getRegBitWidth(), getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getSubRegFromChannel(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::MachinePointerInfo::getWithOffset(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, isAGPRClass(), llvm::AMDGPUMachineFunction::isBottomOfStack(), llvm::RegScavenger::isRegUsed(), llvm::MachineRegisterInfo::isReserved(), llvm::RegState::Kill, MBB, MI, llvm::MOLastUse, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineInstr::ReloadReuse, llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineInstr::setAsmPrinterFlag(), llvm::RegScavenger::setRegUsed(), Size, spillVGPRtoAGPR(), SubReg, llvm::AMDGPU::CPol::TH_LU, and TII.

Referenced by buildVGPRSpillLoadStore(), and eliminateFrameIndex().

◆ buildVGPRSpillLoadStore()

void SIRegisterInfo::buildVGPRSpillLoadStore ( SGPRSpillBuilder SB,
int  Index,
int  Offset,
bool  IsLoad,
bool  IsKill = true 
) const

◆ eliminateFrameIndex()

bool SIRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI,
int  SPAdj,
unsigned  FIOperandNum,
RegScavenger RS 
) const
override

Definition at line 2079 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), buildSpillLoadStore(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::SIInstrFlags::FlatScratch, getBaseRegister(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSVS(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::AMDGPU::getNamedOperandIdx(), getNumSubRegsForSpillOp(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRForEXECCopy(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), hasBasePointer(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPU::hasNamedOperand(), I, llvm::AMDGPUMachineFunction::isBottomOfStack(), llvm::AMDGPU::isInlinableLiteral32(), llvm::MachineOperand::isKill(), llvm::RegScavenger::isRegUsed(), llvm::MachineRegisterInfo::isReserved(), isSGPRClass(), llvm::Register::isValid(), llvm::RegState::Kill, MBB, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::report_fatal_error(), restoreSGPR(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), spillSGPR(), and TII.

◆ eliminateSGPRToVGPRSpillFrameIndex()

bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS,
SlotIndexes Indexes = nullptr,
LiveIntervals LIS = nullptr,
bool  SpillToPhysVGPRLane = false 
) const

Special case of eliminateFrameIndex.

Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.

Definition at line 2040 of file SIRegisterInfo.cpp.

References llvm_unreachable, MI, restoreSGPR(), and spillSGPR().

◆ findReachingDef()

MachineInstr * SIRegisterInfo::findReachingDef ( Register  Reg,
unsigned  SubReg,
MachineInstr Use,
MachineRegisterInfo MRI,
LiveIntervals LIS 
) const

◆ findUnusedRegister()

MCRegister SIRegisterInfo::findUnusedRegister ( const MachineRegisterInfo MRI,
const TargetRegisterClass RC,
const MachineFunction MF,
bool  ReserveHighestRegister = false 
) const

Returns a lowest register that is not used at any point in the function.

If all registers are used, then this function will return AMDGPU::NoRegister. If ReserveHighestRegister = true, then return highest unused register.

Definition at line 2964 of file SIRegisterInfo.cpp.

References MRI, and llvm::reverse().

◆ get32BitRegister()

MCPhysReg SIRegisterInfo::get32BitRegister ( MCPhysReg  Reg) const

Definition at line 3214 of file SIRegisterInfo.cpp.

References assert().

Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::foldImmediate().

◆ getAGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getAGPRClassForBitWidth ( unsigned  BitWidth) const

◆ getAlignedHighSGPRForRC()

MCRegister SIRegisterInfo::getAlignedHighSGPRForRC ( const MachineFunction MF,
const unsigned  Align,
const TargetRegisterClass RC 
) const

Return the largest available SGPR aligned to Align for the register class RC.

Definition at line 551 of file SIRegisterInfo.cpp.

References llvm::alignDown(), and llvm::GCNSubtarget::getMaxNumSGPRs().

Referenced by reservedPrivateSegmentBufferReg().

◆ getAllAGPRRegMask()

const uint32_t * SIRegisterInfo::getAllAGPRRegMask ( ) const

Definition at line 529 of file SIRegisterInfo.cpp.

◆ getAllAllocatableSRegMask()

const uint32_t * SIRegisterInfo::getAllAllocatableSRegMask ( ) const

Definition at line 537 of file SIRegisterInfo.cpp.

◆ getAllSGPR128()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR128 ( const MachineFunction MF) const

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 3266 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::getMaxNumSGPRs().

◆ getAllSGPR32()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR32 ( const MachineFunction MF) const

Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 3276 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::getMaxNumSGPRs().

◆ getAllSGPR64()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR64 ( const MachineFunction MF) const

Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 3271 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::getMaxNumSGPRs().

◆ getAllVectorRegMask()

const uint32_t * SIRegisterInfo::getAllVectorRegMask ( ) const

Definition at line 533 of file SIRegisterInfo.cpp.

◆ getAllVGPRRegMask()

const uint32_t * SIRegisterInfo::getAllVGPRRegMask ( ) const

Definition at line 525 of file SIRegisterInfo.cpp.

◆ getBaseRegister()

Register SIRegisterInfo::getBaseRegister ( ) const

◆ getBoolRC()

const TargetRegisterClass * llvm::SIRegisterInfo::getBoolRC ( ) const
inline

◆ getCalleeSavedRegs()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegs ( const MachineFunction MF) const
override

◆ getCalleeSavedRegsViaCopy()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy ( const MachineFunction MF) const

Definition at line 414 of file SIRegisterInfo.cpp.

◆ getCallPreservedMask()

const uint32_t * SIRegisterInfo::getCallPreservedMask ( const MachineFunction MF,
CallingConv::ID  CC 
) const
override

◆ getChannelFromSubReg()

unsigned llvm::SIRegisterInfo::getChannelFromSubReg ( unsigned  SubReg) const
inline

Definition at line 388 of file SIRegisterInfo.h.

References SubReg.

Referenced by expandSGPRCopy(), and llvm::SIInstrInfo::verifyInstruction().

◆ getCompatibleSubRegClass()

const TargetRegisterClass * SIRegisterInfo::getCompatibleSubRegClass ( const TargetRegisterClass SuperRC,
const TargetRegisterClass SubRC,
unsigned  SubIdx 
) const

Returns a register class which is compatible with SuperRC, such that a subregister exists with class SubRC with subregister index SubIdx.

If this is impossible (e.g., an unaligned subregister index within a register tuple), return null.

Definition at line 2912 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::hasSubClassEq().

Referenced by llvm::SIInstrInfo::verifyInstruction().

◆ getConstrainedRegClassForOperand()

const TargetRegisterClass * SIRegisterInfo::getConstrainedRegClassForOperand ( const MachineOperand MO,
const MachineRegisterInfo MRI 
) const
override

◆ getCrossCopyRegClass()

const TargetRegisterClass * SIRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass RC) const
override

Returns a legal register class to copy a register in the specified class to or from.

If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.

Definition at line 950 of file SIRegisterInfo.cpp.

References getEquivalentVGPRClass(), getWaveMaskRegClass(), llvm::GCNSubtarget::hasGFX90AInsts(), and isAGPRClass().

◆ getCSRFirstUseCost()

unsigned llvm::SIRegisterInfo::getCSRFirstUseCost ( ) const
inlineoverride

Definition at line 102 of file SIRegisterInfo.h.

◆ getEquivalentAGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass ( const TargetRegisterClass SRC) const
Returns
An AGPR reg class with the same width as SRC

Definition at line 2894 of file SIRegisterInfo.cpp.

References assert(), getAGPRClassForBitWidth(), and Size.

Referenced by llvm::SIInstrInfo::legalizeOperands().

◆ getEquivalentSGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass ( const TargetRegisterClass VRC) const
Returns
A SGPR reg class with the same width as SRC

Definition at line 2902 of file SIRegisterInfo.cpp.

References assert(), getSGPRClassForBitWidth(), and Size.

Referenced by llvm::SIInstrInfo::readlaneVGPRToSGPR().

◆ getEquivalentVGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass ( const TargetRegisterClass SRC) const

◆ getExec()

MCRegister SIRegisterInfo::getExec ( ) const

Definition at line 3135 of file SIRegisterInfo.cpp.

◆ getFrameIndexInstrOffset()

int64_t SIRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr MI,
int  Idx 
) const
override

◆ getFrameRegister()

Register SIRegisterInfo::getFrameRegister ( const MachineFunction MF) const
override

◆ getHWRegIndex()

unsigned llvm::SIRegisterInfo::getHWRegIndex ( MCRegister  Reg) const
inline

◆ getLargestLegalSuperClass()

const TargetRegisterClass * SIRegisterInfo::getLargestLegalSuperClass ( const TargetRegisterClass RC,
const MachineFunction MF 
) const
override

◆ getNoPreservedMask()

const uint32_t * SIRegisterInfo::getNoPreservedMask ( ) const
override

Definition at line 439 of file SIRegisterInfo.cpp.

◆ getNumChannelsFromSubReg()

unsigned llvm::SIRegisterInfo::getNumChannelsFromSubReg ( unsigned  SubReg) const
inline

Definition at line 393 of file SIRegisterInfo.h.

References getNumCoveredRegs(), and SubReg.

◆ getNumCoveredRegs()

static unsigned llvm::SIRegisterInfo::getNumCoveredRegs ( LaneBitmask  LM)
inlinestatic

◆ getPointerRegClass()

const TargetRegisterClass * SIRegisterInfo::getPointerRegClass ( const MachineFunction MF,
unsigned  Kind = 0 
) const
override

Definition at line 941 of file SIRegisterInfo.cpp.

◆ getProperlyAlignedRC()

const TargetRegisterClass * SIRegisterInfo::getProperlyAlignedRC ( const TargetRegisterClass RC) const

◆ getRegAsmName()

StringRef SIRegisterInfo::getRegAsmName ( MCRegister  Reg) const
override

Definition at line 2608 of file SIRegisterInfo.cpp.

References llvm::AMDGPUInstPrinter::getRegisterName().

◆ getRegClass()

const TargetRegisterClass * SIRegisterInfo::getRegClass ( unsigned  RCID) const

◆ getRegClassAlignmentNumBits()

unsigned llvm::SIRegisterInfo::getRegClassAlignmentNumBits ( const TargetRegisterClass RC) const
inline

◆ getRegClassForOperandReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForOperandReg ( const MachineRegisterInfo MRI,
const MachineOperand MO 
) const

◆ getRegClassForReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForReg ( const MachineRegisterInfo MRI,
Register  Reg 
) const

◆ getRegClassForSizeOnBank()

const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank ( unsigned  Size,
const RegisterBank Bank 
) const

◆ getRegClassForTypeOnBank()

const TargetRegisterClass * llvm::SIRegisterInfo::getRegClassForTypeOnBank ( LLT  Ty,
const RegisterBank Bank 
) const
inline

◆ getRegPressureLimit()

unsigned SIRegisterInfo::getRegPressureLimit ( const TargetRegisterClass RC,
MachineFunction MF 
) const
override

◆ getRegPressureSetLimit()

unsigned SIRegisterInfo::getRegPressureSetLimit ( const MachineFunction MF,
unsigned  Idx 
) const
override

Definition at line 3070 of file SIRegisterInfo.cpp.

References getRegPressureLimit(), Idx, and llvm_unreachable.

◆ getRegSplitParts()

ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts ( const TargetRegisterClass RC,
unsigned  EltSize 
) const

◆ getRegUnitPressureSets()

const int * SIRegisterInfo::getRegUnitPressureSets ( unsigned  RegUnit) const
override

Definition at line 3084 of file SIRegisterInfo.cpp.

References llvm::Empty.

◆ getReservedRegs()

BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction MF) const
override

◆ getReturnAddressReg()

MCRegister SIRegisterInfo::getReturnAddressReg ( const MachineFunction MF) const

Definition at line 3093 of file SIRegisterInfo.cpp.

◆ getScratchInstrOffset()

int64_t SIRegisterInfo::getScratchInstrOffset ( const MachineInstr MI) const

◆ getSGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getSGPRClassForBitWidth ( unsigned  BitWidth)
static

◆ getSubRegAlignmentNumBits()

unsigned SIRegisterInfo::getSubRegAlignmentNumBits ( const TargetRegisterClass RC,
unsigned  SubReg 
) const

◆ getSubRegFromChannel()

unsigned SIRegisterInfo::getSubRegFromChannel ( unsigned  Channel,
unsigned  NumRegs = 1 
)
static

◆ getVCC()

MCRegister SIRegisterInfo::getVCC ( ) const

◆ getVectorSuperClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getVectorSuperClassForBitWidth ( unsigned  BitWidth) const

◆ getVGPR64Class()

const TargetRegisterClass * SIRegisterInfo::getVGPR64Class ( ) const

◆ getVGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getVGPRClassForBitWidth ( unsigned  BitWidth) const

◆ getWaveMaskRegClass()

const TargetRegisterClass * llvm::SIRegisterInfo::getWaveMaskRegClass ( ) const
inline

◆ hasAGPRs()

static bool llvm::SIRegisterInfo::hasAGPRs ( const TargetRegisterClass RC)
inlinestatic

◆ hasBasePointer()

bool SIRegisterInfo::hasBasePointer ( const MachineFunction MF) const

◆ hasSGPRs()

static bool llvm::SIRegisterInfo::hasSGPRs ( const TargetRegisterClass RC)
inlinestatic
Returns
true if this class contains SGPR registers.

Definition at line 240 of file SIRegisterInfo.h.

References llvm::HasSGPR, and llvm::TargetRegisterClass::TSFlags.

Referenced by isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), and isVSSuperClass().

◆ hasVectorRegisters()

static bool llvm::SIRegisterInfo::hasVectorRegisters ( const TargetRegisterClass RC)
inlinestatic
Returns
true if this class contains any vector registers.

Definition at line 245 of file SIRegisterInfo.h.

References hasAGPRs(), and hasVGPRs().

Referenced by llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().

◆ hasVGPRs()

static bool llvm::SIRegisterInfo::hasVGPRs ( const TargetRegisterClass RC)
inlinestatic

◆ isAGPR()

bool SIRegisterInfo::isAGPR ( const MachineRegisterInfo MRI,
Register  Reg 
) const

◆ isAGPRClass()

static bool llvm::SIRegisterInfo::isAGPRClass ( const TargetRegisterClass RC)
inlinestatic

◆ isAsmClobberable()

bool SIRegisterInfo::isAsmClobberable ( const MachineFunction MF,
MCRegister  PhysReg 
) const
override

◆ isChainScratchRegister()

bool SIRegisterInfo::isChainScratchRegister ( Register  VGPR)
static

Definition at line 443 of file SIRegisterInfo.cpp.

Referenced by llvm::SIMachineFunctionInfo::allocateWWMSpill().

◆ isDivergentRegClass()

bool llvm::SIRegisterInfo::isDivergentRegClass ( const TargetRegisterClass RC) const
inlineoverride

Definition at line 305 of file SIRegisterInfo.h.

References isSGPRClass().

◆ isFrameOffsetLegal()

bool SIRegisterInfo::isFrameOffsetLegal ( const MachineInstr MI,
Register  BaseReg,
int64_t  Offset 
) const
override

◆ isProperlyAlignedRC()

bool SIRegisterInfo::isProperlyAlignedRC ( const TargetRegisterClass RC) const

◆ isRegClassAligned()

bool llvm::SIRegisterInfo::isRegClassAligned ( const TargetRegisterClass RC,
unsigned  AlignNumBits 
) const
inline

Definition at line 440 of file SIRegisterInfo.h.

References assert(), and getRegClassAlignmentNumBits().

◆ isSGPRClass()

static bool llvm::SIRegisterInfo::isSGPRClass ( const TargetRegisterClass RC)
inlinestatic

◆ isSGPRClassID()

bool llvm::SIRegisterInfo::isSGPRClassID ( unsigned  RCID) const
inline
Returns
true if this class ID contains only SGPR registers

Definition at line 203 of file SIRegisterInfo.h.

References getRegClass(), and isSGPRClass().

◆ isSGPRReg()

bool SIRegisterInfo::isSGPRReg ( const MachineRegisterInfo MRI,
Register  Reg 
) const

◆ isUniformReg()

bool SIRegisterInfo::isUniformReg ( const MachineRegisterInfo MRI,
const RegisterBankInfo RBI,
Register  Reg 
) const
override

◆ isVectorRegister()

bool llvm::SIRegisterInfo::isVectorRegister ( const MachineRegisterInfo MRI,
Register  Reg 
) const
inline

Definition at line 297 of file SIRegisterInfo.h.

References isAGPR(), isVGPR(), MRI, and Reg.

◆ isVectorSuperClass()

bool llvm::SIRegisterInfo::isVectorSuperClass ( const TargetRegisterClass RC) const
inline
Returns
true only if this class contains both VGPR and AGPR registers

Definition at line 220 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by getProperlyAlignedRC(), and isProperlyAlignedRC().

◆ isVGPR()

bool SIRegisterInfo::isVGPR ( const MachineRegisterInfo MRI,
Register  Reg 
) const

◆ isVGPRClass()

static bool llvm::SIRegisterInfo::isVGPRClass ( const TargetRegisterClass RC)
inlinestatic
Returns
true if this class contains only VGPR registers

Definition at line 210 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by getLargestLegalSuperClass(), getProperlyAlignedRC(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getReservedRegs(), isProperlyAlignedRC(), and isVGPR().

◆ isVSSuperClass()

bool llvm::SIRegisterInfo::isVSSuperClass ( const TargetRegisterClass RC) const
inline
Returns
true only if this class contains both VGPR and SGPR registers

Definition at line 225 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

◆ materializeFrameBaseRegister()

Register SIRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock MBB,
int  FrameIdx,
int64_t  Offset 
) const
override

◆ needsFrameBaseReg()

bool SIRegisterInfo::needsFrameBaseReg ( MachineInstr MI,
int64_t  Offset 
) const
override

◆ opCanUseInlineConstant()

bool SIRegisterInfo::opCanUseInlineConstant ( unsigned  OpType) const
Returns
True if operands defined with this operand type can accept an inline constant. i.e. An integer value in the range (-16, 64) or -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.

Definition at line 2921 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

◆ opCanUseLiteralConstant()

bool SIRegisterInfo::opCanUseLiteralConstant ( unsigned  OpType) const
Returns
True if operands defined with this operand type can accept a literal constant (i.e. any 32-bit immediate).

Definition at line 2954 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

◆ requiresFrameIndexReplacementScavenging()

bool SIRegisterInfo::requiresFrameIndexReplacementScavenging ( const MachineFunction MF) const
override

◆ requiresFrameIndexScavenging()

bool SIRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction MF) const
override

Definition at line 769 of file SIRegisterInfo.cpp.

◆ requiresRegisterScavenging()

bool SIRegisterInfo::requiresRegisterScavenging ( const MachineFunction Fn) const
override

◆ requiresVirtualBaseRegisters()

bool SIRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction Fn) const
override

Definition at line 784 of file SIRegisterInfo.cpp.

◆ reservedPrivateSegmentBufferReg()

MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg ( const MachineFunction MF) const

Return the end register initially reserved for the scratch buffer in case spilling is needed.

Definition at line 559 of file SIRegisterInfo.cpp.

References getAlignedHighSGPRForRC().

◆ resolveFrameIndex()

void SIRegisterInfo::resolveFrameIndex ( MachineInstr MI,
Register  BaseReg,
int64_t  Offset 
) const
override

◆ restoreSGPR()

bool SIRegisterInfo::restoreSGPR ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS,
SlotIndexes Indexes = nullptr,
LiveIntervals LIS = nullptr,
bool  OnlyToVGPR = false,
bool  SpillToPhysVGPRLane = false 
) const

◆ shouldCoalesce()

bool SIRegisterInfo::shouldCoalesce ( MachineInstr MI,
const TargetRegisterClass SrcRC,
unsigned  SubReg,
const TargetRegisterClass DstRC,
unsigned  DstSubReg,
const TargetRegisterClass NewRC,
LiveIntervals LIS 
) const
override

Definition at line 3032 of file SIRegisterInfo.cpp.

◆ shouldRealignStack()

bool SIRegisterInfo::shouldRealignStack ( const MachineFunction MF) const
override

◆ shouldRewriteCopySrc()

bool SIRegisterInfo::shouldRewriteCopySrc ( const TargetRegisterClass DefRC,
unsigned  DefSubReg,
const TargetRegisterClass SrcRC,
unsigned  SrcSubReg 
) const
override

Definition at line 2930 of file SIRegisterInfo.cpp.

◆ spillEmergencySGPR()

bool SIRegisterInfo::spillEmergencySGPR ( MachineBasicBlock::iterator  MI,
MachineBasicBlock RestoreMBB,
Register  SGPR,
RegScavenger RS 
) const

◆ spillSGPR()

bool SIRegisterInfo::spillSGPR ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS,
SlotIndexes Indexes = nullptr,
LiveIntervals LIS = nullptr,
bool  OnlyToVGPR = false,
bool  SpillToPhysVGPRLane = false 
) const

◆ spillSGPRToVGPR()

bool llvm::SIRegisterInfo::spillSGPRToVGPR ( ) const
inline

The documentation for this class was generated from the following files: