LLVM
15.0.0git
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#include "Target/AMDGPU/SIRegisterInfo.h"
Classes | |
struct | SpilledReg |
Static Public Member Functions | |
static unsigned | getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1) |
static const LLVM_READONLY TargetRegisterClass * | getSGPRClassForBitWidth (unsigned BitWidth) |
static bool | isSGPRClass (const TargetRegisterClass *RC) |
static bool | isVGPRClass (const TargetRegisterClass *RC) |
static bool | isAGPRClass (const TargetRegisterClass *RC) |
static bool | hasVGPRs (const TargetRegisterClass *RC) |
static bool | hasAGPRs (const TargetRegisterClass *RC) |
static bool | hasSGPRs (const TargetRegisterClass *RC) |
static bool | hasVectorRegisters (const TargetRegisterClass *RC) |
static unsigned | getNumCoveredRegs (LaneBitmask LM) |
Definition at line 30 of file SIRegisterInfo.h.
SIRegisterInfo::SIRegisterInfo | ( | const GCNSubtarget & | ST | ) |
Definition at line 319 of file SIRegisterInfo.cpp.
References assert(), llvm::call_once(), E, llvm::MCRegister::from(), lo16(), llvm::M0(), llvm::BitVector::resize(), llvm::BitVector::set(), llvm::size(), and SubRegFromChannelTableWidthMap.
void SIRegisterInfo::buildSpillLoadStore | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | MI, | ||
const DebugLoc & | DL, | ||
unsigned | LoadStoreOp, | ||
int | Index, | ||
Register | ValueReg, | ||
bool | ValueIsKill, | ||
MCRegister | ScratchOffsetReg, | ||
int64_t | InstrOffset, | ||
MachineMemOperand * | MMO, | ||
RegScavenger * | RS, | ||
LivePhysRegs * | LiveRegs = nullptr |
||
) | const |
Definition at line 1270 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::commonAlignment(), llvm::LivePhysRegs::contains(), DL, llvm::numbers::e, llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getConstantBusLimit(), llvm::getDefRegState(), llvm::MachineMemOperand::getFlags(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), getFlatScratchSpillOpcode(), llvm::MachineFunction::getFrameInfo(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), getOffenMUBUFLoad(), getOffenMUBUFStore(), llvm::MachineBasicBlock::getParent(), llvm::MachineMemOperand::getPointerInfo(), llvm::AMDGPU::getRegBitWidth(), getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getSubRegFromChannel(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::MachinePointerInfo::getWithOffset(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::GCNSubtarget::hasGFX90AInsts(), i, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, isAGPRClass(), llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::RegScavenger::isRegUsed(), llvm::MachineRegisterInfo::isReserved(), llvm::RegState::Kill, MBB, MI, llvm::min(), llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineInstr::ReloadReuse, llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegister(), llvm::AMDGPU::CPol::SCC, llvm::MachineInstr::setAsmPrinterFlag(), llvm::RegScavenger::setRegUsed(), spillVGPRtoAGPR(), SubReg, and TII.
Referenced by buildVGPRSpillLoadStore(), and eliminateFrameIndex().
void SIRegisterInfo::buildVGPRSpillLoadStore | ( | SGPRSpillBuilder & | SB, |
int | Index, | ||
int | Offset, | ||
bool | IsLoad, | ||
bool | IsKill = true |
||
) | const |
Definition at line 1636 of file SIRegisterInfo.cpp.
References llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), buildSpillLoadStore(), llvm::SGPRSpillBuilder::DL, llvm::SGPRSpillBuilder::EltSize, llvm::GCNSubtarget::enableFlatScratch(), getBaseRegister(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getStackID(), hasBasePointer(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MF, llvm::SGPRSpillBuilder::MFI, llvm::SGPRSpillBuilder::MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::SGPRSpillBuilder::RS, llvm::TargetStackID::SGPRSpill, and llvm::SGPRSpillBuilder::TmpVGPR.
Referenced by llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), and llvm::SGPRSpillBuilder::restore().
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Definition at line 1973 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), buildSpillLoadStore(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::SIInstrFlags::FlatScratch, getBaseRegister(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSVS(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::AMDGPU::getNamedOperandIdx(), getNumSubRegsForSpillOp(), llvm::MachineInstr::getOpcode(), llvm::MachineInstrBuilder::getReg(), llvm::MachineOperand::getReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), hasBasePointer(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::AMDGPU::isInlinableLiteral32(), llvm::MachineOperand::isKill(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::RegScavenger::isRegUsed(), isSGPRClass(), llvm::Register::isValid(), llvm::RegState::Kill, llvm::M0(), MBB, MI, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::report_fatal_error(), restoreSGPR(), llvm::RegScavenger::scavengeRegister(), llvm::AMDGPU::CPol::SCC, llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), Shift, spillSGPR(), and TII.
bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
LiveIntervals * | LIS = nullptr |
||
) | const |
Special case of eliminateFrameIndex.
Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.
Definition at line 1940 of file SIRegisterInfo.cpp.
References llvm_unreachable, MI, restoreSGPR(), and spillSGPR().
MachineInstr * SIRegisterInfo::findReachingDef | ( | Register | Reg, |
unsigned | SubReg, | ||
MachineInstr & | Use, | ||
MachineRegisterInfo & | MRI, | ||
LiveIntervals * | LIS | ||
) | const |
Definition at line 2958 of file SIRegisterInfo.cpp.
References assert(), llvm::tgtok::Def, llvm::VNInfo::def, llvm::Pass::getAnalysis(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::MachineRegisterInfo::getMaxLaneMaskForVReg(), llvm::LiveIntervals::getRegUnit(), llvm::LiveRange::getVNInfoAt(), llvm::LiveIntervals::hasInterval(), llvm::LiveInterval::hasSubRanges(), llvm::SlotIndex::isValid(), llvm::MCRegisterInfo::DiffListIterator::isValid(), MRI, S, llvm::LiveInterval::subranges(), and SubReg.
MCRegister SIRegisterInfo::findUnusedRegister | ( | const MachineRegisterInfo & | MRI, |
const TargetRegisterClass * | RC, | ||
const MachineFunction & | MF, | ||
bool | ReserveHighestVGPR = false |
||
) | const |
Returns a lowest register that is not used at any point in the function.
If all registers are used, then this function will return AMDGPU::NoRegister. If ReserveHighestVGPR
= true, then return highest unused register.
Definition at line 2780 of file SIRegisterInfo.cpp.
References llvm::MachineRegisterInfo::isAllocatable(), llvm::MachineRegisterInfo::isPhysRegUsed(), MRI, and llvm::reverse().
Definition at line 3012 of file SIRegisterInfo.cpp.
References assert(), getPhysRegClass(), and lo16().
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::FoldImmediate().
const TargetRegisterClass * SIRegisterInfo::getAGPRClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2504 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedAGPRClassForBitWidth(), getAnyAGPRClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by getEquivalentAGPRClass(), getRegClassForSizeOnBank(), getSubRegClass(), and isProperlyAlignedRC().
Definition at line 517 of file SIRegisterInfo.cpp.
Definition at line 525 of file SIRegisterInfo.cpp.
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR128 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3078 of file SIRegisterInfo.cpp.
References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR32 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3090 of file SIRegisterInfo.cpp.
References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR64 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3084 of file SIRegisterInfo.cpp.
References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().
Definition at line 521 of file SIRegisterInfo.cpp.
Definition at line 513 of file SIRegisterInfo.cpp.
Register SIRegisterInfo::getBaseRegister | ( | ) | const |
Definition at line 511 of file SIRegisterInfo.cpp.
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().
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Definition at line 331 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::convertNonUniformIfRegion(), llvm::SIInstrInfo::convertNonUniformLoopRegion(), llvm::SIInstrInfo::getAddNoCarry(), llvm::GCNSubtarget::getBoolRC(), getRegClass(), llvm::SIInstrInfo::insertEQ(), llvm::SIInstrInfo::insertNE(), and llvm::SIInstrInfo::insertVectorSelect().
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Definition at line 390 of file SIRegisterInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, llvm::CallingConv::Cold, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::GCNSubtarget::hasGFX90AInsts().
const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy | ( | const MachineFunction * | MF | ) | const |
Definition at line 411 of file SIRegisterInfo.cpp.
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Definition at line 415 of file SIRegisterInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, llvm::CallingConv::Cold, llvm::CallingConv::Fast, and llvm::GCNSubtarget::hasGFX90AInsts().
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Definition at line 372 of file SIRegisterInfo.h.
References SubReg.
Referenced by expandSGPRCopy(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getCompatibleSubRegClass | ( | const TargetRegisterClass * | SuperRC, |
const TargetRegisterClass * | SubRC, | ||
unsigned | SubIdx | ||
) | const |
Returns a register class which is compatible with SuperRC
, such that a subregister exists with class SubRC
with subregister index SubIdx
.
If this is impossible (e.g., an unaligned subregister index within a register tuple), return null.
Definition at line 2728 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterClass::hasSubClassEq().
Referenced by llvm::SIInstrInfo::verifyInstruction().
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Definition at line 2920 of file SIRegisterInfo.cpp.
References llvm::PointerUnion< PTs >::dyn_cast(), llvm::MachineOperand::getReg(), getRegClassForTypeOnBank(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), llvm::MachineRegisterInfo::getType(), and MRI.
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Returns a legal register class to copy a register in the specified class to or from.
If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.
Definition at line 931 of file SIRegisterInfo.cpp.
References getEquivalentVGPRClass(), llvm::GCNSubtarget::hasGFX90AInsts(), and isAGPRClass().
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Definition at line 89 of file SIRegisterInfo.h.
const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC
Definition at line 2690 of file SIRegisterInfo.cpp.
References assert(), and getAGPRClassForBitWidth().
Referenced by llvm::SIInstrInfo::legalizeOperands().
const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass | ( | const TargetRegisterClass * | VRC | ) | const |
SRC
Definition at line 2698 of file SIRegisterInfo.cpp.
References assert(), and getSGPRClassForBitWidth().
Referenced by llvm::SIInstrInfo::readlaneVGPRToSGPR().
const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC
Definition at line 2682 of file SIRegisterInfo.cpp.
References assert(), and getVGPRClassForBitWidth().
Referenced by getCrossCopyRegClass(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALU(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
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Definition at line 778 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.
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Definition at line 490 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getFrameLowering(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIFrameLowering::hasFP(), and llvm::AMDGPUMachineFunction::isEntryFunction().
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and llvm::SIFrameLowering::getFrameIndexReference().
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Definition at line 165 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::copyPhysReg(), indirectCopyToAGPR(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 436 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterInfo::getLargestLegalSuperClass(), llvm::GCNSubtarget::hasMAIInsts(), isAGPRClass(), and isVGPRClass().
Referenced by llvm::SIInstrInfo::isLegalRegOperand().
Definition at line 431 of file SIRegisterInfo.cpp.
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Definition at line 377 of file SIRegisterInfo.h.
References getNumCoveredRegs(), and SubReg.
Referenced by getSubRegClass().
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Definition at line 361 of file SIRegisterInfo.h.
References llvm::countPopulation(), llvm::LaneBitmask::getAsInteger(), and llvm::BitmaskEnumDetail::Mask().
Referenced by getNumChannelsFromSubReg(), getUsedRegMask(), and llvm::GCNRegPressure::inc().
const TargetRegisterClass * SIRegisterInfo::getPhysRegClass | ( | MCRegister | Reg | ) | const |
Return the 'base' register class for this register.
e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
Definition at line 2603 of file SIRegisterInfo.cpp.
Referenced by llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::FoldImmediate(), get32BitRegister(), llvm::SIInstrInfo::getOpRegClass(), getRegClassForReg(), isSGPRReg(), and llvm::SGPRSpillBuilder::SGPRSpillBuilder().
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Definition at line 922 of file SIRegisterInfo.cpp.
const TargetRegisterClass * SIRegisterInfo::getProperlyAlignedRC | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 3045 of file SIRegisterInfo.cpp.
References getAlignedAGPRClassForBitWidth(), getAlignedVectorSuperClassForBitWidth(), getAlignedVGPRClassForBitWidth(), isAGPRClass(), isVectorSuperClass(), isVGPRClass(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by adjustAllocatableRegClass().
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Definition at line 2391 of file SIRegisterInfo.cpp.
References llvm::AMDGPUInstPrinter::getRegisterName().
const TargetRegisterClass * SIRegisterInfo::getRegClass | ( | unsigned | RCID | ) | const |
Definition at line 2943 of file SIRegisterInfo.cpp.
References getBoolRC(), and getRegClass().
Referenced by adjustAllocatableRegClass(), llvm::SIInstrInfo::getOpSize(), llvm::SIInstrInfo::insertVectorSelect(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIInstrInfo::isOperandLegal(), isSGPRClassID(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALU(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getRegClassForReg | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2812 of file SIRegisterInfo.cpp.
References getPhysRegClass(), llvm::MachineRegisterInfo::getRegClass(), and MRI.
Referenced by buildSpillLoadStore(), isAGPR(), isVGPR(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::moveToVALU(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank | ( | unsigned | Size, |
const RegisterBank & | Bank | ||
) | const |
Definition at line 2901 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), llvm::RegisterBank::getID(), getSGPRClassForBitWidth(), getVGPRClassForBitWidth(), llvm_unreachable, and llvm::max().
Referenced by getRegClassForTypeOnBank().
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Definition at line 323 of file SIRegisterInfo.h.
References getRegClassForSizeOnBank(), and llvm::LLT::getSizeInBits().
Referenced by getConstrainedRegClassForOperand().
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Definition at line 2853 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFunction(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize(), and llvm::min().
Referenced by getRegPressureSetLimit(), and indirectCopyToAGPR().
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Definition at line 2872 of file SIRegisterInfo.cpp.
References getRegPressureLimit(), and llvm_unreachable.
ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts | ( | const TargetRegisterClass * | RC, |
unsigned | EltSize | ||
) | const |
Definition at line 2796 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getRegBitWidth(), llvm::makeArrayRef(), and llvm::TargetRegisterClass::MC.
Referenced by llvm::SIInstrInfo::copyPhysReg(), expandSGPRCopy(), llvm::SIInstrInfo::materializeImmediate(), and llvm::SGPRSpillBuilder::SGPRSpillBuilder().
Definition at line 2886 of file SIRegisterInfo.cpp.
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Definition at line 545 of file SIRegisterInfo.cpp.
References assert(), contains(), llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs(), getBaseRegister(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs(), hasBasePointer(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMAIInsts(), i, lo16(), llvm::Low, llvm::M0(), llvm::BitVector::set(), llvm::SIMachineFunctionInfo::usesAGPRs(), and llvm::SIMachineFunctionInfo::WWMReservedRegs.
MCRegister SIRegisterInfo::getReturnAddressReg | ( | const MachineFunction & | MF | ) | const |
Definition at line 2895 of file SIRegisterInfo.cpp.
int64_t SIRegisterInfo::getScratchInstrOffset | ( | const MachineInstr * | MI | ) | const |
Definition at line 770 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.
Referenced by getFrameIndexInstrOffset(), isFrameOffsetLegal(), and needsFrameBaseReg().
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Definition at line 2573 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by getEquivalentSGPRClass(), getRegClassForSizeOnBank(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), and getSubRegClass().
const TargetRegisterClass * SIRegisterInfo::getSubRegClass | ( | const TargetRegisterClass * | RC, |
unsigned | SubIdx | ||
) | const |
RC
for the given SubIdx
. If SubIdx
equals NoSubRegister, RC
will be returned. Definition at line 2707 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), getNumChannelsFromSubReg(), getSGPRClassForBitWidth(), getVectorSuperClassForBitWidth(), getVGPRClassForBitWidth(), isAGPRClass(), isVectorSuperClass(), and isVGPRClass().
Referenced by llvm::SIInstrInfo::verifyInstruction().
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Channel
(e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) Definition at line 529 of file SIRegisterInfo.cpp.
References assert(), llvm::size(), and SubRegFromChannelTableWidthMap.
Referenced by llvm::SITargetLowering::AddIMGInit(), buildSpillLoadStore(), computeIndirectRegAndOffset(), expandSGPRCopy(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
MCRegister SIRegisterInfo::getVCC | ( | ) | const |
Definition at line 2932 of file SIRegisterInfo.cpp.
Referenced by llvm::SIInstrInfo::getAddNoCarry(), and llvm::SIInstrInfo::moveToVALU().
const TargetRegisterClass * SIRegisterInfo::getVectorSuperClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2562 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedVectorSuperClassForBitWidth(), getAnyVectorSuperClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by getSubRegClass(), and isProperlyAlignedRC().
const TargetRegisterClass * SIRegisterInfo::getVGPR64Class | ( | ) | const |
Definition at line 2936 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::legalizeOpWithMove().
const TargetRegisterClass * SIRegisterInfo::getVGPRClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2444 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedVGPRClassForBitWidth(), getAnyVGPRClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by getEquivalentVGPRClass(), getRegClassForSizeOnBank(), getSubRegClass(), and isProperlyAlignedRC().
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Definition at line 336 of file SIRegisterInfo.h.
Referenced by llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), and llvm::SIInstrInfo::moveToVALU().
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Definition at line 224 of file SIRegisterInfo.h.
References llvm::HasAGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), isVSSuperClass(), llvm::SIInstrInfo::legalizeOperandsVOP3(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
bool SIRegisterInfo::hasBasePointer | ( | const MachineFunction & | MF | ) | const |
Definition at line 504 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getNumFixedObjects(), and shouldRealignStack().
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().
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Definition at line 229 of file SIRegisterInfo.h.
References llvm::HasSGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), and isVSSuperClass().
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Definition at line 234 of file SIRegisterInfo.h.
References hasAGPRs(), and hasVGPRs().
Referenced by llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 219 of file SIRegisterInfo.h.
References llvm::HasVGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::expandPostRAPseudo(), hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), isVSSuperClass(), llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().
bool SIRegisterInfo::isAGPR | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2824 of file SIRegisterInfo.cpp.
References getRegClassForReg(), isAGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getVALUOp(), llvm::SIInstrInfo::isOperandLegal(), isVectorRegister(), llvm::SIInstrInfo::legalizeOperandsVOP2(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 204 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by buildSpillLoadStore(), llvm::SIInstrInfo::copyPhysReg(), getCrossCopyRegClass(), getLargestLegalSuperClass(), llvm::SIInstrInfo::getMovOpcode(), getProperlyAlignedRC(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), getSubRegClass(), isAGPR(), isProperlyAlignedRC(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIMachineFunctionInfo::usesAGPRs().
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Definition at line 720 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getRegInfo(), and llvm::MachineRegisterInfo::isReserved().
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Definition at line 3063 of file SIRegisterInfo.cpp.
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Definition at line 294 of file SIRegisterInfo.h.
References isSGPRClass().
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Definition at line 906 of file SIRegisterInfo.cpp.
References llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.
bool SIRegisterInfo::isProperlyAlignedRC | ( | const TargetRegisterClass & | RC | ) | const |
Definition at line 3029 of file SIRegisterInfo.cpp.
References getAGPRClassForBitWidth(), getVectorSuperClassForBitWidth(), getVGPRClassForBitWidth(), llvm::TargetRegisterClass::hasSuperClassEq(), isAGPRClass(), isVectorSuperClass(), isVGPRClass(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 187 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), eliminateFrameIndex(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getMovOpcode(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), isDivergentRegClass(), isSGPRClassID(), isSGPRReg(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::materializeImmediate(), llvm::SITargetLowering::requiresUniformRegister(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIInstrInfo::usesConstantBus().
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Definition at line 192 of file SIRegisterInfo.h.
References getRegClass(), and isSGPRClass().
bool SIRegisterInfo::isSGPRReg | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2671 of file SIRegisterInfo.cpp.
References getPhysRegClass(), llvm::MachineRegisterInfo::getRegClass(), isSGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::isOperandLegal(), llvm::SIInstrInfo::isVGPRCopy(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::mayReadEXEC(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 288 of file SIRegisterInfo.h.
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Definition at line 209 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by getProperlyAlignedRC(), getSubRegClass(), isProperlyAlignedRC(), llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().
bool SIRegisterInfo::isVGPR | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2817 of file SIRegisterInfo.cpp.
References getRegClassForReg(), isVGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::canShrink(), llvm::SIInstrInfo::FoldImmediate(), isVectorRegister(), and llvm::SIInstrInfo::legalizeOperandsVOP2().
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Definition at line 199 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by getLargestLegalSuperClass(), getProperlyAlignedRC(), getSubRegClass(), isProperlyAlignedRC(), and isVGPR().
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Definition at line 214 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
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Definition at line 806 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MipsISD::Ins, llvm::RegState::Kill, MBB, MRI, and TII.
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Definition at line 792 of file SIRegisterInfo.cpp.
References llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.
bool SIRegisterInfo::opCanUseInlineConstant | ( | unsigned | OpType | ) | const |
Definition at line 2737 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and tryAddToFoldList().
bool SIRegisterInfo::opCanUseLiteralConstant | ( | unsigned | OpType | ) | const |
Definition at line 2770 of file SIRegisterInfo.cpp.
References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal().
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Definition at line 758 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::hasStackObjects().
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Definition at line 749 of file SIRegisterInfo.cpp.
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Definition at line 738 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::hasCalls(), llvm::MachineFrameInfo::hasStackObjects(), and Info.
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Definition at line 764 of file SIRegisterInfo.cpp.
MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg | ( | const MachineFunction & | MF | ) | const |
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition at line 538 of file SIRegisterInfo.cpp.
References llvm::alignDown(), and llvm::GCNSubtarget::getMaxNumSGPRs().
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Definition at line 857 of file SIRegisterInfo.cpp.
References assert(), llvm::MachineOperand::ChangeToRegister(), llvm::SIInstrFlags::FlatScratch, llvm::MachineOperand::getImm(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm_unreachable, MI, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineOperand::setImm(), and TII.
bool SIRegisterInfo::restoreSGPR | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
LiveIntervals * | LIS = nullptr , |
||
bool | OnlyToVGPR = false |
||
) | const |
Definition at line 1788 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::numbers::e, llvm::ArrayRef< T >::empty(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills(), i, llvm::RegState::ImplicitDefine, llvm::LiveIntervals::InsertMachineInstrInMaps(), llvm::SIRegisterInfo::SpilledReg::Lane, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::min(), llvm::SGPRSpillBuilder::NumSubRegs, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::SIRegisterInfo::SpilledReg::VGPR.
Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().
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Definition at line 2832 of file SIRegisterInfo.cpp.
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Definition at line 725 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getInfo(), Info, and llvm::TargetRegisterInfo::shouldRealignStack().
Referenced by hasBasePointer().
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Definition at line 2746 of file SIRegisterInfo.cpp.
bool SIRegisterInfo::spillEmergencySGPR | ( | MachineBasicBlock::iterator | MI, |
MachineBasicBlock & | RestoreMBB, | ||
Register | SGPR, | ||
RegScavenger * | RS | ||
) | const |
Definition at line 1868 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::numbers::e, llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), i, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SGPRSpillBuilder::IsKill, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::min(), llvm::SGPRSpillBuilder::NumSubRegs, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::setMI(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::RegState::Undef.
bool SIRegisterInfo::spillSGPR | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
LiveIntervals * | LIS = nullptr , |
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bool | OnlyToVGPR = false |
||
) | const |
If OnlyToVGPR
is true, this will only succeed if this.
Definition at line 1669 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), assert(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::numbers::e, llvm::ArrayRef< T >::empty(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), i, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::LiveIntervals::InsertMachineInstrInMaps(), llvm::SGPRSpillBuilder::IsKill, llvm::SIRegisterInfo::SpilledReg::Lane, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::min(), llvm::SGPRSpillBuilder::NumSubRegs, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::ArrayRef< T >::size(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, llvm::RegState::Undef, and llvm::SIRegisterInfo::SpilledReg::VGPR.
Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().
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Definition at line 69 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().