LLVM 20.0.0git
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#include "Target/AMDGPU/SIRegisterInfo.h"
Classes | |
struct | SpilledReg |
Static Public Member Functions | |
static unsigned | getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1) |
static bool | isChainScratchRegister (Register VGPR) |
static LLVM_READONLY const TargetRegisterClass * | getSGPRClassForBitWidth (unsigned BitWidth) |
static bool | isSGPRClass (const TargetRegisterClass *RC) |
static bool | isVGPRClass (const TargetRegisterClass *RC) |
static bool | isAGPRClass (const TargetRegisterClass *RC) |
static bool | hasVGPRs (const TargetRegisterClass *RC) |
static bool | hasAGPRs (const TargetRegisterClass *RC) |
static bool | hasSGPRs (const TargetRegisterClass *RC) |
static bool | hasVectorRegisters (const TargetRegisterClass *RC) |
static unsigned | getNumCoveredRegs (LaneBitmask LM) |
Definition at line 32 of file SIRegisterInfo.h.
SIRegisterInfo::SIRegisterInfo | ( | const GCNSubtarget & | ST | ) |
Definition at line 320 of file SIRegisterInfo.cpp.
References assert(), llvm::call_once(), llvm::MCRegister::from(), Idx, llvm::AMDGPU::isHi(), llvm::Offset, llvm::BitVector::resize(), llvm::BitVector::set(), llvm::size(), Size, and SubRegFromChannelTableWidthMap.
void SIRegisterInfo::buildSpillLoadStore | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | MI, | ||
const DebugLoc & | DL, | ||
unsigned | LoadStoreOp, | ||
int | Index, | ||
Register | ValueReg, | ||
bool | ValueIsKill, | ||
MCRegister | ScratchOffsetReg, | ||
int64_t | InstrOffset, | ||
MachineMemOperand * | MMO, | ||
RegScavenger * | RS, | ||
LiveRegUnits * | LiveUnits = nullptr |
||
) | const |
Definition at line 1329 of file SIRegisterInfo.cpp.
References llvm::Add, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LiveRegUnits::available(), llvm::BuildMI(), llvm::commonAlignment(), DL, llvm::MachineBasicBlock::end(), llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getConstantBusLimit(), llvm::getDefRegState(), llvm::MachineMemOperand::getFlags(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), getFlatScratchSpillOpcode(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), getOffenMUBUFLoad(), getOffenMUBUFStore(), llvm::MachineBasicBlock::getParent(), llvm::MachineMemOperand::getPointerInfo(), llvm::AMDGPU::getRegBitWidth(), getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getSubRegFromChannel(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::MachinePointerInfo::getWithOffset(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, isAGPRClass(), llvm::AMDGPUMachineFunction::isBottomOfStack(), llvm::RegScavenger::isRegUsed(), llvm::MachineRegisterInfo::isReserved(), llvm::RegState::Kill, MBB, MI, llvm::MOLastUse, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineInstr::ReloadReuse, llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineInstr::setAsmPrinterFlag(), llvm::RegScavenger::setRegUsed(), Size, spillVGPRtoAGPR(), SubReg, llvm::AMDGPU::CPol::TH_LU, and TII.
Referenced by buildVGPRSpillLoadStore(), and eliminateFrameIndex().
void SIRegisterInfo::buildVGPRSpillLoadStore | ( | SGPRSpillBuilder & | SB, |
int | Index, | ||
int | Offset, | ||
bool | IsLoad, | ||
bool | IsKill = true |
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) | const |
Definition at line 1727 of file SIRegisterInfo.cpp.
References llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), buildSpillLoadStore(), llvm::SGPRSpillBuilder::DL, llvm::SGPRSpillBuilder::EltSize, llvm::GCNSubtarget::enableFlatScratch(), getBaseRegister(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getStackID(), hasBasePointer(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MF, llvm::SGPRSpillBuilder::MFI, llvm::SGPRSpillBuilder::MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::Offset, llvm::SGPRSpillBuilder::RS, llvm::TargetStackID::SGPRSpill, and llvm::SGPRSpillBuilder::TmpVGPR.
Referenced by llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), and llvm::SGPRSpillBuilder::restore().
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Definition at line 2074 of file SIRegisterInfo.cpp.
References llvm::Add, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), buildSpillLoadStore(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::SIInstrFlags::FlatScratch, getBaseRegister(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSVS(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::GCNSubtarget::getMaxWaveScratchSize(), llvm::AMDGPU::getNamedOperandIdx(), getNumSubRegsForSpillOp(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRForEXECCopy(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), hasBasePointer(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPU::hasNamedOperand(), I, llvm::AMDGPUMachineFunction::isBottomOfStack(), llvm::AMDGPU::isInlinableLiteral32(), llvm::MachineOperand::isKill(), llvm::RegScavenger::isRegUsed(), llvm::MachineRegisterInfo::isReserved(), isSGPRClass(), llvm::Register::isValid(), llvm::RegState::Kill, MBB, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::report_fatal_error(), restoreSGPR(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), spillSGPR(), and TII.
bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
SlotIndexes * | Indexes = nullptr , |
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LiveIntervals * | LIS = nullptr , |
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bool | SpillToPhysVGPRLane = false |
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) | const |
Special case of eliminateFrameIndex.
Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.
Definition at line 2035 of file SIRegisterInfo.cpp.
References llvm_unreachable, MI, restoreSGPR(), and spillSGPR().
MachineInstr * SIRegisterInfo::findReachingDef | ( | Register | Reg, |
unsigned | SubReg, | ||
MachineInstr & | Use, | ||
MachineRegisterInfo & | MRI, | ||
LiveIntervals * | LIS | ||
) | const |
Definition at line 3234 of file SIRegisterInfo.cpp.
References assert(), llvm::LiveIntervals::getDomTree(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::LiveIntervals::getRegUnit(), llvm::LiveRange::getVNInfoAt(), llvm::LiveIntervals::hasInterval(), llvm::LiveInterval::hasSubRanges(), llvm::SlotIndex::isValid(), MRI, llvm::LiveInterval::subranges(), and SubReg.
MCRegister SIRegisterInfo::findUnusedRegister | ( | const MachineRegisterInfo & | MRI, |
const TargetRegisterClass * | RC, | ||
const MachineFunction & | MF, | ||
bool | ReserveHighestRegister = false |
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) | const |
Returns a lowest register that is not used at any point in the function.
If all registers are used, then this function will return AMDGPU::NoRegister. If ReserveHighestRegister
= true, then return highest unused register.
Definition at line 3037 of file SIRegisterInfo.cpp.
References MRI, and llvm::reverse().
Definition at line 3287 of file SIRegisterInfo.cpp.
References assert().
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::foldImmediate().
const TargetRegisterClass * SIRegisterInfo::getAGPRClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2830 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedAGPRClassForBitWidth(), getAnyAGPRClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by getEquivalentAGPRClass(), getRegClassForSizeOnBank(), and isProperlyAlignedRC().
MCRegister SIRegisterInfo::getAlignedHighSGPRForRC | ( | const MachineFunction & | MF, |
const unsigned | Align, | ||
const TargetRegisterClass * | RC | ||
) | const |
Return the largest available SGPR aligned to Align
for the register class RC
.
Definition at line 551 of file SIRegisterInfo.cpp.
References llvm::alignDown(), and llvm::GCNSubtarget::getMaxNumSGPRs().
Referenced by reservedPrivateSegmentBufferReg().
Definition at line 529 of file SIRegisterInfo.cpp.
Definition at line 537 of file SIRegisterInfo.cpp.
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR128 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3339 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getMaxNumSGPRs().
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR32 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3349 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getMaxNumSGPRs().
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR64 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 3344 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getMaxNumSGPRs().
Definition at line 533 of file SIRegisterInfo.cpp.
Definition at line 525 of file SIRegisterInfo.cpp.
Register SIRegisterInfo::getBaseRegister | ( | ) | const |
Definition at line 523 of file SIRegisterInfo.cpp.
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().
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Definition at line 345 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::convertNonUniformIfRegion(), llvm::SIInstrInfo::convertNonUniformLoopRegion(), llvm::SIInstrInfo::getAddNoCarry(), llvm::GCNSubtarget::getBoolRC(), getRegClass(), llvm::SIInstrInfo::insertEQ(), llvm::SIInstrInfo::insertNE(), and llvm::SIInstrInfo::insertVectorSelect().
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Definition at line 391 of file SIRegisterInfo.cpp.
References llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, CC, llvm::CallingConv::Cold, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::GCNSubtarget::hasGFX90AInsts().
const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy | ( | const MachineFunction * | MF | ) | const |
Definition at line 414 of file SIRegisterInfo.cpp.
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Definition at line 418 of file SIRegisterInfo.cpp.
References llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, CC, llvm::CallingConv::Cold, llvm::CallingConv::Fast, and llvm::GCNSubtarget::hasGFX90AInsts().
Definition at line 388 of file SIRegisterInfo.h.
References SubReg.
Referenced by expandSGPRCopy(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getCompatibleSubRegClass | ( | const TargetRegisterClass * | SuperRC, |
const TargetRegisterClass * | SubRC, | ||
unsigned | SubIdx | ||
) | const |
Returns a register class which is compatible with SuperRC
, such that a subregister exists with class SubRC
with subregister index SubIdx
.
If this is impossible (e.g., an unaligned subregister index within a register tuple), return null.
Definition at line 2985 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterClass::hasSubClassEq().
Referenced by llvm::SIInstrInfo::verifyInstruction().
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Definition at line 3192 of file SIRegisterInfo.cpp.
References llvm::PointerUnion< PTs >::dyn_cast(), llvm::MachineOperand::getReg(), getRegClassForTypeOnBank(), and MRI.
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Returns a legal register class to copy a register in the specified class to or from.
If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.
Definition at line 950 of file SIRegisterInfo.cpp.
References getEquivalentVGPRClass(), getWaveMaskRegClass(), llvm::GCNSubtarget::hasGFX90AInsts(), and isAGPRClass().
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Definition at line 102 of file SIRegisterInfo.h.
const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC
Definition at line 2967 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), and Size.
Referenced by llvm::SIInstrInfo::legalizeOperands().
const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass | ( | const TargetRegisterClass * | VRC | ) | const |
SRC
Definition at line 2975 of file SIRegisterInfo.cpp.
References assert(), getSGPRClassForBitWidth(), and Size.
Referenced by llvm::SIInstrInfo::readlaneVGPRToSGPR().
const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC
Definition at line 2959 of file SIRegisterInfo.cpp.
References assert(), getVGPRClassForBitWidth(), and Size.
Referenced by getCrossCopyRegClass(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
MCRegister SIRegisterInfo::getExec | ( | ) | const |
Definition at line 3208 of file SIRegisterInfo.cpp.
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Definition at line 798 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), getScratchInstrOffset(), Idx, llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.
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Definition at line 502 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getFrameLowering(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIFrameLowering::hasFP(), and llvm::AMDGPUMachineFunction::isBottomOfStack().
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and llvm::SIFrameLowering::getFrameIndexReference().
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Definition at line 180 of file SIRegisterInfo.h.
References Reg.
Referenced by llvm::SIInstrInfo::copyPhysReg(), getReservedRegs(), indirectCopyToAGPR(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 448 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterInfo::getLargestLegalSuperClass(), llvm::GCNSubtarget::hasMAIInsts(), isAGPRClass(), and isVGPRClass().
Referenced by llvm::SIInstrInfo::isLegalRegOperand().
Definition at line 439 of file SIRegisterInfo.cpp.
Definition at line 393 of file SIRegisterInfo.h.
References getNumCoveredRegs(), and SubReg.
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Definition at line 377 of file SIRegisterInfo.h.
References llvm::LaneBitmask::getAsInteger(), and llvm::popcount().
Referenced by getNumChannelsFromSubReg(), and llvm::GCNRegPressure::inc().
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Definition at line 941 of file SIRegisterInfo.cpp.
const TargetRegisterClass * SIRegisterInfo::getProperlyAlignedRC | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 3320 of file SIRegisterInfo.cpp.
References getAlignedAGPRClassForBitWidth(), getAlignedVectorSuperClassForBitWidth(), getAlignedVGPRClassForBitWidth(), isAGPRClass(), isVectorSuperClass(), isVGPRClass(), llvm::GCNSubtarget::needsAlignedVGPRs(), and Size.
Referenced by adjustAllocatableRegClass().
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Definition at line 2681 of file SIRegisterInfo.cpp.
References llvm::AMDGPUInstPrinter::getRegisterName().
const TargetRegisterClass * SIRegisterInfo::getRegClass | ( | unsigned | RCID | ) | const |
Definition at line 3219 of file SIRegisterInfo.cpp.
References getBoolRC().
Referenced by adjustAllocatableRegClass(), llvm::SIInstrInfo::foldImmediate(), llvm::SIInstrInfo::getOpSize(), llvm::SIInstrInfo::insertVectorSelect(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIInstrInfo::isOperandLegal(), isSGPRClassID(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 435 of file SIRegisterInfo.h.
References llvm::RegTupleAlignUnitsMask, and llvm::TargetRegisterClass::TSFlags.
Referenced by isRegClassAligned().
const TargetRegisterClass * SIRegisterInfo::getRegClassForOperandReg | ( | const MachineRegisterInfo & | MRI, |
const MachineOperand & | MO | ||
) | const |
Definition at line 3084 of file SIRegisterInfo.cpp.
References llvm::MachineOperand::getReg(), getRegClassForReg(), llvm::MachineOperand::getSubReg(), and MRI.
const TargetRegisterClass * SIRegisterInfo::getRegClassForReg | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 3078 of file SIRegisterInfo.cpp.
References MRI.
Referenced by buildSpillLoadStore(), getRegClassForOperandReg(), isAGPR(), llvm::SIInstrInfo::isBasicBlockPrologue(), isVGPR(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank | ( | unsigned | Size, |
const RegisterBank & | Bank | ||
) | const |
Definition at line 3172 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), llvm::RegisterBank::getID(), getSGPRClassForBitWidth(), getVGPRClassForBitWidth(), llvm_unreachable, Size, and llvm::AMDGPUSubtarget::useRealTrue16Insts().
Referenced by getRegClassForTypeOnBank().
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Definition at line 337 of file SIRegisterInfo.h.
References getRegClassForSizeOnBank(), and llvm::LLT::getSizeInBits().
Referenced by getConstrainedRegClassForOperand().
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Definition at line 3126 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFunction(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), and llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize().
Referenced by getRegPressureSetLimit(), and indirectCopyToAGPR().
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Definition at line 3143 of file SIRegisterInfo.cpp.
References getRegPressureLimit(), Idx, and llvm_unreachable.
ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts | ( | const TargetRegisterClass * | RC, |
unsigned | EltSize | ||
) | const |
Definition at line 3062 of file SIRegisterInfo.cpp.
References assert(), and llvm::AMDGPU::getRegBitWidth().
Referenced by llvm::SIInstrInfo::copyPhysReg(), expandSGPRCopy(), llvm::SIInstrInfo::materializeImmediate(), and llvm::SGPRSpillBuilder::SGPRSpillBuilder().
Definition at line 3157 of file SIRegisterInfo.cpp.
References llvm::Empty.
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Definition at line 564 of file SIRegisterInfo.cpp.
References assert(), llvm::divideCeil(), llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs(), getBaseRegister(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), getHWRegIndex(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getLongBranchReservedReg(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRForEXECCopy(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs(), llvm::SIMachineFunctionInfo::getWWMReservedRegs(), hasBasePointer(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMAIInsts(), isAGPRClass(), isSGPRClass(), isVGPRClass(), llvm::Reserved, and llvm::SIMachineFunctionInfo::usesAGPRs().
MCRegister SIRegisterInfo::getReturnAddressReg | ( | const MachineFunction & | MF | ) | const |
Definition at line 3166 of file SIRegisterInfo.cpp.
int64_t SIRegisterInfo::getScratchInstrOffset | ( | const MachineInstr * | MI | ) | const |
Definition at line 790 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.
Referenced by getFrameIndexInstrOffset(), isFrameOffsetLegal(), and needsFrameBaseReg().
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Definition at line 2913 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by getEquivalentSGPRClass(), getRegClassForSizeOnBank(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isIllegalRegisterType(), moreElementsToNextExistingRegClass(), and AMDGPUDAGToDAGISel::Select().
unsigned SIRegisterInfo::getSubRegAlignmentNumBits | ( | const TargetRegisterClass * | RC, |
unsigned | SubReg | ||
) | const |
Definition at line 3354 of file SIRegisterInfo.cpp.
References llvm::HasAGPR, llvm::HasSGPR, llvm::HasVGPR, llvm::RegKindMask, SubReg, and llvm::TargetRegisterClass::TSFlags.
Channel
(e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) Definition at line 541 of file SIRegisterInfo.cpp.
References assert(), llvm::size(), and SubRegFromChannelTableWidthMap.
Referenced by llvm::SITargetLowering::AddMemOpInit(), buildRegSequence(), buildRegSequence32(), buildSpillLoadStore(), computeIndirectRegAndOffset(), expandSGPRCopy(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), and AMDGPUDAGToDAGISel::SelectBuildVector().
MCRegister SIRegisterInfo::getVCC | ( | ) | const |
Definition at line 3204 of file SIRegisterInfo.cpp.
Referenced by llvm::SIInstrInfo::getAddNoCarry(), and llvm::SIInstrInfo::moveToVALUImpl().
const TargetRegisterClass * SIRegisterInfo::getVectorSuperClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2904 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedVectorSuperClassForBitWidth(), getAnyVectorSuperClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by isProperlyAlignedRC().
const TargetRegisterClass * SIRegisterInfo::getVGPR64Class | ( | ) | const |
Definition at line 3212 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by llvm::SIInstrInfo::copyPhysReg().
const TargetRegisterClass * SIRegisterInfo::getVGPRClassForBitWidth | ( | unsigned | BitWidth | ) | const |
Definition at line 2754 of file SIRegisterInfo.cpp.
References llvm::BitWidth, getAlignedVGPRClassForBitWidth(), getAnyVGPRClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by getEquivalentVGPRClass(), getRegClassForSizeOnBank(), and isProperlyAlignedRC().
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Definition at line 350 of file SIRegisterInfo.h.
Referenced by llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), getCrossCopyRegClass(), and llvm::SIInstrInfo::moveToVALUImpl().
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Definition at line 235 of file SIRegisterInfo.h.
References llvm::HasAGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), isVSSuperClass(), llvm::SIInstrInfo::legalizeOperandsVOP3(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
bool SIRegisterInfo::hasBasePointer | ( | const MachineFunction & | MF | ) | const |
Definition at line 516 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getNumFixedObjects(), and shouldRealignStack().
Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().
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Definition at line 240 of file SIRegisterInfo.h.
References llvm::HasSGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), and isVSSuperClass().
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Definition at line 245 of file SIRegisterInfo.h.
References hasAGPRs(), and hasVGPRs().
Referenced by llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 230 of file SIRegisterInfo.h.
References llvm::HasVGPR, and llvm::TargetRegisterClass::TSFlags.
Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::expandPostRAPseudo(), hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), isVSSuperClass(), llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().
bool SIRegisterInfo::isAGPR | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 3097 of file SIRegisterInfo.cpp.
References getRegClassForReg(), isAGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::foldImmediate(), llvm::SIInstrInfo::getVALUOp(), llvm::SIInstrInfo::isOperandLegal(), isVectorRegister(), llvm::SIInstrInfo::legalizeOperandsVOP2(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 215 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by buildSpillLoadStore(), llvm::SIInstrInfo::copyPhysReg(), getCrossCopyRegClass(), getLargestLegalSuperClass(), llvm::SIInstrInfo::getMovOpcode(), getProperlyAlignedRC(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getReservedRegs(), isAGPR(), isProperlyAlignedRC(), llvm::SIInstrInfo::legalizeOperands(), and llvm::SIMachineFunctionInfo::usesAGPRs().
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Definition at line 740 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getRegInfo(), and llvm::MachineRegisterInfo::isReserved().
Definition at line 443 of file SIRegisterInfo.cpp.
Referenced by llvm::SIMachineFunctionInfo::allocateWWMSpill().
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Definition at line 305 of file SIRegisterInfo.h.
References isSGPRClass().
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Definition at line 925 of file SIRegisterInfo.cpp.
References llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.
bool SIRegisterInfo::isProperlyAlignedRC | ( | const TargetRegisterClass & | RC | ) | const |
Definition at line 3304 of file SIRegisterInfo.cpp.
References getAGPRClassForBitWidth(), getVectorSuperClassForBitWidth(), getVGPRClassForBitWidth(), llvm::TargetRegisterClass::hasSuperClassEq(), isAGPRClass(), isVectorSuperClass(), isVGPRClass(), and llvm::GCNSubtarget::needsAlignedVGPRs().
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 440 of file SIRegisterInfo.h.
References assert(), and getRegClassAlignmentNumBits().
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Definition at line 198 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), eliminateFrameIndex(), llvm::SIInstrInfo::foldImmediate(), llvm::SIInstrInfo::getInstructionUniformity(), llvm::SIInstrInfo::getMovOpcode(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getReservedRegs(), llvm::SIInstrInfo::isBasicBlockPrologue(), isDivergentRegClass(), llvm::SIInstrInfo::isSafeToSink(), isSGPRClassID(), isSGPRReg(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::materializeImmediate(), llvm::SITargetLowering::requiresUniformRegister(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIInstrInfo::usesConstantBus().
Definition at line 203 of file SIRegisterInfo.h.
References getRegClass(), and isSGPRClass().
bool SIRegisterInfo::isSGPRReg | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2948 of file SIRegisterInfo.cpp.
References isSGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::foldImmediate(), llvm::PhiLoweringHelper::isLaneMaskReg(), llvm::SIInstrInfo::isOperandLegal(), llvm::SIInstrInfo::isVGPRCopy(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::mayReadEXEC(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), and llvm::SIInstrInfo::verifyInstruction().
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Definition at line 3052 of file SIRegisterInfo.cpp.
References llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::isDivergentRegBank(), and MRI.
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Definition at line 220 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by getProperlyAlignedRC(), and isProperlyAlignedRC().
bool SIRegisterInfo::isVGPR | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 3090 of file SIRegisterInfo.cpp.
References getRegClassForReg(), isVGPRClass(), and MRI.
Referenced by llvm::SIInstrInfo::canShrink(), llvm::SIInstrInfo::foldImmediate(), isVectorRegister(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), and llvm::SIInstrInfo::moveToVALUImpl().
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Definition at line 210 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
Referenced by getLargestLegalSuperClass(), getProperlyAlignedRC(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getReservedRegs(), isProperlyAlignedRC(), and isVGPR().
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Definition at line 225 of file SIRegisterInfo.h.
References hasAGPRs(), hasSGPRs(), and hasVGPRs().
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Definition at line 826 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::RegState::Kill, MBB, MRI, llvm::Offset, and TII.
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Definition at line 812 of file SIRegisterInfo.cpp.
References llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.
Definition at line 2994 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal().
Definition at line 3027 of file SIRegisterInfo.cpp.
References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal().
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Definition at line 778 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::hasStackObjects().
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Definition at line 769 of file SIRegisterInfo.cpp.
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Definition at line 758 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::hasCalls(), llvm::MachineFrameInfo::hasStackObjects(), and Info.
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Definition at line 784 of file SIRegisterInfo.cpp.
MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg | ( | const MachineFunction & | MF | ) | const |
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition at line 559 of file SIRegisterInfo.cpp.
References getAlignedHighSGPRForRC().
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Definition at line 877 of file SIRegisterInfo.cpp.
References assert(), llvm::MachineOperand::ChangeToRegister(), llvm::SIInstrFlags::FlatScratch, llvm::MachineOperand::getImm(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm_unreachable, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineOperand::setImm(), and TII.
bool SIRegisterInfo::restoreSGPR | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
SlotIndexes * | Indexes = nullptr , |
||
LiveIntervals * | LIS = nullptr , |
||
bool | OnlyToVGPR = false , |
||
bool | SpillToPhysVGPRLane = false |
||
) | const |
Definition at line 1883 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::ArrayRef< T >::empty(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRSpillToPhysicalVGPRLanes(), llvm::SIMachineFunctionInfo::getSGPRSpillToVirtualVGPRLanes(), llvm::RegState::ImplicitDefine, llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::SlotIndexes::replaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, and llvm::SGPRSpillBuilder::TmpVGPR.
Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().
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Definition at line 3105 of file SIRegisterInfo.cpp.
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Definition at line 745 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getInfo(), Info, and llvm::TargetRegisterInfo::shouldRealignStack().
Referenced by hasBasePointer().
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Definition at line 3003 of file SIRegisterInfo.cpp.
bool SIRegisterInfo::spillEmergencySGPR | ( | MachineBasicBlock::iterator | MI, |
MachineBasicBlock & | RestoreMBB, | ||
Register | SGPR, | ||
RegScavenger * | RS | ||
) | const |
Definition at line 1963 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SGPRSpillBuilder::IsKill, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::setMI(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::RegState::Undef.
bool SIRegisterInfo::spillSGPR | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
SlotIndexes * | Indexes = nullptr , |
||
LiveIntervals * | LIS = nullptr , |
||
bool | OnlyToVGPR = false , |
||
bool | SpillToPhysVGPRLane = false |
||
) | const |
If OnlyToVGPR
is true, this will only succeed if this manages to find a free VGPR lane to spill.
Definition at line 1760 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), assert(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::ArrayRef< T >::empty(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRSpillToPhysicalVGPRLanes(), llvm::SIMachineFunctionInfo::getSGPRSpillToVirtualVGPRLanes(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::SGPRSpillBuilder::IsKill, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::SlotIndexes::replaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::ArrayRef< T >::size(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::RegState::Undef.
Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().
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Definition at line 71 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().