LLVM  9.0.0svn
Public Member Functions | List of all members
llvm::SIRegisterInfo Class Referencefinal

#include "Target/AMDGPU/SIRegisterInfo.h"

Inheritance diagram for llvm::SIRegisterInfo:
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Public Member Functions

 SIRegisterInfo (const GCNSubtarget &ST)
 
bool spillSGPRToVGPR () const
 
bool spillSGPRToSMEM () const
 
unsigned reservedPrivateSegmentBufferReg (const MachineFunction &MF) const
 Return the end register initially reserved for the scratch buffer in case spilling is needed. More...
 
unsigned reservedPrivateSegmentWaveByteOffsetReg (const MachineFunction &MF) const
 Return the end register initially reserved for the scratch wave offset in case spilling is needed. More...
 
BitVector getReservedRegs (const MachineFunction &MF) const override
 
const MCPhysReggetCalleeSavedRegs (const MachineFunction *MF) const override
 
const MCPhysReggetCalleeSavedRegsViaCopy (const MachineFunction *MF) const
 
const uint32_tgetCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override
 
unsigned getCSRFirstUseCost () const override
 
Register getFrameRegister (const MachineFunction &MF) const override
 
bool canRealignStack (const MachineFunction &MF) const override
 
bool requiresRegisterScavenging (const MachineFunction &Fn) const override
 
bool requiresFrameIndexScavenging (const MachineFunction &MF) const override
 
bool requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const override
 
bool requiresVirtualBaseRegisters (const MachineFunction &Fn) const override
 
bool trackLivenessAfterRegAlloc (const MachineFunction &MF) const override
 
int64_t getMUBUFInstrOffset (const MachineInstr *MI) const
 
int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override
 
bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
 
void materializeFrameBaseRegister (MachineBasicBlock *MBB, unsigned BaseReg, int FrameIdx, int64_t Offset) const override
 
void resolveFrameIndex (MachineInstr &MI, unsigned BaseReg, int64_t Offset) const override
 
bool isFrameOffsetLegal (const MachineInstr *MI, unsigned BaseReg, int64_t Offset) const override
 
const TargetRegisterClassgetPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override
 
bool spillSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
 If OnlyToVGPR is true, this will only succeed if this. More...
 
bool restoreSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, bool OnlyToVGPR=false) const
 
void eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
 
bool eliminateSGPRToVGPRSpillFrameIndex (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS) const
 Special case of eliminateFrameIndex. More...
 
StringRef getRegAsmName (unsigned Reg) const override
 
unsigned getHWRegIndex (unsigned Reg) const
 
const TargetRegisterClassgetPhysRegClass (unsigned Reg) const
 Return the 'base' register class for this register. More...
 
bool isSGPRClass (const TargetRegisterClass *RC) const
 
bool isSGPRClassID (unsigned RCID) const
 
bool isSGPRReg (const MachineRegisterInfo &MRI, unsigned Reg) const
 
bool hasVGPRs (const TargetRegisterClass *RC) const
 
bool hasAGPRs (const TargetRegisterClass *RC) const
 
bool hasVectorRegisters (const TargetRegisterClass *RC) const
 
const TargetRegisterClassgetEquivalentVGPRClass (const TargetRegisterClass *SRC) const
 
const TargetRegisterClassgetEquivalentAGPRClass (const TargetRegisterClass *SRC) const
 
const TargetRegisterClassgetEquivalentSGPRClass (const TargetRegisterClass *VRC) const
 
const TargetRegisterClassgetSubRegClass (const TargetRegisterClass *RC, unsigned SubIdx) const
 
bool shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
 
bool opCanUseLiteralConstant (unsigned OpType) const
 
bool opCanUseInlineConstant (unsigned OpType) const
 
unsigned findUnusedRegister (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF) const
 Returns a register that is not used at any point in the function. More...
 
unsigned getSGPRPressureSet () const
 
unsigned getVGPRPressureSet () const
 
unsigned getAGPRPressureSet () const
 
const TargetRegisterClassgetRegClassForReg (const MachineRegisterInfo &MRI, unsigned Reg) const
 
bool isVGPR (const MachineRegisterInfo &MRI, unsigned Reg) const
 
bool isAGPR (const MachineRegisterInfo &MRI, unsigned Reg) const
 
bool isVectorRegister (const MachineRegisterInfo &MRI, unsigned Reg) const
 
virtual bool isDivergentRegClass (const TargetRegisterClass *RC) const override
 
bool isSGPRPressureSet (unsigned SetID) const
 
bool isVGPRPressureSet (unsigned SetID) const
 
bool isAGPRPressureSet (unsigned SetID) const
 
ArrayRef< int16_t > getRegSplitParts (const TargetRegisterClass *RC, unsigned EltSize) const
 
bool shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
 
unsigned getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override
 
unsigned getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const override
 
const int * getRegUnitPressureSets (unsigned RegUnit) const override
 
unsigned getReturnAddressReg (const MachineFunction &MF) const
 
const TargetRegisterClassgetRegClassForSizeOnBank (unsigned Size, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
 
const TargetRegisterClassgetRegClassForTypeOnBank (LLT Ty, const RegisterBank &Bank, const MachineRegisterInfo &MRI) const
 
const TargetRegisterClassgetConstrainedRegClassForOperand (const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
 
const TargetRegisterClassgetBoolRC () const
 
const TargetRegisterClassgetWaveMaskRegClass () const
 
unsigned getVCC () const
 
const TargetRegisterClassgetRegClass (unsigned RCID) const
 
MachineInstrfindReachingDef (unsigned Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
 
const uint32_tgetAllVGPRRegMask () const
 
const uint32_tgetAllAllocatableSRegMask () const
 
- Public Member Functions inherited from llvm::AMDGPURegisterInfo
 AMDGPURegisterInfo ()
 
void reserveRegisterTuples (BitVector &, unsigned Reg) const
 

Additional Inherited Members

- Static Public Member Functions inherited from llvm::AMDGPURegisterInfo
static unsigned getSubRegFromChannel (unsigned Channel)
 

Detailed Description

Definition at line 28 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

◆ SIRegisterInfo()

SIRegisterInfo::SIRegisterInfo ( const GCNSubtarget ST)

Member Function Documentation

◆ canRealignStack()

bool SIRegisterInfo::canRealignStack ( const MachineFunction MF) const
override

◆ eliminateFrameIndex()

void SIRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI,
int  SPAdj,
unsigned  FIOperandNum,
RegScavenger RS 
) const
override

◆ eliminateSGPRToVGPRSpillFrameIndex()

bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS 
) const

Special case of eliminateFrameIndex.

Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.

Definition at line 1112 of file SIRegisterInfo.cpp.

References llvm_unreachable, restoreSGPR(), and spillSGPR().

Referenced by getCSRFirstUseCost().

◆ findReachingDef()

MachineInstr * SIRegisterInfo::findReachingDef ( unsigned  Reg,
unsigned  SubReg,
MachineInstr Use,
MachineRegisterInfo MRI,
LiveIntervals LIS 
) const

◆ findUnusedRegister()

unsigned SIRegisterInfo::findUnusedRegister ( const MachineRegisterInfo MRI,
const TargetRegisterClass RC,
const MachineFunction MF 
) const

Returns a register that is not used at any point in the function.

If all registers are used, then this function will return

Definition at line 1618 of file SIRegisterInfo.cpp.

References llvm::MachineRegisterInfo::isAllocatable(), and llvm::MachineRegisterInfo::isPhysRegUsed().

Referenced by llvm::SIInstrInfo::calculateLDSSpillAddress(), and opCanUseInlineConstant().

◆ getAGPRPressureSet()

unsigned llvm::SIRegisterInfo::getAGPRPressureSet ( ) const
inline

Definition at line 207 of file SIRegisterInfo.h.

References getRegClassForReg(), isAGPR(), and isVGPR().

Referenced by getRegPressureSetLimit().

◆ getAllAllocatableSRegMask()

const uint32_t * SIRegisterInfo::getAllAllocatableSRegMask ( ) const

Definition at line 100 of file AMDGPURegisterInfo.cpp.

Referenced by getWaveMaskRegClass().

◆ getAllVGPRRegMask()

const uint32_t * SIRegisterInfo::getAllVGPRRegMask ( ) const

Definition at line 96 of file AMDGPURegisterInfo.cpp.

Referenced by getWaveMaskRegClass().

◆ getBoolRC()

const TargetRegisterClass* llvm::SIRegisterInfo::getBoolRC ( ) const
inline

◆ getCalleeSavedRegs()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegs ( const MachineFunction MF) const
override

◆ getCalleeSavedRegsViaCopy()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy ( const MachineFunction MF) const

◆ getCallPreservedMask()

const uint32_t * SIRegisterInfo::getCallPreservedMask ( const MachineFunction MF,
CallingConv::ID  CC 
) const
override

◆ getConstrainedRegClassForOperand()

const TargetRegisterClass * SIRegisterInfo::getConstrainedRegClassForOperand ( const MachineOperand MO,
const MachineRegisterInfo MRI 
) const
override

◆ getCSRFirstUseCost()

unsigned llvm::SIRegisterInfo::getCSRFirstUseCost ( ) const
inlineoverride

◆ getEquivalentAGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass ( const TargetRegisterClass SRC) const
Returns
An AGPR reg class with the same width as SRC

Definition at line 1484 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by foldVGPRCopyIntoRegSequence(), and hasVectorRegisters().

◆ getEquivalentSGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass ( const TargetRegisterClass VRC) const
Returns
A SGPR reg class with the same width as SRC

Definition at line 1502 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by hasVectorRegisters(), and tryChangeVGPRtoSGPRinCopy().

◆ getEquivalentVGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass ( const TargetRegisterClass SRC) const
Returns
A VGPR reg class with the same width as SRC

Definition at line 1460 of file SIRegisterInfo.cpp.

References llvm_unreachable.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), foldVGPRCopyIntoRegSequence(), and hasVectorRegisters().

◆ getFrameIndexInstrOffset()

int64_t SIRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr MI,
int  Idx 
) const
override

◆ getFrameRegister()

Register SIRegisterInfo::getFrameRegister ( const MachineFunction MF) const
override

◆ getHWRegIndex()

unsigned llvm::SIRegisterInfo::getHWRegIndex ( unsigned  Reg) const
inline

◆ getMUBUFInstrOffset()

int64_t SIRegisterInfo::getMUBUFInstrOffset ( const MachineInstr MI) const

◆ getPhysRegClass()

const TargetRegisterClass * SIRegisterInfo::getPhysRegClass ( unsigned  Reg) const

Return the 'base' register class for this register.

e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.

Definition at line 1369 of file SIRegisterInfo.cpp.

References assert(), and llvm::TargetRegisterInfo::isVirtualRegister().

Referenced by addRegsToSet(), llvm::SIInstrInfo::copyPhysReg(), llvm::createR600ISelDag(), llvm::SIInstrInfo::FoldImmediate(), getCopyRegClasses(), getHWRegIndex(), getRegClassForReg(), isSGPRReg(), restoreSGPR(), llvm::SIInstrInfo::shouldClusterMemOps(), and spillSGPR().

◆ getPointerRegClass()

const TargetRegisterClass * SIRegisterInfo::getPointerRegClass ( const MachineFunction MF,
unsigned  Kind = 0 
) const
override

Definition at line 448 of file SIRegisterInfo.cpp.

Referenced by getCSRFirstUseCost().

◆ getRegAsmName()

StringRef SIRegisterInfo::getRegAsmName ( unsigned  Reg) const
override

◆ getRegClass()

const TargetRegisterClass * SIRegisterInfo::getRegClass ( unsigned  RCID) const

◆ getRegClassForReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForReg ( const MachineRegisterInfo MRI,
unsigned  Reg 
) const

◆ getRegClassForSizeOnBank()

const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank ( unsigned  Size,
const RegisterBank Bank,
const MachineRegisterInfo MRI 
) const

◆ getRegClassForTypeOnBank()

const TargetRegisterClass* llvm::SIRegisterInfo::getRegClassForTypeOnBank ( LLT  Ty,
const RegisterBank Bank,
const MachineRegisterInfo MRI 
) const
inline

◆ getRegPressureLimit()

unsigned SIRegisterInfo::getRegPressureLimit ( const TargetRegisterClass RC,
MachineFunction MF 
) const
override

◆ getRegPressureSetLimit()

unsigned SIRegisterInfo::getRegPressureSetLimit ( const MachineFunction MF,
unsigned  Idx 
) const
override

◆ getRegSplitParts()

ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts ( const TargetRegisterClass RC,
unsigned  EltSize 
) const

◆ getRegUnitPressureSets()

const int * SIRegisterInfo::getRegUnitPressureSets ( unsigned  RegUnit) const
override

Definition at line 1877 of file SIRegisterInfo.cpp.

References llvm::Empty.

Referenced by hasPressureSet(), isAGPRPressureSet(), and SIRegisterInfo().

◆ getReservedRegs()

BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction MF) const
override

◆ getReturnAddressReg()

unsigned SIRegisterInfo::getReturnAddressReg ( const MachineFunction MF) const

◆ getSGPRPressureSet()

unsigned llvm::SIRegisterInfo::getSGPRPressureSet ( ) const
inline

◆ getSubRegClass()

const TargetRegisterClass * SIRegisterInfo::getSubRegClass ( const TargetRegisterClass RC,
unsigned  SubIdx 
) const
Returns
The register class that is used for a sub-register of RC for the given SubIdx. If SubIdx equals NoSubRegister, RC will be returned.

Definition at line 1526 of file SIRegisterInfo.cpp.

References hasAGPRs(), isSGPRClass(), and llvm_unreachable.

Referenced by foldVGPRCopyIntoRegSequence(), hasVectorRegisters(), and llvm::SIInstrInfo::isLegalRegOperand().

◆ getVCC()

unsigned SIRegisterInfo::getVCC ( ) const

◆ getVGPRPressureSet()

unsigned llvm::SIRegisterInfo::getVGPRPressureSet ( ) const
inline

◆ getWaveMaskRegClass()

const TargetRegisterClass* llvm::SIRegisterInfo::getWaveMaskRegClass ( ) const
inline

◆ hasAGPRs()

bool SIRegisterInfo::hasAGPRs ( const TargetRegisterClass RC) const

◆ hasVectorRegisters()

bool llvm::SIRegisterInfo::hasVectorRegisters ( const TargetRegisterClass RC) const
inline

◆ hasVGPRs()

bool SIRegisterInfo::hasVGPRs ( const TargetRegisterClass RC) const

◆ isAGPR()

bool SIRegisterInfo::isAGPR ( const MachineRegisterInfo MRI,
unsigned  Reg 
) const

◆ isAGPRPressureSet()

bool llvm::SIRegisterInfo::isAGPRPressureSet ( unsigned  SetID) const
inline

◆ isDivergentRegClass()

virtual bool llvm::SIRegisterInfo::isDivergentRegClass ( const TargetRegisterClass RC) const
inlineoverridevirtual

Definition at line 218 of file SIRegisterInfo.h.

References isSGPRClass().

◆ isFrameOffsetLegal()

bool SIRegisterInfo::isFrameOffsetLegal ( const MachineInstr MI,
unsigned  BaseReg,
int64_t  Offset 
) const
override

Definition at line 437 of file SIRegisterInfo.cpp.

References getMUBUFInstrOffset(), and llvm::SIInstrInfo::isMUBUF().

Referenced by getCSRFirstUseCost().

◆ isSGPRClass()

bool llvm::SIRegisterInfo::isSGPRClass ( const TargetRegisterClass RC) const
inline

◆ isSGPRClassID()

bool llvm::SIRegisterInfo::isSGPRClassID ( unsigned  RCID) const
inline
Returns
true if this class ID contains only SGPR registers

Definition at line 138 of file SIRegisterInfo.h.

References getRegClass(), and isSGPRClass().

◆ isSGPRPressureSet()

bool llvm::SIRegisterInfo::isSGPRPressureSet ( unsigned  SetID) const
inline

Definition at line 222 of file SIRegisterInfo.h.

References llvm::BitVector::test().

Referenced by SIRegisterInfo().

◆ isSGPRReg()

bool llvm::SIRegisterInfo::isSGPRReg ( const MachineRegisterInfo MRI,
unsigned  Reg 
) const
inline

◆ isVectorRegister()

bool llvm::SIRegisterInfo::isVectorRegister ( const MachineRegisterInfo MRI,
unsigned  Reg 
) const
inline

Definition at line 213 of file SIRegisterInfo.h.

References isAGPR(), and isVGPR().

◆ isVGPR()

bool SIRegisterInfo::isVGPR ( const MachineRegisterInfo MRI,
unsigned  Reg 
) const

◆ isVGPRPressureSet()

bool llvm::SIRegisterInfo::isVGPRPressureSet ( unsigned  SetID) const
inline

Definition at line 226 of file SIRegisterInfo.h.

References llvm::BitVector::test().

Referenced by SIRegisterInfo().

◆ materializeFrameBaseRegister()

void SIRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock MBB,
unsigned  BaseReg,
int  FrameIdx,
int64_t  Offset 
) const
override

◆ needsFrameBaseReg()

bool SIRegisterInfo::needsFrameBaseReg ( MachineInstr MI,
int64_t  Offset 
) const
override

Definition at line 355 of file SIRegisterInfo.cpp.

References getMUBUFInstrOffset(), and llvm::MachineInstr::mayLoadOrStore().

Referenced by getCSRFirstUseCost().

◆ opCanUseInlineConstant()

bool llvm::SIRegisterInfo::opCanUseInlineConstant ( unsigned  OpType) const
inline
Returns
True if operands defined with this operand type can accept an inline constant. i.e. An integer value in the range (-16, 64) or -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.

Definition at line 196 of file SIRegisterInfo.h.

References findUnusedRegister(), MRI, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

◆ opCanUseLiteralConstant()

bool llvm::SIRegisterInfo::opCanUseLiteralConstant ( unsigned  OpType) const
inline
Returns
True if operands defined with this operand type can accept a literal constant (i.e. any 32-bit immediate).

Definition at line 187 of file SIRegisterInfo.h.

References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

◆ requiresFrameIndexReplacementScavenging()

bool SIRegisterInfo::requiresFrameIndexReplacementScavenging ( const MachineFunction MF) const
override

◆ requiresFrameIndexScavenging()

bool SIRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction MF) const
override

◆ requiresRegisterScavenging()

bool SIRegisterInfo::requiresRegisterScavenging ( const MachineFunction Fn) const
override

◆ requiresVirtualBaseRegisters()

bool SIRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction Fn) const
override

Definition at line 324 of file SIRegisterInfo.cpp.

Referenced by getCSRFirstUseCost().

◆ reservedPrivateSegmentBufferReg()

unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg ( const MachineFunction MF) const

Return the end register initially reserved for the scratch buffer in case spilling is needed.

Definition at line 119 of file SIRegisterInfo.cpp.

References llvm::alignDown(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::MachineFunction::getSubtarget(), and llvm::ARM_MB::ST.

Referenced by buildEpilogReload(), reservePrivateMemoryRegs(), and spillSGPRToSMEM().

◆ reservedPrivateSegmentWaveByteOffsetReg()

unsigned SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg ( const MachineFunction MF) const

Return the end register initially reserved for the scratch wave offset in case spilling is needed.

Definition at line 145 of file SIRegisterInfo.cpp.

References findPrivateSegmentWaveByteOffsetRegIndex(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::MachineFunction::getSubtarget(), and llvm::ARM_MB::ST.

Referenced by buildEpilogReload(), reservePrivateMemoryRegs(), and spillSGPRToSMEM().

◆ resolveFrameIndex()

void SIRegisterInfo::resolveFrameIndex ( MachineInstr MI,
unsigned  BaseReg,
int64_t  Offset 
) const
override

◆ restoreSGPR()

bool SIRegisterInfo::restoreSGPR ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS,
bool  OnlyToVGPR = false 
) const

◆ shouldCoalesce()

bool SIRegisterInfo::shouldCoalesce ( MachineInstr MI,
const TargetRegisterClass SrcRC,
unsigned  SubReg,
const TargetRegisterClass DstRC,
unsigned  DstSubReg,
const TargetRegisterClass NewRC,
LiveIntervals LIS 
) const
override

Definition at line 1825 of file SIRegisterInfo.cpp.

Referenced by isAGPRPressureSet().

◆ shouldRewriteCopySrc()

bool SIRegisterInfo::shouldRewriteCopySrc ( const TargetRegisterClass DefRC,
unsigned  DefSubReg,
const TargetRegisterClass SrcRC,
unsigned  SrcSubReg 
) const
override

Definition at line 1590 of file SIRegisterInfo.cpp.

Referenced by hasVectorRegisters().

◆ spillSGPR()

bool SIRegisterInfo::spillSGPR ( MachineBasicBlock::iterator  MI,
int  FI,
RegScavenger RS,
bool  OnlyToVGPR = false 
) const

If OnlyToVGPR is true, this will only succeed if this.

Definition at line 782 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::ArrayRef< T >::empty(), llvm::MachineFunction::front(), llvm::MDNode::get(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), getFrameRegister(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineBasicBlock::getParent(), getPhysRegClass(), llvm::MachineFunction::getRegInfo(), getRegSplitParts(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getScratchWaveOffsetReg(), llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills(), getSpillEltSize(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::MachineFunction::getSubtarget(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::RegState::Implicit, llvm::RegScavenger::isRegUsed(), isSGPRClass(), llvm::RegState::Kill, llvm::SIMachineFunctionInfo::SpilledReg::Lane, llvm::MinAlign(), llvm::MachineMemOperand::MOStore, MRI, llvm::ArrayRef< T >::size(), spillSGPRToSMEM(), llvm::ARM_MB::ST, SubReg, TII, llvm::RegState::Undef, and llvm::SIMachineFunctionInfo::SpilledReg::VGPR.

Referenced by eliminateFrameIndex(), eliminateSGPRToVGPRSpillFrameIndex(), and getCSRFirstUseCost().

◆ spillSGPRToSMEM()

bool llvm::SIRegisterInfo::spillSGPRToSMEM ( ) const
inline

◆ spillSGPRToVGPR()

bool llvm::SIRegisterInfo::spillSGPRToVGPR ( ) const
inline

◆ trackLivenessAfterRegAlloc()

bool SIRegisterInfo::trackLivenessAfterRegAlloc ( const MachineFunction MF) const
override

Definition at line 330 of file SIRegisterInfo.cpp.

Referenced by getCSRFirstUseCost().


The documentation for this class was generated from the following files: