LLVM 24.0.0git
Classes | Public Member Functions | Static Public Member Functions | List of all members
llvm::SIRegisterInfo Class Referencefinal

#include "Target/AMDGPU/SIRegisterInfo.h"

Inheritance diagram for llvm::SIRegisterInfo:
[legend]

Classes

struct  SpilledReg

Public Member Functions

 SIRegisterInfo (const GCNSubtarget &ST)
bool spillSGPRToVGPR () const
bool isCFISavedRegsSpillEnabled () const
MCRegister getAlignedHighSGPRForRC (const MachineFunction &MF, const unsigned Align, const TargetRegisterClass *RC) const
 Return the largest available SGPR aligned to Align for the register class RC.
MCRegister reservedPrivateSegmentBufferReg (const MachineFunction &MF) const
 Return the end register initially reserved for the scratch buffer in case spilling is needed.
BitVector getReservedRegs (const MachineFunction &MF) const override
bool isAsmClobberable (const MachineFunction &MF, MCRegister PhysReg) const override
const MCPhysReg * getCalleeSavedRegs (const MachineFunction *MF) const override
const MCPhysReg * getCalleeSavedRegsViaCopy (const MachineFunction *MF) const
const uint32_t * getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override
const uint32_t * getNoPreservedMask () const override
unsigned getCSRFirstUseCost (const MachineFunction &) const override
void addImplicitUsesForBlockCSRLoad (MachineInstrBuilder &MIB, Register BlockReg) const
void buildCFIForBlockCSRStore (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register BlockReg, int64_t Offset) const
const TargetRegisterClass * getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &MF) const override
Register getFrameRegister (const MachineFunction &MF) const override
bool hasBasePointer (const MachineFunction &MF) const
Register getBaseRegister () const
bool shouldRealignStack (const MachineFunction &MF) const override
bool requiresRegisterScavenging (const MachineFunction &Fn) const override
bool requiresFrameIndexScavenging (const MachineFunction &MF) const override
bool requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const override
bool requiresVirtualBaseRegisters (const MachineFunction &Fn) const override
int64_t getScratchInstrOffset (const MachineInstr *MI) const
int64_t getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override
bool needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
Register materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
void resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
const TargetRegisterClass * getCrossCopyRegClass (const TargetRegisterClass *RC) const override
 Returns a legal register class to copy a register in the specified class to or from.
const TargetRegisterClass * getRegClassForBlockOp (const MachineFunction &MF) const
void buildVGPRSpillLoadStore (SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
bool spillSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false, bool NeedsCFI=false) const
 If OnlyToVGPR is true, this will only succeed if this manages to find a free VGPR lane to spill.
bool restoreSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false, bool SpillToPhysVGPRLane=false) const
bool spillEmergencySGPR (MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
bool eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
bool eliminateSGPRToVGPRSpillFrameIndex (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool SpillToPhysVGPRLane=false) const
 Special case of eliminateFrameIndex.
StringRef getRegAsmName (MCRegister Reg) const override
unsigned getHWRegIndex (MCRegister Reg) const
LLVM_READONLY const TargetRegisterClass * getVGPRClassForBitWidth (unsigned BitWidth) const
LLVM_READONLY const TargetRegisterClass * getAlignedLo256VGPRClassForBitWidth (unsigned BitWidth) const
LLVM_READONLY const TargetRegisterClass * getAGPRClassForBitWidth (unsigned BitWidth) const
LLVM_READONLY const TargetRegisterClass * getVectorSuperClassForBitWidth (unsigned BitWidth) const
LLVM_READONLY const TargetRegisterClass * getDefaultVectorSuperClassForBitWidth (unsigned BitWidth) const
bool isSGPRClassID (unsigned RCID) const
bool isSGPRReg (const MachineRegisterInfo &MRI, Register Reg) const
bool isSGPRPhysReg (Register Reg) const
bool isVGPRPhysReg (Register Reg) const
bool isVectorSuperClass (const TargetRegisterClass *RC) const
bool isVSSuperClass (const TargetRegisterClass *RC) const
const TargetRegisterClass * getEquivalentVGPRClass (const TargetRegisterClass *SRC) const
const TargetRegisterClass * getEquivalentAGPRClass (const TargetRegisterClass *SRC) const
const TargetRegisterClass * getEquivalentAVClass (const TargetRegisterClass *SRC) const
const TargetRegisterClass * getEquivalentSGPRClass (const TargetRegisterClass *VRC) const
const TargetRegisterClass * getCompatibleSubRegClass (const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
 Returns a register class which is compatible with SuperRC, such that a subregister exists with class SubRC with subregister index SubIdx.
bool opCanUseLiteralConstant (unsigned OpType) const
bool opCanUseInlineConstant (unsigned OpType) const
MCRegister findUnusedRegister (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
 Returns a lowest register that is not used at any point in the function.
const TargetRegisterClass * getRegClassForReg (const MachineRegisterInfo &MRI, Register Reg) const
const TargetRegisterClass * getRegClassForOperandReg (const MachineRegisterInfo &MRI, const MachineOperand &MO) const
bool isVGPR (const MachineRegisterInfo &MRI, Register Reg) const
bool isAGPR (const MachineRegisterInfo &MRI, Register Reg) const
bool isVectorRegister (const MachineRegisterInfo &MRI, Register Reg) const
bool isDivergentRegClass (const TargetRegisterClass *RC) const override
bool isUniformReg (const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const override
ArrayRef< int16_t > getRegSplitParts (const TargetRegisterClass *RC, unsigned EltSize) const
unsigned getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const override
bool getRegAllocationHints (Register VirtReg, ArrayRef< MCPhysReg > Order, SmallVectorImpl< MCPhysReg > &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const override
bool shouldApplyAntiHints (const MachineFunction &MF, unsigned NumAllocatedVGPRs, unsigned &MaxVGPRsForCurrentOccupancy) const
void filterAndSortForAntiHintedRegs (Register VirtReg, MutableArrayRef< MCPhysReg > CustomOrder, const BitVector &AntiHintedRegUnits, const MachineFunction &MF, const LiveRegMatrix *Matrix=nullptr, const RegisterClassInfo *RegClassInfo=nullptr) const override
const int * getRegUnitPressureSets (MCRegUnit RegUnit) const override
MCRegister getReturnAddressReg (const MachineFunction &MF) const
const TargetRegisterClass * getRegClassForSizeOnBank (unsigned Size, const RegisterBank &Bank) const
const TargetRegisterClass * getRegClassForTypeOnBank (LLT Ty, const RegisterBank &Bank) const
const TargetRegisterClass * getConstrainedRegClassForReg (Register Reg, const MachineRegisterInfo &MRI) const override
const TargetRegisterClass * getBoolRC () const
const TargetRegisterClass * getWaveMaskRegClass () const
const TargetRegisterClass * getVGPR64Class () const
MCRegister getVCC () const
MCRegister getExec () const
MachineInstr * findReachingDef (Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
const uint32_t * getAllVGPRRegMask () const
const uint32_t * getAllAGPRRegMask () const
const uint32_t * getAllVectorRegMask () const
const uint32_t * getAllAllocatableSRegMask () const
unsigned getChannelFromSubReg (unsigned SubReg) const
unsigned getNumChannelsFromSubReg (unsigned SubReg) const
MCPhysReg get32BitRegister (MCPhysReg Reg) const
bool isProperlyAlignedRC (const TargetRegisterClass &RC) const
ArrayRef< MCPhysReg > getAllSGPR128 (const MachineFunction &MF) const
 Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
ArrayRef< MCPhysReg > getAllSGPR64 (const MachineFunction &MF) const
 Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
ArrayRef< MCPhysReg > getAllSGPR32 (const MachineFunction &MF) const
 Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
void buildSpillLoadStore (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LiveRegUnits *LiveUnits=nullptr, bool NeedsCFI=false) const
unsigned getRegClassAlignmentNumBits (const TargetRegisterClass *RC) const
bool isRegClassAligned (const TargetRegisterClass *RC, unsigned AlignNumBits) const
unsigned getSubRegAlignmentNumBits (const TargetRegisterClass *RC, unsigned SubReg) const
unsigned getNumUsedPhysRegs (const MachineRegisterInfo &MRI, const TargetRegisterClass &RC, bool IncludeCalls=true) const
std::optional< uint8_t > getVRegFlagValue (StringRef Name) const override
SmallVector< StringLiteral > getVRegFlagsOfReg (Register Reg, const MachineFunction &MF) const override
float getSpillWeightScaleFactor (const TargetRegisterClass *RC) const override

Static Public Member Functions

static unsigned getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1)
static bool isChainScratchRegister (Register VGPR)
static LLVM_READONLY const TargetRegisterClass * getSGPRClassForBitWidth (unsigned BitWidth)
static bool isSGPRClass (const TargetRegisterClass *RC)
static bool isVGPRClass (const TargetRegisterClass *RC)
static bool isAGPRClass (const TargetRegisterClass *RC)
static bool hasVGPRs (const TargetRegisterClass *RC)
static bool hasAGPRs (const TargetRegisterClass *RC)
static bool hasSGPRs (const TargetRegisterClass *RC)
static bool hasVectorRegisters (const TargetRegisterClass *RC)
static unsigned getNumCoveredRegs (LaneBitmask LM)

Detailed Description

Definition at line 45 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

◆ SIRegisterInfo()

SIRegisterInfo::SIRegisterInfo ( const GCNSubtarget & ST)

Definition at line 348 of file SIRegisterInfo.cpp.

References assert(), llvm::call_once(), EnableSpillSGPRToVGPR, llvm::MCRegister::from(), llvm::AMDGPU::isHi16Reg(), llvm::Offset, Size, llvm::size(), and SubRegFromChannelTableWidthMap.

Referenced by getRegAllocationHints().

Member Function Documentation

◆ addImplicitUsesForBlockCSRLoad()

void SIRegisterInfo::addImplicitUsesForBlockCSRLoad ( MachineInstrBuilder & MIB,
Register BlockReg ) const

Definition at line 2095 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addUse(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getMaskForVGPRBlockOps(), llvm::MachineInstr::getMF(), and llvm::Implicit.

Referenced by buildSpillLoadStore().

◆ buildCFIForBlockCSRStore()

void SIRegisterInfo::buildCFIForBlockCSRStore ( MachineBasicBlock & MBB,
MachineBasicBlock::iterator MBBI,
Register BlockReg,
int64_t Offset ) const

Definition at line 2107 of file SIRegisterInfo.cpp.

References assert(), llvm::dwarf_linker::DebugLoc, llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getMaskForVGPRBlockOps(), MBB, MBBI, and llvm::Offset.

Referenced by buildSpillLoadStore().

◆ buildSpillLoadStore()

void SIRegisterInfo::buildSpillLoadStore ( MachineBasicBlock & MBB,
MachineBasicBlock::iterator MI,
const DebugLoc & DL,
unsigned LoadStoreOp,
int Index,
Register ValueReg,
bool ValueIsKill,
MCRegister ScratchOffsetReg,
int64_t InstrOffset,
MachineMemOperand * MMO,
RegScavenger * RS,
LiveRegUnits * LiveUnits = nullptr,
bool NeedsCFI = false ) const

Definition at line 1585 of file SIRegisterInfo.cpp.

References llvm::Add, llvm::MachineInstrBuilder::addImm(), addImplicitUsesForBlockCSRLoad(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LiveRegUnits::available(), buildCFIForBlockCSRStore(), llvm::SIFrameLowering::buildCFIForVGPRToVMEMSpill(), llvm::BuildMI(), llvm::commonAlignment(), llvm::MCRegisterClass::contains(), llvm::dwarf_linker::DebugLoc, llvm::Define, DL, llvm::AMDGPU::FlatScratch, llvm::getDefRegState(), llvm::MachineMemOperand::getFlags(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), getFlatScratchSpillOpcode(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), getOffenMUBUFLoad(), getOffenMUBUFStore(), llvm::MachineMemOperand::getPointerInfo(), llvm::AMDGPU::getRegBitWidth(), getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getSubRegFromChannel(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::MachinePointerInfo::getWithOffset(), llvm::hasRegState(), llvm::Implicit, llvm::ImplicitDefine, isAGPRClass(), llvm::AMDGPUMachineFunctionInfo::isBottomOfStack(), llvm::MachineRegisterInfo::isReserved(), llvm::Kill, MBB, MI, llvm::MOLastUse, llvm::MOThreadPrivate, llvm::Offset, Opc, llvm::AMDGPUAS::PRIVATE_ADDRESS, Register, llvm::MachineInstr::ReloadReuse, llvm::report_fatal_error(), llvm::MachineInstr::setAsmPrinterFlag(), Size, spillVGPRtoAGPR(), llvm::Sub, llvm::AMDGPU::CPol::TH_LU, and TII.

Referenced by buildVGPRSpillLoadStore(), and eliminateFrameIndex().

◆ buildVGPRSpillLoadStore()

void SIRegisterInfo::buildVGPRSpillLoadStore ( SGPRSpillBuilder & SB,
int Index,
int Offset,
bool IsLoad,
bool IsKill = true ) const

Definition at line 2132 of file SIRegisterInfo.cpp.

References llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), buildSpillLoadStore(), llvm::SGPRSpillBuilder::DL, llvm::SGPRSpillBuilder::EltSize, getBaseRegister(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getMachineMemOperand(), hasBasePointer(), llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MF, llvm::SGPRSpillBuilder::MFI, llvm::SGPRSpillBuilder::MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::Offset, Opc, llvm::SGPRSpillBuilder::RS, llvm::TargetStackID::SGPRSpill, and llvm::SGPRSpillBuilder::TmpVGPR.

◆ eliminateFrameIndex()

bool SIRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator MI,
int SPAdj,
unsigned FIOperandNum,
RegScavenger * RS ) const
override

Definition at line 2557 of file SIRegisterInfo.cpp.

References AbstractManglingParser< Derived, Alloc >::NumOps, llvm::Add, llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), buildSpillLoadStore(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), DL, emitUnsupportedError(), llvm::AMDGPU::FlatScratch, foldingOffsetChangesCarry(), getBaseRegister(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSVS(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), getNumSubRegsForSpillOp(), llvm::MachineInstr::getOpcode(), llvm::DstOp::getReg(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRForEXECCopy(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), hasBasePointer(), llvm::AMDGPU::hasNamedOperand(), I, llvm::AMDGPUMachineFunctionInfo::isBottomOfStack(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::AMDGPU::isInlinableIntLiteral(), llvm::AMDGPU::isInlinableLiteral32(), llvm::MachineOperand::isKill(), llvm::Register::isPhysical(), llvm::MachineOperand::isReg(), llvm::MachineRegisterInfo::isReserved(), isSCCLiveInto(), isSGPRClass(), llvm::isUInt(), llvm::MachineOperand::isUndef(), llvm::Register::isValid(), isVGPRClass(), llvm::SIInstrInfo::isVOP3(), llvm::Kill, MBB, MI, llvm::Offset, Opc, llvm::AMDGPUAS::PRIVATE_ADDRESS, Register, llvm::Renamable, llvm::report_fatal_error(), restoreSGPR(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsRenamable(), llvm::MachineInstrBuilder::setOperandDead(), llvm::MachineOperand::setReg(), llvm::TargetStackID::SGPRSpill, spillSGPR(), std::swap(), and TII.

◆ eliminateSGPRToVGPRSpillFrameIndex()

bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex ( MachineBasicBlock::iterator MI,
int FI,
RegScavenger * RS,
SlotIndexes * Indexes = nullptr,
LiveIntervals * LIS = nullptr,
bool SpillToPhysVGPRLane = false ) const

Special case of eliminateFrameIndex.

Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.

Definition at line 2482 of file SIRegisterInfo.cpp.

References llvm_unreachable, MI, restoreSGPR(), and spillSGPR().

◆ filterAndSortForAntiHintedRegs()

void SIRegisterInfo::filterAndSortForAntiHintedRegs ( Register VirtReg,
MutableArrayRef< MCPhysReg > CustomOrder,
const BitVector & AntiHintedRegUnits,
const MachineFunction & MF,
const LiveRegMatrix * Matrix = nullptr,
const RegisterClassInfo * RegClassInfo = nullptr ) const
override

Definition at line 4418 of file SIRegisterInfo.cpp.

References assert(), llvm::MutableArrayRef< T >::begin(), llvm::dbgs(), llvm::MutableArrayRef< T >::end(), getHWRegIndex(), llvm::RegisterClassInfo::getOrder(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::AMDGPU::getTotalNumVGPRs(), hasVectorRegisters(), llvm::MachineRegisterInfo::isPhysRegUsed(), LLVM_DEBUG, Matrix, llvm::none_of(), and shouldApplyAntiHints().

◆ findReachingDef()

MachineInstr * SIRegisterInfo::findReachingDef ( Register Reg,
unsigned SubReg,
MachineInstr & Use,
MachineRegisterInfo & MRI,
LiveIntervals * LIS ) const

Definition at line 4534 of file SIRegisterInfo.cpp.

References assert(), llvm::LiveIntervals::getDomTree(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::MachineRegisterInfo::getMaxLaneMaskForVReg(), llvm::LiveIntervals::getRegUnit(), llvm::LiveRange::getVNInfoAt(), llvm::LiveIntervals::hasInterval(), llvm::LiveInterval::hasSubRanges(), llvm::SlotIndex::isValid(), and llvm::LiveInterval::subranges().

◆ findUnusedRegister()

MCRegister SIRegisterInfo::findUnusedRegister ( const MachineRegisterInfo & MRI,
const TargetRegisterClass * RC,
const MachineFunction & MF,
bool ReserveHighestRegister = false ) const

Returns a lowest register that is not used at any point in the function.

If all registers are used, then this function will return AMDGPU::NoRegister. If ReserveHighestRegister = true, then return highest unused register.

Definition at line 4160 of file SIRegisterInfo.cpp.

References llvm::MachineRegisterInfo::isAllocatable(), llvm::MachineRegisterInfo::isPhysRegUsed(), and llvm::reverse().

◆ get32BitRegister()

MCPhysReg SIRegisterInfo::get32BitRegister ( MCPhysReg Reg) const

Definition at line 4587 of file SIRegisterInfo.cpp.

References assert().

◆ getAGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getAGPRClassForBitWidth ( unsigned BitWidth) const

Definition at line 3946 of file SIRegisterInfo.cpp.

References llvm::BitWidth, getAlignedAGPRClassForBitWidth(), and getAnyAGPRClassForBitWidth().

Referenced by getEquivalentAGPRClass(), getRegClassForSizeOnBank(), and isProperlyAlignedRC().

◆ getAlignedHighSGPRForRC()

MCRegister SIRegisterInfo::getAlignedHighSGPRForRC ( const MachineFunction & MF,
const unsigned Align,
const TargetRegisterClass * RC ) const

Return the largest available SGPR aligned to Align for the register class RC.

Definition at line 589 of file SIRegisterInfo.cpp.

References llvm::alignDown().

Referenced by reservedPrivateSegmentBufferReg().

◆ getAlignedLo256VGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getAlignedLo256VGPRClassForBitWidth ( unsigned BitWidth) const

Definition at line 3848 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by getEquivalentVGPRClass().

◆ getAllAGPRRegMask()

const uint32_t * SIRegisterInfo::getAllAGPRRegMask ( ) const

Definition at line 563 of file SIRegisterInfo.cpp.

◆ getAllAllocatableSRegMask()

const uint32_t * SIRegisterInfo::getAllAllocatableSRegMask ( ) const

Definition at line 571 of file SIRegisterInfo.cpp.

◆ getAllSGPR128()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR128 ( const MachineFunction & MF) const

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 4622 of file SIRegisterInfo.cpp.

References llvm::ArrayRef().

◆ getAllSGPR32()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR32 ( const MachineFunction & MF) const

Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 4632 of file SIRegisterInfo.cpp.

References llvm::ArrayRef().

◆ getAllSGPR64()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR64 ( const MachineFunction & MF) const

Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 4627 of file SIRegisterInfo.cpp.

References llvm::ArrayRef().

◆ getAllVectorRegMask()

const uint32_t * SIRegisterInfo::getAllVectorRegMask ( ) const

Definition at line 567 of file SIRegisterInfo.cpp.

◆ getAllVGPRRegMask()

const uint32_t * SIRegisterInfo::getAllVGPRRegMask ( ) const

Definition at line 559 of file SIRegisterInfo.cpp.

◆ getBaseRegister()

Register SIRegisterInfo::getBaseRegister ( ) const

Definition at line 557 of file SIRegisterInfo.cpp.

Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().

◆ getBoolRC()

const TargetRegisterClass * llvm::SIRegisterInfo::getBoolRC ( ) const
inline

Definition at line 408 of file SIRegisterInfo.h.

Referenced by llvm::GCNSubtarget::getBoolRC().

◆ getCalleeSavedRegs()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegs ( const MachineFunction * MF) const
override

Definition at line 423 of file SIRegisterInfo.cpp.

References llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_Gfx_WholeWave, llvm::CallingConv::C, llvm::CallingConv::Cold, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), and llvm::MachineFunction::getFunction().

◆ getCalleeSavedRegsViaCopy()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy ( const MachineFunction * MF) const

Definition at line 447 of file SIRegisterInfo.cpp.

◆ getCallPreservedMask()

const uint32_t * SIRegisterInfo::getCallPreservedMask ( const MachineFunction & MF,
CallingConv::ID CC ) const
override

Definition at line 451 of file SIRegisterInfo.cpp.

References llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_Gfx_WholeWave, llvm::CallingConv::C, llvm::CallingConv::Cold, and llvm::CallingConv::Fast.

◆ getChannelFromSubReg()

unsigned llvm::SIRegisterInfo::getChannelFromSubReg ( unsigned SubReg) const
inline

Definition at line 449 of file SIRegisterInfo.h.

Referenced by expandSGPRCopy().

◆ getCompatibleSubRegClass()

const TargetRegisterClass * SIRegisterInfo::getCompatibleSubRegClass ( const TargetRegisterClass * SuperRC,
const TargetRegisterClass * SubRC,
unsigned SubIdx ) const

Returns a register class which is compatible with SuperRC, such that a subregister exists with class SubRC with subregister index SubIdx.

If this is impossible (e.g., an unaligned subregister index within a register tuple), return null.

Definition at line 4132 of file SIRegisterInfo.cpp.

References llvm::MCRegisterClass::hasSubClassEq().

◆ getConstrainedRegClassForReg()

const TargetRegisterClass * SIRegisterInfo::getConstrainedRegClassForReg ( Register Reg,
const MachineRegisterInfo & MRI ) const
override

Definition at line 4507 of file SIRegisterInfo.cpp.

References llvm::dyn_cast(), getRegClassForTypeOnBank(), llvm::MachineRegisterInfo::getRegClassOrRegBank(), and llvm::MachineRegisterInfo::getType().

◆ getCrossCopyRegClass()

const TargetRegisterClass * SIRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass * RC) const
override

Returns a legal register class to copy a register in the specified class to or from.

If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.

Definition at line 1150 of file SIRegisterInfo.cpp.

◆ getCSRFirstUseCost()

unsigned llvm::SIRegisterInfo::getCSRFirstUseCost ( const MachineFunction & ) const
inlineoverride

Definition at line 120 of file SIRegisterInfo.h.

◆ getDefaultVectorSuperClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getDefaultVectorSuperClassForBitWidth ( unsigned BitWidth) const

Definition at line 4029 of file SIRegisterInfo.cpp.

References llvm::BitWidth, getVectorSuperClassForBitWidth(), and getVGPRClassForBitWidth().

◆ getEquivalentAGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass ( const TargetRegisterClass * SRC) const
Returns
An AGPR reg class with the same width as SRC

Definition at line 4106 of file SIRegisterInfo.cpp.

References assert(), getAGPRClassForBitWidth(), and Size.

◆ getEquivalentAVClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentAVClass ( const TargetRegisterClass * SRC) const
Returns
An AGPR+VGPR super reg class with the same width as SRC

Definition at line 4114 of file SIRegisterInfo.cpp.

References assert(), getVectorSuperClassForBitWidth(), and Size.

◆ getEquivalentSGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass ( const TargetRegisterClass * VRC) const
Returns
A SGPR reg class with the same width as SRC

Definition at line 4122 of file SIRegisterInfo.cpp.

References assert(), getSGPRClassForBitWidth(), and Size.

◆ getEquivalentVGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass ( const TargetRegisterClass * SRC) const
Returns
A VGPR reg class with the same width as SRC

Definition at line 4084 of file SIRegisterInfo.cpp.

References assert(), getAlignedLo256VGPRClassForBitWidth(), llvm::MCRegisterClass::getID(), getVGPRClassForBitWidth(), and Size.

◆ getExec()

MCRegister SIRegisterInfo::getExec ( ) const

Definition at line 4523 of file SIRegisterInfo.cpp.

◆ getFrameIndexInstrOffset()

int64_t SIRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr * MI,
int Idx ) const
override

Definition at line 841 of file SIRegisterInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::MachineOperand::isImm(), llvm::SIInstrInfo::isMUBUF(), and MI.

◆ getFrameRegister()

Register SIRegisterInfo::getFrameRegister ( const MachineFunction & MF) const
override

Definition at line 536 of file SIRegisterInfo.cpp.

References llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::TargetFrameLowering::hasFP(), llvm::AMDGPUMachineFunctionInfo::isBottomOfStack(), and Register.

Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and llvm::SIFrameLowering::getFrameIndexReference().

◆ getHWRegIndex()

unsigned SIRegisterInfo::getHWRegIndex ( MCRegister Reg) const

Definition at line 3767 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::HWEncoding::REG_IDX_MASK.

Referenced by filterAndSortForAntiHintedRegs(), getNumUsedPhysRegs(), getReservedRegs(), and indirectCopyToAGPR().

◆ getLargestLegalSuperClass()

const TargetRegisterClass * SIRegisterInfo::getLargestLegalSuperClass ( const TargetRegisterClass * RC,
const MachineFunction & MF ) const
override

Definition at line 482 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterInfo::getLargestLegalSuperClass(), isAGPRClass(), and isVGPRClass().

◆ getNoPreservedMask()

const uint32_t * SIRegisterInfo::getNoPreservedMask ( ) const
override

Definition at line 473 of file SIRegisterInfo.cpp.

◆ getNumChannelsFromSubReg()

unsigned llvm::SIRegisterInfo::getNumChannelsFromSubReg ( unsigned SubReg) const
inline

Definition at line 454 of file SIRegisterInfo.h.

References getNumCoveredRegs().

◆ getNumCoveredRegs()

unsigned llvm::SIRegisterInfo::getNumCoveredRegs ( LaneBitmask LM)
inlinestatic

Definition at line 438 of file SIRegisterInfo.h.

References llvm::LaneBitmask::getAsInteger(), llvm::popcount(), and uint64_t.

Referenced by getNumChannelsFromSubReg(), and llvm::GCNRegPressure::inc().

◆ getNumUsedPhysRegs()

unsigned SIRegisterInfo::getNumUsedPhysRegs ( const MachineRegisterInfo & MRI,
const TargetRegisterClass & RC,
bool IncludeCalls = true ) const

Definition at line 4652 of file SIRegisterInfo.cpp.

References getHWRegIndex(), llvm::MCRegisterClass::getID(), llvm::MCRegisterClass::getRegisters(), llvm::MachineRegisterInfo::isPhysRegUsed(), Registers, and llvm::reverse().

◆ getRegAllocationHints()

bool SIRegisterInfo::getRegAllocationHints ( Register VirtReg,
ArrayRef< MCPhysReg > Order,
SmallVectorImpl< MCPhysReg > & Hints,
const MachineFunction & MF,
const VirtRegMap * VRM,
const LiveRegMatrix * Matrix ) const
override

Definition at line 4275 of file SIRegisterInfo.cpp.

References assert(), contains(), llvm::VirtRegMap::getPhys(), llvm::MachineRegisterInfo::getRegAllocationHint(), llvm::TargetRegisterInfo::getRegAllocationHints(), llvm::MachineFunction::getRegInfo(), llvm::VirtRegMap::hasPhys(), llvm::AMDGPU::isHi16Reg(), llvm::Register::isPhysical(), llvm::MachineRegisterInfo::isReserved(), Matrix, llvm::SmallVectorTemplateBase< T, bool >::push_back(), SIRegisterInfo(), llvm::AMDGPURI::Size16, llvm::AMDGPURI::Size32, and TRI.

◆ getRegAsmName()

StringRef SIRegisterInfo::getRegAsmName ( MCRegister Reg) const
override

Definition at line 3763 of file SIRegisterInfo.cpp.

References llvm::AMDGPUInstPrinter::getRegisterName().

◆ getRegClassAlignmentNumBits()

unsigned llvm::SIRegisterInfo::getRegClassAlignmentNumBits ( const TargetRegisterClass * RC) const
inline

Definition at line 491 of file SIRegisterInfo.h.

References llvm::RegTupleAlignUnitsMask, and llvm::MCRegisterClass::TSFlags.

Referenced by isRegClassAligned().

◆ getRegClassForBlockOp()

const TargetRegisterClass * llvm::SIRegisterInfo::getRegClassForBlockOp ( const MachineFunction & MF) const
inline

Definition at line 190 of file SIRegisterInfo.h.

◆ getRegClassForOperandReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForOperandReg ( const MachineRegisterInfo & MRI,
const MachineOperand & MO ) const

Definition at line 4212 of file SIRegisterInfo.cpp.

References llvm::MachineOperand::getReg(), getRegClassForReg(), and llvm::MachineOperand::getSubReg().

◆ getRegClassForReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForReg ( const MachineRegisterInfo & MRI,
Register Reg ) const

Definition at line 4206 of file SIRegisterInfo.cpp.

References llvm::MachineRegisterInfo::getRegClass().

Referenced by buildSpillLoadStore(), getRegClassForOperandReg(), isAGPR(), and isVGPR().

◆ getRegClassForSizeOnBank()

const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank ( unsigned Size,
const RegisterBank & Bank ) const

Definition at line 4489 of file SIRegisterInfo.cpp.

References assert(), getAGPRClassForBitWidth(), llvm::RegisterBank::getID(), getSGPRClassForBitWidth(), getVGPRClassForBitWidth(), getWaveMaskRegClass(), llvm_unreachable, and Size.

Referenced by getRegClassForTypeOnBank().

◆ getRegClassForTypeOnBank()

const TargetRegisterClass * llvm::SIRegisterInfo::getRegClassForTypeOnBank ( LLT Ty,
const RegisterBank & Bank ) const
inline

Definition at line 400 of file SIRegisterInfo.h.

References getRegClassForSizeOnBank().

Referenced by getConstrainedRegClassForReg().

◆ getRegPressureLimit()

unsigned SIRegisterInfo::getRegPressureLimit ( const TargetRegisterClass * RC,
MachineFunction & MF ) const
override

Definition at line 4233 of file SIRegisterInfo.cpp.

References llvm::SIMachineFunctionInfo::getDynamicVGPRBlockSize(), llvm::MCRegisterClass::getID(), and llvm::MachineFunction::getInfo().

Referenced by getRegPressureSetLimit(), and indirectCopyToAGPR().

◆ getRegPressureSetLimit()

unsigned SIRegisterInfo::getRegPressureSetLimit ( const MachineFunction & MF,
unsigned Idx ) const
override

Definition at line 4251 of file SIRegisterInfo.cpp.

References getRegPressureLimit(), and llvm_unreachable.

◆ getRegSplitParts()

ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts ( const TargetRegisterClass * RC,
unsigned EltSize ) const

Definition at line 4190 of file SIRegisterInfo.cpp.

References llvm::ArrayRef(), assert(), and llvm::AMDGPU::getRegBitWidth().

Referenced by expandSGPRCopy().

◆ getRegUnitPressureSets()

const int * SIRegisterInfo::getRegUnitPressureSets ( MCRegUnit RegUnit) const
override

Definition at line 4266 of file SIRegisterInfo.cpp.

References DenseMapInfo< LocallyHashedType >::Empty.

◆ getReservedRegs()

BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction & MF) const
override

Definition at line 602 of file SIRegisterInfo.cpp.

References assert(), llvm::divideCeil(), llvm::BitVector::empty(), llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs(), getBaseRegister(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getFunction(), getHWRegIndex(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getLongBranchReservedReg(), llvm::SIMachineFunctionInfo::getPerLaneVGPRMask(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRForEXECCopy(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs(), llvm::SIMachineFunctionInfo::getWWMReservedRegs(), hasBasePointer(), isAGPRClass(), isSGPRClass(), isVGPRClass(), llvm::Reserved, StressAGPRLimit, StressSGPRLimit, StressVGPRLimit, and llvm::BitVector::test().

◆ getReturnAddressReg()

MCRegister SIRegisterInfo::getReturnAddressReg ( const MachineFunction & MF) const

Definition at line 4483 of file SIRegisterInfo.cpp.

Referenced by spillSGPR().

◆ getScratchInstrOffset()

int64_t SIRegisterInfo::getScratchInstrOffset ( const MachineInstr * MI) const

Definition at line 833 of file SIRegisterInfo.cpp.

References assert(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.

Referenced by getFrameIndexInstrOffset(), isFrameOffsetLegal(), and needsFrameBaseReg().

◆ getSGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getSGPRClassForBitWidth ( unsigned BitWidth)
static

Definition at line 4040 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by getEquivalentSGPRClass(), getRegClassForSizeOnBank(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isIllegalRegisterType(), moreElementsToNextExistingRegClass(), and llvm::AMDGPUDAGToDAGISel::Select().

◆ getSpillWeightScaleFactor()

float llvm::SIRegisterInfo::getSpillWeightScaleFactor ( const TargetRegisterClass * RC) const
inlineoverride

Definition at line 525 of file SIRegisterInfo.h.

◆ getSubRegAlignmentNumBits()

unsigned SIRegisterInfo::getSubRegAlignmentNumBits ( const TargetRegisterClass * RC,
unsigned SubReg ) const

Definition at line 4637 of file SIRegisterInfo.cpp.

References llvm::HasAGPR, llvm::HasSGPR, llvm::HasVGPR, llvm::RegKindMask, and llvm::MCRegisterClass::TSFlags.

◆ getSubRegFromChannel()

unsigned SIRegisterInfo::getSubRegFromChannel ( unsigned Channel,
unsigned NumRegs = 1 )
static
Returns
the sub reg enum value for the given Channel (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)

Definition at line 575 of file SIRegisterInfo.cpp.

References assert(), llvm::size(), and SubRegFromChannelTableWidthMap.

Referenced by llvm::SITargetLowering::AddMemOpInit(), buildRegSequence(), buildSpillLoadStore(), computeIndirectRegAndOffset(), expandSGPRCopy(), and llvm::AMDGPUDAGToDAGISel::SelectBuildVector().

◆ getVCC()

MCRegister SIRegisterInfo::getVCC ( ) const

Definition at line 4519 of file SIRegisterInfo.cpp.

◆ getVectorSuperClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getVectorSuperClassForBitWidth ( unsigned BitWidth) const

Definition at line 4020 of file SIRegisterInfo.cpp.

References llvm::BitWidth, getAlignedVectorSuperClassForBitWidth(), and getAnyVectorSuperClassForBitWidth().

Referenced by getDefaultVectorSuperClassForBitWidth(), getEquivalentAVClass(), and isProperlyAlignedRC().

◆ getVGPR64Class()

const TargetRegisterClass * SIRegisterInfo::getVGPR64Class ( ) const

Definition at line 4527 of file SIRegisterInfo.cpp.

◆ getVGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getVGPRClassForBitWidth ( unsigned BitWidth) const

Definition at line 3836 of file SIRegisterInfo.cpp.

References llvm::BitWidth, getAlignedVGPRClassForBitWidth(), and getAnyVGPRClassForBitWidth().

Referenced by getDefaultVectorSuperClassForBitWidth(), getEquivalentVGPRClass(), getRegClassForSizeOnBank(), and isProperlyAlignedRC().

◆ getVRegFlagsOfReg()

SmallVector< StringLiteral > SIRegisterInfo::getVRegFlagsOfReg ( Register Reg,
const MachineFunction & MF ) const
override

Definition at line 4669 of file SIRegisterInfo.cpp.

References llvm::SIMachineFunctionInfo::checkFlag(), llvm::MachineFunction::getInfo(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::AMDGPU::VirtRegFlag::WWM_REG.

◆ getVRegFlagValue()

std::optional< uint8_t > llvm::SIRegisterInfo::getVRegFlagValue ( StringRef Name) const
inlineoverride

Definition at line 516 of file SIRegisterInfo.h.

References llvm::AMDGPU::VirtRegFlag::WWM_REG.

◆ getWaveMaskRegClass()

const TargetRegisterClass * llvm::SIRegisterInfo::getWaveMaskRegClass ( ) const
inline

Definition at line 413 of file SIRegisterInfo.h.

Referenced by getRegClassForSizeOnBank().

◆ hasAGPRs()

bool llvm::SIRegisterInfo::hasAGPRs ( const TargetRegisterClass * RC)
inlinestatic
Returns
true if this class contains AGPR registers.

Definition at line 292 of file SIRegisterInfo.h.

References llvm::HasAGPR, and llvm::MCRegisterClass::TSFlags.

Referenced by hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), and isVSSuperClass().

◆ hasBasePointer()

bool SIRegisterInfo::hasBasePointer ( const MachineFunction & MF) const

Definition at line 551 of file SIRegisterInfo.cpp.

References shouldRealignStack().

Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().

◆ hasSGPRs()

bool llvm::SIRegisterInfo::hasSGPRs ( const TargetRegisterClass * RC)
inlinestatic
Returns
true if this class contains SGPR registers.

Definition at line 297 of file SIRegisterInfo.h.

References llvm::HasSGPR, and llvm::MCRegisterClass::TSFlags.

Referenced by isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), and isVSSuperClass().

◆ hasVectorRegisters()

bool llvm::SIRegisterInfo::hasVectorRegisters ( const TargetRegisterClass * RC)
inlinestatic
Returns
true if this class contains any vector registers.

Definition at line 302 of file SIRegisterInfo.h.

References hasAGPRs(), and hasVGPRs().

Referenced by filterAndSortForAntiHintedRegs().

◆ hasVGPRs()

bool llvm::SIRegisterInfo::hasVGPRs ( const TargetRegisterClass * RC)
inlinestatic
Returns
true if this class contains VGPR registers.

Definition at line 287 of file SIRegisterInfo.h.

References llvm::HasVGPR, and llvm::MCRegisterClass::TSFlags.

Referenced by hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), and isVSSuperClass().

◆ isAGPR()

bool SIRegisterInfo::isAGPR ( const MachineRegisterInfo & MRI,
Register Reg ) const

Definition at line 4225 of file SIRegisterInfo.cpp.

References getRegClassForReg(), and isAGPRClass().

Referenced by isVectorRegister().

◆ isAGPRClass()

bool llvm::SIRegisterInfo::isAGPRClass ( const TargetRegisterClass * RC)
inlinestatic
Returns
true if this class contains only AGPR registers

Definition at line 272 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by buildSpillLoadStore(), llvm::SIInstrInfo::expandPostRAPseudo(), getLargestLegalSuperClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getReservedRegs(), isAGPR(), isProperlyAlignedRC(), and llvm::GCNRPTarget::isSaveBeneficial().

◆ isAsmClobberable()

bool SIRegisterInfo::isAsmClobberable ( const MachineFunction & MF,
MCRegister PhysReg ) const
override

Definition at line 783 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getRegInfo(), and llvm::MachineRegisterInfo::isReserved().

◆ isCFISavedRegsSpillEnabled()

bool SIRegisterInfo::isCFISavedRegsSpillEnabled ( ) const

Definition at line 584 of file SIRegisterInfo.cpp.

References EnableSpillCFISavedRegs.

◆ isChainScratchRegister()

bool SIRegisterInfo::isChainScratchRegister ( Register VGPR)
static

Definition at line 477 of file SIRegisterInfo.cpp.

Referenced by llvm::SIMachineFunctionInfo::allocateWWMSpill().

◆ isDivergentRegClass()

bool llvm::SIRegisterInfo::isDivergentRegClass ( const TargetRegisterClass * RC) const
inlineoverride

Definition at line 361 of file SIRegisterInfo.h.

References isSGPRClass().

◆ isFrameOffsetLegal()

bool SIRegisterInfo::isFrameOffsetLegal ( const MachineInstr * MI,
Register BaseReg,
int64_t Offset ) const
override

Definition at line 1121 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::FlatScratch, getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::AMDGPU::isInlinableIntLiteral(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.

◆ isProperlyAlignedRC()

bool SIRegisterInfo::isProperlyAlignedRC ( const TargetRegisterClass & RC) const

Definition at line 4604 of file SIRegisterInfo.cpp.

References assert(), getAGPRClassForBitWidth(), getVectorSuperClassForBitWidth(), getVGPRClassForBitWidth(), llvm::MCRegisterClass::hasSuperClassEq(), isAGPRClass(), isVectorSuperClass(), and isVGPRClass().

◆ isRegClassAligned()

bool llvm::SIRegisterInfo::isRegClassAligned ( const TargetRegisterClass * RC,
unsigned AlignNumBits ) const
inline

Definition at line 496 of file SIRegisterInfo.h.

References assert(), and getRegClassAlignmentNumBits().

◆ isSGPRClass()

bool llvm::SIRegisterInfo::isSGPRClass ( const TargetRegisterClass * RC)
inlinestatic
Returns
true if this class contains only SGPR registers

Definition at line 248 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by eliminateFrameIndex(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getReservedRegs(), isDivergentRegClass(), llvm::GCNRPTarget::isSaveBeneficial(), isSGPRClassID(), isSGPRPhysReg(), isSGPRReg(), and llvm::SITargetLowering::requiresUniformRegister().

◆ isSGPRClassID()

bool llvm::SIRegisterInfo::isSGPRClassID ( unsigned RCID) const
inline
Returns
true if this class ID contains only SGPR registers

Definition at line 253 of file SIRegisterInfo.h.

References getRegClass(), and isSGPRClass().

◆ isSGPRPhysReg()

bool llvm::SIRegisterInfo::isSGPRPhysReg ( Register Reg) const
inline

Definition at line 258 of file SIRegisterInfo.h.

References isSGPRClass(), and Reg.

◆ isSGPRReg()

bool SIRegisterInfo::isSGPRReg ( const MachineRegisterInfo & MRI,
Register Reg ) const

Definition at line 4073 of file SIRegisterInfo.cpp.

References llvm::MachineRegisterInfo::getRegClass(), and isSGPRClass().

Referenced by resolveFrameIndex().

◆ isUniformReg()

bool SIRegisterInfo::isUniformReg ( const MachineRegisterInfo & MRI,
const RegisterBankInfo & RBI,
Register Reg ) const
override

Definition at line 4180 of file SIRegisterInfo.cpp.

References llvm::RegisterBankInfo::getRegBank(), and llvm::RegisterBankInfo::isDivergentRegBank().

◆ isVectorRegister()

bool llvm::SIRegisterInfo::isVectorRegister ( const MachineRegisterInfo & MRI,
Register Reg ) const
inline

Definition at line 353 of file SIRegisterInfo.h.

References isAGPR(), isVGPR(), and Reg.

◆ isVectorSuperClass()

bool llvm::SIRegisterInfo::isVectorSuperClass ( const TargetRegisterClass * RC) const
inline
Returns
true only if this class contains both VGPR and AGPR registers

Definition at line 277 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by isProperlyAlignedRC().

◆ isVGPR()

bool SIRegisterInfo::isVGPR ( const MachineRegisterInfo & MRI,
Register Reg ) const

Definition at line 4218 of file SIRegisterInfo.cpp.

References getRegClassForReg(), and isVGPRClass().

Referenced by isVectorRegister().

◆ isVGPRClass()

bool llvm::SIRegisterInfo::isVGPRClass ( const TargetRegisterClass * RC)
inlinestatic
Returns
true if this class contains only VGPR registers

Definition at line 267 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by eliminateFrameIndex(), getLargestLegalSuperClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getReservedRegs(), isProperlyAlignedRC(), isVGPR(), and isVGPRPhysReg().

◆ isVGPRPhysReg()

bool llvm::SIRegisterInfo::isVGPRPhysReg ( Register Reg) const
inline

Definition at line 262 of file SIRegisterInfo.h.

References isVGPRClass(), and Reg.

◆ isVSSuperClass()

bool llvm::SIRegisterInfo::isVSSuperClass ( const TargetRegisterClass * RC) const
inline
Returns
true only if this class contains both VGPR and SGPR registers

Definition at line 282 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

◆ materializeFrameBaseRegister()

Register SIRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock * MBB,
int FrameIdx,
int64_t Offset ) const
override

Definition at line 940 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), DL, llvm::MachineFunction::getRegInfo(), llvm::Kill, MBB, llvm::Offset, llvm::MachineInstrBuilder::setOperandDead(), and TII.

◆ needsFrameBaseReg()

bool SIRegisterInfo::needsFrameBaseReg ( MachineInstr * MI,
int64_t Offset ) const
override

Definition at line 891 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::FlatScratch, getScratchInstrOffset(), isFIPlusImmOrVGPR(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.

◆ opCanUseInlineConstant()

bool SIRegisterInfo::opCanUseInlineConstant ( unsigned OpType) const
Returns
True if operands defined with this operand type can accept an inline constant. i.e. An integer value in the range (-16, 64) or -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.

Definition at line 4141 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.

◆ opCanUseLiteralConstant()

bool SIRegisterInfo::opCanUseLiteralConstant ( unsigned OpType) const
Returns
True if operands defined with this operand type can accept a literal constant (i.e. any 32-bit immediate).

Definition at line 4150 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.

◆ requiresFrameIndexReplacementScavenging()

bool SIRegisterInfo::requiresFrameIndexReplacementScavenging ( const MachineFunction & MF) const
override

Definition at line 821 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::hasStackObjects().

◆ requiresFrameIndexScavenging()

bool SIRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction & MF) const
override

Definition at line 812 of file SIRegisterInfo.cpp.

◆ requiresRegisterScavenging()

bool SIRegisterInfo::requiresRegisterScavenging ( const MachineFunction & Fn) const
override

Definition at line 801 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::hasCalls(), and llvm::MachineFrameInfo::hasStackObjects().

◆ requiresVirtualBaseRegisters()

bool SIRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction & Fn) const
override

Definition at line 827 of file SIRegisterInfo.cpp.

◆ reservedPrivateSegmentBufferReg()

MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg ( const MachineFunction & MF) const

Return the end register initially reserved for the scratch buffer in case spilling is needed.

Definition at line 597 of file SIRegisterInfo.cpp.

References getAlignedHighSGPRForRC().

◆ resolveFrameIndex()

void SIRegisterInfo::resolveFrameIndex ( MachineInstr & MI,
Register BaseReg,
int64_t Offset ) const
override

Definition at line 993 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::AMDGPU::FlatScratch, llvm::MachineOperand::getImm(), llvm::MachineFunction::getRegInfo(), I, llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isSGPRReg(), llvm_unreachable, MBB, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineOperand::setImm(), std::swap(), and TII.

◆ restoreSGPR()

bool SIRegisterInfo::restoreSGPR ( MachineBasicBlock::iterator MI,
int FI,
RegScavenger * RS,
SlotIndexes * Indexes = nullptr,
LiveIntervals * LIS = nullptr,
bool OnlyToVGPR = false,
bool SpillToPhysVGPRLane = false ) const

Definition at line 2328 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::ArrayRef< T >::empty(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRSpillToPhysicalVGPRLanes(), llvm::SIMachineFunctionInfo::getSGPRSpillToVirtualVGPRLanes(), llvm::ImplicitDefine, llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), Register, llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::SlotIndexes::replaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::SplitParts, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, and llvm::SGPRSpillBuilder::TmpVGPR.

Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().

◆ shouldApplyAntiHints()

bool SIRegisterInfo::shouldApplyAntiHints ( const MachineFunction & MF,
unsigned NumAllocatedVGPRs,
unsigned & MaxVGPRsForCurrentOccupancy ) const

Definition at line 4342 of file SIRegisterInfo.cpp.

References llvm::dbgs(), llvm::SIMachineFunctionInfo::getDynamicVGPRBlockSize(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getOccupancy(), and LLVM_DEBUG.

Referenced by filterAndSortForAntiHintedRegs().

◆ shouldRealignStack()

bool SIRegisterInfo::shouldRealignStack ( const MachineFunction & MF) const
override

Definition at line 788 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getInfo(), and llvm::TargetRegisterInfo::shouldRealignStack().

Referenced by hasBasePointer().

◆ spillEmergencySGPR()

bool SIRegisterInfo::spillEmergencySGPR ( MachineBasicBlock::iterator MI,
MachineBasicBlock & RestoreMBB,
Register SGPR,
RegScavenger * RS ) const

Definition at line 2408 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), assert(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::MachineBasicBlock::end(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::Implicit, llvm::ImplicitDefine, llvm::SGPRSpillBuilder::IsKill, llvm::Register::isPhysical(), llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), Register, llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::setMI(), llvm::SGPRSpillBuilder::SplitParts, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::Undef.

◆ spillSGPR()

bool SIRegisterInfo::spillSGPR ( MachineBasicBlock::iterator MI,
int FI,
RegScavenger * RS,
SlotIndexes * Indexes = nullptr,
LiveIntervals * LIS = nullptr,
bool OnlyToVGPR = false,
bool SpillToPhysVGPRLane = false,
bool NeedsCFI = false ) const

If OnlyToVGPR is true, this will only succeed if this manages to find a free VGPR lane to spill.

Definition at line 2167 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), assert(), llvm::SIFrameLowering::buildCFIForSGPRToVGPRSpill(), llvm::SIFrameLowering::buildCFIForSGPRToVMEMSpill(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::SGPRSpillBuilder::EltSize, llvm::ArrayRef< T >::empty(), llvm::MachineFunction::getFrameInfo(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), getReturnAddressReg(), llvm::SIMachineFunctionInfo::getSGPRSpillToPhysicalVGPRLanes(), llvm::SIMachineFunctionInfo::getSGPRSpillToVirtualVGPRLanes(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::Implicit, llvm::ImplicitDefine, llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::SGPRSpillBuilder::IsKill, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MF, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), Register, llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::SlotIndexes::replaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::ArrayRef< T >::size(), llvm::SGPRSpillBuilder::SplitParts, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, llvm::SGPRSpillBuilder::TRI, and llvm::Undef.

Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().

◆ spillSGPRToVGPR()

bool llvm::SIRegisterInfo::spillSGPRToVGPR ( ) const
inline

Definition at line 89 of file SIRegisterInfo.h.

The documentation for this class was generated from the following files:
Generated on for LLVM by doxygen 1.14.0