LLVM
12.0.0git
|
#include "Target/AMDGPU/SIRegisterInfo.h"
Static Public Member Functions | |
static unsigned | getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1) |
static const TargetRegisterClass * | getVGPRClassForBitWidth (unsigned BitWidth) |
static const TargetRegisterClass * | getAGPRClassForBitWidth (unsigned BitWidth) |
static const TargetRegisterClass * | getSGPRClassForBitWidth (unsigned BitWidth) |
static unsigned | getNumCoveredRegs (LaneBitmask LM) |
Definition at line 27 of file SIRegisterInfo.h.
SIRegisterInfo::SIRegisterInfo | ( | const GCNSubtarget & | ST | ) |
Definition at line 44 of file SIRegisterInfo.cpp.
References assert(), llvm::call_once(), E, llvm::MCRegister::from(), llvm::M0(), Offset, Reg, llvm::BitVector::resize(), llvm::BitVector::set(), llvm::Check::Size, llvm::size(), and SubRegFromChannelTableWidthMap.
void SIRegisterInfo::buildSGPRSpillLoadStore | ( | MachineBasicBlock::iterator | MI, |
int | Index, | ||
int | Offset, | ||
unsigned | EltSize, | ||
Register | VGPR, | ||
int64_t | VGPRLanes, | ||
RegScavenger * | RS, | ||
bool | IsLoad | ||
) | const |
Definition at line 1025 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), DL, llvm::ArrayRef< T >::empty(), llvm::GCNSubtarget::enableFlatScratch(), getBaseRegister(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineBasicBlock::getParent(), getPhysRegClass(), getRegSplitParts(), llvm::MachineFrameInfo::getStackID(), hasBasePointer(), Index, llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::RegState::Kill, MBB, MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, Offset, Register, llvm::TargetStackID::SGPRSpill, llvm::ArrayRef< T >::size(), and TII.
Referenced by restoreSGPR(), and spillSGPR().
|
override |
Definition at line 341 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterInfo::canRealignStack(), llvm::MachineFunction::getInfo(), and Info.
|
override |
Definition at line 1366 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::GCNSubtarget::enableFlatScratch(), getBaseRegister(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::AMDGPU::getNamedOperandIdx(), getNumSubRegsForSpillOp(), llvm::MachineOperand::getReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), hasBasePointer(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), Index, llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::AMDGPU::isInlinableLiteral32(), llvm::MachineOperand::isKill(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::Register::isValid(), llvm::RegState::Kill, llvm::M0(), MBB, MI, Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::report_fatal_error(), restoreSGPR(), llvm::RegScavenger::scavengeRegister(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), spillSGPR(), and TII.
bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS | ||
) | const |
Special case of eliminateFrameIndex.
Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.
Definition at line 1336 of file SIRegisterInfo.cpp.
References llvm_unreachable, MI, restoreSGPR(), and spillSGPR().
MachineInstr * SIRegisterInfo::findReachingDef | ( | Register | Reg, |
unsigned | SubReg, | ||
MachineInstr & | Use, | ||
MachineRegisterInfo & | MRI, | ||
LiveIntervals * | LIS | ||
) | const |
Definition at line 2172 of file SIRegisterInfo.cpp.
References assert(), llvm::tgtok::Def, llvm::VNInfo::def, llvm::Pass::getAnalysis(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::LiveIntervals::getRegUnit(), llvm::LiveRange::getVNInfoAt(), llvm::LiveIntervals::hasInterval(), llvm::LiveInterval::hasSubRanges(), llvm::SlotIndex::isValid(), llvm::MCRegisterInfo::DiffListIterator::isValid(), MRI, Reg, llvm::LiveInterval::subranges(), and SubReg.
MCRegister SIRegisterInfo::findUnusedRegister | ( | const MachineRegisterInfo & | MRI, |
const TargetRegisterClass * | RC, | ||
const MachineFunction & | MF, | ||
bool | ReserveHighestVGPR = false |
||
) | const |
Returns a lowest register that is not used at any point in the function.
If all registers are used, then this function will return AMDGPU::NoRegister. If ReserveHighestVGPR
= true, then return highest unused register.
Definition at line 2001 of file SIRegisterInfo.cpp.
References MRI, Reg, and llvm::reverse().
Definition at line 2226 of file SIRegisterInfo.cpp.
References assert(), getPhysRegClass(), and Reg.
Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::FoldImmediate().
|
static |
Definition at line 1773 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by getEquivalentAGPRClass(), getRegClassForSizeOnBank(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getSubRegClass(), and hasAGPRs().
Definition at line 182 of file SIRegisterInfo.cpp.
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR128 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 2257 of file SIRegisterInfo.cpp.
References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR32 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 2269 of file SIRegisterInfo.cpp.
References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().
ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR64 | ( | const MachineFunction & | MF | ) | const |
Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
Definition at line 2263 of file SIRegisterInfo.cpp.
References llvm::sys::path::begin(), llvm::GCNSubtarget::getMaxNumSGPRs(), and llvm::makeArrayRef().
Definition at line 178 of file SIRegisterInfo.cpp.
Register SIRegisterInfo::getBaseRegister | ( | ) | const |
Definition at line 176 of file SIRegisterInfo.cpp.
Referenced by buildSGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().
|
inline |
Definition at line 262 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::convertNonUniformIfRegion(), llvm::SIInstrInfo::convertNonUniformLoopRegion(), llvm::SIInstrInfo::getAddNoCarry(), llvm::GCNSubtarget::getBoolRC(), getRegClass(), llvm::SIInstrInfo::insertEQ(), llvm::SIInstrInfo::insertNE(), and llvm::SIInstrInfo::insertVectorSelect().
|
override |
Definition at line 115 of file SIRegisterInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, llvm::CallingConv::Cold, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), and llvm::MachineFunction::getFunction().
const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy | ( | const MachineFunction * | MF | ) | const |
Definition at line 133 of file SIRegisterInfo.cpp.
|
override |
Definition at line 137 of file SIRegisterInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, llvm::CallingConv::Cold, and llvm::CallingConv::Fast.
|
override |
Definition at line 2142 of file SIRegisterInfo.cpp.
References llvm::PointerUnion< PTs >::dyn_cast(), llvm::PointerUnion< PTs >::get(), llvm::MachineOperand::getReg(), getRegClassForTypeOnBank(), and MRI.
|
inlineoverride |
Definition at line 73 of file SIRegisterInfo.h.
const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC
Definition at line 1920 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), and llvm::Check::Size.
Referenced by llvm::SIInstrInfo::legalizeOperands().
const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass | ( | const TargetRegisterClass * | VRC | ) | const |
SRC
Definition at line 1928 of file SIRegisterInfo.cpp.
References assert(), getSGPRClassForBitWidth(), and llvm::Check::Size.
Referenced by llvm::SIInstrInfo::readlaneVGPRToSGPR().
const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass | ( | const TargetRegisterClass * | SRC | ) | const |
SRC
Definition at line 1912 of file SIRegisterInfo.cpp.
References assert(), getVGPRClassForBitWidth(), and llvm::Check::Size.
Referenced by llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALU(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
|
override |
Definition at line 394 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.
|
override |
Definition at line 154 of file SIRegisterInfo.cpp.
References llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::MachineFunction::getSubtarget(), llvm::SIFrameLowering::hasFP(), llvm::AMDGPUMachineFunction::isEntryFunction(), and Register.
Referenced by buildSGPRSpillLoadStore(), eliminateFrameIndex(), and llvm::SIFrameLowering::getFrameIndexReference().
|
inline |
Definition at line 134 of file SIRegisterInfo.h.
References Reg.
Referenced by llvm::SIInstrInfo::copyPhysReg(), and indirectCopyToAGPR().
Definition at line 150 of file SIRegisterInfo.cpp.
Definition at line 302 of file SIRegisterInfo.h.
References getNumCoveredRegs(), and SubReg.
Referenced by getSubRegClass().
|
inlinestatic |
Definition at line 286 of file SIRegisterInfo.h.
References llvm::countPopulation(), llvm::LaneBitmask::getAsInteger(), and llvm::BitmaskEnumDetail::Mask().
Referenced by getNumChannelsFromSubReg(), getUsedRegMask(), and llvm::GCNRegPressure::inc().
const TargetRegisterClass * SIRegisterInfo::getPhysRegClass | ( | MCRegister | Reg | ) | const |
Return the 'base' register class for this register.
e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
Definition at line 1827 of file SIRegisterInfo.cpp.
References Reg.
Referenced by buildSGPRSpillLoadStore(), llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::FoldImmediate(), get32BitRegister(), llvm::SIInstrInfo::getOpRegClass(), getRegClassForReg(), isSGPRReg(), restoreSGPR(), and spillSGPR().
|
override |
Definition at line 535 of file SIRegisterInfo.cpp.
|
override |
Definition at line 1740 of file SIRegisterInfo.cpp.
References llvm::AMDGPUInstPrinter::getRegisterName(), and Reg.
const TargetRegisterClass * SIRegisterInfo::getRegClass | ( | unsigned | RCID | ) | const |
Definition at line 2157 of file SIRegisterInfo.cpp.
References getBoolRC(), and getRegClass().
Referenced by llvm::SIInstrInfo::getOpRegClass(), llvm::SIInstrInfo::getOpSize(), llvm::SIInstrInfo::getRegClass(), llvm::SIInstrInfo::insertVectorSelect(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIInstrInfo::isOperandLegal(), isSGPRClassID(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALU(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getRegClassForReg | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2033 of file SIRegisterInfo.cpp.
References getPhysRegClass(), MRI, and Reg.
Referenced by isAGPR(), isVGPR(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::moveToVALU(), and llvm::SIInstrInfo::verifyInstruction().
const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank | ( | unsigned | Size, |
const RegisterBank & | Bank, | ||
const MachineRegisterInfo & | MRI | ||
) | const |
Definition at line 2122 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), llvm::RegisterBank::getID(), getSGPRClassForBitWidth(), getVGPRClassForBitWidth(), llvm_unreachable, llvm::max(), and llvm::Check::Size.
Referenced by getRegClassForTypeOnBank().
|
inline |
Definition at line 252 of file SIRegisterInfo.h.
References getRegClassForSizeOnBank(), llvm::LLT::getSizeInBits(), and MRI.
Referenced by getConstrainedRegClassForOperand().
|
override |
Definition at line 2074 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFunction(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize(), and llvm::min().
Referenced by getRegPressureSetLimit(), and indirectCopyToAGPR().
|
override |
Definition at line 2093 of file SIRegisterInfo.cpp.
References getRegPressureLimit(), and llvm_unreachable.
Referenced by llvm::GCNMaxOccupancySchedStrategy::initialize().
ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts | ( | const TargetRegisterClass * | RC, |
unsigned | EltSize | ||
) | const |
Definition at line 2017 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getRegBitWidth(), llvm::makeArrayRef(), and llvm::TargetRegisterClass::MC.
Referenced by buildSGPRSpillLoadStore(), llvm::SIInstrInfo::copyPhysReg(), expandSGPRCopy(), llvm::SIInstrInfo::materializeImmediate(), restoreSGPR(), and spillSGPR().
Definition at line 2107 of file SIRegisterInfo.cpp.
References llvm::Empty.
|
override |
Definition at line 202 of file SIRegisterInfo.cpp.
References assert(), contains(), llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs(), getBaseRegister(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs(), hasBasePointer(), llvm::GCNSubtarget::hasMAIInsts(), llvm::M0(), Reg, llvm::BitVector::set(), and llvm::SIMachineFunctionInfo::WWMReservedRegs.
MCRegister SIRegisterInfo::getReturnAddressReg | ( | const MachineFunction & | MF | ) | const |
Definition at line 2116 of file SIRegisterInfo.cpp.
int64_t SIRegisterInfo::getScratchInstrOffset | ( | const MachineInstr * | MI | ) | const |
Definition at line 386 of file SIRegisterInfo.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.
Referenced by getFrameIndexInstrOffset(), isFrameOffsetLegal(), and needsFrameBaseReg().
|
static |
Definition at line 1799 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by getEquivalentSGPRClass(), getRegClassForSizeOnBank(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), and getSubRegClass().
const TargetRegisterClass * SIRegisterInfo::getSubRegClass | ( | const TargetRegisterClass * | RC, |
unsigned | SubIdx | ||
) | const |
RC
for the given SubIdx
. If SubIdx
equals NoSubRegister, RC
will be returned. Definition at line 1937 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), getNumChannelsFromSubReg(), getSGPRClassForBitWidth(), getVGPRClassForBitWidth(), hasAGPRs(), isSGPRClass(), and llvm::Check::Size.
Channel
(e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) Definition at line 186 of file SIRegisterInfo.cpp.
References assert(), llvm::size(), and SubRegFromChannelTableWidthMap.
Referenced by computeIndirectRegAndOffset(), expandSGPRCopy(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().
MCRegister SIRegisterInfo::getVCC | ( | ) | const |
Definition at line 2152 of file SIRegisterInfo.cpp.
Referenced by llvm::SIInstrInfo::getAddNoCarry().
|
static |
Definition at line 1745 of file SIRegisterInfo.cpp.
References llvm::BitWidth.
Referenced by getEquivalentVGPRClass(), getRegClassForSizeOnBank(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), getSubRegClass(), hasAGPRs(), and hasVGPRs().
|
inline |
Definition at line 267 of file SIRegisterInfo.h.
Referenced by llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop().
bool SIRegisterInfo::hasAGPRs | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 1899 of file SIRegisterInfo.cpp.
References assert(), getAGPRClassForBitWidth(), getVGPRClassForBitWidth(), and llvm::Check::Size.
Referenced by llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::getMovOpcode(), getSubRegClass(), hasVectorRegisters(), isAGPR(), isAGPRClass(), isSGPRClass(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), and llvm::SIInstrInfo::storeRegToStackSlot().
bool SIRegisterInfo::hasBasePointer | ( | const MachineFunction & | MF | ) | const |
Definition at line 169 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::getNumFixedObjects().
Referenced by buildSGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().
|
inline |
Definition at line 170 of file SIRegisterInfo.h.
References hasAGPRs(), and hasVGPRs().
Referenced by llvm::SIInstrInfo::legalizeOperands().
bool SIRegisterInfo::hasVGPRs | ( | const TargetRegisterClass * | RC | ) | const |
Definition at line 1885 of file SIRegisterInfo.cpp.
References assert(), getVGPRClassForBitWidth(), and llvm::Check::Size.
Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::expandPostRAPseudo(), hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVGPR(), llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().
bool SIRegisterInfo::isAGPR | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2045 of file SIRegisterInfo.cpp.
References getRegClassForReg(), hasAGPRs(), MRI, and Reg.
Referenced by llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getVALUOp(), isVectorRegister(), and llvm::SIInstrInfo::legalizeOperandsVOP2().
|
inline |
Definition at line 159 of file SIRegisterInfo.h.
References hasAGPRs(), and hasVGPRs().
Referenced by llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass().
|
override |
Definition at line 2243 of file SIRegisterInfo.cpp.
|
inlineoverride |
Definition at line 221 of file SIRegisterInfo.h.
References isSGPRClass().
|
override |
Definition at line 520 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SIInstrInfo::isMUBUF(), MI, Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.
|
inline |
Definition at line 147 of file SIRegisterInfo.h.
References hasAGPRs(), and hasVGPRs().
Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getMovOpcode(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), getSubRegClass(), isDivergentRegClass(), isSGPRClassID(), isSGPRReg(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::materializeImmediate(), llvm::SITargetLowering::requiresUniformRegister(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIInstrInfo::usesConstantBus().
Definition at line 152 of file SIRegisterInfo.h.
References getRegClass(), and isSGPRClass().
bool SIRegisterInfo::isSGPRReg | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 1873 of file SIRegisterInfo.cpp.
References getPhysRegClass(), isSGPRClass(), MRI, and Reg.
Referenced by llvm::SIInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::isVGPRCopy(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::mayReadEXEC(), and llvm::SITargetLowering::requiresUniformRegister().
|
inline |
bool SIRegisterInfo::isVGPR | ( | const MachineRegisterInfo & | MRI, |
Register | Reg | ||
) | const |
Definition at line 2038 of file SIRegisterInfo.cpp.
References getRegClassForReg(), hasVGPRs(), MRI, and Reg.
Referenced by llvm::SIInstrInfo::canShrink(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::hasVGPRUses(), isVectorRegister(), and llvm::SIInstrInfo::legalizeOperandsVOP2().
|
override |
Definition at line 421 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MipsISD::Ins, llvm::RegState::Kill, MBB, MRI, Offset, and TII.
|
override |
Definition at line 408 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SIInstrInfo::isMUBUF(), MI, Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.
Definition at line 1958 of file SIRegisterInfo.cpp.
References llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and tryAddToFoldList().
Definition at line 1991 of file SIRegisterInfo.cpp.
References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal().
|
override |
Definition at line 374 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::hasStackObjects().
|
override |
Definition at line 365 of file SIRegisterInfo.cpp.
|
override |
Definition at line 354 of file SIRegisterInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::hasCalls(), llvm::MachineFrameInfo::hasStackObjects(), and Info.
|
override |
Definition at line 380 of file SIRegisterInfo.cpp.
MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg | ( | const MachineFunction & | MF | ) | const |
Return the end register initially reserved for the scratch buffer in case spilling is needed.
Definition at line 195 of file SIRegisterInfo.cpp.
References llvm::alignDown(), and llvm::GCNSubtarget::getMaxNumSGPRs().
|
override |
Definition at line 467 of file SIRegisterInfo.cpp.
References assert(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::MachineOperand::isReg(), llvm_unreachable, MBB, MI, Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineOperand::setImm(), and TII.
bool SIRegisterInfo::restoreSGPR | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
bool | OnlyToVGPR = false |
||
) | const |
Definition at line 1254 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), buildSGPRSpillLoadStore(), DL, llvm::numbers::e, llvm::ArrayRef< T >::empty(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), getPhysRegClass(), getRegSplitParts(), llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills(), llvm::RegState::ImplicitDefine, Index, llvm::SIMachineFunctionInfo::SpilledReg::Lane, llvm::M0(), MBB, MI, llvm::min(), llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs, Offset, Register, llvm::RegScavenger::scavengeRegister(), llvm::RegScavenger::setRegUsed(), llvm::ArrayRef< T >::size(), SubReg, TII, and llvm::SIMachineFunctionInfo::SpilledReg::VGPR.
Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().
|
override |
Definition at line 2053 of file SIRegisterInfo.cpp.
|
override |
Definition at line 1967 of file SIRegisterInfo.cpp.
bool SIRegisterInfo::spillSGPR | ( | MachineBasicBlock::iterator | MI, |
int | FI, | ||
RegScavenger * | RS, | ||
bool | OnlyToVGPR = false |
||
) | const |
If OnlyToVGPR
is true, this will only succeed if this.
Definition at line 1138 of file SIRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), assert(), llvm::BuildMI(), buildSGPRSpillLoadStore(), DL, llvm::numbers::e, llvm::ArrayRef< T >::empty(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), getPhysRegClass(), getRegSplitParts(), llvm::SIMachineFunctionInfo::getSGPRToVGPRSpills(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, Index, llvm::SIMachineFunctionInfo::SpilledReg::Lane, llvm::M0(), MBB, MI, llvm::min(), llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs, Offset, Register, llvm::RegScavenger::scavengeRegister(), llvm::RegScavenger::setRegUsed(), llvm::ArrayRef< T >::size(), SubReg, TII, llvm::RegState::Undef, and llvm::SIMachineFunctionInfo::SpilledReg::VGPR.
Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().
|
inline |
Definition at line 55 of file SIRegisterInfo.h.
Referenced by llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().