llvm::SIRegisterInfo Class Reference

#include "Target/AMDGPU/SIRegisterInfo.h"

Inheritance diagram for llvm::SIRegisterInfo:

Classes
struct	SpilledReg

Public Member Functions
	SIRegisterInfo (const GCNSubtarget &ST)
bool	spillSGPRToVGPR () const
MCRegister	reservedPrivateSegmentBufferReg (const MachineFunction &MF) const
	Return the end register initially reserved for the scratch buffer in case spilling is needed.
BitVector	getReservedRegs (const MachineFunction &MF) const override
bool	isAsmClobberable (const MachineFunction &MF, MCRegister PhysReg) const override
const MCPhysReg *	getCalleeSavedRegs (const MachineFunction *MF) const override
const MCPhysReg *	getCalleeSavedRegsViaCopy (const MachineFunction *MF) const
const uint32_t *	getCallPreservedMask (const MachineFunction &MF, CallingConv::ID) const override
const uint32_t *	getNoPreservedMask () const override
unsigned	getCSRFirstUseCost () const override
const TargetRegisterClass *	getLargestLegalSuperClass (const TargetRegisterClass *RC, const MachineFunction &MF) const override
Register	getFrameRegister (const MachineFunction &MF) const override
bool	hasBasePointer (const MachineFunction &MF) const
Register	getBaseRegister () const
bool	shouldRealignStack (const MachineFunction &MF) const override
bool	requiresRegisterScavenging (const MachineFunction &Fn) const override
bool	requiresFrameIndexScavenging (const MachineFunction &MF) const override
bool	requiresFrameIndexReplacementScavenging (const MachineFunction &MF) const override
bool	requiresVirtualBaseRegisters (const MachineFunction &Fn) const override
int64_t	getScratchInstrOffset (const MachineInstr *MI) const
int64_t	getFrameIndexInstrOffset (const MachineInstr *MI, int Idx) const override
bool	needsFrameBaseReg (MachineInstr *MI, int64_t Offset) const override
Register	materializeFrameBaseRegister (MachineBasicBlock *MBB, int FrameIdx, int64_t Offset) const override
void	resolveFrameIndex (MachineInstr &MI, Register BaseReg, int64_t Offset) const override
bool	isFrameOffsetLegal (const MachineInstr *MI, Register BaseReg, int64_t Offset) const override
const TargetRegisterClass *	getPointerRegClass (const MachineFunction &MF, unsigned Kind=0) const override
const TargetRegisterClass *	getCrossCopyRegClass (const TargetRegisterClass *RC) const override
	Returns a legal register class to copy a register in the specified class to or from.
void	buildVGPRSpillLoadStore (SGPRSpillBuilder &SB, int Index, int Offset, bool IsLoad, bool IsKill=true) const
bool	spillSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
	If OnlyToVGPR is true, this will only succeed if this.
bool	restoreSGPR (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr, bool OnlyToVGPR=false) const
bool	spillEmergencySGPR (MachineBasicBlock::iterator MI, MachineBasicBlock &RestoreMBB, Register SGPR, RegScavenger *RS) const
bool	supportsBackwardScavenger () const override
bool	eliminateFrameIndex (MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const override
bool	eliminateSGPRToVGPRSpillFrameIndex (MachineBasicBlock::iterator MI, int FI, RegScavenger *RS, SlotIndexes *Indexes=nullptr, LiveIntervals *LIS=nullptr) const
	Special case of eliminateFrameIndex.
StringRef	getRegAsmName (MCRegister Reg) const override
unsigned	getHWRegIndex (MCRegister Reg) const
LLVM_READONLY const TargetRegisterClass *	getVGPRClassForBitWidth (unsigned BitWidth) const
LLVM_READONLY const TargetRegisterClass *	getAGPRClassForBitWidth (unsigned BitWidth) const
LLVM_READONLY const TargetRegisterClass *	getVectorSuperClassForBitWidth (unsigned BitWidth) const
bool	isSGPRClassID (unsigned RCID) const
bool	isSGPRReg (const MachineRegisterInfo &MRI, Register Reg) const
bool	isVectorSuperClass (const TargetRegisterClass *RC) const
bool	isVSSuperClass (const TargetRegisterClass *RC) const
const TargetRegisterClass *	getEquivalentVGPRClass (const TargetRegisterClass *SRC) const
const TargetRegisterClass *	getEquivalentAGPRClass (const TargetRegisterClass *SRC) const
const TargetRegisterClass *	getEquivalentSGPRClass (const TargetRegisterClass *VRC) const
const TargetRegisterClass *	getCompatibleSubRegClass (const TargetRegisterClass *SuperRC, const TargetRegisterClass *SubRC, unsigned SubIdx) const
	Returns a register class which is compatible with SuperRC, such that a subregister exists with class SubRC with subregister index SubIdx.
bool	shouldRewriteCopySrc (const TargetRegisterClass *DefRC, unsigned DefSubReg, const TargetRegisterClass *SrcRC, unsigned SrcSubReg) const override
bool	opCanUseLiteralConstant (unsigned OpType) const
bool	opCanUseInlineConstant (unsigned OpType) const
MCRegister	findUnusedRegister (const MachineRegisterInfo &MRI, const TargetRegisterClass *RC, const MachineFunction &MF, bool ReserveHighestVGPR=false) const
	Returns a lowest register that is not used at any point in the function.
const TargetRegisterClass *	getRegClassForReg (const MachineRegisterInfo &MRI, Register Reg) const
const TargetRegisterClass *	getRegClassForOperandReg (const MachineRegisterInfo &MRI, const MachineOperand &MO) const
bool	isVGPR (const MachineRegisterInfo &MRI, Register Reg) const
bool	isAGPR (const MachineRegisterInfo &MRI, Register Reg) const
bool	isVectorRegister (const MachineRegisterInfo &MRI, Register Reg) const
bool	isDivergentRegClass (const TargetRegisterClass *RC) const override
bool	isUniformReg (const MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register Reg) const override
ArrayRef< int16_t >	getRegSplitParts (const TargetRegisterClass *RC, unsigned EltSize) const
bool	shouldCoalesce (MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override
unsigned	getRegPressureLimit (const TargetRegisterClass *RC, MachineFunction &MF) const override
unsigned	getRegPressureSetLimit (const MachineFunction &MF, unsigned Idx) const override
const int *	getRegUnitPressureSets (unsigned RegUnit) const override
MCRegister	getReturnAddressReg (const MachineFunction &MF) const
const TargetRegisterClass *	getRegClassForSizeOnBank (unsigned Size, const RegisterBank &Bank) const
const TargetRegisterClass *	getRegClassForTypeOnBank (LLT Ty, const RegisterBank &Bank) const
const TargetRegisterClass *	getConstrainedRegClassForOperand (const MachineOperand &MO, const MachineRegisterInfo &MRI) const override
const TargetRegisterClass *	getBoolRC () const
const TargetRegisterClass *	getWaveMaskRegClass () const
const TargetRegisterClass *	getVGPR64Class () const
MCRegister	getVCC () const
MCRegister	getExec () const
const TargetRegisterClass *	getRegClass (unsigned RCID) const
MachineInstr *	findReachingDef (Register Reg, unsigned SubReg, MachineInstr &Use, MachineRegisterInfo &MRI, LiveIntervals *LIS) const
const uint32_t *	getAllVGPRRegMask () const
const uint32_t *	getAllAGPRRegMask () const
const uint32_t *	getAllVectorRegMask () const
const uint32_t *	getAllAllocatableSRegMask () const
unsigned	getChannelFromSubReg (unsigned SubReg) const
unsigned	getNumChannelsFromSubReg (unsigned SubReg) const
MCPhysReg	get32BitRegister (MCPhysReg Reg) const
bool	isProperlyAlignedRC (const TargetRegisterClass &RC) const
const TargetRegisterClass *	getProperlyAlignedRC (const TargetRegisterClass *RC) const
ArrayRef< MCPhysReg >	getAllSGPR128 (const MachineFunction &MF) const
	Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.
ArrayRef< MCPhysReg >	getAllSGPR64 (const MachineFunction &MF) const
	Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.
ArrayRef< MCPhysReg >	getAllSGPR32 (const MachineFunction &MF) const
	Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.
void	buildSpillLoadStore (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned LoadStoreOp, int Index, Register ValueReg, bool ValueIsKill, MCRegister ScratchOffsetReg, int64_t InstrOffset, MachineMemOperand *MMO, RegScavenger *RS, LivePhysRegs *LiveRegs=nullptr) const
unsigned	getRegClassAlignmentNumBits (const TargetRegisterClass *RC) const
bool	isRegClassAligned (const TargetRegisterClass *RC, unsigned AlignNumBits) const
unsigned	getSubRegAlignmentNumBits (const TargetRegisterClass *RC, unsigned SubReg) const

Static Public Member Functions
static unsigned	getSubRegFromChannel (unsigned Channel, unsigned NumRegs=1)
static LLVM_READONLY const TargetRegisterClass *	getSGPRClassForBitWidth (unsigned BitWidth)
static bool	isSGPRClass (const TargetRegisterClass *RC)
static bool	isVGPRClass (const TargetRegisterClass *RC)
static bool	isAGPRClass (const TargetRegisterClass *RC)
static bool	hasVGPRs (const TargetRegisterClass *RC)
static bool	hasAGPRs (const TargetRegisterClass *RC)
static bool	hasSGPRs (const TargetRegisterClass *RC)
static bool	hasVectorRegisters (const TargetRegisterClass *RC)
static unsigned	getNumCoveredRegs (LaneBitmask LM)

Detailed Description

Definition at line 30 of file SIRegisterInfo.h.

Constructor & Destructor Documentation

SIRegisterInfo()

SIRegisterInfo::SIRegisterInfo

(

const GCNSubtarget &

ST

)

Definition at line 319 of file SIRegisterInfo.cpp.

References assert(), llvm::call_once(), E, llvm::MCRegister::from(), Idx, llvm::Offset, llvm::BitVector::resize(), llvm::BitVector::set(), llvm::size(), Size, and SubRegFromChannelTableWidthMap.

Member Function Documentation

buildSpillLoadStore()

void SIRegisterInfo::buildSpillLoadStore	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		unsigned	LoadStoreOp,
		int	Index,
		Register	ValueReg,
		bool	ValueIsKill,
		MCRegister	ScratchOffsetReg,
		int64_t	InstrOffset,
		MachineMemOperand *	MMO,
		RegScavenger *	RS,
		LivePhysRegs *	LiveRegs = nullptr
	)		const

Definition at line 1290 of file SIRegisterInfo.cpp.

References llvm::Add, llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::LivePhysRegs::available(), llvm::BuildMI(), llvm::commonAlignment(), llvm::LivePhysRegs::contains(), DL, llvm::MachineBasicBlock::end(), llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getConstantBusLimit(), llvm::getDefRegState(), llvm::MachineMemOperand::getFlags(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), getFlatScratchSpillOpcode(), llvm::MachineFunction::getFrameInfo(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getObjectOffset(), getOffenMUBUFLoad(), getOffenMUBUFStore(), llvm::MachineBasicBlock::getParent(), llvm::MachineMemOperand::getPointerInfo(), llvm::AMDGPU::getRegBitWidth(), getRegClassForReg(), llvm::MachineFunction::getRegInfo(), getSubRegFromChannel(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::MachinePointerInfo::getWithOffset(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, isAGPRClass(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::RegScavenger::isRegUsed(), llvm::MachineRegisterInfo::isReserved(), llvm::RegState::Kill, MBB, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineInstr::ReloadReuse, llvm::report_fatal_error(), llvm::RegScavenger::scavengeRegister(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineInstr::setAsmPrinterFlag(), llvm::RegScavenger::setRegUsed(), Size, spillVGPRtoAGPR(), SubReg, and TII.

Referenced by buildVGPRSpillLoadStore(), and eliminateFrameIndex().

buildVGPRSpillLoadStore()

void SIRegisterInfo::buildVGPRSpillLoadStore	(	SGPRSpillBuilder &	SB,
		int	Index,
		int	Offset,
		bool	IsLoad,
		bool	IsKill = true
	)		const

Definition at line 1684 of file SIRegisterInfo.cpp.

References llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), buildSpillLoadStore(), llvm::SGPRSpillBuilder::DL, llvm::SGPRSpillBuilder::EltSize, llvm::GCNSubtarget::enableFlatScratch(), getBaseRegister(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlign(), llvm::MachineFrameInfo::getStackID(), hasBasePointer(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MF, llvm::SGPRSpillBuilder::MFI, llvm::SGPRSpillBuilder::MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::Offset, llvm::SGPRSpillBuilder::RS, llvm::TargetStackID::SGPRSpill, and llvm::SGPRSpillBuilder::TmpVGPR.

Referenced by llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), and llvm::SGPRSpillBuilder::restore().

eliminateFrameIndex()

bool SIRegisterInfo::eliminateFrameIndex ( MachineBasicBlock::iterator  MI, int  SPAdj, unsigned  FIOperandNum, RegScavenger *  RS  ) const

override

Definition at line 2025 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledVGPRs(), assert(), llvm::BuildMI(), buildMUBUFOffsetLoadStore(), buildSpillLoadStore(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::SIInstrFlags::FlatScratch, getBaseRegister(), llvm::AMDGPU::getFlatScratchInstSTfromSS(), llvm::AMDGPU::getFlatScratchInstSVfromSVS(), llvm::MachineFunction::getFrameInfo(), getFrameRegister(), llvm::MachineOperand::getImm(), llvm::MachineFunction::getInfo(), llvm::MachineInstrBuilder::getInstr(), llvm::GCNSubtarget::getInstrInfo(), llvm::AMDGPU::getNamedOperandIdx(), getNumSubRegsForSpillOp(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstrBuilder::getReg(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::AMDGPUSubtarget::getWavefrontSizeLog2(), hasBasePointer(), llvm::GCNSubtarget::hasFlatScratchSTMode(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPU::hasNamedOperand(), I, llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::AMDGPU::isInlinableLiteral32(), llvm::MachineOperand::isKill(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::RegScavenger::isRegUsed(), isSGPRClass(), llvm::Register::isValid(), llvm::RegState::Kill, MBB, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::report_fatal_error(), restoreSGPR(), llvm::RegScavenger::scavengeRegister(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setIsDead(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), spillSGPR(), and TII.

eliminateSGPRToVGPRSpillFrameIndex()

bool SIRegisterInfo::eliminateSGPRToVGPRSpillFrameIndex	(	MachineBasicBlock::iterator	MI,
		int	FI,
		RegScavenger *	RS,
		SlotIndexes *	Indexes = nullptr,
		LiveIntervals *	LIS = nullptr
	)		const

Special case of eliminateFrameIndex.

Returns true if the SGPR was spilled to a VGPR and the stack slot can be safely eliminated when all other users are handled.

Definition at line 1986 of file SIRegisterInfo.cpp.

References llvm_unreachable, MI, restoreSGPR(), and spillSGPR().

findReachingDef()

MachineInstr * SIRegisterInfo::findReachingDef	(	Register	Reg,
		unsigned	SubReg,
		MachineInstr &	Use,
		MachineRegisterInfo &	MRI,
		LiveIntervals *	LIS
	)		const

Definition at line 3078 of file SIRegisterInfo.cpp.

References assert(), llvm::Pass::getAnalysis(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::LiveIntervals::getRegUnit(), llvm::LiveRange::getVNInfoAt(), llvm::LiveIntervals::hasInterval(), llvm::LiveInterval::hasSubRanges(), llvm::SlotIndex::isValid(), llvm::MCRegisterInfo::DiffListIterator::isValid(), MRI, llvm::LiveInterval::subranges(), and SubReg.

findUnusedRegister()

MCRegister SIRegisterInfo::findUnusedRegister	(	const MachineRegisterInfo &	MRI,
		const TargetRegisterClass *	RC,
		const MachineFunction &	MF,
		bool	ReserveHighestVGPR = false
	)		const

Returns a lowest register that is not used at any point in the function.

If all registers are used, then this function will return AMDGPU::NoRegister. If ReserveHighestVGPR = true, then return highest unused register.

Definition at line 2879 of file SIRegisterInfo.cpp.

References MRI, and llvm::reverse().

get32BitRegister()

MCPhysReg SIRegisterInfo::get32BitRegister

(

MCPhysReg

Reg

)

const

Definition at line 3132 of file SIRegisterInfo.cpp.

References assert().

Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::FoldImmediate().

getAGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getAGPRClassForBitWidth

(

unsigned

BitWidth

)

const

Definition at line 2670 of file SIRegisterInfo.cpp.

References llvm::BitWidth, getAlignedAGPRClassForBitWidth(), getAnyAGPRClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().

Referenced by getEquivalentAGPRClass(), getRegClassForSizeOnBank(), and isProperlyAlignedRC().

getAllAGPRRegMask()

const uint32_t * SIRegisterInfo::getAllAGPRRegMask

(

)

const

Definition at line 515 of file SIRegisterInfo.cpp.

getAllAllocatableSRegMask()

const uint32_t * SIRegisterInfo::getAllAllocatableSRegMask

(

)

const

Definition at line 523 of file SIRegisterInfo.cpp.

getAllSGPR128()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR128

(

const MachineFunction &

MF

)

const

Return all SGPR128 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 3184 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::getMaxNumSGPRs().

getAllSGPR32()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR32

(

const MachineFunction &

MF

)

const

Return all SGPR32 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 3194 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::getMaxNumSGPRs().

getAllSGPR64()

ArrayRef< MCPhysReg > SIRegisterInfo::getAllSGPR64

(

const MachineFunction &

MF

)

const

Return all SGPR64 which satisfy the waves per execution unit requirement of the subtarget.

Definition at line 3189 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::getMaxNumSGPRs().

getAllVectorRegMask()

const uint32_t * SIRegisterInfo::getAllVectorRegMask

(

)

const

Definition at line 519 of file SIRegisterInfo.cpp.

getAllVGPRRegMask()

const uint32_t * SIRegisterInfo::getAllVGPRRegMask

(

)

const

Definition at line 511 of file SIRegisterInfo.cpp.

getBaseRegister()

Register SIRegisterInfo::getBaseRegister

(

)

const

Definition at line 509 of file SIRegisterInfo.cpp.

Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().

getBoolRC()

const TargetRegisterClass * llvm::SIRegisterInfo::getBoolRC ( ) const

inline

Definition at line 333 of file SIRegisterInfo.h.

Referenced by llvm::SIInstrInfo::convertNonUniformIfRegion(), llvm::SIInstrInfo::convertNonUniformLoopRegion(), llvm::SIInstrInfo::getAddNoCarry(), llvm::GCNSubtarget::getBoolRC(), getRegClass(), llvm::SIInstrInfo::insertEQ(), llvm::SIInstrInfo::insertNE(), and llvm::SIInstrInfo::insertVectorSelect().

getCalleeSavedRegs()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegs ( const MachineFunction *  MF ) const

override

Definition at line 388 of file SIRegisterInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, CC, llvm::CallingConv::Cold, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::GCNSubtarget::hasGFX90AInsts().

getCalleeSavedRegsViaCopy()

const MCPhysReg * SIRegisterInfo::getCalleeSavedRegsViaCopy

(

const MachineFunction *

MF

)

const

Definition at line 409 of file SIRegisterInfo.cpp.

getCallPreservedMask()

const uint32_t * SIRegisterInfo::getCallPreservedMask ( const MachineFunction &  MF, CallingConv::ID  CC  ) const

override

Definition at line 413 of file SIRegisterInfo.cpp.

References llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::C, CC, llvm::CallingConv::Cold, llvm::CallingConv::Fast, and llvm::GCNSubtarget::hasGFX90AInsts().

getChannelFromSubReg()

unsigned llvm::SIRegisterInfo::getChannelFromSubReg ( unsigned  SubReg ) const

inline

Definition at line 376 of file SIRegisterInfo.h.

References SubReg.

Referenced by expandSGPRCopy(), and llvm::SIInstrInfo::verifyInstruction().

getCompatibleSubRegClass()

const TargetRegisterClass * SIRegisterInfo::getCompatibleSubRegClass	(	const TargetRegisterClass *	SuperRC,
		const TargetRegisterClass *	SubRC,
		unsigned	SubIdx
	)		const

Returns a register class which is compatible with SuperRC, such that a subregister exists with class SubRC with subregister index SubIdx.

If this is impossible (e.g., an unaligned subregister index within a register tuple), return null.

Definition at line 2827 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterClass::hasSubClassEq().

Referenced by llvm::SIInstrInfo::verifyInstruction().

getConstrainedRegClassForOperand()

const TargetRegisterClass * SIRegisterInfo::getConstrainedRegClassForOperand ( const MachineOperand &  MO, const MachineRegisterInfo &  MRI  ) const

override

Definition at line 3036 of file SIRegisterInfo.cpp.

References llvm::PointerUnion< PTs >::dyn_cast(), llvm::MachineOperand::getReg(), getRegClassForTypeOnBank(), and MRI.

getCrossCopyRegClass()

const TargetRegisterClass * SIRegisterInfo::getCrossCopyRegClass ( const TargetRegisterClass *  RC ) const

override

Returns a legal register class to copy a register in the specified class to or from.

If it is possible to copy the register directly without using a cross register class copy, return the specified RC. Returns NULL if it is not possible to copy between two registers of the specified class.

Definition at line 915 of file SIRegisterInfo.cpp.

References getEquivalentVGPRClass(), getWaveMaskRegClass(), llvm::GCNSubtarget::hasGFX90AInsts(), and isAGPRClass().

getCSRFirstUseCost()

unsigned llvm::SIRegisterInfo::getCSRFirstUseCost ( ) const

inlineoverride

Definition at line 89 of file SIRegisterInfo.h.

getEquivalentAGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentAGPRClass

(

const TargetRegisterClass *

SRC

)

const

Returns

An AGPR reg class with the same width as SRC

Definition at line 2809 of file SIRegisterInfo.cpp.

References assert(), getAGPRClassForBitWidth(), and Size.

Referenced by llvm::SIInstrInfo::legalizeOperands().

getEquivalentSGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentSGPRClass

(

const TargetRegisterClass *

VRC

)

const

Returns

A SGPR reg class with the same width as SRC

Definition at line 2817 of file SIRegisterInfo.cpp.

References assert(), getSGPRClassForBitWidth(), and Size.

Referenced by llvm::SIInstrInfo::readlaneVGPRToSGPR().

getEquivalentVGPRClass()

const TargetRegisterClass * SIRegisterInfo::getEquivalentVGPRClass

(

const TargetRegisterClass *

SRC

)

const

Returns

A VGPR reg class with the same width as SRC

Definition at line 2801 of file SIRegisterInfo.cpp.

References assert(), getVGPRClassForBitWidth(), and Size.

Referenced by getCrossCopyRegClass(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().

getExec()

MCRegister SIRegisterInfo::getExec

(

)

const

Definition at line 3052 of file SIRegisterInfo.cpp.

getFrameIndexInstrOffset()

int64_t SIRegisterInfo::getFrameIndexInstrOffset ( const MachineInstr *  MI, int  Idx  ) const

override

Definition at line 762 of file SIRegisterInfo.cpp.

References assert(), llvm::AMDGPU::getNamedOperandIdx(), getScratchInstrOffset(), Idx, llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.

getFrameRegister()

Register SIRegisterInfo::getFrameRegister ( const MachineFunction &  MF ) const

override

Definition at line 488 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::getFrameLowering(), llvm::MachineFunction::getInfo(), and llvm::SIFrameLowering::hasFP().

Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and llvm::SIFrameLowering::getFrameIndexReference().

getHWRegIndex()

unsigned llvm::SIRegisterInfo::getHWRegIndex ( MCRegister  Reg ) const

inline

Definition at line 168 of file SIRegisterInfo.h.

References Reg.

Referenced by llvm::SIInstrInfo::copyPhysReg(), indirectCopyToAGPR(), and llvm::SIInstrInfo::verifyInstruction().

getLargestLegalSuperClass()

const TargetRegisterClass * SIRegisterInfo::getLargestLegalSuperClass ( const TargetRegisterClass *  RC, const MachineFunction &  MF  ) const

override

Definition at line 434 of file SIRegisterInfo.cpp.

References llvm::TargetRegisterInfo::getLargestLegalSuperClass(), llvm::GCNSubtarget::hasMAIInsts(), isAGPRClass(), and isVGPRClass().

Referenced by llvm::SIInstrInfo::isLegalRegOperand().

getNoPreservedMask()

const uint32_t * SIRegisterInfo::getNoPreservedMask ( ) const

override

Definition at line 429 of file SIRegisterInfo.cpp.

getNumChannelsFromSubReg()

unsigned llvm::SIRegisterInfo::getNumChannelsFromSubReg ( unsigned  SubReg ) const

inline

Definition at line 381 of file SIRegisterInfo.h.

References getNumCoveredRegs(), and SubReg.

getNumCoveredRegs()

static unsigned llvm::SIRegisterInfo::getNumCoveredRegs ( LaneBitmask  LM )

inlinestatic

Definition at line 365 of file SIRegisterInfo.h.

References llvm::LaneBitmask::getAsInteger(), and llvm::popcount().

Referenced by getNumChannelsFromSubReg(), getUsedRegMask(), and llvm::GCNRegPressure::inc().

getPointerRegClass()

const TargetRegisterClass * SIRegisterInfo::getPointerRegClass ( const MachineFunction &  MF, unsigned  Kind = 0  ) const

override

Definition at line 906 of file SIRegisterInfo.cpp.

getProperlyAlignedRC()

const TargetRegisterClass * SIRegisterInfo::getProperlyAlignedRC

(

const TargetRegisterClass *

RC

)

const

Definition at line 3165 of file SIRegisterInfo.cpp.

References getAlignedAGPRClassForBitWidth(), getAlignedVectorSuperClassForBitWidth(), getAlignedVGPRClassForBitWidth(), isAGPRClass(), isVectorSuperClass(), isVGPRClass(), llvm::GCNSubtarget::needsAlignedVGPRs(), and Size.

Referenced by adjustAllocatableRegClass().

getRegAsmName()

StringRef SIRegisterInfo::getRegAsmName ( MCRegister  Reg ) const

override

Definition at line 2525 of file SIRegisterInfo.cpp.

References llvm::AMDGPUInstPrinter::getRegisterName().

getRegClass()

const TargetRegisterClass * SIRegisterInfo::getRegClass

(

unsigned

RCID

)

const

Definition at line 3063 of file SIRegisterInfo.cpp.

References getBoolRC().

Referenced by adjustAllocatableRegClass(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getOpSize(), llvm::SIInstrInfo::insertVectorSelect(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIInstrInfo::isOperandLegal(), isSGPRClassID(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::verifyInstruction().

getRegClassAlignmentNumBits()

unsigned llvm::SIRegisterInfo::getRegClassAlignmentNumBits ( const TargetRegisterClass *  RC ) const

inline

Definition at line 423 of file SIRegisterInfo.h.

References llvm::RegTupleAlignUnitsMask, and llvm::TargetRegisterClass::TSFlags.

Referenced by isRegClassAligned().

getRegClassForOperandReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForOperandReg	(	const MachineRegisterInfo &	MRI,
		const MachineOperand &	MO
	)		const

Definition at line 2927 of file SIRegisterInfo.cpp.

References llvm::MachineOperand::getReg(), getRegClassForReg(), llvm::MachineOperand::getSubReg(), and MRI.

getRegClassForReg()

const TargetRegisterClass * SIRegisterInfo::getRegClassForReg	(	const MachineRegisterInfo &	MRI,
		Register	Reg
	)		const

Definition at line 2921 of file SIRegisterInfo.cpp.

References MRI.

Referenced by buildSpillLoadStore(), getRegClassForOperandReg(), isAGPR(), isVGPR(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SIInstrInfo::verifyInstruction().

getRegClassForSizeOnBank()

const TargetRegisterClass * SIRegisterInfo::getRegClassForSizeOnBank	(	unsigned	Size,
		const RegisterBank &	Bank
	)		const

Definition at line 3017 of file SIRegisterInfo.cpp.

References assert(), getAGPRClassForBitWidth(), llvm::RegisterBank::getID(), getSGPRClassForBitWidth(), getVGPRClassForBitWidth(), llvm_unreachable, and Size.

Referenced by getRegClassForTypeOnBank().

getRegClassForTypeOnBank()

const TargetRegisterClass * llvm::SIRegisterInfo::getRegClassForTypeOnBank ( LLT  Ty, const RegisterBank &  Bank  ) const

inline

Definition at line 325 of file SIRegisterInfo.h.

References getRegClassForSizeOnBank(), and llvm::LLT::getSizeInBits().

Referenced by getConstrainedRegClassForOperand().

getRegPressureLimit()

unsigned SIRegisterInfo::getRegPressureLimit ( const TargetRegisterClass *  RC, MachineFunction &  MF  ) const

override

Definition at line 2969 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFunction(), llvm::TargetRegisterClass::getID(), llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), and llvm::AMDGPUSubtarget::getOccupancyWithLocalMemSize().

Referenced by getRegPressureSetLimit(), and indirectCopyToAGPR().

getRegPressureSetLimit()

unsigned SIRegisterInfo::getRegPressureSetLimit ( const MachineFunction &  MF, unsigned  Idx  ) const

override

Definition at line 2988 of file SIRegisterInfo.cpp.

References getRegPressureLimit(), Idx, and llvm_unreachable.

getRegSplitParts()

ArrayRef< int16_t > SIRegisterInfo::getRegSplitParts	(	const TargetRegisterClass *	RC,
		unsigned	EltSize
	)		const

Definition at line 2905 of file SIRegisterInfo.cpp.

References assert(), llvm::AMDGPU::getRegBitWidth(), and llvm::TargetRegisterClass::MC.

Referenced by llvm::SIInstrInfo::copyPhysReg(), expandSGPRCopy(), llvm::SIInstrInfo::materializeImmediate(), and llvm::SGPRSpillBuilder::SGPRSpillBuilder().

getRegUnitPressureSets()

const int * SIRegisterInfo::getRegUnitPressureSets ( unsigned  RegUnit ) const

override

Definition at line 3002 of file SIRegisterInfo.cpp.

References llvm::Empty.

getReservedRegs()

BitVector SIRegisterInfo::getReservedRegs ( const MachineFunction &  MF ) const

override

Definition at line 543 of file SIRegisterInfo.cpp.

References assert(), llvm::SIMachineFunctionInfo::getAGPRSpillVGPRs(), getBaseRegister(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::GCNSubtarget::getMaxNumSGPRs(), llvm::GCNSubtarget::getMaxNumVGPRs(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), llvm::SIMachineFunctionInfo::getSGPRSpillVGPRs(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::SIMachineFunctionInfo::getVGPRForAGPRCopy(), llvm::SIMachineFunctionInfo::getVGPRSpillAGPRs(), llvm::SIMachineFunctionInfo::getWWMReservedRegs(), hasBasePointer(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMAIInsts(), llvm::Reserved, and llvm::SIMachineFunctionInfo::usesAGPRs().

getReturnAddressReg()

MCRegister SIRegisterInfo::getReturnAddressReg

(

const MachineFunction &

MF

)

const

Definition at line 3011 of file SIRegisterInfo.cpp.

getScratchInstrOffset()

int64_t SIRegisterInfo::getScratchInstrOffset

(

const MachineInstr *

MI

)

const

Definition at line 754 of file SIRegisterInfo.cpp.

References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isMUBUF(), and MI.

Referenced by getFrameIndexInstrOffset(), isFrameOffsetLegal(), and needsFrameBaseReg().

getSGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getSGPRClassForBitWidth ( unsigned  BitWidth )

static

Definition at line 2755 of file SIRegisterInfo.cpp.

References llvm::BitWidth.

Referenced by getEquivalentSGPRClass(), getRegClassForSizeOnBank(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isIllegalRegisterType(), moreElementsToNextExistingRegClass(), and AMDGPUDAGToDAGISel::Select().

getSubRegAlignmentNumBits()

unsigned SIRegisterInfo::getSubRegAlignmentNumBits	(	const TargetRegisterClass *	RC,
		unsigned	SubReg
	)		const

Definition at line 3199 of file SIRegisterInfo.cpp.

References llvm::HasAGPR, llvm::HasSGPR, llvm::HasVGPR, llvm::RegKindMask, SubReg, and llvm::TargetRegisterClass::TSFlags.

getSubRegFromChannel()

unsigned SIRegisterInfo::getSubRegFromChannel ( unsigned  Channel, unsigned  NumRegs = 1  )

static

Returns

the sub reg enum value for the given Channel (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)

Definition at line 527 of file SIRegisterInfo.cpp.

References assert(), llvm::size(), and SubRegFromChannelTableWidthMap.

Referenced by llvm::SITargetLowering::AddIMGInit(), buildSpillLoadStore(), computeIndirectRegAndOffset(), expandSGPRCopy(), llvm::SIInstrInfo::readlaneVGPRToSGPR(), and AMDGPUDAGToDAGISel::SelectBuildVector().

getVCC()

MCRegister SIRegisterInfo::getVCC

(

)

const

Definition at line 3048 of file SIRegisterInfo.cpp.

Referenced by llvm::SIInstrInfo::getAddNoCarry(), and llvm::SIInstrInfo::moveToVALUImpl().

getVectorSuperClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getVectorSuperClassForBitWidth

(

unsigned

BitWidth

)

const

Definition at line 2744 of file SIRegisterInfo.cpp.

References llvm::BitWidth, getAlignedVectorSuperClassForBitWidth(), getAnyVectorSuperClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().

Referenced by isProperlyAlignedRC().

getVGPR64Class()

const TargetRegisterClass * SIRegisterInfo::getVGPR64Class

(

)

const

Definition at line 3056 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::needsAlignedVGPRs().

Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::legalizeOpWithMove().

getVGPRClassForBitWidth()

const TargetRegisterClass * SIRegisterInfo::getVGPRClassForBitWidth

(

unsigned

BitWidth

)

const

Definition at line 2594 of file SIRegisterInfo.cpp.

References llvm::BitWidth, getAlignedVGPRClassForBitWidth(), getAnyVGPRClassForBitWidth(), and llvm::GCNSubtarget::needsAlignedVGPRs().

Referenced by getEquivalentVGPRClass(), getRegClassForSizeOnBank(), and isProperlyAlignedRC().

getWaveMaskRegClass()

const TargetRegisterClass * llvm::SIRegisterInfo::getWaveMaskRegClass ( ) const

inline

Definition at line 338 of file SIRegisterInfo.h.

Referenced by llvm::AMDGPURegisterBankInfo::executeInWaterfallLoop(), getCrossCopyRegClass(), and llvm::SIInstrInfo::moveToVALUImpl().

hasAGPRs()

static bool llvm::SIRegisterInfo::hasAGPRs ( const TargetRegisterClass *  RC )

inlinestatic

Returns

true if this class contains AGPR registers.

Definition at line 223 of file SIRegisterInfo.h.

References llvm::HasAGPR, and llvm::TargetRegisterClass::TSFlags.

Referenced by hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), isVSSuperClass(), llvm::SIInstrInfo::legalizeOperandsVOP3(), and llvm::SIInstrInfo::readlaneVGPRToSGPR().

hasBasePointer()

bool SIRegisterInfo::hasBasePointer

(

const MachineFunction &

MF

)

const

Definition at line 502 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFrameInfo::getNumFixedObjects(), and shouldRealignStack().

Referenced by buildVGPRSpillLoadStore(), eliminateFrameIndex(), and getReservedRegs().

hasSGPRs()

static bool llvm::SIRegisterInfo::hasSGPRs ( const TargetRegisterClass *  RC )

inlinestatic

Returns

true if this class contains SGPR registers.

Definition at line 228 of file SIRegisterInfo.h.

References llvm::HasSGPR, and llvm::TargetRegisterClass::TSFlags.

Referenced by isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), and isVSSuperClass().

hasVectorRegisters()

static bool llvm::SIRegisterInfo::hasVectorRegisters ( const TargetRegisterClass *  RC )

inlinestatic

Returns

true if this class contains any vector registers.

Definition at line 233 of file SIRegisterInfo.h.

References hasAGPRs(), and hasVGPRs().

Referenced by llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().

hasVGPRs()

static bool llvm::SIRegisterInfo::hasVGPRs ( const TargetRegisterClass *  RC )

inlinestatic

Returns

true if this class contains VGPR registers.

Definition at line 218 of file SIRegisterInfo.h.

References llvm::HasVGPR, and llvm::TargetRegisterClass::TSFlags.

Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), llvm::SIInstrInfo::expandPostRAPseudo(), hasVectorRegisters(), isAGPRClass(), isSGPRClass(), isVectorSuperClass(), isVGPRClass(), isVSSuperClass(), llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::verifyInstruction().

isAGPR()

bool SIRegisterInfo::isAGPR	(	const MachineRegisterInfo &	MRI,
		Register	Reg
	)		const

Definition at line 2940 of file SIRegisterInfo.cpp.

References getRegClassForReg(), isAGPRClass(), and MRI.

Referenced by llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getVALUOp(), llvm::SIInstrInfo::isOperandLegal(), isVectorRegister(), llvm::SIInstrInfo::legalizeOperandsVOP2(), and llvm::SIInstrInfo::verifyInstruction().

isAGPRClass()

static bool llvm::SIRegisterInfo::isAGPRClass ( const TargetRegisterClass *  RC )

inlinestatic

Returns

true if this class contains only AGPR registers

Definition at line 203 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by buildSpillLoadStore(), llvm::SIInstrInfo::copyPhysReg(), getCrossCopyRegClass(), getLargestLegalSuperClass(), llvm::SIInstrInfo::getMovOpcode(), getProperlyAlignedRC(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isAGPR(), isProperlyAlignedRC(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIMachineFunctionInfo::usesAGPRs().

isAsmClobberable()

bool SIRegisterInfo::isAsmClobberable ( const MachineFunction &  MF, MCRegister  PhysReg  ) const

override

Definition at line 704 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getRegInfo(), and llvm::MachineRegisterInfo::isReserved().

isDivergentRegClass()

bool llvm::SIRegisterInfo::isDivergentRegClass ( const TargetRegisterClass *  RC ) const

inlineoverride

Definition at line 293 of file SIRegisterInfo.h.

References isSGPRClass().

isFrameOffsetLegal()

bool SIRegisterInfo::isFrameOffsetLegal ( const MachineInstr *  MI, Register  BaseReg, int64_t  Offset  ) const

override

Definition at line 890 of file SIRegisterInfo.cpp.

References llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.

isProperlyAlignedRC()

bool SIRegisterInfo::isProperlyAlignedRC

(

const TargetRegisterClass &

RC

)

const

Definition at line 3149 of file SIRegisterInfo.cpp.

References getAGPRClassForBitWidth(), getVectorSuperClassForBitWidth(), getVGPRClassForBitWidth(), llvm::TargetRegisterClass::hasSuperClassEq(), isAGPRClass(), isVectorSuperClass(), isVGPRClass(), and llvm::GCNSubtarget::needsAlignedVGPRs().

Referenced by llvm::SIInstrInfo::copyPhysReg(), and llvm::SIInstrInfo::verifyInstruction().

isRegClassAligned()

bool llvm::SIRegisterInfo::isRegClassAligned ( const TargetRegisterClass *  RC, unsigned  AlignNumBits  ) const

inline

Definition at line 428 of file SIRegisterInfo.h.

References assert(), and getRegClassAlignmentNumBits().

isSGPRClass()

static bool llvm::SIRegisterInfo::isSGPRClass ( const TargetRegisterClass *  RC )

inlinestatic

Returns

true if this class contains only SGPR registers

Definition at line 186 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by llvm::SIInstrInfo::canInsertSelect(), llvm::SIInstrInfo::copyPhysReg(), eliminateFrameIndex(), llvm::SIInstrInfo::FoldImmediate(), llvm::SIInstrInfo::getInstructionUniformity(), llvm::SIInstrInfo::getMovOpcode(), llvm::AMDGPURegisterBankInfo::getRegBankFromRegClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isDivergentRegClass(), isSGPRClassID(), isSGPRReg(), llvm::SIInstrInfo::legalizeGenericOperand(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsFLAT(), llvm::SIInstrInfo::legalizeOperandsSMRD(), llvm::SIInstrInfo::legalizeOperandsVOP3(), llvm::SIInstrInfo::legalizeOpWithMove(), llvm::SIInstrInfo::loadRegFromStackSlot(), llvm::SIInstrInfo::materializeImmediate(), llvm::SITargetLowering::requiresUniformRegister(), llvm::SIInstrInfo::storeRegToStackSlot(), and llvm::SIInstrInfo::usesConstantBus().

isSGPRClassID()

bool llvm::SIRegisterInfo::isSGPRClassID ( unsigned  RCID ) const

inline

Returns

true if this class ID contains only SGPR registers

Definition at line 191 of file SIRegisterInfo.h.

References getRegClass(), and isSGPRClass().

isSGPRReg()

bool SIRegisterInfo::isSGPRReg	(	const MachineRegisterInfo &	MRI,
		Register	Reg
	)		const

Definition at line 2790 of file SIRegisterInfo.cpp.

References isSGPRClass(), and MRI.

Referenced by llvm::SIInstrInfo::convertToThreeAddress(), llvm::SIInstrInfo::isOperandLegal(), llvm::SIInstrInfo::isVGPRCopy(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::mayReadEXEC(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), and llvm::SIInstrInfo::verifyInstruction().

isUniformReg()

bool SIRegisterInfo::isUniformReg ( const MachineRegisterInfo &  MRI, const RegisterBankInfo &  RBI, Register  Reg  ) const

override

Definition at line 2895 of file SIRegisterInfo.cpp.

References llvm::RegisterBankInfo::getRegBank(), llvm::RegisterBankInfo::isDivergentRegBank(), and MRI.

isVectorRegister()

bool llvm::SIRegisterInfo::isVectorRegister ( const MachineRegisterInfo &  MRI, Register  Reg  ) const

inline

Definition at line 285 of file SIRegisterInfo.h.

References isAGPR(), isVGPR(), MRI, and Reg.

isVectorSuperClass()

bool llvm::SIRegisterInfo::isVectorSuperClass ( const TargetRegisterClass *  RC ) const

inline

Returns

true only if this class contains both VGPR and AGPR registers

Definition at line 208 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by getProperlyAlignedRC(), isProperlyAlignedRC(), llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().

isVGPR()

bool SIRegisterInfo::isVGPR	(	const MachineRegisterInfo &	MRI,
		Register	Reg
	)		const

Definition at line 2933 of file SIRegisterInfo.cpp.

References getRegClassForReg(), isVGPRClass(), and MRI.

Referenced by llvm::SIInstrInfo::canShrink(), llvm::SIInstrInfo::FoldImmediate(), isVectorRegister(), and llvm::SIInstrInfo::legalizeOperandsVOP2().

isVGPRClass()

static bool llvm::SIRegisterInfo::isVGPRClass ( const TargetRegisterClass *  RC )

inlinestatic

Returns

true if this class contains only VGPR registers

Definition at line 198 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

Referenced by getLargestLegalSuperClass(), getProperlyAlignedRC(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), isProperlyAlignedRC(), and isVGPR().

isVSSuperClass()

bool llvm::SIRegisterInfo::isVSSuperClass ( const TargetRegisterClass *  RC ) const

inline

Returns

true only if this class contains both VGPR and SGPR registers

Definition at line 213 of file SIRegisterInfo.h.

References hasAGPRs(), hasSGPRs(), and hasVGPRs().

materializeFrameBaseRegister()

Register SIRegisterInfo::materializeFrameBaseRegister ( MachineBasicBlock *  MBB, int  FrameIdx, int64_t  Offset  ) const

override

Definition at line 790 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), DL, llvm::GCNSubtarget::enableFlatScratch(), llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::RegState::Kill, MBB, MRI, llvm::Offset, and TII.

needsFrameBaseReg()

bool SIRegisterInfo::needsFrameBaseReg ( MachineInstr *  MI, int64_t  Offset  ) const

override

Definition at line 776 of file SIRegisterInfo.cpp.

References llvm::SIInstrFlags::FlatScratch, llvm::GCNSubtarget::getInstrInfo(), getScratchInstrOffset(), llvm::SIInstrInfo::isFLATScratch(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm::SIInstrInfo::isMUBUF(), MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, and TII.

opCanUseInlineConstant()

bool SIRegisterInfo::opCanUseInlineConstant

(

unsigned

OpType

)

const

Returns

True if operands defined with this operand type can accept an inline constant. i.e. An integer value in the range (-16, 64) or -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.

Definition at line 2836 of file SIRegisterInfo.cpp.

References llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::AMDGPU::OPERAND_REG_INLINE_AC_FIRST, llvm::AMDGPU::OPERAND_REG_INLINE_AC_LAST, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

opCanUseLiteralConstant()

bool SIRegisterInfo::opCanUseLiteralConstant

(

unsigned

OpType

)

const

Returns

True if operands defined with this operand type can accept a literal constant (i.e. any 32-bit immediate).

Definition at line 2869 of file SIRegisterInfo.cpp.

References llvm::AMDGPU::OPERAND_REG_IMM_FIRST, and llvm::AMDGPU::OPERAND_REG_IMM_LAST.

Referenced by llvm::SIInstrInfo::isImmOperandLegal().

requiresFrameIndexReplacementScavenging()

bool SIRegisterInfo::requiresFrameIndexReplacementScavenging ( const MachineFunction &  MF ) const

override

Definition at line 742 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), and llvm::MachineFrameInfo::hasStackObjects().

requiresFrameIndexScavenging()

bool SIRegisterInfo::requiresFrameIndexScavenging ( const MachineFunction &  MF ) const

override

Definition at line 733 of file SIRegisterInfo.cpp.

requiresRegisterScavenging()

bool SIRegisterInfo::requiresRegisterScavenging ( const MachineFunction &  Fn ) const

override

Definition at line 722 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFrameInfo::hasCalls(), llvm::MachineFrameInfo::hasStackObjects(), and Info.

requiresVirtualBaseRegisters()

bool SIRegisterInfo::requiresVirtualBaseRegisters ( const MachineFunction &  Fn ) const

override

Definition at line 748 of file SIRegisterInfo.cpp.

reservedPrivateSegmentBufferReg()

MCRegister SIRegisterInfo::reservedPrivateSegmentBufferReg

(

const MachineFunction &

MF

)

const

Return the end register initially reserved for the scratch buffer in case spilling is needed.

Definition at line 536 of file SIRegisterInfo.cpp.

References llvm::alignDown(), and llvm::GCNSubtarget::getMaxNumSGPRs().

resolveFrameIndex()

void SIRegisterInfo::resolveFrameIndex ( MachineInstr &  MI, Register  BaseReg, int64_t  Offset  ) const

override

Definition at line 841 of file SIRegisterInfo.cpp.

References assert(), llvm::MachineOperand::ChangeToRegister(), llvm::SIInstrFlags::FlatScratch, llvm::MachineOperand::getImm(), llvm::GCNSubtarget::getInstrInfo(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), llvm::SIInstrInfo::isLegalMUBUFImmOffset(), llvm_unreachable, MI, llvm::Offset, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::MachineOperand::setImm(), and TII.

restoreSGPR()

bool SIRegisterInfo::restoreSGPR	(	MachineBasicBlock::iterator	MI,
		int	FI,
		RegScavenger *	RS,
		SlotIndexes *	Indexes = nullptr,
		LiveIntervals *	LIS = nullptr,
		bool	OnlyToVGPR = false
	)		const

Definition at line 1837 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::ArrayRef< T >::empty(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRSpillToVGPRLanes(), llvm::RegState::ImplicitDefine, llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::SIRegisterInfo::SpilledReg::Lane, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::SlotIndexes::replaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::SIRegisterInfo::SpilledReg::VGPR.

Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().

shouldCoalesce()

bool SIRegisterInfo::shouldCoalesce ( MachineInstr *  MI, const TargetRegisterClass *  SrcRC, unsigned  SubReg, const TargetRegisterClass *  DstRC, unsigned  DstSubReg, const TargetRegisterClass *  NewRC, LiveIntervals &  LIS  ) const

override

Definition at line 2948 of file SIRegisterInfo.cpp.

shouldRealignStack()

bool SIRegisterInfo::shouldRealignStack ( const MachineFunction &  MF ) const

override

Definition at line 709 of file SIRegisterInfo.cpp.

References llvm::MachineFunction::getInfo(), Info, and llvm::TargetRegisterInfo::shouldRealignStack().

Referenced by hasBasePointer().

shouldRewriteCopySrc()

bool SIRegisterInfo::shouldRewriteCopySrc ( const TargetRegisterClass *  DefRC, unsigned  DefSubReg, const TargetRegisterClass *  SrcRC, unsigned  SrcSubReg  ) const

override

Definition at line 2845 of file SIRegisterInfo.cpp.

spillEmergencySGPR()

bool SIRegisterInfo::spillEmergencySGPR	(	MachineBasicBlock::iterator	MI,
		MachineBasicBlock &	RestoreMBB,
		Register	SGPR,
		RegScavenger *	RS
	)		const

Definition at line 1914 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::MachineBasicBlock::end(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SGPRSpillBuilder::IsKill, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::restore(), llvm::SGPRSpillBuilder::setMI(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, and llvm::RegState::Undef.

spillSGPR()

bool SIRegisterInfo::spillSGPR	(	MachineBasicBlock::iterator	MI,
		int	FI,
		RegScavenger *	RS,
		SlotIndexes *	Indexes = nullptr,
		LiveIntervals *	LIS = nullptr,
		bool	OnlyToVGPR = false
	)		const

If OnlyToVGPR is true, this will only succeed if this.

Definition at line 1717 of file SIRegisterInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::SIMachineFunctionInfo::addToSpilledSGPRs(), assert(), llvm::BuildMI(), llvm::SGPRSpillBuilder::DL, llvm::ArrayRef< T >::empty(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::GCNSubtarget::getInstrInfo(), llvm::getKillRegState(), llvm::SGPRSpillBuilder::getPerVGPRData(), llvm::SIMachineFunctionInfo::getSGPRSpillToVGPRLanes(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SlotIndexes::insertMachineInstrInMaps(), llvm::SGPRSpillBuilder::IsKill, llvm::SIRegisterInfo::SpilledReg::Lane, llvm::SGPRSpillBuilder::MBB, llvm::SGPRSpillBuilder::MFI, MI, llvm::SGPRSpillBuilder::NumSubRegs, llvm::Offset, llvm::SGPRSpillBuilder::prepare(), llvm::SGPRSpillBuilder::readWriteTmpVGPR(), llvm::LiveIntervals::removeAllRegUnitsForPhysReg(), llvm::SlotIndexes::replaceMachineInstrInMaps(), llvm::SGPRSpillBuilder::restore(), llvm::ArrayRef< T >::size(), llvm::SGPRSpillBuilder::SplitParts, SubReg, llvm::SGPRSpillBuilder::SuperReg, llvm::SGPRSpillBuilder::TII, llvm::SGPRSpillBuilder::TmpVGPR, llvm::RegState::Undef, and llvm::SIRegisterInfo::SpilledReg::VGPR.

Referenced by eliminateFrameIndex(), and eliminateSGPRToVGPRSpillFrameIndex().

spillSGPRToVGPR()

bool llvm::SIRegisterInfo::spillSGPRToVGPR ( ) const

inline

Definition at line 69 of file SIRegisterInfo.h.

Referenced by llvm::SIInstrInfo::loadRegFromStackSlot(), and llvm::SIInstrInfo::storeRegToStackSlot().

supportsBackwardScavenger()

bool llvm::SIRegisterInfo::supportsBackwardScavenger ( ) const

inlineoverride

Definition at line 152 of file SIRegisterInfo.h.

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The documentation for this class was generated from the following files:

• lib/Target/AMDGPU/SIRegisterInfo.h
• lib/Target/AMDGPU/SIRegisterInfo.cpp