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9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
25 class MCRegisterClass;
27 class MCSubtargetInfo;
32 struct kernel_descriptor_t;
80 #define GET_MIMGBaseOpcode_DECL
81 #define GET_MIMGDim_DECL
82 #define GET_MIMGEncoding_DECL
83 #define GET_MIMGLZMapping_DECL
84 #define GET_MIMGMIPMapping_DECL
85 #define GET_MIMGBiASMapping_DECL
86 #define GET_MAIInstInfoTable_DECL
87 #include "AMDGPUGenSearchableTables.inc"
141 XnackSetting = NewXnackSetting;
165 return SramEccSetting;
170 SramEccSetting = NewSramEccSetting;
193 unsigned FlatWorkGroupSize);
206 unsigned FlatWorkGroupSize);
217 unsigned FlatWorkGroupSize);
243 bool FlatScrUsed,
bool XNACKUsed);
384 int getMIMGOpcode(
unsigned BaseOpcode,
unsigned MIMGEncoding,
385 unsigned VDataDwords,
unsigned VAddrDwords);
393 bool IsG16Supported);
466 uint8_t NumComponents,
509 std::pair<int, int> Default,
510 bool OnlyFirstRequired =
false);
527 return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
590 unsigned &Vmcnt,
unsigned &Expcnt,
unsigned &Lgkmcnt);
623 unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt);
655 const MCSubtargetInfo &STI);
657 const MCSubtargetInfo &STI);
659 bool &IsDefault,
const MCSubtargetInfo &STI);
675 namespace MTBUFFormat {
680 void decodeDfmtNfmt(
unsigned Format,
unsigned &Dfmt,
unsigned &Nfmt);
686 int64_t
getNfmt(
const StringRef
Name,
const MCSubtargetInfo &STI);
688 StringRef
getNfmtName(
unsigned Id,
const MCSubtargetInfo &STI);
692 bool isValidNfmt(
unsigned Val,
const MCSubtargetInfo &STI);
701 const MCSubtargetInfo &STI);
712 int64_t
getMsgId(
const StringRef
Name,
const MCSubtargetInfo &STI);
718 StringRef
getMsgName(int64_t MsgId,
const MCSubtargetInfo &STI);
721 StringRef
getMsgOpName(int64_t MsgId, int64_t OpId,
const MCSubtargetInfo &STI);
724 bool isValidMsgId(int64_t MsgId,
const MCSubtargetInfo &STI);
727 bool isValidMsgOp(int64_t MsgId, int64_t OpId,
const MCSubtargetInfo &STI,
732 const MCSubtargetInfo &STI,
bool Strict =
true);
735 bool msgRequiresOp(int64_t MsgId,
const MCSubtargetInfo &STI);
822 int getTotalNumVGPRs(
bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
908 return Literal >= -16 && Literal <= 64;
934 int64_t EncodedOffset);
938 int64_t EncodedOffset,
950 int64_t ByteOffset,
bool IsBuffer);
1062 return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1088 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
@ OPERAND_REG_INLINE_C_FP64
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
#define FP_DENORM_FLUSH_OUT
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
bool getMUBUFIsBufferInv(unsigned Opc)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
This class represents an incoming formal argument to a Function.
AMDGPUTargetID(const MCSubtargetInfo &STI)
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
This is an optimization pass for GlobalISel generic memory operations.
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
bool getMUBUFHasSoffset(unsigned Opc)
static Waitcnt allZeroExceptVsCnt()
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool isGFX11Plus(const MCSubtargetInfo &STI)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
int getMUBUFBaseOpcode(unsigned Opc)
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
Optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
bool isSramEccOnOrAny() const
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
bool hasXNACK(const MCSubtargetInfo &STI)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
LLVM_READNONE bool isLegal64BitDPPControl(unsigned DC)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool getVOP2IsSingle(unsigned Opc)
~AMDGPUTargetID()=default
Reg
All possible values of the reg field in the ModR/M byte.
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
#define FP_DENORM_FLUSH_IN
Triple - Helper class for working with autoconf configuration names.
Optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getAmdhsaCodeObjectVersion()
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
@ OPERAND_REG_IMM_V2INT32
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
bool isGFX10(const MCSubtargetInfo &STI)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
void setTargetIDFromTargetIDStream(StringRef TargetID)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const
bool isGlobalSegment(const GlobalValue *GV)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
static bool oneWayCompatible(bool CallerMode, bool CalleeMode)
Returns true if a flag is compatible if it's enabled in the callee, but disabled in the caller.
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
unsigned const TargetRegisterInfo * TRI
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
MCRegisterClass - Base class of TargetRegisterClass.
LLVM_READNONE bool isKernel(CallingConv::ID CC)
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
This holds information about one operand of a machine instruction, indicating the register class for ...
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
bool isGFX90A(const MCSubtargetInfo &STI)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
bool operator==(const SIModeRegisterDefaults Other) const
bool getMTBUFHasSrsrc(unsigned Opc)
bool isShader(CallingConv::ID cc)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
@ OPERAND_REG_INLINE_C_INT32
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isInlinableIntLiteralV216(int32_t Literal)
@ OPERAND_REG_INLINE_AC_FP16
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
const LLVM_READONLY MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX940(const MCSubtargetInfo &STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isXnackOnOrAny() const
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool getMAIIsGFX940XDL(unsigned Opc)
Describe properties that are true of each instruction in the target description file.
bool hasGFX10A16(const MCSubtargetInfo &STI)
int getMTBUFBaseOpcode(unsigned Opc)
unsigned getInitialPSInputAddr(const Function &F)
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
bool getMTBUFHasSoffset(unsigned Opc)
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool dominates(const Waitcnt &Other) const
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
TargetIDSetting getSramEccSetting() const
const LLVM_READONLY MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
bool getMUBUFHasSrsrc(unsigned Opc)
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
@ OPERAND_REG_INLINE_C_V2INT32
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
This struct is a compact representation of a valid (non-zero power of two) alignment.
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isCI(const MCSubtargetInfo &STI)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isGFX10Plus(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
bool hasPackedD16(const MCSubtargetInfo &STI)
bool isValidHwregWidth(int64_t Width)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
bool shouldEmitConstantsToTextSection(const Triple &TT)
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidHwreg(int64_t Id)
bool isVI(const MCSubtargetInfo &STI)
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
unsigned getExpcntBitMask(const IsaVersion &Version)
unsigned getMultigridSyncArgImplicitArgPosition()
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
bool hasG16(const MCSubtargetInfo &STI)
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
@ OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_FP32
bool isGFX9(const MCSubtargetInfo &STI)
bool allFP64FP16Denormals() const
uint8_t OperandType
Information about the type of the operand.
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Waitcnt combined(const Waitcnt &Other) const
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
bool hasWaitExceptVsCnt() const
bool isSramEccOnOrOff() const
#define FP_DENORM_FLUSH_NONE
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
bool isValidHwregOffset(int64_t Offset)
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
TargetIDSetting getXnackSetting() const
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
const MCOperandInfo * OpInfo
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_V2INT16
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
@ OPERAND_REG_IMM_FP32_DEFERRED
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
@ OPERAND_REG_INLINE_AC_FP32
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
const LLVM_READONLY MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
@ OPERAND_REG_INLINE_AC_INT32
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
StringRef - Represent a constant reference to a string, i.e.
bool getVOP3IsSingle(unsigned Opc)
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
bool isModuleEntryFunctionCC(CallingConv::ID CC)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isCompute(CallingConv::ID cc)
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
const LLVM_READONLY MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
static ManagedStatic< DebugCounter > DC
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
bool hasWaitVsCnt() const
bool isGraphics(CallingConv::ID cc)
AMD Kernel Code Object (amd_kernel_code_t).
bool isXnackSupported() const
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
bool getMTBUFHasVAddr(unsigned Opc)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MIMGBaseOpcode BaseOpcode
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool isGFX9Plus(const MCSubtargetInfo &STI)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
unsigned const MachineRegisterInfo * MRI
bool FP64FP16OutputDenormals
bool isGroupSegment(const GlobalValue *GV)
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
bool isSI(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_AC_FP64
std::string toString() const
bool isArgPassedInSGPR(const Argument *A)
Represents the counter values to wait for in an s_waitcnt instruction.
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
@ OPERAND_REG_IMM_V2INT16
int getMUBUFElements(unsigned Opc)
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
bool isXnackOnOrOff() const
@ OPERAND_REG_INLINE_C_V2FP16
bool getVOP1IsSingle(unsigned Opc)
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
unsigned getTgtId(const StringRef Name)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
@ OPERAND_REG_INLINE_C_V2FP32
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isGFX8Plus(const MCSubtargetInfo &STI)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isGCN3Encoding(const MCSubtargetInfo &STI)
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
uint32_t fpDenormModeSPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
bool hasMIMG_R128(const MCSubtargetInfo &STI)
@ OPERAND_REG_INLINE_C_FP16
void setTargetIDFromFeaturesString(StringRef FS)
bool isReadOnlySegment(const GlobalValue *GV)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
static Waitcnt allZero(bool HasVscnt)
@ OPERAND_REG_INLINE_AC_V2INT16
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
bool isSramEccSupported() const
bool isKernelCC(const Function *Func)
const LLVM_READONLY MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
unsigned getHostcallImplicitArgPosition()
Generic base class for all target subtargets.
bool allFP32Denormals() const
bool getHasColorExport(const Function &F)
bool getHasDepthExport(const Function &F)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
int getMTBUFElements(unsigned Opc)
Optional< std::vector< StOtherPiece > > Other
@ OPERAND_REG_INLINE_AC_V2FP16