LLVM 20.0.0git
AMDGPUBaseInfo.h
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1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
12#include "AMDGPUSubtarget.h"
13#include "SIDefines.h"
14#include "llvm/IR/CallingConv.h"
15#include "llvm/IR/InstrTypes.h"
16#include "llvm/IR/Module.h"
18#include <array>
19#include <functional>
20#include <utility>
21
23
24namespace llvm {
25
26struct Align;
27class Argument;
28class Function;
29class GlobalValue;
30class MCInstrInfo;
31class MCRegisterClass;
32class MCRegisterInfo;
33class MCSubtargetInfo;
34class StringRef;
35class Triple;
36class raw_ostream;
37
38namespace AMDGPU {
39
40struct AMDGPUMCKernelCodeT;
41struct IsaVersion;
42
43/// Generic target versions emitted by this version of LLVM.
44///
45/// These numbers are incremented every time a codegen breaking change occurs
46/// within a generic family.
47namespace GenericVersion {
48static constexpr unsigned GFX9 = 1;
49static constexpr unsigned GFX10_1 = 1;
50static constexpr unsigned GFX10_3 = 1;
51static constexpr unsigned GFX11 = 1;
52static constexpr unsigned GFX12 = 1;
53} // namespace GenericVersion
54
55enum { AMDHSA_COV4 = 4, AMDHSA_COV5 = 5, AMDHSA_COV6 = 6 };
56
57/// \returns True if \p STI is AMDHSA.
58bool isHsaAbi(const MCSubtargetInfo &STI);
59
60/// \returns Code object version from the IR module flag.
61unsigned getAMDHSACodeObjectVersion(const Module &M);
62
63/// \returns Code object version from ELF's e_ident[EI_ABIVERSION].
64unsigned getAMDHSACodeObjectVersion(unsigned ABIVersion);
65
66/// \returns The default HSA code object version. This should only be used when
67/// we lack a more accurate CodeObjectVersion value (e.g. from the IR module
68/// flag or a .amdhsa_code_object_version directive)
70
71/// \returns ABIVersion suitable for use in ELF's e_ident[EI_ABIVERSION]. \param
72/// CodeObjectVersion is a value returned by getAMDHSACodeObjectVersion().
73uint8_t getELFABIVersion(const Triple &OS, unsigned CodeObjectVersion);
74
75/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
76unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
77
78/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
79unsigned getHostcallImplicitArgPosition(unsigned COV);
80
81unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
82unsigned getCompletionActionImplicitArgPosition(unsigned COV);
83
85 unsigned Format;
86 unsigned BitsPerComp;
87 unsigned NumComponents;
88 unsigned NumFormat;
89 unsigned DataFormat;
90};
91
96};
97
98#define GET_MIMGBaseOpcode_DECL
99#define GET_MIMGDim_DECL
100#define GET_MIMGEncoding_DECL
101#define GET_MIMGLZMapping_DECL
102#define GET_MIMGMIPMapping_DECL
103#define GET_MIMGBiASMapping_DECL
104#define GET_MAIInstInfoTable_DECL
105#include "AMDGPUGenSearchableTables.inc"
106
107namespace IsaInfo {
108
109enum {
110 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
111 // doesn't spill SGPRs as much as when 80 is set.
113 TRAP_NUM_SGPRS = 16
115
116enum class TargetIDSetting {
118 Any,
119 Off,
120 On
121};
122
124private:
125 const MCSubtargetInfo &STI;
126 TargetIDSetting XnackSetting;
127 TargetIDSetting SramEccSetting;
128
129public:
130 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
131 ~AMDGPUTargetID() = default;
132
133 /// \return True if the current xnack setting is not "Unsupported".
134 bool isXnackSupported() const {
135 return XnackSetting != TargetIDSetting::Unsupported;
136 }
137
138 /// \returns True if the current xnack setting is "On" or "Any".
139 bool isXnackOnOrAny() const {
140 return XnackSetting == TargetIDSetting::On ||
141 XnackSetting == TargetIDSetting::Any;
142 }
143
144 /// \returns True if current xnack setting is "On" or "Off",
145 /// false otherwise.
146 bool isXnackOnOrOff() const {
149 }
150
151 /// \returns The current xnack TargetIDSetting, possible options are
152 /// "Unsupported", "Any", "Off", and "On".
154 return XnackSetting;
155 }
156
157 /// Sets xnack setting to \p NewXnackSetting.
158 void setXnackSetting(TargetIDSetting NewXnackSetting) {
159 XnackSetting = NewXnackSetting;
160 }
161
162 /// \return True if the current sramecc setting is not "Unsupported".
163 bool isSramEccSupported() const {
164 return SramEccSetting != TargetIDSetting::Unsupported;
165 }
166
167 /// \returns True if the current sramecc setting is "On" or "Any".
168 bool isSramEccOnOrAny() const {
169 return SramEccSetting == TargetIDSetting::On ||
170 SramEccSetting == TargetIDSetting::Any;
171 }
172
173 /// \returns True if current sramecc setting is "On" or "Off",
174 /// false otherwise.
175 bool isSramEccOnOrOff() const {
178 }
179
180 /// \returns The current sramecc TargetIDSetting, possible options are
181 /// "Unsupported", "Any", "Off", and "On".
183 return SramEccSetting;
184 }
185
186 /// Sets sramecc setting to \p NewSramEccSetting.
187 void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
188 SramEccSetting = NewSramEccSetting;
189 }
190
193
194 /// \returns String representation of an object.
195 std::string toString() const;
196};
197
198/// \returns Wavefront size for given subtarget \p STI.
199unsigned getWavefrontSize(const MCSubtargetInfo *STI);
200
201/// \returns Local memory size in bytes for given subtarget \p STI.
202unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
203
204/// \returns Maximum addressable local memory size in bytes for given subtarget
205/// \p STI.
207
208/// \returns Number of execution units per compute unit for given subtarget \p
209/// STI.
210unsigned getEUsPerCU(const MCSubtargetInfo *STI);
211
212/// \returns Maximum number of work groups per compute unit for given subtarget
213/// \p STI and limited by given \p FlatWorkGroupSize.
214unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
215 unsigned FlatWorkGroupSize);
216
217/// \returns Minimum number of waves per execution unit for given subtarget \p
218/// STI.
219unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
220
221/// \returns Maximum number of waves per execution unit for given subtarget \p
222/// STI without any kind of limitation.
223unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
224
225/// \returns Number of waves per execution unit required to support the given \p
226/// FlatWorkGroupSize.
228 unsigned FlatWorkGroupSize);
229
230/// \returns Minimum flat work group size for given subtarget \p STI.
231unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
232
233/// \returns Maximum flat work group size for given subtarget \p STI.
234unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
235
236/// \returns Number of waves per work group for given subtarget \p STI and
237/// \p FlatWorkGroupSize.
238unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
239 unsigned FlatWorkGroupSize);
240
241/// \returns SGPR allocation granularity for given subtarget \p STI.
242unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
243
244/// \returns SGPR encoding granularity for given subtarget \p STI.
245unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
246
247/// \returns Total number of SGPRs for given subtarget \p STI.
248unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
249
250/// \returns Addressable number of SGPRs for given subtarget \p STI.
251unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
252
253/// \returns Minimum number of SGPRs that meets the given number of waves per
254/// execution unit requirement for given subtarget \p STI.
255unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
256
257/// \returns Maximum number of SGPRs that meets the given number of waves per
258/// execution unit requirement for given subtarget \p STI.
259unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
260 bool Addressable);
261
262/// \returns Number of extra SGPRs implicitly required by given subtarget \p
263/// STI when the given special registers are used.
264unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
265 bool FlatScrUsed, bool XNACKUsed);
266
267/// \returns Number of extra SGPRs implicitly required by given subtarget \p
268/// STI when the given special registers are used. XNACK is inferred from
269/// \p STI.
270unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
271 bool FlatScrUsed);
272
273/// \returns Number of SGPR blocks needed for given subtarget \p STI when
274/// \p NumSGPRs are used. \p NumSGPRs should already include any special
275/// register counts.
276unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
277
278/// \returns VGPR allocation granularity for given subtarget \p STI.
279///
280/// For subtargets which support it, \p EnableWavefrontSize32 should match
281/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
282unsigned
284 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
285
286/// \returns VGPR encoding granularity for given subtarget \p STI.
287///
288/// For subtargets which support it, \p EnableWavefrontSize32 should match
289/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
291 const MCSubtargetInfo *STI,
292 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
293
294/// \returns Total number of VGPRs for given subtarget \p STI.
295unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
296
297/// \returns Addressable number of architectural VGPRs for a given subtarget \p
298/// STI.
300
301/// \returns Addressable number of VGPRs for given subtarget \p STI.
302unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
303
304/// \returns Minimum number of VGPRs that meets given number of waves per
305/// execution unit requirement for given subtarget \p STI.
306unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
307
308/// \returns Maximum number of VGPRs that meets given number of waves per
309/// execution unit requirement for given subtarget \p STI.
310unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
311
312/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
313/// subtarget \p STI.
315 unsigned NumVGPRs);
316
317/// \returns Number of waves reachable for a given \p NumVGPRs usage, \p Granule
318/// size, \p MaxWaves possible, and \p TotalNumVGPRs available.
319unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
320 unsigned MaxWaves,
321 unsigned TotalNumVGPRs);
322
323/// \returns Occupancy for a given \p SGPRs usage, \p MaxWaves possible, and \p
324/// Gen.
325unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
327
328/// \returns Number of VGPR blocks needed for given subtarget \p STI when
329/// \p NumVGPRs are used. We actually return the number of blocks -1, since
330/// that's what we encode.
331///
332/// For subtargets which support it, \p EnableWavefrontSize32 should match the
333/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
335 const MCSubtargetInfo *STI, unsigned NumVGPRs,
336 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
337
338/// \returns Number of VGPR blocks that need to be allocated for the given
339/// subtarget \p STI when \p NumVGPRs are used.
341 const MCSubtargetInfo *STI, unsigned NumVGPRs,
342 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
343
344} // end namespace IsaInfo
345
346// Represents a field in an encoded value.
347template <unsigned HighBit, unsigned LowBit, unsigned D = 0>
349 static_assert(HighBit >= LowBit, "Invalid bit range!");
350 static constexpr unsigned Offset = LowBit;
351 static constexpr unsigned Width = HighBit - LowBit + 1;
352
354 static constexpr ValueType Default = D;
355
358
359 constexpr uint64_t encode() const { return Value; }
360 static ValueType decode(uint64_t Encoded) { return Encoded; }
361};
362
363// Represents a single bit in an encoded value.
364template <unsigned Bit, unsigned D = 0>
366
367// A helper for encoding and decoding multiple fields.
368template <typename... Fields> struct EncodingFields {
369 static constexpr uint64_t encode(Fields... Values) {
370 return ((Values.encode() << Values.Offset) | ...);
371 }
372
373 static std::tuple<typename Fields::ValueType...> decode(uint64_t Encoded) {
374 return {Fields::decode((Encoded >> Fields::Offset) &
375 maxUIntN(Fields::Width))...};
376 }
377};
378
380int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
381
383inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
384 return getNamedOperandIdx(Opcode, NamedIdx) != -1;
385}
386
389
391 MIMGBaseOpcode BaseOpcode;
392 bool Store;
393 bool Atomic;
397
400 bool G16;
403 bool HasD16;
404 bool MSAA;
405 bool BVH;
406 bool A16;
408};
409
411const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
412
414const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
415
417 MIMGDim Dim;
418 uint8_t NumCoords;
420 bool MSAA;
421 bool DA;
422 uint8_t Encoding;
423 const char *AsmSuffix;
424};
425
427const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
428
431
434
436 MIMGBaseOpcode L;
437 MIMGBaseOpcode LZ;
438};
439
441 MIMGBaseOpcode MIP;
442 MIMGBaseOpcode NONMIP;
443};
444
446 MIMGBaseOpcode Bias;
447 MIMGBaseOpcode NoBias;
448};
449
451 MIMGBaseOpcode Offset;
452 MIMGBaseOpcode NoOffset;
453};
454
456 MIMGBaseOpcode G;
457 MIMGBaseOpcode G16;
458};
459
462
464 unsigned Opcode2Addr;
465 unsigned Opcode3Addr;
466};
467
470
473
476
479
481int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
482 unsigned VDataDwords, unsigned VAddrDwords);
483
485int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
486
488unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
489 const MIMGDimInfo *Dim, bool IsA16,
490 bool IsG16Supported);
491
492struct MIMGInfo {
496 uint8_t VDataDwords;
497 uint8_t VAddrDwords;
499};
500
502const MIMGInfo *getMIMGInfo(unsigned Opc);
503
505int getMTBUFBaseOpcode(unsigned Opc);
506
508int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
509
511int getMTBUFElements(unsigned Opc);
512
514bool getMTBUFHasVAddr(unsigned Opc);
515
517bool getMTBUFHasSrsrc(unsigned Opc);
518
520bool getMTBUFHasSoffset(unsigned Opc);
521
523int getMUBUFBaseOpcode(unsigned Opc);
524
526int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
527
529int getMUBUFElements(unsigned Opc);
530
532bool getMUBUFHasVAddr(unsigned Opc);
533
535bool getMUBUFHasSrsrc(unsigned Opc);
536
538bool getMUBUFHasSoffset(unsigned Opc);
539
541bool getMUBUFIsBufferInv(unsigned Opc);
542
544bool getMUBUFTfe(unsigned Opc);
545
547bool getSMEMIsBuffer(unsigned Opc);
548
550bool getVOP1IsSingle(unsigned Opc);
551
553bool getVOP2IsSingle(unsigned Opc);
554
556bool getVOP3IsSingle(unsigned Opc);
557
559bool isVOPC64DPP(unsigned Opc);
560
562bool isVOPCAsmOnly(unsigned Opc);
563
564/// Returns true if MAI operation is a double precision GEMM.
566bool getMAIIsDGEMM(unsigned Opc);
567
569bool getMAIIsGFX940XDL(unsigned Opc);
570
571struct CanBeVOPD {
572 bool X;
573 bool Y;
574};
575
576/// \returns SIEncodingFamily used for VOPD encoding on a \p ST.
578unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST);
579
581CanBeVOPD getCanBeVOPD(unsigned Opc);
582
584const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
585 uint8_t NumComponents,
586 uint8_t NumFormat,
587 const MCSubtargetInfo &STI);
590 const MCSubtargetInfo &STI);
591
593int getMCOpcode(uint16_t Opcode, unsigned Gen);
594
596unsigned getVOPDOpcode(unsigned Opc);
597
599int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily);
600
602bool isVOPD(unsigned Opc);
603
605bool isMAC(unsigned Opc);
606
608bool isPermlane16(unsigned Opc);
609
611bool isGenericAtomic(unsigned Opc);
612
614bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc);
615
616namespace VOPD {
617
618enum Component : unsigned {
619 DST = 0,
623
628
629// LSB mask for VGPR banks per VOPD component operand.
630// 4 banks result in a mask 3, setting 2 lower bits.
631constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
632
633enum ComponentIndex : unsigned { X = 0, Y = 1 };
635constexpr unsigned COMPONENTS_NUM = 2;
636
637// Properties of VOPD components.
639private:
640 unsigned SrcOperandsNum = 0;
641 unsigned MandatoryLiteralIdx = ~0u;
642 bool HasSrc2Acc = false;
643
644public:
645 ComponentProps() = default;
646 ComponentProps(const MCInstrDesc &OpDesc);
647
648 // Return the total number of src operands this component has.
649 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
650
651 // Return the number of src operands of this component visible to the parser.
653 return SrcOperandsNum - HasSrc2Acc;
654 }
655
656 // Return true iif this component has a mandatory literal.
657 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }
658
659 // If this component has a mandatory literal, return component operand
660 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
663 return MandatoryLiteralIdx;
664 }
665
666 // Return true iif this component has operand
667 // with component index CompSrcIdx and this operand may be a register.
668 bool hasRegSrcOperand(unsigned CompSrcIdx) const {
669 assert(CompSrcIdx < Component::MAX_SRC_NUM);
670 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
671 }
672
673 // Return true iif this component has tied src2.
674 bool hasSrc2Acc() const { return HasSrc2Acc; }
675
676private:
677 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
678 assert(CompSrcIdx < Component::MAX_SRC_NUM);
679 return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
680 }
681};
682
683enum ComponentKind : unsigned {
684 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
685 COMPONENT_X, // A VOPD instruction, X component.
686 COMPONENT_Y, // A VOPD instruction, Y component.
689
690// Interface functions of this class map VOPD component operand indices
691// to indices of operands in MachineInstr/MCInst or parsed operands array.
692//
693// Note that this class operates with 3 kinds of indices:
694// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
695// - MC operand indices (they refer operands in a MachineInstr/MCInst);
696// - parsed operand indices (they refer operands in parsed operands array).
697//
698// For SINGLE components mapping between these indices is trivial.
699// But things get more complicated for COMPONENT_X and
700// COMPONENT_Y because these components share the same
701// MachineInstr/MCInst and the same parsed operands array.
702// Below is an example of component operand to parsed operand
703// mapping for the following instruction:
704//
705// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
706//
707// PARSED COMPONENT PARSED
708// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
709// -------------------------------------------------------------------
710// "v_dual_add_f32" 0
711// v_dual_add_f32 v255 0 (DST) --> 1
712// v4 1 (SRC0) --> 2
713// v5 2 (SRC1) --> 3
714// "::" 4
715// "v_dual_mov_b32" 5
716// v_dual_mov_b32 v6 0 (DST) --> 6
717// v1 1 (SRC0) --> 7
718// -------------------------------------------------------------------
719//
721private:
722 // Regular MachineInstr/MCInst operands are ordered as follows:
723 // dst, src0 [, other src operands]
724 // VOPD MachineInstr/MCInst operands are ordered as follows:
725 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
726 // Each ComponentKind has operand indices defined below.
727 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
728 static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
729
730 // Parsed operands of regular instructions are ordered as follows:
731 // Mnemo dst src0 [vsrc1 ...]
732 // Parsed VOPD operands are ordered as follows:
733 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
734 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
735 // Each ComponentKind has operand indices defined below.
736 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
737 4 /* + OpX.ParsedSrcNum */};
738 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
739 2, 2, 5 /* + OpX.ParsedSrcNum */};
740
741private:
742 const ComponentKind Kind;
743 const ComponentProps PrevComp;
744
745public:
746 // Create layout for COMPONENT_X or SINGLE component.
747 ComponentLayout(ComponentKind Kind) : Kind(Kind) {
749 }
750
751 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
753 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
754
755public:
756 // Return the index of dst operand in MCInst operands.
757 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
758
759 // Return the index of the specified src operand in MCInst operands.
760 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
761 assert(CompSrcIdx < Component::MAX_SRC_NUM);
762 return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
763 }
764
765 // Return the index of dst operand in the parsed operands array.
767 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
768 }
769
770 // Return the index of the specified src operand in the parsed operands array.
771 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
772 assert(CompSrcIdx < Component::MAX_SRC_NUM);
773 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
774 }
775
776private:
777 unsigned getPrevCompSrcNum() const {
778 return PrevComp.getCompSrcOperandsNum();
779 }
780 unsigned getPrevCompParsedSrcNum() const {
781 return PrevComp.getCompParsedSrcOperandsNum();
782 }
783};
784
785// Layout and properties of VOPD components.
787public:
788 // Create ComponentInfo for COMPONENT_X or SINGLE component.
791 : ComponentLayout(Kind), ComponentProps(OpDesc) {}
792
793 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
794 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
795 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
796
797 // Map component operand index to parsed operand index.
798 // Return 0 if the specified operand does not exist.
799 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
800};
801
802// Properties of VOPD instructions.
803class InstInfo {
804private:
805 const ComponentInfo CompInfo[COMPONENTS_NUM];
806
807public:
808 using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
809
810 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
811 : CompInfo{OpX, OpY} {}
812
813 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
814 : CompInfo{OprInfoX, OprInfoY} {}
815
816 const ComponentInfo &operator[](size_t ComponentIdx) const {
817 assert(ComponentIdx < COMPONENTS_NUM);
818 return CompInfo[ComponentIdx];
819 }
820
821 // Check VOPD operands constraints.
822 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
823 // for the specified component and MC operand. The callback must return 0
824 // if the operand is not a register or not a VGPR.
825 // If \p SkipSrc is set to true then constraints for source operands are not
826 // checked.
827 bool hasInvalidOperand(std::function<unsigned(unsigned, unsigned)> GetRegIdx,
828 bool SkipSrc = false) const {
829 return getInvalidCompOperandIndex(GetRegIdx, SkipSrc).has_value();
830 }
831
832 // Check VOPD operands constraints.
833 // Return the index of an invalid component operand, if any.
834 // If \p SkipSrc is set to true then constraints for source operands are not
835 // checked.
836 std::optional<unsigned> getInvalidCompOperandIndex(
837 std::function<unsigned(unsigned, unsigned)> GetRegIdx,
838 bool SkipSrc = false) const;
839
840private:
842 getRegIndices(unsigned ComponentIdx,
843 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
844};
845
846} // namespace VOPD
847
849std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
850
852// Get properties of 2 single VOP1/VOP2 instructions
853// used as components to create a VOPD instruction.
854VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
855
857// Get properties of VOPD X and Y components.
858VOPD::InstInfo
859getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
860
862bool isTrue16Inst(unsigned Opc);
863
865bool isInvalidSingleUseConsumerInst(unsigned Opc);
866
868bool isInvalidSingleUseProducerInst(unsigned Opc);
869
871unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
872
874unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
875
876void initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT &Header,
877 const MCSubtargetInfo *STI);
878
879bool isGroupSegment(const GlobalValue *GV);
880bool isGlobalSegment(const GlobalValue *GV);
881bool isReadOnlySegment(const GlobalValue *GV);
882
883/// \returns True if constants should be emitted to .text section for given
884/// target triple \p TT, false otherwise.
886
887/// \returns Integer value requested using \p F's \p Name attribute.
888///
889/// \returns \p Default if attribute is not present.
890///
891/// \returns \p Default and emits error if requested value cannot be converted
892/// to integer.
894
895/// \returns A pair of integer values requested using \p F's \p Name attribute
896/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
897/// is false).
898///
899/// \returns \p Default if attribute is not present.
900///
901/// \returns \p Default and emits error if one of the requested values cannot be
902/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
903/// not present.
904std::pair<unsigned, unsigned>
906 std::pair<unsigned, unsigned> Default,
907 bool OnlyFirstRequired = false);
908
909/// \returns Generate a vector of integer values requested using \p F's \p Name
910/// attribute.
911///
912/// \returns true if exactly Size (>2) number of integers are found in the
913/// attribute.
914///
915/// \returns false if any error occurs.
917 unsigned Size);
918
919/// Represents the counter values to wait for in an s_waitcnt instruction.
920///
921/// Large values (including the maximum possible integer) can be used to
922/// represent "don't care" waits.
923struct Waitcnt {
924 unsigned LoadCnt = ~0u; // Corresponds to Vmcnt prior to gfx12.
925 unsigned ExpCnt = ~0u;
926 unsigned DsCnt = ~0u; // Corresponds to LGKMcnt prior to gfx12.
927 unsigned StoreCnt = ~0u; // Corresponds to VScnt on gfx10/gfx11.
928 unsigned SampleCnt = ~0u; // gfx12+ only.
929 unsigned BvhCnt = ~0u; // gfx12+ only.
930 unsigned KmCnt = ~0u; // gfx12+ only.
931
932 Waitcnt() = default;
933 // Pre-gfx12 constructor.
934 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
935 : LoadCnt(VmCnt), ExpCnt(ExpCnt), DsCnt(LgkmCnt), StoreCnt(VsCnt),
936 SampleCnt(~0u), BvhCnt(~0u), KmCnt(~0u) {}
937
938 // gfx12+ constructor.
939 Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt,
940 unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt)
943
944 bool hasWait() const { return StoreCnt != ~0u || hasWaitExceptStoreCnt(); }
945
947 return LoadCnt != ~0u || ExpCnt != ~0u || DsCnt != ~0u ||
948 SampleCnt != ~0u || BvhCnt != ~0u || KmCnt != ~0u;
949 }
950
951 bool hasWaitStoreCnt() const { return StoreCnt != ~0u; }
952
954 // Does the right thing provided self and Other are either both pre-gfx12
955 // or both gfx12+.
956 return Waitcnt(
957 std::min(LoadCnt, Other.LoadCnt), std::min(ExpCnt, Other.ExpCnt),
958 std::min(DsCnt, Other.DsCnt), std::min(StoreCnt, Other.StoreCnt),
959 std::min(SampleCnt, Other.SampleCnt), std::min(BvhCnt, Other.BvhCnt),
960 std::min(KmCnt, Other.KmCnt));
961 }
962};
963
964// The following methods are only meaningful on targets that support
965// S_WAITCNT.
966
967/// \returns Vmcnt bit mask for given isa \p Version.
968unsigned getVmcntBitMask(const IsaVersion &Version);
969
970/// \returns Expcnt bit mask for given isa \p Version.
971unsigned getExpcntBitMask(const IsaVersion &Version);
972
973/// \returns Lgkmcnt bit mask for given isa \p Version.
974unsigned getLgkmcntBitMask(const IsaVersion &Version);
975
976/// \returns Waitcnt bit mask for given isa \p Version.
977unsigned getWaitcntBitMask(const IsaVersion &Version);
978
979/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
980unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
981
982/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
983unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
984
985/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
986unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
987
988/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
989/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
990/// \p Lgkmcnt respectively. Should not be used on gfx12+, the instruction
991/// which needs it is deprecated
992///
993/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
994/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
995/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
996/// \p Vmcnt = \p Waitcnt[15:10] (gfx11)
997/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
998/// \p Expcnt = \p Waitcnt[2:0] (gfx11)
999/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
1000/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
1001/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11)
1002///
1003void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
1004 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
1005
1006Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
1007
1008/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
1009unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
1010 unsigned Vmcnt);
1011
1012/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
1013unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
1014 unsigned Expcnt);
1015
1016/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
1017unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
1018 unsigned Lgkmcnt);
1019
1020/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
1021/// \p Version. Should not be used on gfx12+, the instruction which needs
1022/// it is deprecated
1023///
1024/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
1025/// Waitcnt[2:0] = \p Expcnt (gfx11+)
1026/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
1027/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
1028/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
1029/// Waitcnt[9:4] = \p Lgkmcnt (gfx11)
1030/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
1031/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
1032/// Waitcnt[15:10] = \p Vmcnt (gfx11)
1033/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
1034///
1035/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
1036/// isa \p Version.
1037///
1038unsigned encodeWaitcnt(const IsaVersion &Version,
1039 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
1040
1041unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
1042
1043// The following methods are only meaningful on targets that support
1044// S_WAIT_*CNT, introduced with gfx12.
1045
1046/// \returns Loadcnt bit mask for given isa \p Version.
1047/// Returns 0 for versions that do not support LOADcnt
1048unsigned getLoadcntBitMask(const IsaVersion &Version);
1049
1050/// \returns Samplecnt bit mask for given isa \p Version.
1051/// Returns 0 for versions that do not support SAMPLEcnt
1052unsigned getSamplecntBitMask(const IsaVersion &Version);
1053
1054/// \returns Bvhcnt bit mask for given isa \p Version.
1055/// Returns 0 for versions that do not support BVHcnt
1056unsigned getBvhcntBitMask(const IsaVersion &Version);
1057
1058/// \returns Dscnt bit mask for given isa \p Version.
1059/// Returns 0 for versions that do not support DScnt
1060unsigned getDscntBitMask(const IsaVersion &Version);
1061
1062/// \returns Dscnt bit mask for given isa \p Version.
1063/// Returns 0 for versions that do not support KMcnt
1064unsigned getKmcntBitMask(const IsaVersion &Version);
1065
1066/// \return STOREcnt or VScnt bit mask for given isa \p Version.
1067/// returns 0 for versions that do not support STOREcnt or VScnt.
1068/// STOREcnt and VScnt are the same counter, the name used
1069/// depends on the ISA version.
1070unsigned getStorecntBitMask(const IsaVersion &Version);
1071
1072// The following are only meaningful on targets that support
1073// S_WAIT_LOADCNT_DSCNT and S_WAIT_STORECNT_DSCNT.
1074
1075/// \returns Decoded Waitcnt structure from given \p LoadcntDscnt for given
1076/// isa \p Version.
1077Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt);
1078
1079/// \returns Decoded Waitcnt structure from given \p StorecntDscnt for given
1080/// isa \p Version.
1081Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt);
1082
1083/// \returns \p Loadcnt and \p Dscnt components of \p Decoded encoded as an
1084/// immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa
1085/// \p Version.
1086unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);
1087
1088/// \returns \p Storecnt and \p Dscnt components of \p Decoded encoded as an
1089/// immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa
1090/// \p Version.
1091unsigned encodeStorecntDscnt(const IsaVersion &Version, const Waitcnt &Decoded);
1092
1093namespace Hwreg {
1094
1097
1098struct HwregSize : EncodingField<15, 11, 32> {
1100 constexpr uint64_t encode() const { return Value - 1; }
1101 static ValueType decode(uint64_t Encoded) { return Encoded + 1; }
1102};
1103
1105
1106} // namespace Hwreg
1107
1108namespace DepCtr {
1109
1111int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
1112 const MCSubtargetInfo &STI);
1113bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
1114 const MCSubtargetInfo &STI);
1115bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
1116 bool &IsDefault, const MCSubtargetInfo &STI);
1117
1118/// \returns Decoded VaVdst from given immediate \p Encoded.
1119unsigned decodeFieldVaVdst(unsigned Encoded);
1120
1121/// \returns Decoded VmVsrc from given immediate \p Encoded.
1122unsigned decodeFieldVmVsrc(unsigned Encoded);
1123
1124/// \returns Decoded SaSdst from given immediate \p Encoded.
1125unsigned decodeFieldSaSdst(unsigned Encoded);
1126
1127/// \returns \p VmVsrc as an encoded Depctr immediate.
1128unsigned encodeFieldVmVsrc(unsigned VmVsrc);
1129
1130/// \returns \p Encoded combined with encoded \p VmVsrc.
1131unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
1132
1133/// \returns \p VaVdst as an encoded Depctr immediate.
1134unsigned encodeFieldVaVdst(unsigned VaVdst);
1135
1136/// \returns \p Encoded combined with encoded \p VaVdst.
1137unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
1138
1139/// \returns \p SaSdst as an encoded Depctr immediate.
1140unsigned encodeFieldSaSdst(unsigned SaSdst);
1141
1142/// \returns \p Encoded combined with encoded \p SaSdst.
1143unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
1144
1145} // namespace DepCtr
1146
1147namespace Exp {
1148
1149bool getTgtName(unsigned Id, StringRef &Name, int &Index);
1150
1152unsigned getTgtId(const StringRef Name);
1153
1155bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
1156
1157} // namespace Exp
1158
1159namespace MTBUFFormat {
1160
1162int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1163
1164void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
1165
1166int64_t getDfmt(const StringRef Name);
1167
1168StringRef getDfmtName(unsigned Id);
1169
1170int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
1171
1172StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
1173
1174bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
1175
1176bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
1177
1178int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
1179
1180StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
1181
1182bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
1183
1184int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1185 const MCSubtargetInfo &STI);
1186
1187bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
1188
1189unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
1190
1191} // namespace MTBUFFormat
1192
1193namespace SendMsg {
1194
1196bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1197
1199bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1200 bool Strict = true);
1201
1203bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1204 const MCSubtargetInfo &STI, bool Strict = true);
1205
1207bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1208
1210bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1211
1212void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1213 uint16_t &StreamId, const MCSubtargetInfo &STI);
1214
1217 uint64_t OpId,
1219
1220} // namespace SendMsg
1221
1222
1223unsigned getInitialPSInputAddr(const Function &F);
1224
1225bool getHasColorExport(const Function &F);
1226
1227bool getHasDepthExport(const Function &F);
1228
1231
1234
1237
1240
1241// These functions are considered entrypoints into the current module, i.e. they
1242// are allowed to be called from outside the current module. This is different
1243// from isEntryFunctionCC, which is only true for functions that are entered by
1244// the hardware. Module entry points include all entry functions but also
1245// include functions that can be called from other functions inside or outside
1246// the current module. Module entry functions are allowed to allocate LDS.
1249
1252
1253bool isKernelCC(const Function *Func);
1254
1255// FIXME: Remove this when calling conventions cleaned up
1258 switch (CC) {
1261 return true;
1262 default:
1263 return false;
1264 }
1265}
1266
1267bool hasXNACK(const MCSubtargetInfo &STI);
1268bool hasSRAMECC(const MCSubtargetInfo &STI);
1269bool hasMIMG_R128(const MCSubtargetInfo &STI);
1270bool hasA16(const MCSubtargetInfo &STI);
1271bool hasG16(const MCSubtargetInfo &STI);
1272bool hasPackedD16(const MCSubtargetInfo &STI);
1273bool hasGDS(const MCSubtargetInfo &STI);
1274unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler = false);
1275unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI);
1276
1277bool isSI(const MCSubtargetInfo &STI);
1278bool isCI(const MCSubtargetInfo &STI);
1279bool isVI(const MCSubtargetInfo &STI);
1280bool isGFX9(const MCSubtargetInfo &STI);
1281bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1282bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI);
1283bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1284bool isGFX8Plus(const MCSubtargetInfo &STI);
1285bool isGFX9Plus(const MCSubtargetInfo &STI);
1286bool isNotGFX9Plus(const MCSubtargetInfo &STI);
1287bool isGFX10(const MCSubtargetInfo &STI);
1288bool isGFX10_GFX11(const MCSubtargetInfo &STI);
1289bool isGFX10Plus(const MCSubtargetInfo &STI);
1290bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1291bool isGFX10Before1030(const MCSubtargetInfo &STI);
1292bool isGFX11(const MCSubtargetInfo &STI);
1293bool isGFX11Plus(const MCSubtargetInfo &STI);
1294bool isGFX12(const MCSubtargetInfo &STI);
1295bool isGFX12Plus(const MCSubtargetInfo &STI);
1296bool isNotGFX12Plus(const MCSubtargetInfo &STI);
1297bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1298bool isGCN3Encoding(const MCSubtargetInfo &STI);
1299bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1300bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1301bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1302bool isGFX10_3_GFX11(const MCSubtargetInfo &STI);
1303bool isGFX90A(const MCSubtargetInfo &STI);
1304bool isGFX940(const MCSubtargetInfo &STI);
1306bool hasMAIInsts(const MCSubtargetInfo &STI);
1307bool hasVOPD(const MCSubtargetInfo &STI);
1308bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI);
1309int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1310unsigned hasKernargPreload(const MCSubtargetInfo &STI);
1312
1313/// Is Reg - scalar register
1314bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1315
1316/// \returns if \p Reg occupies the high 16-bits of a 32-bit register.
1318
1319/// If \p Reg is a pseudo reg, return the correct hardware register given
1320/// \p STI otherwise return \p Reg.
1321unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1322
1323/// Convert hardware register \p Reg to a pseudo register
1325unsigned mc2PseudoReg(unsigned Reg);
1326
1328bool isInlineValue(unsigned Reg);
1329
1330/// Is this an AMDGPU specific source operand? These include registers,
1331/// inline constants, literals and mandatory literals (KImm).
1332bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1333
1334/// Is this a KImm operand?
1335bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1336
1337/// Is this floating-point operand?
1338bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1339
1340/// Does this operand support only inlinable literals?
1341bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1342
1343/// Get the size in bits of a register from the register class \p RC.
1344unsigned getRegBitWidth(unsigned RCID);
1345
1346/// Get the size in bits of a register from the register class \p RC.
1347unsigned getRegBitWidth(const MCRegisterClass &RC);
1348
1349/// Get size of register operand
1350unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1351 unsigned OpNo);
1352
1354inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1355 switch (OpInfo.OperandType) {
1368 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1370 return 4;
1371
1377 return 8;
1378
1399 return 2;
1400
1401 default:
1402 llvm_unreachable("unhandled operand type");
1403 }
1404}
1405
1407inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1408 return getOperandSize(Desc.operands()[OpNo]);
1409}
1410
1411/// Is this literal inlinable, and not one of the values intended for floating
1412/// point values.
1414inline bool isInlinableIntLiteral(int64_t Literal) {
1415 return Literal >= -16 && Literal <= 64;
1416}
1417
1418/// Is this literal inlinable
1420bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1421
1423bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1424
1426bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi);
1427
1429bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi);
1430
1432bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi);
1433
1435bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi);
1436
1438std::optional<unsigned> getInlineEncodingV2I16(uint32_t Literal);
1439
1441std::optional<unsigned> getInlineEncodingV2BF16(uint32_t Literal);
1442
1444std::optional<unsigned> getInlineEncodingV2F16(uint32_t Literal);
1445
1447bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType);
1448
1451
1454
1457
1459bool isValid32BitLiteral(uint64_t Val, bool IsFP64);
1460
1461bool isArgPassedInSGPR(const Argument *Arg);
1462
1463bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
1464
1467 int64_t EncodedOffset);
1468
1471 int64_t EncodedOffset,
1472 bool IsBuffer);
1473
1474/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1475/// offsets.
1477
1478/// \returns The encoding that will be used for \p ByteOffset in the
1479/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
1480/// S_LOAD instructions have a signed offset, on other subtargets it is
1481/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1482std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1483 int64_t ByteOffset, bool IsBuffer,
1484 bool HasSOffset = false);
1485
1486/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1487/// instruction. This is only useful on CI.s
1488std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1489 int64_t ByteOffset);
1490
1491/// For pre-GFX12 FLAT instructions the offset must be positive;
1492/// MSB is ignored and forced to zero.
1493///
1494/// \return The number of bits available for the signed offset field in flat
1495/// instructions. Note that some forms of the instruction disallow negative
1496/// offsets.
1497unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1498
1499/// \returns true if this offset is small enough to fit in the SMRD
1500/// offset field. \p ByteOffset should be the offset in bytes and
1501/// not the encoded offset.
1502bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1503
1505inline bool isLegalDPALU_DPPControl(unsigned DC) {
1506 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1507}
1508
1509/// \returns true if an instruction may have a 64-bit VGPR operand.
1510bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1511
1512/// \returns true if an instruction is a DP ALU DPP.
1513bool isDPALU_DPP(const MCInstrDesc &OpDesc);
1514
1515/// \returns true if the intrinsic is divergent
1516bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1517
1518/// \returns true if the intrinsic is uniform
1519bool isIntrinsicAlwaysUniform(unsigned IntrID);
1520
1521/// \returns lds block size in terms of dwords. \p
1522/// This is used to calculate the lds size encoded for PAL metadata 3.0+ which
1523/// must be defined in terms of bytes.
1524unsigned getLdsDwGranularity(const MCSubtargetInfo &ST);
1525
1526} // end namespace AMDGPU
1527
1528raw_ostream &operator<<(raw_ostream &OS,
1530
1531} // end namespace llvm
1532
1533#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
unsigned const MachineRegisterInfo * MRI
Base class for AMDGPU specific classes of TargetSubtarget.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
#define LLVM_READNONE
Definition: Compiler.h:220
#define LLVM_READONLY
Definition: Compiler.h:227
uint64_t Align
std::string Name
uint64_t Size
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void setTargetIDFromFeaturesString(StringRef FS)
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
TargetIDSetting getXnackSetting() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
ComponentInfo(const MCInstrDesc &OpDesc, ComponentKind Kind=ComponentKind::SINGLE)
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const
unsigned getIndexOfDstInParsedOperands() const
ComponentLayout(const ComponentProps &OpXProps)
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
bool hasRegSrcOperand(unsigned CompSrcIdx) const
unsigned getMandatoryLiteralCompOperandIndex() const
unsigned getCompParsedSrcOperandsNum() const
InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
bool hasInvalidOperand(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
const ComponentInfo & operator[](size_t ComponentIdx) const
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Definition: Argument.h:31
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1236
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
Generic base class for all target subtargets.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
static constexpr unsigned GFX10_1
static constexpr unsigned GFX10_3
static constexpr unsigned GFX11
static constexpr unsigned GFX9
static constexpr unsigned GFX12
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
constexpr unsigned COMPONENTS[]
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
SmallVector< unsigned > getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size)
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
LLVM_READONLY const MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
int getMTBUFElements(unsigned Opc)
bool isHi16Reg(MCRegister Reg, const MCRegisterInfo &MRI)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
CanBeVOPD getCanBeVOPD(unsigned Opc)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
bool isInvalidSingleUseProducerInst(unsigned Opc)
bool isInvalidSingleUseConsumerInst(unsigned Opc)
bool isGroupSegment(const GlobalValue *GV)
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getKmcntBitMask(const IsaVersion &Version)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFTfe(unsigned Opc)
LLVM_READONLY const MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
unsigned getBvhcntBitMask(const IsaVersion &Version)
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:234
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:201
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:211
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:227
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:223
@ OPERAND_REG_INLINE_C_BF16
Definition: SIDefines.h:220
@ OPERAND_REG_INLINE_C_V2BF16
Definition: SIDefines.h:225
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:212
@ OPERAND_REG_IMM_BF16
Definition: SIDefines.h:205
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:246
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:200
@ OPERAND_REG_IMM_V2BF16
Definition: SIDefines.h:210
@ OPERAND_REG_IMM_BF16_DEFERRED
Definition: SIDefines.h:207
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:206
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:219
@ OPERAND_REG_INLINE_AC_BF16
Definition: SIDefines.h:240
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:217
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:238
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:226
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:244
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:241
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:239
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:242
@ OPERAND_REG_INLINE_AC_V2BF16
Definition: SIDefines.h:245
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:213
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:203
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:218
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:224
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:214
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:243
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:221
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:202
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:228
@ OPERAND_INLINE_SPLIT_BARRIER_INT32
Definition: SIDefines.h:231
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:209
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:208
void initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI)
bool isNotGFX9Plus(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
bool getMUBUFIsBufferInv(unsigned Opc)
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isMAC(unsigned Opc)
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:200
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:144
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:293
@ Default
The result values are uniform if and only if all operands are uniform.
uint64_t maxUIntN(uint64_t N)
Gets the maximum value for a N-bit unsigned integer.
Definition: MathExtras.h:219
AMD Kernel Code Object (amd_kernel_code_t).
static constexpr unsigned Width
constexpr EncodingField(ValueType Value)
static constexpr unsigned Offset
static constexpr ValueType Default
static ValueType decode(uint64_t Encoded)
constexpr uint64_t encode() const
static constexpr uint64_t encode(Fields... Values)
static std::tuple< typename Fields::ValueType... > decode(uint64_t Encoded)
constexpr uint64_t encode() const
static ValueType decode(uint64_t Encoded)
Represents the counter values to wait for in an s_waitcnt instruction.
Waitcnt(unsigned LoadCnt, unsigned ExpCnt, unsigned DsCnt, unsigned StoreCnt, unsigned SampleCnt, unsigned BvhCnt, unsigned KmCnt)
bool hasWaitExceptStoreCnt() const
bool hasWaitStoreCnt() const
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Waitcnt combined(const Waitcnt &Other) const
Description of the encoding of one expression Op.