LLVM  13.0.0git
AMDGPUBaseInfo.h
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1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 
49  unsigned Format;
50  unsigned BitsPerComp;
51  unsigned NumComponents;
52  unsigned NumFormat;
53  unsigned DataFormat;
54 };
55 
56 #define GET_MIMGBaseOpcode_DECL
57 #define GET_MIMGDim_DECL
58 #define GET_MIMGEncoding_DECL
59 #define GET_MIMGLZMapping_DECL
60 #define GET_MIMGMIPMapping_DECL
61 #include "AMDGPUGenSearchableTables.inc"
62 
63 namespace IsaInfo {
64 
65 enum {
66  // The closed Vulkan driver sets 96, which limits the wave count to 8 but
67  // doesn't spill SGPRs as much as when 80 is set.
70 };
71 
72 enum class TargetIDSetting {
74  Any,
75  Off,
76  On
77 };
78 
80 private:
81  TargetIDSetting XnackSetting;
82  TargetIDSetting SramEccSetting;
83 
84 public:
85  explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
86  ~AMDGPUTargetID() = default;
87 
88  /// \return True if the current xnack setting is not "Unsupported".
89  bool isXnackSupported() const {
90  return XnackSetting != TargetIDSetting::Unsupported;
91  }
92 
93  /// \returns True if the current xnack setting is "On" or "Any".
94  bool isXnackOnOrAny() const {
95  return XnackSetting == TargetIDSetting::On ||
96  XnackSetting == TargetIDSetting::Any;
97  }
98 
99  /// \returns True if current xnack setting is "On" or "Off",
100  /// false otherwise.
101  bool isXnackOnOrOff() const {
102  return getXnackSetting() == TargetIDSetting::On ||
104  }
105 
106  /// \returns The current xnack TargetIDSetting, possible options are
107  /// "Unsupported", "Any", "Off", and "On".
109  return XnackSetting;
110  }
111 
112  /// Sets xnack setting to \p NewXnackSetting.
113  void setXnackSetting(TargetIDSetting NewXnackSetting) {
114  XnackSetting = NewXnackSetting;
115  }
116 
117  /// \return True if the current sramecc setting is not "Unsupported".
118  bool isSramEccSupported() const {
119  return SramEccSetting != TargetIDSetting::Unsupported;
120  }
121 
122  /// \returns True if the current sramecc setting is "On" or "Any".
123  bool isSramEccOnOrAny() const {
124  return SramEccSetting == TargetIDSetting::On ||
125  SramEccSetting == TargetIDSetting::Any;
126  }
127 
128  /// \returns True if current sramecc setting is "On" or "Off",
129  /// false otherwise.
130  bool isSramEccOnOrOff() const {
133  }
134 
135  /// \returns The current sramecc TargetIDSetting, possible options are
136  /// "Unsupported", "Any", "Off", and "On".
138  return SramEccSetting;
139  }
140 
141  /// Sets sramecc setting to \p NewSramEccSetting.
142  void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
143  SramEccSetting = NewSramEccSetting;
144  }
145 
148 };
149 
150 /// Streams isa version string for given subtarget \p STI into \p Stream.
151 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
152 
153 /// \returns Wavefront size for given subtarget \p STI.
154 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
155 
156 /// \returns Local memory size in bytes for given subtarget \p STI.
157 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
158 
159 /// \returns Number of execution units per compute unit for given subtarget \p
160 /// STI.
161 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
162 
163 /// \returns Maximum number of work groups per compute unit for given subtarget
164 /// \p STI and limited by given \p FlatWorkGroupSize.
165 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
166  unsigned FlatWorkGroupSize);
167 
168 /// \returns Minimum number of waves per execution unit for given subtarget \p
169 /// STI.
170 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
171 
172 /// \returns Maximum number of waves per execution unit for given subtarget \p
173 /// STI without any kind of limitation.
174 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
175 
176 /// \returns Number of waves per execution unit required to support the given \p
177 /// FlatWorkGroupSize.
178 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
179  unsigned FlatWorkGroupSize);
180 
181 /// \returns Minimum flat work group size for given subtarget \p STI.
182 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
183 
184 /// \returns Maximum flat work group size for given subtarget \p STI.
185 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
186 
187 /// \returns Number of waves per work group for given subtarget \p STI and
188 /// \p FlatWorkGroupSize.
189 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
190  unsigned FlatWorkGroupSize);
191 
192 /// \returns SGPR allocation granularity for given subtarget \p STI.
193 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
194 
195 /// \returns SGPR encoding granularity for given subtarget \p STI.
196 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
197 
198 /// \returns Total number of SGPRs for given subtarget \p STI.
199 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
200 
201 /// \returns Addressable number of SGPRs for given subtarget \p STI.
202 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
203 
204 /// \returns Minimum number of SGPRs that meets the given number of waves per
205 /// execution unit requirement for given subtarget \p STI.
206 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
207 
208 /// \returns Maximum number of SGPRs that meets the given number of waves per
209 /// execution unit requirement for given subtarget \p STI.
210 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
211  bool Addressable);
212 
213 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
214 /// STI when the given special registers are used.
215 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
216  bool FlatScrUsed, bool XNACKUsed);
217 
218 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
219 /// STI when the given special registers are used. XNACK is inferred from
220 /// \p STI.
221 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
222  bool FlatScrUsed);
223 
224 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
225 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
226 /// register counts.
227 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
228 
229 /// \returns VGPR allocation granularity for given subtarget \p STI.
230 ///
231 /// For subtargets which support it, \p EnableWavefrontSize32 should match
232 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
233 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
234  Optional<bool> EnableWavefrontSize32 = None);
235 
236 /// \returns VGPR encoding granularity for given subtarget \p STI.
237 ///
238 /// For subtargets which support it, \p EnableWavefrontSize32 should match
239 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
240 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
241  Optional<bool> EnableWavefrontSize32 = None);
242 
243 /// \returns Total number of VGPRs for given subtarget \p STI.
244 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
245 
246 /// \returns Addressable number of VGPRs for given subtarget \p STI.
247 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
248 
249 /// \returns Minimum number of VGPRs that meets given number of waves per
250 /// execution unit requirement for given subtarget \p STI.
251 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
252 
253 /// \returns Maximum number of VGPRs that meets given number of waves per
254 /// execution unit requirement for given subtarget \p STI.
255 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
256 
257 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
258 /// \p NumVGPRs are used.
259 ///
260 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
261 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
262 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
263  Optional<bool> EnableWavefrontSize32 = None);
264 
265 } // end namespace IsaInfo
266 
268 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
269 
271 int getSOPPWithRelaxation(uint16_t Opcode);
272 
274  MIMGBaseOpcode BaseOpcode;
275  bool Store;
276  bool Atomic;
277  bool AtomicX2;
278  bool Sampler;
279  bool Gather4;
280 
281  uint8_t NumExtraArgs;
282  bool Gradients;
283  bool G16;
286  bool HasD16;
287 };
288 
290 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
291 
292 struct MIMGDimInfo {
293  MIMGDim Dim;
294  uint8_t NumCoords;
295  uint8_t NumGradients;
296  bool DA;
297  uint8_t Encoding;
298  const char *AsmSuffix;
299 };
300 
302 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
303 
305 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
306 
309 
311  MIMGBaseOpcode L;
312  MIMGBaseOpcode LZ;
313 };
314 
316  MIMGBaseOpcode MIP;
317  MIMGBaseOpcode NONMIP;
318 };
319 
321  MIMGBaseOpcode G;
322  MIMGBaseOpcode G16;
323 };
324 
326 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
327 
329 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
330 
333 
335 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
336  unsigned VDataDwords, unsigned VAddrDwords);
337 
339 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
340 
341 struct MIMGInfo {
344  uint8_t MIMGEncoding;
345  uint8_t VDataDwords;
346  uint8_t VAddrDwords;
347 };
348 
350 const MIMGInfo *getMIMGInfo(unsigned Opc);
351 
353 int getMTBUFBaseOpcode(unsigned Opc);
354 
356 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
357 
359 int getMTBUFElements(unsigned Opc);
360 
362 bool getMTBUFHasVAddr(unsigned Opc);
363 
365 bool getMTBUFHasSrsrc(unsigned Opc);
366 
368 bool getMTBUFHasSoffset(unsigned Opc);
369 
371 int getMUBUFBaseOpcode(unsigned Opc);
372 
374 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
375 
377 int getMUBUFElements(unsigned Opc);
378 
380 bool getMUBUFHasVAddr(unsigned Opc);
381 
383 bool getMUBUFHasSrsrc(unsigned Opc);
384 
386 bool getMUBUFHasSoffset(unsigned Opc);
387 
389 bool getSMEMIsBuffer(unsigned Opc);
390 
392 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
393  uint8_t NumComponents,
394  uint8_t NumFormat,
395  const MCSubtargetInfo &STI);
397 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
398  const MCSubtargetInfo &STI);
399 
401 int getMCOpcode(uint16_t Opcode, unsigned Gen);
402 
404  const MCSubtargetInfo *STI);
405 
407  const MCSubtargetInfo *STI);
408 
409 bool isGroupSegment(const GlobalValue *GV);
410 bool isGlobalSegment(const GlobalValue *GV);
411 bool isReadOnlySegment(const GlobalValue *GV);
412 
413 /// \returns True if constants should be emitted to .text section for given
414 /// target triple \p TT, false otherwise.
416 
417 /// \returns Integer value requested using \p F's \p Name attribute.
418 ///
419 /// \returns \p Default if attribute is not present.
420 ///
421 /// \returns \p Default and emits error if requested value cannot be converted
422 /// to integer.
423 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
424 
425 /// \returns A pair of integer values requested using \p F's \p Name attribute
426 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
427 /// is false).
428 ///
429 /// \returns \p Default if attribute is not present.
430 ///
431 /// \returns \p Default and emits error if one of the requested values cannot be
432 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
433 /// not present.
434 std::pair<int, int> getIntegerPairAttribute(const Function &F,
435  StringRef Name,
436  std::pair<int, int> Default,
437  bool OnlyFirstRequired = false);
438 
439 /// Represents the counter values to wait for in an s_waitcnt instruction.
440 ///
441 /// Large values (including the maximum possible integer) can be used to
442 /// represent "don't care" waits.
443 struct Waitcnt {
444  unsigned VmCnt = ~0u;
445  unsigned ExpCnt = ~0u;
446  unsigned LgkmCnt = ~0u;
447  unsigned VsCnt = ~0u;
448 
449  Waitcnt() {}
450  Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
452 
453  static Waitcnt allZero(bool HasVscnt) {
454  return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
455  }
456  static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
457 
458  bool hasWait() const {
459  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
460  }
461 
462  bool dominates(const Waitcnt &Other) const {
463  return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
464  LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
465  }
466 
467  Waitcnt combined(const Waitcnt &Other) const {
468  return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
469  std::min(LgkmCnt, Other.LgkmCnt),
470  std::min(VsCnt, Other.VsCnt));
471  }
472 };
473 
474 /// \returns Vmcnt bit mask for given isa \p Version.
475 unsigned getVmcntBitMask(const IsaVersion &Version);
476 
477 /// \returns Expcnt bit mask for given isa \p Version.
478 unsigned getExpcntBitMask(const IsaVersion &Version);
479 
480 /// \returns Lgkmcnt bit mask for given isa \p Version.
481 unsigned getLgkmcntBitMask(const IsaVersion &Version);
482 
483 /// \returns Waitcnt bit mask for given isa \p Version.
484 unsigned getWaitcntBitMask(const IsaVersion &Version);
485 
486 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
487 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
488 
489 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
490 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
491 
492 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
493 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
494 
495 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
496 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
497 /// \p Lgkmcnt respectively.
498 ///
499 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
500 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
501 /// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
502 /// \p Expcnt = \p Waitcnt[6:4]
503 /// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10 only)
504 /// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10+ only)
505 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
506  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
507 
508 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
509 
510 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
511 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
512  unsigned Vmcnt);
513 
514 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
515 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
516  unsigned Expcnt);
517 
518 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
519 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
520  unsigned Lgkmcnt);
521 
522 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
523 /// \p Version.
524 ///
525 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
526 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
527 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
528 /// Waitcnt[6:4] = \p Expcnt
529 /// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10 only)
530 /// Waitcnt[13:8] = \p Lgkmcnt (gfx10+ only)
531 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
532 ///
533 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
534 /// isa \p Version.
535 unsigned encodeWaitcnt(const IsaVersion &Version,
536  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
537 
538 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
539 
540 namespace Hwreg {
541 
543 int64_t getHwregId(const StringRef Name);
544 
546 bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI);
547 
549 bool isValidHwreg(int64_t Id);
550 
552 bool isValidHwregOffset(int64_t Offset);
553 
555 bool isValidHwregWidth(int64_t Width);
556 
558 uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
559 
561 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
562 
563 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
564 
565 } // namespace Hwreg
566 
567 namespace Exp {
568 
569 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
570 
572 unsigned getTgtId(const StringRef Name);
573 
575 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
576 
577 } // namespace Exp
578 
579 namespace MTBUFFormat {
580 
582 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
583 
584 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
585 
586 int64_t getDfmt(const StringRef Name);
587 
588 StringRef getDfmtName(unsigned Id);
589 
590 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
591 
592 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
593 
594 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
595 
596 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
597 
598 int64_t getUnifiedFormat(const StringRef Name);
599 
600 StringRef getUnifiedFormatName(unsigned Id);
601 
602 bool isValidUnifiedFormat(unsigned Val);
603 
604 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt);
605 
606 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
607 
608 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
609 
610 } // namespace MTBUFFormat
611 
612 namespace SendMsg {
613 
615 int64_t getMsgId(const StringRef Name);
616 
618 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
619 
621 StringRef getMsgName(int64_t MsgId);
622 
624 StringRef getMsgOpName(int64_t MsgId, int64_t OpId);
625 
627 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict = true);
628 
630 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
631  bool Strict = true);
632 
634 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
635  const MCSubtargetInfo &STI, bool Strict = true);
636 
638 bool msgRequiresOp(int64_t MsgId);
639 
641 bool msgSupportsStream(int64_t MsgId, int64_t OpId);
642 
643 void decodeMsg(unsigned Val,
644  uint16_t &MsgId,
645  uint16_t &OpId,
646  uint16_t &StreamId);
647 
649 uint64_t encodeMsg(uint64_t MsgId,
650  uint64_t OpId,
651  uint64_t StreamId);
652 
653 } // namespace SendMsg
654 
655 
656 unsigned getInitialPSInputAddr(const Function &F);
657 
659 bool isShader(CallingConv::ID CC);
660 
662 bool isGraphics(CallingConv::ID CC);
663 
665 bool isCompute(CallingConv::ID CC);
666 
669 
670 // These functions are considered entrypoints into the current module, i.e. they
671 // are allowed to be called from outside the current module. This is different
672 // from isEntryFunctionCC, which is only true for functions that are entered by
673 // the hardware. Module entry points include all entry functions but also
674 // include functions that can be called from other functions inside or outside
675 // the current module. Module entry functions are allowed to allocate LDS.
678 
679 // FIXME: Remove this when calling conventions cleaned up
681 inline bool isKernel(CallingConv::ID CC) {
682  switch (CC) {
685  return true;
686  default:
687  return false;
688  }
689 }
690 
691 bool hasXNACK(const MCSubtargetInfo &STI);
692 bool hasSRAMECC(const MCSubtargetInfo &STI);
693 bool hasMIMG_R128(const MCSubtargetInfo &STI);
694 bool hasGFX10A16(const MCSubtargetInfo &STI);
695 bool hasG16(const MCSubtargetInfo &STI);
696 bool hasPackedD16(const MCSubtargetInfo &STI);
697 
698 bool isSI(const MCSubtargetInfo &STI);
699 bool isCI(const MCSubtargetInfo &STI);
700 bool isVI(const MCSubtargetInfo &STI);
701 bool isGFX9(const MCSubtargetInfo &STI);
702 bool isGFX9Plus(const MCSubtargetInfo &STI);
703 bool isGFX10(const MCSubtargetInfo &STI);
704 bool isGFX10Plus(const MCSubtargetInfo &STI);
705 bool isGCN3Encoding(const MCSubtargetInfo &STI);
706 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
707 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
708 bool isGFX90A(const MCSubtargetInfo &STI);
709 
710 /// Is Reg - scalar register
711 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
712 
713 /// Is there any intersection between registers
714 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
715 
716 /// If \p Reg is a pseudo reg, return the correct hardware register given
717 /// \p STI otherwise return \p Reg.
718 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
719 
720 /// Convert hardware register \p Reg to a pseudo register
722 unsigned mc2PseudoReg(unsigned Reg);
723 
724 /// Can this operand also contain immediate values?
725 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
726 
727 /// Is this floating-point operand?
728 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
729 
730 /// Does this opearnd support only inlinable literals?
731 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
732 
733 /// Get the size in bits of a register from the register class \p RC.
734 unsigned getRegBitWidth(unsigned RCID);
735 
736 /// Get the size in bits of a register from the register class \p RC.
737 unsigned getRegBitWidth(const MCRegisterClass &RC);
738 
739 /// Get size of register operand
740 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
741  unsigned OpNo);
742 
744 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
745  switch (OpInfo.OperandType) {
756  return 4;
757 
763  return 8;
764 
777  return 2;
778 
779  default:
780  llvm_unreachable("unhandled operand type");
781  }
782 }
783 
785 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
786  return getOperandSize(Desc.OpInfo[OpNo]);
787 }
788 
789 /// Is this literal inlinable, and not one of the values intended for floating
790 /// point values.
792 inline bool isInlinableIntLiteral(int64_t Literal) {
793  return Literal >= -16 && Literal <= 64;
794 }
795 
796 /// Is this literal inlinable
798 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
799 
801 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
802 
804 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
805 
807 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
808 
810 bool isInlinableIntLiteralV216(int32_t Literal);
811 
813 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
814 
815 bool isArgPassedInSGPR(const Argument *Arg);
816 
819  int64_t EncodedOffset);
820 
823  int64_t EncodedOffset,
824  bool IsBuffer);
825 
826 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
827 /// offsets.
828 uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
829 
830 /// \returns The encoding that will be used for \p ByteOffset in the
831 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
832 /// S_LOAD instructions have a signed offset, on other subtargets it is
833 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
835  int64_t ByteOffset, bool IsBuffer);
836 
837 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
838 /// instruction. This is only useful on CI.s
840  int64_t ByteOffset);
841 
842 /// For FLAT segment the offset must be positive;
843 /// MSB is ignored and forced to zero.
844 ///
845 /// \return The number of bits available for the offset field in flat
846 /// instructions.
847 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
848 
849 /// \returns true if this offset is small enough to fit in the SMRD
850 /// offset field. \p ByteOffset should be the offset in bytes and
851 /// not the encoded offset.
852 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
853 
854 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
855  const GCNSubtarget *Subtarget,
856  Align Alignment = Align(4));
857 
859 inline bool isLegal64BitDPPControl(unsigned DC) {
861 }
862 
863 /// \returns true if the intrinsic is divergent
864 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
865 
866 // Track defaults for fields in the MODE registser.
868  /// Floating point opcodes that support exception flag gathering quiet and
869  /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
870  /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
871  /// quieting.
872  bool IEEE : 1;
873 
874  /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
875  /// clamp NaN to zero; otherwise, pass NaN through.
876  bool DX10Clamp : 1;
877 
878  /// If this is set, neither input or output denormals are flushed for most f32
879  /// instructions.
882 
883  /// If this is set, neither input or output denormals are flushed for both f64
884  /// and f16/v2f16 instructions.
887 
889  IEEE(true),
890  DX10Clamp(true),
895 
897 
900  Mode.IEEE = !AMDGPU::isShader(CC);
901  return Mode;
902  }
903 
904  bool operator ==(const SIModeRegisterDefaults Other) const {
905  return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
906  FP32InputDenormals == Other.FP32InputDenormals &&
907  FP32OutputDenormals == Other.FP32OutputDenormals &&
908  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
909  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
910  }
911 
912  bool allFP32Denormals() const {
914  }
915 
916  bool allFP64FP16Denormals() const {
918  }
919 
920  /// Get the encoding value for the FP_DENORM bits of the mode register for the
921  /// FP32 denormal mode.
924  return FP_DENORM_FLUSH_NONE;
925  if (FP32InputDenormals)
926  return FP_DENORM_FLUSH_OUT;
928  return FP_DENORM_FLUSH_IN;
930  }
931 
932  /// Get the encoding value for the FP_DENORM bits of the mode register for the
933  /// FP64/FP16 denormal mode.
936  return FP_DENORM_FLUSH_NONE;
938  return FP_DENORM_FLUSH_OUT;
940  return FP_DENORM_FLUSH_IN;
942  }
943 
944  /// Returns true if a flag is compatible if it's enabled in the callee, but
945  /// disabled in the caller.
946  static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
947  return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
948  }
949 
950  // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
951  // be able to override.
953  if (DX10Clamp != CalleeMode.DX10Clamp)
954  return false;
955  if (IEEE != CalleeMode.IEEE)
956  return false;
957 
958  // Allow inlining denormals enabled into denormals flushed functions.
963  }
964 };
965 
966 } // end namespace AMDGPU
967 
968 raw_ostream &operator<<(raw_ostream &OS,
970 
971 } // end namespace llvm
972 
973 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:154
llvm::AMDGPU::Hwreg::encodeHwreg
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:877
FP_DENORM_FLUSH_OUT
#define FP_DENORM_FLUSH_OUT
Definition: SIDefines.h:874
llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeDPValue
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
Definition: AMDGPUBaseInfo.h:934
llvm::AMDGPU::SendMsg::getMsgName
StringRef getMsgName(int64_t MsgId)
Definition: AMDGPUBaseInfo.cpp:1091
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1365
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:110
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:29
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID
AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:249
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1377
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4550
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:211
llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
llvm::AMDGPU::IsaInfo::getSGPRAllocGranule
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:432
llvm::AMDGPU::getMUBUFHasSoffset
bool getMUBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:230
llvm::AMDGPU::MIMGBaseOpcodeInfo::HasD16
bool HasD16
Definition: AMDGPUBaseInfo.h:286
Reg
unsigned Reg
Definition: MachineSink.cpp:1540
llvm::AMDGPU::Waitcnt::allZeroExceptVsCnt
static Waitcnt allZeroExceptVsCnt()
Definition: AMDGPUBaseInfo.h:456
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:449
llvm::AMDGPU::Hwreg::getHwreg
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:883
llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1046
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:149
llvm::AMDGPU::MIMGBaseOpcodeInfo::Store
bool Store
Definition: AMDGPUBaseInfo.h:275
llvm::AMDGPU::MIMGDimInfo::AsmSuffix
const char * AsmSuffix
Definition: AMDGPUBaseInfo.h:298
llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients
bool Gradients
Definition: AMDGPUBaseInfo.h:282
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs
constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Definition: AMDGPUMetadata.h:243
llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip
bool LodOrClampOrMip
Definition: AMDGPUBaseInfo.h:285
llvm::AMDGPU::MTBUFFormat::getDfmtName
StringRef getDfmtName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:970
llvm::AMDGPU::SendMsg::encodeMsg
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
Definition: AMDGPUBaseInfo.cpp:1170
llvm::AMDGPU::decodeLgkmcnt
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:779
llvm::Function
Definition: Function.h:61
llvm::AMDGPU::getMUBUFBaseOpcode
int getMUBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:205
llvm::AMDGPU::SIModeRegisterDefaults::FP32OutputDenormals
bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:881
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setXnackSetting
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
Definition: AMDGPUBaseInfo.h:113
llvm::AMDGPU::getSMRDEncodedOffset
Optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1686
llvm::AMDGPU::getMCOpcode
int getMCOpcode(uint16_t Opcode, unsigned Gen)
Definition: AMDGPUBaseInfo.cpp:243
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrAny
bool isSramEccOnOrAny() const
Definition: AMDGPUBaseInfo.h:123
llvm::AMDGPU::decodeVmcnt
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:763
llvm::AMDGPU::hasSRAMECC
bool hasSRAMECC(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1241
llvm::AMDGPU::SIModeRegisterDefaults::IEEE
bool IEEE
Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:872
llvm::AMDGPU::hasXNACK
bool hasXNACK(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1237
llvm::AMDGPU::IsaInfo::TargetIDSetting::Unsupported
@ Unsupported
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:143
llvm::AMDGPU::IsaInfo::TargetIDSetting::On
@ On
llvm::AMDGPU::IsaInfo::streamIsaVersion
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream)
Streams isa version string for given subtarget STI into Stream.
Definition: AMDGPUBaseInfo.cpp:337
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bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1291
llvm::AMDGPU::isLegal64BitDPPControl
LLVM_READNONE bool isLegal64BitDPPControl(unsigned DC)
Definition: AMDGPUBaseInfo.h:859
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Definition: AMDGPUBaseInfo.h:279
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Definition: AMDGPUBaseInfo.h:292
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~AMDGPUTargetID()=default
llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt
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Definition: AMDGPUBaseInfo.cpp:1008
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Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:90
FP_DENORM_FLUSH_IN
#define FP_DENORM_FLUSH_IN
Definition: SIDefines.h:875
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:68
llvm::AMDGPU::getSMRDEncodedLiteralOffset32
Optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:1703
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const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
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bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1004
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@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:145
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unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
Definition: AMDGPUBaseInfo.cpp:498
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1281
llvm::AMDGPU::IsaInfo::getTotalNumVGPRs
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:561
llvm::AMDGPU::MTBUFFormat::getUnifiedFormat
int64_t getUnifiedFormat(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1017
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void setTargetIDFromTargetIDStream(StringRef TargetID)
Definition: AMDGPUBaseInfo.cpp:325
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unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:399
llvm::Optional< bool >
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static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:898
llvm::AMDGPU::SIModeRegisterDefaults
Definition: AMDGPUBaseInfo.h:867
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:880
llvm::AMDGPU::IsaInfo::TargetIDSetting::Any
@ Any
llvm::GCNSubtarget
Definition: GCNSubtarget.h:38
llvm::AMDGPU::getVmcntBitMask
unsigned getVmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:733
llvm::AMDGPU::SIModeRegisterDefaults::isInlineCompatible
bool isInlineCompatible(SIModeRegisterDefaults CalleeMode) const
Definition: AMDGPUBaseInfo.h:952
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bool isGlobalSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:679
llvm::AMDGPU::MIMGDimInfo::Dim
MIMGDim Dim
Definition: AMDGPUBaseInfo.h:293
llvm::AMDGPU::SendMsg::getMsgId
int64_t getMsgId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1060
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bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1295
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LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::AMDGPU::SIModeRegisterDefaults::oneWayCompatible
static bool oneWayCompatible(bool CallerMode, bool CalleeMode)
Returns true if a flag is compatible if it's enabled in the callee, but disabled in the caller.
Definition: AMDGPUBaseInfo.h:946
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unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:586
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unsigned getWaitcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:750
llvm::X86AS::FS
@ FS
Definition: X86.h:182
llvm::AMDGPU::isIntrinsicSourceOfDivergence
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
Definition: AMDGPUBaseInfo.cpp:1813
llvm::AMDGPU::SendMsg::getMsgOpName
StringRef getMsgOpName(int64_t MsgId, int64_t OpId)
Definition: AMDGPUBaseInfo.cpp:1128
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uint8_t NumGradients
Definition: AMDGPUBaseInfo.h:295
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1541
llvm::AMDGPU::getMTBUFOpcode
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:180
llvm::AMDGPU::MIMGMIPMappingInfo::NONMIP
MIMGBaseOpcode NONMIP
Definition: AMDGPUBaseInfo.h:317
llvm::AMDGPU::MIMGInfo::VAddrDwords
uint8_t VAddrDwords
Definition: AMDGPUBaseInfo.h:346
llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:387
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:997
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AMDGPU::isKernel
LLVM_READNONE bool isKernel(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:681
llvm::AMDGPU::IsaInfo::TargetIDSetting
TargetIDSetting
Definition: AMDGPUBaseInfo.h:72
llvm::AMDGPU::Hwreg::decodeHwreg
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
Definition: AMDGPUBaseInfo.cpp:887
llvm::AMDGPU::GcnBufferFormatInfo::DataFormat
unsigned DataFormat
Definition: AMDGPUBaseInfo.h:53
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:205
llvm::MCOperandInfo
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:84
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:441
llvm::AMDGPU::getSOPPWithRelaxation
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1299
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:140
llvm::AMDGPU::SIModeRegisterDefaults::operator==
bool operator==(const SIModeRegisterDefaults Other) const
Definition: AMDGPUBaseInfo.h:904
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Definition: AMDGPUBaseInfo.h:79
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bool getMTBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:195
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1188
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unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:427
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:150
llvm::AMDGPU::getRegOperandSize
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:1516
llvm::AMDGPU::Waitcnt::Waitcnt
Waitcnt()
Definition: AMDGPUBaseInfo.h:449
llvm::ReplacementType::Literal
@ Literal
llvm::AMDGPU::Hwreg::isValidHwreg
bool isValidHwreg(int64_t Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:859
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:273
llvm::AMDGPU::isInlinableIntLiteralV216
bool isInlinableIntLiteralV216(int32_t Literal)
Definition: AMDGPUBaseInfo.cpp:1600
llvm::AMDGPU::MIMGG16MappingInfo::G
MIMGBaseOpcode G
Definition: AMDGPUBaseInfo.h:321
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:163
llvm::AMDGPU::getMUBUFOpcode
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:210
llvm::AMDGPU::getSMEMIsBuffer
bool getSMEMIsBuffer(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:235
llvm::AMDGPU::MIMGDimInfo::Encoding
uint8_t Encoding
Definition: AMDGPUBaseInfo.h:297
llvm::AMDGPU::IsaInfo::getMaxNumSGPRs
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
Definition: AMDGPUBaseInfo.cpp:481
llvm::AMDGPU::isSGPR
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1303
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:339
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrAny
bool isXnackOnOrAny() const
Definition: AMDGPUBaseInfo.h:94
llvm::AMDGPU::GcnBufferFormatInfo::NumFormat
unsigned NumFormat
Definition: AMDGPUBaseInfo.h:52
llvm::AMDGPU::decodeExpcnt
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:775
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:196
llvm::AMDGPU::hasGFX10A16
bool hasGFX10A16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1249
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:211
llvm::AMDGPU::MIMGLZMappingInfo
Definition: AMDGPUBaseInfo.h:310
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:141
llvm::AMDGPU::getMTBUFBaseOpcode
int getMTBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:175
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1184
FP_DENORM_FLUSH_IN_FLUSH_OUT
#define FP_DENORM_FLUSH_IN_FLUSH_OUT
Definition: SIDefines.h:873
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:50
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Definition: AMDGPUBaseInfo.cpp:200
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Definition: AMDGPUBaseInfo.h:447
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Definition: APFixedPoint.h:230
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void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
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Definition: AMDGPUBaseInfo.cpp:784
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bool dominates(const Waitcnt &Other) const
Definition: AMDGPUBaseInfo.h:462
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@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:146
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Definition: AMDGPUBaseInfo.h:137
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Definition: InstrProf.h:995
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Definition: AMDGPUBaseInfo.cpp:225
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Definition: AMDGPUBaseInfo.cpp:1677
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Definition: AMDGPUBaseInfo.cpp:376
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Definition: AMDGPUBaseInfo.h:344
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Definition: AMDGPUBaseInfo.cpp:367
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Definition: Alignment.h:39
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Definition: SIDefines.h:325
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Definition: CallingConv.h:24
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Definition: AMDGPUBaseInfo.cpp:1285
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Definition: AMDGPUBaseInfo.cpp:1042
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Definition: AMDGPUBaseInfo.cpp:104
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Definition: AMDGPUBaseInfo.cpp:742
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Definition: GlobalValue.h:44
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Definition: AMDGPUBaseInfo.cpp:464
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Definition: AMDGPUBaseInfo.h:792
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Definition: AMDGPUBaseInfo.cpp:1253
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Definition: SIDefines.h:368
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:151
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Definition: ELFObjHandler.cpp:84
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Definition: ARMBaseInfo.h:73
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@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:153
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Definition: AMDGPUBaseInfo.h:311
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Definition: AMDGPUBaseInfo.h:916
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Information about the type of the operand.
Definition: MCInstrDesc.h:96
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Definition: AMDGPUBaseInfo.cpp:605
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Definition: AMDGPUBaseInfo.h:467
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Definition: AMDGPUBaseInfo.cpp:693
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Definition: AMDGPUBaseInfo.h:130
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Definition: AMDGPUBaseInfo.h:50
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#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:876
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Definition: AMDGPUBaseInfo.cpp:1817
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Definition: AMDGPUBaseInfo.h:315
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Definition: AMDGPUBaseInfo.cpp:358
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Does this opearnd support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:1419
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Definition: AMDGPUBaseInfo.cpp:869
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Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:876
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Definition: AMDGPUBaseInfo.cpp:799
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Definition: AMDGPUBaseInfo.cpp:1153
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Definition: AMDGPUBaseInfo.h:108
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Definition: AMDGPUBaseInfo.h:885
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@ OPERAND_REG_INLINE_AC_INT16
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Definition: SIDefines.h:161
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Definition: MCInstrDesc.h:207
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@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:155
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Definition: AMDGPUBaseInfo.cpp:452
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Definition: AMDGPUBaseInfo.h:277
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Definition: AMDGPUBaseInfo.cpp:528
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:164
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MIMGInfo::BaseOpcode
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Definition: AMDGPUBaseInfo.h:343
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Definition: AMDGPUBaseInfo.cpp:1566
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:139
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::getMIMGMIPMappingInfo
const LLVM_READONLY MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:162
llvm::AMDGPU::SendMsg::msgSupportsStream
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Definition: AMDGPUBaseInfo.cpp:1157
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Definition: FileCheck.cpp:339
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Definition: StringRef.h:57
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MIMGBaseOpcode LZ
Definition: AMDGPUBaseInfo.h:312
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bool hasWait() const
Definition: AMDGPUBaseInfo.h:458
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Definition: AMDGPUBaseInfo.cpp:1228
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#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
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Definition: AMDGPUBaseInfo.cpp:1207
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Definition: AMDGPUBaseInfo.cpp:549
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Definition: AMDGPUBaseInfo.cpp:595
DC
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Definition: DebugCounter.cpp:55
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
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bool Coordinates
Definition: AMDGPUBaseInfo.h:284
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
Definition: AMDGPUBaseInfo.cpp:1659
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bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1385
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bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1203
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AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
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bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:89
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Definition: AMDGPUBaseInfo.cpp:422
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bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:916
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Definition: AMDGPUBaseInfo.h:444
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:190
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Definition: MCRegisterInfo.h:128
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int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1033
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Definition: AMDGPUBaseInfo.h:274
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Definition: AMDGPUBaseInfo.h:48
llvm::AMDGPU::GcnBufferFormatInfo::Format
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Definition: AMDGPUBaseInfo.h:49
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Definition: AMDGPUBaseInfo.cpp:1277
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MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
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Definition: AMDGPUBaseInfo.h:886
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Definition: AMDGPUBaseInfo.cpp:675
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Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Definition: AMDGPUBaseInfo.h:450
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setSramEccSetting
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
Definition: AMDGPUBaseInfo.h:142
CallingConv.h
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:821
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1108
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1261
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:165
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:204
Alignment.h
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:1624
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Definition: AMDGPUBaseInfo.h:443
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Definition: GraphWriter.h:52
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Definition: AMDGPUBaseInfo.h:888
llvm::AMDGPU::getMUBUFHasVAddr
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Definition: AMDGPUBaseInfo.cpp:220
llvm::AMDGPU::isInlinableLiteral64
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Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:1523
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:144
uint16_t
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:215
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1096
SIDefines.h
llvm::AMDGPU::MIMGBaseOpcodeInfo::Atomic
bool Atomic
Definition: AMDGPUBaseInfo.h:276
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:1611
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrOff
bool isXnackOnOrOff() const
Definition: AMDGPUBaseInfo.h:101
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:156
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:342
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:165
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:1727
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Definition: AMDGPUBaseInfo.h:341
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1012
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:927
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:158
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
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Definition: AMDGPUBaseInfo.cpp:569
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Definition: AMDGPUBaseInfo.cpp:1161
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bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1133
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Definition: AMDGPUBaseInfo.cpp:992
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:391
llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS
@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:69
llvm::AMDGPU::getLgkmcntBitMask
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Definition: AMDGPUBaseInfo.cpp:746
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llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs
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Definition: AMDGPUBaseInfo.h:281
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Definition: AMDGPUBaseInfo.cpp:1540
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unsigned NumComponents
Definition: AMDGPUBaseInfo.h:51
llvm::AMDGPU::isSISrcFPOperand
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
Definition: AMDGPUBaseInfo.cpp:1392
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Definition: AMDGPUBaseInfo.cpp:810
llvm::AMDGPU::isRegIntersect
bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo *TRI)
Is there any intersection between registers.
Definition: AMDGPUBaseInfo.cpp:1310
llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName
StringRef getUnifiedFormatName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1025
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bool isGCN3Encoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1287
llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST
@ ROW_NEWBCAST_FIRST
Definition: SIDefines.h:696
llvm::AMDGPU::MTBUFFormat::getNfmt
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:983
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Definition: AMDGPUBaseInfo.h:744
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uint32_t fpDenormModeSPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP32 denormal mode.
Definition: AMDGPUBaseInfo.h:922
llvm::AMDGPU::getNumFlatOffsetBits
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
Definition: AMDGPUBaseInfo.cpp:1712
llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:412
llvm::AMDGPU::MIMGDimInfo::DA
bool DA
Definition: AMDGPUBaseInfo.h:296
llvm::AMDGPU::IsaInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:403
llvm::AMDGPU::IsaInfo::getMinNumVGPRs
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:575
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int64_t getHwregId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:840
llvm::AMDGPU::OPERAND_REG_IMM_INT32
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:137
llvm::AMDGPU::hasMIMG_R128
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Definition: AMDGPUBaseInfo.cpp:1245
llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST
@ ROW_NEWBCAST_LAST
Definition: SIDefines.h:697
llvm::AMDGPU::MIMGBaseOpcodeInfo::G16
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Definition: AMDGPUBaseInfo.h:283
llvm::AMDGPU::MIMGMIPMappingInfo::MIP
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Definition: AMDGPUBaseInfo.h:316
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:152
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromFeaturesString
void setTargetIDFromFeaturesString(StringRef FS)
Definition: AMDGPUBaseInfo.cpp:257
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Definition: AMDGPUBaseInfo.cpp:683
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Definition: AMDGPUBaseInfo.h:320
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bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:1665
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:142
llvm::AMDGPU::encodeLgkmcnt
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
Definition: AMDGPUBaseInfo.cpp:815
llvm::AMDGPU::Waitcnt::allZero
static Waitcnt allZero(bool HasVscnt)
Definition: AMDGPUBaseInfo.h:453
llvm::AMDGPU::MIMGInfo::VDataDwords
uint8_t VDataDwords
Definition: AMDGPUBaseInfo.h:345
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:166
llvm::AMDGPU::MTBUFFormat::getDfmt
int64_t getDfmt(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:962
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:221
llvm::AMDGPU::Waitcnt::ExpCnt
unsigned ExpCnt
Definition: AMDGPUBaseInfo.h:445
llvm::AMDGPU::getIntegerPairAttribute
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
Definition: AMDGPUBaseInfo.cpp:708
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccSupported
bool isSramEccSupported() const
Definition: AMDGPUBaseInfo.h:118
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:147
llvm::AMDGPU::getMIMGG16MappingInfo
const LLVM_READONLY MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1827
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1068
llvm::AMDGPU::MIMGG16MappingInfo::G16
MIMGBaseOpcode G16
Definition: AMDGPUBaseInfo.h:322
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPU::SIModeRegisterDefaults::allFP32Denormals
bool allFP32Denormals() const
Definition: AMDGPUBaseInfo.h:912
llvm::AMDGPU::IsaInfo::getVGPRAllocGranule
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:534
llvm::AMDGPU::OPERAND_REG_IMM_INT64
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:138
llvm::AMDGPU::getMaskedMIMGOp
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
Definition: AMDGPUBaseInfo.cpp:136
llvm::codeview::PublicSymFlags::Function
@ Function
llvm::AMDGPU::MIMGBaseOpcodeInfo::Sampler
bool Sampler
Definition: AMDGPUBaseInfo.h:278
llvm::AMDGPU::getMTBUFElements
int getMTBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:185
Other
Optional< std::vector< StOtherPiece > > Other
Definition: ELFYAML.cpp:1131
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:167
llvm::AMDGPU::MIMGDimInfo::NumCoords
uint8_t NumCoords
Definition: AMDGPUBaseInfo.h:294