LLVM 18.0.0git
AMDGPUBaseInfo.h
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1//===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11
12#include "SIDefines.h"
13#include "llvm/IR/CallingConv.h"
14#include "llvm/IR/InstrTypes.h"
15#include "llvm/IR/Module.h"
17#include <array>
18#include <functional>
19#include <utility>
20
22
23namespace llvm {
24
25struct Align;
26class Argument;
27class Function;
28class GlobalValue;
29class MCInstrInfo;
30class MCRegisterClass;
31class MCRegisterInfo;
32class MCSubtargetInfo;
33class StringRef;
34class Triple;
35class raw_ostream;
36
37namespace amdhsa {
38struct kernel_descriptor_t;
39}
40
41namespace AMDGPU {
42
43struct IsaVersion;
44
45enum {
49 AMDHSA_COV5 = 5
50};
51
52/// \returns HSA OS ABI Version identification.
53std::optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
54/// \returns True if HSA OS ABI Version identification is 2,
55/// false otherwise.
56bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
57/// \returns True if HSA OS ABI Version identification is 3,
58/// false otherwise.
59bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
60/// \returns True if HSA OS ABI Version identification is 4,
61/// false otherwise.
62bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
63/// \returns True if HSA OS ABI Version identification is 5,
64/// false otherwise.
65bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
66/// \returns True if HSA OS ABI Version identification is 3 and above,
67/// false otherwise.
69
70/// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
71unsigned getMultigridSyncArgImplicitArgPosition(unsigned COV);
72
73/// \returns The offset of the hostcall pointer argument from implicitarg_ptr
74unsigned getHostcallImplicitArgPosition(unsigned COV);
75
76unsigned getDefaultQueueImplicitArgPosition(unsigned COV);
77unsigned getCompletionActionImplicitArgPosition(unsigned COV);
78
79/// \returns Code object version.
81
82/// \returns Code object version.
83unsigned getCodeObjectVersion(const Module &M);
84
86 unsigned Format;
87 unsigned BitsPerComp;
88 unsigned NumComponents;
89 unsigned NumFormat;
90 unsigned DataFormat;
91};
92
97};
98
99#define GET_MIMGBaseOpcode_DECL
100#define GET_MIMGDim_DECL
101#define GET_MIMGEncoding_DECL
102#define GET_MIMGLZMapping_DECL
103#define GET_MIMGMIPMapping_DECL
104#define GET_MIMGBiASMapping_DECL
105#define GET_MAIInstInfoTable_DECL
106#include "AMDGPUGenSearchableTables.inc"
107
108namespace IsaInfo {
109
110enum {
111 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
112 // doesn't spill SGPRs as much as when 80 is set.
114 TRAP_NUM_SGPRS = 16
116
117enum class TargetIDSetting {
119 Any,
120 Off,
121 On
122};
123
125private:
126 const MCSubtargetInfo &STI;
127 TargetIDSetting XnackSetting;
128 TargetIDSetting SramEccSetting;
129 unsigned CodeObjectVersion;
130
131public:
132 explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
133 ~AMDGPUTargetID() = default;
134
135 /// \return True if the current xnack setting is not "Unsupported".
136 bool isXnackSupported() const {
137 return XnackSetting != TargetIDSetting::Unsupported;
138 }
139
140 /// \returns True if the current xnack setting is "On" or "Any".
141 bool isXnackOnOrAny() const {
142 return XnackSetting == TargetIDSetting::On ||
143 XnackSetting == TargetIDSetting::Any;
144 }
145
146 /// \returns True if current xnack setting is "On" or "Off",
147 /// false otherwise.
148 bool isXnackOnOrOff() const {
151 }
152
153 /// \returns The current xnack TargetIDSetting, possible options are
154 /// "Unsupported", "Any", "Off", and "On".
156 return XnackSetting;
157 }
158
159 void setCodeObjectVersion(unsigned COV) {
160 CodeObjectVersion = COV;
161 }
162
163 /// Sets xnack setting to \p NewXnackSetting.
164 void setXnackSetting(TargetIDSetting NewXnackSetting) {
165 XnackSetting = NewXnackSetting;
166 }
167
168 /// \return True if the current sramecc setting is not "Unsupported".
169 bool isSramEccSupported() const {
170 return SramEccSetting != TargetIDSetting::Unsupported;
171 }
172
173 /// \returns True if the current sramecc setting is "On" or "Any".
174 bool isSramEccOnOrAny() const {
175 return SramEccSetting == TargetIDSetting::On ||
176 SramEccSetting == TargetIDSetting::Any;
177 }
178
179 /// \returns True if current sramecc setting is "On" or "Off",
180 /// false otherwise.
181 bool isSramEccOnOrOff() const {
184 }
185
186 /// \returns The current sramecc TargetIDSetting, possible options are
187 /// "Unsupported", "Any", "Off", and "On".
189 return SramEccSetting;
190 }
191
192 /// Sets sramecc setting to \p NewSramEccSetting.
193 void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
194 SramEccSetting = NewSramEccSetting;
195 }
196
199
200 /// \returns String representation of an object.
201 std::string toString() const;
202};
203
204/// \returns Wavefront size for given subtarget \p STI.
205unsigned getWavefrontSize(const MCSubtargetInfo *STI);
206
207/// \returns Local memory size in bytes for given subtarget \p STI.
208unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
209
210/// \returns Maximum addressable local memory size in bytes for given subtarget
211/// \p STI.
213
214/// \returns Number of execution units per compute unit for given subtarget \p
215/// STI.
216unsigned getEUsPerCU(const MCSubtargetInfo *STI);
217
218/// \returns Maximum number of work groups per compute unit for given subtarget
219/// \p STI and limited by given \p FlatWorkGroupSize.
220unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
221 unsigned FlatWorkGroupSize);
222
223/// \returns Minimum number of waves per execution unit for given subtarget \p
224/// STI.
225unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
226
227/// \returns Maximum number of waves per execution unit for given subtarget \p
228/// STI without any kind of limitation.
229unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
230
231/// \returns Number of waves per execution unit required to support the given \p
232/// FlatWorkGroupSize.
234 unsigned FlatWorkGroupSize);
235
236/// \returns Minimum flat work group size for given subtarget \p STI.
237unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
238
239/// \returns Maximum flat work group size for given subtarget \p STI.
240unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
241
242/// \returns Number of waves per work group for given subtarget \p STI and
243/// \p FlatWorkGroupSize.
244unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
245 unsigned FlatWorkGroupSize);
246
247/// \returns SGPR allocation granularity for given subtarget \p STI.
248unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
249
250/// \returns SGPR encoding granularity for given subtarget \p STI.
251unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
252
253/// \returns Total number of SGPRs for given subtarget \p STI.
254unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
255
256/// \returns Addressable number of SGPRs for given subtarget \p STI.
257unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
258
259/// \returns Minimum number of SGPRs that meets the given number of waves per
260/// execution unit requirement for given subtarget \p STI.
261unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
262
263/// \returns Maximum number of SGPRs that meets the given number of waves per
264/// execution unit requirement for given subtarget \p STI.
265unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
266 bool Addressable);
267
268/// \returns Number of extra SGPRs implicitly required by given subtarget \p
269/// STI when the given special registers are used.
270unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
271 bool FlatScrUsed, bool XNACKUsed);
272
273/// \returns Number of extra SGPRs implicitly required by given subtarget \p
274/// STI when the given special registers are used. XNACK is inferred from
275/// \p STI.
276unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
277 bool FlatScrUsed);
278
279/// \returns Number of SGPR blocks needed for given subtarget \p STI when
280/// \p NumSGPRs are used. \p NumSGPRs should already include any special
281/// register counts.
282unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
283
284/// \returns VGPR allocation granularity for given subtarget \p STI.
285///
286/// For subtargets which support it, \p EnableWavefrontSize32 should match
287/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
288unsigned
290 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
291
292/// \returns VGPR encoding granularity for given subtarget \p STI.
293///
294/// For subtargets which support it, \p EnableWavefrontSize32 should match
295/// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
297 const MCSubtargetInfo *STI,
298 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
299
300/// \returns Total number of VGPRs for given subtarget \p STI.
301unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
302
303/// \returns Addressable number of VGPRs for given subtarget \p STI.
304unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
305
306/// \returns Minimum number of VGPRs that meets given number of waves per
307/// execution unit requirement for given subtarget \p STI.
308unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
309
310/// \returns Maximum number of VGPRs that meets given number of waves per
311/// execution unit requirement for given subtarget \p STI.
312unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
313
314/// \returns Number of waves reachable for a given \p NumVGPRs usage for given
315/// subtarget \p STI.
317 unsigned NumVGPRs);
318
319/// \returns Number of VGPR blocks needed for given subtarget \p STI when
320/// \p NumVGPRs are used.
321///
322/// For subtargets which support it, \p EnableWavefrontSize32 should match the
323/// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
324unsigned
325getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
326 std::optional<bool> EnableWavefrontSize32 = std::nullopt);
327
328} // end namespace IsaInfo
329
331int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
332
334inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
335 return getNamedOperandIdx(Opcode, NamedIdx) != -1;
336}
337
340
342 MIMGBaseOpcode BaseOpcode;
343 bool Store;
344 bool Atomic;
348
351 bool G16;
354 bool HasD16;
355 bool MSAA;
356 bool BVH;
357 bool A16;
358};
359
361const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
362
364const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
365
367 MIMGDim Dim;
368 uint8_t NumCoords;
370 bool MSAA;
371 bool DA;
372 uint8_t Encoding;
373 const char *AsmSuffix;
374};
375
377const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
378
381
384
386 MIMGBaseOpcode L;
387 MIMGBaseOpcode LZ;
388};
389
391 MIMGBaseOpcode MIP;
392 MIMGBaseOpcode NONMIP;
393};
394
396 MIMGBaseOpcode Bias;
397 MIMGBaseOpcode NoBias;
398};
399
401 MIMGBaseOpcode Offset;
402 MIMGBaseOpcode NoOffset;
403};
404
406 MIMGBaseOpcode G;
407 MIMGBaseOpcode G16;
408};
409
412
414 unsigned Opcode2Addr;
415 unsigned Opcode3Addr;
416};
417
420
423
426
429
431int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
432 unsigned VDataDwords, unsigned VAddrDwords);
433
435int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
436
438unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
439 const MIMGDimInfo *Dim, bool IsA16,
440 bool IsG16Supported);
441
442struct MIMGInfo {
446 uint8_t VDataDwords;
447 uint8_t VAddrDwords;
449};
450
452const MIMGInfo *getMIMGInfo(unsigned Opc);
453
455int getMTBUFBaseOpcode(unsigned Opc);
456
458int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
459
461int getMTBUFElements(unsigned Opc);
462
464bool getMTBUFHasVAddr(unsigned Opc);
465
467bool getMTBUFHasSrsrc(unsigned Opc);
468
470bool getMTBUFHasSoffset(unsigned Opc);
471
473int getMUBUFBaseOpcode(unsigned Opc);
474
476int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
477
479int getMUBUFElements(unsigned Opc);
480
482bool getMUBUFHasVAddr(unsigned Opc);
483
485bool getMUBUFHasSrsrc(unsigned Opc);
486
488bool getMUBUFHasSoffset(unsigned Opc);
489
491bool getMUBUFIsBufferInv(unsigned Opc);
492
494bool getSMEMIsBuffer(unsigned Opc);
495
497bool getVOP1IsSingle(unsigned Opc);
498
500bool getVOP2IsSingle(unsigned Opc);
501
503bool getVOP3IsSingle(unsigned Opc);
504
506bool isVOPC64DPP(unsigned Opc);
507
508/// Returns true if MAI operation is a double precision GEMM.
510bool getMAIIsDGEMM(unsigned Opc);
511
513bool getMAIIsGFX940XDL(unsigned Opc);
514
515struct CanBeVOPD {
516 bool X;
517 bool Y;
518};
519
521CanBeVOPD getCanBeVOPD(unsigned Opc);
522
524const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
525 uint8_t NumComponents,
526 uint8_t NumFormat,
527 const MCSubtargetInfo &STI);
530 const MCSubtargetInfo &STI);
531
533int getMCOpcode(uint16_t Opcode, unsigned Gen);
534
536unsigned getVOPDOpcode(unsigned Opc);
537
539int getVOPDFull(unsigned OpX, unsigned OpY);
540
542bool isVOPD(unsigned Opc);
543
545bool isMAC(unsigned Opc);
546
548bool isPermlane16(unsigned Opc);
549
551bool isGenericAtomic(unsigned Opc);
552
553namespace VOPD {
554
555enum Component : unsigned {
556 DST = 0,
560
565
566// LSB mask for VGPR banks per VOPD component operand.
567// 4 banks result in a mask 3, setting 2 lower bits.
568constexpr unsigned VOPD_VGPR_BANK_MASKS[] = {1, 3, 3, 1};
569
570enum ComponentIndex : unsigned { X = 0, Y = 1 };
572constexpr unsigned COMPONENTS_NUM = 2;
573
574// Properties of VOPD components.
576private:
577 unsigned SrcOperandsNum = 0;
578 unsigned MandatoryLiteralIdx = ~0u;
579 bool HasSrc2Acc = false;
580
581public:
582 ComponentProps() = default;
583 ComponentProps(const MCInstrDesc &OpDesc);
584
585 // Return the total number of src operands this component has.
586 unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
587
588 // Return the number of src operands of this component visible to the parser.
590 return SrcOperandsNum - HasSrc2Acc;
591 }
592
593 // Return true iif this component has a mandatory literal.
594 bool hasMandatoryLiteral() const { return MandatoryLiteralIdx != ~0u; }
595
596 // If this component has a mandatory literal, return component operand
597 // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
600 return MandatoryLiteralIdx;
601 }
602
603 // Return true iif this component has operand
604 // with component index CompSrcIdx and this operand may be a register.
605 bool hasRegSrcOperand(unsigned CompSrcIdx) const {
606 assert(CompSrcIdx < Component::MAX_SRC_NUM);
607 return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
608 }
609
610 // Return true iif this component has tied src2.
611 bool hasSrc2Acc() const { return HasSrc2Acc; }
612
613private:
614 bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
615 assert(CompSrcIdx < Component::MAX_SRC_NUM);
616 return MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
617 }
618};
619
620enum ComponentKind : unsigned {
621 SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
622 COMPONENT_X, // A VOPD instruction, X component.
623 COMPONENT_Y, // A VOPD instruction, Y component.
626
627// Interface functions of this class map VOPD component operand indices
628// to indices of operands in MachineInstr/MCInst or parsed operands array.
629//
630// Note that this class operates with 3 kinds of indices:
631// - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
632// - MC operand indices (they refer operands in a MachineInstr/MCInst);
633// - parsed operand indices (they refer operands in parsed operands array).
634//
635// For SINGLE components mapping between these indices is trivial.
636// But things get more complicated for COMPONENT_X and
637// COMPONENT_Y because these components share the same
638// MachineInstr/MCInst and the same parsed operands array.
639// Below is an example of component operand to parsed operand
640// mapping for the following instruction:
641//
642// v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
643//
644// PARSED COMPONENT PARSED
645// COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
646// -------------------------------------------------------------------
647// "v_dual_add_f32" 0
648// v_dual_add_f32 v255 0 (DST) --> 1
649// v4 1 (SRC0) --> 2
650// v5 2 (SRC1) --> 3
651// "::" 4
652// "v_dual_mov_b32" 5
653// v_dual_mov_b32 v6 0 (DST) --> 6
654// v1 1 (SRC0) --> 7
655// -------------------------------------------------------------------
656//
658private:
659 // Regular MachineInstr/MCInst operands are ordered as follows:
660 // dst, src0 [, other src operands]
661 // VOPD MachineInstr/MCInst operands are ordered as follows:
662 // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
663 // Each ComponentKind has operand indices defined below.
664 static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
665 static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
666
667 // Parsed operands of regular instructions are ordered as follows:
668 // Mnemo dst src0 [vsrc1 ...]
669 // Parsed VOPD operands are ordered as follows:
670 // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
671 // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
672 // Each ComponentKind has operand indices defined below.
673 static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
674 4 /* + OpX.ParsedSrcNum */};
675 static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
676 2, 2, 5 /* + OpX.ParsedSrcNum */};
677
678private:
679 const ComponentKind Kind;
680 const ComponentProps PrevComp;
681
682public:
683 // Create layout for COMPONENT_X or SINGLE component.
684 ComponentLayout(ComponentKind Kind) : Kind(Kind) {
686 }
687
688 // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
690 : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
691
692public:
693 // Return the index of dst operand in MCInst operands.
694 unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
695
696 // Return the index of the specified src operand in MCInst operands.
697 unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
698 assert(CompSrcIdx < Component::MAX_SRC_NUM);
699 return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
700 }
701
702 // Return the index of dst operand in the parsed operands array.
704 return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
705 }
706
707 // Return the index of the specified src operand in the parsed operands array.
708 unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
709 assert(CompSrcIdx < Component::MAX_SRC_NUM);
710 return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
711 }
712
713private:
714 unsigned getPrevCompSrcNum() const {
715 return PrevComp.getCompSrcOperandsNum();
716 }
717 unsigned getPrevCompParsedSrcNum() const {
718 return PrevComp.getCompParsedSrcOperandsNum();
719 }
720};
721
722// Layout and properties of VOPD components.
724public:
725 // Create ComponentInfo for COMPONENT_X or SINGLE component.
728 : ComponentLayout(Kind), ComponentProps(OpDesc) {}
729
730 // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
731 ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
732 : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
733
734 // Map component operand index to parsed operand index.
735 // Return 0 if the specified operand does not exist.
736 unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
737};
738
739// Properties of VOPD instructions.
740class InstInfo {
741private:
742 const ComponentInfo CompInfo[COMPONENTS_NUM];
743
744public:
745 using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
746
747 InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
748 : CompInfo{OpX, OpY} {}
749
750 InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
751 : CompInfo{OprInfoX, OprInfoY} {}
752
753 const ComponentInfo &operator[](size_t ComponentIdx) const {
754 assert(ComponentIdx < COMPONENTS_NUM);
755 return CompInfo[ComponentIdx];
756 }
757
758 // Check VOPD operands constraints.
759 // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
760 // for the specified component and MC operand. The callback must return 0
761 // if the operand is not a register or not a VGPR.
763 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
764 return getInvalidCompOperandIndex(GetRegIdx).has_value();
765 }
766
767 // Check VOPD operands constraints.
768 // Return the index of an invalid component operand, if any.
769 std::optional<unsigned> getInvalidCompOperandIndex(
770 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
771
772private:
774 getRegIndices(unsigned ComponentIdx,
775 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
776};
777
778} // namespace VOPD
779
781std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
782
784// Get properties of 2 single VOP1/VOP2 instructions
785// used as components to create a VOPD instruction.
786VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
787
789// Get properties of VOPD X and Y components.
790VOPD::InstInfo
791getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
792
794bool isTrue16Inst(unsigned Opc);
795
797unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
798
800unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
801
803 const MCSubtargetInfo *STI);
804
806 const MCSubtargetInfo *STI);
807
808bool isGroupSegment(const GlobalValue *GV);
809bool isGlobalSegment(const GlobalValue *GV);
810bool isReadOnlySegment(const GlobalValue *GV);
811
812/// \returns True if constants should be emitted to .text section for given
813/// target triple \p TT, false otherwise.
815
816/// \returns Integer value requested using \p F's \p Name attribute.
817///
818/// \returns \p Default if attribute is not present.
819///
820/// \returns \p Default and emits error if requested value cannot be converted
821/// to integer.
823
824/// \returns A pair of integer values requested using \p F's \p Name attribute
825/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
826/// is false).
827///
828/// \returns \p Default if attribute is not present.
829///
830/// \returns \p Default and emits error if one of the requested values cannot be
831/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
832/// not present.
833std::pair<unsigned, unsigned>
835 std::pair<unsigned, unsigned> Default,
836 bool OnlyFirstRequired = false);
837
838/// Represents the counter values to wait for in an s_waitcnt instruction.
839///
840/// Large values (including the maximum possible integer) can be used to
841/// represent "don't care" waits.
842struct Waitcnt {
843 unsigned VmCnt = ~0u;
844 unsigned ExpCnt = ~0u;
845 unsigned LgkmCnt = ~0u;
846 unsigned VsCnt = ~0u;
847
848 Waitcnt() = default;
849 Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
851
852 static Waitcnt allZero(bool HasVscnt) {
853 return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
854 }
855 static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
856
857 bool hasWait() const {
858 return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
859 }
860
861 bool hasWaitExceptVsCnt() const {
862 return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
863 }
864
865 bool hasWaitVsCnt() const {
866 return VsCnt != ~0u;
867 }
868
870 return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
871 std::min(LgkmCnt, Other.LgkmCnt),
872 std::min(VsCnt, Other.VsCnt));
873 }
874};
875
876/// \returns Vmcnt bit mask for given isa \p Version.
877unsigned getVmcntBitMask(const IsaVersion &Version);
878
879/// \returns Expcnt bit mask for given isa \p Version.
880unsigned getExpcntBitMask(const IsaVersion &Version);
881
882/// \returns Lgkmcnt bit mask for given isa \p Version.
883unsigned getLgkmcntBitMask(const IsaVersion &Version);
884
885/// \returns Waitcnt bit mask for given isa \p Version.
886unsigned getWaitcntBitMask(const IsaVersion &Version);
887
888/// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
889unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
890
891/// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
892unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
893
894/// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
895unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
896
897/// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
898/// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
899/// \p Lgkmcnt respectively.
900///
901/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
902/// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
903/// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
904/// \p Vmcnt = \p Waitcnt[15:10] (gfx11+)
905/// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
906/// \p Expcnt = \p Waitcnt[2:0] (gfx11+)
907/// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
908/// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
909/// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11+)
910void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
911 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
912
913Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
914
915/// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
916unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
917 unsigned Vmcnt);
918
919/// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
920unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
921 unsigned Expcnt);
922
923/// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
924unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
925 unsigned Lgkmcnt);
926
927/// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
928/// \p Version.
929///
930/// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
931/// Waitcnt[2:0] = \p Expcnt (gfx11+)
932/// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
933/// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
934/// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
935/// Waitcnt[9:4] = \p Lgkmcnt (gfx11+)
936/// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
937/// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
938/// Waitcnt[15:10] = \p Vmcnt (gfx11+)
939/// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
940///
941/// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
942/// isa \p Version.
943unsigned encodeWaitcnt(const IsaVersion &Version,
944 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
945
946unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
947
948namespace Hwreg {
949
951int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
952
954bool isValidHwreg(int64_t Id);
955
957bool isValidHwregOffset(int64_t Offset);
958
960bool isValidHwregWidth(int64_t Width);
961
964
966StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
967
968void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
969
970} // namespace Hwreg
971
972namespace DepCtr {
973
974int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
975int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
976 const MCSubtargetInfo &STI);
977bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
978 const MCSubtargetInfo &STI);
979bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
980 bool &IsDefault, const MCSubtargetInfo &STI);
981
982/// \returns Decoded VaVdst from given immediate \p Encoded.
983unsigned decodeFieldVaVdst(unsigned Encoded);
984
985/// \returns Decoded VmVsrc from given immediate \p Encoded.
986unsigned decodeFieldVmVsrc(unsigned Encoded);
987
988/// \returns Decoded SaSdst from given immediate \p Encoded.
989unsigned decodeFieldSaSdst(unsigned Encoded);
990
991/// \returns \p VmVsrc as an encoded Depctr immediate.
992unsigned encodeFieldVmVsrc(unsigned VmVsrc);
993
994/// \returns \p Encoded combined with encoded \p VmVsrc.
995unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc);
996
997/// \returns \p VaVdst as an encoded Depctr immediate.
998unsigned encodeFieldVaVdst(unsigned VaVdst);
999
1000/// \returns \p Encoded combined with encoded \p VaVdst.
1001unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst);
1002
1003/// \returns \p SaSdst as an encoded Depctr immediate.
1004unsigned encodeFieldSaSdst(unsigned SaSdst);
1005
1006/// \returns \p Encoded combined with encoded \p SaSdst.
1007unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst);
1008
1009} // namespace DepCtr
1010
1011namespace Exp {
1012
1013bool getTgtName(unsigned Id, StringRef &Name, int &Index);
1014
1016unsigned getTgtId(const StringRef Name);
1017
1019bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
1020
1021} // namespace Exp
1022
1023namespace MTBUFFormat {
1024
1026int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
1027
1028void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
1029
1030int64_t getDfmt(const StringRef Name);
1031
1032StringRef getDfmtName(unsigned Id);
1033
1034int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
1035
1036StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
1037
1038bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
1039
1040bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
1041
1042int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
1043
1044StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
1045
1046bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
1047
1048int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1049 const MCSubtargetInfo &STI);
1050
1051bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
1052
1053unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
1054
1055} // namespace MTBUFFormat
1056
1057namespace SendMsg {
1058
1060int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
1061
1063int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
1064
1066StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
1067
1069StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1070
1072bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1073
1075bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1076 bool Strict = true);
1077
1079bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1080 const MCSubtargetInfo &STI, bool Strict = true);
1081
1083bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1084
1086bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1087
1088void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1089 uint16_t &StreamId, const MCSubtargetInfo &STI);
1090
1093 uint64_t OpId,
1095
1096} // namespace SendMsg
1097
1098
1099unsigned getInitialPSInputAddr(const Function &F);
1100
1101bool getHasColorExport(const Function &F);
1102
1103bool getHasDepthExport(const Function &F);
1104
1107
1110
1113
1116
1117// These functions are considered entrypoints into the current module, i.e. they
1118// are allowed to be called from outside the current module. This is different
1119// from isEntryFunctionCC, which is only true for functions that are entered by
1120// the hardware. Module entry points include all entry functions but also
1121// include functions that can be called from other functions inside or outside
1122// the current module. Module entry functions are allowed to allocate LDS.
1125
1128
1129bool isKernelCC(const Function *Func);
1130
1131// FIXME: Remove this when calling conventions cleaned up
1134 switch (CC) {
1137 return true;
1138 default:
1139 return false;
1140 }
1141}
1142
1143bool hasXNACK(const MCSubtargetInfo &STI);
1144bool hasSRAMECC(const MCSubtargetInfo &STI);
1145bool hasMIMG_R128(const MCSubtargetInfo &STI);
1146bool hasA16(const MCSubtargetInfo &STI);
1147bool hasG16(const MCSubtargetInfo &STI);
1148bool hasPackedD16(const MCSubtargetInfo &STI);
1149bool hasGDS(const MCSubtargetInfo &STI);
1150unsigned getNSAMaxSize(const MCSubtargetInfo &STI);
1151unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI);
1152
1153bool isSI(const MCSubtargetInfo &STI);
1154bool isCI(const MCSubtargetInfo &STI);
1155bool isVI(const MCSubtargetInfo &STI);
1156bool isGFX9(const MCSubtargetInfo &STI);
1157bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1158bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1159bool isGFX8Plus(const MCSubtargetInfo &STI);
1160bool isGFX9Plus(const MCSubtargetInfo &STI);
1161bool isGFX10(const MCSubtargetInfo &STI);
1162bool isGFX10Plus(const MCSubtargetInfo &STI);
1163bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1164bool isGFX10Before1030(const MCSubtargetInfo &STI);
1165bool isGFX11(const MCSubtargetInfo &STI);
1166bool isGFX11Plus(const MCSubtargetInfo &STI);
1167bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1168bool isGCN3Encoding(const MCSubtargetInfo &STI);
1169bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1170bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1171bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1172bool isGFX90A(const MCSubtargetInfo &STI);
1173bool isGFX940(const MCSubtargetInfo &STI);
1175bool hasMAIInsts(const MCSubtargetInfo &STI);
1176bool hasVOPD(const MCSubtargetInfo &STI);
1177int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1178unsigned hasKernargPreload(const MCSubtargetInfo &STI);
1179
1180/// Is Reg - scalar register
1181bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1182
1183/// If \p Reg is a pseudo reg, return the correct hardware register given
1184/// \p STI otherwise return \p Reg.
1185unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1186
1187/// Convert hardware register \p Reg to a pseudo register
1189unsigned mc2PseudoReg(unsigned Reg);
1190
1192bool isInlineValue(unsigned Reg);
1193
1194/// Is this an AMDGPU specific source operand? These include registers,
1195/// inline constants, literals and mandatory literals (KImm).
1196bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1197
1198/// Is this a KImm operand?
1199bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo);
1200
1201/// Is this floating-point operand?
1202bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1203
1204/// Does this operand support only inlinable literals?
1205bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1206
1207/// Get the size in bits of a register from the register class \p RC.
1208unsigned getRegBitWidth(unsigned RCID);
1209
1210/// Get the size in bits of a register from the register class \p RC.
1211unsigned getRegBitWidth(const MCRegisterClass &RC);
1212
1213/// Get size of register operand
1214unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1215 unsigned OpNo);
1216
1218inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1219 switch (OpInfo.OperandType) {
1232 case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1233 return 4;
1234
1240 return 8;
1241
1255 return 2;
1256
1257 default:
1258 llvm_unreachable("unhandled operand type");
1259 }
1260}
1261
1263inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1264 return getOperandSize(Desc.operands()[OpNo]);
1265}
1266
1267/// Is this literal inlinable, and not one of the values intended for floating
1268/// point values.
1270inline bool isInlinableIntLiteral(int64_t Literal) {
1271 return Literal >= -16 && Literal <= 64;
1272}
1273
1274/// Is this literal inlinable
1276bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1277
1279bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1280
1282bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
1283
1285bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
1286
1289
1291bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
1292
1293bool isArgPassedInSGPR(const Argument *Arg);
1294
1295bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
1296
1299 int64_t EncodedOffset);
1300
1303 int64_t EncodedOffset,
1304 bool IsBuffer);
1305
1306/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1307/// offsets.
1309
1310/// \returns The encoding that will be used for \p ByteOffset in the
1311/// SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10
1312/// S_LOAD instructions have a signed offset, on other subtargets it is
1313/// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1314std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
1315 int64_t ByteOffset, bool IsBuffer);
1316
1317/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1318/// instruction. This is only useful on CI.s
1319std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
1320 int64_t ByteOffset);
1321
1322/// For FLAT segment the offset must be positive;
1323/// MSB is ignored and forced to zero.
1324///
1325/// \return The number of bits available for the signed offset field in flat
1326/// instructions. Note that some forms of the instruction disallow negative
1327/// offsets.
1328unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
1329
1330/// \returns true if this offset is small enough to fit in the SMRD
1331/// offset field. \p ByteOffset should be the offset in bytes and
1332/// not the encoded offset.
1333bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1334
1336inline bool isLegalDPALU_DPPControl(unsigned DC) {
1337 return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1338}
1339
1340/// \returns true if an instruction may have a 64-bit VGPR operand.
1341bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc);
1342
1343/// \returns true if an instruction is a DP ALU DPP.
1344bool isDPALU_DPP(const MCInstrDesc &OpDesc);
1345
1346/// \returns true if the intrinsic is divergent
1347bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1348
1349/// \returns true if the intrinsic is uniform
1350bool isIntrinsicAlwaysUniform(unsigned IntrID);
1351
1352} // end namespace AMDGPU
1353
1354raw_ostream &operator<<(raw_ostream &OS,
1356
1357} // end namespace llvm
1358
1359#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
unsigned const MachineRegisterInfo * MRI
#define LLVM_READNONE
Definition: Compiler.h:201
#define LLVM_READONLY
Definition: Compiler.h:208
uint64_t Align
std::string Name
#define F(x, y, z)
Definition: MD5.cpp:55
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
unsigned Reg
Module.h This file contains the declarations for the Module class.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
void setTargetIDFromFeaturesString(StringRef FS)
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
TargetIDSetting getXnackSetting() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
ComponentInfo(const MCInstrDesc &OpDesc, ComponentKind Kind=ComponentKind::SINGLE)
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const
unsigned getIndexOfDstInParsedOperands() const
ComponentLayout(const ComponentProps &OpXProps)
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
bool hasRegSrcOperand(unsigned CompSrcIdx) const
unsigned getMandatoryLiteralCompOperandIndex() const
unsigned getCompParsedSrcOperandsNum() const
InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
const ComponentInfo & operator[](size_t ComponentIdx) const
bool hasInvalidOperand(std::function< unsigned(unsigned, unsigned)> GetRegIdx) const
InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1190
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
This holds information about one operand of a machine instruction, indicating the register class for ...
Definition: MCInstrDesc.h:85
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:97
MCRegisterClass - Base class of TargetRegisterClass.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
bool isValidHwreg(int64_t Id)
bool isValidHwregOffset(int64_t Offset)
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
bool isValidHwregWidth(int64_t Width)
int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
constexpr unsigned COMPONENTS[]
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGG16MappingInfo * getMIMGG16MappingInfo(unsigned G)
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI)
int getVOPDFull(unsigned OpX, unsigned OpY)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
LLVM_READONLY const MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
bool isInlinableIntLiteralV216(int32_t Literal)
LLVM_READNONE bool isLegalDPALU_DPPControl(unsigned DC)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
int getMTBUFElements(unsigned Opc)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
CanBeVOPD getCanBeVOPD(unsigned Opc)
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getCodeObjectVersion(const Module &M)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
LLVM_READNONE bool isKernel(CallingConv::ID CC)
bool isGFX11(const MCSubtargetInfo &STI)
bool getSMEMIsBuffer(unsigned Opc)
bool isGroupSegment(const GlobalValue *GV)
LLVM_READONLY const MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
unsigned getAmdhsaCodeObjectVersion()
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
LLVM_READONLY const MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByAsmSuffix(StringRef AsmSuffix)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:214
@ OPERAND_REG_IMM_INT64
Definition: SIDefines.h:189
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:196
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:210
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:207
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:197
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:224
@ OPERAND_REG_IMM_INT32
Operands with register or 32-bit immediate.
Definition: SIDefines.h:188
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:193
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:202
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:218
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:192
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:209
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:223
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:220
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:219
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:221
@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:198
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:191
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:206
@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:203
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:208
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:199
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:205
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:190
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:211
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:195
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:194
LLVM_READONLY const MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
std::optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
bool getMUBUFIsBufferInv(unsigned Opc)
bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isMAC(unsigned Opc)
LLVM_READNONE unsigned getOperandSize(const MCOperandInfo &OpInfo)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
bool getVOP2IsSingle(unsigned Opc)
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
bool hasVOPD(const MCSubtargetInfo &STI)
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:197
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
@ Other
Any other memory.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:292
@ Default
The result values are uniform if and only if all operands are uniform.
AMD Kernel Code Object (amd_kernel_code_t).
Represents the counter values to wait for in an s_waitcnt instruction.
bool hasWaitExceptVsCnt() const
static Waitcnt allZero(bool HasVscnt)
static Waitcnt allZeroExceptVsCnt()
bool hasWaitVsCnt() const
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Waitcnt combined(const Waitcnt &Other) const
Description of the encoding of one expression Op.