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AMDGPUBaseInfo.h
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1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/ADT/Optional.h"
14 #include "llvm/IR/CallingConv.h"
15 #include "llvm/Support/Alignment.h"
16 #include <array>
17 #include <functional>
18 #include <utility>
19 
20 struct amd_kernel_code_t;
21 
22 namespace llvm {
23 
24 struct Align;
25 class Argument;
26 class Function;
27 class GCNSubtarget;
28 class GlobalValue;
29 class MCInstrInfo;
30 class MCRegisterClass;
31 class MCRegisterInfo;
32 class MCSubtargetInfo;
33 class StringRef;
34 class Triple;
35 
36 namespace amdhsa {
37 struct kernel_descriptor_t;
38 }
39 
40 namespace AMDGPU {
41 
42 struct IsaVersion;
43 
44 /// \returns HSA OS ABI Version identification.
45 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
46 /// \returns True if HSA OS ABI Version identification is 2,
47 /// false otherwise.
48 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
49 /// \returns True if HSA OS ABI Version identification is 3,
50 /// false otherwise.
51 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
52 /// \returns True if HSA OS ABI Version identification is 4,
53 /// false otherwise.
54 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
55 /// \returns True if HSA OS ABI Version identification is 5,
56 /// false otherwise.
57 bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
58 /// \returns True if HSA OS ABI Version identification is 3 and above,
59 /// false otherwise.
60 bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
61 
62 /// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
64 
65 /// \returns The offset of the hostcall pointer argument from implicitarg_ptr
67 
68 /// \returns Code object version.
70 
72  unsigned Format;
73  unsigned BitsPerComp;
74  unsigned NumComponents;
75  unsigned NumFormat;
76  unsigned DataFormat;
77 };
78 
79 struct MAIInstInfo {
81  bool is_dgemm;
83 };
84 
85 #define GET_MIMGBaseOpcode_DECL
86 #define GET_MIMGDim_DECL
87 #define GET_MIMGEncoding_DECL
88 #define GET_MIMGLZMapping_DECL
89 #define GET_MIMGMIPMapping_DECL
90 #define GET_MIMGBiASMapping_DECL
91 #define GET_MAIInstInfoTable_DECL
92 #include "AMDGPUGenSearchableTables.inc"
93 
94 namespace IsaInfo {
95 
96 enum {
97  // The closed Vulkan driver sets 96, which limits the wave count to 8 but
98  // doesn't spill SGPRs as much as when 80 is set.
101 };
102 
103 enum class TargetIDSetting {
104  Unsupported,
105  Any,
106  Off,
107  On
108 };
109 
111 private:
112  const MCSubtargetInfo &STI;
113  TargetIDSetting XnackSetting;
114  TargetIDSetting SramEccSetting;
115 
116 public:
117  explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
118  ~AMDGPUTargetID() = default;
119 
120  /// \return True if the current xnack setting is not "Unsupported".
121  bool isXnackSupported() const {
122  return XnackSetting != TargetIDSetting::Unsupported;
123  }
124 
125  /// \returns True if the current xnack setting is "On" or "Any".
126  bool isXnackOnOrAny() const {
127  return XnackSetting == TargetIDSetting::On ||
128  XnackSetting == TargetIDSetting::Any;
129  }
130 
131  /// \returns True if current xnack setting is "On" or "Off",
132  /// false otherwise.
133  bool isXnackOnOrOff() const {
134  return getXnackSetting() == TargetIDSetting::On ||
136  }
137 
138  /// \returns The current xnack TargetIDSetting, possible options are
139  /// "Unsupported", "Any", "Off", and "On".
141  return XnackSetting;
142  }
143 
144  /// Sets xnack setting to \p NewXnackSetting.
145  void setXnackSetting(TargetIDSetting NewXnackSetting) {
146  XnackSetting = NewXnackSetting;
147  }
148 
149  /// \return True if the current sramecc setting is not "Unsupported".
150  bool isSramEccSupported() const {
151  return SramEccSetting != TargetIDSetting::Unsupported;
152  }
153 
154  /// \returns True if the current sramecc setting is "On" or "Any".
155  bool isSramEccOnOrAny() const {
156  return SramEccSetting == TargetIDSetting::On ||
157  SramEccSetting == TargetIDSetting::Any;
158  }
159 
160  /// \returns True if current sramecc setting is "On" or "Off",
161  /// false otherwise.
162  bool isSramEccOnOrOff() const {
165  }
166 
167  /// \returns The current sramecc TargetIDSetting, possible options are
168  /// "Unsupported", "Any", "Off", and "On".
170  return SramEccSetting;
171  }
172 
173  /// Sets sramecc setting to \p NewSramEccSetting.
174  void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
175  SramEccSetting = NewSramEccSetting;
176  }
177 
180 
181  /// \returns String representation of an object.
182  std::string toString() const;
183 };
184 
185 /// \returns Wavefront size for given subtarget \p STI.
186 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
187 
188 /// \returns Local memory size in bytes for given subtarget \p STI.
189 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
190 
191 /// \returns Number of execution units per compute unit for given subtarget \p
192 /// STI.
193 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
194 
195 /// \returns Maximum number of work groups per compute unit for given subtarget
196 /// \p STI and limited by given \p FlatWorkGroupSize.
197 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
198  unsigned FlatWorkGroupSize);
199 
200 /// \returns Minimum number of waves per execution unit for given subtarget \p
201 /// STI.
202 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
203 
204 /// \returns Maximum number of waves per execution unit for given subtarget \p
205 /// STI without any kind of limitation.
206 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
207 
208 /// \returns Number of waves per execution unit required to support the given \p
209 /// FlatWorkGroupSize.
210 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
211  unsigned FlatWorkGroupSize);
212 
213 /// \returns Minimum flat work group size for given subtarget \p STI.
214 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
215 
216 /// \returns Maximum flat work group size for given subtarget \p STI.
217 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
218 
219 /// \returns Number of waves per work group for given subtarget \p STI and
220 /// \p FlatWorkGroupSize.
221 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
222  unsigned FlatWorkGroupSize);
223 
224 /// \returns SGPR allocation granularity for given subtarget \p STI.
225 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
226 
227 /// \returns SGPR encoding granularity for given subtarget \p STI.
228 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
229 
230 /// \returns Total number of SGPRs for given subtarget \p STI.
231 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
232 
233 /// \returns Addressable number of SGPRs for given subtarget \p STI.
234 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
235 
236 /// \returns Minimum number of SGPRs that meets the given number of waves per
237 /// execution unit requirement for given subtarget \p STI.
238 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
239 
240 /// \returns Maximum number of SGPRs that meets the given number of waves per
241 /// execution unit requirement for given subtarget \p STI.
242 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
243  bool Addressable);
244 
245 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
246 /// STI when the given special registers are used.
247 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
248  bool FlatScrUsed, bool XNACKUsed);
249 
250 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
251 /// STI when the given special registers are used. XNACK is inferred from
252 /// \p STI.
253 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
254  bool FlatScrUsed);
255 
256 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
257 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
258 /// register counts.
259 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
260 
261 /// \returns VGPR allocation granularity for given subtarget \p STI.
262 ///
263 /// For subtargets which support it, \p EnableWavefrontSize32 should match
264 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
265 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
266  Optional<bool> EnableWavefrontSize32 = None);
267 
268 /// \returns VGPR encoding granularity for given subtarget \p STI.
269 ///
270 /// For subtargets which support it, \p EnableWavefrontSize32 should match
271 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
272 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
273  Optional<bool> EnableWavefrontSize32 = None);
274 
275 /// \returns Total number of VGPRs for given subtarget \p STI.
276 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
277 
278 /// \returns Addressable number of VGPRs for given subtarget \p STI.
279 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
280 
281 /// \returns Minimum number of VGPRs that meets given number of waves per
282 /// execution unit requirement for given subtarget \p STI.
283 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
284 
285 /// \returns Maximum number of VGPRs that meets given number of waves per
286 /// execution unit requirement for given subtarget \p STI.
287 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
288 
289 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
290 /// \p NumVGPRs are used.
291 ///
292 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
293 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
294 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
295  Optional<bool> EnableWavefrontSize32 = None);
296 
297 } // end namespace IsaInfo
298 
300 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
301 
303 inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
304  return getNamedOperandIdx(Opcode, NamedIdx) != -1;
305 }
306 
308 int getSOPPWithRelaxation(uint16_t Opcode);
309 
311  MIMGBaseOpcode BaseOpcode;
312  bool Store;
313  bool Atomic;
314  bool AtomicX2;
315  bool Sampler;
316  bool Gather4;
317 
318  uint8_t NumExtraArgs;
319  bool Gradients;
320  bool G16;
323  bool HasD16;
324  bool MSAA;
325  bool BVH;
326 };
327 
329 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
330 
332 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
333 
334 struct MIMGDimInfo {
335  MIMGDim Dim;
336  uint8_t NumCoords;
337  uint8_t NumGradients;
338  bool MSAA;
339  bool DA;
340  uint8_t Encoding;
341  const char *AsmSuffix;
342 };
343 
345 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
346 
348 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
349 
352 
354  MIMGBaseOpcode L;
355  MIMGBaseOpcode LZ;
356 };
357 
359  MIMGBaseOpcode MIP;
360  MIMGBaseOpcode NONMIP;
361 };
362 
364  MIMGBaseOpcode Bias;
365  MIMGBaseOpcode NoBias;
366 };
367 
369  MIMGBaseOpcode Offset;
370  MIMGBaseOpcode NoOffset;
371 };
372 
374  MIMGBaseOpcode G;
375  MIMGBaseOpcode G16;
376 };
377 
379 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
380 
382  unsigned Opcode2Addr;
383  unsigned Opcode3Addr;
384 };
385 
387 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
388 
390 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
391 
393 const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
394 
397 
399 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
400  unsigned VDataDwords, unsigned VAddrDwords);
401 
403 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
404 
406 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
407  const MIMGDimInfo *Dim, bool IsA16,
408  bool IsG16Supported);
409 
410 struct MIMGInfo {
413  uint8_t MIMGEncoding;
414  uint8_t VDataDwords;
415  uint8_t VAddrDwords;
416  uint8_t VAddrOperands;
417 };
418 
420 const MIMGInfo *getMIMGInfo(unsigned Opc);
421 
423 int getMTBUFBaseOpcode(unsigned Opc);
424 
426 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
427 
429 int getMTBUFElements(unsigned Opc);
430 
432 bool getMTBUFHasVAddr(unsigned Opc);
433 
435 bool getMTBUFHasSrsrc(unsigned Opc);
436 
438 bool getMTBUFHasSoffset(unsigned Opc);
439 
441 int getMUBUFBaseOpcode(unsigned Opc);
442 
444 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
445 
447 int getMUBUFElements(unsigned Opc);
448 
450 bool getMUBUFHasVAddr(unsigned Opc);
451 
453 bool getMUBUFHasSrsrc(unsigned Opc);
454 
456 bool getMUBUFHasSoffset(unsigned Opc);
457 
459 bool getMUBUFIsBufferInv(unsigned Opc);
460 
462 bool getSMEMIsBuffer(unsigned Opc);
463 
465 bool getVOP1IsSingle(unsigned Opc);
466 
468 bool getVOP2IsSingle(unsigned Opc);
469 
471 bool getVOP3IsSingle(unsigned Opc);
472 
474 bool isVOPC64DPP(unsigned Opc);
475 
476 /// Returns true if MAI operation is a double precision GEMM.
478 bool getMAIIsDGEMM(unsigned Opc);
479 
481 bool getMAIIsGFX940XDL(unsigned Opc);
482 
483 struct CanBeVOPD {
484  bool X;
485  bool Y;
486 };
487 
489 CanBeVOPD getCanBeVOPD(unsigned Opc);
490 
492 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
493  uint8_t NumComponents,
494  uint8_t NumFormat,
495  const MCSubtargetInfo &STI);
497 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
498  const MCSubtargetInfo &STI);
499 
501 int getMCOpcode(uint16_t Opcode, unsigned Gen);
502 
504 unsigned getVOPDOpcode(unsigned Opc);
505 
507 int getVOPDFull(unsigned OpX, unsigned OpY);
508 
510 bool isVOPD(unsigned Opc);
511 
513 bool isMAC(unsigned Opc);
514 
516 bool isPermlane16(unsigned Opc);
517 
518 namespace VOPD {
519 
520 enum Component : unsigned {
521  DST = 0,
525 
526  DST_NUM = 1,
529 };
530 
531 // Number of VGPR banks per VOPD component operand.
532 constexpr unsigned BANKS_NUM[] = {2, 4, 4, 2};
533 
534 enum ComponentIndex : unsigned { X = 0, Y = 1 };
536 constexpr unsigned COMPONENTS_NUM = 2;
537 
538 // Properties of VOPD components.
540 private:
541  unsigned SrcOperandsNum = 0;
542  Optional<unsigned> MandatoryLiteralIdx;
543  bool HasSrc2Acc = false;
544 
545 public:
546  ComponentProps() = default;
547  ComponentProps(const MCInstrDesc &OpDesc);
548 
549  // Return the total number of src operands this component has.
550  unsigned getCompSrcOperandsNum() const { return SrcOperandsNum; }
551 
552  // Return the number of src operands of this component visible to the parser.
553  unsigned getCompParsedSrcOperandsNum() const {
554  return SrcOperandsNum - HasSrc2Acc;
555  }
556 
557  // Return true iif this component has a mandatory literal.
558  bool hasMandatoryLiteral() const { return MandatoryLiteralIdx.has_value(); }
559 
560  // If this component has a mandatory literal, return component operand
561  // index of this literal (i.e. either Component::SRC1 or Component::SRC2).
564  return *MandatoryLiteralIdx;
565  }
566 
567  // Return true iif this component has operand
568  // with component index CompSrcIdx and this operand may be a register.
569  bool hasRegSrcOperand(unsigned CompSrcIdx) const {
570  assert(CompSrcIdx < Component::MAX_SRC_NUM);
571  return SrcOperandsNum > CompSrcIdx && !hasMandatoryLiteralAt(CompSrcIdx);
572  }
573 
574  // Return true iif this component has tied src2.
575  bool hasSrc2Acc() const { return HasSrc2Acc; }
576 
577 private:
578  bool hasMandatoryLiteralAt(unsigned CompSrcIdx) const {
579  assert(CompSrcIdx < Component::MAX_SRC_NUM);
580  return hasMandatoryLiteral() &&
581  *MandatoryLiteralIdx == Component::DST_NUM + CompSrcIdx;
582  }
583 };
584 
585 enum ComponentKind : unsigned {
586  SINGLE = 0, // A single VOP1 or VOP2 instruction which may be used in VOPD.
587  COMPONENT_X, // A VOPD instruction, X component.
588  COMPONENT_Y, // A VOPD instruction, Y component.
590 };
591 
592 // Interface functions of this class map VOPD component operand indices
593 // to indices of operands in MachineInstr/MCInst or parsed operands array.
594 //
595 // Note that this class operates with 3 kinds of indices:
596 // - VOPD component operand indices (Component::DST, Component::SRC0, etc.);
597 // - MC operand indices (they refer operands in a MachineInstr/MCInst);
598 // - parsed operand indices (they refer operands in parsed operands array).
599 //
600 // For SINGLE components mapping between these indices is trivial.
601 // But things get more complicated for COMPONENT_X and
602 // COMPONENT_Y because these components share the same
603 // MachineInstr/MCInst and the same parsed operands array.
604 // Below is an example of component operand to parsed operand
605 // mapping for the following instruction:
606 //
607 // v_dual_add_f32 v255, v4, v5 :: v_dual_mov_b32 v6, v1
608 //
609 // PARSED COMPONENT PARSED
610 // COMPONENT OPERANDS OPERAND INDEX OPERAND INDEX
611 // -------------------------------------------------------------------
612 // "v_dual_add_f32" 0
613 // v_dual_add_f32 v255 0 (DST) --> 1
614 // v4 1 (SRC0) --> 2
615 // v5 2 (SRC1) --> 3
616 // "::" 4
617 // "v_dual_mov_b32" 5
618 // v_dual_mov_b32 v6 0 (DST) --> 6
619 // v1 1 (SRC0) --> 7
620 // -------------------------------------------------------------------
621 //
623 private:
624  // Regular MachineInstr/MCInst operands are ordered as follows:
625  // dst, src0 [, other src operands]
626  // VOPD MachineInstr/MCInst operands are ordered as follows:
627  // dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
628  // Each ComponentKind has operand indices defined below.
629  static constexpr unsigned MC_DST_IDX[] = {0, 0, 1};
630  static constexpr unsigned FIRST_MC_SRC_IDX[] = {1, 2, 2 /* + OpX.MCSrcNum */};
631 
632  // Parsed operands of regular instructions are ordered as follows:
633  // Mnemo dst src0 [vsrc1 ...]
634  // Parsed VOPD operands are ordered as follows:
635  // OpXMnemo dstX src0X [vsrc1X|imm vsrc1X|vsrc1X imm] '::'
636  // OpYMnemo dstY src0Y [vsrc1Y|imm vsrc1Y|vsrc1Y imm]
637  // Each ComponentKind has operand indices defined below.
638  static constexpr unsigned PARSED_DST_IDX[] = {1, 1,
639  4 /* + OpX.ParsedSrcNum */};
640  static constexpr unsigned FIRST_PARSED_SRC_IDX[] = {
641  2, 2, 5 /* + OpX.ParsedSrcNum */};
642 
643 private:
644  const ComponentKind Kind;
645  const ComponentProps PrevComp;
646 
647 public:
648  // Create layout for COMPONENT_X or SINGLE component.
649  ComponentLayout(ComponentKind Kind) : Kind(Kind) {
651  }
652 
653  // Create layout for COMPONENT_Y which depends on COMPONENT_X layout.
655  : Kind(ComponentKind::COMPONENT_Y), PrevComp(OpXProps) {}
656 
657 public:
658  // Return the index of dst operand in MCInst operands.
659  unsigned getIndexOfDstInMCOperands() const { return MC_DST_IDX[Kind]; }
660 
661  // Return the index of the specified src operand in MCInst operands.
662  unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const {
663  assert(CompSrcIdx < Component::MAX_SRC_NUM);
664  return FIRST_MC_SRC_IDX[Kind] + getPrevCompSrcNum() + CompSrcIdx;
665  }
666 
667  // Return the index of dst operand in the parsed operands array.
668  unsigned getIndexOfDstInParsedOperands() const {
669  return PARSED_DST_IDX[Kind] + getPrevCompParsedSrcNum();
670  }
671 
672  // Return the index of the specified src operand in the parsed operands array.
673  unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const {
674  assert(CompSrcIdx < Component::MAX_SRC_NUM);
675  return FIRST_PARSED_SRC_IDX[Kind] + getPrevCompParsedSrcNum() + CompSrcIdx;
676  }
677 
678 private:
679  unsigned getPrevCompSrcNum() const {
680  return PrevComp.getCompSrcOperandsNum();
681  }
682  unsigned getPrevCompParsedSrcNum() const {
683  return PrevComp.getCompParsedSrcOperandsNum();
684  }
685 };
686 
687 // Layout and properties of VOPD components.
689 public:
690  // Create ComponentInfo for COMPONENT_X or SINGLE component.
691  ComponentInfo(const MCInstrDesc &OpDesc,
693  : ComponentLayout(Kind), ComponentProps(OpDesc) {}
694 
695  // Create ComponentInfo for COMPONENT_Y which depends on COMPONENT_X layout.
696  ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
697  : ComponentLayout(OpXProps), ComponentProps(OpDesc) {}
698 
699  // Map component operand index to parsed operand index.
700  // Return 0 if the specified operand does not exist.
701  unsigned getIndexInParsedOperands(unsigned CompOprIdx) const;
702 };
703 
704 // Properties of VOPD instructions.
705 class InstInfo {
706 private:
707  const ComponentInfo CompInfo[COMPONENTS_NUM];
708 
709 public:
710  using RegIndices = std::array<unsigned, Component::MAX_OPR_NUM>;
711 
712  InstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
713  : CompInfo{OpX, OpY} {}
714 
715  InstInfo(const ComponentInfo &OprInfoX, const ComponentInfo &OprInfoY)
716  : CompInfo{OprInfoX, OprInfoY} {}
717 
718  const ComponentInfo &operator[](size_t ComponentIdx) const {
719  assert(ComponentIdx < COMPONENTS_NUM);
720  return CompInfo[ComponentIdx];
721  }
722 
723  // Check VOPD operands constraints.
724  // GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
725  // for the specified component and MC operand. The callback must return 0
726  // if the operand is not a register or not a VGPR.
728  std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
729  return getInvalidCompOperandIndex(GetRegIdx).has_value();
730  }
731 
732  // Check VOPD operands constraints.
733  // Return the index of an invalid component operand, if any.
735  std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
736 
737 private:
738  RegIndices
739  getRegIndices(unsigned ComponentIdx,
740  std::function<unsigned(unsigned, unsigned)> GetRegIdx) const;
741 };
742 
743 } // namespace VOPD
744 
746 std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode);
747 
749 // Get properties of 2 single VOP1/VOP2 instructions
750 // used as components to create a VOPD instruction.
751 VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY);
752 
754 // Get properties of VOPD X and Y components.
755 VOPD::InstInfo
756 getVOPDInstInfo(unsigned VOPDOpcode, const MCInstrInfo *InstrInfo);
757 
759 bool isTrue16Inst(unsigned Opc);
760 
762 unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc);
763 
765 unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc);
766 
768  const MCSubtargetInfo *STI);
769 
771  const MCSubtargetInfo *STI);
772 
773 bool isGroupSegment(const GlobalValue *GV);
774 bool isGlobalSegment(const GlobalValue *GV);
775 bool isReadOnlySegment(const GlobalValue *GV);
776 
777 /// \returns True if constants should be emitted to .text section for given
778 /// target triple \p TT, false otherwise.
780 
781 /// \returns Integer value requested using \p F's \p Name attribute.
782 ///
783 /// \returns \p Default if attribute is not present.
784 ///
785 /// \returns \p Default and emits error if requested value cannot be converted
786 /// to integer.
787 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
788 
789 /// \returns A pair of integer values requested using \p F's \p Name attribute
790 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
791 /// is false).
792 ///
793 /// \returns \p Default if attribute is not present.
794 ///
795 /// \returns \p Default and emits error if one of the requested values cannot be
796 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
797 /// not present.
798 std::pair<int, int> getIntegerPairAttribute(const Function &F,
799  StringRef Name,
800  std::pair<int, int> Default,
801  bool OnlyFirstRequired = false);
802 
803 /// Represents the counter values to wait for in an s_waitcnt instruction.
804 ///
805 /// Large values (including the maximum possible integer) can be used to
806 /// represent "don't care" waits.
807 struct Waitcnt {
808  unsigned VmCnt = ~0u;
809  unsigned ExpCnt = ~0u;
810  unsigned LgkmCnt = ~0u;
811  unsigned VsCnt = ~0u;
812 
813  Waitcnt() = default;
814  Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
816 
817  static Waitcnt allZero(bool HasVscnt) {
818  return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
819  }
820  static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
821 
822  bool hasWait() const {
823  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
824  }
825 
826  bool hasWaitExceptVsCnt() const {
827  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
828  }
829 
830  bool hasWaitVsCnt() const {
831  return VsCnt != ~0u;
832  }
833 
834  bool dominates(const Waitcnt &Other) const {
835  return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
836  LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
837  }
838 
839  Waitcnt combined(const Waitcnt &Other) const {
840  return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
841  std::min(LgkmCnt, Other.LgkmCnt),
842  std::min(VsCnt, Other.VsCnt));
843  }
844 };
845 
846 /// \returns Vmcnt bit mask for given isa \p Version.
847 unsigned getVmcntBitMask(const IsaVersion &Version);
848 
849 /// \returns Expcnt bit mask for given isa \p Version.
850 unsigned getExpcntBitMask(const IsaVersion &Version);
851 
852 /// \returns Lgkmcnt bit mask for given isa \p Version.
853 unsigned getLgkmcntBitMask(const IsaVersion &Version);
854 
855 /// \returns Waitcnt bit mask for given isa \p Version.
856 unsigned getWaitcntBitMask(const IsaVersion &Version);
857 
858 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
859 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
860 
861 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
862 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
863 
864 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
865 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
866 
867 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
868 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
869 /// \p Lgkmcnt respectively.
870 ///
871 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
872 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
873 /// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
874 /// \p Vmcnt = \p Waitcnt[15:10] (gfx11+)
875 /// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
876 /// \p Expcnt = \p Waitcnt[2:0] (gfx11+)
877 /// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
878 /// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
879 /// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11+)
880 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
881  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
882 
883 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
884 
885 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
886 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
887  unsigned Vmcnt);
888 
889 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
890 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
891  unsigned Expcnt);
892 
893 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
894 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
895  unsigned Lgkmcnt);
896 
897 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
898 /// \p Version.
899 ///
900 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
901 /// Waitcnt[2:0] = \p Expcnt (gfx11+)
902 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
903 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
904 /// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
905 /// Waitcnt[9:4] = \p Lgkmcnt (gfx11+)
906 /// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
907 /// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
908 /// Waitcnt[15:10] = \p Vmcnt (gfx11+)
909 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
910 ///
911 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
912 /// isa \p Version.
913 unsigned encodeWaitcnt(const IsaVersion &Version,
914  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
915 
916 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
917 
918 namespace Hwreg {
919 
921 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
922 
924 bool isValidHwreg(int64_t Id);
925 
927 bool isValidHwregOffset(int64_t Offset);
928 
930 bool isValidHwregWidth(int64_t Width);
931 
934 
936 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
937 
938 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
939 
940 } // namespace Hwreg
941 
942 namespace DepCtr {
943 
944 int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
945 int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
946  const MCSubtargetInfo &STI);
947 bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
948  const MCSubtargetInfo &STI);
949 bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
950  bool &IsDefault, const MCSubtargetInfo &STI);
951 
952 } // namespace DepCtr
953 
954 namespace Exp {
955 
956 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
957 
959 unsigned getTgtId(const StringRef Name);
960 
962 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
963 
964 } // namespace Exp
965 
966 namespace MTBUFFormat {
967 
969 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
970 
971 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
972 
973 int64_t getDfmt(const StringRef Name);
974 
975 StringRef getDfmtName(unsigned Id);
976 
977 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
978 
979 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
980 
981 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
982 
983 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
984 
985 int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
986 
987 StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
988 
989 bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
990 
991 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
992  const MCSubtargetInfo &STI);
993 
994 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
995 
996 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
997 
998 } // namespace MTBUFFormat
999 
1000 namespace SendMsg {
1001 
1003 int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
1004 
1006 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
1007 
1009 StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
1010 
1012 StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1013 
1015 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
1016 
1018 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1019  bool Strict = true);
1020 
1022 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1023  const MCSubtargetInfo &STI, bool Strict = true);
1024 
1026 bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
1027 
1029 bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
1030 
1031 void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1032  uint16_t &StreamId, const MCSubtargetInfo &STI);
1033 
1036  uint64_t OpId,
1037  uint64_t StreamId);
1038 
1039 } // namespace SendMsg
1040 
1041 
1042 unsigned getInitialPSInputAddr(const Function &F);
1043 
1044 bool getHasColorExport(const Function &F);
1045 
1046 bool getHasDepthExport(const Function &F);
1047 
1050 
1053 
1056 
1059 
1060 // These functions are considered entrypoints into the current module, i.e. they
1061 // are allowed to be called from outside the current module. This is different
1062 // from isEntryFunctionCC, which is only true for functions that are entered by
1063 // the hardware. Module entry points include all entry functions but also
1064 // include functions that can be called from other functions inside or outside
1065 // the current module. Module entry functions are allowed to allocate LDS.
1068 
1069 bool isKernelCC(const Function *Func);
1070 
1071 // FIXME: Remove this when calling conventions cleaned up
1074  switch (CC) {
1077  return true;
1078  default:
1079  return false;
1080  }
1081 }
1082 
1083 bool hasXNACK(const MCSubtargetInfo &STI);
1084 bool hasSRAMECC(const MCSubtargetInfo &STI);
1085 bool hasMIMG_R128(const MCSubtargetInfo &STI);
1086 bool hasGFX10A16(const MCSubtargetInfo &STI);
1087 bool hasG16(const MCSubtargetInfo &STI);
1088 bool hasPackedD16(const MCSubtargetInfo &STI);
1089 
1090 bool isSI(const MCSubtargetInfo &STI);
1091 bool isCI(const MCSubtargetInfo &STI);
1092 bool isVI(const MCSubtargetInfo &STI);
1093 bool isGFX9(const MCSubtargetInfo &STI);
1094 bool isGFX9_GFX10(const MCSubtargetInfo &STI);
1095 bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
1096 bool isGFX8Plus(const MCSubtargetInfo &STI);
1097 bool isGFX9Plus(const MCSubtargetInfo &STI);
1098 bool isGFX10(const MCSubtargetInfo &STI);
1099 bool isGFX10Plus(const MCSubtargetInfo &STI);
1100 bool isNotGFX10Plus(const MCSubtargetInfo &STI);
1101 bool isGFX10Before1030(const MCSubtargetInfo &STI);
1102 bool isGFX11(const MCSubtargetInfo &STI);
1103 bool isGFX11Plus(const MCSubtargetInfo &STI);
1104 bool isNotGFX11Plus(const MCSubtargetInfo &STI);
1105 bool isGCN3Encoding(const MCSubtargetInfo &STI);
1106 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
1107 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
1108 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
1109 bool isGFX90A(const MCSubtargetInfo &STI);
1110 bool isGFX940(const MCSubtargetInfo &STI);
1112 bool hasMAIInsts(const MCSubtargetInfo &STI);
1113 bool hasVOPD(const MCSubtargetInfo &STI);
1114 int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
1115 
1116 /// Is Reg - scalar register
1117 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
1118 
1119 /// If \p Reg is a pseudo reg, return the correct hardware register given
1120 /// \p STI otherwise return \p Reg.
1121 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
1122 
1123 /// Convert hardware register \p Reg to a pseudo register
1125 unsigned mc2PseudoReg(unsigned Reg);
1126 
1127 /// Can this operand also contain immediate values?
1128 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
1129 
1130 /// Is this floating-point operand?
1131 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
1132 
1133 /// Does this operand support only inlinable literals?
1134 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
1135 
1136 /// Get the size in bits of a register from the register class \p RC.
1137 unsigned getRegBitWidth(unsigned RCID);
1138 
1139 /// Get the size in bits of a register from the register class \p RC.
1140 unsigned getRegBitWidth(const MCRegisterClass &RC);
1141 
1142 /// Get size of register operand
1143 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
1144  unsigned OpNo);
1145 
1147 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
1148  switch (OpInfo.OperandType) {
1161  case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
1162  return 4;
1163 
1169  return 8;
1170 
1184  return 2;
1185 
1186  default:
1187  llvm_unreachable("unhandled operand type");
1188  }
1189 }
1190 
1192 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
1193  return getOperandSize(Desc.OpInfo[OpNo]);
1194 }
1195 
1196 /// Is this literal inlinable, and not one of the values intended for floating
1197 /// point values.
1199 inline bool isInlinableIntLiteral(int64_t Literal) {
1200  return Literal >= -16 && Literal <= 64;
1201 }
1202 
1203 /// Is this literal inlinable
1205 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
1206 
1208 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
1209 
1211 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
1212 
1214 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
1215 
1217 bool isInlinableIntLiteralV216(int32_t Literal);
1218 
1220 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
1221 
1222 bool isArgPassedInSGPR(const Argument *Arg);
1223 
1226  int64_t EncodedOffset);
1227 
1230  int64_t EncodedOffset,
1231  bool IsBuffer);
1232 
1233 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
1234 /// offsets.
1236 
1237 /// \returns The encoding that will be used for \p ByteOffset in the
1238 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
1239 /// S_LOAD instructions have a signed offset, on other subtargets it is
1240 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
1242  int64_t ByteOffset, bool IsBuffer);
1243 
1244 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
1245 /// instruction. This is only useful on CI.s
1247  int64_t ByteOffset);
1248 
1249 /// For FLAT segment the offset must be positive;
1250 /// MSB is ignored and forced to zero.
1251 ///
1252 /// \return The number of bits available for the offset field in flat
1253 /// instructions.
1254 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
1255 
1256 /// \returns true if this offset is small enough to fit in the SMRD
1257 /// offset field. \p ByteOffset should be the offset in bytes and
1258 /// not the encoded offset.
1259 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
1260 
1261 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
1262  const GCNSubtarget *Subtarget,
1263  Align Alignment = Align(4));
1264 
1266 inline bool isLegal64BitDPPControl(unsigned DC) {
1267  return DC >= DPP::ROW_NEWBCAST_FIRST && DC <= DPP::ROW_NEWBCAST_LAST;
1268 }
1269 
1270 /// \returns true if the intrinsic is divergent
1271 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
1272 
1273 // Track defaults for fields in the MODE register.
1275  /// Floating point opcodes that support exception flag gathering quiet and
1276  /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
1277  /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
1278  /// quieting.
1279  bool IEEE : 1;
1280 
1281  /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
1282  /// clamp NaN to zero; otherwise, pass NaN through.
1283  bool DX10Clamp : 1;
1284 
1285  /// If this is set, neither input or output denormals are flushed for most f32
1286  /// instructions.
1289 
1290  /// If this is set, neither input or output denormals are flushed for both f64
1291  /// and f16/v2f16 instructions.
1294 
1296  IEEE(true),
1297  DX10Clamp(true),
1302 
1304 
1307  Mode.IEEE = !AMDGPU::isShader(CC);
1308  return Mode;
1309  }
1310 
1311  bool operator ==(const SIModeRegisterDefaults Other) const {
1312  return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
1313  FP32InputDenormals == Other.FP32InputDenormals &&
1314  FP32OutputDenormals == Other.FP32OutputDenormals &&
1315  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
1316  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
1317  }
1318 
1319  bool allFP32Denormals() const {
1321  }
1322 
1323  bool allFP64FP16Denormals() const {
1325  }
1326 
1327  /// Get the encoding value for the FP_DENORM bits of the mode register for the
1328  /// FP32 denormal mode.
1331  return FP_DENORM_FLUSH_NONE;
1332  if (FP32InputDenormals)
1333  return FP_DENORM_FLUSH_OUT;
1334  if (FP32OutputDenormals)
1335  return FP_DENORM_FLUSH_IN;
1337  }
1338 
1339  /// Get the encoding value for the FP_DENORM bits of the mode register for the
1340  /// FP64/FP16 denormal mode.
1343  return FP_DENORM_FLUSH_NONE;
1345  return FP_DENORM_FLUSH_OUT;
1347  return FP_DENORM_FLUSH_IN;
1349  }
1350 
1351  /// Returns true if a flag is compatible if it's enabled in the callee, but
1352  /// disabled in the caller.
1353  static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1354  return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1355  }
1356 
1357  // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1358  // be able to override.
1360  if (DX10Clamp != CalleeMode.DX10Clamp)
1361  return false;
1362  if (IEEE != CalleeMode.IEEE)
1363  return false;
1364 
1365  // Allow inlining denormals enabled into denormals flushed functions.
1370  }
1371 };
1372 
1373 } // end namespace AMDGPU
1374 
1375 raw_ostream &operator<<(raw_ostream &OS,
1377 
1378 } // end namespace llvm
1379 
1380 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:173
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1641
llvm::AMDGPU::Hwreg::encodeHwreg
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:1465
FP_DENORM_FLUSH_OUT
#define FP_DENORM_FLUSH_OUT
Definition: SIDefines.h:1025
llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:470
llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeDPValue
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
Definition: AMDGPUBaseInfo.h:1341
llvm::AMDGPU::getMUBUFIsBufferInv
bool getMUBUFIsBufferInv(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:381
llvm::AMDGPU::VOPD::COMPONENTS_NUM
constexpr unsigned COMPONENTS_NUM
Definition: AMDGPUBaseInfo.h:536
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:2053
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:126
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::AMDGPUTargetID
AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:601
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:2069
llvm::AMDGPU::VOPD::ComponentLayout::getIndexOfSrcInMCOperands
unsigned getIndexOfSrcInMCOperands(unsigned CompSrcIdx) const
Definition: AMDGPUBaseInfo.h:662
llvm::AMDGPU::VOPD::SINGLE
@ SINGLE
Definition: AMDGPUBaseInfo.h:586
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4715
LLVM_READONLY
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Definition: SIDefines.h:168
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Definition: Triple.h:44
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Definition: AMDGPUBaseInfo.h:523
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Definition: X86.h:200
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Definition: AMDGPUBaseInfo.h:589
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Definition: AMDGPUBaseInfo.h:534
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Definition: SIDefines.h:157
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Definition: AMDGPUBaseInfo.h:534
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Definition: SIDefines.h:169
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Get size of register operand.
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Definition: AMDGPUBaseInfo.h:310
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Definition: AMDGPUBaseInfo.h:374
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@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:186
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Definition: AMDGPUBaseInfo.h:705
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Is Reg - scalar register.
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Definition: AMDGPUBaseInfo.cpp:1974
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Definition: SIDefines.h:385
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Definition: AMDGPUBaseInfo.h:75
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Definition: AMDGPUBaseInfo.cpp:585
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Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
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Definition: AMDGPUBaseInfo.h:353
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@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:158
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Definition: SIDefines.h:1024
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Definition: AMDGPUBaseInfo.cpp:346
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Definition: AMDGPUBaseInfo.h:811
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Definition: APFixedPoint.h:291
llvm::AMDGPU::decodeWaitcnt
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Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:1223
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Definition: AMDGPUBaseInfo.h:834
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Definition: SIDefines.h:165
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Definition: AMDGPUBaseInfo.cpp:857
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Definition: AMDGPUBaseInfo.h:169
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Definition: InstrProf.h:1056
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Definition: AMDGPUBaseInfo.h:324
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Definition: AMDGPUBaseInfo.cpp:2430
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Definition: AMDGPUBaseInfo.cpp:815
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Definition: AMDGPUBaseInfo.h:688
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Definition: AMDGPUBaseInfo.cpp:806
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This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
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Definition: AMDGPUBaseInfo.cpp:1890
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Definition: SIDefines.h:371
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LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
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Definition: AMDGPUBaseInfo.cpp:1922
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Definition: AMDGPUBaseInfo.cpp:1831
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Definition: AMDGPUBaseInfo.cpp:1662
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Definition: AMDGPUBaseInfo.cpp:120
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@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:100
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Definition: AMDGPUBaseInfo.h:588
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Definition: AMDGPUBaseInfo.h:526
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@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:160
G
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Definition: AMDGPUBaseInfo.cpp:2124
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Definition: AMDGPUBaseInfo.cpp:1185
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Definition: AMDGPUBaseInfo.h:712
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Definition: GlobalValue.h:44
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Definition: AMDGPUBaseInfo.cpp:153
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Definition: AMDGPUBaseInfo.cpp:132
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Definition: AMDGPUBaseInfo.cpp:903
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Definition: AMDGPUBaseInfo.h:1199
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bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1877
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Definition: SIDefines.h:416
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:170
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Definition: ELFObjHandler.cpp:83
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Definition: AMDGPUBaseInfo.cpp:406
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@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:172
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bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1898
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Definition: AMDGPUBaseInfo.h:82
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MIMGBaseOpcode L
Definition: AMDGPUBaseInfo.h:354
llvm::AMDGPU::SIModeRegisterDefaults::allFP64FP16Denormals
bool allFP64FP16Denormals() const
Definition: AMDGPUBaseInfo.h:1323
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uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::AMDGPU::initDefaultAMDKernelCodeT
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:1051
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Waitcnt combined(const Waitcnt &Other) const
Definition: AMDGPUBaseInfo.h:839
llvm::AMDGPU::getIntegerAttribute
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
Definition: AMDGPUBaseInfo.cpp:1139
llvm::AMDGPU::Waitcnt::hasWaitExceptVsCnt
bool hasWaitExceptVsCnt() const
Definition: AMDGPUBaseInfo.h:826
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrOff
bool isSramEccOnOrOff() const
Definition: AMDGPUBaseInfo.h:162
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@ COMPONENT_X
Definition: AMDGPUBaseInfo.h:587
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unsigned BitsPerComp
Definition: AMDGPUBaseInfo.h:73
FP_DENORM_FLUSH_NONE
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:1027
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const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2571
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unsigned Opcode3Addr
Definition: AMDGPUBaseInfo.h:383
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Definition: AMDGPUBaseInfo.h:358
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unsigned getWavefrontSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:797
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bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:2115
llvm::AMDGPU::Hwreg::isValidHwregOffset
bool isValidHwregOffset(int64_t Offset)
Definition: AMDGPUBaseInfo.cpp:1457
llvm::AMDGPU::VOPD::ComponentProps::hasMandatoryLiteral
bool hasMandatoryLiteral() const
Definition: AMDGPUBaseInfo.h:558
llvm::AMDGPU::isMAC
bool isMAC(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:437
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:1283
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Definition: AMDGPUBaseInfo.h:483
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AMDGPU::encodeVmcnt
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
Definition: AMDGPUBaseInfo.cpp:1238
llvm::AMDGPU::VOPD::ComponentInfo::ComponentInfo
ComponentInfo(const MCInstrDesc &OpDesc, ComponentKind Kind=ComponentKind::SINGLE)
Definition: AMDGPUBaseInfo.h:691
llvm::AMDGPU::MIMGOffsetMappingInfo
Definition: AMDGPUBaseInfo.h:368
llvm::AMDGPU::getAddrSizeMIMGOp
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:215
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:99
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getXnackSetting
TargetIDSetting getXnackSetting() const
Definition: AMDGPUBaseInfo.h:140
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:1292
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bool isGFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1902
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:184
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::AMDGPU::VOPD::ComponentProps::getMandatoryLiteralCompOperandIndex
unsigned getMandatoryLiteralCompOperandIndex() const
Definition: AMDGPUBaseInfo.h:562
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:264
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::AMDGPU::WMMAOpcodeMappingInfo::Opcode2Addr
unsigned Opcode2Addr
Definition: AMDGPUBaseInfo.h:382
llvm::AMDGPU::Waitcnt::LgkmCnt
unsigned LgkmCnt
Definition: AMDGPUBaseInfo.h:810
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1540
llvm::AMDGPU::IsaInfo::getTotalNumSGPRs
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:884
llvm::AMDGPU::VOPD::MAX_OPR_NUM
@ MAX_OPR_NUM
Definition: AMDGPUBaseInfo.h:528
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::isGFX10Before1030
bool isGFX10Before1030(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1942
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:174
llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:891
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:161
llvm::AMDGPU::VOPD::ComponentInfo::ComponentInfo
ComponentInfo(const MCInstrDesc &OpDesc, const ComponentProps &OpXProps)
Definition: AMDGPUBaseInfo.h:696
llvm::AMDGPU::MIMGBaseOpcodeInfo::AtomicX2
bool AtomicX2
Definition: AMDGPUBaseInfo.h:314
llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1645
llvm::AMDGPU::IsaInfo::getNumSGPRBlocks
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
Definition: AMDGPUBaseInfo.cpp:968
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:187
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MIMGInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.h:412
llvm::AMDGPU::isInlinableLiteral16
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2319
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:156
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::getMIMGMIPMappingInfo
const LLVM_READONLY MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:185
llvm::AMDGPU::isHsaAbiVersion5
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:138
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::AMDGPU::WMMAOpcodeMappingInfo
Definition: AMDGPUBaseInfo.h:381
llvm::AMDGPU::isNotGFX10Plus
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1938
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1689
llvm::AMDGPU::MAIInstInfo::is_dgemm
bool is_dgemm
Definition: AMDGPUBaseInfo.h:81
llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1422
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
llvm::AMDGPU::MIMGLZMappingInfo::LZ
MIMGBaseOpcode LZ
Definition: AMDGPUBaseInfo.h:355
llvm::AMDGPU::Waitcnt::hasWait
bool hasWait() const
Definition: AMDGPUBaseInfo.h:822
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bool getVOP3IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:401
llvm::AMDGPU::isModuleEntryFunctionCC
bool isModuleEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1848
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AMDGPU::isCompute
bool isCompute(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1827
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:992
uint32_t
llvm::AMDGPU::getMIMGBiasMappingInfo
const LLVM_READONLY MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
llvm::AMDGPU::IsaInfo::getNumVGPRBlocks
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:1041
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates
bool Coordinates
Definition: AMDGPUBaseInfo.h:321
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
Definition: AMDGPUBaseInfo.cpp:2412
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bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:2079
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::AMDGPU::Waitcnt::hasWaitVsCnt
bool hasWaitVsCnt() const
Definition: AMDGPUBaseInfo.h:830
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1823
llvm::Optional::has_value
constexpr bool has_value() const
Definition: Optional.h:285
amd_kernel_code_t
AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:121
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:861
llvm::AMDGPU::Exp::getTgtName
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1506
llvm::AMDGPU::Waitcnt::VmCnt
unsigned VmCnt
Definition: AMDGPUBaseInfo.h:808
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:336
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::AMDGPU::VOPD::ComponentProps::getCompParsedSrcOperandsNum
unsigned getCompParsedSrcOperandsNum() const
Definition: AMDGPUBaseInfo.h:553
llvm::AMDGPU::VOPD::COMPONENTS
constexpr unsigned COMPONENTS[]
Definition: AMDGPUBaseInfo.h:535
llvm::AMDGPU::MIMGBaseOpcodeInfo::BaseOpcode
MIMGBaseOpcode BaseOpcode
Definition: AMDGPUBaseInfo.h:311
llvm::AMDGPU::GcnBufferFormatInfo
Definition: AMDGPUBaseInfo.h:71
llvm::AMDGPU::isGFX8_GFX9_GFX10
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1906
llvm::AMDGPU::GcnBufferFormatInfo::Format
unsigned Format
Definition: AMDGPUBaseInfo.h:72
llvm::AMDGPU::MTBUFFormat::getUnifiedFormat
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1620
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1914
llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:1087
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:1293
llvm::AMDGPU::isGroupSegment
bool isGroupSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:1121
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:201
llvm::AMDGPU::Waitcnt::Waitcnt
Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
Definition: AMDGPUBaseInfo.h:814
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setSramEccSetting
void setSramEccSetting(TargetIDSetting NewSramEccSetting)
Sets sramecc setting to NewSramEccSetting.
Definition: AMDGPUBaseInfo.h:174
CallingConv.h
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:1259
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1710
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1886
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:188
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString
std::string toString() const
Definition: AMDGPUBaseInfo.cpp:690
LLVM_READNONE
#define LLVM_READNONE
Definition: Compiler.h:189
Alignment.h
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:2377
llvm::AMDGPU::Waitcnt
Represents the counter values to wait for in an s_waitcnt instruction.
Definition: AMDGPUBaseInfo.h:807
llvm::AMDGPU::OPERAND_KIMM32
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:180
llvm::AMDGPU::SendMsg::decodeMsg
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1769
llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults
SIModeRegisterDefaults()
Definition: AMDGPUBaseInfo.h:1295
llvm::AMDGPU::getMUBUFHasVAddr
bool getMUBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:366
llvm::AMDGPU::isInlinableLiteral64
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:2276
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:163
llvm::AMDGPU::VOPD::SRC0
@ SRC0
Definition: AMDGPUBaseInfo.h:522
uint16_t
llvm::AMDGPU::VOPD::MAX_SRC_NUM
@ MAX_SRC_NUM
Definition: AMDGPUBaseInfo.h:527
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:361
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1698
SIDefines.h
llvm::AMDGPU::MIMGBaseOpcodeInfo::Atomic
bool Atomic
Definition: AMDGPUBaseInfo.h:313
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2364
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrOff
bool isXnackOnOrOff() const
Definition: AMDGPUBaseInfo.h:133
llvm::AMDGPU::isPermlane16
bool isPermlane16(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:458
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:175
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:411
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:170
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:391
llvm::AMDGPU::getVOPDOpcode
unsigned getVOPDOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:428
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:2480
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:410
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1615
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1517
llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:475
llvm::AMDGPU::getTotalNumVGPRs
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
Definition: AMDGPUBaseInfo.cpp:1982
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:177
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:1015
llvm::AMDGPU::VOPD::DST
@ DST
Definition: AMDGPUBaseInfo.h:521
llvm::AMDGPU::SendMsg::isValidMsgStream
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1736
llvm::AMDGPU::MTBUFFormat::getNfmtName
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1595
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:433
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1189
llvm::AMDGPU::isLegalSMRDImmOffset
bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset)
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
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