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AMDGPUBaseInfo.h
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1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
10 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 
12 #include "SIDefines.h"
13 #include "llvm/IR/CallingConv.h"
14 #include "llvm/Support/Alignment.h"
15 
16 struct amd_kernel_code_t;
17 
18 namespace llvm {
19 
20 struct Align;
21 class Argument;
22 class Function;
23 class GCNSubtarget;
24 class GlobalValue;
25 class MCRegisterClass;
26 class MCRegisterInfo;
27 class MCSubtargetInfo;
28 class StringRef;
29 class Triple;
30 
31 namespace amdhsa {
32 struct kernel_descriptor_t;
33 }
34 
35 namespace AMDGPU {
36 
37 struct IsaVersion;
38 
39 /// \returns HSA OS ABI Version identification.
40 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
41 /// \returns True if HSA OS ABI Version identification is 2,
42 /// false otherwise.
43 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
44 /// \returns True if HSA OS ABI Version identification is 3,
45 /// false otherwise.
46 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
47 /// \returns True if HSA OS ABI Version identification is 4,
48 /// false otherwise.
49 bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
50 /// \returns True if HSA OS ABI Version identification is 5,
51 /// false otherwise.
52 bool isHsaAbiVersion5(const MCSubtargetInfo *STI);
53 /// \returns True if HSA OS ABI Version identification is 3 and above,
54 /// false otherwise.
55 bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI);
56 
57 /// \returns The offset of the multigrid_sync_arg argument from implicitarg_ptr
59 
60 /// \returns The offset of the hostcall pointer argument from implicitarg_ptr
62 
63 /// \returns Code object version.
65 
67  unsigned Format;
68  unsigned BitsPerComp;
69  unsigned NumComponents;
70  unsigned NumFormat;
71  unsigned DataFormat;
72 };
73 
74 struct MAIInstInfo {
76  bool is_dgemm;
78 };
79 
80 #define GET_MIMGBaseOpcode_DECL
81 #define GET_MIMGDim_DECL
82 #define GET_MIMGEncoding_DECL
83 #define GET_MIMGLZMapping_DECL
84 #define GET_MIMGMIPMapping_DECL
85 #define GET_MIMGBiASMapping_DECL
86 #define GET_MAIInstInfoTable_DECL
87 #include "AMDGPUGenSearchableTables.inc"
88 
89 namespace IsaInfo {
90 
91 enum {
92  // The closed Vulkan driver sets 96, which limits the wave count to 8 but
93  // doesn't spill SGPRs as much as when 80 is set.
96 };
97 
98 enum class TargetIDSetting {
100  Any,
101  Off,
102  On
103 };
104 
106 private:
107  const MCSubtargetInfo &STI;
108  TargetIDSetting XnackSetting;
109  TargetIDSetting SramEccSetting;
110 
111 public:
112  explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
113  ~AMDGPUTargetID() = default;
114 
115  /// \return True if the current xnack setting is not "Unsupported".
116  bool isXnackSupported() const {
117  return XnackSetting != TargetIDSetting::Unsupported;
118  }
119 
120  /// \returns True if the current xnack setting is "On" or "Any".
121  bool isXnackOnOrAny() const {
122  return XnackSetting == TargetIDSetting::On ||
123  XnackSetting == TargetIDSetting::Any;
124  }
125 
126  /// \returns True if current xnack setting is "On" or "Off",
127  /// false otherwise.
128  bool isXnackOnOrOff() const {
129  return getXnackSetting() == TargetIDSetting::On ||
131  }
132 
133  /// \returns The current xnack TargetIDSetting, possible options are
134  /// "Unsupported", "Any", "Off", and "On".
136  return XnackSetting;
137  }
138 
139  /// Sets xnack setting to \p NewXnackSetting.
140  void setXnackSetting(TargetIDSetting NewXnackSetting) {
141  XnackSetting = NewXnackSetting;
142  }
143 
144  /// \return True if the current sramecc setting is not "Unsupported".
145  bool isSramEccSupported() const {
146  return SramEccSetting != TargetIDSetting::Unsupported;
147  }
148 
149  /// \returns True if the current sramecc setting is "On" or "Any".
150  bool isSramEccOnOrAny() const {
151  return SramEccSetting == TargetIDSetting::On ||
152  SramEccSetting == TargetIDSetting::Any;
153  }
154 
155  /// \returns True if current sramecc setting is "On" or "Off",
156  /// false otherwise.
157  bool isSramEccOnOrOff() const {
160  }
161 
162  /// \returns The current sramecc TargetIDSetting, possible options are
163  /// "Unsupported", "Any", "Off", and "On".
165  return SramEccSetting;
166  }
167 
168  /// Sets sramecc setting to \p NewSramEccSetting.
169  void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
170  SramEccSetting = NewSramEccSetting;
171  }
172 
175 
176  /// \returns String representation of an object.
177  std::string toString() const;
178 };
179 
180 /// \returns Wavefront size for given subtarget \p STI.
181 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
182 
183 /// \returns Local memory size in bytes for given subtarget \p STI.
184 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
185 
186 /// \returns Number of execution units per compute unit for given subtarget \p
187 /// STI.
188 unsigned getEUsPerCU(const MCSubtargetInfo *STI);
189 
190 /// \returns Maximum number of work groups per compute unit for given subtarget
191 /// \p STI and limited by given \p FlatWorkGroupSize.
192 unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
193  unsigned FlatWorkGroupSize);
194 
195 /// \returns Minimum number of waves per execution unit for given subtarget \p
196 /// STI.
197 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI);
198 
199 /// \returns Maximum number of waves per execution unit for given subtarget \p
200 /// STI without any kind of limitation.
201 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI);
202 
203 /// \returns Number of waves per execution unit required to support the given \p
204 /// FlatWorkGroupSize.
205 unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI,
206  unsigned FlatWorkGroupSize);
207 
208 /// \returns Minimum flat work group size for given subtarget \p STI.
209 unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI);
210 
211 /// \returns Maximum flat work group size for given subtarget \p STI.
212 unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI);
213 
214 /// \returns Number of waves per work group for given subtarget \p STI and
215 /// \p FlatWorkGroupSize.
216 unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI,
217  unsigned FlatWorkGroupSize);
218 
219 /// \returns SGPR allocation granularity for given subtarget \p STI.
220 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI);
221 
222 /// \returns SGPR encoding granularity for given subtarget \p STI.
223 unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI);
224 
225 /// \returns Total number of SGPRs for given subtarget \p STI.
226 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI);
227 
228 /// \returns Addressable number of SGPRs for given subtarget \p STI.
229 unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI);
230 
231 /// \returns Minimum number of SGPRs that meets the given number of waves per
232 /// execution unit requirement for given subtarget \p STI.
233 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
234 
235 /// \returns Maximum number of SGPRs that meets the given number of waves per
236 /// execution unit requirement for given subtarget \p STI.
237 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
238  bool Addressable);
239 
240 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
241 /// STI when the given special registers are used.
242 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
243  bool FlatScrUsed, bool XNACKUsed);
244 
245 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
246 /// STI when the given special registers are used. XNACK is inferred from
247 /// \p STI.
248 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
249  bool FlatScrUsed);
250 
251 /// \returns Number of SGPR blocks needed for given subtarget \p STI when
252 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
253 /// register counts.
254 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs);
255 
256 /// \returns VGPR allocation granularity for given subtarget \p STI.
257 ///
258 /// For subtargets which support it, \p EnableWavefrontSize32 should match
259 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
260 unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI,
261  Optional<bool> EnableWavefrontSize32 = None);
262 
263 /// \returns VGPR encoding granularity for given subtarget \p STI.
264 ///
265 /// For subtargets which support it, \p EnableWavefrontSize32 should match
266 /// the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
267 unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
268  Optional<bool> EnableWavefrontSize32 = None);
269 
270 /// \returns Total number of VGPRs for given subtarget \p STI.
271 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI);
272 
273 /// \returns Addressable number of VGPRs for given subtarget \p STI.
274 unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI);
275 
276 /// \returns Minimum number of VGPRs that meets given number of waves per
277 /// execution unit requirement for given subtarget \p STI.
278 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
279 
280 /// \returns Maximum number of VGPRs that meets given number of waves per
281 /// execution unit requirement for given subtarget \p STI.
282 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU);
283 
284 /// \returns Number of VGPR blocks needed for given subtarget \p STI when
285 /// \p NumVGPRs are used.
286 ///
287 /// For subtargets which support it, \p EnableWavefrontSize32 should match the
288 /// ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
289 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs,
290  Optional<bool> EnableWavefrontSize32 = None);
291 
292 } // end namespace IsaInfo
293 
295 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
296 
298 int getSOPPWithRelaxation(uint16_t Opcode);
299 
301  MIMGBaseOpcode BaseOpcode;
302  bool Store;
303  bool Atomic;
304  bool AtomicX2;
305  bool Sampler;
306  bool Gather4;
307 
308  uint8_t NumExtraArgs;
309  bool Gradients;
310  bool G16;
313  bool HasD16;
314  bool MSAA;
315  bool BVH;
316 };
317 
319 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc);
320 
322 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
323 
324 struct MIMGDimInfo {
325  MIMGDim Dim;
326  uint8_t NumCoords;
327  uint8_t NumGradients;
328  bool MSAA;
329  bool DA;
330  uint8_t Encoding;
331  const char *AsmSuffix;
332 };
333 
335 const MIMGDimInfo *getMIMGDimInfo(unsigned DimEnum);
336 
338 const MIMGDimInfo *getMIMGDimInfoByEncoding(uint8_t DimEnc);
339 
342 
344  MIMGBaseOpcode L;
345  MIMGBaseOpcode LZ;
346 };
347 
349  MIMGBaseOpcode MIP;
350  MIMGBaseOpcode NONMIP;
351 };
352 
354  MIMGBaseOpcode Bias;
355  MIMGBaseOpcode NoBias;
356 };
357 
359  MIMGBaseOpcode Offset;
360  MIMGBaseOpcode NoOffset;
361 };
362 
364  MIMGBaseOpcode G;
365  MIMGBaseOpcode G16;
366 };
367 
369 const MIMGLZMappingInfo *getMIMGLZMappingInfo(unsigned L);
370 
372 const MIMGMIPMappingInfo *getMIMGMIPMappingInfo(unsigned MIP);
373 
375 const MIMGBiasMappingInfo *getMIMGBiasMappingInfo(unsigned Bias);
376 
378 const MIMGOffsetMappingInfo *getMIMGOffsetMappingInfo(unsigned Offset);
379 
382 
384 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
385  unsigned VDataDwords, unsigned VAddrDwords);
386 
388 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
389 
391 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
392  const MIMGDimInfo *Dim, bool IsA16,
393  bool IsG16Supported);
394 
395 struct MIMGInfo {
398  uint8_t MIMGEncoding;
399  uint8_t VDataDwords;
400  uint8_t VAddrDwords;
401 };
402 
404 const MIMGInfo *getMIMGInfo(unsigned Opc);
405 
407 int getMTBUFBaseOpcode(unsigned Opc);
408 
410 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
411 
413 int getMTBUFElements(unsigned Opc);
414 
416 bool getMTBUFHasVAddr(unsigned Opc);
417 
419 bool getMTBUFHasSrsrc(unsigned Opc);
420 
422 bool getMTBUFHasSoffset(unsigned Opc);
423 
425 int getMUBUFBaseOpcode(unsigned Opc);
426 
428 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
429 
431 int getMUBUFElements(unsigned Opc);
432 
434 bool getMUBUFHasVAddr(unsigned Opc);
435 
437 bool getMUBUFHasSrsrc(unsigned Opc);
438 
440 bool getMUBUFHasSoffset(unsigned Opc);
441 
443 bool getMUBUFIsBufferInv(unsigned Opc);
444 
446 bool getSMEMIsBuffer(unsigned Opc);
447 
449 bool getVOP1IsSingle(unsigned Opc);
450 
452 bool getVOP2IsSingle(unsigned Opc);
453 
455 bool getVOP3IsSingle(unsigned Opc);
456 
457 /// Returns true if MAI operation is a double precision GEMM.
459 bool getMAIIsDGEMM(unsigned Opc);
460 
462 bool getMAIIsGFX940XDL(unsigned Opc);
463 
465 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
466  uint8_t NumComponents,
467  uint8_t NumFormat,
468  const MCSubtargetInfo &STI);
470 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
471  const MCSubtargetInfo &STI);
472 
474 int getMCOpcode(uint16_t Opcode, unsigned Gen);
475 
477  const MCSubtargetInfo *STI);
478 
480  const MCSubtargetInfo *STI);
481 
482 bool isGroupSegment(const GlobalValue *GV);
483 bool isGlobalSegment(const GlobalValue *GV);
484 bool isReadOnlySegment(const GlobalValue *GV);
485 
486 /// \returns True if constants should be emitted to .text section for given
487 /// target triple \p TT, false otherwise.
489 
490 /// \returns Integer value requested using \p F's \p Name attribute.
491 ///
492 /// \returns \p Default if attribute is not present.
493 ///
494 /// \returns \p Default and emits error if requested value cannot be converted
495 /// to integer.
496 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
497 
498 /// \returns A pair of integer values requested using \p F's \p Name attribute
499 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
500 /// is false).
501 ///
502 /// \returns \p Default if attribute is not present.
503 ///
504 /// \returns \p Default and emits error if one of the requested values cannot be
505 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
506 /// not present.
507 std::pair<int, int> getIntegerPairAttribute(const Function &F,
508  StringRef Name,
509  std::pair<int, int> Default,
510  bool OnlyFirstRequired = false);
511 
512 /// Represents the counter values to wait for in an s_waitcnt instruction.
513 ///
514 /// Large values (including the maximum possible integer) can be used to
515 /// represent "don't care" waits.
516 struct Waitcnt {
517  unsigned VmCnt = ~0u;
518  unsigned ExpCnt = ~0u;
519  unsigned LgkmCnt = ~0u;
520  unsigned VsCnt = ~0u;
521 
522  Waitcnt() = default;
523  Waitcnt(unsigned VmCnt, unsigned ExpCnt, unsigned LgkmCnt, unsigned VsCnt)
525 
526  static Waitcnt allZero(bool HasVscnt) {
527  return Waitcnt(0, 0, 0, HasVscnt ? 0 : ~0u);
528  }
529  static Waitcnt allZeroExceptVsCnt() { return Waitcnt(0, 0, 0, ~0u); }
530 
531  bool hasWait() const {
532  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u || VsCnt != ~0u;
533  }
534 
535  bool hasWaitExceptVsCnt() const {
536  return VmCnt != ~0u || ExpCnt != ~0u || LgkmCnt != ~0u;
537  }
538 
539  bool hasWaitVsCnt() const {
540  return VsCnt != ~0u;
541  }
542 
543  bool dominates(const Waitcnt &Other) const {
544  return VmCnt <= Other.VmCnt && ExpCnt <= Other.ExpCnt &&
545  LgkmCnt <= Other.LgkmCnt && VsCnt <= Other.VsCnt;
546  }
547 
548  Waitcnt combined(const Waitcnt &Other) const {
549  return Waitcnt(std::min(VmCnt, Other.VmCnt), std::min(ExpCnt, Other.ExpCnt),
550  std::min(LgkmCnt, Other.LgkmCnt),
551  std::min(VsCnt, Other.VsCnt));
552  }
553 };
554 
555 /// \returns Vmcnt bit mask for given isa \p Version.
556 unsigned getVmcntBitMask(const IsaVersion &Version);
557 
558 /// \returns Expcnt bit mask for given isa \p Version.
559 unsigned getExpcntBitMask(const IsaVersion &Version);
560 
561 /// \returns Lgkmcnt bit mask for given isa \p Version.
562 unsigned getLgkmcntBitMask(const IsaVersion &Version);
563 
564 /// \returns Waitcnt bit mask for given isa \p Version.
565 unsigned getWaitcntBitMask(const IsaVersion &Version);
566 
567 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
568 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt);
569 
570 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
571 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt);
572 
573 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
574 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt);
575 
576 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
577 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
578 /// \p Lgkmcnt respectively.
579 ///
580 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
581 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9)
582 /// \p Vmcnt = \p Waitcnt[15:14,3:0] (gfx9,10)
583 /// \p Vmcnt = \p Waitcnt[15:10] (gfx11+)
584 /// \p Expcnt = \p Waitcnt[6:4] (pre-gfx11)
585 /// \p Expcnt = \p Waitcnt[2:0] (gfx11+)
586 /// \p Lgkmcnt = \p Waitcnt[11:8] (pre-gfx10)
587 /// \p Lgkmcnt = \p Waitcnt[13:8] (gfx10)
588 /// \p Lgkmcnt = \p Waitcnt[9:4] (gfx11+)
589 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
590  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
591 
592 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded);
593 
594 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
595 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
596  unsigned Vmcnt);
597 
598 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
599 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
600  unsigned Expcnt);
601 
602 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
603 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
604  unsigned Lgkmcnt);
605 
606 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
607 /// \p Version.
608 ///
609 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
610 /// Waitcnt[2:0] = \p Expcnt (gfx11+)
611 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9)
612 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9,10)
613 /// Waitcnt[6:4] = \p Expcnt (pre-gfx11)
614 /// Waitcnt[9:4] = \p Lgkmcnt (gfx11+)
615 /// Waitcnt[11:8] = \p Lgkmcnt (pre-gfx10)
616 /// Waitcnt[13:8] = \p Lgkmcnt (gfx10)
617 /// Waitcnt[15:10] = \p Vmcnt (gfx11+)
618 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9,10)
619 ///
620 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
621 /// isa \p Version.
622 unsigned encodeWaitcnt(const IsaVersion &Version,
623  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
624 
625 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded);
626 
627 namespace Hwreg {
628 
630 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI);
631 
633 bool isValidHwreg(int64_t Id);
634 
636 bool isValidHwregOffset(int64_t Offset);
637 
639 bool isValidHwregWidth(int64_t Width);
640 
643 
645 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
646 
647 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width);
648 
649 } // namespace Hwreg
650 
651 namespace DepCtr {
652 
653 int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI);
654 int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
655  const MCSubtargetInfo &STI);
656 bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
657  const MCSubtargetInfo &STI);
658 bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
659  bool &IsDefault, const MCSubtargetInfo &STI);
660 
661 } // namespace DepCtr
662 
663 namespace Exp {
664 
665 bool getTgtName(unsigned Id, StringRef &Name, int &Index);
666 
668 unsigned getTgtId(const StringRef Name);
669 
671 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI);
672 
673 } // namespace Exp
674 
675 namespace MTBUFFormat {
676 
678 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt);
679 
680 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt);
681 
682 int64_t getDfmt(const StringRef Name);
683 
684 StringRef getDfmtName(unsigned Id);
685 
686 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI);
687 
688 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI);
689 
690 bool isValidDfmtNfmt(unsigned Val, const MCSubtargetInfo &STI);
691 
692 bool isValidNfmt(unsigned Val, const MCSubtargetInfo &STI);
693 
694 int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI);
695 
696 StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI);
697 
698 bool isValidUnifiedFormat(unsigned Val, const MCSubtargetInfo &STI);
699 
700 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
701  const MCSubtargetInfo &STI);
702 
703 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI);
704 
705 unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI);
706 
707 } // namespace MTBUFFormat
708 
709 namespace SendMsg {
710 
712 int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI);
713 
715 int64_t getMsgOpId(int64_t MsgId, const StringRef Name);
716 
718 StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI);
719 
721 StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
722 
724 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI);
725 
727 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
728  bool Strict = true);
729 
731 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
732  const MCSubtargetInfo &STI, bool Strict = true);
733 
735 bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI);
736 
738 bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI);
739 
740 void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
741  uint16_t &StreamId, const MCSubtargetInfo &STI);
742 
745  uint64_t OpId,
747 
748 } // namespace SendMsg
749 
750 
751 unsigned getInitialPSInputAddr(const Function &F);
752 
753 bool getHasColorExport(const Function &F);
754 
755 bool getHasDepthExport(const Function &F);
756 
758 bool isShader(CallingConv::ID CC);
759 
761 bool isGraphics(CallingConv::ID CC);
762 
764 bool isCompute(CallingConv::ID CC);
765 
768 
769 // These functions are considered entrypoints into the current module, i.e. they
770 // are allowed to be called from outside the current module. This is different
771 // from isEntryFunctionCC, which is only true for functions that are entered by
772 // the hardware. Module entry points include all entry functions but also
773 // include functions that can be called from other functions inside or outside
774 // the current module. Module entry functions are allowed to allocate LDS.
777 
778 bool isKernelCC(const Function *Func);
779 
780 // FIXME: Remove this when calling conventions cleaned up
782 inline bool isKernel(CallingConv::ID CC) {
783  switch (CC) {
786  return true;
787  default:
788  return false;
789  }
790 }
791 
792 bool hasXNACK(const MCSubtargetInfo &STI);
793 bool hasSRAMECC(const MCSubtargetInfo &STI);
794 bool hasMIMG_R128(const MCSubtargetInfo &STI);
795 bool hasGFX10A16(const MCSubtargetInfo &STI);
796 bool hasG16(const MCSubtargetInfo &STI);
797 bool hasPackedD16(const MCSubtargetInfo &STI);
798 
799 bool isSI(const MCSubtargetInfo &STI);
800 bool isCI(const MCSubtargetInfo &STI);
801 bool isVI(const MCSubtargetInfo &STI);
802 bool isGFX9(const MCSubtargetInfo &STI);
803 bool isGFX9_GFX10(const MCSubtargetInfo &STI);
804 bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI);
805 bool isGFX8Plus(const MCSubtargetInfo &STI);
806 bool isGFX9Plus(const MCSubtargetInfo &STI);
807 bool isGFX10(const MCSubtargetInfo &STI);
808 bool isGFX10Plus(const MCSubtargetInfo &STI);
809 bool isNotGFX10Plus(const MCSubtargetInfo &STI);
810 bool isGFX10Before1030(const MCSubtargetInfo &STI);
811 bool isGFX11(const MCSubtargetInfo &STI);
812 bool isGFX11Plus(const MCSubtargetInfo &STI);
813 bool isNotGFX11Plus(const MCSubtargetInfo &STI);
814 bool isGCN3Encoding(const MCSubtargetInfo &STI);
815 bool isGFX10_AEncoding(const MCSubtargetInfo &STI);
816 bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
817 bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
818 bool isGFX90A(const MCSubtargetInfo &STI);
819 bool isGFX940(const MCSubtargetInfo &STI);
821 bool hasMAIInsts(const MCSubtargetInfo &STI);
822 int getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR);
823 
824 /// Is Reg - scalar register
825 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
826 
827 /// If \p Reg is a pseudo reg, return the correct hardware register given
828 /// \p STI otherwise return \p Reg.
829 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
830 
831 /// Convert hardware register \p Reg to a pseudo register
833 unsigned mc2PseudoReg(unsigned Reg);
834 
835 /// Can this operand also contain immediate values?
836 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
837 
838 /// Is this floating-point operand?
839 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
840 
841 /// Does this operand support only inlinable literals?
842 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
843 
844 /// Get the size in bits of a register from the register class \p RC.
845 unsigned getRegBitWidth(unsigned RCID);
846 
847 /// Get the size in bits of a register from the register class \p RC.
848 unsigned getRegBitWidth(const MCRegisterClass &RC);
849 
850 /// Get size of register operand
851 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
852  unsigned OpNo);
853 
855 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
856  switch (OpInfo.OperandType) {
869  case AMDGPU::OPERAND_KIMM16: // mandatory literal is always size 4
870  return 4;
871 
877  return 8;
878 
892  return 2;
893 
894  default:
895  llvm_unreachable("unhandled operand type");
896  }
897 }
898 
900 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
901  return getOperandSize(Desc.OpInfo[OpNo]);
902 }
903 
904 /// Is this literal inlinable, and not one of the values intended for floating
905 /// point values.
907 inline bool isInlinableIntLiteral(int64_t Literal) {
908  return Literal >= -16 && Literal <= 64;
909 }
910 
911 /// Is this literal inlinable
913 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
914 
916 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
917 
919 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
920 
922 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
923 
925 bool isInlinableIntLiteralV216(int32_t Literal);
926 
928 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi);
929 
930 bool isArgPassedInSGPR(const Argument *Arg);
931 
934  int64_t EncodedOffset);
935 
938  int64_t EncodedOffset,
939  bool IsBuffer);
940 
941 /// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
942 /// offsets.
944 
945 /// \returns The encoding that will be used for \p ByteOffset in the
946 /// SMRD offset field, or None if it won't fit. On GFX9 and GFX10
947 /// S_LOAD instructions have a signed offset, on other subtargets it is
948 /// unsigned. S_BUFFER has an unsigned offset for all subtargets.
950  int64_t ByteOffset, bool IsBuffer);
951 
952 /// \return The encoding that can be used for a 32-bit literal offset in an SMRD
953 /// instruction. This is only useful on CI.s
955  int64_t ByteOffset);
956 
957 /// For FLAT segment the offset must be positive;
958 /// MSB is ignored and forced to zero.
959 ///
960 /// \return The number of bits available for the offset field in flat
961 /// instructions.
962 unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
963 
964 /// \returns true if this offset is small enough to fit in the SMRD
965 /// offset field. \p ByteOffset should be the offset in bytes and
966 /// not the encoded offset.
967 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
968 
969 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
970  const GCNSubtarget *Subtarget,
971  Align Alignment = Align(4));
972 
974 inline bool isLegal64BitDPPControl(unsigned DC) {
976 }
977 
978 /// \returns true if the intrinsic is divergent
979 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
980 
981 // Track defaults for fields in the MODE register.
983  /// Floating point opcodes that support exception flag gathering quiet and
984  /// propagate signaling NaN inputs per IEEE 754-2008. Min_dx10 and max_dx10
985  /// become IEEE 754- 2008 compliant due to signaling NaN propagation and
986  /// quieting.
987  bool IEEE : 1;
988 
989  /// Used by the vector ALU to force DX10-style treatment of NaNs: when set,
990  /// clamp NaN to zero; otherwise, pass NaN through.
991  bool DX10Clamp : 1;
992 
993  /// If this is set, neither input or output denormals are flushed for most f32
994  /// instructions.
997 
998  /// If this is set, neither input or output denormals are flushed for both f64
999  /// and f16/v2f16 instructions.
1002 
1004  IEEE(true),
1005  DX10Clamp(true),
1010 
1012 
1015  Mode.IEEE = !AMDGPU::isShader(CC);
1016  return Mode;
1017  }
1018 
1019  bool operator ==(const SIModeRegisterDefaults Other) const {
1020  return IEEE == Other.IEEE && DX10Clamp == Other.DX10Clamp &&
1021  FP32InputDenormals == Other.FP32InputDenormals &&
1022  FP32OutputDenormals == Other.FP32OutputDenormals &&
1023  FP64FP16InputDenormals == Other.FP64FP16InputDenormals &&
1024  FP64FP16OutputDenormals == Other.FP64FP16OutputDenormals;
1025  }
1026 
1027  bool allFP32Denormals() const {
1029  }
1030 
1031  bool allFP64FP16Denormals() const {
1033  }
1034 
1035  /// Get the encoding value for the FP_DENORM bits of the mode register for the
1036  /// FP32 denormal mode.
1039  return FP_DENORM_FLUSH_NONE;
1040  if (FP32InputDenormals)
1041  return FP_DENORM_FLUSH_OUT;
1042  if (FP32OutputDenormals)
1043  return FP_DENORM_FLUSH_IN;
1045  }
1046 
1047  /// Get the encoding value for the FP_DENORM bits of the mode register for the
1048  /// FP64/FP16 denormal mode.
1051  return FP_DENORM_FLUSH_NONE;
1053  return FP_DENORM_FLUSH_OUT;
1055  return FP_DENORM_FLUSH_IN;
1057  }
1058 
1059  /// Returns true if a flag is compatible if it's enabled in the callee, but
1060  /// disabled in the caller.
1061  static bool oneWayCompatible(bool CallerMode, bool CalleeMode) {
1062  return CallerMode == CalleeMode || (!CallerMode && CalleeMode);
1063  }
1064 
1065  // FIXME: Inlining should be OK for dx10-clamp, since the caller's mode should
1066  // be able to override.
1068  if (DX10Clamp != CalleeMode.DX10Clamp)
1069  return false;
1070  if (IEEE != CalleeMode.IEEE)
1071  return false;
1072 
1073  // Allow inlining denormals enabled into denormals flushed functions.
1078  }
1079 };
1080 
1081 } // end namespace AMDGPU
1082 
1083 raw_ostream &operator<<(raw_ostream &OS,
1085 
1086 } // end namespace llvm
1087 
1088 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:167
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1409
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uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
Definition: AMDGPUBaseInfo.cpp:1247
FP_DENORM_FLUSH_OUT
#define FP_DENORM_FLUSH_OUT
Definition: SIDefines.h:1021
llvm::AMDGPU::SIModeRegisterDefaults::fpDenormModeDPValue
uint32_t fpDenormModeDPValue() const
Get the encoding value for the FP_DENORM bits of the mode register for the FP64/FP16 denormal mode.
Definition: AMDGPUBaseInfo.h:1049
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bool getMUBUFIsBufferInv(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:345
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1813
llvm::AMDGPU::isHsaAbiVersion3
bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:125
llvm::Argument
This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
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AMDGPUTargetID(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:389
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const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPU::mc2PseudoReg
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
Definition: AMDGPUBaseInfo.cpp:1827
Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4637
LLVM_READONLY
#define LLVM_READONLY
Definition: Compiler.h:206
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::AMDGPU::getMAIIsDGEMM
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
Definition: AMDGPUBaseInfo.cpp:370
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unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:659
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bool getMUBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:340
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bool HasD16
Definition: AMDGPUBaseInfo.h:313
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static Waitcnt allZeroExceptVsCnt()
Definition: AMDGPUBaseInfo.h:529
llvm::AMDGPU::MTBUFFormat::NumFormat
NumFormat
Definition: SIDefines.h:490
llvm::AMDGPU::Hwreg::getHwreg
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1253
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unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1434
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@ OPERAND_REG_INLINE_C_INT16
Operands with register or inline constant.
Definition: SIDefines.h:162
llvm::AMDGPU::MIMGBaseOpcodeInfo::Store
bool Store
Definition: AMDGPUBaseInfo.h:302
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const char * AsmSuffix
Definition: AMDGPUBaseInfo.h:331
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bool Gradients
Definition: AMDGPUBaseInfo.h:309
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constexpr char NumSGPRs[]
Key for Kernel::CodeProps::Metadata::mNumSGPRs.
Definition: AMDGPUMetadata.h:258
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int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1230
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bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1524
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bool LodOrClampOrMip
Definition: AMDGPUBaseInfo.h:312
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StringRef getDfmtName(unsigned Id)
Definition: AMDGPUBaseInfo.cpp:1341
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uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
Definition: AMDGPUBaseInfo.cpp:1549
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bool isGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1698
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unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:1000
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Definition: Function.h:60
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int getMUBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:315
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bool FP32OutputDenormals
Definition: AMDGPUBaseInfo.h:996
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void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
Definition: AMDGPUBaseInfo.h:140
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Optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:2160
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int getMCOpcode(uint16_t Opcode, unsigned Gen)
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bool isSramEccOnOrAny() const
Definition: AMDGPUBaseInfo.h:150
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Definition: AMDGPUBaseInfo.cpp:987
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Definition: AMDGPUBaseInfo.cpp:1633
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Floating point opcodes that support exception flag gathering quiet and propagate signaling NaN inputs...
Definition: AMDGPUBaseInfo.h:987
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Definition: AMDGPUBaseInfo.cpp:1629
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@ Unsupported
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@ OPERAND_KIMM16
Definition: SIDefines.h:175
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:156
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@ On
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Definition: AMDGPUBaseInfo.cpp:1718
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Definition: AMDGPUBaseInfo.h:324
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~AMDGPUTargetID()=default
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All possible values of the reg field in the ModR/M byte.
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#define FP_DENORM_FLUSH_IN
Definition: SIDefines.h:1022
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Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
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true
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Definition: BasicAliasAnalysis.cpp:1909
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bool isGFX11(const MCSubtargetInfo &STI)
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@ OPERAND_REG_IMM_V2INT32
Definition: SIDefines.h:158
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unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
Definition: AMDGPUBaseInfo.cpp:725
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bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1686
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unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
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Definition: AMDGPUBaseInfo.h:353
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static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:1013
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Definition: AMDGPUBaseInfo.h:982
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If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:995
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@ Any
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Definition: GCNSubtarget.h:31
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unsigned getVmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:961
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Definition: AMDGPUBaseInfo.h:1067
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bool isGlobalSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:907
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Definition: AMDGPUBaseInfo.h:325
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Definition: SPIRVBaseInfo.h:279
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Definition: AMDGPUBaseInfo.cpp:1726
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Returns true if a flag is compatible if it's enabled in the callee, but disabled in the caller.
Definition: AMDGPUBaseInfo.h:1061
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Definition: AMDGPUBaseInfo.h:315
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Definition: AMDGPUBaseInfo.h:327
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Definition: AMDGPUBaseInfo.cpp:290
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Definition: AMDGPUBaseInfo.h:350
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Definition: AMDGPUBaseInfo.h:400
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Definition: AMDGPUBaseInfo.cpp:614
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#define F(x, y, z)
Definition: MD5.cpp:55
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Definition: AMDGPUBaseInfo.cpp:1368
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Definition: AMDGPUBaseInfo.cpp:1210
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Definition: MCRegisterInfo.h:31
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LLVM_READNONE bool isKernel(CallingConv::ID CC)
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Definition: AMDGPUBaseInfo.h:359
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Definition: AMDGPUBaseInfo.h:98
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Definition: AMDGPUBaseInfo.h:71
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Definition: MCInstrDesc.h:84
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Definition: AMDGPUBaseInfo.cpp:668
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@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:151
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Definition: AMDGPUBaseInfo.cpp:1530
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Definition: AMDGPUBaseInfo.h:105
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Definition: AMDGPUBaseInfo.cpp:1576
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Definition: AMDGPUBaseInfo.cpp:654
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@ OPERAND_REG_INLINE_C_INT32
Definition: SIDefines.h:163
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Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:1990
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Definition: AMDGPUBaseInfo.h:364
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@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:180
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Definition: AMDGPUBaseInfo.cpp:320
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Definition: AMDGPUBaseInfo.h:75
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const LLVM_READONLY MIMGOffsetMappingInfo * getMIMGOffsetMappingInfo(unsigned Offset)
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Definition: AMDGPUBaseInfo.cpp:350
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Definition: AMDGPUBaseInfo.h:330
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Definition: AMDGPUBaseInfo.cpp:1734
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Definition: AMDGPUBaseInfo.cpp:708
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bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1753
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Definition: AMDGPUBaseInfo.cpp:1742
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Definition: SIDefines.h:378
llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS
@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:95
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Definition: AMDGPUBaseInfo.h:121
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Definition: AMDGPUBaseInfo.h:70
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Definition: AMDGPUBaseInfo.cpp:995
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Definition: AMDGPUBaseInfo.cpp:375
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Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
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Definition: AMDGPUBaseInfo.cpp:1641
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Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
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Definition: AMDGPUBaseInfo.h:343
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@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:152
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int getMTBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:285
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Definition: AMDGPUBaseInfo.cpp:1561
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Definition: SIDefines.h:1020
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Definition: AMDGPUBaseInfo.cpp:310
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Definition: AMDGPUBaseInfo.h:520
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raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:1005
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bool dominates(const Waitcnt &Other) const
Definition: AMDGPUBaseInfo.h:543
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@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:159
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unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:645
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TargetIDSetting getSramEccSetting() const
Definition: AMDGPUBaseInfo.h:164
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const LLVM_READONLY MIMGLZMappingInfo * getMIMGLZMappingInfo(unsigned L)
llvm::AMDGPU::getMUBUFHasSrsrc
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Definition: AMDGPUBaseInfo.cpp:335
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Definition: AMDGPUBaseInfo.h:314
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uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
Definition: AMDGPUBaseInfo.cpp:2151
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unsigned getEUsPerCU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:603
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uint8_t MIMGEncoding
Definition: AMDGPUBaseInfo.h:398
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32
@ OPERAND_REG_INLINE_C_V2INT32
Definition: SIDefines.h:170
llvm::AMDGPU::IsaInfo::getLocalMemorySize
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:594
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Waitcnt()=default
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:194
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bool isCI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1658
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:364
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1690
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1599
llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1430
llvm::AMDGPU::isHsaAbiVersion2
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:119
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1649
llvm::AMDGPU::Hwreg::isValidHwregWidth
bool isValidHwregWidth(int64_t Width)
Definition: AMDGPUBaseInfo.cpp:1243
llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1197
llvm::AMDGPU::shouldEmitConstantsToTextSection
bool shouldEmitConstantsToTextSection(const Triple &TT)
Definition: AMDGPUBaseInfo.cpp:917
llvm::AMDGPU::SendMsg::getMsgId
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1452
llvm::AMDGPU::Hwreg::isValidHwreg
bool isValidHwreg(int64_t Id)
Definition: AMDGPUBaseInfo.cpp:1235
llvm::AMDGPU::isVI
bool isVI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1662
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:154
G
const DataFlowGraph & G
Definition: RDFGraph.cpp:200
llvm::AMDGPU::isInlinableLiteralV216
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2059
llvm::AMDGPU::getMIMGDimInfo
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfo(unsigned DimEnum)
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1881
llvm::AMDGPU::getExpcntBitMask
unsigned getExpcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:967
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition
unsigned getMultigridSyncArgImplicitArgPosition()
Definition: AMDGPUBaseInfo.cpp:152
llvm::AMDGPU::isHsaAbiVersion4
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:131
llvm::AMDGPU::IsaInfo::getMinNumSGPRs
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:691
llvm::AMDGPU::isInlinableIntLiteral
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
Definition: AMDGPUBaseInfo.h:907
llvm::AMDGPU::hasG16
bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1645
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Calling convention for AMDGPU code object kernels.
Definition: CallingConv.h:216
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:409
llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64
@ OPERAND_REG_INLINE_C_INT64
Definition: SIDefines.h:164
uint64_t
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:166
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1666
llvm::AMDGPU::MAIInstInfo::is_gfx940_xdl
bool is_gfx940_xdl
Definition: AMDGPUBaseInfo.h:77
llvm::AMDGPU::MIMGLZMappingInfo::L
MIMGBaseOpcode L
Definition: AMDGPUBaseInfo.h:344
llvm::AMDGPU::SIModeRegisterDefaults::allFP64FP16Denormals
bool allFP64FP16Denormals() const
Definition: AMDGPUBaseInfo.h:1031
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uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::AMDGPU::initDefaultAMDKernelCodeT
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:833
llvm::AMDGPU::Waitcnt::combined
Waitcnt combined(const Waitcnt &Other) const
Definition: AMDGPUBaseInfo.h:548
llvm::AMDGPU::getIntegerAttribute
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
Definition: AMDGPUBaseInfo.cpp:921
llvm::AMDGPU::Waitcnt::hasWaitExceptVsCnt
bool hasWaitExceptVsCnt() const
Definition: AMDGPUBaseInfo.h:535
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccOnOrOff
bool isSramEccOnOrOff() const
Definition: AMDGPUBaseInfo.h:157
llvm::AMDGPU::GcnBufferFormatInfo::BitsPerComp
unsigned BitsPerComp
Definition: AMDGPUBaseInfo.h:68
FP_DENORM_FLUSH_NONE
#define FP_DENORM_FLUSH_NONE
Definition: SIDefines.h:1023
llvm::AMDGPU::getGcnBufferFormatInfo
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2292
llvm::AMDGPU::MIMGMIPMappingInfo
Definition: AMDGPUBaseInfo.h:348
llvm::AMDGPU::IsaInfo::getWavefrontSize
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:585
llvm::AMDGPU::isSISrcInlinableOperand
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:1872
llvm::AMDGPU::Hwreg::isValidHwregOffset
bool isValidHwregOffset(int64_t Offset)
Definition: AMDGPUBaseInfo.cpp:1239
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:991
llvm::AMDGPU::encodeVmcnt
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
Definition: AMDGPUBaseInfo.cpp:1020
llvm::AMDGPU::MIMGOffsetMappingInfo
Definition: AMDGPUBaseInfo.h:358
llvm::AMDGPU::getAddrSizeMIMGOp
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:214
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getXnackSetting
TargetIDSetting getXnackSetting() const
Definition: AMDGPUBaseInfo.h:135
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:1000
llvm::AMDGPU::isGFX9_GFX10
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1670
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16
@ OPERAND_REG_INLINE_AC_INT16
Operands with an AccVGPR register or inline constant.
Definition: SIDefines.h:178
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:262
llvm::AMDGPU::Waitcnt::LgkmCnt
unsigned LgkmCnt
Definition: AMDGPUBaseInfo.h:519
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1321
llvm::AMDGPU::IsaInfo::getTotalNumSGPRs
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:672
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::isGFX10Before1030
bool isGFX10Before1030(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1710
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:168
llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:679
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:155
llvm::AMDGPU::MIMGBaseOpcodeInfo::AtomicX2
bool AtomicX2
Definition: AMDGPUBaseInfo.h:304
llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1413
llvm::AMDGPU::IsaInfo::getNumSGPRBlocks
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
Definition: AMDGPUBaseInfo.cpp:756
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:181
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MIMGInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.h:397
llvm::AMDGPU::isInlinableLiteral16
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2040
llvm::AMDGPU::OPERAND_REG_IMM_INT16
@ OPERAND_REG_IMM_INT16
Definition: SIDefines.h:150
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::getMIMGMIPMappingInfo
const LLVM_READONLY MIMGMIPMappingInfo * getMIMGMIPMappingInfo(unsigned MIP)
llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32
@ OPERAND_REG_INLINE_AC_INT32
Definition: SIDefines.h:179
llvm::AMDGPU::isHsaAbiVersion5
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:137
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::AMDGPU::isNotGFX10Plus
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1706
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1457
llvm::AMDGPU::MAIInstInfo::is_dgemm
bool is_dgemm
Definition: AMDGPUBaseInfo.h:76
llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1204
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::AMDGPU::MIMGLZMappingInfo::LZ
MIMGBaseOpcode LZ
Definition: AMDGPUBaseInfo.h:345
llvm::AMDGPU::Waitcnt::hasWait
bool hasWait() const
Definition: AMDGPUBaseInfo.h:531
llvm::AMDGPU::getVOP3IsSingle
bool getVOP3IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:365
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:94
llvm::AMDGPU::isModuleEntryFunctionCC
bool isModuleEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1616
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AMDGPU::isCompute
bool isCompute(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1595
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:777
uint32_t
llvm::AMDGPU::getMIMGBiasMappingInfo
const LLVM_READONLY MIMGBiasMappingInfo * getMIMGBiasMappingInfo(unsigned Bias)
llvm::AMDGPU::IsaInfo::getNumVGPRBlocks
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:823
DC
static ManagedStatic< DebugCounter > DC
Definition: DebugCounter.cpp:70
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates
bool Coordinates
Definition: AMDGPUBaseInfo.h:311
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
Definition: AMDGPUBaseInfo.cpp:2133
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
SPIR_KERNEL - Calling convention for SPIR kernel functions.
Definition: CallingConv.h:152
llvm::AMDGPU::isSISrcOperand
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1836
llvm::AMDGPU::Waitcnt::hasWaitVsCnt
bool hasWaitVsCnt() const
Definition: AMDGPUBaseInfo.h:539
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1591
amd_kernel_code_t
AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:116
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:649
llvm::AMDGPU::Exp::getTgtName
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1287
llvm::AMDGPU::Waitcnt::VmCnt
unsigned VmCnt
Definition: AMDGPUBaseInfo.h:517
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:300
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::AMDGPU::MIMGBaseOpcodeInfo::BaseOpcode
MIMGBaseOpcode BaseOpcode
Definition: AMDGPUBaseInfo.h:301
llvm::AMDGPU::GcnBufferFormatInfo
Definition: AMDGPUBaseInfo.h:66
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Definition: SIDefines.h:174
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Definition: SIDefines.h:171
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Definition: AMDGPUBaseInfo.cpp:797
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Definition: AMDGPUBaseInfo.h:69
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Definition: SIDefines.h:828
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Definition: AMDGPUBaseInfo.cpp:1498
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Definition: AMDGPUBaseInfo.h:329
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Definition: SIDefines.h:829
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Definition: AMDGPUBaseInfo.h:310
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Definition: SIDefines.h:165
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Definition: AMDGPUBaseInfo.h:354
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Definition: AMDGPUBaseInfo.cpp:911
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Definition: AMDGPUBaseInfo.h:328
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Definition: AMDGPUBaseInfo.h:363
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@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:153
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Definition: AMDGPUBaseInfo.h:526
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Definition: SIDefines.h:183
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Definition: AMDGPUBaseInfo.h:360
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Definition: SIDefines.h:235
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Definition: X86.h:188
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Definition: AMDGPUBaseInfo.h:518
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Definition: AMDGPUBaseInfo.h:365
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Definition: MCSubtargetInfo.h:76
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Definition: AMDGPUBaseInfo.cpp:295
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@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:184
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