21#include "llvm/IR/IntrinsicsAMDGPU.h"
22#include "llvm/IR/IntrinsicsR600.h"
32#define GET_INSTRINFO_NAMED_OPS
33#define GET_INSTRMAP_INFO
34#include "AMDGPUGenInstrInfo.inc"
39 llvm::cl::desc(
"Set default AMDHSA Code Object Version (module flag "
40 "or asm directive still take priority if present)"));
45unsigned getBitMask(
unsigned Shift,
unsigned Width) {
46 return ((1 << Width) - 1) << Shift;
52unsigned packBits(
unsigned Src,
unsigned Dst,
unsigned Shift,
unsigned Width) {
53 unsigned Mask = getBitMask(Shift, Width);
54 return ((Src << Shift) & Mask) | (Dst & ~Mask);
60unsigned unpackBits(
unsigned Src,
unsigned Shift,
unsigned Width) {
61 return (Src & getBitMask(Shift, Width)) >> Shift;
65unsigned getVmcntBitShiftLo(
unsigned VersionMajor) {
70unsigned getVmcntBitWidthLo(
unsigned VersionMajor) {
75unsigned getExpcntBitShift(
unsigned VersionMajor) {
80unsigned getExpcntBitWidth(
unsigned VersionMajor) {
return 3; }
83unsigned getLgkmcntBitShift(
unsigned VersionMajor) {
88unsigned getLgkmcntBitWidth(
unsigned VersionMajor) {
93unsigned getVmcntBitShiftHi(
unsigned VersionMajor) {
return 14; }
96unsigned getVmcntBitWidthHi(
unsigned VersionMajor) {
97 return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0;
101unsigned getLoadcntBitWidth(
unsigned VersionMajor) {
106unsigned getSamplecntBitWidth(
unsigned VersionMajor) {
111unsigned getBvhcntBitWidth(
unsigned VersionMajor) {
116unsigned getDscntBitWidth(
unsigned VersionMajor) {
121unsigned getDscntBitShift(
unsigned VersionMajor) {
return 0; }
124unsigned getStorecntBitWidth(
unsigned VersionMajor) {
129unsigned getKmcntBitWidth(
unsigned VersionMajor) {
134unsigned getLoadcntStorecntBitShift(
unsigned VersionMajor) {
139inline unsigned getVmVsrcBitWidth() {
return 3; }
142inline unsigned getVmVsrcBitShift() {
return 2; }
145inline unsigned getVaVdstBitWidth() {
return 4; }
148inline unsigned getVaVdstBitShift() {
return 12; }
151inline unsigned getSaSdstBitWidth() {
return 1; }
154inline unsigned getSaSdstBitShift() {
return 0; }
174 if (
auto Ver = mdconst::extract_or_null<ConstantInt>(
175 M.getModuleFlag(
"amdhsa_code_object_version"))) {
176 return (
unsigned)Ver->getZExtValue() / 100;
187 switch (ABIVersion) {
203 switch (CodeObjectVersion) {
212 Twine(CodeObjectVersion));
217 switch (CodeObjectVersion) {
231 switch (CodeObjectVersion) {
242 switch (CodeObjectVersion) {
253 switch (CodeObjectVersion) {
263#define GET_MIMGBaseOpcodesTable_IMPL
264#define GET_MIMGDimInfoTable_IMPL
265#define GET_MIMGInfoTable_IMPL
266#define GET_MIMGLZMappingTable_IMPL
267#define GET_MIMGMIPMappingTable_IMPL
268#define GET_MIMGBiasMappingTable_IMPL
269#define GET_MIMGOffsetMappingTable_IMPL
270#define GET_MIMGG16MappingTable_IMPL
271#define GET_MAIInstInfoTable_IMPL
272#include "AMDGPUGenSearchableTables.inc"
275 unsigned VDataDwords,
unsigned VAddrDwords) {
276 const MIMGInfo *
Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
277 VDataDwords, VAddrDwords);
291 return NewInfo ? NewInfo->
Opcode : -1;
296 bool IsG16Supported) {
303 AddrWords += AddrComponents;
311 if ((IsA16 && !IsG16Supported) || BaseOpcode->
G16)
388#define GET_MTBUFInfoTable_DECL
389#define GET_MTBUFInfoTable_IMPL
390#define GET_MUBUFInfoTable_DECL
391#define GET_MUBUFInfoTable_IMPL
392#define GET_SingleUseExceptionTable_DECL
393#define GET_SingleUseExceptionTable_IMPL
394#define GET_SMInfoTable_DECL
395#define GET_SMInfoTable_IMPL
396#define GET_VOP1InfoTable_DECL
397#define GET_VOP1InfoTable_IMPL
398#define GET_VOP2InfoTable_DECL
399#define GET_VOP2InfoTable_IMPL
400#define GET_VOP3InfoTable_DECL
401#define GET_VOP3InfoTable_IMPL
402#define GET_VOPC64DPPTable_DECL
403#define GET_VOPC64DPPTable_IMPL
404#define GET_VOPC64DPP8Table_DECL
405#define GET_VOPC64DPP8Table_IMPL
406#define GET_VOPCAsmOnlyInfoTable_DECL
407#define GET_VOPCAsmOnlyInfoTable_IMPL
408#define GET_VOP3CAsmOnlyInfoTable_DECL
409#define GET_VOP3CAsmOnlyInfoTable_IMPL
410#define GET_VOPDComponentTable_DECL
411#define GET_VOPDComponentTable_IMPL
412#define GET_VOPDPairs_DECL
413#define GET_VOPDPairs_IMPL
414#define GET_VOPTrue16Table_DECL
415#define GET_VOPTrue16Table_IMPL
416#define GET_WMMAOpcode2AddrMappingTable_DECL
417#define GET_WMMAOpcode2AddrMappingTable_IMPL
418#define GET_WMMAOpcode3AddrMappingTable_DECL
419#define GET_WMMAOpcode3AddrMappingTable_IMPL
420#include "AMDGPUGenSearchableTables.inc"
424 return Info ?
Info->BaseOpcode : -1;
428 const MTBUFInfo *
Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
439 return Info ?
Info->has_vaddr :
false;
444 return Info ?
Info->has_srsrc :
false;
449 return Info ?
Info->has_soffset :
false;
454 return Info ?
Info->BaseOpcode : -1;
458 const MUBUFInfo *
Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
469 return Info ?
Info->has_vaddr :
false;
474 return Info ?
Info->has_srsrc :
false;
479 return Info ?
Info->has_soffset :
false;
484 return Info ?
Info->IsBufferInv :
false;
493 const SMInfo *
Info = getSMEMOpcodeHelper(Opc);
494 return Info ?
Info->IsBuffer :
false;
499 return Info ?
Info->IsSingle :
false;
504 return Info ?
Info->IsSingle :
false;
509 return Info ?
Info->IsSingle :
false;
513 return isVOPC64DPPOpcodeHelper(Opc) || isVOPC64DPP8OpcodeHelper(Opc);
520 return Info ?
Info->is_dgemm :
false;
525 return Info ?
Info->is_gfx940_xdl :
false;
529 if (ST.hasFeature(AMDGPU::FeatureGFX12Insts))
531 if (ST.hasFeature(AMDGPU::FeatureGFX11Insts))
539 return {
Info->CanBeVOPDX,
true};
541 return {
false,
false};
554 return Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
555 Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
556 Opc == AMDGPU::V_MAC_F32_e64_vi ||
557 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
558 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
559 Opc == AMDGPU::V_MAC_F16_e64_vi ||
560 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
561 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
562 Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
563 Opc == AMDGPU::V_FMAC_F32_e64_gfx12 ||
564 Opc == AMDGPU::V_FMAC_F32_e64_vi ||
565 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
566 Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
567 Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
568 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx11 ||
569 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx12 ||
570 Opc == AMDGPU::V_DOT2C_F32_F16_e64_vi ||
571 Opc == AMDGPU::V_DOT2C_I32_I16_e64_vi ||
572 Opc == AMDGPU::V_DOT4C_I32_I8_e64_vi ||
573 Opc == AMDGPU::V_DOT8C_I32_I4_e64_vi;
577 return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
578 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
579 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
580 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
581 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
582 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
583 Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
584 Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
588 return Opc == AMDGPU::V_CVT_F32_BF8_e64_gfx12 ||
589 Opc == AMDGPU::V_CVT_F32_FP8_e64_gfx12 ||
590 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12 ||
591 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
592 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
593 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
594 Opc == AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 ||
595 Opc == AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12;
599 return Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP ||
600 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD ||
601 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB ||
602 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN ||
603 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN ||
604 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX ||
605 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX ||
606 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND ||
607 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR ||
608 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR ||
609 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC ||
610 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC ||
611 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD ||
612 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN ||
613 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX ||
614 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP ||
615 Opc == AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG;
620 return Info ?
Info->IsTrue16 :
false;
625 return Info &&
Info->IsInvalidSingleUseConsumer;
630 return Info &&
Info->IsInvalidSingleUseProducer;
635 return Info ?
Info->Opcode3Addr : ~0u;
640 return Info ?
Info->Opcode2Addr : ~0u;
647 return getMCOpcodeGen(Opcode,
static_cast<Subtarget
>(Gen));
650int getVOPDFull(
unsigned OpX,
unsigned OpY,
unsigned EncodingFamily) {
652 getVOPDInfoFromComponentOpcodes(OpX, OpY, EncodingFamily);
659 auto OpX = getVOPDBaseFromComponent(
Info->OpX);
660 auto OpY = getVOPDBaseFromComponent(
Info->OpY);
662 return {OpX->BaseVOP, OpY->BaseVOP};
674 HasSrc2Acc = TiedIdx != -1;
681 for (CompOprIdx =
Component::SRC1; CompOprIdx < OperandsNum; ++CompOprIdx) {
683 MandatoryLiteralIdx = CompOprIdx;
704 std::function<
unsigned(
unsigned,
unsigned)> GetRegIdx,
bool SkipSrc)
const {
709 const unsigned CompOprNum =
712 for (CompOprIdx = 0; CompOprIdx < CompOprNum; ++CompOprIdx) {
714 if (OpXRegs[CompOprIdx] && OpYRegs[CompOprIdx] &&
715 ((OpXRegs[CompOprIdx] & BanksMasks) ==
716 (OpYRegs[CompOprIdx] & BanksMasks)))
732 std::function<
unsigned(
unsigned,
unsigned)> GetRegIdx)
const {
735 const auto &Comp = CompInfo[CompIdx];
738 RegIndices[
DST] = GetRegIdx(CompIdx, Comp.getIndexOfDstInMCOperands());
741 unsigned CompSrcIdx = CompOprIdx -
DST_NUM;
743 Comp.hasRegSrcOperand(CompSrcIdx)
744 ? GetRegIdx(CompIdx, Comp.getIndexOfSrcInMCOperands(CompSrcIdx))
759 const auto &OpXDesc = InstrInfo->
get(OpX);
760 const auto &OpYDesc = InstrInfo->
get(OpY);
782 std::optional<bool> XnackRequested;
783 std::optional<bool> SramEccRequested;
785 for (
const std::string &Feature : Features.
getFeatures()) {
786 if (Feature ==
"+xnack")
787 XnackRequested =
true;
788 else if (Feature ==
"-xnack")
789 XnackRequested =
false;
790 else if (Feature ==
"+sramecc")
791 SramEccRequested =
true;
792 else if (Feature ==
"-sramecc")
793 SramEccRequested =
false;
799 if (XnackRequested) {
800 if (XnackSupported) {
806 if (*XnackRequested) {
807 errs() <<
"warning: xnack 'On' was requested for a processor that does "
810 errs() <<
"warning: xnack 'Off' was requested for a processor that "
811 "does not support it!\n";
816 if (SramEccRequested) {
817 if (SramEccSupported) {
824 if (*SramEccRequested) {
825 errs() <<
"warning: sramecc 'On' was requested for a processor that "
826 "does not support it!\n";
828 errs() <<
"warning: sramecc 'Off' was requested for a processor that "
829 "does not support it!\n";
847 TargetID.
split(TargetIDSplit,
':');
849 for (
const auto &FeatureString : TargetIDSplit) {
850 if (FeatureString.starts_with(
"xnack"))
852 if (FeatureString.starts_with(
"sramecc"))
858 std::string StringRep;
864 StreamRep << TargetTriple.getArchName() <<
'-'
865 << TargetTriple.getVendorName() <<
'-'
866 << TargetTriple.getOSName() <<
'-'
867 << TargetTriple.getEnvironmentName() <<
'-';
869 std::string Processor;
880 std::string Features;
884 Features +=
":sramecc-";
886 Features +=
":sramecc+";
889 Features +=
":xnack-";
891 Features +=
":xnack+";
894 StreamRep << Processor << Features;
910 unsigned BytesPerCU = 0;
945 unsigned FlatWorkGroupSize) {
946 assert(FlatWorkGroupSize != 0);
956 unsigned MaxBarriers = 16;
960 return std::min(MaxWaves /
N, MaxBarriers);
977 unsigned FlatWorkGroupSize) {
992 unsigned FlatWorkGroupSize) {
1052 return Addressable ? AddressableNumSGPRs : 108;
1053 if (
Version.Major >= 8 && !Addressable)
1054 AddressableNumSGPRs = 112;
1059 return std::min(MaxNumSGPRs, AddressableNumSGPRs);
1063 bool FlatScrUsed,
bool XNACKUsed) {
1064 unsigned ExtraSGPRs = 0;
1095 return divideCeil(std::max(1u, NumRegs), Granule);
1105 std::optional<bool> EnableWavefrontSize32) {
1109 bool IsWave32 = EnableWavefrontSize32 ?
1110 *EnableWavefrontSize32 :
1114 return IsWave32 ? 24 : 12;
1117 return IsWave32 ? 16 : 8;
1119 return IsWave32 ? 8 : 4;
1123 std::optional<bool> EnableWavefrontSize32) {
1127 bool IsWave32 = EnableWavefrontSize32 ?
1128 *EnableWavefrontSize32 :
1131 return IsWave32 ? 8 : 4;
1141 return IsWave32 ? 1536 : 768;
1142 return IsWave32 ? 1024 : 512;
1154 unsigned NumVGPRs) {
1162 unsigned TotalNumVGPRs) {
1163 if (NumVGPRs < Granule)
1165 unsigned RoundedRegs =
alignTo(NumVGPRs, Granule);
1166 return std::min(std::max(TotalNumVGPRs / RoundedRegs, 1u), MaxWaves);
1200 if (WavesPerEU >= MaxWavesPerEU)
1206 unsigned MaxNumVGPRs =
alignDown(TotNumVGPRs / WavesPerEU, Granule);
1208 if (MaxNumVGPRs ==
alignDown(TotNumVGPRs / MaxWavesPerEU, Granule))
1212 if (WavesPerEU < MinWavesPerEU)
1215 unsigned MaxNumVGPRsNext =
alignDown(TotNumVGPRs / (WavesPerEU + 1), Granule);
1216 unsigned MinNumVGPRs = 1 + std::min(MaxNumVGPRs - Granule, MaxNumVGPRsNext);
1217 return std::min(MinNumVGPRs, AddrsableNumVGPRs);
1226 return std::min(MaxNumVGPRs, AddressableNumVGPRs);
1230 std::optional<bool> EnableWavefrontSize32) {
1238 std::optional<bool> EnableWavefrontSize32) {
1296std::pair<unsigned, unsigned>
1298 std::pair<unsigned, unsigned>
Default,
1299 bool OnlyFirstRequired) {
1301 if (!
A.isStringAttribute())
1305 std::pair<unsigned, unsigned> Ints =
Default;
1306 std::pair<StringRef, StringRef> Strs =
A.getValueAsString().split(
',');
1307 if (Strs.first.trim().getAsInteger(0, Ints.first)) {
1308 Ctx.
emitError(
"can't parse first integer attribute " +
Name);
1311 if (Strs.second.trim().getAsInteger(0, Ints.second)) {
1312 if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
1313 Ctx.
emitError(
"can't parse second integer attribute " +
Name);
1327 if (!
A.isStringAttribute())
1337 std::pair<StringRef, StringRef> Strs = S.
split(
',');
1339 if (Strs.first.trim().getAsInteger(0, IntVal)) {
1340 Ctx.
emitError(
"can't parse integer attribute " + Strs.first +
" in " +
1350 " has incorrect number of integers; expected " +
1351 llvm::utostr(
Size));
1358 return (1 << (getVmcntBitWidthLo(
Version.Major) +
1359 getVmcntBitWidthHi(
Version.Major))) -
1364 return (1 << getLoadcntBitWidth(
Version.Major)) - 1;
1368 return (1 << getSamplecntBitWidth(
Version.Major)) - 1;
1372 return (1 << getBvhcntBitWidth(
Version.Major)) - 1;
1376 return (1 << getExpcntBitWidth(
Version.Major)) - 1;
1380 return (1 << getLgkmcntBitWidth(
Version.Major)) - 1;
1384 return (1 << getDscntBitWidth(
Version.Major)) - 1;
1388 return (1 << getKmcntBitWidth(
Version.Major)) - 1;
1392 return (1 << getStorecntBitWidth(
Version.Major)) - 1;
1396 unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(
Version.Major),
1397 getVmcntBitWidthLo(
Version.Major));
1398 unsigned Expcnt = getBitMask(getExpcntBitShift(
Version.Major),
1399 getExpcntBitWidth(
Version.Major));
1400 unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(
Version.Major),
1401 getLgkmcntBitWidth(
Version.Major));
1402 unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(
Version.Major),
1403 getVmcntBitWidthHi(
Version.Major));
1404 return VmcntLo | Expcnt | Lgkmcnt | VmcntHi;
1408 unsigned VmcntLo = unpackBits(
Waitcnt, getVmcntBitShiftLo(
Version.Major),
1409 getVmcntBitWidthLo(
Version.Major));
1410 unsigned VmcntHi = unpackBits(
Waitcnt, getVmcntBitShiftHi(
Version.Major),
1411 getVmcntBitWidthHi(
Version.Major));
1412 return VmcntLo | VmcntHi << getVmcntBitWidthLo(
Version.Major);
1417 getExpcntBitWidth(
Version.Major));
1422 getLgkmcntBitWidth(
Version.Major));
1426 unsigned &Vmcnt,
unsigned &Expcnt,
unsigned &Lgkmcnt) {
1443 getVmcntBitWidthLo(
Version.Major));
1444 return packBits(Vmcnt >> getVmcntBitWidthLo(
Version.Major),
Waitcnt,
1445 getVmcntBitShiftHi(
Version.Major),
1446 getVmcntBitWidthHi(
Version.Major));
1451 return packBits(Expcnt,
Waitcnt, getExpcntBitShift(
Version.Major),
1452 getExpcntBitWidth(
Version.Major));
1457 return packBits(Lgkmcnt,
Waitcnt, getLgkmcntBitShift(
Version.Major),
1458 getLgkmcntBitWidth(
Version.Major));
1462 unsigned Vmcnt,
unsigned Expcnt,
unsigned Lgkmcnt) {
1476 unsigned Dscnt = getBitMask(getDscntBitShift(
Version.Major),
1477 getDscntBitWidth(
Version.Major));
1479 unsigned Storecnt = getBitMask(getLoadcntStorecntBitShift(
Version.Major),
1480 getStorecntBitWidth(
Version.Major));
1481 return Dscnt | Storecnt;
1483 unsigned Loadcnt = getBitMask(getLoadcntStorecntBitShift(
Version.Major),
1484 getLoadcntBitWidth(
Version.Major));
1485 return Dscnt | Loadcnt;
1492 unpackBits(LoadcntDscnt, getLoadcntStorecntBitShift(
Version.Major),
1493 getLoadcntBitWidth(
Version.Major));
1494 Decoded.
DsCnt = unpackBits(LoadcntDscnt, getDscntBitShift(
Version.Major),
1495 getDscntBitWidth(
Version.Major));
1502 unpackBits(StorecntDscnt, getLoadcntStorecntBitShift(
Version.Major),
1503 getStorecntBitWidth(
Version.Major));
1504 Decoded.
DsCnt = unpackBits(StorecntDscnt, getDscntBitShift(
Version.Major),
1505 getDscntBitWidth(
Version.Major));
1511 return packBits(Loadcnt,
Waitcnt, getLoadcntStorecntBitShift(
Version.Major),
1512 getLoadcntBitWidth(
Version.Major));
1516 unsigned Storecnt) {
1517 return packBits(Storecnt,
Waitcnt, getLoadcntStorecntBitShift(
Version.Major),
1518 getStorecntBitWidth(
Version.Major));
1524 getDscntBitWidth(
Version.Major));
1540 unsigned Storecnt,
unsigned Dscnt) {
1561 const auto &
Op = Opr[
Idx];
1562 if (
Op.isSupported(STI))
1563 Enc |=
Op.encode(
Op.Default);
1569 int Size,
unsigned Code,
1570 bool &HasNonDefaultVal,
1572 unsigned UsedOprMask = 0;
1573 HasNonDefaultVal =
false;
1575 const auto &
Op = Opr[
Idx];
1576 if (!
Op.isSupported(STI))
1578 UsedOprMask |=
Op.getMask();
1579 unsigned Val =
Op.decode(Code);
1580 if (!
Op.isValid(Val))
1582 HasNonDefaultVal |= (Val !=
Op.Default);
1584 return (Code & ~UsedOprMask) == 0;
1589 unsigned &Val,
bool &IsDefault,
1592 const auto &
Op = Opr[
Idx++];
1593 if (
Op.isSupported(STI)) {
1595 Val =
Op.decode(Code);
1596 IsDefault = (Val ==
Op.Default);
1606 if (InputVal < 0 || InputVal >
Op.Max)
1608 return Op.encode(InputVal);
1613 unsigned &UsedOprMask,
1617 const auto &
Op = Opr[
Idx];
1619 if (!
Op.isSupported(STI)) {
1623 auto OprMask =
Op.getMask();
1624 if (OprMask & UsedOprMask)
1626 UsedOprMask |= OprMask;
1649 HasNonDefaultVal, STI);
1665 return unpackBits(Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1669 return unpackBits(Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1673 return unpackBits(Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1677 return packBits(VmVsrc, Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1685 return packBits(VaVdst, Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1693 return packBits(SaSdst, Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1726 if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1727 Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1738 if (Val.MaxIndex == 0 &&
Name == Val.Name)
1741 if (Val.MaxIndex > 0 &&
Name.starts_with(Val.Name)) {
1749 if (Suffix.
size() > 1 && Suffix[0] ==
'0')
1752 return Val.Tgt + Id;
1781namespace MTBUFFormat {
1807 if (
Name == lookupTable[Id])
1911 return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1981 return F.getFnAttributeAsParsedInteger(
"InitialPSInputAddr", 0);
1986 return F.getFnAttributeAsParsedInteger(
1987 "amdgpu-color-export",
1992 return F.getFnAttributeAsParsedInteger(
"amdgpu-depth-export", 0) != 0;
2065 return STI.
hasFeature(AMDGPU::FeatureSRAMECC);
2081 return !STI.
hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !
isCI(STI) &&
2092 return Version.Minor >= 3 ? 13 : 5;
2096 return HasSampler ? 4 : 5;
2103 return STI.
hasFeature(AMDGPU::FeatureSouthernIslands);
2107 return STI.
hasFeature(AMDGPU::FeatureSeaIslands);
2111 return STI.
hasFeature(AMDGPU::FeatureVolcanicIslands);
2181 return STI.
hasFeature(AMDGPU::FeatureGCN3Encoding);
2185 return STI.
hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2189 return STI.
hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2193 return STI.
hasFeature(AMDGPU::FeatureGFX10_3Insts);
2201 return STI.
hasFeature(AMDGPU::FeatureGFX90AInsts);
2205 return STI.
hasFeature(AMDGPU::FeatureGFX940Insts);
2209 return STI.
hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2213 return STI.
hasFeature(AMDGPU::FeatureMAIInsts);
2221 return STI.
hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2225 return STI.
hasFeature(AMDGPU::FeatureKernargPreload);
2229 int32_t ArgNumVGPR) {
2230 if (has90AInsts && ArgNumAGPR)
2231 return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
2232 return std::max(ArgNumVGPR, ArgNumAGPR);
2237 const unsigned FirstSubReg =
TRI->getSubReg(
Reg, AMDGPU::sub0);
2238 return SGPRClass.
contains(FirstSubReg != 0 ? FirstSubReg :
Reg) ||
2246#define MAP_REG2REG \
2247 using namespace AMDGPU; \
2249 default: return Reg; \
2250 CASE_CI_VI(FLAT_SCR) \
2251 CASE_CI_VI(FLAT_SCR_LO) \
2252 CASE_CI_VI(FLAT_SCR_HI) \
2253 CASE_VI_GFX9PLUS(TTMP0) \
2254 CASE_VI_GFX9PLUS(TTMP1) \
2255 CASE_VI_GFX9PLUS(TTMP2) \
2256 CASE_VI_GFX9PLUS(TTMP3) \
2257 CASE_VI_GFX9PLUS(TTMP4) \
2258 CASE_VI_GFX9PLUS(TTMP5) \
2259 CASE_VI_GFX9PLUS(TTMP6) \
2260 CASE_VI_GFX9PLUS(TTMP7) \
2261 CASE_VI_GFX9PLUS(TTMP8) \
2262 CASE_VI_GFX9PLUS(TTMP9) \
2263 CASE_VI_GFX9PLUS(TTMP10) \
2264 CASE_VI_GFX9PLUS(TTMP11) \
2265 CASE_VI_GFX9PLUS(TTMP12) \
2266 CASE_VI_GFX9PLUS(TTMP13) \
2267 CASE_VI_GFX9PLUS(TTMP14) \
2268 CASE_VI_GFX9PLUS(TTMP15) \
2269 CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
2270 CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
2271 CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
2272 CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
2273 CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
2274 CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
2275 CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
2276 CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
2277 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
2278 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
2279 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
2280 CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
2281 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
2282 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
2283 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2284 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2285 CASE_GFXPRE11_GFX11PLUS(M0) \
2286 CASE_GFXPRE11_GFX11PLUS(SGPR_NULL) \
2287 CASE_GFXPRE11_GFX11PLUS_TO(SGPR_NULL64, SGPR_NULL) \
2290#define CASE_CI_VI(node) \
2291 assert(!isSI(STI)); \
2292 case node: return isCI(STI) ? node##_ci : node##_vi;
2294#define CASE_VI_GFX9PLUS(node) \
2295 case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
2297#define CASE_GFXPRE11_GFX11PLUS(node) \
2298 case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
2300#define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
2301 case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
2310#undef CASE_VI_GFX9PLUS
2311#undef CASE_GFXPRE11_GFX11PLUS
2312#undef CASE_GFXPRE11_GFX11PLUS_TO
2314#define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
2315#define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
2316#define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
2317#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
2325 case AMDGPU::SRC_SHARED_BASE_LO:
2326 case AMDGPU::SRC_SHARED_BASE:
2327 case AMDGPU::SRC_SHARED_LIMIT_LO:
2328 case AMDGPU::SRC_SHARED_LIMIT:
2329 case AMDGPU::SRC_PRIVATE_BASE_LO:
2330 case AMDGPU::SRC_PRIVATE_BASE:
2331 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
2332 case AMDGPU::SRC_PRIVATE_LIMIT:
2333 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
2335 case AMDGPU::SRC_VCCZ:
2336 case AMDGPU::SRC_EXECZ:
2337 case AMDGPU::SRC_SCC:
2339 case AMDGPU::SGPR_NULL:
2347#undef CASE_VI_GFX9PLUS
2348#undef CASE_GFXPRE11_GFX11PLUS
2349#undef CASE_GFXPRE11_GFX11PLUS_TO
2354 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2361 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2368 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2394 unsigned OpType =
Desc.operands()[OpNo].OperandType;
2405 case AMDGPU::SGPR_LO16RegClassID:
2406 case AMDGPU::AGPR_LO16RegClassID:
2408 case AMDGPU::SGPR_32RegClassID:
2409 case AMDGPU::VGPR_32RegClassID:
2410 case AMDGPU::VRegOrLds_32RegClassID:
2411 case AMDGPU::AGPR_32RegClassID:
2412 case AMDGPU::VS_32RegClassID:
2413 case AMDGPU::AV_32RegClassID:
2414 case AMDGPU::SReg_32RegClassID:
2415 case AMDGPU::SReg_32_XM0RegClassID:
2416 case AMDGPU::SRegOrLds_32RegClassID:
2418 case AMDGPU::SGPR_64RegClassID:
2419 case AMDGPU::VS_64RegClassID:
2420 case AMDGPU::SReg_64RegClassID:
2421 case AMDGPU::VReg_64RegClassID:
2422 case AMDGPU::AReg_64RegClassID:
2423 case AMDGPU::SReg_64_XEXECRegClassID:
2424 case AMDGPU::VReg_64_Align2RegClassID:
2425 case AMDGPU::AReg_64_Align2RegClassID:
2426 case AMDGPU::AV_64RegClassID:
2427 case AMDGPU::AV_64_Align2RegClassID:
2429 case AMDGPU::SGPR_96RegClassID:
2430 case AMDGPU::SReg_96RegClassID:
2431 case AMDGPU::VReg_96RegClassID:
2432 case AMDGPU::AReg_96RegClassID:
2433 case AMDGPU::VReg_96_Align2RegClassID:
2434 case AMDGPU::AReg_96_Align2RegClassID:
2435 case AMDGPU::AV_96RegClassID:
2436 case AMDGPU::AV_96_Align2RegClassID:
2438 case AMDGPU::SGPR_128RegClassID:
2439 case AMDGPU::SReg_128RegClassID:
2440 case AMDGPU::VReg_128RegClassID:
2441 case AMDGPU::AReg_128RegClassID:
2442 case AMDGPU::VReg_128_Align2RegClassID:
2443 case AMDGPU::AReg_128_Align2RegClassID:
2444 case AMDGPU::AV_128RegClassID:
2445 case AMDGPU::AV_128_Align2RegClassID:
2447 case AMDGPU::SGPR_160RegClassID:
2448 case AMDGPU::SReg_160RegClassID:
2449 case AMDGPU::VReg_160RegClassID:
2450 case AMDGPU::AReg_160RegClassID:
2451 case AMDGPU::VReg_160_Align2RegClassID:
2452 case AMDGPU::AReg_160_Align2RegClassID:
2453 case AMDGPU::AV_160RegClassID:
2454 case AMDGPU::AV_160_Align2RegClassID:
2456 case AMDGPU::SGPR_192RegClassID:
2457 case AMDGPU::SReg_192RegClassID:
2458 case AMDGPU::VReg_192RegClassID:
2459 case AMDGPU::AReg_192RegClassID:
2460 case AMDGPU::VReg_192_Align2RegClassID:
2461 case AMDGPU::AReg_192_Align2RegClassID:
2462 case AMDGPU::AV_192RegClassID:
2463 case AMDGPU::AV_192_Align2RegClassID:
2465 case AMDGPU::SGPR_224RegClassID:
2466 case AMDGPU::SReg_224RegClassID:
2467 case AMDGPU::VReg_224RegClassID:
2468 case AMDGPU::AReg_224RegClassID:
2469 case AMDGPU::VReg_224_Align2RegClassID:
2470 case AMDGPU::AReg_224_Align2RegClassID:
2471 case AMDGPU::AV_224RegClassID:
2472 case AMDGPU::AV_224_Align2RegClassID:
2474 case AMDGPU::SGPR_256RegClassID:
2475 case AMDGPU::SReg_256RegClassID:
2476 case AMDGPU::VReg_256RegClassID:
2477 case AMDGPU::AReg_256RegClassID:
2478 case AMDGPU::VReg_256_Align2RegClassID:
2479 case AMDGPU::AReg_256_Align2RegClassID:
2480 case AMDGPU::AV_256RegClassID:
2481 case AMDGPU::AV_256_Align2RegClassID:
2483 case AMDGPU::SGPR_288RegClassID:
2484 case AMDGPU::SReg_288RegClassID:
2485 case AMDGPU::VReg_288RegClassID:
2486 case AMDGPU::AReg_288RegClassID:
2487 case AMDGPU::VReg_288_Align2RegClassID:
2488 case AMDGPU::AReg_288_Align2RegClassID:
2489 case AMDGPU::AV_288RegClassID:
2490 case AMDGPU::AV_288_Align2RegClassID:
2492 case AMDGPU::SGPR_320RegClassID:
2493 case AMDGPU::SReg_320RegClassID:
2494 case AMDGPU::VReg_320RegClassID:
2495 case AMDGPU::AReg_320RegClassID:
2496 case AMDGPU::VReg_320_Align2RegClassID:
2497 case AMDGPU::AReg_320_Align2RegClassID:
2498 case AMDGPU::AV_320RegClassID:
2499 case AMDGPU::AV_320_Align2RegClassID:
2501 case AMDGPU::SGPR_352RegClassID:
2502 case AMDGPU::SReg_352RegClassID:
2503 case AMDGPU::VReg_352RegClassID:
2504 case AMDGPU::AReg_352RegClassID:
2505 case AMDGPU::VReg_352_Align2RegClassID:
2506 case AMDGPU::AReg_352_Align2RegClassID:
2507 case AMDGPU::AV_352RegClassID:
2508 case AMDGPU::AV_352_Align2RegClassID:
2510 case AMDGPU::SGPR_384RegClassID:
2511 case AMDGPU::SReg_384RegClassID:
2512 case AMDGPU::VReg_384RegClassID:
2513 case AMDGPU::AReg_384RegClassID:
2514 case AMDGPU::VReg_384_Align2RegClassID:
2515 case AMDGPU::AReg_384_Align2RegClassID:
2516 case AMDGPU::AV_384RegClassID:
2517 case AMDGPU::AV_384_Align2RegClassID:
2519 case AMDGPU::SGPR_512RegClassID:
2520 case AMDGPU::SReg_512RegClassID:
2521 case AMDGPU::VReg_512RegClassID:
2522 case AMDGPU::AReg_512RegClassID:
2523 case AMDGPU::VReg_512_Align2RegClassID:
2524 case AMDGPU::AReg_512_Align2RegClassID:
2525 case AMDGPU::AV_512RegClassID:
2526 case AMDGPU::AV_512_Align2RegClassID:
2528 case AMDGPU::SGPR_1024RegClassID:
2529 case AMDGPU::SReg_1024RegClassID:
2530 case AMDGPU::VReg_1024RegClassID:
2531 case AMDGPU::AReg_1024RegClassID:
2532 case AMDGPU::VReg_1024_Align2RegClassID:
2533 case AMDGPU::AReg_1024_Align2RegClassID:
2534 case AMDGPU::AV_1024RegClassID:
2535 case AMDGPU::AV_1024_Align2RegClassID:
2549 unsigned RCID =
Desc.operands()[OpNo].RegClass;
2558 return (Val == llvm::bit_cast<uint64_t>(0.0)) ||
2559 (Val == llvm::bit_cast<uint64_t>(1.0)) ||
2560 (Val == llvm::bit_cast<uint64_t>(-1.0)) ||
2561 (Val == llvm::bit_cast<uint64_t>(0.5)) ||
2562 (Val == llvm::bit_cast<uint64_t>(-0.5)) ||
2563 (Val == llvm::bit_cast<uint64_t>(2.0)) ||
2564 (Val == llvm::bit_cast<uint64_t>(-2.0)) ||
2565 (Val == llvm::bit_cast<uint64_t>(4.0)) ||
2566 (Val == llvm::bit_cast<uint64_t>(-4.0)) ||
2567 (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
2584 return (Val == llvm::bit_cast<uint32_t>(0.0f)) ||
2585 (Val == llvm::bit_cast<uint32_t>(1.0f)) ||
2586 (Val == llvm::bit_cast<uint32_t>(-1.0f)) ||
2587 (Val == llvm::bit_cast<uint32_t>(0.5f)) ||
2588 (Val == llvm::bit_cast<uint32_t>(-0.5f)) ||
2589 (Val == llvm::bit_cast<uint32_t>(2.0f)) ||
2590 (Val == llvm::bit_cast<uint32_t>(-2.0f)) ||
2591 (Val == llvm::bit_cast<uint32_t>(4.0f)) ||
2592 (Val == llvm::bit_cast<uint32_t>(-4.0f)) ||
2593 (Val == 0x3e22f983 && HasInv2Pi);
2602 return Val == 0x3F00 ||
2623 return Val == 0x3C00 ||
2650 return 192 + std::abs(
Signed);
2655 case 0x3800:
return 240;
2656 case 0xB800:
return 241;
2657 case 0x3C00:
return 242;
2658 case 0xBC00:
return 243;
2659 case 0x4000:
return 244;
2660 case 0xC000:
return 245;
2661 case 0x4400:
return 246;
2662 case 0xC400:
return 247;
2663 case 0x3118:
return 248;
2670 case 0x3F000000:
return 240;
2671 case 0xBF000000:
return 241;
2672 case 0x3F800000:
return 242;
2673 case 0xBF800000:
return 243;
2674 case 0x40000000:
return 244;
2675 case 0xC0000000:
return 245;
2676 case 0x40800000:
return 246;
2677 case 0xC0800000:
return 247;
2678 case 0x3E22F983:
return 248;
2701 return 192 + std::abs(
Signed);
2705 case 0x3F00:
return 240;
2706 case 0xBF00:
return 241;
2707 case 0x3F80:
return 242;
2708 case 0xBF80:
return 243;
2709 case 0x4000:
return 244;
2710 case 0xC000:
return 245;
2711 case 0x4080:
return 246;
2712 case 0xC080:
return 247;
2713 case 0x3E22:
return 248;
2718 return std::nullopt;
2764 return !(Val & 0xffffffffu);
2766 return isUInt<32>(Val) || isInt<32>(Val);
2790 return A->hasAttribute(Attribute::InReg) ||
2791 A->hasAttribute(Attribute::ByVal);
2794 return A->hasAttribute(Attribute::InReg);
2829 int64_t EncodedOffset) {
2831 return isUInt<23>(EncodedOffset);
2834 : isUInt<8>(EncodedOffset);
2838 int64_t EncodedOffset,
2841 return isInt<24>(EncodedOffset);
2845 isInt<21>(EncodedOffset);
2849 return (ByteOffset & 3) == 0;
2858 return ByteOffset >> 2;
2862 int64_t ByteOffset,
bool IsBuffer,
2868 return std::nullopt;
2871 return isInt<24>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2877 return isInt<20>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2882 return std::nullopt;
2886 ? std::optional<int64_t>(EncodedOffset)
2891 int64_t ByteOffset) {
2893 return std::nullopt;
2896 return isUInt<32>(EncodedOffset) ? std::optional<int64_t>(EncodedOffset)
2911struct SourceOfDivergence {
2914const SourceOfDivergence *lookupSourceOfDivergence(
unsigned Intr);
2921#define GET_SourcesOfDivergence_IMPL
2922#define GET_UniformIntrinsics_IMPL
2923#define GET_Gfx9BufferFormat_IMPL
2924#define GET_Gfx10BufferFormat_IMPL
2925#define GET_Gfx11PlusBufferFormat_IMPL
2926#include "AMDGPUGenSearchableTables.inc"
2931 return lookupSourceOfDivergence(IntrID);
2935 return lookupAlwaysUniform(IntrID);
2939 uint8_t NumComponents,
2943 ? getGfx11PlusBufferFormatInfo(BitsPerComp, NumComponents,
2945 :
isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
2946 NumComponents, NumFormat)
2947 : getGfx9BufferFormatInfo(BitsPerComp,
2948 NumComponents, NumFormat);
2955 : getGfx9BufferFormatInfo(
Format);
2959 for (
auto OpName : { OpName::vdst, OpName::src0, OpName::src1,
2965 if (OpDesc.
operands()[
Idx].RegClass == AMDGPU::VReg_64RegClassID ||
2966 OpDesc.
operands()[
Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)
2988 OS <<
"Unsupported";
unsigned const MachineRegisterInfo * MRI
static llvm::cl::opt< unsigned > DefaultAMDHSACodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5), llvm::cl::desc("Set default AMDHSA Code Object Version (module flag " "or asm directive still take priority if present)"))
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
MC layer struct for AMDGPUMCKernelCodeT, provides MCExpr functionality where required.
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
This file contains the simple types necessary to represent the attributes associated with functions a...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
#define S_00B848_MEM_ORDERED(x)
#define S_00B848_WGP_MODE(x)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isSramEccSupported() const
void setTargetIDFromFeaturesString(StringRef FS)
TargetIDSetting getXnackSetting() const
AMDGPUTargetID(const MCSubtargetInfo &STI)
bool isXnackSupported() const
void setTargetIDFromTargetIDStream(StringRef TargetID)
std::string toString() const
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
unsigned getIndexOfDstInParsedOperands() const
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
unsigned getCompParsedSrcOperandsNum() const
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
This class represents an incoming formal argument to a Function.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
CallingConv::ID getCallingConv() const
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Determine whether the argument or parameter has the given attribute.
This class represents an Operation in the Expression.
constexpr bool test(unsigned I) const
unsigned getAddressSpace() const
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
const FeatureBitset & getFeatureBits() const
A Module instance is used to store all the information related to an LLVM module.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
std::string str() const
str - Get the contents as an std::string.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Manages the enabling and disabling of subtarget specific features.
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Triple - Helper class for working with autoconf configuration names.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
@ LOCAL_ADDRESS
Address space for local memory.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
const CustomOperandVal DepCtrInfo[]
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
static constexpr ExpTgt ExpTgtInfo[]
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
@ ET_DUAL_SRC_BLEND_MAX_IDX
constexpr uint32_t VersionMajor
HSA metadata major version.
@ COMPLETION_ACTION_OFFSET
@ MULTIGRID_SYNC_ARG_OFFSET
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen)
static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs, unsigned Granule)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
StringRef getMsgOpName(int64_t MsgId, uint64_t Encoding, const MCSubtargetInfo &STI)
Map from an encoding to the symbolic name for a sendmsg operation.
static uint64_t getMsgIdMask(const MCSubtargetInfo &STI)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
SmallVector< unsigned > getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size)
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
static unsigned encodeStorecnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
const int OPR_ID_UNSUPPORTED
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
int getMTBUFElements(unsigned Opc)
static int encodeCustomOperandVal(const CustomOperandVal &Op, int64_t InputVal)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV216(bool IsFloat, uint32_t Literal)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
CanBeVOPD getCanBeVOPD(unsigned Opc)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
const int OPR_VAL_INVALID
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
bool isInvalidSingleUseProducerInst(unsigned Opc)
bool isInvalidSingleUseConsumerInst(unsigned Opc)
bool isGroupSegment(const GlobalValue *GV)
IsaVersion getIsaVersion(StringRef GPU)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
static unsigned getCombinedCountBitMask(const IsaVersion &Version, bool IsStore)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
static bool isDwordAligned(uint64_t ByteOffset)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
unsigned getKmcntBitMask(const IsaVersion &Version)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFTfe(unsigned Opc)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool isHi(unsigned Reg, const MCRegisterInfo &MRI)
unsigned getBvhcntBitMask(const IsaVersion &Version)
bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
static unsigned encodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset)
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
@ OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_V2BF16
@ OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_FIRST
@ OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_V2BF16
@ OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_AC_LAST
@ OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
void initDefaultAMDKernelCodeT(AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI)
bool isNotGFX9Plus(const MCSubtargetInfo &STI)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
const int OPR_ID_DUPLICATE
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
bool getMUBUFIsBufferInv(unsigned Opc)
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
static int encodeCustomOperand(const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
static unsigned encodeDscnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
@ AMDGPU_Gfx
Used for AMD graphics targets.
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
@ SPIR_KERNEL
Used for SPIR kernel functions.
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
@ ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V5
@ ELFABIVERSION_AMDGPU_HSA_V6
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
@ AlwaysUniform
The result values are always uniform.
@ Default
The result values are uniform if and only if all operands are uniform.
AMD Kernel Code Object (amd_kernel_code_t).
uint16_t amd_machine_version_major
uint16_t amd_machine_kind
uint16_t amd_machine_version_stepping
uint8_t private_segment_alignment
int64_t kernel_code_entry_byte_offset
uint32_t amd_kernel_code_version_major
uint16_t amd_machine_version_minor
uint8_t group_segment_alignment
uint8_t kernarg_segment_alignment
uint32_t amd_kernel_code_version_minor
uint64_t compute_pgm_resource_registers
Instruction set architecture version.
bool IsInvalidSingleUseConsumer
bool IsInvalidSingleUseProducer
Represents the counter values to wait for in an s_waitcnt instruction.
Description of the encoding of one expression Op.