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AMDGPUBaseInfo.cpp
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1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "AMDGPUBaseInfo.h"
10 #include "AMDGPU.h"
11 #include "AMDGPUAsmUtils.h"
12 #include "AMDKernelCodeT.h"
13 #include "GCNSubtarget.h"
15 #include "llvm/BinaryFormat/ELF.h"
16 #include "llvm/IR/Attributes.h"
17 #include "llvm/IR/Function.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/IR/IntrinsicsAMDGPU.h"
20 #include "llvm/IR/IntrinsicsR600.h"
21 #include "llvm/IR/LLVMContext.h"
26 
27 #define GET_INSTRINFO_NAMED_OPS
28 #define GET_INSTRMAP_INFO
29 #include "AMDGPUGenInstrInfo.inc"
30 
32  AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden,
33  llvm::cl::desc("AMDHSA Code Object Version"),
34  llvm::cl::init(4));
35 
36 // TODO-GFX11: Remove this when full 16-bit codegen is implemented.
38  LimitTo128VGPRs("amdgpu-limit-to-128-vgprs", llvm::cl::Hidden,
39  llvm::cl::desc("Never use more than 128 VGPRs"));
40 
41 namespace {
42 
43 /// \returns Bit mask for given bit \p Shift and bit \p Width.
44 unsigned getBitMask(unsigned Shift, unsigned Width) {
45  return ((1 << Width) - 1) << Shift;
46 }
47 
48 /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
49 ///
50 /// \returns Packed \p Dst.
51 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
52  unsigned Mask = getBitMask(Shift, Width);
53  return ((Src << Shift) & Mask) | (Dst & ~Mask);
54 }
55 
56 /// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
57 ///
58 /// \returns Unpacked bits.
59 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
60  return (Src & getBitMask(Shift, Width)) >> Shift;
61 }
62 
63 /// \returns Vmcnt bit shift (lower bits).
64 unsigned getVmcntBitShiftLo(unsigned VersionMajor) {
65  return VersionMajor >= 11 ? 10 : 0;
66 }
67 
68 /// \returns Vmcnt bit width (lower bits).
69 unsigned getVmcntBitWidthLo(unsigned VersionMajor) {
70  return VersionMajor >= 11 ? 6 : 4;
71 }
72 
73 /// \returns Expcnt bit shift.
74 unsigned getExpcntBitShift(unsigned VersionMajor) {
75  return VersionMajor >= 11 ? 0 : 4;
76 }
77 
78 /// \returns Expcnt bit width.
79 unsigned getExpcntBitWidth(unsigned VersionMajor) { return 3; }
80 
81 /// \returns Lgkmcnt bit shift.
82 unsigned getLgkmcntBitShift(unsigned VersionMajor) {
83  return VersionMajor >= 11 ? 4 : 8;
84 }
85 
86 /// \returns Lgkmcnt bit width.
87 unsigned getLgkmcntBitWidth(unsigned VersionMajor) {
88  return VersionMajor >= 10 ? 6 : 4;
89 }
90 
91 /// \returns Vmcnt bit shift (higher bits).
92 unsigned getVmcntBitShiftHi(unsigned VersionMajor) { return 14; }
93 
94 /// \returns Vmcnt bit width (higher bits).
95 unsigned getVmcntBitWidthHi(unsigned VersionMajor) {
96  return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0;
97 }
98 
99 } // end namespace anonymous
100 
101 namespace llvm {
102 
103 namespace AMDGPU {
104 
106  if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA)
107  return None;
108 
109  switch (AmdhsaCodeObjectVersion) {
110  case 2:
112  case 3:
114  case 4:
116  case 5:
118  default:
119  report_fatal_error(Twine("Unsupported AMDHSA Code Object Version ") +
121  }
122 }
123 
125  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
126  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V2;
127  return false;
128 }
129 
131  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
132  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V3;
133  return false;
134 }
135 
137  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
138  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V4;
139  return false;
140 }
141 
143  if (Optional<uint8_t> HsaAbiVer = getHsaAbiVersion(STI))
144  return *HsaAbiVer == ELF::ELFABIVERSION_AMDGPU_HSA_V5;
145  return false;
146 }
147 
149  return isHsaAbiVersion3(STI) || isHsaAbiVersion4(STI) ||
150  isHsaAbiVersion5(STI);
151 }
152 
155 }
156 
158  switch (AmdhsaCodeObjectVersion) {
159  case 2:
160  case 3:
161  case 4:
162  return 48;
163  case 5:
165  default:
166  llvm_unreachable("Unexpected code object version");
167  return 0;
168  }
169 }
170 
171 
172 // FIXME: All such magic numbers about the ABI should be in a
173 // central TD file.
175  switch (AmdhsaCodeObjectVersion) {
176  case 2:
177  case 3:
178  case 4:
179  return 24;
180  case 5:
182  default:
183  llvm_unreachable("Unexpected code object version");
184  return 0;
185  }
186 }
187 
188 #define GET_MIMGBaseOpcodesTable_IMPL
189 #define GET_MIMGDimInfoTable_IMPL
190 #define GET_MIMGInfoTable_IMPL
191 #define GET_MIMGLZMappingTable_IMPL
192 #define GET_MIMGMIPMappingTable_IMPL
193 #define GET_MIMGBiasMappingTable_IMPL
194 #define GET_MIMGOffsetMappingTable_IMPL
195 #define GET_MIMGG16MappingTable_IMPL
196 #define GET_MAIInstInfoTable_IMPL
197 #include "AMDGPUGenSearchableTables.inc"
198 
199 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
200  unsigned VDataDwords, unsigned VAddrDwords) {
201  const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
202  VDataDwords, VAddrDwords);
203  return Info ? Info->Opcode : -1;
204 }
205 
206 const MIMGBaseOpcodeInfo *getMIMGBaseOpcode(unsigned Opc) {
207  const MIMGInfo *Info = getMIMGInfo(Opc);
208  return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr;
209 }
210 
211 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) {
212  const MIMGInfo *OrigInfo = getMIMGInfo(Opc);
213  const MIMGInfo *NewInfo =
214  getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
215  NewChannels, OrigInfo->VAddrDwords);
216  return NewInfo ? NewInfo->Opcode : -1;
217 }
218 
219 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
220  const MIMGDimInfo *Dim, bool IsA16,
221  bool IsG16Supported) {
222  unsigned AddrWords = BaseOpcode->NumExtraArgs;
223  unsigned AddrComponents = (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
224  (BaseOpcode->LodOrClampOrMip ? 1 : 0);
225  if (IsA16)
226  AddrWords += divideCeil(AddrComponents, 2);
227  else
228  AddrWords += AddrComponents;
229 
230  // Note: For subtargets that support A16 but not G16, enabling A16 also
231  // enables 16 bit gradients.
232  // For subtargets that support A16 (operand) and G16 (done with a different
233  // instruction encoding), they are independent.
234 
235  if (BaseOpcode->Gradients) {
236  if ((IsA16 && !IsG16Supported) || BaseOpcode->G16)
237  // There are two gradients per coordinate, we pack them separately.
238  // For the 3d case,
239  // we get (dy/du, dx/du) (-, dz/du) (dy/dv, dx/dv) (-, dz/dv)
240  AddrWords += alignTo<2>(Dim->NumGradients / 2);
241  else
242  AddrWords += Dim->NumGradients;
243  }
244  return AddrWords;
245 }
246 
247 struct MUBUFInfo {
250  uint8_t elements;
251  bool has_vaddr;
252  bool has_srsrc;
255 };
256 
257 struct MTBUFInfo {
260  uint8_t elements;
261  bool has_vaddr;
262  bool has_srsrc;
264 };
265 
266 struct SMInfo {
268  bool IsBuffer;
269 };
270 
271 struct VOPInfo {
273  bool IsSingle;
274 };
275 
278 };
279 
284 };
285 
286 struct VOPDInfo {
290 };
291 
292 #define GET_MTBUFInfoTable_DECL
293 #define GET_MTBUFInfoTable_IMPL
294 #define GET_MUBUFInfoTable_DECL
295 #define GET_MUBUFInfoTable_IMPL
296 #define GET_SMInfoTable_DECL
297 #define GET_SMInfoTable_IMPL
298 #define GET_VOP1InfoTable_DECL
299 #define GET_VOP1InfoTable_IMPL
300 #define GET_VOP2InfoTable_DECL
301 #define GET_VOP2InfoTable_IMPL
302 #define GET_VOP3InfoTable_DECL
303 #define GET_VOP3InfoTable_IMPL
304 #define GET_VOPC64DPPTable_DECL
305 #define GET_VOPC64DPPTable_IMPL
306 #define GET_VOPC64DPP8Table_DECL
307 #define GET_VOPC64DPP8Table_IMPL
308 #define GET_VOPDComponentTable_DECL
309 #define GET_VOPDComponentTable_IMPL
310 #define GET_VOPDPairs_DECL
311 #define GET_VOPDPairs_IMPL
312 #define GET_WMMAOpcode2AddrMappingTable_DECL
313 #define GET_WMMAOpcode2AddrMappingTable_IMPL
314 #define GET_WMMAOpcode3AddrMappingTable_DECL
315 #define GET_WMMAOpcode3AddrMappingTable_IMPL
316 #include "AMDGPUGenSearchableTables.inc"
317 
318 int getMTBUFBaseOpcode(unsigned Opc) {
319  const MTBUFInfo *Info = getMTBUFInfoFromOpcode(Opc);
320  return Info ? Info->BaseOpcode : -1;
321 }
322 
323 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) {
324  const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
325  return Info ? Info->Opcode : -1;
326 }
327 
328 int getMTBUFElements(unsigned Opc) {
329  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
330  return Info ? Info->elements : 0;
331 }
332 
333 bool getMTBUFHasVAddr(unsigned Opc) {
334  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
335  return Info ? Info->has_vaddr : false;
336 }
337 
338 bool getMTBUFHasSrsrc(unsigned Opc) {
339  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
340  return Info ? Info->has_srsrc : false;
341 }
342 
343 bool getMTBUFHasSoffset(unsigned Opc) {
344  const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
345  return Info ? Info->has_soffset : false;
346 }
347 
348 int getMUBUFBaseOpcode(unsigned Opc) {
349  const MUBUFInfo *Info = getMUBUFInfoFromOpcode(Opc);
350  return Info ? Info->BaseOpcode : -1;
351 }
352 
353 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) {
354  const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
355  return Info ? Info->Opcode : -1;
356 }
357 
358 int getMUBUFElements(unsigned Opc) {
359  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
360  return Info ? Info->elements : 0;
361 }
362 
363 bool getMUBUFHasVAddr(unsigned Opc) {
364  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
365  return Info ? Info->has_vaddr : false;
366 }
367 
368 bool getMUBUFHasSrsrc(unsigned Opc) {
369  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
370  return Info ? Info->has_srsrc : false;
371 }
372 
373 bool getMUBUFHasSoffset(unsigned Opc) {
374  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
375  return Info ? Info->has_soffset : false;
376 }
377 
378 bool getMUBUFIsBufferInv(unsigned Opc) {
379  const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
380  return Info ? Info->IsBufferInv : false;
381 }
382 
383 bool getSMEMIsBuffer(unsigned Opc) {
384  const SMInfo *Info = getSMEMOpcodeHelper(Opc);
385  return Info ? Info->IsBuffer : false;
386 }
387 
388 bool getVOP1IsSingle(unsigned Opc) {
389  const VOPInfo *Info = getVOP1OpcodeHelper(Opc);
390  return Info ? Info->IsSingle : false;
391 }
392 
393 bool getVOP2IsSingle(unsigned Opc) {
394  const VOPInfo *Info = getVOP2OpcodeHelper(Opc);
395  return Info ? Info->IsSingle : false;
396 }
397 
398 bool getVOP3IsSingle(unsigned Opc) {
399  const VOPInfo *Info = getVOP3OpcodeHelper(Opc);
400  return Info ? Info->IsSingle : false;
401 }
402 
403 bool isVOPC64DPP(unsigned Opc) {
404  return isVOPC64DPPOpcodeHelper(Opc) || isVOPC64DPP8OpcodeHelper(Opc);
405 }
406 
407 bool getMAIIsDGEMM(unsigned Opc) {
408  const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
409  return Info ? Info->is_dgemm : false;
410 }
411 
412 bool getMAIIsGFX940XDL(unsigned Opc) {
413  const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
414  return Info ? Info->is_gfx940_xdl : false;
415 }
416 
417 CanBeVOPD getCanBeVOPD(unsigned Opc) {
418  const VOPDComponentInfo *Info = getVOPDComponentHelper(Opc);
419  if (Info)
420  return {Info->CanBeVOPDX, true};
421  else
422  return {false, false};
423 }
424 
425 unsigned getVOPDOpcode(unsigned Opc) {
426  const VOPDComponentInfo *Info = getVOPDComponentHelper(Opc);
427  return Info ? Info->VOPDOp : ~0u;
428 }
429 
430 bool isVOPD(unsigned Opc) {
431  return AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0X) != -1;
432 }
433 
434 unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc) {
435  const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom2AddrOpcode(Opc);
436  return Info ? Info->Opcode3Addr : ~0u;
437 }
438 
439 unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc) {
440  const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom3AddrOpcode(Opc);
441  return Info ? Info->Opcode2Addr : ~0u;
442 }
443 
444 // Wrapper for Tablegen'd function. enum Subtarget is not defined in any
445 // header files, so we need to wrap it in a function that takes unsigned
446 // instead.
447 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
448  return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
449 }
450 
451 int getVOPDFull(unsigned OpX, unsigned OpY) {
452  const VOPDInfo *Info = getVOPDInfoFromComponentOpcodes(OpX, OpY);
453  return Info ? Info->Opcode : -1;
454 }
455 
456 namespace IsaInfo {
457 
459  : STI(STI), XnackSetting(TargetIDSetting::Any),
460  SramEccSetting(TargetIDSetting::Any) {
461  if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
462  XnackSetting = TargetIDSetting::Unsupported;
463  if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
464  SramEccSetting = TargetIDSetting::Unsupported;
465 }
466 
468  // Check if xnack or sramecc is explicitly enabled or disabled. In the
469  // absence of the target features we assume we must generate code that can run
470  // in any environment.
471  SubtargetFeatures Features(FS);
472  Optional<bool> XnackRequested;
473  Optional<bool> SramEccRequested;
474 
475  for (const std::string &Feature : Features.getFeatures()) {
476  if (Feature == "+xnack")
477  XnackRequested = true;
478  else if (Feature == "-xnack")
479  XnackRequested = false;
480  else if (Feature == "+sramecc")
481  SramEccRequested = true;
482  else if (Feature == "-sramecc")
483  SramEccRequested = false;
484  }
485 
486  bool XnackSupported = isXnackSupported();
487  bool SramEccSupported = isSramEccSupported();
488 
489  if (XnackRequested) {
490  if (XnackSupported) {
491  XnackSetting =
492  *XnackRequested ? TargetIDSetting::On : TargetIDSetting::Off;
493  } else {
494  // If a specific xnack setting was requested and this GPU does not support
495  // xnack emit a warning. Setting will remain set to "Unsupported".
496  if (*XnackRequested) {
497  errs() << "warning: xnack 'On' was requested for a processor that does "
498  "not support it!\n";
499  } else {
500  errs() << "warning: xnack 'Off' was requested for a processor that "
501  "does not support it!\n";
502  }
503  }
504  }
505 
506  if (SramEccRequested) {
507  if (SramEccSupported) {
508  SramEccSetting =
509  *SramEccRequested ? TargetIDSetting::On : TargetIDSetting::Off;
510  } else {
511  // If a specific sramecc setting was requested and this GPU does not
512  // support sramecc emit a warning. Setting will remain set to
513  // "Unsupported".
514  if (*SramEccRequested) {
515  errs() << "warning: sramecc 'On' was requested for a processor that "
516  "does not support it!\n";
517  } else {
518  errs() << "warning: sramecc 'Off' was requested for a processor that "
519  "does not support it!\n";
520  }
521  }
522  }
523 }
524 
525 static TargetIDSetting
527  if (FeatureString.endswith("-"))
528  return TargetIDSetting::Off;
529  if (FeatureString.endswith("+"))
530  return TargetIDSetting::On;
531 
532  llvm_unreachable("Malformed feature string");
533 }
534 
536  SmallVector<StringRef, 3> TargetIDSplit;
537  TargetID.split(TargetIDSplit, ':');
538 
539  for (const auto &FeatureString : TargetIDSplit) {
540  if (FeatureString.startswith("xnack"))
541  XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);
542  if (FeatureString.startswith("sramecc"))
543  SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);
544  }
545 }
546 
547 std::string AMDGPUTargetID::toString() const {
548  std::string StringRep;
549  raw_string_ostream StreamRep(StringRep);
550 
551  auto TargetTriple = STI.getTargetTriple();
552  auto Version = getIsaVersion(STI.getCPU());
553 
554  StreamRep << TargetTriple.getArchName() << '-'
555  << TargetTriple.getVendorName() << '-'
556  << TargetTriple.getOSName() << '-'
557  << TargetTriple.getEnvironmentName() << '-';
558 
559  std::string Processor;
560  // TODO: Following else statement is present here because we used various
561  // alias names for GPUs up until GFX9 (e.g. 'fiji' is same as 'gfx803').
562  // Remove once all aliases are removed from GCNProcessors.td.
563  if (Version.Major >= 9)
564  Processor = STI.getCPU().str();
565  else
566  Processor = (Twine("gfx") + Twine(Version.Major) + Twine(Version.Minor) +
567  Twine(Version.Stepping))
568  .str();
569 
570  std::string Features;
571  if (Optional<uint8_t> HsaAbiVersion = getHsaAbiVersion(&STI)) {
572  switch (*HsaAbiVersion) {
574  // Code object V2 only supported specific processors and had fixed
575  // settings for the XNACK.
576  if (Processor == "gfx600") {
577  } else if (Processor == "gfx601") {
578  } else if (Processor == "gfx602") {
579  } else if (Processor == "gfx700") {
580  } else if (Processor == "gfx701") {
581  } else if (Processor == "gfx702") {
582  } else if (Processor == "gfx703") {
583  } else if (Processor == "gfx704") {
584  } else if (Processor == "gfx705") {
585  } else if (Processor == "gfx801") {
586  if (!isXnackOnOrAny())
588  "AMD GPU code object V2 does not support processor " +
589  Twine(Processor) + " without XNACK");
590  } else if (Processor == "gfx802") {
591  } else if (Processor == "gfx803") {
592  } else if (Processor == "gfx805") {
593  } else if (Processor == "gfx810") {
594  if (!isXnackOnOrAny())
596  "AMD GPU code object V2 does not support processor " +
597  Twine(Processor) + " without XNACK");
598  } else if (Processor == "gfx900") {
599  if (isXnackOnOrAny())
600  Processor = "gfx901";
601  } else if (Processor == "gfx902") {
602  if (isXnackOnOrAny())
603  Processor = "gfx903";
604  } else if (Processor == "gfx904") {
605  if (isXnackOnOrAny())
606  Processor = "gfx905";
607  } else if (Processor == "gfx906") {
608  if (isXnackOnOrAny())
609  Processor = "gfx907";
610  } else if (Processor == "gfx90c") {
611  if (isXnackOnOrAny())
613  "AMD GPU code object V2 does not support processor " +
614  Twine(Processor) + " with XNACK being ON or ANY");
615  } else {
617  "AMD GPU code object V2 does not support processor " +
618  Twine(Processor));
619  }
620  break;
622  // xnack.
623  if (isXnackOnOrAny())
624  Features += "+xnack";
625  // In code object v2 and v3, "sramecc" feature was spelled with a
626  // hyphen ("sram-ecc").
627  if (isSramEccOnOrAny())
628  Features += "+sram-ecc";
629  break;
632  // sramecc.
634  Features += ":sramecc-";
636  Features += ":sramecc+";
637  // xnack.
639  Features += ":xnack-";
640  else if (getXnackSetting() == TargetIDSetting::On)
641  Features += ":xnack+";
642  break;
643  default:
644  break;
645  }
646  }
647 
648  StreamRep << Processor << Features;
649 
650  StreamRep.flush();
651  return StringRep;
652 }
653 
654 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
655  if (STI->getFeatureBits().test(FeatureWavefrontSize16))
656  return 16;
657  if (STI->getFeatureBits().test(FeatureWavefrontSize32))
658  return 32;
659 
660  return 64;
661 }
662 
663 unsigned getLocalMemorySize(const MCSubtargetInfo *STI) {
664  if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
665  return 32768;
666  if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
667  return 65536;
668 
669  return 0;
670 }
671 
672 unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
673  // "Per CU" really means "per whatever functional block the waves of a
674  // workgroup must share". For gfx10 in CU mode this is the CU, which contains
675  // two SIMDs.
676  if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode))
677  return 2;
678  // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP contains
679  // two CUs, so a total of four SIMDs.
680  return 4;
681 }
682 
684  unsigned FlatWorkGroupSize) {
685  assert(FlatWorkGroupSize != 0);
686  if (STI->getTargetTriple().getArch() != Triple::amdgcn)
687  return 8;
688  unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
689  if (N == 1)
690  return 40;
691  N = 40 / N;
692  return std::min(N, 16u);
693 }
694 
695 unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
696  return 1;
697 }
698 
699 unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
700  // FIXME: Need to take scratch memory into account.
701  if (isGFX90A(*STI))
702  return 8;
703  if (!isGFX10Plus(*STI))
704  return 10;
705  return hasGFX10_3Insts(*STI) ? 16 : 20;
706 }
707 
709  unsigned FlatWorkGroupSize) {
710  return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
711  getEUsPerCU(STI));
712 }
713 
715  return 1;
716 }
717 
719  // Some subtargets allow encoding 2048, but this isn't tested or supported.
720  return 1024;
721 }
722 
724  unsigned FlatWorkGroupSize) {
725  return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
726 }
727 
728 unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI) {
730  if (Version.Major >= 10)
731  return getAddressableNumSGPRs(STI);
732  if (Version.Major >= 8)
733  return 16;
734  return 8;
735 }
736 
738  return 8;
739 }
740 
741 unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
743  if (Version.Major >= 8)
744  return 800;
745  return 512;
746 }
747 
749  if (STI->getFeatureBits().test(FeatureSGPRInitBug))
751 
753  if (Version.Major >= 10)
754  return 106;
755  if (Version.Major >= 8)
756  return 102;
757  return 104;
758 }
759 
760 unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
761  assert(WavesPerEU != 0);
762 
764  if (Version.Major >= 10)
765  return 0;
766 
767  if (WavesPerEU >= getMaxWavesPerEU(STI))
768  return 0;
769 
770  unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
771  if (STI->getFeatureBits().test(FeatureTrapHandler))
772  MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
773  MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
774  return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
775 }
776 
777 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
778  bool Addressable) {
779  assert(WavesPerEU != 0);
780 
781  unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
783  if (Version.Major >= 10)
784  return Addressable ? AddressableNumSGPRs : 108;
785  if (Version.Major >= 8 && !Addressable)
786  AddressableNumSGPRs = 112;
787  unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
788  if (STI->getFeatureBits().test(FeatureTrapHandler))
789  MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
790  MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
791  return std::min(MaxNumSGPRs, AddressableNumSGPRs);
792 }
793 
794 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
795  bool FlatScrUsed, bool XNACKUsed) {
796  unsigned ExtraSGPRs = 0;
797  if (VCCUsed)
798  ExtraSGPRs = 2;
799 
801  if (Version.Major >= 10)
802  return ExtraSGPRs;
803 
804  if (Version.Major < 8) {
805  if (FlatScrUsed)
806  ExtraSGPRs = 4;
807  } else {
808  if (XNACKUsed)
809  ExtraSGPRs = 4;
810 
811  if (FlatScrUsed ||
812  STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch))
813  ExtraSGPRs = 6;
814  }
815 
816  return ExtraSGPRs;
817 }
818 
819 unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
820  bool FlatScrUsed) {
821  return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
822  STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
823 }
824 
825 unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
827  // SGPRBlocks is actual number of SGPR blocks minus 1.
828  return NumSGPRs / getSGPREncodingGranule(STI) - 1;
829 }
830 
832  Optional<bool> EnableWavefrontSize32) {
833  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
834  return 8;
835 
836  bool IsWave32 = EnableWavefrontSize32 ?
837  *EnableWavefrontSize32 :
838  STI->getFeatureBits().test(FeatureWavefrontSize32);
839 
840  if (hasGFX10_3Insts(*STI))
841  return IsWave32 ? 16 : 8;
842 
843  return IsWave32 ? 8 : 4;
844 }
845 
847  Optional<bool> EnableWavefrontSize32) {
848  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
849  return 8;
850 
851  bool IsWave32 = EnableWavefrontSize32 ?
852  *EnableWavefrontSize32 :
853  STI->getFeatureBits().test(FeatureWavefrontSize32);
854 
855  return IsWave32 ? 8 : 4;
856 }
857 
858 unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
859  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
860  return 512;
861  if (!isGFX10Plus(*STI))
862  return 256;
863  return STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1024 : 512;
864 }
865 
868  : isGFX11Plus(*STI)) {
869  // GFX11 changes the encoding of 16-bit operands in VOP1/2/C instructions
870  // such that values 128..255 no longer mean v128..v255, they mean
871  // v0.hi..v127.hi instead. Until the compiler understands this, it is not
872  // safe to use v128..v255.
873  // TODO-GFX11: Remove this when full 16-bit codegen is implemented.
874  return 128;
875  }
876  if (STI->getFeatureBits().test(FeatureGFX90AInsts))
877  return 512;
878  return 256;
879 }
880 
881 unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
882  assert(WavesPerEU != 0);
883 
884  if (WavesPerEU >= getMaxWavesPerEU(STI))
885  return 0;
886  unsigned MinNumVGPRs =
887  alignDown(getTotalNumVGPRs(STI) / (WavesPerEU + 1),
888  getVGPRAllocGranule(STI)) + 1;
889  return std::min(MinNumVGPRs, getAddressableNumVGPRs(STI));
890 }
891 
892 unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
893  assert(WavesPerEU != 0);
894 
895  unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
896  getVGPRAllocGranule(STI));
897  unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
898  return std::min(MaxNumVGPRs, AddressableNumVGPRs);
899 }
900 
901 unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
902  Optional<bool> EnableWavefrontSize32) {
904  getVGPREncodingGranule(STI, EnableWavefrontSize32));
905  // VGPRBlocks is actual number of VGPR blocks minus 1.
906  return NumVGPRs / getVGPREncodingGranule(STI, EnableWavefrontSize32) - 1;
907 }
908 
909 } // end namespace IsaInfo
910 
912  const MCSubtargetInfo *STI) {
914 
915  memset(&Header, 0, sizeof(Header));
916 
919  Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
920  Header.amd_machine_version_major = Version.Major;
921  Header.amd_machine_version_minor = Version.Minor;
922  Header.amd_machine_version_stepping = Version.Stepping;
923  Header.kernel_code_entry_byte_offset = sizeof(Header);
924  Header.wavefront_size = 6;
925 
926  // If the code object does not support indirect functions, then the value must
927  // be 0xffffffff.
928  Header.call_convention = -1;
929 
930  // These alignment values are specified in powers of two, so alignment =
931  // 2^n. The minimum alignment is 2^4 = 16.
932  Header.kernarg_segment_alignment = 4;
933  Header.group_segment_alignment = 4;
934  Header.private_segment_alignment = 4;
935 
936  if (Version.Major >= 10) {
937  if (STI->getFeatureBits().test(FeatureWavefrontSize32)) {
938  Header.wavefront_size = 5;
940  }
942  S_00B848_WGP_MODE(STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1) |
944  }
945 }
946 
948  const MCSubtargetInfo *STI) {
950 
952  memset(&KD, 0, sizeof(KD));
953 
955  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
958  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1);
960  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1);
962  amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, 1);
963  if (Version.Major >= 10) {
965  amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
966  STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1 : 0);
968  amdhsa::COMPUTE_PGM_RSRC1_WGP_MODE,
969  STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1);
971  amdhsa::COMPUTE_PGM_RSRC1_MEM_ORDERED, 1);
972  }
973  if (AMDGPU::isGFX90A(*STI)) {
975  amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
976  STI->getFeatureBits().test(FeatureTgSplit) ? 1 : 0);
977  }
978  return KD;
979 }
980 
981 bool isGroupSegment(const GlobalValue *GV) {
983 }
984 
985 bool isGlobalSegment(const GlobalValue *GV) {
987 }
988 
990  unsigned AS = GV->getAddressSpace();
991  return AS == AMDGPUAS::CONSTANT_ADDRESS ||
993 }
994 
996  return TT.getArch() == Triple::r600;
997 }
998 
999 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
1000  Attribute A = F.getFnAttribute(Name);
1001  int Result = Default;
1002 
1003  if (A.isStringAttribute()) {
1004  StringRef Str = A.getValueAsString();
1005  if (Str.getAsInteger(0, Result)) {
1006  LLVMContext &Ctx = F.getContext();
1007  Ctx.emitError("can't parse integer attribute " + Name);
1008  }
1009  }
1010 
1011  return Result;
1012 }
1013 
1014 std::pair<int, int> getIntegerPairAttribute(const Function &F,
1015  StringRef Name,
1016  std::pair<int, int> Default,
1017  bool OnlyFirstRequired) {
1018  Attribute A = F.getFnAttribute(Name);
1019  if (!A.isStringAttribute())
1020  return Default;
1021 
1022  LLVMContext &Ctx = F.getContext();
1023  std::pair<int, int> Ints = Default;
1024  std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
1025  if (Strs.first.trim().getAsInteger(0, Ints.first)) {
1026  Ctx.emitError("can't parse first integer attribute " + Name);
1027  return Default;
1028  }
1029  if (Strs.second.trim().getAsInteger(0, Ints.second)) {
1030  if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
1031  Ctx.emitError("can't parse second integer attribute " + Name);
1032  return Default;
1033  }
1034  }
1035 
1036  return Ints;
1037 }
1038 
1040  return (1 << (getVmcntBitWidthLo(Version.Major) +
1041  getVmcntBitWidthHi(Version.Major))) -
1042  1;
1043 }
1044 
1046  return (1 << getExpcntBitWidth(Version.Major)) - 1;
1047 }
1048 
1050  return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
1051 }
1052 
1054  unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(Version.Major),
1055  getVmcntBitWidthLo(Version.Major));
1056  unsigned Expcnt = getBitMask(getExpcntBitShift(Version.Major),
1057  getExpcntBitWidth(Version.Major));
1058  unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(Version.Major),
1059  getLgkmcntBitWidth(Version.Major));
1060  unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(Version.Major),
1061  getVmcntBitWidthHi(Version.Major));
1062  return VmcntLo | Expcnt | Lgkmcnt | VmcntHi;
1063 }
1064 
1065 unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {
1066  unsigned VmcntLo = unpackBits(Waitcnt, getVmcntBitShiftLo(Version.Major),
1067  getVmcntBitWidthLo(Version.Major));
1068  unsigned VmcntHi = unpackBits(Waitcnt, getVmcntBitShiftHi(Version.Major),
1069  getVmcntBitWidthHi(Version.Major));
1070  return VmcntLo | VmcntHi << getVmcntBitWidthLo(Version.Major);
1071 }
1072 
1073 unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {
1074  return unpackBits(Waitcnt, getExpcntBitShift(Version.Major),
1075  getExpcntBitWidth(Version.Major));
1076 }
1077 
1078 unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {
1079  return unpackBits(Waitcnt, getLgkmcntBitShift(Version.Major),
1080  getLgkmcntBitWidth(Version.Major));
1081 }
1082 
1083 void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
1084  unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
1085  Vmcnt = decodeVmcnt(Version, Waitcnt);
1086  Expcnt = decodeExpcnt(Version, Waitcnt);
1087  Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
1088 }
1089 
1090 Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
1091  Waitcnt Decoded;
1092  Decoded.VmCnt = decodeVmcnt(Version, Encoded);
1093  Decoded.ExpCnt = decodeExpcnt(Version, Encoded);
1094  Decoded.LgkmCnt = decodeLgkmcnt(Version, Encoded);
1095  return Decoded;
1096 }
1097 
1098 unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
1099  unsigned Vmcnt) {
1100  Waitcnt = packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(Version.Major),
1101  getVmcntBitWidthLo(Version.Major));
1102  return packBits(Vmcnt >> getVmcntBitWidthLo(Version.Major), Waitcnt,
1103  getVmcntBitShiftHi(Version.Major),
1104  getVmcntBitWidthHi(Version.Major));
1105 }
1106 
1107 unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
1108  unsigned Expcnt) {
1109  return packBits(Expcnt, Waitcnt, getExpcntBitShift(Version.Major),
1110  getExpcntBitWidth(Version.Major));
1111 }
1112 
1113 unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
1114  unsigned Lgkmcnt) {
1115  return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(Version.Major),
1116  getLgkmcntBitWidth(Version.Major));
1117 }
1118 
1120  unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
1121  unsigned Waitcnt = getWaitcntBitMask(Version);
1122  Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
1123  Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
1124  Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
1125  return Waitcnt;
1126 }
1127 
1128 unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
1129  return encodeWaitcnt(Version, Decoded.VmCnt, Decoded.ExpCnt, Decoded.LgkmCnt);
1130 }
1131 
1132 //===----------------------------------------------------------------------===//
1133 // Custom Operands.
1134 //
1135 // A table of custom operands shall describe "primary" operand names
1136 // first followed by aliases if any. It is not required but recommended
1137 // to arrange operands so that operand encoding match operand position
1138 // in the table. This will make disassembly a bit more efficient.
1139 // Unused slots in the table shall have an empty name.
1140 //
1141 //===----------------------------------------------------------------------===//
1142 
1143 template <class T>
1144 static bool isValidOpr(int Idx, const CustomOperand<T> OpInfo[], int OpInfoSize,
1145  T Context) {
1146  return 0 <= Idx && Idx < OpInfoSize && !OpInfo[Idx].Name.empty() &&
1147  (!OpInfo[Idx].Cond || OpInfo[Idx].Cond(Context));
1148 }
1149 
1150 template <class T>
1151 static int getOprIdx(std::function<bool(const CustomOperand<T> &)> Test,
1152  const CustomOperand<T> OpInfo[], int OpInfoSize,
1153  T Context) {
1154  int InvalidIdx = OPR_ID_UNKNOWN;
1155  for (int Idx = 0; Idx < OpInfoSize; ++Idx) {
1156  if (Test(OpInfo[Idx])) {
1157  if (!OpInfo[Idx].Cond || OpInfo[Idx].Cond(Context))
1158  return Idx;
1160  }
1161  }
1162  return InvalidIdx;
1163 }
1164 
1165 template <class T>
1166 static int getOprIdx(const StringRef Name, const CustomOperand<T> OpInfo[],
1167  int OpInfoSize, T Context) {
1168  auto Test = [=](const CustomOperand<T> &Op) { return Op.Name == Name; };
1169  return getOprIdx<T>(Test, OpInfo, OpInfoSize, Context);
1170 }
1171 
1172 template <class T>
1173 static int getOprIdx(int Id, const CustomOperand<T> OpInfo[], int OpInfoSize,
1174  T Context, bool QuickCheck = true) {
1175  auto Test = [=](const CustomOperand<T> &Op) {
1176  return Op.Encoding == Id && !Op.Name.empty();
1177  };
1178  // This is an optimization that should work in most cases.
1179  // As a side effect, it may cause selection of an alias
1180  // instead of a primary operand name in case of sparse tables.
1181  if (QuickCheck && isValidOpr<T>(Id, OpInfo, OpInfoSize, Context) &&
1182  OpInfo[Id].Encoding == Id) {
1183  return Id;
1184  }
1185  return getOprIdx<T>(Test, OpInfo, OpInfoSize, Context);
1186 }
1187 
1188 //===----------------------------------------------------------------------===//
1189 // Custom Operand Values
1190 //===----------------------------------------------------------------------===//
1191 
1193  int Size,
1194  const MCSubtargetInfo &STI) {
1195  unsigned Enc = 0;
1196  for (int Idx = 0; Idx < Size; ++Idx) {
1197  const auto &Op = Opr[Idx];
1198  if (Op.isSupported(STI))
1199  Enc |= Op.encode(Op.Default);
1200  }
1201  return Enc;
1202 }
1203 
1205  int Size, unsigned Code,
1206  bool &HasNonDefaultVal,
1207  const MCSubtargetInfo &STI) {
1208  unsigned UsedOprMask = 0;
1209  HasNonDefaultVal = false;
1210  for (int Idx = 0; Idx < Size; ++Idx) {
1211  const auto &Op = Opr[Idx];
1212  if (!Op.isSupported(STI))
1213  continue;
1214  UsedOprMask |= Op.getMask();
1215  unsigned Val = Op.decode(Code);
1216  if (!Op.isValid(Val))
1217  return false;
1218  HasNonDefaultVal |= (Val != Op.Default);
1219  }
1220  return (Code & ~UsedOprMask) == 0;
1221 }
1222 
1223 static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size,
1224  unsigned Code, int &Idx, StringRef &Name,
1225  unsigned &Val, bool &IsDefault,
1226  const MCSubtargetInfo &STI) {
1227  while (Idx < Size) {
1228  const auto &Op = Opr[Idx++];
1229  if (Op.isSupported(STI)) {
1230  Name = Op.Name;
1231  Val = Op.decode(Code);
1232  IsDefault = (Val == Op.Default);
1233  return true;
1234  }
1235  }
1236 
1237  return false;
1238 }
1239 
1241  int64_t InputVal) {
1242  if (InputVal < 0 || InputVal > Op.Max)
1243  return OPR_VAL_INVALID;
1244  return Op.encode(InputVal);
1245 }
1246 
1247 static int encodeCustomOperand(const CustomOperandVal *Opr, int Size,
1248  const StringRef Name, int64_t InputVal,
1249  unsigned &UsedOprMask,
1250  const MCSubtargetInfo &STI) {
1251  int InvalidId = OPR_ID_UNKNOWN;
1252  for (int Idx = 0; Idx < Size; ++Idx) {
1253  const auto &Op = Opr[Idx];
1254  if (Op.Name == Name) {
1255  if (!Op.isSupported(STI)) {
1256  InvalidId = OPR_ID_UNSUPPORTED;
1257  continue;
1258  }
1259  auto OprMask = Op.getMask();
1260  if (OprMask & UsedOprMask)
1261  return OPR_ID_DUPLICATE;
1262  UsedOprMask |= OprMask;
1263  return encodeCustomOperandVal(Op, InputVal);
1264  }
1265  }
1266  return InvalidId;
1267 }
1268 
1269 //===----------------------------------------------------------------------===//
1270 // DepCtr
1271 //===----------------------------------------------------------------------===//
1272 
1273 namespace DepCtr {
1274 
1276  static int Default = -1;
1277  if (Default == -1)
1279  return Default;
1280 }
1281 
1282 bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
1283  const MCSubtargetInfo &STI) {
1285  HasNonDefaultVal, STI);
1286 }
1287 
1288 bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
1289  bool &IsDefault, const MCSubtargetInfo &STI) {
1290  return decodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Code, Id, Name, Val,
1291  IsDefault, STI);
1292 }
1293 
1294 int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
1295  const MCSubtargetInfo &STI) {
1296  return encodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Name, Val, UsedOprMask,
1297  STI);
1298 }
1299 
1300 } // namespace DepCtr
1301 
1302 //===----------------------------------------------------------------------===//
1303 // hwreg
1304 //===----------------------------------------------------------------------===//
1305 
1306 namespace Hwreg {
1307 
1308 int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI) {
1309  int Idx = getOprIdx<const MCSubtargetInfo &>(Name, Opr, OPR_SIZE, STI);
1310  return (Idx < 0) ? Idx : Opr[Idx].Encoding;
1311 }
1312 
1313 bool isValidHwreg(int64_t Id) {
1314  return 0 <= Id && isUInt<ID_WIDTH_>(Id);
1315 }
1316 
1318  return 0 <= Offset && isUInt<OFFSET_WIDTH_>(Offset);
1319 }
1320 
1321 bool isValidHwregWidth(int64_t Width) {
1322  return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
1323 }
1324 
1326  return (Id << ID_SHIFT_) |
1327  (Offset << OFFSET_SHIFT_) |
1328  ((Width - 1) << WIDTH_M1_SHIFT_);
1329 }
1330 
1331 StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI) {
1332  int Idx = getOprIdx<const MCSubtargetInfo &>(Id, Opr, OPR_SIZE, STI);
1333  return (Idx < 0) ? "" : Opr[Idx].Name;
1334 }
1335 
1336 void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width) {
1337  Id = (Val & ID_MASK_) >> ID_SHIFT_;
1338  Offset = (Val & OFFSET_MASK_) >> OFFSET_SHIFT_;
1339  Width = ((Val & WIDTH_M1_MASK_) >> WIDTH_M1_SHIFT_) + 1;
1340 }
1341 
1342 } // namespace Hwreg
1343 
1344 //===----------------------------------------------------------------------===//
1345 // exp tgt
1346 //===----------------------------------------------------------------------===//
1347 
1348 namespace Exp {
1349 
1350 struct ExpTgt {
1352  unsigned Tgt;
1353  unsigned MaxIndex;
1354 };
1355 
1356 static constexpr ExpTgt ExpTgtInfo[] = {
1357  {{"null"}, ET_NULL, ET_NULL_MAX_IDX},
1358  {{"mrtz"}, ET_MRTZ, ET_MRTZ_MAX_IDX},
1359  {{"prim"}, ET_PRIM, ET_PRIM_MAX_IDX},
1360  {{"mrt"}, ET_MRT0, ET_MRT_MAX_IDX},
1361  {{"pos"}, ET_POS0, ET_POS_MAX_IDX},
1362  {{"dual_src_blend"}, ET_DUAL_SRC_BLEND0, ET_DUAL_SRC_BLEND_MAX_IDX},
1363  {{"param"}, ET_PARAM0, ET_PARAM_MAX_IDX},
1364 };
1365 
1366 bool getTgtName(unsigned Id, StringRef &Name, int &Index) {
1367  for (const ExpTgt &Val : ExpTgtInfo) {
1368  if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1369  Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1370  Name = Val.Name;
1371  return true;
1372  }
1373  }
1374  return false;
1375 }
1376 
1377 unsigned getTgtId(const StringRef Name) {
1378 
1379  for (const ExpTgt &Val : ExpTgtInfo) {
1380  if (Val.MaxIndex == 0 && Name == Val.Name)
1381  return Val.Tgt;
1382 
1383  if (Val.MaxIndex > 0 && Name.startswith(Val.Name)) {
1384  StringRef Suffix = Name.drop_front(Val.Name.size());
1385 
1386  unsigned Id;
1387  if (Suffix.getAsInteger(10, Id) || Id > Val.MaxIndex)
1388  return ET_INVALID;
1389 
1390  // Disable leading zeroes
1391  if (Suffix.size() > 1 && Suffix[0] == '0')
1392  return ET_INVALID;
1393 
1394  return Val.Tgt + Id;
1395  }
1396  }
1397  return ET_INVALID;
1398 }
1399 
1400 bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) {
1401  switch (Id) {
1402  case ET_NULL:
1403  return !isGFX11Plus(STI);
1404  case ET_POS4:
1405  case ET_PRIM:
1406  return isGFX10Plus(STI);
1407  case ET_DUAL_SRC_BLEND0:
1408  case ET_DUAL_SRC_BLEND1:
1409  return isGFX11Plus(STI);
1410  default:
1411  if (Id >= ET_PARAM0 && Id <= ET_PARAM31)
1412  return !isGFX11Plus(STI);
1413  return true;
1414  }
1415 }
1416 
1417 } // namespace Exp
1418 
1419 //===----------------------------------------------------------------------===//
1420 // MTBUF Format
1421 //===----------------------------------------------------------------------===//
1422 
1423 namespace MTBUFFormat {
1424 
1425 int64_t getDfmt(const StringRef Name) {
1426  for (int Id = DFMT_MIN; Id <= DFMT_MAX; ++Id) {
1427  if (Name == DfmtSymbolic[Id])
1428  return Id;
1429  }
1430  return DFMT_UNDEF;
1431 }
1432 
1434  assert(Id <= DFMT_MAX);
1435  return DfmtSymbolic[Id];
1436 }
1437 
1439  if (isSI(STI) || isCI(STI))
1440  return NfmtSymbolicSICI;
1441  if (isVI(STI) || isGFX9(STI))
1442  return NfmtSymbolicVI;
1443  return NfmtSymbolicGFX10;
1444 }
1445 
1446 int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI) {
1447  auto lookupTable = getNfmtLookupTable(STI);
1448  for (int Id = NFMT_MIN; Id <= NFMT_MAX; ++Id) {
1449  if (Name == lookupTable[Id])
1450  return Id;
1451  }
1452  return NFMT_UNDEF;
1453 }
1454 
1455 StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI) {
1456  assert(Id <= NFMT_MAX);
1457  return getNfmtLookupTable(STI)[Id];
1458 }
1459 
1460 bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1461  unsigned Dfmt;
1462  unsigned Nfmt;
1463  decodeDfmtNfmt(Id, Dfmt, Nfmt);
1464  return isValidNfmt(Nfmt, STI);
1465 }
1466 
1467 bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1468  return !getNfmtName(Id, STI).empty();
1469 }
1470 
1471 int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt) {
1472  return (Dfmt << DFMT_SHIFT) | (Nfmt << NFMT_SHIFT);
1473 }
1474 
1475 void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt) {
1476  Dfmt = (Format >> DFMT_SHIFT) & DFMT_MASK;
1477  Nfmt = (Format >> NFMT_SHIFT) & NFMT_MASK;
1478 }
1479 
1480 int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI) {
1481  if (isGFX11Plus(STI)) {
1482  for (int Id = UfmtGFX11::UFMT_FIRST; Id <= UfmtGFX11::UFMT_LAST; ++Id) {
1483  if (Name == UfmtSymbolicGFX11[Id])
1484  return Id;
1485  }
1486  } else {
1487  for (int Id = UfmtGFX10::UFMT_FIRST; Id <= UfmtGFX10::UFMT_LAST; ++Id) {
1488  if (Name == UfmtSymbolicGFX10[Id])
1489  return Id;
1490  }
1491  }
1492  return UFMT_UNDEF;
1493 }
1494 
1496  if(isValidUnifiedFormat(Id, STI))
1497  return isGFX10(STI) ? UfmtSymbolicGFX10[Id] : UfmtSymbolicGFX11[Id];
1498  return "";
1499 }
1500 
1501 bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI) {
1502  return isGFX10(STI) ? Id <= UfmtGFX10::UFMT_LAST : Id <= UfmtGFX11::UFMT_LAST;
1503 }
1504 
1505 int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1506  const MCSubtargetInfo &STI) {
1507  int64_t Fmt = encodeDfmtNfmt(Dfmt, Nfmt);
1508  if (isGFX11Plus(STI)) {
1509  for (int Id = UfmtGFX11::UFMT_FIRST; Id <= UfmtGFX11::UFMT_LAST; ++Id) {
1510  if (Fmt == DfmtNfmt2UFmtGFX11[Id])
1511  return Id;
1512  }
1513  } else {
1514  for (int Id = UfmtGFX10::UFMT_FIRST; Id <= UfmtGFX10::UFMT_LAST; ++Id) {
1515  if (Fmt == DfmtNfmt2UFmtGFX10[Id])
1516  return Id;
1517  }
1518  }
1519  return UFMT_UNDEF;
1520 }
1521 
1522 bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) {
1523  return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
1524 }
1525 
1527  if (isGFX10Plus(STI))
1528  return UFMT_DEFAULT;
1529  return DFMT_NFMT_DEFAULT;
1530 }
1531 
1532 } // namespace MTBUFFormat
1533 
1534 //===----------------------------------------------------------------------===//
1535 // SendMsg
1536 //===----------------------------------------------------------------------===//
1537 
1538 namespace SendMsg {
1539 
1542 }
1543 
1544 int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI) {
1545  int Idx = getOprIdx<const MCSubtargetInfo &>(Name, Msg, MSG_SIZE, STI);
1546  return (Idx < 0) ? Idx : Msg[Idx].Encoding;
1547 }
1548 
1549 bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI) {
1550  return (MsgId & ~(getMsgIdMask(STI))) == 0;
1551 }
1552 
1553 StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI) {
1554  int Idx = getOprIdx<const MCSubtargetInfo &>(MsgId, Msg, MSG_SIZE, STI);
1555  return (Idx < 0) ? "" : Msg[Idx].Name;
1556 }
1557 
1558 int64_t getMsgOpId(int64_t MsgId, const StringRef Name) {
1559  const char* const *S = (MsgId == ID_SYSMSG) ? OpSysSymbolic : OpGsSymbolic;
1560  const int F = (MsgId == ID_SYSMSG) ? OP_SYS_FIRST_ : OP_GS_FIRST_;
1561  const int L = (MsgId == ID_SYSMSG) ? OP_SYS_LAST_ : OP_GS_LAST_;
1562  for (int i = F; i < L; ++i) {
1563  if (Name == S[i]) {
1564  return i;
1565  }
1566  }
1567  return OP_UNKNOWN_;
1568 }
1569 
1570 bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1571  bool Strict) {
1572  assert(isValidMsgId(MsgId, STI));
1573 
1574  if (!Strict)
1575  return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1576 
1577  if (MsgId == ID_SYSMSG)
1578  return OP_SYS_FIRST_ <= OpId && OpId < OP_SYS_LAST_;
1579  if (!isGFX11Plus(STI)) {
1580  switch (MsgId) {
1581  case ID_GS_PreGFX11:
1582  return (OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_) && OpId != OP_GS_NOP;
1583  case ID_GS_DONE_PreGFX11:
1584  return OP_GS_FIRST_ <= OpId && OpId < OP_GS_LAST_;
1585  }
1586  }
1587  return OpId == OP_NONE_;
1588 }
1589 
1590 StringRef getMsgOpName(int64_t MsgId, int64_t OpId,
1591  const MCSubtargetInfo &STI) {
1592  assert(msgRequiresOp(MsgId, STI));
1593  return (MsgId == ID_SYSMSG)? OpSysSymbolic[OpId] : OpGsSymbolic[OpId];
1594 }
1595 
1596 bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1597  const MCSubtargetInfo &STI, bool Strict) {
1598  assert(isValidMsgOp(MsgId, OpId, STI, Strict));
1599 
1600  if (!Strict)
1601  return 0 <= StreamId && isUInt<STREAM_ID_WIDTH_>(StreamId);
1602 
1603  if (!isGFX11Plus(STI)) {
1604  switch (MsgId) {
1605  case ID_GS_PreGFX11:
1607  case ID_GS_DONE_PreGFX11:
1608  return (OpId == OP_GS_NOP) ?
1609  (StreamId == STREAM_ID_NONE_) :
1611  }
1612  }
1613  return StreamId == STREAM_ID_NONE_;
1614 }
1615 
1616 bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI) {
1617  return MsgId == ID_SYSMSG ||
1618  (!isGFX11Plus(STI) &&
1619  (MsgId == ID_GS_PreGFX11 || MsgId == ID_GS_DONE_PreGFX11));
1620 }
1621 
1622 bool msgSupportsStream(int64_t MsgId, int64_t OpId,
1623  const MCSubtargetInfo &STI) {
1624  return !isGFX11Plus(STI) &&
1625  (MsgId == ID_GS_PreGFX11 || MsgId == ID_GS_DONE_PreGFX11) &&
1626  OpId != OP_GS_NOP;
1627 }
1628 
1629 void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1630  uint16_t &StreamId, const MCSubtargetInfo &STI) {
1631  MsgId = Val & getMsgIdMask(STI);
1632  if (isGFX11Plus(STI)) {
1633  OpId = 0;
1634  StreamId = 0;
1635  } else {
1636  OpId = (Val & OP_MASK_) >> OP_SHIFT_;
1638  }
1639 }
1640 
1642  uint64_t OpId,
1643  uint64_t StreamId) {
1644  return MsgId | (OpId << OP_SHIFT_) | (StreamId << STREAM_ID_SHIFT_);
1645 }
1646 
1647 } // namespace SendMsg
1648 
1649 //===----------------------------------------------------------------------===//
1650 //
1651 //===----------------------------------------------------------------------===//
1652 
1654  return getIntegerAttribute(F, "InitialPSInputAddr", 0);
1655 }
1656 
1658  // As a safe default always respond as if PS has color exports.
1659  return getIntegerAttribute(
1660  F, "amdgpu-color-export",
1661  F.getCallingConv() == CallingConv::AMDGPU_PS ? 1 : 0) != 0;
1662 }
1663 
1665  return getIntegerAttribute(F, "amdgpu-depth-export", 0) != 0;
1666 }
1667 
1669  switch(cc) {
1677  return true;
1678  default:
1679  return false;
1680  }
1681 }
1682 
1684  return isShader(cc) || cc == CallingConv::AMDGPU_Gfx;
1685 }
1686 
1688  return !isGraphics(cc) || cc == CallingConv::AMDGPU_CS;
1689 }
1690 
1692  switch (CC) {
1702  return true;
1703  default:
1704  return false;
1705  }
1706 }
1707 
1709  switch (CC) {
1711  return true;
1712  default:
1713  return isEntryFunctionCC(CC);
1714  }
1715 }
1716 
1717 bool isKernelCC(const Function *Func) {
1718  return AMDGPU::isModuleEntryFunctionCC(Func->getCallingConv());
1719 }
1720 
1721 bool hasXNACK(const MCSubtargetInfo &STI) {
1722  return STI.getFeatureBits()[AMDGPU::FeatureXNACK];
1723 }
1724 
1725 bool hasSRAMECC(const MCSubtargetInfo &STI) {
1726  return STI.getFeatureBits()[AMDGPU::FeatureSRAMECC];
1727 }
1728 
1729 bool hasMIMG_R128(const MCSubtargetInfo &STI) {
1730  return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128A16];
1731 }
1732 
1733 bool hasGFX10A16(const MCSubtargetInfo &STI) {
1734  return STI.getFeatureBits()[AMDGPU::FeatureGFX10A16];
1735 }
1736 
1737 bool hasG16(const MCSubtargetInfo &STI) {
1738  return STI.getFeatureBits()[AMDGPU::FeatureG16];
1739 }
1740 
1741 bool hasPackedD16(const MCSubtargetInfo &STI) {
1742  return !STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem] && !isCI(STI) &&
1743  !isSI(STI);
1744 }
1745 
1746 bool isSI(const MCSubtargetInfo &STI) {
1747  return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
1748 }
1749 
1750 bool isCI(const MCSubtargetInfo &STI) {
1751  return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
1752 }
1753 
1754 bool isVI(const MCSubtargetInfo &STI) {
1755  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1756 }
1757 
1758 bool isGFX9(const MCSubtargetInfo &STI) {
1759  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1760 }
1761 
1762 bool isGFX9_GFX10(const MCSubtargetInfo &STI) {
1763  return isGFX9(STI) || isGFX10(STI);
1764 }
1765 
1767  return isVI(STI) || isGFX9(STI) || isGFX10(STI);
1768 }
1769 
1770 bool isGFX8Plus(const MCSubtargetInfo &STI) {
1771  return isVI(STI) || isGFX9Plus(STI);
1772 }
1773 
1774 bool isGFX9Plus(const MCSubtargetInfo &STI) {
1775  return isGFX9(STI) || isGFX10Plus(STI);
1776 }
1777 
1778 bool isGFX10(const MCSubtargetInfo &STI) {
1779  return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1780 }
1781 
1782 bool isGFX10Plus(const MCSubtargetInfo &STI) {
1783  return isGFX10(STI) || isGFX11Plus(STI);
1784 }
1785 
1786 bool isGFX11(const MCSubtargetInfo &STI) {
1787  return STI.getFeatureBits()[AMDGPU::FeatureGFX11];
1788 }
1789 
1790 bool isGFX11Plus(const MCSubtargetInfo &STI) {
1791  return isGFX11(STI);
1792 }
1793 
1795  return !isGFX11Plus(STI);
1796 }
1797 
1799  return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI);
1800 }
1801 
1803  return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
1804 }
1805 
1807  return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
1808 }
1809 
1811  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_AEncoding];
1812 }
1813 
1815  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding];
1816 }
1817 
1819  return STI.getFeatureBits()[AMDGPU::FeatureGFX10_3Insts];
1820 }
1821 
1822 bool isGFX90A(const MCSubtargetInfo &STI) {
1823  return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
1824 }
1825 
1826 bool isGFX940(const MCSubtargetInfo &STI) {
1827  return STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts];
1828 }
1829 
1831  return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
1832 }
1833 
1834 bool hasMAIInsts(const MCSubtargetInfo &STI) {
1835  return STI.getFeatureBits()[AMDGPU::FeatureMAIInsts];
1836 }
1837 
1838 bool hasVOPD(const MCSubtargetInfo &STI) {
1839  return STI.getFeatureBits()[AMDGPU::FeatureVOPD];
1840 }
1841 
1842 int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR,
1843  int32_t ArgNumVGPR) {
1844  if (has90AInsts && ArgNumAGPR)
1845  return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
1846  return std::max(ArgNumVGPR, ArgNumAGPR);
1847 }
1848 
1849 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
1850  const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
1851  const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
1852  return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
1853  Reg == AMDGPU::SCC;
1854 }
1855 
1856 #define MAP_REG2REG \
1857  using namespace AMDGPU; \
1858  switch(Reg) { \
1859  default: return Reg; \
1860  CASE_CI_VI(FLAT_SCR) \
1861  CASE_CI_VI(FLAT_SCR_LO) \
1862  CASE_CI_VI(FLAT_SCR_HI) \
1863  CASE_VI_GFX9PLUS(TTMP0) \
1864  CASE_VI_GFX9PLUS(TTMP1) \
1865  CASE_VI_GFX9PLUS(TTMP2) \
1866  CASE_VI_GFX9PLUS(TTMP3) \
1867  CASE_VI_GFX9PLUS(TTMP4) \
1868  CASE_VI_GFX9PLUS(TTMP5) \
1869  CASE_VI_GFX9PLUS(TTMP6) \
1870  CASE_VI_GFX9PLUS(TTMP7) \
1871  CASE_VI_GFX9PLUS(TTMP8) \
1872  CASE_VI_GFX9PLUS(TTMP9) \
1873  CASE_VI_GFX9PLUS(TTMP10) \
1874  CASE_VI_GFX9PLUS(TTMP11) \
1875  CASE_VI_GFX9PLUS(TTMP12) \
1876  CASE_VI_GFX9PLUS(TTMP13) \
1877  CASE_VI_GFX9PLUS(TTMP14) \
1878  CASE_VI_GFX9PLUS(TTMP15) \
1879  CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
1880  CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
1881  CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
1882  CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
1883  CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
1884  CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
1885  CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
1886  CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
1887  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
1888  CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
1889  CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
1890  CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
1891  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
1892  CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
1893  CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
1894  CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
1895  CASE_GFXPRE11_GFX11PLUS(M0) \
1896  CASE_GFXPRE11_GFX11PLUS(SGPR_NULL) \
1897  CASE_GFXPRE11_GFX11PLUS_TO(SGPR_NULL64, SGPR_NULL) \
1898  }
1899 
1900 #define CASE_CI_VI(node) \
1901  assert(!isSI(STI)); \
1902  case node: return isCI(STI) ? node##_ci : node##_vi;
1903 
1904 #define CASE_VI_GFX9PLUS(node) \
1905  case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
1906 
1907 #define CASE_GFXPRE11_GFX11PLUS(node) \
1908  case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
1909 
1910 #define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
1911  case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
1912 
1913 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
1914  if (STI.getTargetTriple().getArch() == Triple::r600)
1915  return Reg;
1916  MAP_REG2REG
1917 }
1918 
1919 #undef CASE_CI_VI
1920 #undef CASE_VI_GFX9PLUS
1921 #undef CASE_GFXPRE11_GFX11PLUS
1922 #undef CASE_GFXPRE11_GFX11PLUS_TO
1923 
1924 #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
1925 #define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
1926 #define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
1927 #define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
1928 
1929 unsigned mc2PseudoReg(unsigned Reg) {
1930  MAP_REG2REG
1931 }
1932 
1933 #undef CASE_CI_VI
1934 #undef CASE_VI_GFX9PLUS
1935 #undef CASE_GFXPRE11_GFX11PLUS
1936 #undef CASE_GFXPRE11_GFX11PLUS_TO
1937 #undef MAP_REG2REG
1938 
1939 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1940  assert(OpNo < Desc.NumOperands);
1941  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1942  return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
1943  OpType <= AMDGPU::OPERAND_SRC_LAST;
1944 }
1945 
1946 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1947  assert(OpNo < Desc.NumOperands);
1948  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1949  switch (OpType) {
1969  return true;
1970  default:
1971  return false;
1972  }
1973 }
1974 
1975 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
1976  assert(OpNo < Desc.NumOperands);
1977  unsigned OpType = Desc.OpInfo[OpNo].OperandType;
1978  return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
1980 }
1981 
1982 // Avoid using MCRegisterClass::getSize, since that function will go away
1983 // (move from MC* level to Target* level). Return size in bits.
1984 unsigned getRegBitWidth(unsigned RCID) {
1985  switch (RCID) {
1986  case AMDGPU::VGPR_LO16RegClassID:
1987  case AMDGPU::VGPR_HI16RegClassID:
1988  case AMDGPU::SGPR_LO16RegClassID:
1989  case AMDGPU::AGPR_LO16RegClassID:
1990  return 16;
1991  case AMDGPU::SGPR_32RegClassID:
1992  case AMDGPU::VGPR_32RegClassID:
1993  case AMDGPU::VRegOrLds_32RegClassID:
1994  case AMDGPU::AGPR_32RegClassID:
1995  case AMDGPU::VS_32RegClassID:
1996  case AMDGPU::AV_32RegClassID:
1997  case AMDGPU::SReg_32RegClassID:
1998  case AMDGPU::SReg_32_XM0RegClassID:
1999  case AMDGPU::SRegOrLds_32RegClassID:
2000  return 32;
2001  case AMDGPU::SGPR_64RegClassID:
2002  case AMDGPU::VS_64RegClassID:
2003  case AMDGPU::SReg_64RegClassID:
2004  case AMDGPU::VReg_64RegClassID:
2005  case AMDGPU::AReg_64RegClassID:
2006  case AMDGPU::SReg_64_XEXECRegClassID:
2007  case AMDGPU::VReg_64_Align2RegClassID:
2008  case AMDGPU::AReg_64_Align2RegClassID:
2009  case AMDGPU::AV_64RegClassID:
2010  case AMDGPU::AV_64_Align2RegClassID:
2011  return 64;
2012  case AMDGPU::SGPR_96RegClassID:
2013  case AMDGPU::SReg_96RegClassID:
2014  case AMDGPU::VReg_96RegClassID:
2015  case AMDGPU::AReg_96RegClassID:
2016  case AMDGPU::VReg_96_Align2RegClassID:
2017  case AMDGPU::AReg_96_Align2RegClassID:
2018  case AMDGPU::AV_96RegClassID:
2019  case AMDGPU::AV_96_Align2RegClassID:
2020  return 96;
2021  case AMDGPU::SGPR_128RegClassID:
2022  case AMDGPU::SReg_128RegClassID:
2023  case AMDGPU::VReg_128RegClassID:
2024  case AMDGPU::AReg_128RegClassID:
2025  case AMDGPU::VReg_128_Align2RegClassID:
2026  case AMDGPU::AReg_128_Align2RegClassID:
2027  case AMDGPU::AV_128RegClassID:
2028  case AMDGPU::AV_128_Align2RegClassID:
2029  return 128;
2030  case AMDGPU::SGPR_160RegClassID:
2031  case AMDGPU::SReg_160RegClassID:
2032  case AMDGPU::VReg_160RegClassID:
2033  case AMDGPU::AReg_160RegClassID:
2034  case AMDGPU::VReg_160_Align2RegClassID:
2035  case AMDGPU::AReg_160_Align2RegClassID:
2036  case AMDGPU::AV_160RegClassID:
2037  case AMDGPU::AV_160_Align2RegClassID:
2038  return 160;
2039  case AMDGPU::SGPR_192RegClassID:
2040  case AMDGPU::SReg_192RegClassID:
2041  case AMDGPU::VReg_192RegClassID:
2042  case AMDGPU::AReg_192RegClassID:
2043  case AMDGPU::VReg_192_Align2RegClassID:
2044  case AMDGPU::AReg_192_Align2RegClassID:
2045  case AMDGPU::AV_192RegClassID:
2046  case AMDGPU::AV_192_Align2RegClassID:
2047  return 192;
2048  case AMDGPU::SGPR_224RegClassID:
2049  case AMDGPU::SReg_224RegClassID:
2050  case AMDGPU::VReg_224RegClassID:
2051  case AMDGPU::AReg_224RegClassID:
2052  case AMDGPU::VReg_224_Align2RegClassID:
2053  case AMDGPU::AReg_224_Align2RegClassID:
2054  case AMDGPU::AV_224RegClassID:
2055  case AMDGPU::AV_224_Align2RegClassID:
2056  return 224;
2057  case AMDGPU::SGPR_256RegClassID:
2058  case AMDGPU::SReg_256RegClassID:
2059  case AMDGPU::VReg_256RegClassID:
2060  case AMDGPU::AReg_256RegClassID:
2061  case AMDGPU::VReg_256_Align2RegClassID:
2062  case AMDGPU::AReg_256_Align2RegClassID:
2063  case AMDGPU::AV_256RegClassID:
2064  case AMDGPU::AV_256_Align2RegClassID:
2065  return 256;
2066  case AMDGPU::SGPR_512RegClassID:
2067  case AMDGPU::SReg_512RegClassID:
2068  case AMDGPU::VReg_512RegClassID:
2069  case AMDGPU::AReg_512RegClassID:
2070  case AMDGPU::VReg_512_Align2RegClassID:
2071  case AMDGPU::AReg_512_Align2RegClassID:
2072  case AMDGPU::AV_512RegClassID:
2073  case AMDGPU::AV_512_Align2RegClassID:
2074  return 512;
2075  case AMDGPU::SGPR_1024RegClassID:
2076  case AMDGPU::SReg_1024RegClassID:
2077  case AMDGPU::VReg_1024RegClassID:
2078  case AMDGPU::AReg_1024RegClassID:
2079  case AMDGPU::VReg_1024_Align2RegClassID:
2080  case AMDGPU::AReg_1024_Align2RegClassID:
2081  case AMDGPU::AV_1024RegClassID:
2082  case AMDGPU::AV_1024_Align2RegClassID:
2083  return 1024;
2084  default:
2085  llvm_unreachable("Unexpected register class");
2086  }
2087 }
2088 
2089 unsigned getRegBitWidth(const MCRegisterClass &RC) {
2090  return getRegBitWidth(RC.getID());
2091 }
2092 
2093 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
2094  unsigned OpNo) {
2095  assert(OpNo < Desc.NumOperands);
2096  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
2097  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
2098 }
2099 
2100 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
2101  if (isInlinableIntLiteral(Literal))
2102  return true;
2103 
2104  uint64_t Val = static_cast<uint64_t>(Literal);
2105  return (Val == DoubleToBits(0.0)) ||
2106  (Val == DoubleToBits(1.0)) ||
2107  (Val == DoubleToBits(-1.0)) ||
2108  (Val == DoubleToBits(0.5)) ||
2109  (Val == DoubleToBits(-0.5)) ||
2110  (Val == DoubleToBits(2.0)) ||
2111  (Val == DoubleToBits(-2.0)) ||
2112  (Val == DoubleToBits(4.0)) ||
2113  (Val == DoubleToBits(-4.0)) ||
2114  (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
2115 }
2116 
2117 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
2118  if (isInlinableIntLiteral(Literal))
2119  return true;
2120 
2121  // The actual type of the operand does not seem to matter as long
2122  // as the bits match one of the inline immediate values. For example:
2123  //
2124  // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
2125  // so it is a legal inline immediate.
2126  //
2127  // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
2128  // floating-point, so it is a legal inline immediate.
2129 
2130  uint32_t Val = static_cast<uint32_t>(Literal);
2131  return (Val == FloatToBits(0.0f)) ||
2132  (Val == FloatToBits(1.0f)) ||
2133  (Val == FloatToBits(-1.0f)) ||
2134  (Val == FloatToBits(0.5f)) ||
2135  (Val == FloatToBits(-0.5f)) ||
2136  (Val == FloatToBits(2.0f)) ||
2137  (Val == FloatToBits(-2.0f)) ||
2138  (Val == FloatToBits(4.0f)) ||
2139  (Val == FloatToBits(-4.0f)) ||
2140  (Val == 0x3e22f983 && HasInv2Pi);
2141 }
2142 
2143 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
2144  if (!HasInv2Pi)
2145  return false;
2146 
2147  if (isInlinableIntLiteral(Literal))
2148  return true;
2149 
2150  uint16_t Val = static_cast<uint16_t>(Literal);
2151  return Val == 0x3C00 || // 1.0
2152  Val == 0xBC00 || // -1.0
2153  Val == 0x3800 || // 0.5
2154  Val == 0xB800 || // -0.5
2155  Val == 0x4000 || // 2.0
2156  Val == 0xC000 || // -2.0
2157  Val == 0x4400 || // 4.0
2158  Val == 0xC400 || // -4.0
2159  Val == 0x3118; // 1/2pi
2160 }
2161 
2162 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
2163  assert(HasInv2Pi);
2164 
2165  if (isInt<16>(Literal) || isUInt<16>(Literal)) {
2166  int16_t Trunc = static_cast<int16_t>(Literal);
2167  return AMDGPU::isInlinableLiteral16(Trunc, HasInv2Pi);
2168  }
2169  if (!(Literal & 0xffff))
2170  return AMDGPU::isInlinableLiteral16(Literal >> 16, HasInv2Pi);
2171 
2172  int16_t Lo16 = static_cast<int16_t>(Literal);
2173  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
2174  return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
2175 }
2176 
2177 bool isInlinableIntLiteralV216(int32_t Literal) {
2178  int16_t Lo16 = static_cast<int16_t>(Literal);
2179  if (isInt<16>(Literal) || isUInt<16>(Literal))
2180  return isInlinableIntLiteral(Lo16);
2181 
2182  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
2183  if (!(Literal & 0xffff))
2184  return isInlinableIntLiteral(Hi16);
2185  return Lo16 == Hi16 && isInlinableIntLiteral(Lo16);
2186 }
2187 
2188 bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi) {
2189  assert(HasInv2Pi);
2190 
2191  int16_t Lo16 = static_cast<int16_t>(Literal);
2192  if (isInt<16>(Literal) || isUInt<16>(Literal))
2193  return true;
2194 
2195  int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
2196  if (!(Literal & 0xffff))
2197  return true;
2198  return Lo16 == Hi16;
2199 }
2200 
2201 bool isArgPassedInSGPR(const Argument *A) {
2202  const Function *F = A->getParent();
2203 
2204  // Arguments to compute shaders are never a source of divergence.
2205  CallingConv::ID CC = F->getCallingConv();
2206  switch (CC) {
2209  return true;
2218  // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
2219  // Everything else is in VGPRs.
2220  return F->getAttributes().hasParamAttr(A->getArgNo(), Attribute::InReg) ||
2221  F->getAttributes().hasParamAttr(A->getArgNo(), Attribute::ByVal);
2222  default:
2223  // TODO: Should calls support inreg for SGPR inputs?
2224  return false;
2225  }
2226 }
2227 
2228 static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
2229  return isGCN3Encoding(ST) || isGFX10Plus(ST);
2230 }
2231 
2233  return isGFX9Plus(ST);
2234 }
2235 
2237  int64_t EncodedOffset) {
2238  return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset)
2239  : isUInt<8>(EncodedOffset);
2240 }
2241 
2243  int64_t EncodedOffset,
2244  bool IsBuffer) {
2245  return !IsBuffer &&
2247  isInt<21>(EncodedOffset);
2248 }
2249 
2250 static bool isDwordAligned(uint64_t ByteOffset) {
2251  return (ByteOffset & 3) == 0;
2252 }
2253 
2255  uint64_t ByteOffset) {
2256  if (hasSMEMByteOffset(ST))
2257  return ByteOffset;
2258 
2259  assert(isDwordAligned(ByteOffset));
2260  return ByteOffset >> 2;
2261 }
2262 
2264  int64_t ByteOffset, bool IsBuffer) {
2265  // The signed version is always a byte offset.
2266  if (!IsBuffer && hasSMRDSignedImmOffset(ST)) {
2268  return isInt<20>(ByteOffset) ? Optional<int64_t>(ByteOffset) : None;
2269  }
2270 
2271  if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
2272  return None;
2273 
2274  int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
2275  return isLegalSMRDEncodedUnsignedOffset(ST, EncodedOffset)
2276  ? Optional<int64_t>(EncodedOffset)
2277  : None;
2278 }
2279 
2281  int64_t ByteOffset) {
2282  if (!isCI(ST) || !isDwordAligned(ByteOffset))
2283  return None;
2284 
2285  int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
2286  return isUInt<32>(EncodedOffset) ? Optional<int64_t>(EncodedOffset) : None;
2287 }
2288 
2290  // Address offset is 12-bit signed for GFX10, 13-bit for GFX9 and GFX11+.
2291  if (AMDGPU::isGFX10(ST))
2292  return Signed ? 12 : 11;
2293 
2294  return Signed ? 13 : 12;
2295 }
2296 
2297 // Given Imm, split it into the values to put into the SOffset and ImmOffset
2298 // fields in an MUBUF instruction. Return false if it is not possible (due to a
2299 // hardware bug needing a workaround).
2300 //
2301 // The required alignment ensures that individual address components remain
2302 // aligned if they are aligned to begin with. It also ensures that additional
2303 // offsets within the given alignment can be added to the resulting ImmOffset.
2304 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
2305  const GCNSubtarget *Subtarget, Align Alignment) {
2306  const uint32_t MaxImm = alignDown(4095, Alignment.value());
2307  uint32_t Overflow = 0;
2308 
2309  if (Imm > MaxImm) {
2310  if (Imm <= MaxImm + 64) {
2311  // Use an SOffset inline constant for 4..64
2312  Overflow = Imm - MaxImm;
2313  Imm = MaxImm;
2314  } else {
2315  // Try to keep the same value in SOffset for adjacent loads, so that
2316  // the corresponding register contents can be re-used.
2317  //
2318  // Load values with all low-bits (except for alignment bits) set into
2319  // SOffset, so that a larger range of values can be covered using
2320  // s_movk_i32.
2321  //
2322  // Atomic operations fail to work correctly when individual address
2323  // components are unaligned, even if their sum is aligned.
2324  uint32_t High = (Imm + Alignment.value()) & ~4095;
2325  uint32_t Low = (Imm + Alignment.value()) & 4095;
2326  Imm = Low;
2327  Overflow = High - Alignment.value();
2328  }
2329  }
2330 
2331  // There is a hardware bug in SI and CI which prevents address clamping in
2332  // MUBUF instructions from working correctly with SOffsets. The immediate
2333  // offset is unaffected.
2334  if (Overflow > 0 &&
2336  return false;
2337 
2338  ImmOffset = Imm;
2339  SOffset = Overflow;
2340  return true;
2341 }
2342 
2344  *this = getDefaultForCallingConv(F.getCallingConv());
2345 
2346  StringRef IEEEAttr = F.getFnAttribute("amdgpu-ieee").getValueAsString();
2347  if (!IEEEAttr.empty())
2348  IEEE = IEEEAttr == "true";
2349 
2350  StringRef DX10ClampAttr
2351  = F.getFnAttribute("amdgpu-dx10-clamp").getValueAsString();
2352  if (!DX10ClampAttr.empty())
2353  DX10Clamp = DX10ClampAttr == "true";
2354 
2355  StringRef DenormF32Attr = F.getFnAttribute("denormal-fp-math-f32").getValueAsString();
2356  if (!DenormF32Attr.empty()) {
2357  DenormalMode DenormMode = parseDenormalFPAttribute(DenormF32Attr);
2360  }
2361 
2362  StringRef DenormAttr = F.getFnAttribute("denormal-fp-math").getValueAsString();
2363  if (!DenormAttr.empty()) {
2364  DenormalMode DenormMode = parseDenormalFPAttribute(DenormAttr);
2365 
2366  if (DenormF32Attr.empty()) {
2369  }
2370 
2373  }
2374 }
2375 
2376 namespace {
2377 
2378 struct SourceOfDivergence {
2379  unsigned Intr;
2380 };
2381 const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
2382 
2383 #define GET_SourcesOfDivergence_IMPL
2384 #define GET_Gfx9BufferFormat_IMPL
2385 #define GET_Gfx10BufferFormat_IMPL
2386 #define GET_Gfx11PlusBufferFormat_IMPL
2387 #include "AMDGPUGenSearchableTables.inc"
2388 
2389 } // end anonymous namespace
2390 
2391 bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
2392  return lookupSourceOfDivergence(IntrID);
2393 }
2394 
2395 const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
2396  uint8_t NumComponents,
2397  uint8_t NumFormat,
2398  const MCSubtargetInfo &STI) {
2399  return isGFX11Plus(STI)
2400  ? getGfx11PlusBufferFormatInfo(BitsPerComp, NumComponents,
2401  NumFormat)
2402  : isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
2403  NumComponents, NumFormat)
2404  : getGfx9BufferFormatInfo(BitsPerComp,
2405  NumComponents, NumFormat);
2406 }
2407 
2409  const MCSubtargetInfo &STI) {
2410  return isGFX11Plus(STI) ? getGfx11PlusBufferFormatInfo(Format)
2411  : isGFX10(STI) ? getGfx10BufferFormatInfo(Format)
2412  : getGfx9BufferFormatInfo(Format);
2413 }
2414 
2415 } // namespace AMDGPU
2416 
2419  switch (S) {
2421  OS << "Unsupported";
2422  break;
2424  OS << "Any";
2425  break;
2427  OS << "Off";
2428  break;
2430  OS << "On";
2431  break;
2432  }
2433  return OS;
2434 }
2435 
2436 } // namespace llvm
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:173
llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1501
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uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width)
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unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
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i
i
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uint8_t elements
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const int OPR_SIZE
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llvm::AMDGPU::OPR_ID_UNSUPPORTED
const int OPR_ID_UNSUPPORTED
Definition: AMDGPUAsmUtils.h:24
llvm::AMDGPU::getMUBUFIsBufferInv
bool getMUBUFIsBufferInv(unsigned Opc)
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llvm::alignTo
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:156
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
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bool isHsaAbiVersion3(const MCSubtargetInfo *STI)
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@ UFMT_FIRST
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This class represents an incoming formal argument to a Function.
Definition: Argument.h:28
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AMDGPUTargetID(const MCSubtargetInfo &STI)
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unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
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bool IsSingle
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Signed
@ Signed
Definition: NVPTXISelLowering.cpp:4709
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
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bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
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unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
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bool getMUBUFHasSoffset(unsigned Opc)
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emitError - Emit an error message to the currently installed error handler with optional location inf...
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NumFormat
Definition: SIDefines.h:497
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StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI)
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unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
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Key for Kernel::CodeProps::Metadata::mNumSGPRs.
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int64_t getHwregId(const StringRef Name, const MCSubtargetInfo &STI)
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@ ID_SHIFT_
Definition: SIDefines.h:411
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@ DFMT_MASK
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Definition: AMDGPUBaseInfo.h:1020
llvm::AMDGPU::hasXNACK
bool hasXNACK(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1721
llvm::AMDGPU::IsaInfo::TargetIDSetting::Unsupported
@ Unsupported
llvm::AMDGPU::OPERAND_REG_IMM_V2FP16
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:162
High
uint64_t High
Definition: NVVMIntrRange.cpp:61
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1182
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:372
llvm::AMDGPU::isVOPD
bool isVOPD(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:430
llvm::AMDGPU::IsaInfo::TargetIDSetting::On
@ On
llvm::AMDGPU::isGFX10_BEncoding
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1814
llvm::Triple::amdgcn
@ amdgcn
Definition: Triple.h:74
llvm::AMDGPU::CustomOperand::Name
StringLiteral Name
Definition: AMDGPUAsmUtils.h:29
llvm::AMDGPU::isGFX10_AEncoding
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1810
llvm::CallingConv::AMDGPU_Gfx
@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:233
amd_kernel_code_t::compute_pgm_resource_registers
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
Definition: AMDKernelCodeT.h:558
llvm::AMDGPU::getVOP2IsSingle
bool getVOP2IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:393
llvm::AMDGPU::OPR_VAL_INVALID
const int OPR_VAL_INVALID
Definition: AMDGPUAsmUtils.h:26
llvm::AMDGPU::MIMGDimInfo
Definition: AMDGPUBaseInfo.h:324
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE
@ FLOAT_DENORM_MODE_FLUSH_NONE
Definition: AMDHSAKernelDescriptor.h:63
llvm::AMDGPU::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1830
llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
Definition: AMDGPUBaseInfo.cpp:1471
llvm::AMDGPU::getHsaAbiVersion
Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:105
llvm::AMDGPU::MTBUFFormat::NFMT_UNDEF
@ NFMT_UNDEF
Definition: SIDefines.h:511
llvm::AMDGPU::VOPDInfo::OpX
uint16_t OpX
Definition: AMDGPUBaseInfo.cpp:288
llvm::AMDGPUSubtarget::SEA_ISLANDS
@ SEA_ISLANDS
Definition: AMDGPUSubtarget.h:38
llvm::AMDGPU::Exp::ET_NULL
@ ET_NULL
Definition: SIDefines.h:862
llvm::AMDGPU::SendMsg::STREAM_ID_MASK_
@ STREAM_ID_MASK_
Definition: SIDefines.h:378
llvm::CallingConv::AMDGPU_GS
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:192
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::AMDGPU::getVOPDFull
int getVOPDFull(unsigned OpX, unsigned OpY)
Definition: AMDGPUBaseInfo.cpp:451
llvm::AMDGPU::SendMsg::OpSysSymbolic
const char *const OpSysSymbolic[OP_SYS_LAST_]
Definition: AMDGPUAsmUtils.cpp:69
llvm::AMDGPU::getSMRDEncodedLiteralOffset32
Optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:2280
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::AMDGPU::getAmdhsaCodeObjectVersion
unsigned getAmdhsaCodeObjectVersion()
Definition: AMDGPUBaseInfo.cpp:153
llvm::AMDGPU::MTBUFInfo::has_vaddr
bool has_vaddr
Definition: AMDGPUBaseInfo.cpp:261
llvm::AMDGPU::SendMsg::OP_GS_LAST_
@ OP_GS_LAST_
Definition: SIDefines.h:360
llvm::AMDGPU::MTBUFFormat::isValidNfmt
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1467
llvm::AMDGPU::DepCtr::encodeDepCtr
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1294
llvm::AMDGPU::isGFX11
bool isGFX11(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1786
Shift
bool Shift
Definition: README.txt:468
llvm::AMDGPU::Hwreg::ID_MASK_
@ ID_MASK_
Definition: SIDefines.h:413
llvm::AMDGPU::Exp::ET_POS0
@ ET_POS0
Definition: SIDefines.h:863
llvm::AMDGPU::CustomOperand::Encoding
int Encoding
Definition: AMDGPUAsmUtils.h:30
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_MAX
@ DFMT_NFMT_MAX
Definition: SIDefines.h:526
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:594
llvm::AMDGPU::IsaInfo::getNumExtraSGPRs
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
Definition: AMDGPUBaseInfo.cpp:794
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1778
llvm::AMDGPU::IsaInfo::getTotalNumVGPRs
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:858
LimitTo128VGPRs
static llvm::cl::opt< bool > LimitTo128VGPRs("amdgpu-limit-to-128-vgprs", llvm::cl::Hidden, llvm::cl::desc("Never use more than 128 VGPRs"))
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromTargetIDStream
void setTargetIDFromTargetIDStream(StringRef TargetID)
Definition: AMDGPUBaseInfo.cpp:535
llvm::CallingConv::AMDGPU_LS
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:214
llvm::AMDGPU::IsaInfo::getMinWavesPerEU
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:695
llvm::Optional< uint8_t >
llvm::AMDGPU::SIModeRegisterDefaults::getDefaultForCallingConv
static SIModeRegisterDefaults getDefaultForCallingConv(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.h:1046
llvm::AMDGPU::MUBUFInfo::has_soffset
bool has_soffset
Definition: AMDGPUBaseInfo.cpp:253
llvm::MCRegisterClass::contains
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
Definition: MCRegisterInfo.h:68
llvm::AMDGPU::SIModeRegisterDefaults::FP32InputDenormals
bool FP32InputDenormals
If this is set, neither input or output denormals are flushed for most f32 instructions.
Definition: AMDGPUBaseInfo.h:1028
llvm::AMDGPU::IsaInfo::TargetIDSetting::Any
@ Any
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
AMDGPUAsmUtils.h
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::AMDGPU::getVmcntBitMask
unsigned getVmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1039
llvm::AMDGPU::isGlobalSegment
bool isGlobalSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:985
llvm::AMDGPU::hasGFX10_3Insts
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1818
TargetParser.h
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::CallingConv::AMDGPU_VS
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
Definition: CallingConv.h:189
llvm::AMDGPU::IsaInfo::getMaxNumVGPRs
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:892
llvm::AMDGPU::Exp::ET_PARAM0
@ ET_PARAM0
Definition: SIDefines.h:870
llvm::AMDGPU::getWaitcntBitMask
unsigned getWaitcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1053
llvm::AMDGPU::isIntrinsicSourceOfDivergence
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
Definition: AMDGPUBaseInfo.cpp:2391
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2
uint32_t compute_pgm_rsrc2
Definition: AMDHSAKernelDescriptor.h:179
llvm::AMDGPU::SendMsg::MSG_SIZE
const int MSG_SIZE
Definition: AMDGPUAsmUtils.cpp:65
llvm::AMDGPU::MIMGDimInfo::NumGradients
uint8_t NumGradients
Definition: AMDGPUBaseInfo.h:327
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::AMDGPU::getMTBUFOpcode
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:323
llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable
static const StringLiteral * getNfmtLookupTable(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1438
AmdhsaCodeObjectVersion
static llvm::cl::opt< unsigned > AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4))
llvm::AMDGPU::MUBUFInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:248
llvm::AMDGPU::MIMGInfo::VAddrDwords
uint8_t VAddrDwords
Definition: AMDGPUBaseInfo.h:405
llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:683
llvm::AMDGPU::IsaInfo::TRAP_NUM_SGPRS
@ TRAP_NUM_SGPRS
Definition: AMDGPUBaseInfo.h:95
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1460
llvm::AMDGPU::SendMsg::ID_MASK_PreGFX11_
@ ID_MASK_PreGFX11_
Definition: SIDefines.h:344
llvm::AMDGPU::DepCtr::decodeDepCtr
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1288
llvm::AMDGPU::VOPDInfo
Definition: AMDGPUBaseInfo.cpp:286
AMDHSAKernelDescriptor.h
llvm::AMDGPU::HSAMD::V3::VersionMajor
constexpr uint32_t VersionMajor
HSA metadata major version.
Definition: AMDGPUMetadata.h:459
llvm::MCRegisterClass
MCRegisterClass - Base class of TargetRegisterClass.
Definition: MCRegisterInfo.h:31
llvm::AMDGPU::getDefaultCustomOperandEncoding
static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1192
llvm::AMDGPU::IsaInfo::TargetIDSetting
TargetIDSetting
Definition: AMDGPUBaseInfo.h:98
llvm::parseDenormalFPAttribute
DenormalMode parseDenormalFPAttribute(StringRef Str)
Returns the denormal mode to use for inputs and outputs.
Definition: FloatingPointMode.h:176
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::AMDGPU::Hwreg::decodeHwreg
void decodeHwreg(unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
Definition: AMDGPUBaseInfo.cpp:1336
llvm::AMDGPU::IsaVersion
Instruction set architecture version.
Definition: TargetParser.h:113
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:737
CommandLine.h
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicVI
const StringLiteral NfmtSymbolicVI[]
Definition: AMDGPUAsmUtils.cpp:182
llvm::AMDGPU::isGFX90A
bool isGFX90A(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1822
llvm::AMDGPU::OPR_ID_DUPLICATE
const int OPR_ID_DUPLICATE
Definition: AMDGPUAsmUtils.h:25
llvm::AMDGPU::SendMsg::OP_GS_FIRST_
@ OP_GS_FIRST_
Definition: SIDefines.h:361
llvm::AMDGPU::OPERAND_REG_IMM_FP32
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:157
llvm::AMDGPU::SendMsg::msgSupportsStream
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1622
llvm::AMDGPU::MTBUFFormat::UfmtSymbolicGFX11
const StringLiteral UfmtSymbolicGFX11[]
Definition: AMDGPUAsmUtils.cpp:381
llvm::AMDGPU::MUBUFInfo::has_srsrc
bool has_srsrc
Definition: AMDGPUBaseInfo.cpp:252
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:842
llvm::AMDGPU::getMTBUFHasSrsrc
bool getMTBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:338
GlobalValue.h
ELF.h
llvm::DenormalMode::Input
DenormalModeKind Input
Denormal treatment kind for floating point instruction inputs in the default floating-point environme...
Definition: FloatingPointMode.h:92
llvm::AMDGPU::isShader
bool isShader(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1668
llvm::PGSOQueryType::Test
@ Test
llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:723
llvm::ARM::InvalidIdx
@ InvalidIdx
Definition: ARMRegisterBankInfo.cpp:69
llvm::AMDGPU::MTBUFInfo::has_soffset
bool has_soffset
Definition: AMDGPUBaseInfo.cpp:263
amd_kernel_code_t::amd_kernel_code_version_major
uint32_t amd_kernel_code_version_major
Definition: AMDKernelCodeT.h:527
llvm::AMDGPU::Exp::ET_INVALID
@ ET_INVALID
Definition: SIDefines.h:881
llvm::AMDGPU::Exp::ET_MRTZ_MAX_IDX
@ ET_MRTZ_MAX_IDX
Definition: SIDefines.h:874
GCNSubtarget.h
llvm::AMDGPU::hasSMEMByteOffset
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
Definition: AMDGPUBaseInfo.cpp:2228
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::AMDGPU::getRegOperandSize
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
Definition: AMDGPUBaseInfo.cpp:2093
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
@ OP_SYS_LAST_
Definition: SIDefines.h:367
llvm::AMDGPU::getMIMGBaseOpcode
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:206
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:300
llvm::AMDGPU::isInlinableIntLiteralV216
bool isInlinableIntLiteralV216(int32_t Literal)
Definition: AMDGPUBaseInfo.cpp:2177
Intr
unsigned Intr
Definition: AMDGPUBaseInfo.cpp:2379
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:186
llvm::AMDGPU::MTBUFFormat::DfmtSymbolic
const StringLiteral DfmtSymbolic[]
Definition: AMDGPUAsmUtils.cpp:141
llvm::AMDGPU::getMUBUFOpcode
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
Definition: AMDGPUBaseInfo.cpp:353
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
llvm::AMDGPU::getSMEMIsBuffer
bool getSMEMIsBuffer(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:383
llvm::AMDGPU::isGFX940
bool isGFX940(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1826
llvm::AMDGPU::IsaInfo::getMaxNumSGPRs
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
Definition: AMDGPUBaseInfo.cpp:777
llvm::AMDGPU::isSGPR
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
Definition: AMDGPUBaseInfo.cpp:1849
llvm::AMDGPU::hasMAIInsts
bool hasMAIInsts(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1834
llvm::AMDGPU::VOPC64DPPInfo
Definition: AMDGPUBaseInfo.cpp:276
llvm::AMDGPU::IsaInfo::getTargetIDSettingFromFeatureString
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
Definition: AMDGPUBaseInfo.cpp:526
llvm::AMDGPU::SendMsg::STREAM_ID_LAST_
@ STREAM_ID_LAST_
Definition: SIDefines.h:374
llvm::SubtargetFeatures::getFeatures
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Definition: SubtargetFeature.h:193
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:586
llvm::SubtargetFeatures
Manages the enabling and disabling of subtarget specific features.
Definition: SubtargetFeature.h:180
llvm::AMDGPU::SendMsg::ID_SYSMSG
@ ID_SYSMSG
Definition: SIDefines.h:335
llvm::AMDGPU::Hwreg::Id
Id
Definition: SIDefines.h:385
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackOnOrAny
bool isXnackOnOrAny() const
Definition: AMDGPUBaseInfo.h:121
llvm::AMDGPU::decodeExpcnt
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
Definition: AMDGPUBaseInfo.cpp:1073
llvm::AMDGPU::getMAIIsGFX940XDL
bool getMAIIsGFX940XDL(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:412
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5
@ ELFABIVERSION_AMDGPU_HSA_V5
Definition: ELF.h:377
llvm::AMDGPU::MTBUFInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.cpp:259
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::alignDown
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:695
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
S_00B848_MEM_ORDERED
#define S_00B848_MEM_ORDERED(x)
Definition: SIDefines.h:1011
llvm::AMDGPU::hasGFX10A16
bool hasGFX10A16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1733
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::AMDGPU::Exp::ET_PRIM
@ ET_PRIM
Definition: SIDefines.h:867
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::AMDGPU::encodeCustomOperand
static int encodeCustomOperand(const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1247
llvm::AMDGPU::SendMsg::OP_GS_NOP
@ OP_GS_NOP
Definition: SIDefines.h:356
llvm::AMDGPU::OPERAND_REG_IMM_FP64
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:158
llvm::AMDGPU::getMTBUFBaseOpcode
int getMTBUFBaseOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:318
llvm::AMDGPU::getInitialPSInputAddr
unsigned getInitialPSInputAddr(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1653
llvm::AMDGPU::SendMsg::OP_SHIFT_
@ OP_SHIFT_
Definition: SIDefines.h:350
llvm::Triple::r600
@ r600
Definition: Triple.h:73
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
llvm::AMDGPU::Exp::ExpTgt::Name
StringLiteral Name
Definition: AMDGPUBaseInfo.cpp:1351
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::AMDGPU::getMTBUFHasSoffset
bool getMTBUFHasSoffset(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:343
llvm::raw_ostream::flush
void flush()
Definition: raw_ostream.h:185
llvm::operator<<
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:230
llvm::AMDGPU::MTBUFFormat::DFMT_UNDEF
@ DFMT_UNDEF
Definition: SIDefines.h:490
llvm::cl::Option::getNumOccurrences
int getNumOccurrences() const
Definition: CommandLine.h:402
llvm::ThreadPriority::Low
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
llvm::AMDGPU::decodeWaitcnt
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
Definition: AMDGPUBaseInfo.cpp:1083
amd_kernel_code_t::wavefront_size
uint8_t wavefront_size
Wavefront size expressed as a power of two.
Definition: AMDKernelCodeT.h:643
llvm::AMDGPU::MTBUFInfo
Definition: AMDGPUBaseInfo.cpp:257
llvm::AMDGPU::OPERAND_REG_IMM_V2FP32
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:165
llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:714
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getSramEccSetting
TargetIDSetting getSramEccSetting() const
Definition: AMDGPUBaseInfo.h:164
llvm::amdhsa::kernel_descriptor_t::kernel_code_properties
uint16_t kernel_code_properties
Definition: AMDHSAKernelDescriptor.h:180
llvm::IndexedInstrProf::Version
const uint64_t Version
Definition: InstrProf.h:1056
llvm::AMDGPU::getMUBUFHasSrsrc
bool getMUBUFHasSrsrc(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:368
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AMDGPU::convertSMRDOffsetUnits
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
Definition: AMDGPUBaseInfo.cpp:2254
llvm::AMDGPU::IsaInfo::getEUsPerCU
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:672
llvm::AMDGPU::MIMGInfo::MIMGEncoding
uint8_t MIMGEncoding
Definition: AMDGPUBaseInfo.h:403
llvm::MCOperandInfo::RegClass
int16_t RegClass
This specifies the register class enumeration of the operand if the operand is a register.
Definition: MCInstrDesc.h:90
llvm::AMDGPU::MTBUFInfo::elements
uint8_t elements
Definition: AMDGPUBaseInfo.cpp:260
llvm::AMDGPU::IsaInfo::getLocalMemorySize
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:663
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:199
llvm::Triple::getArch
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:346
llvm::AMDGPU::isCI
bool isCI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1750
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:463
llvm::None
const NoneType None
Definition: None.h:24
llvm::CallingConv::AMDGPU_CS
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:198
llvm::AMDGPU::SendMsg::StreamId
StreamId
Definition: SIDefines.h:371
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::AMDGPU::VOPC64DPPInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:277
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1782
llvm::AMDGPU::isSymbolicCustomOperandEncoding
static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1204
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc3
uint32_t compute_pgm_rsrc3
Definition: AMDHSAKernelDescriptor.h:177
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0
@ ET_DUAL_SRC_BLEND0
Definition: SIDefines.h:868
llvm::AMDGPU::isEntryFunctionCC
bool isEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1691
amd_kernel_code_t::amd_machine_version_minor
uint16_t amd_machine_version_minor
Definition: AMDKernelCodeT.h:531
llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1522
llvm::AMDGPU::isHsaAbiVersion2
bool isHsaAbiVersion2(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:124
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1741
llvm::AMDGPU::MTBUFFormat::NFMT_MIN
@ NFMT_MIN
Definition: SIDefines.h:508
llvm::AMDGPU::VOPDInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:287
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:368
llvm::AMDGPU::SMInfo::IsBuffer
bool IsBuffer
Definition: AMDGPUBaseInfo.cpp:268
llvm::AMDGPU::Hwreg::OFFSET_MASK_
@ OFFSET_MASK_
Definition: SIDefines.h:420
llvm::AMDGPU::Hwreg::isValidHwregWidth
bool isValidHwregWidth(int64_t Width)
Definition: AMDGPUBaseInfo.cpp:1321
llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1275
llvm::AMDGPU::shouldEmitConstantsToTextSection
bool shouldEmitConstantsToTextSection(const Triple &TT)
Definition: AMDGPUBaseInfo.cpp:995
llvm::AMDGPU::SendMsg::getMsgId
int64_t getMsgId(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1544
llvm::AMDGPU::Hwreg::WIDTH_M1_SHIFT_
@ WIDTH_M1_SHIFT_
Definition: SIDefines.h:430
llvm::AMDGPU::DepCtr::DepCtrInfo
const CustomOperandVal DepCtrInfo[]
Definition: AMDGPUAsmUtils.cpp:18
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:208
llvm::StringRef::empty
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
llvm::AMDGPU::Hwreg::isValidHwreg
bool isValidHwreg(int64_t Id)
Definition: AMDGPUBaseInfo.cpp:1313
llvm::AMDGPU::UfmtGFX11::UFMT_FIRST
@ UFMT_FIRST
Definition: SIDefines.h:717
llvm::AMDGPU::isVI
bool isVI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1754
llvm::AMDGPU::VOPDInfo::OpY
uint16_t OpY
Definition: AMDGPUBaseInfo.cpp:289
llvm::AMDGPU::MUBUFInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.cpp:249
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:160
llvm::AMDGPU::isInlinableLiteralV216
bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2162
llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET
@ HOSTCALL_PTR_OFFSET
Definition: SIDefines.h:899
llvm::cl::opt
Definition: CommandLine.h:1399
llvm::AMDGPU::Exp::ET_PARAM_MAX_IDX
@ ET_PARAM_MAX_IDX
Definition: SIDefines.h:879
llvm::AMDGPU::getRegBitWidth
unsigned getRegBitWidth(unsigned RCID)
Get the size in bits of a register from the register class RC.
Definition: AMDGPUBaseInfo.cpp:1984
llvm::AMDGPU::MTBUFFormat::NFMT_MAX
@ NFMT_MAX
Definition: SIDefines.h:509
llvm::AMDGPU::getExpcntBitMask
unsigned getExpcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1045
llvm::MCInstrDesc::NumOperands
unsigned short NumOperands
Definition: MCInstrDesc.h:200
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition
unsigned getMultigridSyncArgImplicitArgPosition()
Definition: AMDGPUBaseInfo.cpp:157
llvm::divideCeil
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:684
llvm::AMDGPU::isHsaAbiVersion4
bool isHsaAbiVersion4(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:136
llvm::AMDGPU::IsaInfo::getMinNumSGPRs
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:760
llvm::AMDGPU::isInlinableIntLiteral
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
Definition: AMDGPUBaseInfo.h:940
llvm::AMDGPU::hasG16
bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1737
AMDGPUMCTargetDesc.h
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:416
llvm::AMDGPU::SMInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:267
uint64_t
llvm::AMDGPU::MTBUFFormat::NFMT_MASK
@ NFMT_MASK
Definition: SIDefines.h:515
llvm::Triple::getOS
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:355
llvm::AMDGPU::isVOPC64DPP
bool isVOPC64DPP(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:403
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:172
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1758
llvm::AMDGPU::MTBUFFormat::DFMT_SHIFT
@ DFMT_SHIFT
Definition: SIDefines.h:493
llvm::AMDGPU::SendMsg::ID_MASK_GFX11Plus_
@ ID_MASK_GFX11Plus_
Definition: SIDefines.h:345
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
llvm::AMDGPU::initDefaultAMDKernelCodeT
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:911
llvm::AMDGPU::getIntegerAttribute
int getIntegerAttribute(const Function &F, StringRef Name, int Default)
Definition: AMDGPUBaseInfo.cpp:999
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1
@ ET_DUAL_SRC_BLEND1
Definition: SIDefines.h:869
llvm::AMDGPU::VOPInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:272
llvm::AMDGPU::OPERAND_SRC_FIRST
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:203
amd_kernel_code_t::call_convention
int32_t call_convention
Definition: AMDKernelCodeT.h:645
llvm::MCSubtargetInfo::getCPU
StringRef getCPU() const
Definition: MCSubtargetInfo.h:109
llvm::AMDGPU::MUBUFInfo::IsBufferInv
bool IsBufferInv
Definition: AMDGPUBaseInfo.cpp:254
llvm::AMDGPU::OPR_ID_UNKNOWN
const int OPR_ID_UNKNOWN
Definition: AMDGPUAsmUtils.h:23
llvm::DenormalMode
Represent subnormal handling kind for floating point instruction inputs and outputs.
Definition: FloatingPointMode.h:69
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:439
llvm::AMDGPU::getGcnBufferFormatInfo
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:2395
llvm::AMDGPU::SendMsg::OP_UNKNOWN_
@ OP_UNKNOWN_
Definition: SIDefines.h:349
llvm::AMDGPU::IsaInfo::getWavefrontSize
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:654
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V2
@ ELFABIVERSION_AMDGPU_HSA_V2
Definition: ELF.h:374
llvm::AMDGPU::isSISrcInlinableOperand
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
Definition: AMDGPUBaseInfo.cpp:1975
llvm::AMDGPU::Hwreg::isValidHwregOffset
bool isValidHwregOffset(int64_t Offset)
Definition: AMDGPUBaseInfo.cpp:1317
llvm::AMDGPU::SIModeRegisterDefaults::DX10Clamp
bool DX10Clamp
Used by the vector ALU to force DX10-style treatment of NaNs: when set, clamp NaN to zero; otherwise,...
Definition: AMDGPUBaseInfo.h:1024
llvm::AMDGPU::CanBeVOPD
Definition: AMDGPUBaseInfo.h:473
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::AMDGPU::encodeVmcnt
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
Definition: AMDGPUBaseInfo.cpp:1098
llvm::CallingConv::AMDGPU_KERNEL
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:201
llvm::AMDGPU::getAddrSizeMIMGOp
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:219
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::getXnackSetting
TargetIDSetting getXnackSetting() const
Definition: AMDGPUBaseInfo.h:135
llvm::CallingConv::AMDGPU_ES
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:219
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16InputDenormals
bool FP64FP16InputDenormals
If this is set, neither input or output denormals are flushed for both f64 and f16/v2f16 instructions...
Definition: AMDGPUBaseInfo.h:1033
amd_kernel_code_t::amd_machine_version_stepping
uint16_t amd_machine_version_stepping
Definition: AMDKernelCodeT.h:532
llvm::AMDGPU::isGFX9_GFX10
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1762
amd_kernel_code_t::group_segment_alignment
uint8_t group_segment_alignment
Definition: AMDKernelCodeT.h:635
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::AMDGPU::Waitcnt::LgkmCnt
unsigned LgkmCnt
Definition: AMDGPUBaseInfo.h:551
llvm::AMDGPU::Exp::isSupportedTgtId
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1400
llvm::AMDGPU::IsaInfo::getTotalNumSGPRs
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:741
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::isGFX10Before1030
bool isGFX10Before1030(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1802
llvm::AMDGPU::VOPInfo
Definition: AMDGPUBaseInfo.cpp:271
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:174
llvm::AMDGPU::Exp::ET_MRT0
@ ET_MRT0
Definition: SIDefines.h:859
llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:748
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:161
llvm::DenormalMode::IEEE
@ IEEE
IEEE-754 denormal numbers preserved.
Definition: FloatingPointMode.h:76
llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1505
llvm::AMDGPU::IsaInfo::getNumSGPRBlocks
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
Definition: AMDGPUBaseInfo.cpp:825
amd_kernel_code_t::kernarg_segment_alignment
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment.
Definition: AMDKernelCodeT.h:634
amd_kernel_code_t::amd_kernel_code_version_minor
uint32_t amd_kernel_code_version_minor
Definition: AMDKernelCodeT.h:528
llvm::AMDGPU::Exp::ExpTgtInfo
static constexpr ExpTgt ExpTgtInfo[]
Definition: AMDGPUBaseInfo.cpp:1356
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:187
llvm::AMDGPU::IsaInfo::TargetIDSetting::Off
@ Off
llvm::AMDGPU::MTBUFFormat::DFMT_MIN
@ DFMT_MIN
Definition: SIDefines.h:487
llvm::AMDGPU::MIMGInfo::BaseOpcode
uint16_t BaseOpcode
Definition: AMDGPUBaseInfo.h:402
llvm::AMDGPU::CustomOperand
Definition: AMDGPUAsmUtils.h:28
llvm::AMDGPU::isInlinableLiteral16
bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2143
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:307
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicGFX10
const StringLiteral NfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:160
llvm::AMDGPU::isDwordAligned
static bool isDwordAligned(uint64_t ByteOffset)
Definition: AMDGPUBaseInfo.cpp:2250
llvm::AMDGPU::Exp::ExpTgt::Tgt
unsigned Tgt
Definition: AMDGPUBaseInfo.cpp:1352
llvm::AMDGPU::isHsaAbiVersion5
bool isHsaAbiVersion5(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:142
llvm::AMDGPU::DepCtr::DEP_CTR_SIZE
const int DEP_CTR_SIZE
Definition: AMDGPUAsmUtils.cpp:30
llvm::AMDGPU::hasSMRDSignedImmOffset
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
Definition: AMDGPUBaseInfo.cpp:2232
llvm::AMDGPU::Exp::ET_MRTZ
@ ET_MRTZ
Definition: SIDefines.h:861
llvm::AMDGPU::MTBUFFormat::UFMT_UNDEF
@ UFMT_UNDEF
Definition: SIDefines.h:531
llvm::AMDGPU::Exp::ExpTgt::MaxIndex
unsigned MaxIndex
Definition: AMDGPUBaseInfo.cpp:1353
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
llvm::AMDGPU::WMMAOpcodeMappingInfo
Definition: AMDGPUBaseInfo.h:371
llvm::AMDGPU::isNotGFX10Plus
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1798
llvm::AMDGPU::SendMsg::isValidMsgId
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1549
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1282
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
AMDGPU.h
MAP_REG2REG
#define MAP_REG2REG
Definition: AMDGPUBaseInfo.cpp:1856
llvm::AMDGPU::getVOP3IsSingle
bool getVOP3IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:398
llvm::AMDGPU::Hwreg::OFFSET_SHIFT_
@ OFFSET_SHIFT_
Definition: SIDefines.h:418
llvm::AMDGPU::isModuleEntryFunctionCC
bool isModuleEntryFunctionCC(CallingConv::ID CC)
Definition: AMDGPUBaseInfo.cpp:1708
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::AMDGPU::isCompute
bool isCompute(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1687
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:846
llvm::MCRegisterClass::getID
unsigned getID() const
getID() - Return the register class ID number.
Definition: MCRegisterInfo.h:48
uint32_t
llvm::AMDGPU::IsaInfo::getNumVGPRBlocks
unsigned getNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:901
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates
bool Coordinates
Definition: AMDGPUBaseInfo.h:311
llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
Definition: AMDGPUBaseInfo.cpp:2236
llvm::AMDGPU::isSISrcOperand
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Can this operand also contain immediate values?
Definition: AMDGPUBaseInfo.cpp:1939
CC
auto CC
Definition: RISCVRedundantCopyElimination.cpp:79
llvm::AMDGPU::isGraphics
bool isGraphics(CallingConv::ID cc)
Definition: AMDGPUBaseInfo.cpp:1683
amd_kernel_code_t
AMD Kernel Code Object (amd_kernel_code_t).
Definition: AMDKernelCodeT.h:526
llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
Definition: AMDGPUBaseInfo.h:94
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isXnackSupported
bool isXnackSupported() const
Definition: AMDGPUBaseInfo.h:116
llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:718
llvm::AMDGPU::Exp::getTgtName
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
Definition: AMDGPUBaseInfo.cpp:1366
llvm::AMDGPU::Waitcnt::VmCnt
unsigned VmCnt
Definition: AMDGPUBaseInfo.h:549
llvm::AMDGPU::getMTBUFHasVAddr
bool getMTBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:333
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
AMDHSA_BITS_SET
#define AMDHSA_BITS_SET(DST, MSK, VAL)
Definition: AMDHSAKernelDescriptor.h:42
amd_kernel_code_t::kernel_code_entry_byte_offset
int64_t kernel_code_entry_byte_offset
Byte offset (possibly negative) from start of amd_kernel_code_t object to kernel's entry point instru...
Definition: AMDKernelCodeT.h:544
llvm::AMDGPU::MTBUFFormat::UfmtSymbolicGFX10
const StringLiteral UfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:193
llvm::AMDGPU::GcnBufferFormatInfo
Definition: AMDGPUBaseInfo.h:66
llvm::AMDGPU::isGFX8_GFX9_GFX10
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1766
llvm::AMDGPU::MTBUFFormat::getUnifiedFormat
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1480
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1774
llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor
amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:947
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::MTBUFFormat::UFMT_DEFAULT
@ UFMT_DEFAULT
Definition: SIDefines.h:532
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
amd_kernel_code_t::amd_machine_kind
uint16_t amd_machine_kind
Definition: AMDKernelCodeT.h:529
llvm::AMDGPU::SIModeRegisterDefaults::FP64FP16OutputDenormals
bool FP64FP16OutputDenormals
Definition: AMDGPUBaseInfo.h:1034
llvm::AMDGPU::isGroupSegment
bool isGroupSegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:981
llvm::AMDGPU::SendMsg::STREAM_ID_FIRST_
@ STREAM_ID_FIRST_
Definition: SIDefines.h:375
llvm::AMDGPU::SMInfo
Definition: AMDGPUBaseInfo.cpp:266
llvm::StringRef::size
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
llvm::AMDGPU::encodeWaitcnt
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
Definition: AMDGPUBaseInfo.cpp:1119
llvm::AMDGPU::SendMsg::isValidMsgOp
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1570
llvm::AMDGPU::SendMsg::OP_SYS_FIRST_
@ OP_SYS_FIRST_
Definition: SIDefines.h:368
Attributes.h
llvm::AMDGPU::isSI
bool isSI(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1746
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4
@ ELFABIVERSION_AMDGPU_HSA_V4
Definition: ELF.h:376
llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:188
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString
std::string toString() const
Definition: AMDGPUBaseInfo.cpp:547
amd_kernel_code_t::amd_machine_version_major
uint16_t amd_machine_version_major
Definition: AMDKernelCodeT.h:530
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
llvm::Any
Definition: Any.h:28
llvm::AMDGPU::OPERAND_SRC_LAST
@ OPERAND_SRC_LAST
Definition: SIDefines.h:204
llvm::AMDGPU::isArgPassedInSGPR
bool isArgPassedInSGPR(const Argument *A)
Definition: AMDGPUBaseInfo.cpp:2201
llvm::AMDGPU::UfmtGFX11::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:718
llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET
@ MULTIGRID_SYNC_ARG_OFFSET
Definition: SIDefines.h:900
llvm::AMDGPU::Waitcnt
Represents the counter values to wait for in an s_waitcnt instruction.
Definition: AMDGPUBaseInfo.h:548
llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND_MAX_IDX
@ ET_DUAL_SRC_BLEND_MAX_IDX
Definition: SIDefines.h:878
llvm::AMDGPU::Hwreg::Opr
const CustomOperand< const MCSubtargetInfo & > Opr[]
Definition: AMDGPUAsmUtils.cpp:90
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
llvm::AMDGPU::SendMsg::decodeMsg
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1629
amd_kernel_code_t::private_segment_alignment
uint8_t private_segment_alignment
Definition: AMDKernelCodeT.h:636
llvm::AMDGPU::SIModeRegisterDefaults::SIModeRegisterDefaults
SIModeRegisterDefaults()
Definition: AMDGPUBaseInfo.h:1036
llvm::AMDGPU::decodeCustomOperand
static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1223
llvm::AMDGPU::getMUBUFHasVAddr
bool getMUBUFHasVAddr(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:363
llvm::AMDGPU::isInlinableLiteral64
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
Definition: AMDGPUBaseInfo.cpp:2100
llvm::AMDGPU::OPERAND_REG_IMM_V2INT16
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:163
uint16_t
llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:375
llvm::AMDGPU::getMUBUFElements
int getMUBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:358
llvm::AMDGPU::encodeCustomOperandVal
static int encodeCustomOperandVal(const CustomOperandVal &Op, int64_t InputVal)
Definition: AMDGPUBaseInfo.cpp:1240
llvm::AMDGPU::MTBUFFormat::DFMT_NFMT_DEFAULT
@ DFMT_NFMT_DEFAULT
Definition: SIDefines.h:520
llvm::AMDGPU::SendMsg::getMsgOpId
int64_t getMsgOpId(int64_t MsgId, const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1558
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::AMDGPU::Exp::ET_POS4
@ ET_POS4
Definition: SIDefines.h:865
llvm::Align::value
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85
llvm::FPOpFusion::Strict
@ Strict
Definition: TargetOptions.h:39
amd_kernel_code_t::code_properties
uint32_t code_properties
Code properties.
Definition: AMDKernelCodeT.h:562
llvm::AMDGPU::isFoldableLiteralV216
bool isFoldableLiteralV216(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2188
llvm::CallingConv::SPIR_KERNEL
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:141
llvm::StringRef::endswith
bool endswith(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:265
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:175
llvm::AMDGPU::CustomOperand::Cond
bool(* Cond)(T Context)
Definition: AMDGPUAsmUtils.h:31
llvm::AMDGPU::MIMGInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.h:401
Function.h
llvm::AMDGPU::MUBUFInfo::has_vaddr
bool has_vaddr
Definition: AMDGPUBaseInfo.cpp:251
llvm::AMDGPU::OPERAND_REG_INLINE_C_FIRST
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:197
llvm::amdhsa::kernel_descriptor_t
Definition: AMDHSAKernelDescriptor.h:170
llvm::AMDGPU::getVOP1IsSingle
bool getVOP1IsSingle(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:388
llvm::AMDGPU::getVOPDOpcode
unsigned getVOPDOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:425
llvm::AMDGPU::splitMUBUFOffset
bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, const GCNSubtarget *Subtarget, Align Alignment)
Definition: AMDGPUBaseInfo.cpp:2304
llvm::AMDGPU::SendMsg::STREAM_ID_NONE_
@ STREAM_ID_NONE_
Definition: SIDefines.h:372
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:400
llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
Definition: AMDGPUBaseInfo.cpp:1475
llvm::AMDGPU::Exp::getTgtId
unsigned getTgtId(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1377
llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:439
llvm::CallingConv::AMDGPU_HS
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:207
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicSICI
const StringLiteral NfmtSymbolicSICI[]
Definition: AMDGPUAsmUtils.cpp:171
llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT
@ NFMT_SHIFT
Definition: SIDefines.h:514
llvm::AMDGPU::getTotalNumVGPRs
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
Definition: AMDGPUBaseInfo.cpp:1842
llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:177
llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:866
llvm::AMDGPU::SendMsg::isValidMsgStream
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
Definition: AMDGPUBaseInfo.cpp:1596
llvm::AMDGPU::MTBUFFormat::getNfmtName
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1455
AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
Definition: AMDKernelCodeT.h:127
llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1
uint32_t compute_pgm_rsrc1
Definition: AMDHSAKernelDescriptor.h:178
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::AMDGPU::SendMsg::STREAM_ID_SHIFT_
@ STREAM_ID_SHIFT_
Definition: SIDefines.h:376
llvm::AMDGPU::getLgkmcntBitMask
unsigned getLgkmcntBitMask(const IsaVersion &Version)
Definition: AMDGPUBaseInfo.cpp:1049
llvm::GlobalValue::getAddressSpace
unsigned getAddressSpace() const
Definition: Globals.cpp:121
llvm::GCNSubtarget::getGeneration
Generation getGeneration() const
Definition: GCNSubtarget.h:264
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::AMDGPU::Hwreg::WIDTH_M1_MASK_
@ WIDTH_M1_MASK_
Definition: SIDefines.h:432
llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs
uint8_t NumExtraArgs
Definition: AMDGPUBaseInfo.h:308
llvm::AMDGPU::isInlinableLiteral32
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
Definition: AMDGPUBaseInfo.cpp:2117
llvm::AMDGPU::isSISrcFPOperand
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
Definition: AMDGPUBaseInfo.cpp:1946
llvm::AMDGPU::isGFX8Plus
bool isGFX8Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1770
llvm::FeatureBitset::test
constexpr bool test(unsigned I) const
Definition: SubtargetFeature.h:87
llvm::AMDGPU::isNotGFX11Plus
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1794
llvm::AMDGPU::encodeExpcnt
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
Definition: AMDGPUBaseInfo.cpp:1107
llvm::AMDGPU::Exp::ET_POS_MAX_IDX
@ ET_POS_MAX_IDX
Definition: SIDefines.h:877
llvm::AMDGPU::isGCN3Encoding
bool isGCN3Encoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1806
llvm::AMDGPU::MTBUFFormat::getNfmt
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1446
llvm::AMDGPU::Exp::ExpTgt
Definition: AMDGPUBaseInfo.cpp:1350
llvm::AMDGPU::isValidOpr
static bool isValidOpr(int Idx, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
Definition: AMDGPUBaseInfo.cpp:1144
llvm::AMDGPU::SendMsg::getMsgOpName
StringRef getMsgOpName(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1590
llvm::AMDGPU::VOPDComponentInfo::BaseVOP
uint16_t BaseVOP
Definition: AMDGPUBaseInfo.cpp:281
llvm::AMDGPU::Exp::ET_PRIM_MAX_IDX
@ ET_PRIM_MAX_IDX
Definition: SIDefines.h:875
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:371
llvm::AMDGPU::getNumFlatOffsetBits
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed)
For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
Definition: AMDGPUBaseInfo.cpp:2289
llvm::AMDGPU::SendMsg::ID_GS_DONE_PreGFX11
@ ID_GS_DONE_PreGFX11
Definition: SIDefines.h:322
N
#define N
AMDKernelCodeT.h
llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
Definition: AMDGPUBaseInfo.cpp:708
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:195
llvm::AMDGPU::IsaInfo::getMaxWavesPerEU
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:699
llvm::AMDGPU::isHsaAbiVersion3AndAbove
bool isHsaAbiVersion3AndAbove(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:148
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmtGFX10
const unsigned DfmtNfmt2UFmtGFX10[]
Definition: AMDGPUAsmUtils.cpp:287
llvm::AMDGPU::IsaInfo::getMinNumVGPRs
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
Definition: AMDGPUBaseInfo.cpp:881
llvm::AMDGPU::MTBUFFormat::UFMT_MAX
@ UFMT_MAX
Definition: SIDefines.h:530
llvm::AMDGPU::hasMIMG_R128
bool hasMIMG_R128(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1729
llvm::AMDGPU::getCanBeVOPD
CanBeVOPD getCanBeVOPD(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:417
llvm::AMDGPU::MIMGBaseOpcodeInfo::G16
bool G16
Definition: AMDGPUBaseInfo.h:310
llvm::AMDGPU::Exp::ET_NULL_MAX_IDX
@ ET_NULL_MAX_IDX
Definition: SIDefines.h:873
llvm::DenormalMode::Output
DenormalModeKind Output
Denormal flushing mode for floating point instruction results in the default floating point environme...
Definition: FloatingPointMode.h:87
llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:171
llvm::StringRef::str
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:221
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs
constexpr char NumVGPRs[]
Key for Kernel::CodeProps::Metadata::mNumVGPRs.
Definition: AMDGPUMetadata.h:260
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromFeaturesString
void setTargetIDFromFeaturesString(StringRef FS)
Definition: AMDGPUBaseInfo.cpp:467
llvm::AMDGPU::isReadOnlySegment
bool isReadOnlySegment(const GlobalValue *GV)
Definition: AMDGPUBaseInfo.cpp:989
llvm::AMDGPU::SendMsg::OP_NONE_
@ OP_NONE_
Definition: SIDefines.h:351
llvm::AMDGPU::isLegalSMRDEncodedSignedOffset
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
Definition: AMDGPUBaseInfo.cpp:2242
llvm::AMDGPU::VOPDComponentInfo::CanBeVOPDX
bool CanBeVOPDX
Definition: AMDGPUBaseInfo.cpp:283
llvm::AMDGPU::OPERAND_REG_IMM_FP16
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:159
llvm::AMDGPU::Exp::ET_PARAM31
@ ET_PARAM31
Definition: SIDefines.h:871
S_00B848_WGP_MODE
#define S_00B848_WGP_MODE(x)
Definition: SIDefines.h:1008
LLVMContext.h
llvm::AMDGPU::encodeLgkmcnt
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
Definition: AMDGPUBaseInfo.cpp:1113
llvm::AMDGPU::MAIInstInfo
Definition: AMDGPUBaseInfo.h:74
llvm::cl::desc
Definition: CommandLine.h:412
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:189
llvm::AMDGPU::MTBUFFormat::getDfmt
int64_t getDfmt(const StringRef Name)
Definition: AMDGPUBaseInfo.cpp:1425
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmtGFX11
const unsigned DfmtNfmt2UFmtGFX11[]
Definition: AMDGPUAsmUtils.cpp:461
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:241
llvm::AMDGPU::CustomOperandVal
Definition: AMDGPUAsmUtils.h:34
llvm::AMDGPU::Waitcnt::ExpCnt
unsigned ExpCnt
Definition: AMDGPUBaseInfo.h:550
llvm::AMDGPU::getIntegerPairAttribute
std::pair< int, int > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
Definition: AMDGPUBaseInfo.cpp:1014
llvm::AMDGPU::IsaInfo::AMDGPUTargetID::isSramEccSupported
bool isSramEccSupported() const
Definition: AMDGPUBaseInfo.h:145
llvm::AMDGPU::SendMsg::ID_GS_PreGFX11
@ ID_GS_PreGFX11
Definition: SIDefines.h:321
llvm::AMDGPU::MTBUFInfo::Opcode
uint16_t Opcode
Definition: AMDGPUBaseInfo.cpp:258
llvm::AMDGPU::isKernelCC
bool isKernelCC(const Function *Func)
Definition: AMDGPUBaseInfo.cpp:1717
llvm::AMDGPU::MTBUFInfo::has_srsrc
bool has_srsrc
Definition: AMDGPUBaseInfo.cpp:262
llvm::AMDGPU::getHostcallImplicitArgPosition
unsigned getHostcallImplicitArgPosition()
Definition: AMDGPUBaseInfo.cpp:174
llvm::AMDGPU::SendMsg::getMsgIdMask
static uint64_t getMsgIdMask(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1540
llvm::AMDGPU::SendMsg::OP_MASK_
@ OP_MASK_
Definition: SIDefines.h:354
llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1495
llvm::AMDGPU::VOPDComponentInfo
Definition: AMDGPUBaseInfo.cpp:280
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::AMDGPU::MUBUFInfo
Definition: AMDGPUBaseInfo.cpp:247
llvm::AMDGPU::Exp::ET_MRT_MAX_IDX
@ ET_MRT_MAX_IDX
Definition: SIDefines.h:876
llvm::StringRef::split
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:689
llvm::AMDGPU::getHasColorExport
bool getHasColorExport(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1657
llvm::AMDGPU::getHasDepthExport
bool getHasDepthExport(const Function &F)
Definition: AMDGPUBaseInfo.cpp:1664
llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V3
@ ELFABIVERSION_AMDGPU_HSA_V3
Definition: ELF.h:375
llvm::AMDGPU::IsaInfo::getVGPRAllocGranule
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:831
llvm::AMDGPU::SendMsg::getMsgName
StringRef getMsgName(int64_t MsgId, const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1553
llvm::AMDGPU::getMaskedMIMGOp
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
Definition: AMDGPUBaseInfo.cpp:211
llvm::AMDGPU::getMTBUFElements
int getMTBUFElements(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:328
llvm::AMDGPU::OPERAND_REG_INLINE_C_LAST
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:198
llvm::AMDGPU::UfmtGFX10::UFMT_LAST
@ UFMT_LAST
Definition: SIDefines.h:632
AMDGPUBaseInfo.h
llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:190
llvm::AMDGPU::getOprIdx
static int getOprIdx(std::function< bool(const CustomOperand< T > &)> Test, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
Definition: AMDGPUBaseInfo.cpp:1151
llvm::AMDGPU::MTBUFFormat::DFMT_MAX
@ DFMT_MAX
Definition: SIDefines.h:488
llvm::AMDGPU::MIMGDimInfo::NumCoords
uint8_t NumCoords
Definition: AMDGPUBaseInfo.h:326