LLVM 17.0.0git
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AMDGPUBaseInfo.cpp File Reference
#include "AMDGPUBaseInfo.h"
#include "AMDGPU.h"
#include "AMDGPUAsmUtils.h"
#include "AMDKernelCodeT.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/TargetParser/TargetParser.h"
#include <optional>
#include "AMDGPUGenInstrInfo.inc"
#include "AMDGPUGenSearchableTables.inc"

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Classes

struct  llvm::AMDGPU::MUBUFInfo
 
struct  llvm::AMDGPU::MTBUFInfo
 
struct  llvm::AMDGPU::SMInfo
 
struct  llvm::AMDGPU::VOPInfo
 
struct  llvm::AMDGPU::VOPC64DPPInfo
 
struct  llvm::AMDGPU::VOPDComponentInfo
 
struct  llvm::AMDGPU::VOPDInfo
 
struct  llvm::AMDGPU::VOPTrue16Info
 
struct  llvm::AMDGPU::Exp::ExpTgt
 

Namespaces

namespace  llvm
 This is an optimization pass for GlobalISel generic memory operations.
 
namespace  llvm::AMDGPU
 
namespace  llvm::AMDGPU::VOPD
 
namespace  llvm::AMDGPU::IsaInfo
 
namespace  llvm::AMDGPU::DepCtr
 
namespace  llvm::AMDGPU::Hwreg
 
namespace  llvm::AMDGPU::Exp
 
namespace  llvm::AMDGPU::MTBUFFormat
 
namespace  llvm::AMDGPU::SendMsg
 

Macros

#define GET_INSTRINFO_NAMED_OPS
 
#define GET_INSTRMAP_INFO
 
#define GET_MIMGBaseOpcodesTable_IMPL
 
#define GET_MIMGDimInfoTable_IMPL
 
#define GET_MIMGInfoTable_IMPL
 
#define GET_MIMGLZMappingTable_IMPL
 
#define GET_MIMGMIPMappingTable_IMPL
 
#define GET_MIMGBiasMappingTable_IMPL
 
#define GET_MIMGOffsetMappingTable_IMPL
 
#define GET_MIMGG16MappingTable_IMPL
 
#define GET_MAIInstInfoTable_IMPL
 
#define GET_MTBUFInfoTable_DECL
 
#define GET_MTBUFInfoTable_IMPL
 
#define GET_MUBUFInfoTable_DECL
 
#define GET_MUBUFInfoTable_IMPL
 
#define GET_SMInfoTable_DECL
 
#define GET_SMInfoTable_IMPL
 
#define GET_VOP1InfoTable_DECL
 
#define GET_VOP1InfoTable_IMPL
 
#define GET_VOP2InfoTable_DECL
 
#define GET_VOP2InfoTable_IMPL
 
#define GET_VOP3InfoTable_DECL
 
#define GET_VOP3InfoTable_IMPL
 
#define GET_VOPC64DPPTable_DECL
 
#define GET_VOPC64DPPTable_IMPL
 
#define GET_VOPC64DPP8Table_DECL
 
#define GET_VOPC64DPP8Table_IMPL
 
#define GET_VOPDComponentTable_DECL
 
#define GET_VOPDComponentTable_IMPL
 
#define GET_VOPDPairs_DECL
 
#define GET_VOPDPairs_IMPL
 
#define GET_VOPTrue16Table_DECL
 
#define GET_VOPTrue16Table_IMPL
 
#define GET_WMMAOpcode2AddrMappingTable_DECL
 
#define GET_WMMAOpcode2AddrMappingTable_IMPL
 
#define GET_WMMAOpcode3AddrMappingTable_DECL
 
#define GET_WMMAOpcode3AddrMappingTable_IMPL
 
#define MAP_REG2REG
 
#define CASE_CI_VI(node)
 
#define CASE_VI_GFX9PLUS(node)    case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
 
#define CASE_GFXPRE11_GFX11PLUS(node)    case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
 
#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)    case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
 
#define CASE_CI_VI(node)   case node##_ci: case node##_vi: return node;
 
#define CASE_VI_GFX9PLUS(node)   case node##_vi: case node##_gfx9plus: return node;
 
#define CASE_GFXPRE11_GFX11PLUS(node)   case node##_gfx11plus: case node##_gfxpre11: return node;
 
#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
 
#define GET_SourcesOfDivergence_IMPL
 
#define GET_UniformIntrinsics_IMPL
 
#define GET_Gfx9BufferFormat_IMPL
 
#define GET_Gfx10BufferFormat_IMPL
 
#define GET_Gfx11PlusBufferFormat_IMPL
 

Functions

std::optional< uint8_t > llvm::AMDGPU::getHsaAbiVersion (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion2 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion3 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion4 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion5 (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isHsaAbiVersion3AndAbove (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::getAmdhsaCodeObjectVersion ()
 
unsigned llvm::AMDGPU::getCodeObjectVersion (const Module &M)
 
unsigned llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion)
 
unsigned llvm::AMDGPU::getHostcallImplicitArgPosition (unsigned CodeObjectVersion)
 
unsigned llvm::AMDGPU::getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion)
 
unsigned llvm::AMDGPU::getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion)
 
int llvm::AMDGPU::getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
 
const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMaskedMIMGOp (unsigned Opc, unsigned NewChannels)
 
unsigned llvm::AMDGPU::getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
 
int llvm::AMDGPU::getMTBUFBaseOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMTBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int llvm::AMDGPU::getMTBUFElements (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasVAddr (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasSrsrc (unsigned Opc)
 
bool llvm::AMDGPU::getMTBUFHasSoffset (unsigned Opc)
 
int llvm::AMDGPU::getMUBUFBaseOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMUBUFOpcode (unsigned BaseOpc, unsigned Elements)
 
int llvm::AMDGPU::getMUBUFElements (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasVAddr (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasSrsrc (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFHasSoffset (unsigned Opc)
 
bool llvm::AMDGPU::getMUBUFIsBufferInv (unsigned Opc)
 
bool llvm::AMDGPU::getSMEMIsBuffer (unsigned Opc)
 
bool llvm::AMDGPU::getVOP1IsSingle (unsigned Opc)
 
bool llvm::AMDGPU::getVOP2IsSingle (unsigned Opc)
 
bool llvm::AMDGPU::getVOP3IsSingle (unsigned Opc)
 
bool llvm::AMDGPU::isVOPC64DPP (unsigned Opc)
 
bool llvm::AMDGPU::getMAIIsDGEMM (unsigned Opc)
 Returns true if MAI operation is a double precision GEMM.
 
bool llvm::AMDGPU::getMAIIsGFX940XDL (unsigned Opc)
 
CanBeVOPD llvm::AMDGPU::getCanBeVOPD (unsigned Opc)
 
unsigned llvm::AMDGPU::getVOPDOpcode (unsigned Opc)
 
bool llvm::AMDGPU::isVOPD (unsigned Opc)
 
bool llvm::AMDGPU::isMAC (unsigned Opc)
 
bool llvm::AMDGPU::isPermlane16 (unsigned Opc)
 
bool llvm::AMDGPU::isTrue16Inst (unsigned Opc)
 
unsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode (unsigned Opc)
 
unsigned llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode (unsigned Opc)
 
int llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen)
 
int llvm::AMDGPU::getVOPDFull (unsigned OpX, unsigned OpY)
 
std::pair< unsigned, unsigned > llvm::AMDGPU::getVOPDComponents (unsigned VOPDOpcode)
 
VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY)
 
VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo)
 
static TargetIDSetting llvm::AMDGPU::IsaInfo::getTargetIDSettingFromFeatureString (StringRef FeatureString)
 
unsigned llvm::AMDGPU::IsaInfo::getWavefrontSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getLocalMemorySize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableLocalMemorySize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getEUsPerCU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
 
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
 
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed)
 
unsigned llvm::AMDGPU::IsaInfo::getNumSGPRBlocks (const MCSubtargetInfo *STI, unsigned NumSGPRs)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
 
unsigned llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
 
unsigned llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const MCSubtargetInfo *STI)
 
unsigned llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (const MCSubtargetInfo *STI, unsigned NumVGPRs)
 
unsigned llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU)
 
unsigned llvm::AMDGPU::IsaInfo::getNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
 
void llvm::AMDGPU::initDefaultAMDKernelCodeT (amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
 
amdhsa::kernel_descriptor_t llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor (const MCSubtargetInfo *STI)
 
bool llvm::AMDGPU::isGroupSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV)
 
bool llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT)
 
std::pair< int, int > llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< int, int > Default, bool OnlyFirstRequired)
 
unsigned llvm::AMDGPU::getVmcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getExpcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getLgkmcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::getWaitcntBitMask (const IsaVersion &Version)
 
unsigned llvm::AMDGPU::decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt)
 
unsigned llvm::AMDGPU::decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt)
 
void llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
 Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values into Vmcnt, Expcnt and Lgkmcnt respectively.
 
Waitcnt llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Encoded)
 
unsigned llvm::AMDGPU::encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
 
unsigned llvm::AMDGPU::encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
 
unsigned llvm::AMDGPU::encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
 
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
 Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
 
unsigned llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded)
 
template<class T >
static bool llvm::AMDGPU::isValidOpr (int Idx, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
 
template<class T >
static int llvm::AMDGPU::getOprIdx (std::function< bool(const CustomOperand< T > &)> Test, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
 
template<class T >
static int llvm::AMDGPU::getOprIdx (const StringRef Name, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context)
 
template<class T >
static int llvm::AMDGPU::getOprIdx (int Id, const CustomOperand< T > OpInfo[], int OpInfoSize, T Context, bool QuickCheck=true)
 
static unsigned llvm::AMDGPU::getDefaultCustomOperandEncoding (const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
 
static bool llvm::AMDGPU::isSymbolicCustomOperandEncoding (const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
 
static bool llvm::AMDGPU::decodeCustomOperand (const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
 
static int llvm::AMDGPU::encodeCustomOperandVal (const CustomOperandVal &Op, int64_t InputVal)
 
static int llvm::AMDGPU::encodeCustomOperand (const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
 
int llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding (unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::DepCtr::decodeDepCtr (unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
 
int llvm::AMDGPU::DepCtr::encodeDepCtr (const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::Hwreg::getHwregId (const StringRef Name, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::Hwreg::isValidHwreg (int64_t Id)
 
bool llvm::AMDGPU::Hwreg::isValidHwregOffset (int64_t Offset)
 
bool llvm::AMDGPU::Hwreg::isValidHwregWidth (int64_t Width)
 
uint64_t llvm::AMDGPU::Hwreg::encodeHwreg (uint64_t Id, uint64_t Offset, uint64_t Width)
 
StringRef llvm::AMDGPU::Hwreg::getHwreg (unsigned Id, const MCSubtargetInfo &STI)
 
void llvm::AMDGPU::Hwreg::decodeHwreg (unsigned Val, unsigned &Id, unsigned &Offset, unsigned &Width)
 
bool llvm::AMDGPU::Exp::getTgtName (unsigned Id, StringRef &Name, int &Index)
 
unsigned llvm::AMDGPU::Exp::getTgtId (const StringRef Name)
 
bool llvm::AMDGPU::Exp::isSupportedTgtId (unsigned Id, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::getDfmt (const StringRef Name)
 
StringRef llvm::AMDGPU::MTBUFFormat::getDfmtName (unsigned Id)
 
static StringLiteral const * llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable (const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::getNfmt (const StringRef Name, const MCSubtargetInfo &STI)
 
StringRef llvm::AMDGPU::MTBUFFormat::getNfmtName (unsigned Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt (unsigned Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::MTBUFFormat::isValidNfmt (unsigned Id, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt (unsigned Dfmt, unsigned Nfmt)
 
void llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt (unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
 
int64_t llvm::AMDGPU::MTBUFFormat::getUnifiedFormat (const StringRef Name, const MCSubtargetInfo &STI)
 
StringRef llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName (unsigned Id, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat (unsigned Id, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt (unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding (unsigned Val, const MCSubtargetInfo &STI)
 
unsigned llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding (const MCSubtargetInfo &STI)
 
static uint64_t llvm::AMDGPU::SendMsg::getMsgIdMask (const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::SendMsg::getMsgId (const StringRef Name, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::SendMsg::isValidMsgId (int64_t MsgId, const MCSubtargetInfo &STI)
 
StringRef llvm::AMDGPU::SendMsg::getMsgName (int64_t MsgId, const MCSubtargetInfo &STI)
 
int64_t llvm::AMDGPU::SendMsg::getMsgOpId (int64_t MsgId, const StringRef Name)
 
bool llvm::AMDGPU::SendMsg::isValidMsgOp (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
 
StringRef llvm::AMDGPU::SendMsg::getMsgOpName (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::SendMsg::isValidMsgStream (int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
 
bool llvm::AMDGPU::SendMsg::msgRequiresOp (int64_t MsgId, const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::SendMsg::msgSupportsStream (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
 
void llvm::AMDGPU::SendMsg::decodeMsg (unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
 
uint64_t llvm::AMDGPU::SendMsg::encodeMsg (uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
 
unsigned llvm::AMDGPU::getInitialPSInputAddr (const Function &F)
 
bool llvm::AMDGPU::getHasColorExport (const Function &F)
 
bool llvm::AMDGPU::getHasDepthExport (const Function &F)
 
bool llvm::AMDGPU::isShader (CallingConv::ID cc)
 
bool llvm::AMDGPU::isGraphics (CallingConv::ID cc)
 
bool llvm::AMDGPU::isCompute (CallingConv::ID cc)
 
bool llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC)
 
bool llvm::AMDGPU::isModuleEntryFunctionCC (CallingConv::ID CC)
 
bool llvm::AMDGPU::isKernelCC (const Function *Func)
 
bool llvm::AMDGPU::hasXNACK (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasSRAMECC (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasMIMG_R128 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasA16 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasG16 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasPackedD16 (const MCSubtargetInfo &STI)
 
unsigned llvm::AMDGPU::getNSAMaxSize (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isSI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isCI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isVI (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9_GFX10 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX8Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX9Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX11 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX11Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isNotGFX11Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isNotGFX10Plus (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10Before1030 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGCN3Encoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10_AEncoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX10_BEncoding (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasGFX10_3Insts (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX90A (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::isGFX940 (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasArchitectedFlatScratch (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasMAIInsts (const MCSubtargetInfo &STI)
 
bool llvm::AMDGPU::hasVOPD (const MCSubtargetInfo &STI)
 
int32_t llvm::AMDGPU::getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
 
bool llvm::AMDGPU::isSGPR (unsigned Reg, const MCRegisterInfo *TRI)
 Is Reg - scalar register.
 
unsigned llvm::AMDGPU::getMCReg (unsigned Reg, const MCSubtargetInfo &STI)
 If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
 
unsigned llvm::AMDGPU::mc2PseudoReg (unsigned Reg)
 Convert hardware register Reg to a pseudo register.
 
bool llvm::AMDGPU::isInlineValue (unsigned Reg)
 
bool llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).
 
bool llvm::AMDGPU::isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this a KImm operand?
 
bool llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Is this floating-point operand?
 
bool llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo)
 Does this operand support only inlinable literals?
 
unsigned llvm::AMDGPU::getRegBitWidth (unsigned RCID)
 Get the size in bits of a register from the register class RC.
 
unsigned llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC)
 Get the size in bits of a register from the register class RC.
 
unsigned llvm::AMDGPU::getRegBitWidth (const TargetRegisterClass &RC)
 Get the size in bits of a register from the register class RC.
 
unsigned llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
 Get size of register operand.
 
bool llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi)
 Is this literal inlinable.
 
bool llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteral16 (int16_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isInlinableIntLiteralV216 (int32_t Literal)
 
bool llvm::AMDGPU::isFoldableLiteralV216 (int32_t Literal, bool HasInv2Pi)
 
bool llvm::AMDGPU::isArgPassedInSGPR (const Argument *A)
 
bool llvm::AMDGPU::isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo)
 
static bool llvm::AMDGPU::hasSMEMByteOffset (const MCSubtargetInfo &ST)
 
static bool llvm::AMDGPU::hasSMRDSignedImmOffset (const MCSubtargetInfo &ST)
 
bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset)
 
bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
 
static bool llvm::AMDGPU::isDwordAligned (uint64_t ByteOffset)
 
uint64_t llvm::AMDGPU::convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset)
 Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
 
std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
 
std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset)
 
unsigned llvm::AMDGPU::getNumFlatOffsetBits (const MCSubtargetInfo &ST)
 For FLAT segment the offset must be positive; MSB is ignored and forced to zero.
 
bool llvm::AMDGPU::isIntrinsicSourceOfDivergence (unsigned IntrID)
 
bool llvm::AMDGPU::isIntrinsicAlwaysUniform (unsigned IntrID)
 
const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
 
const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI)
 
raw_ostream & llvm::operator<< (raw_ostream &OS, const AMDGPU::IsaInfo::TargetIDSetting S)
 

Variables

static llvm::cl::opt< unsigned > AmdhsaCodeObjectVersion ("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4))
 
static constexpr ExpTgt llvm::AMDGPU::Exp::ExpTgtInfo []
 

Macro Definition Documentation

◆ CASE_CI_VI [1/2]

#define CASE_CI_VI (   node)
Value:
assert(!isSI(STI)); \
case node: return isCI(STI) ? node##_ci : node##_vi;
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())

Definition at line 2136 of file AMDGPUBaseInfo.cpp.

◆ CASE_CI_VI [2/2]

#define CASE_CI_VI (   node)    case node##_ci: case node##_vi: return node;

Definition at line 2136 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS [1/2]

#define CASE_GFXPRE11_GFX11PLUS (   node)     case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;

Definition at line 2138 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS [2/2]

#define CASE_GFXPRE11_GFX11PLUS (   node)    case node##_gfx11plus: case node##_gfxpre11: return node;

Definition at line 2138 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS_TO [1/2]

#define CASE_GFXPRE11_GFX11PLUS_TO (   node,
  result 
)     case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;

Definition at line 2139 of file AMDGPUBaseInfo.cpp.

◆ CASE_GFXPRE11_GFX11PLUS_TO [2/2]

#define CASE_GFXPRE11_GFX11PLUS_TO (   node,
  result 
)

Definition at line 2139 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9PLUS [1/2]

#define CASE_VI_GFX9PLUS (   node)     case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;

Definition at line 2137 of file AMDGPUBaseInfo.cpp.

◆ CASE_VI_GFX9PLUS [2/2]

#define CASE_VI_GFX9PLUS (   node)    case node##_vi: case node##_gfx9plus: return node;

Definition at line 2137 of file AMDGPUBaseInfo.cpp.

◆ GET_Gfx10BufferFormat_IMPL

#define GET_Gfx10BufferFormat_IMPL

Definition at line 2621 of file AMDGPUBaseInfo.cpp.

◆ GET_Gfx11PlusBufferFormat_IMPL

#define GET_Gfx11PlusBufferFormat_IMPL

Definition at line 2622 of file AMDGPUBaseInfo.cpp.

◆ GET_Gfx9BufferFormat_IMPL

#define GET_Gfx9BufferFormat_IMPL

Definition at line 2620 of file AMDGPUBaseInfo.cpp.

◆ GET_INSTRINFO_NAMED_OPS

#define GET_INSTRINFO_NAMED_OPS

Definition at line 31 of file AMDGPUBaseInfo.cpp.

◆ GET_INSTRMAP_INFO

#define GET_INSTRMAP_INFO

Definition at line 32 of file AMDGPUBaseInfo.cpp.

◆ GET_MAIInstInfoTable_IMPL

#define GET_MAIInstInfoTable_IMPL

Definition at line 225 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGBaseOpcodesTable_IMPL

#define GET_MIMGBaseOpcodesTable_IMPL

Definition at line 217 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGBiasMappingTable_IMPL

#define GET_MIMGBiasMappingTable_IMPL

Definition at line 222 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGDimInfoTable_IMPL

#define GET_MIMGDimInfoTable_IMPL

Definition at line 218 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGG16MappingTable_IMPL

#define GET_MIMGG16MappingTable_IMPL

Definition at line 224 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGInfoTable_IMPL

#define GET_MIMGInfoTable_IMPL

Definition at line 219 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGLZMappingTable_IMPL

#define GET_MIMGLZMappingTable_IMPL

Definition at line 220 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGMIPMappingTable_IMPL

#define GET_MIMGMIPMappingTable_IMPL

Definition at line 221 of file AMDGPUBaseInfo.cpp.

◆ GET_MIMGOffsetMappingTable_IMPL

#define GET_MIMGOffsetMappingTable_IMPL

Definition at line 223 of file AMDGPUBaseInfo.cpp.

◆ GET_MTBUFInfoTable_DECL

#define GET_MTBUFInfoTable_DECL

Definition at line 326 of file AMDGPUBaseInfo.cpp.

◆ GET_MTBUFInfoTable_IMPL

#define GET_MTBUFInfoTable_IMPL

Definition at line 327 of file AMDGPUBaseInfo.cpp.

◆ GET_MUBUFInfoTable_DECL

#define GET_MUBUFInfoTable_DECL

Definition at line 328 of file AMDGPUBaseInfo.cpp.

◆ GET_MUBUFInfoTable_IMPL

#define GET_MUBUFInfoTable_IMPL

Definition at line 329 of file AMDGPUBaseInfo.cpp.

◆ GET_SMInfoTable_DECL

#define GET_SMInfoTable_DECL

Definition at line 330 of file AMDGPUBaseInfo.cpp.

◆ GET_SMInfoTable_IMPL

#define GET_SMInfoTable_IMPL

Definition at line 331 of file AMDGPUBaseInfo.cpp.

◆ GET_SourcesOfDivergence_IMPL

#define GET_SourcesOfDivergence_IMPL

Definition at line 2618 of file AMDGPUBaseInfo.cpp.

◆ GET_UniformIntrinsics_IMPL

#define GET_UniformIntrinsics_IMPL

Definition at line 2619 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP1InfoTable_DECL

#define GET_VOP1InfoTable_DECL

Definition at line 332 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP1InfoTable_IMPL

#define GET_VOP1InfoTable_IMPL

Definition at line 333 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP2InfoTable_DECL

#define GET_VOP2InfoTable_DECL

Definition at line 334 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP2InfoTable_IMPL

#define GET_VOP2InfoTable_IMPL

Definition at line 335 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP3InfoTable_DECL

#define GET_VOP3InfoTable_DECL

Definition at line 336 of file AMDGPUBaseInfo.cpp.

◆ GET_VOP3InfoTable_IMPL

#define GET_VOP3InfoTable_IMPL

Definition at line 337 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPC64DPP8Table_DECL

#define GET_VOPC64DPP8Table_DECL

Definition at line 340 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPC64DPP8Table_IMPL

#define GET_VOPC64DPP8Table_IMPL

Definition at line 341 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPC64DPPTable_DECL

#define GET_VOPC64DPPTable_DECL

Definition at line 338 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPC64DPPTable_IMPL

#define GET_VOPC64DPPTable_IMPL

Definition at line 339 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPDComponentTable_DECL

#define GET_VOPDComponentTable_DECL

Definition at line 342 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPDComponentTable_IMPL

#define GET_VOPDComponentTable_IMPL

Definition at line 343 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPDPairs_DECL

#define GET_VOPDPairs_DECL

Definition at line 344 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPDPairs_IMPL

#define GET_VOPDPairs_IMPL

Definition at line 345 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPTrue16Table_DECL

#define GET_VOPTrue16Table_DECL

Definition at line 346 of file AMDGPUBaseInfo.cpp.

◆ GET_VOPTrue16Table_IMPL

#define GET_VOPTrue16Table_IMPL

Definition at line 347 of file AMDGPUBaseInfo.cpp.

◆ GET_WMMAOpcode2AddrMappingTable_DECL

#define GET_WMMAOpcode2AddrMappingTable_DECL

Definition at line 348 of file AMDGPUBaseInfo.cpp.

◆ GET_WMMAOpcode2AddrMappingTable_IMPL

#define GET_WMMAOpcode2AddrMappingTable_IMPL

Definition at line 349 of file AMDGPUBaseInfo.cpp.

◆ GET_WMMAOpcode3AddrMappingTable_DECL

#define GET_WMMAOpcode3AddrMappingTable_DECL

Definition at line 350 of file AMDGPUBaseInfo.cpp.

◆ GET_WMMAOpcode3AddrMappingTable_IMPL

#define GET_WMMAOpcode3AddrMappingTable_IMPL

Definition at line 351 of file AMDGPUBaseInfo.cpp.

◆ MAP_REG2REG

#define MAP_REG2REG

Definition at line 2068 of file AMDGPUBaseInfo.cpp.

Variable Documentation

◆ AmdhsaCodeObjectVersion

llvm::cl::opt< unsigned > AmdhsaCodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4)) ( "amdhsa-code-object-version"  ,
llvm::cl::Hidden  ,
llvm::cl::desc("AMDHSA Code Object Version")  ,
llvm::cl::init(4)   
)
static

Referenced by llvm::AMDGPU::getAmdhsaCodeObjectVersion(), and llvm::AMDGPU::getHsaAbiVersion().

◆ Intr

unsigned Intr

Definition at line 2609 of file AMDGPUBaseInfo.cpp.

Referenced by emitIntrinsicWithCC(), emitIntrinsicWithCCAndChain(), getBundleFromUse(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AMDGPULegalizerInfo::legalizeImageIntrinsic(), packImage16bitOpsToDwords(), llvm::PPCTargetLowering::PerformDAGCombine(), requireAssignType(), llvm::salvageKnowledge(), llvm::AMDGPUInstructionSelector::select(), simplifyInvariantGroupIntrinsic(), and llvm::UpgradeIntrinsicCall().

Generated on Thu Jun 8 2023 04:33:18 for LLVM by doxygen 1.9.6