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15 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
16 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
26 class MCObjectTargetWriter;
28 class MCSubtargetInfo;
29 class MCTargetOptions;
39 const MCSubtargetInfo &STI,
40 const MCRegisterInfo &
MRI,
41 const MCTargetOptions &
Options);
43 std::unique_ptr<MCObjectTargetWriter>
45 bool HasRelocationAddend, uint8_t ABIVersion);
48 #define GET_REGINFO_ENUM
49 #include "AMDGPUGenRegisterInfo.inc"
51 #define GET_INSTRINFO_ENUM
52 #define GET_INSTRINFO_OPERAND_ENUM
53 #include "AMDGPUGenInstrInfo.inc"
55 #define GET_SUBTARGETINFO_ENUM
56 #include "AMDGPUGenSubtargetInfo.inc"
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
This is an optimization pass for GlobalISel generic memory operations.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
unsigned const MachineRegisterInfo * MRI
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion)
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)