LLVM 17.0.0git
AMDGPUMCTargetDesc.h
Go to the documentation of this file.
1//===-- AMDGPUMCTargetDesc.h - AMDGPU Target Descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Provides AMDGPU specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
16#define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H
17
18#include <memory>
19
20namespace llvm {
21class Target;
22class MCAsmBackend;
23class MCCodeEmitter;
24class MCContext;
25class MCInstrInfo;
26class MCObjectTargetWriter;
27class MCRegisterInfo;
28class MCSubtargetInfo;
29class MCTargetOptions;
30
31enum AMDGPUDwarfFlavour : unsigned { Wave64 = 0, Wave32 = 1 };
32
33MCRegisterInfo *createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour);
34
35MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
36 MCContext &Ctx);
37
38MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
39 const MCSubtargetInfo &STI,
40 const MCRegisterInfo &MRI,
41 const MCTargetOptions &Options);
42
43std::unique_ptr<MCObjectTargetWriter>
44createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
45 bool HasRelocationAddend, uint8_t ABIVersion);
46} // End llvm namespace
47
48#define GET_REGINFO_ENUM
49#include "AMDGPUGenRegisterInfo.inc"
50
51#define GET_INSTRINFO_ENUM
52#define GET_INSTRINFO_OPERAND_ENUM
53#define GET_INSTRINFO_MC_HELPER_DECLS
54#include "AMDGPUGenInstrInfo.inc"
55
56#define GET_SUBTARGETINFO_ENUM
57#include "AMDGPUGenSubtargetInfo.inc"
58
59#endif
unsigned const MachineRegisterInfo * MRI
static LVOptions Options
Definition: LVOptions.cpp:25
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion)
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)