LLVM 17.0.0git
AMDGPUMCTargetDesc.cpp
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1//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file provides AMDGPU specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPUMCTargetDesc.h"
15#include "AMDGPUELFStreamer.h"
16#include "AMDGPUInstPrinter.h"
17#include "AMDGPUMCAsmInfo.h"
19#include "R600InstPrinter.h"
20#include "R600MCTargetDesc.h"
22#include "llvm/MC/LaneBitmask.h"
28#include "llvm/MC/MCInstrDesc.h"
29#include "llvm/MC/MCInstrInfo.h"
32#include "llvm/MC/MCStreamer.h"
35
36using namespace llvm;
37
38#define GET_INSTRINFO_MC_DESC
39#define ENABLE_INSTR_PREDICATE_VERIFIER
40#include "AMDGPUGenInstrInfo.inc"
41
42#define GET_SUBTARGETINFO_MC_DESC
43#include "AMDGPUGenSubtargetInfo.inc"
44
45#define NoSchedModel NoSchedModelR600
46#define GET_SUBTARGETINFO_MC_DESC
47#include "R600GenSubtargetInfo.inc"
48#undef NoSchedModelR600
49
50#define GET_REGINFO_MC_DESC
51#include "AMDGPUGenRegisterInfo.inc"
52
53#define GET_REGINFO_MC_DESC
54#include "R600GenRegisterInfo.inc"
55
57 MCInstrInfo *X = new MCInstrInfo();
58 InitAMDGPUMCInstrInfo(X);
59 return X;
60}
61
64 if (TT.getArch() == Triple::r600)
65 InitR600MCRegisterInfo(X, 0);
66 else
67 InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG);
68 return X;
69}
70
73 InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG, DwarfFlavour);
74 return X;
75}
76
77static MCSubtargetInfo *
79 if (TT.getArch() == Triple::r600)
80 return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
81 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
82}
83
85 unsigned SyntaxVariant,
86 const MCAsmInfo &MAI,
87 const MCInstrInfo &MII,
88 const MCRegisterInfo &MRI) {
89 if (T.getArch() == Triple::r600)
90 return new R600InstPrinter(MAI, MII, MRI);
91 else
92 return new AMDGPUInstPrinter(MAI, MII, MRI);
93}
94
97 MCInstPrinter *InstPrint,
98 bool isVerboseAsm) {
99 return new AMDGPUTargetAsmStreamer(S, OS);
100}
101
103 MCStreamer &S,
104 const MCSubtargetInfo &STI) {
105 return new AMDGPUTargetELFStreamer(S, STI);
106}
107
109 return new AMDGPUTargetStreamer(S);
110}
111
113 std::unique_ptr<MCAsmBackend> &&MAB,
114 std::unique_ptr<MCObjectWriter> &&OW,
115 std::unique_ptr<MCCodeEmitter> &&Emitter,
116 bool RelaxAll) {
117 return createAMDGPUELFStreamer(T, Context, std::move(MAB), std::move(OW),
118 std::move(Emitter), RelaxAll);
119}
120
121namespace {
122
123class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
124public:
125 explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
127
128 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
129 uint64_t &Target) const override {
130 if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
131 Info->get(Inst.getOpcode()).operands()[0].OperandType !=
133 return false;
134
135 int64_t Imm = Inst.getOperand(0).getImm();
136 // Our branches take a simm16, but we need two extra bits to account for
137 // the factor of 4.
138 APInt SignedOffset(18, Imm * 4, true);
139 Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue();
140 return true;
141 }
142};
143
144} // end anonymous namespace
145
147 return new AMDGPUMCInstrAnalysis(Info);
148}
149
151
154 for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
156
163 }
164
165 // R600 specific registration
170
171 // GCN specific registration
174
181}
unsigned const MachineRegisterInfo * MRI
static MCInstrInfo * createAMDGPUMCInstrInfo()
static MCStreamer * createMCStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
static MCSubtargetInfo * createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
static MCInstrAnalysis * createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
static MCTargetStreamer * createAMDGPUNullTargetStreamer(MCStreamer &S)
static MCTargetStreamer * createAMDGPUObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
static MCInstPrinter * createAMDGPUMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static MCRegisterInfo * createAMDGPUMCRegisterInfo(const Triple &TT)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC()
static MCTargetStreamer * createAMDGPUAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Provides AMDGPU specific target descriptions.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
dxil DXContainer Global Emitter
uint64_t Addr
uint64_t Size
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
A common definition of LaneBitmask for use in TableGen and CodeGen.
LLVMContext & Context
Provides R600 specific target descriptions.
Class for arbitrary precision integers.
Definition: APInt.h:75
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
Context object for machine code objects.
Definition: MCContext.h:76
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:44
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
virtual bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, uint64_t &Target) const
Given a branch instruction try to get the address the branch targets.
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
int64_t getImm() const
Definition: MCInst.h:80
bool isImm() const
Definition: MCInst.h:62
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Streaming machine code generation interface.
Definition: MCStreamer.h:212
Generic base class for all target subtargets.
Target specific streamer interface.
Definition: MCStreamer.h:93
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Target & getTheGCNTarget()
The target for GCN GPUs.
MCELFStreamer * createAMDGPUELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
MCInstrInfo * createR600MCInstrInfo()
RegisterMCAsmInfo - Helper template for registering a target assembly info implementation.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
static void RegisterNullTargetStreamer(Target &T, Target::NullTargetStreamerCtorTy Fn)
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)