LLVM  15.0.0git
AMDGPUMCTargetDesc.cpp
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1 //===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file provides AMDGPU specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AMDGPUMCTargetDesc.h"
15 #include "AMDGPUELFStreamer.h"
16 #include "AMDGPUInstPrinter.h"
17 #include "AMDGPUMCAsmInfo.h"
18 #include "AMDGPUTargetStreamer.h"
19 #include "R600InstPrinter.h"
20 #include "R600MCTargetDesc.h"
22 #include "llvm/MC/LaneBitmask.h"
23 #include "llvm/MC/MCAsmBackend.h"
24 #include "llvm/MC/MCCodeEmitter.h"
25 #include "llvm/MC/MCELFStreamer.h"
26 #include "llvm/MC/MCInstPrinter.h"
28 #include "llvm/MC/MCInstrDesc.h"
29 #include "llvm/MC/MCInstrInfo.h"
30 #include "llvm/MC/MCObjectWriter.h"
31 #include "llvm/MC/MCRegisterInfo.h"
32 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/MC/TargetRegistry.h"
35 
36 using namespace llvm;
37 
38 #define GET_INSTRINFO_MC_DESC
39 #include "AMDGPUGenInstrInfo.inc"
40 
41 #define GET_SUBTARGETINFO_MC_DESC
42 #include "AMDGPUGenSubtargetInfo.inc"
43 
44 #define NoSchedModel NoSchedModelR600
45 #define GET_SUBTARGETINFO_MC_DESC
46 #include "R600GenSubtargetInfo.inc"
47 #undef NoSchedModelR600
48 
49 #define GET_REGINFO_MC_DESC
50 #include "AMDGPUGenRegisterInfo.inc"
51 
52 #define GET_REGINFO_MC_DESC
53 #include "R600GenRegisterInfo.inc"
54 
56  MCInstrInfo *X = new MCInstrInfo();
57  InitAMDGPUMCInstrInfo(X);
58  return X;
59 }
60 
63  if (TT.getArch() == Triple::r600)
64  InitR600MCRegisterInfo(X, 0);
65  else
66  InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG);
67  return X;
68 }
69 
72  InitAMDGPUMCRegisterInfo(X, AMDGPU::PC_REG, DwarfFlavour);
73  return X;
74 }
75 
76 static MCSubtargetInfo *
78  if (TT.getArch() == Triple::r600)
79  return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
80  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
81 }
82 
84  unsigned SyntaxVariant,
85  const MCAsmInfo &MAI,
86  const MCInstrInfo &MII,
87  const MCRegisterInfo &MRI) {
88  if (T.getArch() == Triple::r600)
89  return new R600InstPrinter(MAI, MII, MRI);
90  else
91  return new AMDGPUInstPrinter(MAI, MII, MRI);
92 }
93 
96  MCInstPrinter *InstPrint,
97  bool isVerboseAsm) {
98  return new AMDGPUTargetAsmStreamer(S, OS);
99 }
100 
102  MCStreamer &S,
103  const MCSubtargetInfo &STI) {
104  return new AMDGPUTargetELFStreamer(S, STI);
105 }
106 
108  std::unique_ptr<MCAsmBackend> &&MAB,
109  std::unique_ptr<MCObjectWriter> &&OW,
110  std::unique_ptr<MCCodeEmitter> &&Emitter,
111  bool RelaxAll) {
113  std::move(Emitter), RelaxAll);
114 }
115 
116 namespace {
117 
118 class AMDGPUMCInstrAnalysis : public MCInstrAnalysis {
119 public:
120  explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
121  : MCInstrAnalysis(Info) {}
122 
123  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
124  uint64_t &Target) const override {
125  if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() ||
126  Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
128  return false;
129 
130  int64_t Imm = Inst.getOperand(0).getImm();
131  // Our branches take a simm16, but we need two extra bits to account for
132  // the factor of 4.
133  APInt SignedOffset(18, Imm * 4, true);
134  Target = (SignedOffset.sext(64) + Addr + Size).getZExtValue();
135  return true;
136  }
137 };
138 
139 } // end anonymous namespace
140 
142  return new AMDGPUMCInstrAnalysis(Info);
143 }
144 
146 
149  for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
151 
158  }
159 
160  // R600 specific registration
165 
166  // GCN specific registration
169 
174 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:76
llvm::createSIMCCodeEmitter
MCCodeEmitter * createSIMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: SIMCCodeEmitter.cpp:83
AMDGPUELFStreamer.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
MCInstrDesc.h
T
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:74
MCCodeEmitter.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:140
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
createAMDGPUAsmTargetStreamer
static MCTargetStreamer * createAMDGPUAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
Definition: AMDGPUMCTargetDesc.cpp:94
llvm::createAMDGPUELFStreamer
MCELFStreamer * createAMDGPUELFStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
Definition: AMDGPUELFStreamer.cpp:31
llvm::TargetRegistry::RegisterAsmTargetStreamer
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:993
llvm::TargetRegistry::RegisterMCInstrAnalysis
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target.
Definition: TargetRegistry.h:840
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
createAMDGPUObjectTargetStreamer
static MCTargetStreamer * createAMDGPUObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
Definition: AMDGPUMCTargetDesc.cpp:101
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::TargetRegistry::RegisterMCInstPrinter
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
Definition: TargetRegistry.h:947
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
MCELFStreamer.h
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MCStreamer
Streaming machine code generation interface.
Definition: MCStreamer.h:201
llvm::createR600MCInstrInfo
MCInstrInfo * createR600MCInstrInfo()
Definition: R600MCTargetDesc.cpp:22
llvm::AMDGPUInstPrinter
Definition: AMDGPUInstPrinter.h:19
MCAsmBackend.h
llvm::getTheAMDGPUTarget
Target & getTheAMDGPUTarget()
The target which supports all AMD GPUs.
Definition: AMDGPUTargetInfo.cpp:20
AMDGPUTargetInfo.h
MCInstrInfo.h
llvm::MCOperand::getImm
int64_t getImm() const
Definition: MCInst.h:80
llvm::MCInstrAnalysis
Definition: MCInstrAnalysis.h:30
MCSubtargetInfo.h
createMCStreamer
static MCStreamer * createMCStreamer(const Triple &T, MCContext &Context, std::unique_ptr< MCAsmBackend > &&MAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll)
Definition: AMDGPUMCTargetDesc.cpp:107
llvm::Triple::r600
@ r600
Definition: Triple.h:73
createAMDGPUMCInstrAnalysis
static MCInstrAnalysis * createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info)
Definition: AMDGPUMCTargetDesc.cpp:141
llvm::MCTargetStreamer
Target specific streamer interface.
Definition: MCStreamer.h:93
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MCOI::OPERAND_PCREL
@ OPERAND_PCREL
Definition: MCInstrDesc.h:62
R600InstPrinter.h
MCInstPrinter.h
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
R600MCTargetDesc.h
llvm::AMDGPUDwarfFlavour
AMDGPUDwarfFlavour
Definition: AMDGPUMCTargetDesc.h:31
llvm::MCOperand::isImm
bool isImm() const
Definition: MCInst.h:62
AMDGPUMCTargetDesc.h
llvm::TargetRegistry::RegisterMCAsmBackend
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Definition: TargetRegistry.h:894
AMDGPUTargetStreamer.h
uint64_t
llvm::MCInstPrinter
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:43
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::TargetRegistry::RegisterObjectTargetStreamer
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Definition: TargetRegistry.h:999
MCRegisterInfo.h
AMDGPUInstPrinter.h
llvm::formatted_raw_ostream
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
Definition: FormattedStream.h:30
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::TargetRegistry::RegisterMCSubtargetInfo
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target.
Definition: TargetRegistry.h:867
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::createR600MCCodeEmitter
MCCodeEmitter * createR600MCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
Definition: R600MCCodeEmitter.cpp:87
LLVMInitializeAMDGPUTargetMC
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTargetMC()
Definition: AMDGPUMCTargetDesc.cpp:145
MCInstrAnalysis.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::RegisterMCAsmInfo
RegisterMCAsmInfo - Helper template for registering a target assembly info implementation.
Definition: TargetRegistry.h:1098
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
AMDGPUMCAsmInfo.h
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPUTargetAsmStreamer
Definition: AMDGPUTargetStreamer.h:115
MCObjectWriter.h
llvm::TargetRegistry::RegisterMCInstrInfo
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target.
Definition: TargetRegistry.h:834
llvm::TargetRegistry::RegisterMCCodeEmitter
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
Definition: TargetRegistry.h:960
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::TargetRegistry::RegisterMCRegInfo
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Definition: TargetRegistry.h:854
llvm::TargetRegistry::RegisterELFStreamer
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
Definition: TargetRegistry.h:972
createAMDGPUMCRegisterInfo
static MCRegisterInfo * createAMDGPUMCRegisterInfo(const Triple &TT)
Definition: AMDGPUMCTargetDesc.cpp:61
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::R600InstPrinter
Definition: R600InstPrinter.h:16
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
MCStreamer.h
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::AMDGPUTargetELFStreamer
Definition: AMDGPUTargetStreamer.h:155
createAMDGPUMCInstPrinter
static MCInstPrinter * createAMDGPUMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
Definition: AMDGPUMCTargetDesc.cpp:83
LaneBitmask.h
createAMDGPUMCSubtargetInfo
static MCSubtargetInfo * createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
Definition: AMDGPUMCTargetDesc.cpp:77
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::createGCNMCRegisterInfo
MCRegisterInfo * createGCNMCRegisterInfo(AMDGPUDwarfFlavour DwarfFlavour)
Definition: AMDGPUMCTargetDesc.cpp:70
createAMDGPUMCInstrInfo
static MCInstrInfo * createAMDGPUMCInstrInfo()
Definition: AMDGPUMCTargetDesc.cpp:55
llvm::createAMDGPUAsmBackend
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AMDGPUAsmBackend.cpp:237