36 uint64_t
Value,
bool IsResolved,
38 bool fixupNeedsRelaxation(
const MCFixup &Fixup, uint64_t
Value,
43 MCInst &Res)
const override;
45 bool mayNeedRelaxation(
const MCInst &Inst,
48 unsigned getMinimumNopSize()
const override;
49 bool writeNopData(
raw_ostream &OS, uint64_t Count)
const override;
56 void AMDGPUAsmBackend::relaxInstruction(
const MCInst &Inst,
65 bool AMDGPUAsmBackend::fixupNeedsRelaxation(
const MCFixup &Fixup,
72 return (((int64_t(Value)/4)-1) == 0x3f);
75 bool AMDGPUAsmBackend::mayNeedRelaxation(
const MCInst &Inst,
110 int64_t SignedValue =
static_cast<int64_t
>(
Value);
114 int64_t BrImm = (SignedValue - 4) / 4;
149 assert(Offset + NumBytes <= Data.
size() &&
"Invalid fixup offset!");
153 for (
unsigned i = 0; i != NumBytes; ++i)
154 Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
170 unsigned AMDGPUAsmBackend::getMinimumNopSize()
const {
174 bool AMDGPUAsmBackend::writeNopData(
raw_ostream &OS, uint64_t Count)
const {
185 const uint32_t Encoded_S_NOP_0 = 0xbf800000;
187 for (uint64_t
I = 0;
I != Count; ++
I)
188 support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian);
199 class ELFAMDGPUAsmBackend :
public AMDGPUAsmBackend {
201 bool HasRelocationAddend;
203 uint8_t ABIVersion = 0;
206 ELFAMDGPUAsmBackend(
const Target &
T,
const Triple &
TT, uint8_t ABIVersion) :
209 ABIVersion(ABIVersion) {
210 switch (TT.
getOS()) {
225 std::unique_ptr<MCObjectTargetWriter>
226 createObjectTargetWriter()
const override {
This class represents lattice values for constants.
This represents an "assembler immediate".
OSType getOS() const
getOS - Get the parsed operating system type of this triple.
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
constexpr bool isInt< 16 >(int64_t x)
unsigned TargetOffset
The bit offset to write the relocation into.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
const Triple & getTargetTriple() const
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
MCContext & getContext() const
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion)
const FeatureBitset & getFeatureBits() const
Encapsulates the layout of an assembly file at a particular point in time.
A four-byte section relative fixup.
bool hasCodeObjectV3(const MCSubtargetInfo *STI)
Context object for machine code objects.
A two-byte section relative fixup.
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Analysis containing CSE Info
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
unsigned const MachineRegisterInfo * MRI
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
size_t size() const
size - Get the array size.
MCFixupKind
Extensible enumeration to represent the type of a fixup.
void reportError(SMLoc L, const Twine &Msg)
uint32_t getOffset() const
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
void setOpcode(unsigned Op)
A four-byte pc relative fixup.
const MCOperand & getOperand(unsigned i) const
Target - Wrapper for Target specific information.
A one-byte section relative fixup.
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
Provides AMDGPU specific target descriptions.
static unsigned getFixupKindNumBytes(unsigned Kind)
A eight-byte section relative fixup.
16-bit PC relative fixup for SOPP branch instructions.
Generic base class for all target subtargets.
Target independent information on a fixup kind.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Generic interface to target specific assembler backends.
unsigned getTargetKind() const
This class implements an extremely fast bulk output stream that can only output to a stream...
void addOperand(const MCOperand &Op)
unsigned getOpcode() const
MCFixupKind getKind() const