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43 void relaxInstruction(
MCInst &Inst,
46 bool mayNeedRelaxation(
const MCInst &Inst,
49 unsigned getMinimumNopSize()
const override;
53 std::optional<MCFixupKind> getFixupKind(
StringRef Name)
const override;
61 void AMDGPUAsmBackend::relaxInstruction(
MCInst &Inst,
70 bool AMDGPUAsmBackend::fixupNeedsRelaxation(
const MCFixup &Fixup,
77 return (((int64_t(
Value)/4)-1) == 0x3f);
80 bool AMDGPUAsmBackend::mayNeedRelaxation(
const MCInst &Inst,
115 int64_t SignedValue =
static_cast<int64_t
>(
Value);
117 switch (
Fixup.getTargetKind()) {
119 int64_t BrImm = (SignedValue - 4) / 4;
121 if (Ctx && !isInt<16>(BrImm))
157 assert(Offset + NumBytes <=
Data.size() &&
"Invalid fixup offset!");
161 for (
unsigned i = 0;
i != NumBytes; ++
i)
162 Data[Offset +
i] |=
static_cast<uint8_t
>((
Value >> (
i * 8)) & 0xff);
165 std::optional<MCFixupKind>
166 AMDGPUAsmBackend::getFixupKind(
StringRef Name)
const {
170 #
include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
191 bool AMDGPUAsmBackend::shouldForceRelocation(
const MCAssembler &,
197 unsigned AMDGPUAsmBackend::getMinimumNopSize()
const {
213 const uint32_t Encoded_S_NOP_0 = 0xbf800000;
216 support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian);
227 class ELFAMDGPUAsmBackend :
public AMDGPUAsmBackend {
229 bool HasRelocationAddend;
231 uint8_t ABIVersion = 0;
234 ELFAMDGPUAsmBackend(
const Target &
T,
const Triple &TT, uint8_t ABIVersion) :
235 AMDGPUAsmBackend(
T), Is64Bit(
TT.getArch() ==
Triple::amdgcn),
236 HasRelocationAddend(
TT.getOS() ==
Triple::AMDHSA),
237 ABIVersion(ABIVersion) {
238 switch (
TT.getOS()) {
253 std::unique_ptr<MCObjectTargetWriter>
254 createObjectTargetWriter()
const override {
This is an optimization pass for GlobalISel generic memory operations.
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
#define ELF_RELOC(Name, Value)
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
Context object for machine code objects.
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
Instances of this class represent a single low-level machine instruction.
Error applyFixup(LinkGraph &G, Block &B, const Edge &E)
Apply fixup expression for edge to block content.
void setOpcode(unsigned Op)
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
@ FK_Data_4
A four-byte fixup.
Generic interface to target specific assembler backends.
@ FK_SecRel_4
A four-byte section relative fixup.
const Triple & getTargetTriple() const
static unsigned getFixupKindNumBytes(unsigned Kind)
@ FK_SecRel_2
A two-byte section relative fixup.
const FeatureBitset & getFeatureBits() const
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRPrinter) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(DWARFLinkerParallel) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(ObjCopy) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(Debuginfod) add_subdirectory(DebugInfo) add_subdirectory(DWP) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TargetParser) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsDriver) add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
This class implements an extremely fast bulk output stream that can only output to a stream.
Analysis containing CSE Info
std::optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
void addOperand(const MCOperand Op)
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target independent information on a fixup kind.
void reportError(SMLoc L, const Twine &Msg)
@ FK_Data_1
A one-byte fixup.
@ FK_PCRel_4
A four-byte pc relative fixup.
PowerPC TLS Dynamic Call Fixup
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
@ FK_SecRel_1
A one-byte section relative fixup.
unsigned const MachineRegisterInfo * MRI
Encapsulates the layout of an assembly file at a particular point in time.
@ FK_SecRel_8
A eight-byte section relative fixup.
unsigned getOpcode() const
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_Data_8
A eight-byte fixup.
const MCOperand & getOperand(unsigned i) const
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
A switch()-like statement whose cases are string literals.
This represents an "assembler immediate".
@ FK_Data_2
A two-byte fixup.
Generic base class for all target subtargets.
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
LLVM Value Representation.
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion)
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)