LLVM  15.0.0git
AMDGPUAsmBackend.cpp
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1 //===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
12 #include "Utils/AMDGPUBaseInfo.h"
13 #include "llvm/BinaryFormat/ELF.h"
14 #include "llvm/MC/MCAsmBackend.h"
15 #include "llvm/MC/MCAssembler.h"
16 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCObjectWriter.h"
20 #include "llvm/MC/TargetRegistry.h"
23 
24 using namespace llvm;
25 using namespace llvm::AMDGPU;
26 
27 namespace {
28 
29 class AMDGPUAsmBackend : public MCAsmBackend {
30 public:
31  AMDGPUAsmBackend(const Target &T) : MCAsmBackend(support::little) {}
32 
33  unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
34 
35  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
37  uint64_t Value, bool IsResolved,
38  const MCSubtargetInfo *STI) const override;
39  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
40  const MCRelaxableFragment *DF,
41  const MCAsmLayout &Layout) const override;
42 
43  void relaxInstruction(MCInst &Inst,
44  const MCSubtargetInfo &STI) const override;
45 
46  bool mayNeedRelaxation(const MCInst &Inst,
47  const MCSubtargetInfo &STI) const override;
48 
49  unsigned getMinimumNopSize() const override;
50  bool writeNopData(raw_ostream &OS, uint64_t Count,
51  const MCSubtargetInfo *STI) const override;
52 
53  Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
54  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
55  bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
56  const MCValue &Target) override;
57 };
58 
59 } //End anonymous namespace
60 
61 void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst,
62  const MCSubtargetInfo &STI) const {
63  MCInst Res;
64  unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode());
65  Res.setOpcode(RelaxedOpcode);
66  Res.addOperand(Inst.getOperand(0));
67  Inst = std::move(Res);
68 }
69 
70 bool AMDGPUAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
72  const MCRelaxableFragment *DF,
73  const MCAsmLayout &Layout) const {
74  // if the branch target has an offset of x3f this needs to be relaxed to
75  // add a s_nop 0 immediately after branch to effectively increment offset
76  // for hardware workaround in gfx1010
77  return (((int64_t(Value)/4)-1) == 0x3f);
78 }
79 
80 bool AMDGPUAsmBackend::mayNeedRelaxation(const MCInst &Inst,
81  const MCSubtargetInfo &STI) const {
82  if (!STI.getFeatureBits()[AMDGPU::FeatureOffset3fBug])
83  return false;
84 
86  return true;
87 
88  return false;
89 }
90 
91 static unsigned getFixupKindNumBytes(unsigned Kind) {
92  switch (Kind) {
94  return 2;
95  case FK_SecRel_1:
96  case FK_Data_1:
97  return 1;
98  case FK_SecRel_2:
99  case FK_Data_2:
100  return 2;
101  case FK_SecRel_4:
102  case FK_Data_4:
103  case FK_PCRel_4:
104  return 4;
105  case FK_SecRel_8:
106  case FK_Data_8:
107  return 8;
108  default:
109  llvm_unreachable("Unknown fixup kind!");
110  }
111 }
112 
114  MCContext *Ctx) {
115  int64_t SignedValue = static_cast<int64_t>(Value);
116 
117  switch (Fixup.getTargetKind()) {
119  int64_t BrImm = (SignedValue - 4) / 4;
120 
121  if (Ctx && !isInt<16>(BrImm))
122  Ctx->reportError(Fixup.getLoc(), "branch size exceeds simm16");
123 
124  return BrImm;
125  }
126  case FK_Data_1:
127  case FK_Data_2:
128  case FK_Data_4:
129  case FK_Data_8:
130  case FK_PCRel_4:
131  case FK_SecRel_4:
132  return Value;
133  default:
134  llvm_unreachable("unhandled fixup kind");
135  }
136 }
137 
138 void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
139  const MCValue &Target,
141  bool IsResolved,
142  const MCSubtargetInfo *STI) const {
143  if (Fixup.getKind() >= FirstLiteralRelocationKind)
144  return;
145 
146  Value = adjustFixupValue(Fixup, Value, &Asm.getContext());
147  if (!Value)
148  return; // Doesn't change encoding.
149 
150  MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
151 
152  // Shift the value into position.
153  Value <<= Info.TargetOffset;
154 
155  unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
156  uint32_t Offset = Fixup.getOffset();
157  assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
158 
159  // For each byte of the fragment that the fixup touches, mask in the bits from
160  // the fixup value.
161  for (unsigned i = 0; i != NumBytes; ++i)
162  Data[Offset + i] |= static_cast<uint8_t>((Value >> (i * 8)) & 0xff);
163 }
164 
165 Optional<MCFixupKind> AMDGPUAsmBackend::getFixupKind(StringRef Name) const {
167 #define ELF_RELOC(Name, Value) \
169 #include "llvm/BinaryFormat/ELFRelocs/AMDGPU.def"
170 #undef ELF_RELOC
171  .Default(None);
172 }
173 
174 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo(
175  MCFixupKind Kind) const {
176  const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = {
177  // name offset bits flags
178  { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
179  };
180 
183 
186 
187  return Infos[Kind - FirstTargetFixupKind];
188 }
189 
190 bool AMDGPUAsmBackend::shouldForceRelocation(const MCAssembler &,
191  const MCFixup &Fixup,
192  const MCValue &) {
193  return Fixup.getKind() >= FirstLiteralRelocationKind;
194 }
195 
196 unsigned AMDGPUAsmBackend::getMinimumNopSize() const {
197  return 4;
198 }
199 
200 bool AMDGPUAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
201  const MCSubtargetInfo *STI) const {
202  // If the count is not 4-byte aligned, we must be writing data into the text
203  // section (otherwise we have unaligned instructions, and thus have far
204  // bigger problems), so just write zeros instead.
205  OS.write_zeros(Count % 4);
206 
207  // We are properly aligned, so write NOPs as requested.
208  Count /= 4;
209 
210  // FIXME: R600 support.
211  // s_nop 0
212  const uint32_t Encoded_S_NOP_0 = 0xbf800000;
213 
214  for (uint64_t I = 0; I != Count; ++I)
215  support::endian::write<uint32_t>(OS, Encoded_S_NOP_0, Endian);
216 
217  return true;
218 }
219 
220 //===----------------------------------------------------------------------===//
221 // ELFAMDGPUAsmBackend class
222 //===----------------------------------------------------------------------===//
223 
224 namespace {
225 
226 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend {
227  bool Is64Bit;
228  bool HasRelocationAddend;
229  uint8_t OSABI = ELF::ELFOSABI_NONE;
230  uint8_t ABIVersion = 0;
231 
232 public:
233  ELFAMDGPUAsmBackend(const Target &T, const Triple &TT, uint8_t ABIVersion) :
234  AMDGPUAsmBackend(T), Is64Bit(TT.getArch() == Triple::amdgcn),
235  HasRelocationAddend(TT.getOS() == Triple::AMDHSA),
236  ABIVersion(ABIVersion) {
237  switch (TT.getOS()) {
238  case Triple::AMDHSA:
239  OSABI = ELF::ELFOSABI_AMDGPU_HSA;
240  break;
241  case Triple::AMDPAL:
242  OSABI = ELF::ELFOSABI_AMDGPU_PAL;
243  break;
244  case Triple::Mesa3D:
246  break;
247  default:
248  break;
249  }
250  }
251 
252  std::unique_ptr<MCObjectTargetWriter>
253  createObjectTargetWriter() const override {
254  return createAMDGPUELFObjectWriter(Is64Bit, OSABI, HasRelocationAddend,
255  ABIVersion);
256  }
257 };
258 
259 } // end anonymous namespace
260 
262  const MCSubtargetInfo &STI,
263  const MCRegisterInfo &MRI,
264  const MCTargetOptions &Options) {
265  return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(),
266  getHsaAbiVersion(&STI).value_or(0));
267 }
i
i
Definition: README.txt:29
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::MCRelaxableFragment
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:270
AMDGPUFixupKinds.h
llvm::ELF::ELFOSABI_AMDGPU_PAL
@ ELFOSABI_AMDGPU_PAL
Definition: ELF.h:361
llvm::ARM::PredBlockMask::TT
@ TT
llvm::MCAsmBackend::getFixupKindInfo
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
Definition: MCAsmBackend.cpp:82
ELF_RELOC
#define ELF_RELOC(Name, Value)
T
llvm::raw_ostream::write_zeros
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
Definition: raw_ostream.cpp:501
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::AMDGPU::fixup_si_sopp_br
@ fixup_si_sopp_br
16-bit PC relative fixup for SOPP branch instructions.
Definition: AMDGPUFixupKinds.h:18
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::ELF::ELFOSABI_AMDGPU_MESA3D
@ ELFOSABI_AMDGPU_MESA3D
Definition: ELF.h:362
llvm::FirstTargetFixupKind
@ FirstTargetFixupKind
Definition: MCFixup.h:45
llvm::AMDGPU::getHsaAbiVersion
Optional< uint8_t > getHsaAbiVersion(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:105
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCAssembler.h
llvm::Optional
Definition: APInt.h:33
MCFixupKindInfo.h
adjustFixupValue
static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value, MCContext *Ctx)
Definition: AMDGPUAsmBackend.cpp:113
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
TargetParser.h
llvm::Data
@ Data
Definition: SIMachineScheduler.h:55
llvm::MCInst::setOpcode
void setOpcode(unsigned Op)
Definition: MCInst.h:197
include
include(LLVM-Build) add_subdirectory(IR) add_subdirectory(FuzzMutate) add_subdirectory(FileCheck) add_subdirectory(InterfaceStub) add_subdirectory(IRReader) add_subdirectory(CodeGen) add_subdirectory(BinaryFormat) add_subdirectory(Bitcode) add_subdirectory(Bitstream) add_subdirectory(DWARFLinker) add_subdirectory(Extensions) add_subdirectory(Frontend) add_subdirectory(Transforms) add_subdirectory(Linker) add_subdirectory(Analysis) add_subdirectory(LTO) add_subdirectory(MC) add_subdirectory(MCA) add_subdirectory(ObjCopy) add_subdirectory(Object) add_subdirectory(ObjectYAML) add_subdirectory(Option) add_subdirectory(Remarks) add_subdirectory(Debuginfod) add_subdirectory(DebugInfo) add_subdirectory(DWP) add_subdirectory(ExecutionEngine) add_subdirectory(Target) add_subdirectory(AsmParser) add_subdirectory(LineEditor) add_subdirectory(ProfileData) add_subdirectory(Passes) add_subdirectory(TextAPI) add_subdirectory(ToolDrivers) add_subdirectory(XRay) if(LLVM_INCLUDE_TESTS) add_subdirectory(Testing) endif() add_subdirectory(WindowsDriver) add_subdirectory(WindowsManifest) set(LLVMCONFIGLIBRARYDEPENDENCIESINC "$
Definition: CMakeLists.txt:1
llvm::FirstLiteralRelocationKind
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
Definition: MCFixup.h:50
llvm::AMDGPU::getSOPPWithRelaxation
LLVM_READONLY int getSOPPWithRelaxation(uint16_t Opcode)
llvm::FK_Data_4
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
llvm::ELF::ELFOSABI_NONE
@ ELFOSABI_NONE
Definition: ELF.h:341
llvm::MCAsmBackend
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:42
ELF.h
MCAsmBackend.h
llvm::MutableArrayRef< char >
llvm::FK_SecRel_4
@ FK_SecRel_4
A four-byte section relative fixup.
Definition: MCFixup.h:42
llvm::support::little
@ little
Definition: Endian.h:27
llvm::Triple::Mesa3D
@ Mesa3D
Definition: Triple.h:214
llvm::MCSubtargetInfo::getTargetTriple
const Triple & getTargetTriple() const
Definition: MCSubtargetInfo.h:108
getFixupKindNumBytes
static unsigned getFixupKindNumBytes(unsigned Kind)
Definition: AMDGPUAsmBackend.cpp:91
MCContext.h
llvm::FK_SecRel_2
@ FK_SecRel_2
A two-byte section relative fixup.
Definition: MCFixup.h:41
MCSubtargetInfo.h
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
llvm::AMDGPU
Definition: AMDGPUMetadataVerifier.h:34
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::ELF::ELFOSABI_AMDGPU_HSA
@ ELFOSABI_AMDGPU_HSA
Definition: ELF.h:360
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
DF
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::Triple::AMDHSA
@ AMDHSA
Definition: Triple.h:207
llvm::MCAssembler
Definition: MCAssembler.h:73
AMDGPUMCTargetDesc.h
llvm::AMDGPU::Hwreg::Offset
Offset
Definition: SIDefines.h:413
uint64_t
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCFixupKindInfo::FKF_IsPCRel
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...
Definition: MCFixupKindInfo.h:19
I
#define I(x, y, z)
Definition: MD5.cpp:58
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MCFixupKindInfo
Target independent information on a fixup kind.
Definition: MCFixupKindInfo.h:15
llvm::MCContext::reportError
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:1037
llvm::FK_Data_1
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
llvm::FK_PCRel_4
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
llvm::MCTargetOptions
Definition: MCTargetOptions.h:42
llvm::FK_NONE
@ FK_NONE
A no-op fixup.
Definition: MCFixup.h:22
Fixup
PowerPC TLS Dynamic Call Fixup
Definition: PPCTLSDynamicCall.cpp:233
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
uint32_t
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::FK_SecRel_1
@ FK_SecRel_1
A one-byte section relative fixup.
Definition: MCFixup.h:40
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::isInt< 16 >
constexpr bool isInt< 16 >(int64_t x)
Definition: MathExtras.h:370
MCObjectWriter.h
llvm::AMDGPU::NumTargetFixupKinds
@ NumTargetFixupKinds
Definition: AMDGPUFixupKinds.h:22
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
EndianStream.h
llvm::MCAsmLayout
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
llvm::FK_SecRel_8
@ FK_SecRel_8
A eight-byte section relative fixup.
Definition: MCFixup.h:43
llvm::Triple::AMDPAL
@ AMDPAL
Definition: Triple.h:216
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::TargetStackID::Default
@ Default
Definition: TargetFrameLowering.h:28
llvm::MCFixupKind
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
llvm::FK_Data_8
@ FK_Data_8
A eight-byte fixup.
Definition: MCFixup.h:26
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
support
Reimplement select in terms of SEL *We would really like to support but we need to prove that the add doesn t need to overflow between the two bit chunks *Implement pre post increment support(e.g. PR935) *Implement smarter const ant generation for binops with large immediates. A few ARMv6T2 ops should be pattern matched
Definition: README.txt:10
llvm::StringSwitch
A switch()-like statement whose cases are string literals.
Definition: StringSwitch.h:44
llvm::HexStyle::Asm
@ Asm
0ffh
Definition: MCInstPrinter.h:34
llvm::MCValue
This represents an "assembler immediate".
Definition: MCValue.h:36
llvm::FK_Data_2
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
TargetRegistry.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::MCFixup
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
AMDGPUBaseInfo.h
llvm::createAMDGPUELFObjectWriter
std::unique_ptr< MCObjectTargetWriter > createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion)
Definition: AMDGPUELFObjectWriter.cpp:98
llvm::createAMDGPUAsmBackend
MCAsmBackend * createAMDGPUAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Definition: AMDGPUAsmBackend.cpp:261