13#ifndef LLVM_EXECUTIONENGINE_JITLINK_AARCH32
14#define LLVM_EXECUTIONENGINE_JITLINK_AARCH32
139 dbgs() <<
" Warning: ARM config not defined for CPU architecture "
151 assert(isUInt<16>(
Hi) &&
"Overflow in first half-word");
152 assert(isUInt<16>(
Lo) &&
"Overflow in second half-word");
173 static constexpr uint32_t Unconditional = 0xe0000000;
228 const ArmConfig &ArmCfg);
255 const ArmConfig &ArmCfg);
282template <StubsFlavor Flavor>
292 if (
E.getTarget().isDefined())
295 switch (
E.getKind()) {
299 dbgs() <<
" Fixing " <<
G.getEdgeKindName(
E.getKind()) <<
" edge at "
300 <<
B->getFixupAddress(
E) <<
" (" <<
B->getAddress() <<
" + "
301 <<
formatv(
"{0:x}",
E.getOffset()) <<
")\n";
315 template <
size_t Size>
319 return G.createContentBlock(getStubsSection(
G),
Template,
328 return *StubsSection;
331 Section *StubsSection =
nullptr;
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define DEBUG_WITH_TYPE(TYPE, X)
DEBUG_WITH_TYPE macro - This macro should be used by passes to emit debug information.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Lightweight error class with error context and mandatory checking.
Tagged union holding either a T or a Error.
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
An Addressable with content and edges.
Represents fixups and constraints in the LinkGraph.
Represents an object file section.
A CRTP base for tables that are built on demand, e.g.
Symbol & getEntryForTarget(LinkGraph &G, Symbol &Target)
Return the constructed entry.
Stubs builder for a specific StubsFlavor.
static StringRef getSectionName()
Name of the object file section that will contain all our stubs.
Symbol & createEntry(LinkGraph &G, Symbol &Target)
Create a branch range extension stub for the class's flavor.
bool visitEdge(LinkGraph &G, Block *B, Edge &E)
Implements link-graph traversal via visitExistingEdges().
Represents an address in the executor process.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Expected< int64_t > readAddendThumb(LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)
Helper function to read the initial addend for Thumb-class relocations.
EdgeKind_aarch32
JITLink-internal AArch32 fixup kinds.
@ Arm_MovtAbs
Write immediate value to the top halfword of the destination register.
@ Data_Pointer32
Absolute 32-bit value relocation.
@ FirstThumbRelocation
Relocations of class Thumb16 and Thumb32 (covers Thumb instruction subset)
@ Arm_MovwAbsNC
Write immediate value to the lower halfword of the destination register.
@ Arm_Call
Write immediate value for unconditional PC-relative branch with link.
@ FirstDataRelocation
Relocations of class Data respect target endianness (unless otherwise specified)
@ Thumb_Jump24
Write immediate value for PC-relative branch without link.
@ Arm_Jump24
Write immediate value for conditional PC-relative branch without link.
@ Thumb_MovwAbsNC
Write immediate value to the lower halfword of the destination register.
@ FirstArmRelocation
Relocations of class Arm (covers fixed-width 4-byte instruction subset)
@ Data_Delta32
Relative 32-bit value relocation.
@ Thumb_Call
Write immediate value for unconditional PC-relative branch with link.
@ Thumb_MovtAbs
Write immediate value to the top halfword of the destination register.
Error applyFixupThumb(LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)
Helper function to apply the fixup for Thumb-class relocations.
Error applyFixup(LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)
Apply fixup expression for edge to block content.
Error applyFixupData(LinkGraph &G, Block &B, const Edge &E)
Helper function to apply the fixup for Data-class relocations.
ArmConfig getArmConfigForCPUArch(ARMBuildAttrs::CPUArch CPUArch)
Obtain the sub-arch configuration for a given Arm CPU model.
const char * getCPUArchName(ARMBuildAttrs::CPUArch K)
Human-readable name for a given CPU architecture kind.
Error applyFixupArm(LinkGraph &G, Block &B, const Edge &E)
Helper function to apply the fixup for Arm-class relocations.
const char * getEdgeKindName(Edge::Kind K)
Get a human-readable name for the given AArch32 edge kind.
bool hasTargetFlags(Symbol &Sym, TargetFlagsType Flags)
Check whether the given target flags are set for this Symbol.
StubsFlavor
AArch32 uses stubs for a number of purposes, like branch range extension or interworking between Arm ...
TargetFlags_aarch32
Flags enum for AArch32-specific symbol properties.
Expected< int64_t > readAddend(LinkGraph &G, Block &B, const Edge &E, const ArmConfig &ArmCfg)
Read the initial addend for a REL-type relocation.
Expected< int64_t > readAddendArm(LinkGraph &G, Block &B, const Edge &E)
Helper function to read the initial addend for Arm-class relocations.
Expected< int64_t > readAddendData(LinkGraph &G, Block &B, const Edge &E)
Helper function to read the initial addend for Data-class relocations.
uint8_t TargetFlagsType
Holds target-specific properties for a symbol.
This is an optimization pass for GlobalISel generic memory operations.
auto formatv(const char *Fmt, Ts &&... Vals) -> formatv_object< decltype(std::make_tuple(detail::build_format_adapter(std::forward< Ts >(Vals))...))>
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
JITLink sub-arch configuration for Arm CPU models.
Collection of named constants per fixup kind.
Immutable pair of halfwords, Hi and Lo, with overflow check.
constexpr HalfWords(uint32_t Hi, uint32_t Lo)