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bool | llvm::AMDGPU::isHsaAbi (const MCSubtargetInfo &STI) |
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unsigned | llvm::AMDGPU::getAMDHSACodeObjectVersion (const Module &M) |
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unsigned | llvm::AMDGPU::getAMDHSACodeObjectVersion (unsigned ABIVersion) |
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unsigned | llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion () |
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uint8_t | llvm::AMDGPU::getELFABIVersion (const Triple &T, unsigned CodeObjectVersion) |
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unsigned | llvm::AMDGPU::getMultigridSyncArgImplicitArgPosition (unsigned CodeObjectVersion) |
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unsigned | llvm::AMDGPU::getHostcallImplicitArgPosition (unsigned CodeObjectVersion) |
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unsigned | llvm::AMDGPU::getDefaultQueueImplicitArgPosition (unsigned CodeObjectVersion) |
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unsigned | llvm::AMDGPU::getCompletionActionImplicitArgPosition (unsigned CodeObjectVersion) |
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unsigned | llvm::AMDGPU::IsaInfo::getWavefrontSize (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getLocalMemorySize (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getAddressableLocalMemorySize (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getEUsPerCU (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) |
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unsigned | llvm::AMDGPU::IsaInfo::getMinWavesPerEU (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getMaxWavesPerEU (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) |
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unsigned | llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup (const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize) |
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unsigned | llvm::AMDGPU::IsaInfo::getSGPRAllocGranule (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getSGPREncodingGranule (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getTotalNumSGPRs (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getMinNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU) |
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unsigned | llvm::AMDGPU::IsaInfo::getMaxNumSGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable) |
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unsigned | llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed) |
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unsigned | llvm::AMDGPU::IsaInfo::getNumExtraSGPRs (const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed) |
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unsigned | llvm::AMDGPU::IsaInfo::getNumSGPRBlocks (const MCSubtargetInfo *STI, unsigned NumSGPRs) |
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unsigned | llvm::AMDGPU::IsaInfo::getVGPRAllocGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32) |
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unsigned | llvm::AMDGPU::IsaInfo::getVGPREncodingGranule (const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32) |
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unsigned | llvm::AMDGPU::IsaInfo::getTotalNumVGPRs (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getAddressableNumArchVGPRs (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs (const MCSubtargetInfo *STI) |
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unsigned | llvm::AMDGPU::IsaInfo::getMinNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU) |
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unsigned | llvm::AMDGPU::IsaInfo::getMaxNumVGPRs (const MCSubtargetInfo *STI, unsigned WavesPerEU) |
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unsigned | llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (const MCSubtargetInfo *STI, unsigned NumVGPRs) |
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unsigned | llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs (unsigned NumVGPRs, unsigned Granule, unsigned MaxWaves, unsigned TotalNumVGPRs) |
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unsigned | llvm::AMDGPU::IsaInfo::getOccupancyWithNumSGPRs (unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen) |
|
unsigned | llvm::AMDGPU::IsaInfo::getEncodedNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32) |
|
unsigned | llvm::AMDGPU::IsaInfo::getAllocatedNumVGPRBlocks (const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32) |
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LLVM_READONLY int16_t | llvm::AMDGPU::getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIdx) |
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LLVM_READONLY bool | llvm::AMDGPU::hasNamedOperand (uint64_t Opcode, uint64_t NamedIdx) |
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LLVM_READONLY int | llvm::AMDGPU::getSOPPWithRelaxation (uint16_t Opcode) |
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const MIMGBaseOpcodeInfo * | llvm::AMDGPU::getMIMGBaseOpcode (unsigned Opc) |
|
LLVM_READONLY const MIMGBaseOpcodeInfo * | llvm::AMDGPU::getMIMGBaseOpcodeInfo (unsigned BaseOpcode) |
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LLVM_READONLY const MIMGDimInfo * | llvm::AMDGPU::getMIMGDimInfo (unsigned DimEnum) |
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LLVM_READONLY const MIMGDimInfo * | llvm::AMDGPU::getMIMGDimInfoByEncoding (uint8_t DimEnc) |
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LLVM_READONLY const MIMGDimInfo * | llvm::AMDGPU::getMIMGDimInfoByAsmSuffix (StringRef AsmSuffix) |
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LLVM_READONLY const MIMGLZMappingInfo * | llvm::AMDGPU::getMIMGLZMappingInfo (unsigned L) |
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LLVM_READONLY const MIMGMIPMappingInfo * | llvm::AMDGPU::getMIMGMIPMappingInfo (unsigned MIP) |
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LLVM_READONLY const MIMGBiasMappingInfo * | llvm::AMDGPU::getMIMGBiasMappingInfo (unsigned Bias) |
|
LLVM_READONLY const MIMGOffsetMappingInfo * | llvm::AMDGPU::getMIMGOffsetMappingInfo (unsigned Offset) |
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LLVM_READONLY const MIMGG16MappingInfo * | llvm::AMDGPU::getMIMGG16MappingInfo (unsigned G) |
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int | llvm::AMDGPU::getMIMGOpcode (unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords) |
|
int | llvm::AMDGPU::getMaskedMIMGOp (unsigned Opc, unsigned NewChannels) |
|
unsigned | llvm::AMDGPU::getAddrSizeMIMGOp (const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported) |
|
LLVM_READONLY const MIMGInfo * | llvm::AMDGPU::getMIMGInfo (unsigned Opc) |
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int | llvm::AMDGPU::getMTBUFBaseOpcode (unsigned Opc) |
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int | llvm::AMDGPU::getMTBUFOpcode (unsigned BaseOpc, unsigned Elements) |
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int | llvm::AMDGPU::getMTBUFElements (unsigned Opc) |
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bool | llvm::AMDGPU::getMTBUFHasVAddr (unsigned Opc) |
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bool | llvm::AMDGPU::getMTBUFHasSrsrc (unsigned Opc) |
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bool | llvm::AMDGPU::getMTBUFHasSoffset (unsigned Opc) |
|
int | llvm::AMDGPU::getMUBUFBaseOpcode (unsigned Opc) |
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int | llvm::AMDGPU::getMUBUFOpcode (unsigned BaseOpc, unsigned Elements) |
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int | llvm::AMDGPU::getMUBUFElements (unsigned Opc) |
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bool | llvm::AMDGPU::getMUBUFHasVAddr (unsigned Opc) |
|
bool | llvm::AMDGPU::getMUBUFHasSrsrc (unsigned Opc) |
|
bool | llvm::AMDGPU::getMUBUFHasSoffset (unsigned Opc) |
|
bool | llvm::AMDGPU::getMUBUFIsBufferInv (unsigned Opc) |
|
bool | llvm::AMDGPU::getMUBUFTfe (unsigned Opc) |
|
bool | llvm::AMDGPU::getSMEMIsBuffer (unsigned Opc) |
|
bool | llvm::AMDGPU::getVOP1IsSingle (unsigned Opc) |
|
bool | llvm::AMDGPU::getVOP2IsSingle (unsigned Opc) |
|
bool | llvm::AMDGPU::getVOP3IsSingle (unsigned Opc) |
|
bool | llvm::AMDGPU::isVOPC64DPP (unsigned Opc) |
|
bool | llvm::AMDGPU::isVOPCAsmOnly (unsigned Opc) |
|
bool | llvm::AMDGPU::getMAIIsDGEMM (unsigned Opc) |
| Returns true if MAI operation is a double precision GEMM.
|
|
bool | llvm::AMDGPU::getMAIIsGFX940XDL (unsigned Opc) |
|
unsigned | llvm::AMDGPU::getVOPDEncodingFamily (const MCSubtargetInfo &ST) |
|
CanBeVOPD | llvm::AMDGPU::getCanBeVOPD (unsigned Opc) |
|
const GcnBufferFormatInfo * | llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI) |
|
const GcnBufferFormatInfo * | llvm::AMDGPU::getGcnBufferFormatInfo (uint8_t Format, const MCSubtargetInfo &STI) |
|
int | llvm::AMDGPU::getMCOpcode (uint16_t Opcode, unsigned Gen) |
|
unsigned | llvm::AMDGPU::getVOPDOpcode (unsigned Opc) |
|
int | llvm::AMDGPU::getVOPDFull (unsigned OpX, unsigned OpY, unsigned EncodingFamily) |
|
bool | llvm::AMDGPU::isVOPD (unsigned Opc) |
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bool | llvm::AMDGPU::isMAC (unsigned Opc) |
|
bool | llvm::AMDGPU::isPermlane16 (unsigned Opc) |
|
bool | llvm::AMDGPU::isGenericAtomic (unsigned Opc) |
|
bool | llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64 (unsigned Opc) |
|
std::pair< unsigned, unsigned > | llvm::AMDGPU::getVOPDComponents (unsigned VOPDOpcode) |
|
VOPD::InstInfo | llvm::AMDGPU::getVOPDInstInfo (const MCInstrDesc &OpX, const MCInstrDesc &OpY) |
|
VOPD::InstInfo | llvm::AMDGPU::getVOPDInstInfo (unsigned VOPDOpcode, const MCInstrInfo *InstrInfo) |
|
bool | llvm::AMDGPU::isTrue16Inst (unsigned Opc) |
|
bool | llvm::AMDGPU::isInvalidSingleUseConsumerInst (unsigned Opc) |
|
bool | llvm::AMDGPU::isInvalidSingleUseProducerInst (unsigned Opc) |
|
unsigned | llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode (unsigned Opc) |
|
unsigned | llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode (unsigned Opc) |
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void | llvm::AMDGPU::initDefaultAMDKernelCodeT (AMDGPUMCKernelCodeT &KernelCode, const MCSubtargetInfo *STI) |
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bool | llvm::AMDGPU::isGroupSegment (const GlobalValue *GV) |
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bool | llvm::AMDGPU::isGlobalSegment (const GlobalValue *GV) |
|
bool | llvm::AMDGPU::isReadOnlySegment (const GlobalValue *GV) |
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bool | llvm::AMDGPU::shouldEmitConstantsToTextSection (const Triple &TT) |
|
int | llvm::AMDGPU::getIntegerAttribute (const Function &F, StringRef Name, int Default) |
|
std::pair< unsigned, unsigned > | llvm::AMDGPU::getIntegerPairAttribute (const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired) |
|
SmallVector< unsigned > | llvm::AMDGPU::getIntegerVecAttribute (const Function &F, StringRef Name, unsigned Size) |
|
unsigned | llvm::AMDGPU::getVmcntBitMask (const IsaVersion &Version) |
|
unsigned | llvm::AMDGPU::getExpcntBitMask (const IsaVersion &Version) |
|
unsigned | llvm::AMDGPU::getLgkmcntBitMask (const IsaVersion &Version) |
|
unsigned | llvm::AMDGPU::getWaitcntBitMask (const IsaVersion &Version) |
|
unsigned | llvm::AMDGPU::decodeVmcnt (const IsaVersion &Version, unsigned Waitcnt) |
|
unsigned | llvm::AMDGPU::decodeExpcnt (const IsaVersion &Version, unsigned Waitcnt) |
|
unsigned | llvm::AMDGPU::decodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt) |
|
void | llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) |
| Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version , and writes decoded values into Vmcnt , Expcnt and Lgkmcnt respectively.
|
|
Waitcnt | llvm::AMDGPU::decodeWaitcnt (const IsaVersion &Version, unsigned Encoded) |
|
unsigned | llvm::AMDGPU::encodeVmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt) |
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unsigned | llvm::AMDGPU::encodeExpcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt) |
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unsigned | llvm::AMDGPU::encodeLgkmcnt (const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt) |
|
unsigned | llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) |
| Encodes Vmcnt , Expcnt and Lgkmcnt into Waitcnt for given isa Version .
|
|
unsigned | llvm::AMDGPU::encodeWaitcnt (const IsaVersion &Version, const Waitcnt &Decoded) |
|
unsigned | llvm::AMDGPU::getLoadcntBitMask (const IsaVersion &Version) |
|
unsigned | llvm::AMDGPU::getSamplecntBitMask (const IsaVersion &Version) |
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unsigned | llvm::AMDGPU::getBvhcntBitMask (const IsaVersion &Version) |
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unsigned | llvm::AMDGPU::getDscntBitMask (const IsaVersion &Version) |
|
unsigned | llvm::AMDGPU::getKmcntBitMask (const IsaVersion &Version) |
|
unsigned | llvm::AMDGPU::getStorecntBitMask (const IsaVersion &Version) |
|
Waitcnt | llvm::AMDGPU::decodeLoadcntDscnt (const IsaVersion &Version, unsigned LoadcntDscnt) |
|
Waitcnt | llvm::AMDGPU::decodeStorecntDscnt (const IsaVersion &Version, unsigned StorecntDscnt) |
|
unsigned | llvm::AMDGPU::encodeLoadcntDscnt (const IsaVersion &Version, const Waitcnt &Decoded) |
|
unsigned | llvm::AMDGPU::encodeStorecntDscnt (const IsaVersion &Version, const Waitcnt &Decoded) |
|
int | llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding (const MCSubtargetInfo &STI) |
|
int | llvm::AMDGPU::DepCtr::encodeDepCtr (const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding (unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::DepCtr::decodeDepCtr (unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI) |
|
unsigned | llvm::AMDGPU::DepCtr::decodeFieldVaVdst (unsigned Encoded) |
|
unsigned | llvm::AMDGPU::DepCtr::decodeFieldVmVsrc (unsigned Encoded) |
|
unsigned | llvm::AMDGPU::DepCtr::decodeFieldSaSdst (unsigned Encoded) |
|
unsigned | llvm::AMDGPU::DepCtr::encodeFieldVmVsrc (unsigned VmVsrc) |
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unsigned | llvm::AMDGPU::DepCtr::encodeFieldVmVsrc (unsigned Encoded, unsigned VmVsrc) |
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unsigned | llvm::AMDGPU::DepCtr::encodeFieldVaVdst (unsigned VaVdst) |
|
unsigned | llvm::AMDGPU::DepCtr::encodeFieldVaVdst (unsigned Encoded, unsigned VaVdst) |
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unsigned | llvm::AMDGPU::DepCtr::encodeFieldSaSdst (unsigned SaSdst) |
|
unsigned | llvm::AMDGPU::DepCtr::encodeFieldSaSdst (unsigned Encoded, unsigned SaSdst) |
|
bool | llvm::AMDGPU::Exp::getTgtName (unsigned Id, StringRef &Name, int &Index) |
|
unsigned | llvm::AMDGPU::Exp::getTgtId (const StringRef Name) |
|
bool | llvm::AMDGPU::Exp::isSupportedTgtId (unsigned Id, const MCSubtargetInfo &STI) |
|
int64_t | llvm::AMDGPU::MTBUFFormat::encodeDfmtNfmt (unsigned Dfmt, unsigned Nfmt) |
|
void | llvm::AMDGPU::MTBUFFormat::decodeDfmtNfmt (unsigned Format, unsigned &Dfmt, unsigned &Nfmt) |
|
int64_t | llvm::AMDGPU::MTBUFFormat::getDfmt (const StringRef Name) |
|
StringRef | llvm::AMDGPU::MTBUFFormat::getDfmtName (unsigned Id) |
|
int64_t | llvm::AMDGPU::MTBUFFormat::getNfmt (const StringRef Name, const MCSubtargetInfo &STI) |
|
StringRef | llvm::AMDGPU::MTBUFFormat::getNfmtName (unsigned Id, const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::MTBUFFormat::isValidDfmtNfmt (unsigned Id, const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::MTBUFFormat::isValidNfmt (unsigned Id, const MCSubtargetInfo &STI) |
|
int64_t | llvm::AMDGPU::MTBUFFormat::getUnifiedFormat (const StringRef Name, const MCSubtargetInfo &STI) |
|
StringRef | llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName (unsigned Id, const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat (unsigned Id, const MCSubtargetInfo &STI) |
|
int64_t | llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt (unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding (unsigned Val, const MCSubtargetInfo &STI) |
|
unsigned | llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::SendMsg::isValidMsgId (int64_t MsgId, const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::SendMsg::isValidMsgOp (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict) |
|
bool | llvm::AMDGPU::SendMsg::isValidMsgStream (int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict) |
|
bool | llvm::AMDGPU::SendMsg::msgRequiresOp (int64_t MsgId, const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::SendMsg::msgSupportsStream (int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI) |
|
void | llvm::AMDGPU::SendMsg::decodeMsg (unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI) |
|
uint64_t | llvm::AMDGPU::SendMsg::encodeMsg (uint64_t MsgId, uint64_t OpId, uint64_t StreamId) |
|
unsigned | llvm::AMDGPU::getInitialPSInputAddr (const Function &F) |
|
bool | llvm::AMDGPU::getHasColorExport (const Function &F) |
|
bool | llvm::AMDGPU::getHasDepthExport (const Function &F) |
|
bool | llvm::AMDGPU::isShader (CallingConv::ID cc) |
|
bool | llvm::AMDGPU::isGraphics (CallingConv::ID cc) |
|
bool | llvm::AMDGPU::isCompute (CallingConv::ID cc) |
|
bool | llvm::AMDGPU::isEntryFunctionCC (CallingConv::ID CC) |
|
bool | llvm::AMDGPU::isModuleEntryFunctionCC (CallingConv::ID CC) |
|
bool | llvm::AMDGPU::isChainCC (CallingConv::ID CC) |
|
bool | llvm::AMDGPU::isKernelCC (const Function *Func) |
|
LLVM_READNONE bool | llvm::AMDGPU::isKernel (CallingConv::ID CC) |
|
bool | llvm::AMDGPU::hasXNACK (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasSRAMECC (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasMIMG_R128 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasA16 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasG16 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasPackedD16 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasGDS (const MCSubtargetInfo &STI) |
|
unsigned | llvm::AMDGPU::getNSAMaxSize (const MCSubtargetInfo &STI, bool HasSampler) |
|
unsigned | llvm::AMDGPU::getMaxNumUserSGPRs (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isSI (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isCI (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isVI (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX9 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX9_GFX10 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX9_GFX10_GFX11 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX8_GFX9_GFX10 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX8Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX9Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isNotGFX9Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX10 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX10_GFX11 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX10Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isNotGFX10Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX10Before1030 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX11 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX11Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX12 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX12Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isNotGFX12Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isNotGFX11Plus (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGCN3Encoding (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX10_AEncoding (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX10_BEncoding (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasGFX10_3Insts (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX10_3_GFX11 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX90A (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::isGFX940 (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasArchitectedFlatScratch (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasMAIInsts (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasVOPD (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasDPPSrc1SGPR (const MCSubtargetInfo &STI) |
|
int32_t | llvm::AMDGPU::getTotalNumVGPRs (bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR) |
|
unsigned | llvm::AMDGPU::hasKernargPreload (const MCSubtargetInfo &STI) |
|
bool | llvm::AMDGPU::hasSMRDSignedImmOffset (const MCSubtargetInfo &ST) |
|
bool | llvm::AMDGPU::isSGPR (unsigned Reg, const MCRegisterInfo *TRI) |
| Is Reg - scalar register.
|
|
bool | llvm::AMDGPU::isHi (unsigned Reg, const MCRegisterInfo &MRI) |
|
unsigned | llvm::AMDGPU::getMCReg (unsigned Reg, const MCSubtargetInfo &STI) |
| If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg .
|
|
unsigned | llvm::AMDGPU::mc2PseudoReg (unsigned Reg) |
| Convert hardware register Reg to a pseudo register.
|
|
bool | llvm::AMDGPU::isInlineValue (unsigned Reg) |
|
bool | llvm::AMDGPU::isSISrcOperand (const MCInstrDesc &Desc, unsigned OpNo) |
| Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).
|
|
bool | llvm::AMDGPU::isKImmOperand (const MCInstrDesc &Desc, unsigned OpNo) |
| Is this a KImm operand?
|
|
bool | llvm::AMDGPU::isSISrcFPOperand (const MCInstrDesc &Desc, unsigned OpNo) |
| Is this floating-point operand?
|
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bool | llvm::AMDGPU::isSISrcInlinableOperand (const MCInstrDesc &Desc, unsigned OpNo) |
| Does this operand support only inlinable literals?
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unsigned | llvm::AMDGPU::getRegBitWidth (unsigned RCID) |
| Get the size in bits of a register from the register class RC .
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unsigned | llvm::AMDGPU::getRegBitWidth (const MCRegisterClass &RC) |
| Get the size in bits of a register from the register class RC .
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unsigned | llvm::AMDGPU::getRegOperandSize (const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo) |
| Get size of register operand.
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LLVM_READNONE unsigned | llvm::AMDGPU::getOperandSize (const MCOperandInfo &OpInfo) |
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LLVM_READNONE unsigned | llvm::AMDGPU::getOperandSize (const MCInstrDesc &Desc, unsigned OpNo) |
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LLVM_READNONE bool | llvm::AMDGPU::isInlinableIntLiteral (int64_t Literal) |
| Is this literal inlinable, and not one of the values intended for floating point values.
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bool | llvm::AMDGPU::isInlinableLiteral64 (int64_t Literal, bool HasInv2Pi) |
| Is this literal inlinable.
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bool | llvm::AMDGPU::isInlinableLiteral32 (int32_t Literal, bool HasInv2Pi) |
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bool | llvm::AMDGPU::isInlinableLiteralBF16 (int16_t Literal, bool HasInv2Pi) |
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bool | llvm::AMDGPU::isInlinableLiteralFP16 (int16_t Literal, bool HasInv2Pi) |
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bool | llvm::AMDGPU::isInlinableLiteralI16 (int32_t Literal, bool HasInv2Pi) |
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std::optional< unsigned > | llvm::AMDGPU::getInlineEncodingV2I16 (uint32_t Literal) |
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std::optional< unsigned > | llvm::AMDGPU::getInlineEncodingV2BF16 (uint32_t Literal) |
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std::optional< unsigned > | llvm::AMDGPU::getInlineEncodingV2F16 (uint32_t Literal) |
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bool | llvm::AMDGPU::isInlinableLiteralV216 (uint32_t Literal, uint8_t OpType) |
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bool | llvm::AMDGPU::isInlinableLiteralV2I16 (uint32_t Literal) |
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bool | llvm::AMDGPU::isInlinableLiteralV2BF16 (uint32_t Literal) |
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bool | llvm::AMDGPU::isInlinableLiteralV2F16 (uint32_t Literal) |
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bool | llvm::AMDGPU::isValid32BitLiteral (uint64_t Val, bool IsFP64) |
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bool | llvm::AMDGPU::isArgPassedInSGPR (const Argument *A) |
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bool | llvm::AMDGPU::isArgPassedInSGPR (const CallBase *CB, unsigned ArgNo) |
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bool | llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset) |
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bool | llvm::AMDGPU::isLegalSMRDEncodedSignedOffset (const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer) |
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uint64_t | llvm::AMDGPU::convertSMRDOffsetUnits (const MCSubtargetInfo &ST, uint64_t ByteOffset) |
| Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
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std::optional< int64_t > | llvm::AMDGPU::getSMRDEncodedOffset (const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer, bool HasSOffset) |
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std::optional< int64_t > | llvm::AMDGPU::getSMRDEncodedLiteralOffset32 (const MCSubtargetInfo &ST, int64_t ByteOffset) |
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unsigned | llvm::AMDGPU::getNumFlatOffsetBits (const MCSubtargetInfo &ST) |
| For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
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bool | llvm::AMDGPU::isLegalSMRDImmOffset (const MCSubtargetInfo &ST, int64_t ByteOffset) |
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LLVM_READNONE bool | llvm::AMDGPU::isLegalDPALU_DPPControl (unsigned DC) |
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bool | llvm::AMDGPU::hasAny64BitVGPROperands (const MCInstrDesc &OpDesc) |
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bool | llvm::AMDGPU::isDPALU_DPP (const MCInstrDesc &OpDesc) |
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bool | llvm::AMDGPU::isIntrinsicSourceOfDivergence (unsigned IntrID) |
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bool | llvm::AMDGPU::isIntrinsicAlwaysUniform (unsigned IntrID) |
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unsigned | llvm::AMDGPU::getLdsDwGranularity (const MCSubtargetInfo &ST) |
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raw_ostream & | llvm::operator<< (raw_ostream &OS, const AMDGPU::IsaInfo::TargetIDSetting S) |
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