LLVM 18.0.0git
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Classes | |
class | AMDGPUTargetID |
Enumerations | |
enum | { FIXED_NUM_SGPRS_FOR_INIT_BUG = 96 , TRAP_NUM_SGPRS = 16 } |
enum class | TargetIDSetting { Unsupported , Any , Off , On } |
anonymous enum |
Enumerator | |
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FIXED_NUM_SGPRS_FOR_INIT_BUG | |
TRAP_NUM_SGPRS |
Definition at line 98 of file AMDGPUBaseInfo.h.
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strong |
Enumerator | |
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Unsupported | |
Any | |
Off | |
On |
Definition at line 105 of file AMDGPUBaseInfo.h.
unsigned llvm::AMDGPU::IsaInfo::getAddressableLocalMemorySize | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 814 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), and llvm::FeatureBitset::test().
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 905 of file AMDGPUBaseInfo.cpp.
References FIXED_NUM_SGPRS_FOR_INIT_BUG, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::getIsaVersion(), and llvm::FeatureBitset::test().
Referenced by llvm::GCNSubtarget::getAddressableNumSGPRs(), getMaxNumSGPRs(), getMinNumSGPRs(), and getSGPRAllocGranule().
unsigned llvm::AMDGPU::IsaInfo::getAddressableNumVGPRs | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 1029 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), and llvm::FeatureBitset::test().
Referenced by llvm::GCNSubtarget::getAddressableNumVGPRs(), getMaxNumVGPRs(), getMinNumVGPRs(), and llvm::GCNSchedStrategy::initialize().
unsigned llvm::AMDGPU::IsaInfo::getEUsPerCU | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 822 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::isGFX10Plus(), and llvm::FeatureBitset::test().
Referenced by llvm::GCNSubtarget::GCNSubtarget(), getMaxWorkGroupsPerCU(), and getWavesPerEUForWorkGroup().
unsigned llvm::AMDGPU::IsaInfo::getLocalMemorySize | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 798 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::isGFX10Plus(), and llvm::FeatureBitset::test().
unsigned llvm::AMDGPU::IsaInfo::getMaxFlatWorkGroupSize | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 875 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::GCNSubtarget::getMaxFlatWorkGroupSize(), and llvm::R600Subtarget::getMaxFlatWorkGroupSize().
unsigned llvm::AMDGPU::IsaInfo::getMaxNumSGPRs | ( | const MCSubtargetInfo * | STI, |
unsigned | WavesPerEU, | ||
bool | Addressable | ||
) |
STI
. Definition at line 934 of file AMDGPUBaseInfo.cpp.
References llvm::alignDown(), assert(), getAddressableNumSGPRs(), llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::getIsaVersion(), getSGPRAllocGranule(), getTotalNumSGPRs(), llvm::FeatureBitset::test(), and TRAP_NUM_SGPRS.
Referenced by llvm::GCNSubtarget::getMaxNumSGPRs().
unsigned llvm::AMDGPU::IsaInfo::getMaxNumVGPRs | ( | const MCSubtargetInfo * | STI, |
unsigned | WavesPerEU | ||
) |
STI
. Definition at line 1069 of file AMDGPUBaseInfo.cpp.
References llvm::alignDown(), assert(), getAddressableNumVGPRs(), getTotalNumVGPRs(), and getVGPRAllocGranule().
Referenced by llvm::GCNSubtarget::getMaxNumVGPRs().
unsigned llvm::AMDGPU::IsaInfo::getMaxWavesPerEU | ( | const MCSubtargetInfo * | STI | ) |
STI
without any kind of limitation. Definition at line 856 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::hasGFX10_3Insts(), llvm::AMDGPU::isGFX10Plus(), and llvm::AMDGPU::isGFX90A().
Referenced by llvm::GCNSubtarget::GCNSubtarget(), getMaxWorkGroupsPerCU(), getMinNumSGPRs(), getMinNumVGPRs(), and getNumWavesPerEUWithNumVGPRs().
unsigned llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU | ( | const MCSubtargetInfo * | STI, |
unsigned | FlatWorkGroupSize | ||
) |
STI
and limited by given FlatWorkGroupSize
. Definition at line 833 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::amdgcn, assert(), llvm::Triple::getArch(), getEUsPerCU(), llvm::MCSubtargetInfo::getFeatureBits(), getMaxWavesPerEU(), llvm::MCSubtargetInfo::getTargetTriple(), getWavesPerWorkGroup(), llvm::AMDGPU::isGFX10Plus(), N, and llvm::FeatureBitset::test().
Referenced by llvm::GCNSubtarget::getMaxWorkGroupsPerCU(), and llvm::R600Subtarget::getMaxWorkGroupsPerCU().
unsigned llvm::AMDGPU::IsaInfo::getMinFlatWorkGroupSize | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 871 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::GCNSubtarget::getMinFlatWorkGroupSize(), and llvm::R600Subtarget::getMinFlatWorkGroupSize().
unsigned llvm::AMDGPU::IsaInfo::getMinNumSGPRs | ( | const MCSubtargetInfo * | STI, |
unsigned | WavesPerEU | ||
) |
STI
. Definition at line 917 of file AMDGPUBaseInfo.cpp.
References llvm::alignDown(), assert(), getAddressableNumSGPRs(), llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::getIsaVersion(), getMaxWavesPerEU(), getSGPRAllocGranule(), getTotalNumSGPRs(), llvm::FeatureBitset::test(), and TRAP_NUM_SGPRS.
Referenced by llvm::GCNSubtarget::getMinNumSGPRs().
unsigned llvm::AMDGPU::IsaInfo::getMinNumVGPRs | ( | const MCSubtargetInfo * | STI, |
unsigned | WavesPerEU | ||
) |
STI
. Definition at line 1045 of file AMDGPUBaseInfo.cpp.
References llvm::alignDown(), assert(), getAddressableNumVGPRs(), getMaxWavesPerEU(), getMinNumVGPRs(), getNumWavesPerEUWithNumVGPRs(), getTotalNumVGPRs(), and getVGPRAllocGranule().
Referenced by getMinNumVGPRs(), and llvm::GCNSubtarget::getMinNumVGPRs().
unsigned llvm::AMDGPU::IsaInfo::getMinWavesPerEU | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 852 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::GCNSubtarget::getMinWavesPerEU(), and llvm::R600Subtarget::getMinWavesPerEU().
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs | ( | const MCSubtargetInfo * | STI, |
bool | VCCUsed, | ||
bool | FlatScrUsed | ||
) |
STI
when the given special registers are used. XNACK is inferred from STI
. Definition at line 976 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), getNumExtraSGPRs(), and llvm::FeatureBitset::test().
unsigned llvm::AMDGPU::IsaInfo::getNumExtraSGPRs | ( | const MCSubtargetInfo * | STI, |
bool | VCCUsed, | ||
bool | FlatScrUsed, | ||
bool | XNACKUsed | ||
) |
STI
when the given special registers are used. Definition at line 951 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::getIsaVersion(), and llvm::FeatureBitset::test().
Referenced by llvm::AMDGPUAsmPrinter::emitFunctionBodyEnd(), getNumExtraSGPRs(), and llvm::AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumSGPRs().
unsigned llvm::AMDGPU::IsaInfo::getNumSGPRBlocks | ( | const MCSubtargetInfo * | STI, |
unsigned | NumSGPRs | ||
) |
STI
when NumSGPRs
are used. NumSGPRs
should already include any special register counts. Definition at line 982 of file AMDGPUBaseInfo.cpp.
References llvm::alignTo(), and getSGPREncodingGranule().
unsigned llvm::AMDGPU::IsaInfo::getNumVGPRBlocks | ( | const MCSubtargetInfo * | STI, |
unsigned | NumSGPRs, | ||
std::optional< bool > | EnableWavefrontSize32 = std::nullopt |
||
) |
STI
when NumVGPRs
are used.For subtargets which support it, EnableWavefrontSize32
should match the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
Definition at line 1078 of file AMDGPUBaseInfo.cpp.
References llvm::alignTo(), and getVGPREncodingGranule().
unsigned llvm::AMDGPU::IsaInfo::getNumWavesPerEUWithNumVGPRs | ( | const MCSubtargetInfo * | STI, |
unsigned | NumVGPRs | ||
) |
NumVGPRs
usage for given subtarget STI
. Definition at line 1035 of file AMDGPUBaseInfo.cpp.
References llvm::alignTo(), getMaxWavesPerEU(), getTotalNumVGPRs(), and getVGPRAllocGranule().
Referenced by getMinNumVGPRs(), and llvm::GCNSubtarget::getOccupancyWithNumVGPRs().
unsigned llvm::AMDGPU::IsaInfo::getSGPRAllocGranule | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 885 of file AMDGPUBaseInfo.cpp.
References getAddressableNumSGPRs(), llvm::MCSubtargetInfo::getCPU(), and llvm::AMDGPU::getIsaVersion().
Referenced by getMaxNumSGPRs(), getMinNumSGPRs(), and llvm::GCNSubtarget::getSGPRAllocGranule().
unsigned llvm::AMDGPU::IsaInfo::getSGPREncodingGranule | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 894 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), getNumSGPRBlocks(), and llvm::GCNSubtarget::getSGPREncodingGranule().
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static |
Definition at line 718 of file AMDGPUBaseInfo.cpp.
References llvm::StringRef::endswith(), llvm_unreachable, Off, and On.
Referenced by llvm::AMDGPU::IsaInfo::AMDGPUTargetID::setTargetIDFromTargetIDStream().
unsigned llvm::AMDGPU::IsaInfo::getTotalNumSGPRs | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 898 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getCPU(), and llvm::AMDGPU::getIsaVersion().
Referenced by getMaxNumSGPRs(), getMinNumSGPRs(), and llvm::GCNSubtarget::getTotalNumSGPRs().
unsigned llvm::AMDGPU::IsaInfo::getTotalNumVGPRs | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 1018 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::isGFX10Plus(), and llvm::FeatureBitset::test().
Referenced by getMaxNumVGPRs(), getMinNumVGPRs(), getNumWavesPerEUWithNumVGPRs(), and llvm::GCNSubtarget::getTotalNumVGPRs().
unsigned llvm::AMDGPU::IsaInfo::getVGPRAllocGranule | ( | const MCSubtargetInfo * | STI, |
std::optional< bool > | EnableWavefrontSize32 = std::nullopt |
||
) |
STI
.For subtargets which support it, EnableWavefrontSize32
should match the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
Definition at line 988 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), llvm::AMDGPU::hasGFX10_3Insts(), and llvm::FeatureBitset::test().
Referenced by getMaxNumVGPRs(), getMinNumVGPRs(), getNumWavesPerEUWithNumVGPRs(), llvm::GCNSubtarget::getVGPRAllocGranule(), and llvm::GCNSchedStrategy::initialize().
unsigned llvm::AMDGPU::IsaInfo::getVGPREncodingGranule | ( | const MCSubtargetInfo * | STI, |
std::optional< bool > | EnableWavefrontSize32 = std::nullopt |
||
) |
STI
.For subtargets which support it, EnableWavefrontSize32
should match the ENABLE_WAVEFRONT_SIZE32 kernel descriptor field.
Definition at line 1006 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), and llvm::FeatureBitset::test().
Referenced by llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(), getNumVGPRBlocks(), and llvm::GCNSubtarget::getVGPREncodingGranule().
unsigned llvm::AMDGPU::IsaInfo::getWavefrontSize | ( | const MCSubtargetInfo * | STI | ) |
STI
. Definition at line 789 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits(), and llvm::FeatureBitset::test().
Referenced by getWavesPerWorkGroup().
unsigned llvm::AMDGPU::IsaInfo::getWavesPerEUForWorkGroup | ( | const MCSubtargetInfo * | STI, |
unsigned | FlatWorkGroupSize | ||
) |
FlatWorkGroupSize
. Definition at line 865 of file AMDGPUBaseInfo.cpp.
References llvm::divideCeil(), getEUsPerCU(), and getWavesPerWorkGroup().
Referenced by llvm::GCNSubtarget::getWavesPerEUForWorkGroup(), and llvm::R600Subtarget::getWavesPerEUForWorkGroup().
unsigned llvm::AMDGPU::IsaInfo::getWavesPerWorkGroup | ( | const MCSubtargetInfo * | STI, |
unsigned | FlatWorkGroupSize | ||
) |
STI
and FlatWorkGroupSize
. Definition at line 880 of file AMDGPUBaseInfo.cpp.
References llvm::divideCeil(), and getWavefrontSize().
Referenced by getMaxWorkGroupsPerCU(), and getWavesPerEUForWorkGroup().