LLVM 17.0.0git
AMDGPUDisassembler.cpp
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1//===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//===----------------------------------------------------------------------===//
10//
11/// \file
12///
13/// This file contains definition for AMDGPU ISA disassembler
14//
15//===----------------------------------------------------------------------===//
16
17// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18
21#include "SIDefines.h"
22#include "SIRegisterInfo.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/MC/MCContext.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInstrDesc.h"
36
37using namespace llvm;
38
39#define DEBUG_TYPE "amdgpu-disassembler"
40
41#define SGPR_MAX \
42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
43 : AMDGPU::EncValues::SGPR_MAX_SI)
44
46
48 MCContext &Ctx,
49 MCInstrInfo const *MCII) :
50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
52
53 // ToDo: AMDGPUDisassembler supports only VI ISA.
54 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
55 report_fatal_error("Disassembly not yet supported for subtarget");
56}
57
59addOperand(MCInst &Inst, const MCOperand& Opnd) {
60 Inst.addOperand(Opnd);
61 return Opnd.isValid() ?
64}
65
66static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
67 uint16_t NameIdx) {
68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
69 if (OpIdx != -1) {
70 auto I = MI.begin();
71 std::advance(I, OpIdx);
72 MI.insert(I, Op);
73 }
74 return OpIdx;
75}
76
77static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
79 const MCDisassembler *Decoder) {
80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
81
82 // Our branches take a simm16, but we need two extra bits to account for the
83 // factor of 4.
84 APInt SignedOffset(18, Imm * 4, true);
85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
86
87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0))
89 return addOperand(Inst, MCOperand::createImm(Imm));
90}
91
92static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr,
93 const MCDisassembler *Decoder) {
94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
95 int64_t Offset;
96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets.
97 Offset = Imm & 0xFFFFF;
98 } else { // GFX9+ supports 21-bit signed offsets.
99 Offset = SignExtend64<21>(Imm);
100 }
102}
103
104static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr,
105 const MCDisassembler *Decoder) {
106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
107 return addOperand(Inst, DAsm->decodeBoolReg(Val));
108}
109
110#define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
112 uint64_t /*Addr*/, \
113 const MCDisassembler *Decoder) { \
114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
115 return addOperand(Inst, DAsm->DecoderName(Imm)); \
116 }
117
118// Decoder for registers, decode directly using RegClassID. Imm(8-bit) is
119// number of register. Used by VGPR only and AGPR only operands.
120#define DECODE_OPERAND_REG_8(RegClass) \
121 static DecodeStatus Decode##RegClass##RegisterClass( \
122 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
123 const MCDisassembler *Decoder) { \
124 assert(Imm < (1 << 8) && "8-bit encoding"); \
125 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
126 return addOperand( \
127 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
128 }
129
130#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \
131 ImmWidth) \
132 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \
133 const MCDisassembler *Decoder) { \
134 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
135 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
136 return addOperand(Inst, \
137 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \
138 MandatoryLiteral, ImmWidth)); \
139 }
140
141// Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to
142// get register class. Used by SGPR only operands.
143#define DECODE_OPERAND_REG_7(RegClass, OpWidth) \
144 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
145
146// Decoder for registers. Imm(10-bit): Imm{7-0} is number of register,
147// Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC).
148// Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp.
149// Used by AV_ register classes (AGPR or VGPR only register operands).
150#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \
151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \
152 Imm | AMDGPU::EncValues::IS_VGPR, false, 0)
153
154// Decoder for Src(9-bit encoding) registers only.
155#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \
156 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
157
158// Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set
159// Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers
160// only.
161#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \
162 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
163
164// Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding
165// Imm{9} is acc, registers only.
166#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \
167 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
168
169// Decoder for RegisterOperands using 9-bit Src encoding. Operand can be
170// register from RegClass or immediate. Registers that don't belong to RegClass
171// will be decoded and InstPrinter will report warning. Immediate will be
172// decoded into constant of size ImmWidth, should match width of immediate used
173// by OperandType (important for floating point types).
174#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \
175 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \
176 false, ImmWidth)
177
178// Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc)
179// and decode using 'enum10' from decodeSrcOp.
180#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \
181 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \
182 Imm | 512, false, ImmWidth)
183
184#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \
185 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \
186 OpWidth, Imm, true, ImmWidth)
187
188// Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass'
189// when RegisterClass is used as an operand. Most often used for destination
190// operands.
191
193DECODE_OPERAND_REG_8(VGPR_32_Lo128)
196DECODE_OPERAND_REG_8(VReg_128)
197DECODE_OPERAND_REG_8(VReg_256)
198DECODE_OPERAND_REG_8(VReg_288)
199DECODE_OPERAND_REG_8(VReg_352)
200DECODE_OPERAND_REG_8(VReg_384)
201DECODE_OPERAND_REG_8(VReg_512)
202DECODE_OPERAND_REG_8(VReg_1024)
203
204DECODE_OPERAND_REG_7(SReg_32, OPW32)
205DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32)
206DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32)
207DECODE_OPERAND_REG_7(SReg_64, OPW64)
208DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64)
209DECODE_OPERAND_REG_7(SReg_128, OPW128)
210DECODE_OPERAND_REG_7(SReg_256, OPW256)
211DECODE_OPERAND_REG_7(SReg_512, OPW512)
212
215DECODE_OPERAND_REG_8(AReg_128)
216DECODE_OPERAND_REG_8(AReg_256)
217DECODE_OPERAND_REG_8(AReg_512)
218DECODE_OPERAND_REG_8(AReg_1024)
219
220DECODE_OPERAND_REG_AV10(AVDst_128, OPW128)
221DECODE_OPERAND_REG_AV10(AVDst_512, OPW512)
222
223// Decoders for register only source RegisterOperands that use use 9-bit Src
224// encoding: 'decodeOperand_<RegClass>'.
225
226DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32)
227DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64)
228DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128)
229DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256)
230DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32)
231
232DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32)
233
234DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32)
235DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64)
236DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128)
237
238// Decoders for register or immediate RegisterOperands that use 9-bit Src
239// encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'.
240
241DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64)
242DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32)
243DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32)
244DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16)
245DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16)
246DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32)
247DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64)
248DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32)
249DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64)
250DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32)
251DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64)
252DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32)
253DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32)
254
255DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64)
256DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32)
257DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64)
258DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32)
259DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32)
260
261DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16)
264
265static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm,
267 const MCDisassembler *Decoder) {
268 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
269 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
270}
271
272static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm,
274 const MCDisassembler *Decoder) {
275 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
276 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
277}
278
279static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val,
280 uint64_t Addr, const void *Decoder) {
281 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
282 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
283}
284
285static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
286 const MCRegisterInfo *MRI) {
287 if (OpIdx < 0)
288 return false;
289
290 const MCOperand &Op = Inst.getOperand(OpIdx);
291 if (!Op.isReg())
292 return false;
293
294 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
295 auto Reg = Sub ? Sub : Op.getReg();
296 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
297}
298
301 const MCDisassembler *Decoder) {
302 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
303 if (!DAsm->isGFX90A()) {
304 Imm &= 511;
305 } else {
306 // If atomic has both vdata and vdst their register classes are tied.
307 // The bit is decoded along with the vdst, first operand. We need to
308 // change register class to AGPR if vdst was AGPR.
309 // If a DS instruction has both data0 and data1 their register classes
310 // are also tied.
311 unsigned Opc = Inst.getOpcode();
312 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
313 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
314 : AMDGPU::OpName::vdata;
315 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
316 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx);
317 if ((int)Inst.getNumOperands() == DataIdx) {
318 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
319 if (IsAGPROperand(Inst, DstIdx, MRI))
320 Imm |= 512;
321 }
322
324 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
325 if ((int)Inst.getNumOperands() == Data2Idx &&
326 IsAGPROperand(Inst, DataIdx, MRI))
327 Imm |= 512;
328 }
329 }
330 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
331}
332
333static DecodeStatus
335 const MCDisassembler *Decoder) {
336 return decodeOperand_AVLdSt_Any(Inst, Imm,
338}
339
340static DecodeStatus
342 const MCDisassembler *Decoder) {
343 return decodeOperand_AVLdSt_Any(Inst, Imm,
345}
346
347static DecodeStatus
349 const MCDisassembler *Decoder) {
350 return decodeOperand_AVLdSt_Any(Inst, Imm,
352}
353
354static DecodeStatus
356 const MCDisassembler *Decoder) {
357 return decodeOperand_AVLdSt_Any(Inst, Imm,
359}
360
361static DecodeStatus
363 const MCDisassembler *Decoder) {
365 Decoder);
366}
367
368#define DECODE_SDWA(DecName) \
369DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
370
371DECODE_SDWA(Src32)
372DECODE_SDWA(Src16)
373DECODE_SDWA(VopcDst)
374
375#include "AMDGPUGenDisassemblerTables.inc"
376
377//===----------------------------------------------------------------------===//
378//
379//===----------------------------------------------------------------------===//
380
381template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
382 assert(Bytes.size() >= sizeof(T));
383 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
384 Bytes = Bytes.slice(sizeof(T));
385 return Res;
386}
387
389 assert(Bytes.size() >= 12);
390 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>(
391 Bytes.data());
392 Bytes = Bytes.slice(8);
393 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>(
394 Bytes.data());
395 Bytes = Bytes.slice(4);
396 return DecoderUInt128(Lo, Hi);
397}
398
399// The disassembler is greedy, so we need to check FI operand value to
400// not parse a dpp if the correct literal is not set. For dpp16 the
401// autogenerated decoder checks the dpp literal
402static bool isValidDPP8(const MCInst &MI) {
403 using namespace llvm::AMDGPU::DPP;
404 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
405 assert(FiIdx != -1);
406 if ((unsigned)FiIdx >= MI.getNumOperands())
407 return false;
408 unsigned Fi = MI.getOperand(FiIdx).getImm();
409 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
410}
411
413 ArrayRef<uint8_t> Bytes_,
415 raw_ostream &CS) const {
416 bool IsSDWA = false;
417
418 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
419 Bytes = Bytes_.slice(0, MaxInstBytesNum);
420
422 do {
423 // ToDo: better to switch encoding length using some bit predicate
424 // but it is unknown yet, so try all we can
425
426 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
427 // encodings
428 if (isGFX11Plus() && Bytes.size() >= 12 ) {
429 DecoderUInt128 DecW = eat12Bytes(Bytes);
430 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, Address, CS);
432 break;
433 MI = MCInst(); // clear
434 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, Address, CS);
435 if (Res) {
436 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)
438 else if (AMDGPU::isVOPC64DPP(MI.getOpcode()))
439 convertVOPCDPPInst(MI); // Special VOP3 case
440 else {
441 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3);
442 convertVOP3DPPInst(MI); // Regular VOP3 case
443 }
444 break;
445 }
446 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS);
447 if (Res)
448 break;
449 }
450 // Reinitialize Bytes
451 Bytes = Bytes_.slice(0, MaxInstBytesNum);
452
453 if (Bytes.size() >= 8) {
454 const uint64_t QW = eatBytes<uint64_t>(Bytes);
455
456 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) {
457 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS);
458 if (Res) {
459 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
460 == -1)
461 break;
463 break;
464 MI = MCInst(); // clear
465 }
466 }
467
468 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS);
470 break;
471 MI = MCInst(); // clear
472
473 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address, CS);
475 break;
476 MI = MCInst(); // clear
477
478 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS);
479 if (Res) break;
480
481 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address, CS);
482 if (Res) {
483 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
485 break;
486 }
487
488 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS);
489 if (Res) { IsSDWA = true; break; }
490
491 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS);
492 if (Res) { IsSDWA = true; break; }
493
494 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS);
495 if (Res) { IsSDWA = true; break; }
496
497 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) {
498 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS);
499 if (Res)
500 break;
501 }
502
503 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
504 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
505 // table first so we print the correct name.
506 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) {
507 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS);
508 if (Res)
509 break;
510 }
511 }
512
513 // Reinitialize Bytes as DPP64 could have eaten too much
514 Bytes = Bytes_.slice(0, MaxInstBytesNum);
515
516 // Try decode 32-bit instruction
517 if (Bytes.size() < 4) break;
518 const uint32_t DW = eatBytes<uint32_t>(Bytes);
519 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS);
520 if (Res) break;
521
522 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS);
523 if (Res) break;
524
525 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS);
526 if (Res) break;
527
528 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) {
529 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS);
530 if (Res)
531 break;
532 }
533
534 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) {
535 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS);
536 if (Res) break;
537 }
538
539 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS);
540 if (Res) break;
541
542 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address, CS);
543 if (Res) break;
544
545 if (Bytes.size() < 4) break;
546 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
547
548 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) {
549 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS);
550 if (Res)
551 break;
552 }
553
554 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) {
555 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS);
556 if (Res)
557 break;
558 }
559
560 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS);
561 if (Res) break;
562
563 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS);
564 if (Res) break;
565
566 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS);
567 if (Res) break;
568
569 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS);
570 if (Res) break;
571
572 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address, CS);
573 if (Res)
574 break;
575
576 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS);
577 } while (false);
578
579 if (Res && AMDGPU::isMAC(MI.getOpcode())) {
580 // Insert dummy unused src2_modifiers.
582 AMDGPU::OpName::src2_modifiers);
583 }
584
585 if (Res && (MCII->get(MI.getOpcode()).TSFlags &
587 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
588 AMDGPU::OpName::cpol);
589 if (CPolPos != -1) {
590 unsigned CPol =
591 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ?
593 if (MI.getNumOperands() <= (unsigned)CPolPos) {
595 AMDGPU::OpName::cpol);
596 } else if (CPol) {
597 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol);
598 }
599 }
600 }
601
602 if (Res && (MCII->get(MI.getOpcode()).TSFlags &
604 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) {
605 // GFX90A lost TFE, its place is occupied by ACC.
606 int TFEOpIdx =
607 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);
608 if (TFEOpIdx != -1) {
609 auto TFEIter = MI.begin();
610 std::advance(TFEIter, TFEOpIdx);
611 MI.insert(TFEIter, MCOperand::createImm(0));
612 }
613 }
614
615 if (Res && (MCII->get(MI.getOpcode()).TSFlags &
617 int SWZOpIdx =
618 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz);
619 if (SWZOpIdx != -1) {
620 auto SWZIter = MI.begin();
621 std::advance(SWZIter, SWZOpIdx);
622 MI.insert(SWZIter, MCOperand::createImm(0));
623 }
624 }
625
626 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
627 int VAddr0Idx =
628 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
629 int RsrcIdx =
630 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
631 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
632 if (VAddr0Idx >= 0 && NSAArgs > 0) {
633 unsigned NSAWords = (NSAArgs + 3) / 4;
634 if (Bytes.size() < 4 * NSAWords) {
636 } else {
637 for (unsigned i = 0; i < NSAArgs; ++i) {
638 const unsigned VAddrIdx = VAddr0Idx + 1 + i;
639 auto VAddrRCID =
640 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass;
641 MI.insert(MI.begin() + VAddrIdx,
642 createRegOperand(VAddrRCID, Bytes[i]));
643 }
644 Bytes = Bytes.slice(4 * NSAWords);
645 }
646 }
647
648 if (Res)
649 Res = convertMIMGInst(MI);
650 }
651
652 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP))
653 Res = convertEXPInst(MI);
654
655 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP))
656 Res = convertVINTERPInst(MI);
657
658 if (Res && IsSDWA)
659 Res = convertSDWAInst(MI);
660
661 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
662 AMDGPU::OpName::vdst_in);
663 if (VDstIn_Idx != -1) {
664 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
666 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
667 !MI.getOperand(VDstIn_Idx).isReg() ||
668 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
669 if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
670 MI.erase(&MI.getOperand(VDstIn_Idx));
672 MCOperand::createReg(MI.getOperand(Tied).getReg()),
673 AMDGPU::OpName::vdst_in);
674 }
675 }
676
677 int ImmLitIdx =
678 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);
679 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK;
680 if (Res && ImmLitIdx != -1 && !IsSOPK)
681 Res = convertFMAanyK(MI, ImmLitIdx);
682
683 // if the opcode was not recognized we'll assume a Size of 4 bytes
684 // (unless there are fewer bytes left)
685 Size = Res ? (MaxInstBytesNum - Bytes.size())
686 : std::min((size_t)4, Bytes_.size());
687 return Res;
688}
689
691 if (STI.hasFeature(AMDGPU::FeatureGFX11)) {
692 // The MCInst still has these fields even though they are no longer encoded
693 // in the GFX11 instruction.
694 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm);
695 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr);
696 }
698}
699
701 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 ||
702 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 ||
703 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 ||
704 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) {
705 // The MCInst has this field that is not directly encoded in the
706 // instruction.
707 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel);
708 }
710}
711
713 if (STI.hasFeature(AMDGPU::FeatureGFX9) ||
714 STI.hasFeature(AMDGPU::FeatureGFX10)) {
715 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst))
716 // VOPC - insert clamp
717 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
718 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
719 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
720 if (SDst != -1) {
721 // VOPC - insert VCC register as sdst
723 AMDGPU::OpName::sdst);
724 } else {
725 // VOP1/2 - insert omod if present in instruction
726 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
727 }
728 }
730}
731
733 unsigned OpSel = 0;
734 unsigned OpSelHi = 0;
735 unsigned NegLo = 0;
736 unsigned NegHi = 0;
737};
738
739// Reconstruct values of VOP3/VOP3P operands such as op_sel.
740// Note that these values do not affect disassembler output,
741// so this is only necessary for consistency with src_modifiers.
743 bool IsVOP3P = false) {
744 VOPModifiers Modifiers;
745 unsigned Opc = MI.getOpcode();
746 const int ModOps[] = {AMDGPU::OpName::src0_modifiers,
747 AMDGPU::OpName::src1_modifiers,
748 AMDGPU::OpName::src2_modifiers};
749 for (int J = 0; J < 3; ++J) {
750 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
751 if (OpIdx == -1)
752 continue;
753
754 unsigned Val = MI.getOperand(OpIdx).getImm();
755
756 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J;
757 if (IsVOP3P) {
758 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J;
759 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J;
760 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J;
761 } else if (J == 0) {
762 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3;
763 }
764 }
765
766 return Modifiers;
767}
768
769// MAC opcodes have special old and src2 operands.
770// src2 is tied to dst, while old is not tied (but assumed to be).
772 constexpr int DST_IDX = 0;
773 auto Opcode = MI.getOpcode();
774 const auto &Desc = MCII->get(Opcode);
775 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old);
776
777 if (OldIdx != -1 && Desc.getOperandConstraint(
778 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) {
779 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2));
780 assert(Desc.getOperandConstraint(
781 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2),
783 (void)DST_IDX;
784 return true;
785 }
786
787 return false;
788}
789
790// Create dummy old operand and insert dummy unused src2_modifiers
792 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands());
793 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old);
795 AMDGPU::OpName::src2_modifiers);
796}
797
798// We must check FI == literal to reject not genuine dpp8 insts, and we must
799// first add optional MI operands to check FI
801 unsigned Opc = MI.getOpcode();
802 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) {
804 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) ||
805 AMDGPU::isVOPC64DPP(Opc)) {
807 } else {
808 if (isMacDPP(MI))
810
811 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
812 if (MI.getNumOperands() < DescNumOps &&
813 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
814 auto Mods = collectVOPModifiers(MI);
816 AMDGPU::OpName::op_sel);
817 } else {
818 // Insert dummy unused src modifiers.
819 if (MI.getNumOperands() < DescNumOps &&
820 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
822 AMDGPU::OpName::src0_modifiers);
823
824 if (MI.getNumOperands() < DescNumOps &&
825 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
827 AMDGPU::OpName::src1_modifiers);
828 }
829 }
831}
832
834 if (isMacDPP(MI))
836
837 unsigned Opc = MI.getOpcode();
838 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
839 if (MI.getNumOperands() < DescNumOps &&
840 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
841 auto Mods = collectVOPModifiers(MI);
843 AMDGPU::OpName::op_sel);
844 }
846}
847
848// Note that before gfx10, the MIMG encoding provided no information about
849// VADDR size. Consequently, decoded instructions always show address as if it
850// has 1 dword, which could be not really so.
852
853 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
854 AMDGPU::OpName::vdst);
855
856 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
857 AMDGPU::OpName::vdata);
858 int VAddr0Idx =
859 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
860 int RsrcIdx =
861 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
862 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
863 AMDGPU::OpName::dmask);
864
865 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
866 AMDGPU::OpName::tfe);
867 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
868 AMDGPU::OpName::d16);
869
870 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
871 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
873
874 assert(VDataIdx != -1);
875 if (BaseOpcode->BVH) {
876 // Add A16 operand for intersect_ray instructions
877 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::a16))
880 }
881
882 bool IsAtomic = (VDstIdx != -1);
883 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
884 bool IsNSA = false;
885 bool IsPartialNSA = false;
886 unsigned AddrSize = Info->VAddrDwords;
887
888 if (isGFX10Plus()) {
889 unsigned DimIdx =
890 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
891 int A16Idx =
892 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16);
893 const AMDGPU::MIMGDimInfo *Dim =
894 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
895 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm());
896
897 AddrSize =
898 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI));
899
900 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA ||
901 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA;
902 if (!IsNSA) {
903 if (AddrSize > 12)
904 AddrSize = 16;
905 } else {
906 if (AddrSize > Info->VAddrDwords) {
907 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) {
908 // The NSA encoding does not contain enough operands for the
909 // combination of base opcode / dimension. Should this be an error?
911 }
912 IsPartialNSA = true;
913 }
914 }
915 }
916
917 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
918 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1);
919
920 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
921 if (D16 && AMDGPU::hasPackedD16(STI)) {
922 DstSize = (DstSize + 1) / 2;
923 }
924
925 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm())
926 DstSize += 1;
927
928 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
930
931 int NewOpcode =
932 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
933 if (NewOpcode == -1)
935
936 // Widen the register to the correct number of enabled channels.
937 unsigned NewVdata = AMDGPU::NoRegister;
938 if (DstSize != Info->VDataDwords) {
939 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
940
941 // Get first subregister of VData
942 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
943 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
944 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
945
946 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
947 &MRI.getRegClass(DataRCID));
948 if (NewVdata == AMDGPU::NoRegister) {
949 // It's possible to encode this such that the low register + enabled
950 // components exceeds the register count.
952 }
953 }
954
955 // If not using NSA on GFX10+, widen vaddr0 address register to correct size.
956 // If using partial NSA on GFX11+ widen last address register.
957 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx;
958 unsigned NewVAddrSA = AMDGPU::NoRegister;
959 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) &&
960 AddrSize != Info->VAddrDwords) {
961 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg();
962 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
963 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
964
965 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;
966 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0,
967 &MRI.getRegClass(AddrRCID));
968 if (!NewVAddrSA)
970 }
971
972 MI.setOpcode(NewOpcode);
973
974 if (NewVdata != AMDGPU::NoRegister) {
975 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
976
977 if (IsAtomic) {
978 // Atomic operations have an additional operand (a copy of data)
979 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
980 }
981 }
982
983 if (NewVAddrSA) {
984 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA);
985 } else if (IsNSA) {
986 assert(AddrSize <= Info->VAddrDwords);
987 MI.erase(MI.begin() + VAddr0Idx + AddrSize,
988 MI.begin() + VAddr0Idx + Info->VAddrDwords);
989 }
990
992}
993
994// Opsel and neg bits are used in src_modifiers and standalone operands. Autogen
995// decoder only adds to src_modifiers, so manually add the bits to the other
996// operands.
998 unsigned Opc = MI.getOpcode();
999 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1000 auto Mods = collectVOPModifiers(MI, true);
1001
1002 if (MI.getNumOperands() < DescNumOps &&
1003 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in))
1004 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in);
1005
1006 if (MI.getNumOperands() < DescNumOps &&
1007 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel))
1009 AMDGPU::OpName::op_sel);
1010 if (MI.getNumOperands() < DescNumOps &&
1011 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi))
1013 AMDGPU::OpName::op_sel_hi);
1014 if (MI.getNumOperands() < DescNumOps &&
1015 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo))
1017 AMDGPU::OpName::neg_lo);
1018 if (MI.getNumOperands() < DescNumOps &&
1019 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi))
1021 AMDGPU::OpName::neg_hi);
1022
1024}
1025
1026// Create dummy old operand and insert optional operands
1028 unsigned Opc = MI.getOpcode();
1029 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1030
1031 if (MI.getNumOperands() < DescNumOps &&
1032 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old))
1033 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old);
1034
1035 if (MI.getNumOperands() < DescNumOps &&
1036 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
1038 AMDGPU::OpName::src0_modifiers);
1039
1040 if (MI.getNumOperands() < DescNumOps &&
1041 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
1043 AMDGPU::OpName::src1_modifiers);
1045}
1046
1048 int ImmLitIdx) const {
1049 assert(HasLiteral && "Should have decoded a literal");
1050 const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
1051 unsigned DescNumOps = Desc.getNumOperands();
1053 AMDGPU::OpName::immDeferred);
1054 assert(DescNumOps == MI.getNumOperands());
1055 for (unsigned I = 0; I < DescNumOps; ++I) {
1056 auto &Op = MI.getOperand(I);
1057 auto OpType = Desc.operands()[I].OperandType;
1058 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED ||
1060 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST &&
1061 IsDeferredOp)
1062 Op.setImm(Literal);
1063 }
1065}
1066
1067const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
1068 return getContext().getRegisterInfo()->
1069 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
1070}
1071
1072inline
1074 const Twine& ErrMsg) const {
1075 *CommentStream << "Error: " + ErrMsg;
1076
1077 // ToDo: add support for error operands to MCInst.h
1078 // return MCOperand::createError(V);
1079 return MCOperand();
1080}
1081
1082inline
1085}
1086
1087inline
1089 unsigned Val) const {
1090 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
1091 if (Val >= RegCl.getNumRegs())
1092 return errOperand(Val, Twine(getRegClassName(RegClassID)) +
1093 ": unknown register " + Twine(Val));
1094 return createRegOperand(RegCl.getRegister(Val));
1095}
1096
1097inline
1099 unsigned Val) const {
1100 // ToDo: SI/CI have 104 SGPRs, VI - 102
1101 // Valery: here we accepting as much as we can, let assembler sort it out
1102 int shift = 0;
1103 switch (SRegClassID) {
1104 case AMDGPU::SGPR_32RegClassID:
1105 case AMDGPU::TTMP_32RegClassID:
1106 break;
1107 case AMDGPU::SGPR_64RegClassID:
1108 case AMDGPU::TTMP_64RegClassID:
1109 shift = 1;
1110 break;
1111 case AMDGPU::SGPR_128RegClassID:
1112 case AMDGPU::TTMP_128RegClassID:
1113 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
1114 // this bundle?
1115 case AMDGPU::SGPR_256RegClassID:
1116 case AMDGPU::TTMP_256RegClassID:
1117 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
1118 // this bundle?
1119 case AMDGPU::SGPR_288RegClassID:
1120 case AMDGPU::TTMP_288RegClassID:
1121 case AMDGPU::SGPR_320RegClassID:
1122 case AMDGPU::TTMP_320RegClassID:
1123 case AMDGPU::SGPR_352RegClassID:
1124 case AMDGPU::TTMP_352RegClassID:
1125 case AMDGPU::SGPR_384RegClassID:
1126 case AMDGPU::TTMP_384RegClassID:
1127 case AMDGPU::SGPR_512RegClassID:
1128 case AMDGPU::TTMP_512RegClassID:
1129 shift = 2;
1130 break;
1131 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
1132 // this bundle?
1133 default:
1134 llvm_unreachable("unhandled register class");
1135 }
1136
1137 if (Val % (1 << shift)) {
1138 *CommentStream << "Warning: " << getRegClassName(SRegClassID)
1139 << ": scalar reg isn't aligned " << Val;
1140 }
1141
1142 return createRegOperand(SRegClassID, Val >> shift);
1143}
1144
1145// Decode Literals for insts which always have a literal in the encoding
1148 if (HasLiteral) {
1149 assert(
1151 "Should only decode multiple kimm with VOPD, check VSrc operand types");
1152 if (Literal != Val)
1153 return errOperand(Val, "More than one unique literal is illegal");
1154 }
1155 HasLiteral = true;
1156 Literal = Val;
1157 return MCOperand::createImm(Literal);
1158}
1159
1161 // For now all literal constants are supposed to be unsigned integer
1162 // ToDo: deal with signed/unsigned 64-bit integer constants
1163 // ToDo: deal with float/double constants
1164 if (!HasLiteral) {
1165 if (Bytes.size() < 4) {
1166 return errOperand(0, "cannot read literal, inst bytes left " +
1167 Twine(Bytes.size()));
1168 }
1169 HasLiteral = true;
1170 Literal = eatBytes<uint32_t>(Bytes);
1171 }
1172 return MCOperand::createImm(Literal);
1173}
1174
1176 using namespace AMDGPU::EncValues;
1177
1178 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
1179 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
1180 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
1181 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
1182 // Cast prevents negative overflow.
1183}
1184
1185static int64_t getInlineImmVal32(unsigned Imm) {
1186 switch (Imm) {
1187 case 240:
1188 return llvm::bit_cast<uint32_t>(0.5f);
1189 case 241:
1190 return llvm::bit_cast<uint32_t>(-0.5f);
1191 case 242:
1192 return llvm::bit_cast<uint32_t>(1.0f);
1193 case 243:
1194 return llvm::bit_cast<uint32_t>(-1.0f);
1195 case 244:
1196 return llvm::bit_cast<uint32_t>(2.0f);
1197 case 245:
1198 return llvm::bit_cast<uint32_t>(-2.0f);
1199 case 246:
1200 return llvm::bit_cast<uint32_t>(4.0f);
1201 case 247:
1202 return llvm::bit_cast<uint32_t>(-4.0f);
1203 case 248: // 1 / (2 * PI)
1204 return 0x3e22f983;
1205 default:
1206 llvm_unreachable("invalid fp inline imm");
1207 }
1208}
1209
1210static int64_t getInlineImmVal64(unsigned Imm) {
1211 switch (Imm) {
1212 case 240:
1213 return llvm::bit_cast<uint64_t>(0.5);
1214 case 241:
1215 return llvm::bit_cast<uint64_t>(-0.5);
1216 case 242:
1217 return llvm::bit_cast<uint64_t>(1.0);
1218 case 243:
1219 return llvm::bit_cast<uint64_t>(-1.0);
1220 case 244:
1221 return llvm::bit_cast<uint64_t>(2.0);
1222 case 245:
1223 return llvm::bit_cast<uint64_t>(-2.0);
1224 case 246:
1225 return llvm::bit_cast<uint64_t>(4.0);
1226 case 247:
1227 return llvm::bit_cast<uint64_t>(-4.0);
1228 case 248: // 1 / (2 * PI)
1229 return 0x3fc45f306dc9c882;
1230 default:
1231 llvm_unreachable("invalid fp inline imm");
1232 }
1233}
1234
1235static int64_t getInlineImmVal16(unsigned Imm) {
1236 switch (Imm) {
1237 case 240:
1238 return 0x3800;
1239 case 241:
1240 return 0xB800;
1241 case 242:
1242 return 0x3C00;
1243 case 243:
1244 return 0xBC00;
1245 case 244:
1246 return 0x4000;
1247 case 245:
1248 return 0xC000;
1249 case 246:
1250 return 0x4400;
1251 case 247:
1252 return 0xC400;
1253 case 248: // 1 / (2 * PI)
1254 return 0x3118;
1255 default:
1256 llvm_unreachable("invalid fp inline imm");
1257 }
1258}
1259
1260MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) {
1263
1264 // ToDo: case 248: 1/(2*PI) - is allowed only on VI
1265 // ImmWidth 0 is a default case where operand should not allow immediates.
1266 // Imm value is still decoded into 32 bit immediate operand, inst printer will
1267 // use it to print verbose error message.
1268 switch (ImmWidth) {
1269 case 0:
1270 case 32:
1272 case 64:
1274 case 16:
1276 default:
1277 llvm_unreachable("implement me");
1278 }
1279}
1280
1282 using namespace AMDGPU;
1283
1284 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
1285 switch (Width) {
1286 default: // fall
1287 case OPW32:
1288 case OPW16:
1289 case OPWV216:
1290 return VGPR_32RegClassID;
1291 case OPW64:
1292 case OPWV232: return VReg_64RegClassID;
1293 case OPW96: return VReg_96RegClassID;
1294 case OPW128: return VReg_128RegClassID;
1295 case OPW160: return VReg_160RegClassID;
1296 case OPW256: return VReg_256RegClassID;
1297 case OPW288: return VReg_288RegClassID;
1298 case OPW320: return VReg_320RegClassID;
1299 case OPW352: return VReg_352RegClassID;
1300 case OPW384: return VReg_384RegClassID;
1301 case OPW512: return VReg_512RegClassID;
1302 case OPW1024: return VReg_1024RegClassID;
1303 }
1304}
1305
1307 using namespace AMDGPU;
1308
1309 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
1310 switch (Width) {
1311 default: // fall
1312 case OPW32:
1313 case OPW16:
1314 case OPWV216:
1315 return AGPR_32RegClassID;
1316 case OPW64:
1317 case OPWV232: return AReg_64RegClassID;
1318 case OPW96: return AReg_96RegClassID;
1319 case OPW128: return AReg_128RegClassID;
1320 case OPW160: return AReg_160RegClassID;
1321 case OPW256: return AReg_256RegClassID;
1322 case OPW288: return AReg_288RegClassID;
1323 case OPW320: return AReg_320RegClassID;
1324 case OPW352: return AReg_352RegClassID;
1325 case OPW384: return AReg_384RegClassID;
1326 case OPW512: return AReg_512RegClassID;
1327 case OPW1024: return AReg_1024RegClassID;
1328 }
1329}
1330
1331
1333 using namespace AMDGPU;
1334
1335 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
1336 switch (Width) {
1337 default: // fall
1338 case OPW32:
1339 case OPW16:
1340 case OPWV216:
1341 return SGPR_32RegClassID;
1342 case OPW64:
1343 case OPWV232: return SGPR_64RegClassID;
1344 case OPW96: return SGPR_96RegClassID;
1345 case OPW128: return SGPR_128RegClassID;
1346 case OPW160: return SGPR_160RegClassID;
1347 case OPW256: return SGPR_256RegClassID;
1348 case OPW288: return SGPR_288RegClassID;
1349 case OPW320: return SGPR_320RegClassID;
1350 case OPW352: return SGPR_352RegClassID;
1351 case OPW384: return SGPR_384RegClassID;
1352 case OPW512: return SGPR_512RegClassID;
1353 }
1354}
1355
1357 using namespace AMDGPU;
1358
1359 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
1360 switch (Width) {
1361 default: // fall
1362 case OPW32:
1363 case OPW16:
1364 case OPWV216:
1365 return TTMP_32RegClassID;
1366 case OPW64:
1367 case OPWV232: return TTMP_64RegClassID;
1368 case OPW128: return TTMP_128RegClassID;
1369 case OPW256: return TTMP_256RegClassID;
1370 case OPW288: return TTMP_288RegClassID;
1371 case OPW320: return TTMP_320RegClassID;
1372 case OPW352: return TTMP_352RegClassID;
1373 case OPW384: return TTMP_384RegClassID;
1374 case OPW512: return TTMP_512RegClassID;
1375 }
1376}
1377
1378int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1379 using namespace AMDGPU::EncValues;
1380
1381 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1382 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1383
1384 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1385}
1386
1388 bool MandatoryLiteral,
1389 unsigned ImmWidth) const {
1390 using namespace AMDGPU::EncValues;
1391
1392 assert(Val < 1024); // enum10
1393
1394 bool IsAGPR = Val & 512;
1395 Val &= 511;
1396
1397 if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1398 return createRegOperand(IsAGPR ? getAgprClassId(Width)
1399 : getVgprClassId(Width), Val - VGPR_MIN);
1400 }
1401 if (Val <= SGPR_MAX) {
1402 // "SGPR_MIN <= Val" is always true and causes compilation warning.
1403 static_assert(SGPR_MIN == 0);
1404 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1405 }
1406
1407 int TTmpIdx = getTTmpIdx(Val);
1408 if (TTmpIdx >= 0) {
1409 return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1410 }
1411
1412 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1413 return decodeIntImmed(Val);
1414
1415 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1416 return decodeFPImmed(ImmWidth, Val);
1417
1418 if (Val == LITERAL_CONST) {
1419 if (MandatoryLiteral)
1420 // Keep a sentinel value for deferred setting
1421 return MCOperand::createImm(LITERAL_CONST);
1422 else
1423 return decodeLiteralConstant();
1424 }
1425
1426 switch (Width) {
1427 case OPW32:
1428 case OPW16:
1429 case OPWV216:
1430 return decodeSpecialReg32(Val);
1431 case OPW64:
1432 case OPWV232:
1433 return decodeSpecialReg64(Val);
1434 default:
1435 llvm_unreachable("unexpected immediate type");
1436 }
1437}
1438
1439// Bit 0 of DstY isn't stored in the instruction, because it's always the
1440// opposite of bit 0 of DstX.
1442 unsigned Val) const {
1443 int VDstXInd =
1444 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX);
1445 assert(VDstXInd != -1);
1446 assert(Inst.getOperand(VDstXInd).isReg());
1447 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg());
1448 Val |= ~XDstReg & 1;
1450 return createRegOperand(getVgprClassId(Width), Val);
1451}
1452
1454 using namespace AMDGPU;
1455
1456 switch (Val) {
1457 // clang-format off
1458 case 102: return createRegOperand(FLAT_SCR_LO);
1459 case 103: return createRegOperand(FLAT_SCR_HI);
1460 case 104: return createRegOperand(XNACK_MASK_LO);
1461 case 105: return createRegOperand(XNACK_MASK_HI);
1462 case 106: return createRegOperand(VCC_LO);
1463 case 107: return createRegOperand(VCC_HI);
1464 case 108: return createRegOperand(TBA_LO);
1465 case 109: return createRegOperand(TBA_HI);
1466 case 110: return createRegOperand(TMA_LO);
1467 case 111: return createRegOperand(TMA_HI);
1468 case 124:
1469 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0);
1470 case 125:
1471 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL);
1472 case 126: return createRegOperand(EXEC_LO);
1473 case 127: return createRegOperand(EXEC_HI);
1474 case 235: return createRegOperand(SRC_SHARED_BASE_LO);
1475 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO);
1476 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO);
1477 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO);
1478 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1479 case 251: return createRegOperand(SRC_VCCZ);
1480 case 252: return createRegOperand(SRC_EXECZ);
1481 case 253: return createRegOperand(SRC_SCC);
1482 case 254: return createRegOperand(LDS_DIRECT);
1483 default: break;
1484 // clang-format on
1485 }
1486 return errOperand(Val, "unknown operand encoding " + Twine(Val));
1487}
1488
1490 using namespace AMDGPU;
1491
1492 switch (Val) {
1493 case 102: return createRegOperand(FLAT_SCR);
1494 case 104: return createRegOperand(XNACK_MASK);
1495 case 106: return createRegOperand(VCC);
1496 case 108: return createRegOperand(TBA);
1497 case 110: return createRegOperand(TMA);
1498 case 124:
1499 if (isGFX11Plus())
1500 return createRegOperand(SGPR_NULL);
1501 break;
1502 case 125:
1503 if (!isGFX11Plus())
1504 return createRegOperand(SGPR_NULL);
1505 break;
1506 case 126: return createRegOperand(EXEC);
1507 case 235: return createRegOperand(SRC_SHARED_BASE);
1508 case 236: return createRegOperand(SRC_SHARED_LIMIT);
1509 case 237: return createRegOperand(SRC_PRIVATE_BASE);
1510 case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1511 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1512 case 251: return createRegOperand(SRC_VCCZ);
1513 case 252: return createRegOperand(SRC_EXECZ);
1514 case 253: return createRegOperand(SRC_SCC);
1515 default: break;
1516 }
1517 return errOperand(Val, "unknown operand encoding " + Twine(Val));
1518}
1519
1521 const unsigned Val,
1522 unsigned ImmWidth) const {
1523 using namespace AMDGPU::SDWA;
1524 using namespace AMDGPU::EncValues;
1525
1526 if (STI.hasFeature(AMDGPU::FeatureGFX9) ||
1527 STI.hasFeature(AMDGPU::FeatureGFX10)) {
1528 // XXX: cast to int is needed to avoid stupid warning:
1529 // compare with unsigned is always true
1530 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1531 Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1532 return createRegOperand(getVgprClassId(Width),
1533 Val - SDWA9EncValues::SRC_VGPR_MIN);
1534 }
1535 if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1536 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1537 : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1538 return createSRegOperand(getSgprClassId(Width),
1539 Val - SDWA9EncValues::SRC_SGPR_MIN);
1540 }
1541 if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1542 Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1543 return createSRegOperand(getTtmpClassId(Width),
1544 Val - SDWA9EncValues::SRC_TTMP_MIN);
1545 }
1546
1547 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1548
1549 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1550 return decodeIntImmed(SVal);
1551
1552 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1553 return decodeFPImmed(ImmWidth, SVal);
1554
1555 return decodeSpecialReg32(SVal);
1556 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) {
1557 return createRegOperand(getVgprClassId(Width), Val);
1558 }
1559 llvm_unreachable("unsupported target");
1560}
1561
1563 return decodeSDWASrc(OPW16, Val, 16);
1564}
1565
1567 return decodeSDWASrc(OPW32, Val, 32);
1568}
1569
1571 using namespace AMDGPU::SDWA;
1572
1573 assert((STI.hasFeature(AMDGPU::FeatureGFX9) ||
1574 STI.hasFeature(AMDGPU::FeatureGFX10)) &&
1575 "SDWAVopcDst should be present only on GFX9+");
1576
1577 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64);
1578
1579 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1580 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1581
1582 int TTmpIdx = getTTmpIdx(Val);
1583 if (TTmpIdx >= 0) {
1584 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1585 return createSRegOperand(TTmpClsId, TTmpIdx);
1586 } else if (Val > SGPR_MAX) {
1587 return IsWave64 ? decodeSpecialReg64(Val)
1588 : decodeSpecialReg32(Val);
1589 } else {
1590 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1591 }
1592 } else {
1593 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1594 }
1595}
1596
1598 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64)
1599 ? decodeSrcOp(OPW64, Val)
1600 : decodeSrcOp(OPW32, Val);
1601}
1602
1604 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
1605}
1606
1608
1610 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
1611}
1612
1614
1616
1618 return AMDGPU::isGFX10Plus(STI);
1619}
1620
1622 return STI.hasFeature(AMDGPU::FeatureGFX11);
1623}
1624
1626 return AMDGPU::isGFX11Plus(STI);
1627}
1628
1629
1631 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
1632}
1633
1634//===----------------------------------------------------------------------===//
1635// AMDGPU specific symbol handling
1636//===----------------------------------------------------------------------===//
1637#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1638 do { \
1639 KdStream << Indent << DIRECTIVE " " \
1640 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1641 } while (0)
1642
1643// NOLINTNEXTLINE(readability-identifier-naming)
1645 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1646 using namespace amdhsa;
1647 StringRef Indent = "\t";
1648
1649 // We cannot accurately backward compute #VGPRs used from
1650 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same
1651 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we
1652 // simply calculate the inverse of what the assembler does.
1653
1654 uint32_t GranulatedWorkitemVGPRCount =
1655 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >>
1656 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT;
1657
1658 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) *
1660
1661 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n';
1662
1663 // We cannot backward compute values used to calculate
1664 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following
1665 // directives can't be computed:
1666 // .amdhsa_reserve_vcc
1667 // .amdhsa_reserve_flat_scratch
1668 // .amdhsa_reserve_xnack_mask
1669 // They take their respective default values if not specified in the assembly.
1670 //
1671 // GRANULATED_WAVEFRONT_SGPR_COUNT
1672 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK)
1673 //
1674 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR
1675 // are set to 0. So while disassembling we consider that:
1676 //
1677 // GRANULATED_WAVEFRONT_SGPR_COUNT
1678 // = f(NEXT_FREE_SGPR + 0 + 0 + 0)
1679 //
1680 // The disassembler cannot recover the original values of those 3 directives.
1681
1682 uint32_t GranulatedWavefrontSGPRCount =
1683 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
1684 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
1685
1686 if (isGFX10Plus() && GranulatedWavefrontSGPRCount)
1687 return MCDisassembler::Fail;
1688
1689 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1691
1692 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n';
1694 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n';
1695 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n';
1696 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n";
1697
1698 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1699 return MCDisassembler::Fail;
1700
1701 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32",
1702 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1703 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64",
1704 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1705 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32",
1706 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1707 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64",
1708 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1709
1710 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1711 return MCDisassembler::Fail;
1712
1713 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1714
1715 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1716 return MCDisassembler::Fail;
1717
1718 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1719
1720 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1721 return MCDisassembler::Fail;
1722
1723 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1724 return MCDisassembler::Fail;
1725
1726 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1727
1728 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1729 return MCDisassembler::Fail;
1730
1731 if (isGFX10Plus()) {
1732 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
1733 COMPUTE_PGM_RSRC1_WGP_MODE);
1734 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1735 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1736 }
1738}
1739
1740// NOLINTNEXTLINE(readability-identifier-naming)
1742 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1743 using namespace amdhsa;
1744 StringRef Indent = "\t";
1746 PRINT_DIRECTIVE(".amdhsa_enable_private_segment",
1747 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1748 else
1749 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset",
1750 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1751 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x",
1752 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1753 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y",
1754 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1755 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z",
1756 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1757 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info",
1758 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1759 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id",
1760 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1761
1762 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1763 return MCDisassembler::Fail;
1764
1765 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1766 return MCDisassembler::Fail;
1767
1768 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1769 return MCDisassembler::Fail;
1770
1772 ".amdhsa_exception_fp_ieee_invalid_op",
1773 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1774 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src",
1775 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1777 ".amdhsa_exception_fp_ieee_div_zero",
1778 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1779 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow",
1780 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1781 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow",
1782 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1783 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact",
1784 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1785 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero",
1786 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1787
1788 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1789 return MCDisassembler::Fail;
1790
1792}
1793
1794#undef PRINT_DIRECTIVE
1795
1799 raw_string_ostream &KdStream) const {
1800#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1801 do { \
1802 KdStream << Indent << DIRECTIVE " " \
1803 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1804 } while (0)
1805
1806 uint16_t TwoByteBuffer = 0;
1807 uint32_t FourByteBuffer = 0;
1808
1809 StringRef ReservedBytes;
1810 StringRef Indent = "\t";
1811
1812 assert(Bytes.size() == 64);
1813 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8);
1814
1815 switch (Cursor.tell()) {
1817 FourByteBuffer = DE.getU32(Cursor);
1818 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer
1819 << '\n';
1821
1823 FourByteBuffer = DE.getU32(Cursor);
1824 KdStream << Indent << ".amdhsa_private_segment_fixed_size "
1825 << FourByteBuffer << '\n';
1827
1829 FourByteBuffer = DE.getU32(Cursor);
1830 KdStream << Indent << ".amdhsa_kernarg_size "
1831 << FourByteBuffer << '\n';
1833
1835 // 4 reserved bytes, must be 0.
1836 ReservedBytes = DE.getBytes(Cursor, 4);
1837 for (int I = 0; I < 4; ++I) {
1838 if (ReservedBytes[I] != 0) {
1839 return MCDisassembler::Fail;
1840 }
1841 }
1843
1845 // KERNEL_CODE_ENTRY_BYTE_OFFSET
1846 // So far no directive controls this for Code Object V3, so simply skip for
1847 // disassembly.
1848 DE.skip(Cursor, 8);
1850
1852 // 20 reserved bytes, must be 0.
1853 ReservedBytes = DE.getBytes(Cursor, 20);
1854 for (int I = 0; I < 20; ++I) {
1855 if (ReservedBytes[I] != 0) {
1856 return MCDisassembler::Fail;
1857 }
1858 }
1860
1862 // COMPUTE_PGM_RSRC3
1863 // - Only set for GFX10, GFX6-9 have this to be 0.
1864 // - Currently no directives directly control this.
1865 FourByteBuffer = DE.getU32(Cursor);
1866 if (!isGFX10Plus() && FourByteBuffer) {
1867 return MCDisassembler::Fail;
1868 }
1870
1872 FourByteBuffer = DE.getU32(Cursor);
1873 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) ==
1875 return MCDisassembler::Fail;
1876 }
1878
1880 FourByteBuffer = DE.getU32(Cursor);
1881 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) ==
1883 return MCDisassembler::Fail;
1884 }
1886
1888 using namespace amdhsa;
1889 TwoByteBuffer = DE.getU16(Cursor);
1890
1892 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer",
1893 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
1894 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr",
1895 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
1896 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr",
1897 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
1898 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr",
1899 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
1900 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id",
1901 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
1903 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init",
1904 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
1905 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size",
1906 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
1907
1908 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
1909 return MCDisassembler::Fail;
1910
1911 // Reserved for GFX9
1912 if (isGFX9() &&
1913 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
1914 return MCDisassembler::Fail;
1915 } else if (isGFX10Plus()) {
1916 PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
1917 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
1918 }
1919
1921 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack",
1922 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
1923
1924 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
1925 return MCDisassembler::Fail;
1926
1928
1930 // 6 bytes from here are reserved, must be 0.
1931 ReservedBytes = DE.getBytes(Cursor, 6);
1932 for (int I = 0; I < 6; ++I) {
1933 if (ReservedBytes[I] != 0)
1934 return MCDisassembler::Fail;
1935 }
1937
1938 default:
1939 llvm_unreachable("Unhandled index. Case statements cover everything.");
1940 return MCDisassembler::Fail;
1941 }
1942#undef PRINT_DIRECTIVE
1943}
1944
1946 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const {
1947 // CP microcode requires the kernel descriptor to be 64 aligned.
1948 if (Bytes.size() != 64 || KdAddress % 64 != 0)
1949 return MCDisassembler::Fail;
1950
1951 std::string Kd;
1952 raw_string_ostream KdStream(Kd);
1953 KdStream << ".amdhsa_kernel " << KdName << '\n';
1954
1956 while (C && C.tell() < Bytes.size()) {
1958 decodeKernelDescriptorDirective(C, Bytes, KdStream);
1959
1960 cantFail(C.takeError());
1961
1963 return MCDisassembler::Fail;
1964 }
1965 KdStream << ".end_amdhsa_kernel\n";
1966 outs() << KdStream.str();
1968}
1969
1970std::optional<MCDisassembler::DecodeStatus>
1973 raw_ostream &CStream) const {
1974 // Right now only kernel descriptor needs to be handled.
1975 // We ignore all other symbols for target specific handling.
1976 // TODO:
1977 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code
1978 // Object V2 and V3 when symbols are marked protected.
1979
1980 // amd_kernel_code_t for Code Object V2.
1981 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) {
1982 Size = 256;
1983 return MCDisassembler::Fail;
1984 }
1985
1986 // Code Object V3 kernel descriptors.
1987 StringRef Name = Symbol.Name;
1988 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) {
1989 Size = 64; // Size = 64 regardless of success or failure.
1990 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address);
1991 }
1992 return std::nullopt;
1993}
1994
1995//===----------------------------------------------------------------------===//
1996// AMDGPUSymbolizer
1997//===----------------------------------------------------------------------===//
1998
1999// Try to find symbol name for specified label
2001 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value,
2002 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/,
2003 uint64_t /*OpSize*/, uint64_t /*InstSize*/) {
2004
2005 if (!IsBranch) {
2006 return false;
2007 }
2008
2009 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
2010 if (!Symbols)
2011 return false;
2012
2013 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) {
2014 return Val.Addr == static_cast<uint64_t>(Value) &&
2015 Val.Type == ELF::STT_NOTYPE;
2016 });
2017 if (Result != Symbols->end()) {
2018 auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
2019 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
2021 return true;
2022 }
2023 // Add to list of referenced addresses, so caller can synthesize a label.
2024 ReferencedAddresses.push_back(static_cast<uint64_t>(Value));
2025 return false;
2026}
2027
2029 int64_t Value,
2030 uint64_t Address) {
2031 llvm_unreachable("unimplemented");
2032}
2033
2034//===----------------------------------------------------------------------===//
2035// Initialization
2036//===----------------------------------------------------------------------===//
2037
2039 LLVMOpInfoCallback /*GetOpInfo*/,
2040 LLVMSymbolLookupCallback /*SymbolLookUp*/,
2041 void *DisInfo,
2042 MCContext *Ctx,
2043 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
2044 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
2045}
2046
2048 const MCSubtargetInfo &STI,
2049 MCContext &Ctx) {
2050 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
2051}
2052
2058}
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx, const MCRegisterInfo *MRI)
static VOPModifiers collectVOPModifiers(const MCInst &MI, bool IsVOP3P=false)
static bool isValidDPP8(const MCInst &MI)
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth)
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static DecodeStatus DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecoderUInt128 eat12Bytes(ArrayRef< uint8_t > &Bytes)
#define DECODE_SDWA(DecName)
#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth)
#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth)
#define DECODE_OPERAND_REG_8(RegClass)
#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth)
static int64_t getInlineImmVal16(unsigned Imm)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static int64_t getInlineImmVal32(unsigned Imm)
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_REG_7(RegClass, OpWidth)
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth)
#define SGPR_MAX
static int64_t getInlineImmVal64(unsigned Imm)
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth)
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth)
static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
This file contains declaration for AMDGPU ISA disassembler.
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
uint64_t Addr
std::string Name
uint64_t Size
Symbol * Sym
Definition: ELF_riscv.cpp:463
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
uint64_t TSFlags
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm)
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeLiteralConstant() const
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus convertSDWAInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
DecodeStatus convertMIMGInst(MCInst &MI) const
DecodeStatus convertVINTERPInst(MCInst &MI) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
DecodeStatus convertEXPInst(MCInst &MI) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getTtmpClassId(const OpWidthTy Width) const
std::optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth=0) const
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeSDWASrc16(unsigned Val) const
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
Definition: APInt.h:75
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:945
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:163
const T * data() const
Definition: ArrayRef.h:160
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:193
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
uint64_t tell() const
Return the current position of this Cursor.
Definition: DataExtractor.h:71
uint32_t getU32(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint32_t value from *offset_ptr.
uint16_t getU16(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint16_t value from *offset_ptr.
void skip(Cursor &C, uint64_t Length) const
Advance the Cursor position by the given number of bytes.
StringRef getBytes(uint64_t *OffsetPtr, uint64_t Length, Error *Err=nullptr) const
Extract a fixed number of bytes from the specified offset.
Context object for machine code objects.
Definition: MCContext.h:76
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:448
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Definition: MCContext.cpp:201
Superclass for all disassemblers.
MCContext & getContext() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
unsigned getNumOperands() const
Definition: MCInst.h:208
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
bool isReg() const
Definition: MCInst.h:61
bool isValid() const
Definition: MCInst.h:60
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
MCContext & Ctx
Definition: MCSymbolizer.h:41
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:660
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool hasPackedD16(const MCSubtargetInfo &STI)
bool isVOPC64DPP(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getAmdhsaCodeObjectVersion()
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:174
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:173
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool isMAC(unsigned Opc)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
bool hasVOPD(const MCSubtargetInfo &STI)
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ STT_NOTYPE
Definition: ELF.h:1253
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1267
@ STT_OBJECT
Definition: ELF.h:1254
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
int popcount(T Value) noexcept
Count the number of set bits in a value.
Definition: bit.h:349
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Definition: Error.h:745
Target & getTheGCNTarget()
The target for GCN GPUs.
@ Add
Sum of integers.
std::vector< SymbolInfoTy > SectionSymbolsTy
unsigned M0(unsigned Val)
Definition: VE.h:467
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1846
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.