39#define DEBUG_TYPE "amdgpu-disassembler"
42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
43 : AMDGPU::EncValues::SGPR_MAX_SI)
51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
71 std::advance(
I, OpIdx);
84 APInt SignedOffset(18, Imm * 4,
true);
85 int64_t
Offset = (SignedOffset.
sext(64) + 4 +
Addr).getSExtValue();
87 if (DAsm->tryAddingSymbolicOperand(Inst,
Offset,
Addr,
true, 2, 2, 0))
99 Offset = SignExtend64<21>(Imm);
107 return addOperand(Inst, DAsm->decodeBoolReg(Val));
110#define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
113 const MCDisassembler *Decoder) { \
114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
115 return addOperand(Inst, DAsm->DecoderName(Imm)); \
118#define DECODE_OPERAND_REG(RegClass) \
119DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
164 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
171 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
178 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm));
185 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
192 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
269 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
276 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
298 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
310 unsigned Sub =
MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
311 auto Reg = Sub ? Sub : Op.getReg();
312 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
319 if (!DAsm->isGFX90A()) {
330 : AMDGPU::OpName::vdata;
346 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
388 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
391#define DECODE_SDWA(DecName) \
392DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
398#include "AMDGPUGenDisassemblerTables.inc"
406 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.
data());
407 Bytes = Bytes.
slice(
sizeof(
T));
413 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>(
415 Bytes = Bytes.
slice(8);
416 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>(
418 Bytes = Bytes.
slice(4);
429 if ((
unsigned)FiIdx >=
MI.getNumOperands())
431 unsigned Fi =
MI.getOperand(FiIdx).getImm();
432 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
442 unsigned MaxInstBytesNum = std::min((
size_t)TargetMaxInstBytes, Bytes_.
size());
443 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
477 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
479 if (Bytes.
size() >= 8) {
480 const uint64_t QW = eatBytes<uint64_t>(Bytes);
515 if (Res) { IsSDWA =
true;
break; }
518 if (Res) { IsSDWA =
true;
break; }
521 if (Res) { IsSDWA =
true;
break; }
540 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
543 if (Bytes.
size() < 4)
break;
544 const uint32_t DW = eatBytes<uint32_t>(Bytes);
571 if (Bytes.
size() < 4)
break;
608 AMDGPU::OpName::src2_modifiers);
611 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
614 AMDGPU::OpName::cpol);
619 if (
MI.getNumOperands() <= (
unsigned)CPolPos) {
621 AMDGPU::OpName::cpol);
623 MI.getOperand(CPolPos).setImm(
MI.getOperand(CPolPos).getImm() | CPol);
628 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
634 if (TFEOpIdx != -1) {
635 auto TFEIter =
MI.begin();
636 std::advance(TFEIter, TFEOpIdx);
641 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
645 if (SWZOpIdx != -1) {
646 auto SWZIter =
MI.begin();
647 std::advance(SWZIter, SWZOpIdx);
657 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
658 if (VAddr0Idx >= 0 && NSAArgs > 0) {
659 unsigned NSAWords = (NSAArgs + 3) / 4;
660 if (Bytes.
size() < 4 * NSAWords) {
663 for (
unsigned i = 0; i < NSAArgs; ++i) {
664 const unsigned VAddrIdx = VAddr0Idx + 1 + i;
666 MCII->get(
MI.getOpcode()).operands()[VAddrIdx].RegClass;
667 MI.insert(
MI.begin() + VAddrIdx,
670 Bytes = Bytes.
slice(4 * NSAWords);
688 AMDGPU::OpName::vdst_in);
689 if (VDstIn_Idx != -1) {
690 int Tied = MCII->get(
MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
692 if (Tied != -1 && (
MI.getNumOperands() <= (
unsigned)VDstIn_Idx ||
693 !
MI.getOperand(VDstIn_Idx).isReg() ||
694 MI.getOperand(VDstIn_Idx).getReg() !=
MI.getOperand(Tied).getReg())) {
695 if (
MI.getNumOperands() > (
unsigned)VDstIn_Idx)
696 MI.erase(&
MI.getOperand(VDstIn_Idx));
699 AMDGPU::OpName::vdst_in);
706 if (Res && ImmLitIdx != -1 && !IsSOPK)
711 Size = Res ? (MaxInstBytesNum - Bytes.
size())
712 : std::min((
size_t)4, Bytes_.
size());
727 if (
MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 ||
728 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 ||
729 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 ||
730 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) {
749 AMDGPU::OpName::sdst);
760 unsigned OpSelHi = 0;
769 bool IsVOP3P =
false) {
771 unsigned Opc =
MI.getOpcode();
772 const int ModOps[] = {AMDGPU::OpName::src0_modifiers,
773 AMDGPU::OpName::src1_modifiers,
774 AMDGPU::OpName::src2_modifiers};
775 for (
int J = 0; J < 3; ++J) {
780 unsigned Val =
MI.getOperand(OpIdx).getImm();
798 constexpr int DST_IDX = 0;
799 auto Opcode =
MI.getOpcode();
800 const auto &Desc = MCII->get(Opcode);
803 if (OldIdx != -1 && Desc.getOperandConstraint(
806 assert(Desc.getOperandConstraint(
818 assert(
MI.getNumOperands() + 1 < MCII->get(
MI.getOpcode()).getNumOperands());
821 AMDGPU::OpName::src2_modifiers);
827 unsigned Opc =
MI.getOpcode();
837 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
838 if (
MI.getNumOperands() < DescNumOps &&
842 AMDGPU::OpName::op_sel);
845 if (
MI.getNumOperands() < DescNumOps &&
848 AMDGPU::OpName::src0_modifiers);
850 if (
MI.getNumOperands() < DescNumOps &&
853 AMDGPU::OpName::src1_modifiers);
863 unsigned Opc =
MI.getOpcode();
864 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
865 if (
MI.getNumOperands() < DescNumOps &&
869 AMDGPU::OpName::op_sel);
880 AMDGPU::OpName::vdst);
883 AMDGPU::OpName::vdata);
887 AMDGPU::OpName::dmask);
890 AMDGPU::OpName::tfe);
892 AMDGPU::OpName::d16);
899 if (BaseOpcode->
BVH) {
906 bool IsAtomic = (VDstIdx != -1);
909 unsigned AddrSize =
Info->VAddrDwords;
918 const bool IsA16 = (A16Idx != -1 &&
MI.getOperand(A16Idx).getImm());
923 IsNSA =
Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA ||
924 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA;
929 if (AddrSize >
Info->VAddrDwords) {
937 unsigned DMask =
MI.getOperand(DMaskIdx).getImm() & 0xf;
938 unsigned DstSize = IsGather4 ? 4 : std::max(
llvm::popcount(DMask), 1);
940 bool D16 = D16Idx >= 0 &&
MI.getOperand(D16Idx).getImm();
942 DstSize = (DstSize + 1) / 2;
945 if (TFEIdx != -1 &&
MI.getOperand(TFEIdx).getImm())
948 if (DstSize ==
Info->VDataDwords && AddrSize ==
Info->VAddrDwords)
957 unsigned NewVdata = AMDGPU::NoRegister;
958 if (DstSize !=
Info->VDataDwords) {
959 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
962 unsigned Vdata0 =
MI.getOperand(VDataIdx).getReg();
963 unsigned VdataSub0 = MRI.
getSubReg(Vdata0, AMDGPU::sub0);
964 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
968 if (NewVdata == AMDGPU::NoRegister) {
976 unsigned NewVAddr0 = AMDGPU::NoRegister;
978 unsigned VAddr0 =
MI.getOperand(VAddr0Idx).getReg();
979 unsigned VAddrSub0 = MRI.
getSubReg(VAddr0, AMDGPU::sub0);
980 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
982 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddr0Idx].RegClass;
985 if (NewVAddr0 == AMDGPU::NoRegister)
989 MI.setOpcode(NewOpcode);
991 if (NewVdata != AMDGPU::NoRegister) {
1000 if (NewVAddr0 != AMDGPU::NoRegister) {
1003 assert(AddrSize <= Info->VAddrDwords);
1004 MI.erase(
MI.begin() + VAddr0Idx + AddrSize,
1005 MI.begin() + VAddr0Idx +
Info->VAddrDwords);
1015 unsigned Opc =
MI.getOpcode();
1016 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1019 if (
MI.getNumOperands() < DescNumOps &&
1023 if (
MI.getNumOperands() < DescNumOps &&
1026 AMDGPU::OpName::op_sel);
1027 if (
MI.getNumOperands() < DescNumOps &&
1030 AMDGPU::OpName::op_sel_hi);
1031 if (
MI.getNumOperands() < DescNumOps &&
1034 AMDGPU::OpName::neg_lo);
1035 if (
MI.getNumOperands() < DescNumOps &&
1038 AMDGPU::OpName::neg_hi);
1045 unsigned Opc =
MI.getOpcode();
1046 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1048 if (
MI.getNumOperands() < DescNumOps &&
1052 if (
MI.getNumOperands() < DescNumOps &&
1055 AMDGPU::OpName::src0_modifiers);
1057 if (
MI.getNumOperands() < DescNumOps &&
1060 AMDGPU::OpName::src1_modifiers);
1065 int ImmLitIdx)
const {
1066 assert(HasLiteral &&
"Should have decoded a literal");
1070 AMDGPU::OpName::immDeferred);
1071 assert(DescNumOps ==
MI.getNumOperands());
1072 for (
unsigned I = 0;
I < DescNumOps; ++
I) {
1073 auto &Op =
MI.getOperand(
I);
1074 auto OpType = Desc.
operands()[
I].OperandType;
1091 const Twine& ErrMsg)
const {
1106 unsigned Val)
const {
1107 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
1108 if (Val >= RegCl.getNumRegs())
1110 ": unknown register " +
Twine(Val));
1116 unsigned Val)
const {
1120 switch (SRegClassID) {
1121 case AMDGPU::SGPR_32RegClassID:
1122 case AMDGPU::TTMP_32RegClassID:
1124 case AMDGPU::SGPR_64RegClassID:
1125 case AMDGPU::TTMP_64RegClassID:
1128 case AMDGPU::SGPR_128RegClassID:
1129 case AMDGPU::TTMP_128RegClassID:
1132 case AMDGPU::SGPR_256RegClassID:
1133 case AMDGPU::TTMP_256RegClassID:
1136 case AMDGPU::SGPR_288RegClassID:
1137 case AMDGPU::TTMP_288RegClassID:
1138 case AMDGPU::SGPR_320RegClassID:
1139 case AMDGPU::TTMP_320RegClassID:
1140 case AMDGPU::SGPR_352RegClassID:
1141 case AMDGPU::TTMP_352RegClassID:
1142 case AMDGPU::SGPR_384RegClassID:
1143 case AMDGPU::TTMP_384RegClassID:
1144 case AMDGPU::SGPR_512RegClassID:
1145 case AMDGPU::TTMP_512RegClassID:
1154 if (Val % (1 << shift)) {
1156 <<
": scalar reg isn't aligned " << Val;
1257 using namespace AMDGPU::EncValues;
1258 assert((Val & IS_VGPR) == 0);
1263 using namespace AMDGPU::EncValues;
1264 assert((Val & IS_VGPR) == 0);
1316 unsigned Val)
const {
1322 unsigned Val)
const {
1376 "Should only decode multiple kimm with VOPD, check VSrc operand types");
1378 return errOperand(Val,
"More than one unique literal is illegal");
1390 if (Bytes.
size() < 4) {
1391 return errOperand(0,
"cannot read literal, inst bytes left " +
1395 Literal = eatBytes<uint32_t>(Bytes);
1401 using namespace AMDGPU::EncValues;
1403 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
1405 (
static_cast<int64_t
>(Imm) - INLINE_INTEGER_C_MIN) :
1406 (INLINE_INTEGER_C_POSITIVE_MAX -
static_cast<int64_t
>(Imm)));
1454 return 0x3fc45f306dc9c882;
1517 return VGPR_32RegClassID;
1519 case OPWV232:
return VReg_64RegClassID;
1520 case OPW96:
return VReg_96RegClassID;
1521 case OPW128:
return VReg_128RegClassID;
1522 case OPW160:
return VReg_160RegClassID;
1523 case OPW256:
return VReg_256RegClassID;
1524 case OPW288:
return VReg_288RegClassID;
1525 case OPW320:
return VReg_320RegClassID;
1526 case OPW352:
return VReg_352RegClassID;
1527 case OPW384:
return VReg_384RegClassID;
1528 case OPW512:
return VReg_512RegClassID;
1529 case OPW1024:
return VReg_1024RegClassID;
1542 return AGPR_32RegClassID;
1544 case OPWV232:
return AReg_64RegClassID;
1545 case OPW96:
return AReg_96RegClassID;
1546 case OPW128:
return AReg_128RegClassID;
1547 case OPW160:
return AReg_160RegClassID;
1548 case OPW256:
return AReg_256RegClassID;
1549 case OPW288:
return AReg_288RegClassID;
1550 case OPW320:
return AReg_320RegClassID;
1551 case OPW352:
return AReg_352RegClassID;
1552 case OPW384:
return AReg_384RegClassID;
1553 case OPW512:
return AReg_512RegClassID;
1554 case OPW1024:
return AReg_1024RegClassID;
1568 return SGPR_32RegClassID;
1570 case OPWV232:
return SGPR_64RegClassID;
1571 case OPW96:
return SGPR_96RegClassID;
1572 case OPW128:
return SGPR_128RegClassID;
1573 case OPW160:
return SGPR_160RegClassID;
1574 case OPW256:
return SGPR_256RegClassID;
1575 case OPW288:
return SGPR_288RegClassID;
1576 case OPW320:
return SGPR_320RegClassID;
1577 case OPW352:
return SGPR_352RegClassID;
1578 case OPW384:
return SGPR_384RegClassID;
1579 case OPW512:
return SGPR_512RegClassID;
1592 return TTMP_32RegClassID;
1594 case OPWV232:
return TTMP_64RegClassID;
1595 case OPW128:
return TTMP_128RegClassID;
1596 case OPW256:
return TTMP_256RegClassID;
1597 case OPW288:
return TTMP_288RegClassID;
1598 case OPW320:
return TTMP_320RegClassID;
1599 case OPW352:
return TTMP_352RegClassID;
1600 case OPW384:
return TTMP_384RegClassID;
1601 case OPW512:
return TTMP_512RegClassID;
1606 using namespace AMDGPU::EncValues;
1608 unsigned TTmpMin =
isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1609 unsigned TTmpMax =
isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1611 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1615 bool MandatoryLiteral)
const {
1616 using namespace AMDGPU::EncValues;
1620 bool IsAGPR = Val & 512;
1623 if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1629 static_assert(SGPR_MIN == 0);
1638 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1641 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1644 if (Val == LITERAL_CONST) {
1645 if (MandatoryLiteral)
1666 using namespace AMDGPU::EncValues;
1673 static_assert(SGPR_MIN == 0);
1688 unsigned Val)
const {
1694 Val |= ~XDstReg & 1;
1767 const unsigned Val)
const {
1768 using namespace AMDGPU::SDWA;
1769 using namespace AMDGPU::EncValues;
1775 if (
int(SDWA9EncValues::SRC_VGPR_MIN) <=
int(Val) &&
1776 Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1778 Val - SDWA9EncValues::SRC_VGPR_MIN);
1780 if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1781 Val <= (
isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1782 : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1784 Val - SDWA9EncValues::SRC_SGPR_MIN);
1786 if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1787 Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1789 Val - SDWA9EncValues::SRC_TTMP_MIN);
1792 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1794 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1797 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1816 using namespace AMDGPU::SDWA;
1820 "SDWAVopcDst should be present only on GFX9+");
1824 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1825 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1881#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1883 KdStream << Indent << DIRECTIVE " " \
1884 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1890 using namespace amdhsa;
1898 uint32_t GranulatedWorkitemVGPRCount =
1899 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >>
1900 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT;
1902 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) *
1905 KdStream << Indent <<
".amdhsa_next_free_vgpr " << NextFreeVGPR <<
'\n';
1926 uint32_t GranulatedWavefrontSGPRCount =
1927 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
1928 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
1930 if (
isGFX10Plus() && GranulatedWavefrontSGPRCount)
1933 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1936 KdStream << Indent <<
".amdhsa_reserve_vcc " << 0 <<
'\n';
1938 KdStream << Indent <<
".amdhsa_reserve_flat_scratch " << 0 <<
'\n';
1939 KdStream << Indent <<
".amdhsa_reserve_xnack_mask " << 0 <<
'\n';
1940 KdStream << Indent <<
".amdhsa_next_free_sgpr " << NextFreeSGPR <<
"\n";
1942 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1946 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1948 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1950 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1952 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1954 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1957 PRINT_DIRECTIVE(
".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1959 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1962 PRINT_DIRECTIVE(
".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1964 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1967 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1970 PRINT_DIRECTIVE(
".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1972 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1977 COMPUTE_PGM_RSRC1_WGP_MODE);
1978 PRINT_DIRECTIVE(
".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1979 PRINT_DIRECTIVE(
".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1987 using namespace amdhsa;
1991 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1993 PRINT_DIRECTIVE(
".amdhsa_system_sgpr_private_segment_wavefront_offset",
1994 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1996 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1998 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
2000 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
2002 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
2004 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
2006 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
2009 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
2012 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
2016 ".amdhsa_exception_fp_ieee_invalid_op",
2017 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
2019 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
2021 ".amdhsa_exception_fp_ieee_div_zero",
2022 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
2024 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
2026 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
2028 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
2030 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
2032 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
2038#undef PRINT_DIRECTIVE
2044#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
2046 KdStream << Indent << DIRECTIVE " " \
2047 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
2059 switch (Cursor.
tell()) {
2061 FourByteBuffer = DE.
getU32(Cursor);
2062 KdStream << Indent <<
".amdhsa_group_segment_fixed_size " << FourByteBuffer
2067 FourByteBuffer = DE.
getU32(Cursor);
2068 KdStream << Indent <<
".amdhsa_private_segment_fixed_size "
2069 << FourByteBuffer <<
'\n';
2073 FourByteBuffer = DE.
getU32(Cursor);
2074 KdStream << Indent <<
".amdhsa_kernarg_size "
2075 << FourByteBuffer <<
'\n';
2080 ReservedBytes = DE.
getBytes(Cursor, 4);
2081 for (
int I = 0;
I < 4; ++
I) {
2082 if (ReservedBytes[
I] != 0) {
2097 ReservedBytes = DE.
getBytes(Cursor, 20);
2098 for (
int I = 0;
I < 20; ++
I) {
2099 if (ReservedBytes[
I] != 0) {
2109 FourByteBuffer = DE.
getU32(Cursor);
2116 FourByteBuffer = DE.
getU32(Cursor);
2124 FourByteBuffer = DE.
getU32(Cursor);
2132 using namespace amdhsa;
2133 TwoByteBuffer = DE.
getU16(Cursor);
2137 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
2139 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
2141 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
2143 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
2145 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
2148 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
2150 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
2152 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
2157 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
2161 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
2166 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
2168 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
2175 ReservedBytes = DE.
getBytes(Cursor, 6);
2176 for (
int I = 0;
I < 6; ++
I) {
2177 if (ReservedBytes[
I] != 0)
2186#undef PRINT_DIRECTIVE
2192 if (Bytes.
size() != 64 || KdAddress % 64 != 0)
2197 KdStream <<
".amdhsa_kernel " << KdName <<
'\n';
2200 while (
C &&
C.tell() < Bytes.
size()) {
2209 KdStream <<
".end_amdhsa_kernel\n";
2214std::optional<MCDisassembler::DecodeStatus>
2236 return std::nullopt;
2261 if (Result != Symbols->end()) {
2268 ReferencedAddresses.push_back(
static_cast<uint64_t>(
Value));
2287 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
unsigned const MachineRegisterInfo * MRI
static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx, const MCRegisterInfo *MRI)
static VOPModifiers collectVOPModifiers(const MCInst &MI, bool IsVOP3P=false)
static bool isValidDPP8(const MCInst &MI)
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_REG(RegClass)
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static DecodeStatus DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecoderUInt128 eat12Bytes(ArrayRef< uint8_t > &Bytes)
static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_SDWA(DecName)
static int64_t getInlineImmVal16(unsigned Imm)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static int64_t getInlineImmVal32(unsigned Imm)
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static int64_t getInlineImmVal64(unsigned Imm)
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
This file contains declaration for AMDGPU ISA disassembler.
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
MCOperand decodeOperand_VS_128(unsigned Val) const
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeLiteralConstant() const
MCOperand decodeOperand_VReg_288(unsigned Val) const
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
MCOperand decodeOperand_VReg_384(unsigned Val) const
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
unsigned getVgprClassId(const OpWidthTy Width) const
MCOperand decodeOperand_AVDst_512(unsigned Val) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus convertSDWAInst(MCInst &MI) const
MCOperand decodeOperand_SReg_256(unsigned Val) const
MCOperand decodeOperand_AReg_384(unsigned Val) const
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand decodeOperand_SReg_128(unsigned Val) const
MCOperand decodeOperand_AV_64(unsigned Val) const
MCOperand decodeOperand_AV_32(unsigned Val) const
MCOperand decodeOperand_VReg_128(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
MCOperand decodeOperand_AVDst_128(unsigned Val) const
MCOperand decodeOperand_VSrcV216(unsigned Val) const
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeOperand_AReg_256(unsigned Val) const
MCOperand decodeOperand_VReg_256(unsigned Val) const
MCOperand decodeOperand_AReg_128(unsigned Val) const
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
MCOperand decodeOperand_VReg_352(unsigned Val) const
MCOperand decodeOperand_SReg_64(unsigned Val) const
MCOperand decodeOperand_AReg_1024(unsigned Val) const
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeOperand_VGPR_32_Lo128(unsigned Val) const
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
MCOperand decodeOperand_VSrcV232(unsigned Val) const
MCOperand decodeOperand_VSrc16(unsigned Val) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
MCOperand decodeOperand_SReg_288(unsigned Val) const
MCOperand decodeOperand_VReg_320(unsigned Val) const
MCOperand decodeOperand_AReg_512(unsigned Val) const
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
MCOperand decodeOperand_SReg_352(unsigned Val) const
MCOperand decodeOperand_VS_64(unsigned Val) const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
DecodeStatus convertMIMGInst(MCInst &MI) const
MCOperand decodeOperand_SReg_320(unsigned Val) const
MCOperand decodeOperand_AReg_352(unsigned Val) const
DecodeStatus convertVINTERPInst(MCInst &MI) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
MCOperand decodeOperand_AReg_288(unsigned Val) const
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
MCOperand decodeOperand_VReg_96(unsigned Val) const
DecodeStatus convertEXPInst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address) const
MCOperand decodeOperand_AReg_320(unsigned Val) const
MCOperand decodeOperand_VReg_512(unsigned Val) const
MCOperand decodeOperand_SReg_384(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
MCOperand decodeOperand_VReg_1024(unsigned Val) const
MCOperand decodeOperand_AGPR_32(unsigned Val) const
MCOperand decodeOperand_AV_128(unsigned Val) const
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand decodeOperand_AReg_64(unsigned Val) const
bool hasArchitectedFlatScratch() const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
MCOperand decodeOperand_SReg_512(unsigned Val) const
unsigned getTtmpClassId(const OpWidthTy Width) const
MCOperand decodeOperand_VS_32(unsigned Val) const
std::optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
MCOperand decodeSDWASrc16(unsigned Val) const
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
APInt sext(unsigned width) const
Sign extend to a new width.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Superclass for all disassemblers.
MCContext & getContext() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Generic base class for all target subtargets.
const FeatureBitset & getFeatureBits() const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Symbolize and annotate disassembled instructions.
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool hasPackedD16(const MCSubtargetInfo &STI)
bool isVOPC64DPP(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getAmdhsaCodeObjectVersion()
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isGFX9Plus(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
bool hasVOPD(const MCSubtargetInfo &STI)
@ C
The default llvm calling convention, compatible with C.
@ KERNEL_CODE_PROPERTIES_OFFSET
@ GROUP_SEGMENT_FIXED_SIZE_OFFSET
@ COMPUTE_PGM_RSRC3_OFFSET
@ KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
@ COMPUTE_PGM_RSRC1_OFFSET
@ COMPUTE_PGM_RSRC2_OFFSET
@ PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Target & getTheGCNTarget()
The target for GCN GPUs.
std::vector< SymbolInfoTy > SectionSymbolsTy
unsigned M0(unsigned Val)
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.