LLVM  14.0.0git
AMDGPUDisassembler.cpp
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1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
22 #include "Utils/AMDGPUBaseInfo.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCExpr.h"
28 #include "llvm/MC/TargetRegistry.h"
29 #include "llvm/MC/MCInstrDesc.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "amdgpu-disassembler"
35 
36 #define SGPR_MAX \
37  (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
38  : AMDGPU::EncValues::SGPR_MAX_SI)
39 
41 
43  MCContext &Ctx,
44  MCInstrInfo const *MCII) :
45  MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
46  TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
47 
48  // ToDo: AMDGPUDisassembler supports only VI ISA.
49  if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus())
50  report_fatal_error("Disassembly not yet supported for subtarget");
51 }
52 
53 inline static MCDisassembler::DecodeStatus
54 addOperand(MCInst &Inst, const MCOperand& Opnd) {
55  Inst.addOperand(Opnd);
56  return Opnd.isValid() ?
59 }
60 
62  uint16_t NameIdx) {
63  int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
64  if (OpIdx != -1) {
65  auto I = MI.begin();
66  std::advance(I, OpIdx);
67  MI.insert(I, Op);
68  }
69  return OpIdx;
70 }
71 
72 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
73  uint64_t Addr, const void *Decoder) {
74  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
75 
76  // Our branches take a simm16, but we need two extra bits to account for the
77  // factor of 4.
78  APInt SignedOffset(18, Imm * 4, true);
79  int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
80 
81  if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
83  return addOperand(Inst, MCOperand::createImm(Imm));
84 }
85 
86 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
87  uint64_t Addr, const void *Decoder) {
88  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
89  int64_t Offset;
90  if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets.
91  Offset = Imm & 0xFFFFF;
92  } else { // GFX9+ supports 21-bit signed offsets.
93  Offset = SignExtend64<21>(Imm);
94  }
95  return addOperand(Inst, MCOperand::createImm(Offset));
96 }
97 
98 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
99  uint64_t Addr, const void *Decoder) {
100  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
101  return addOperand(Inst, DAsm->decodeBoolReg(Val));
102 }
103 
104 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
105 static DecodeStatus StaticDecoderName(MCInst &Inst, \
106  unsigned Imm, \
107  uint64_t /*Addr*/, \
108  const void *Decoder) { \
109  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
110  return addOperand(Inst, DAsm->DecoderName(Imm)); \
111 }
112 
113 #define DECODE_OPERAND_REG(RegClass) \
114 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
115 
116 DECODE_OPERAND_REG(VGPR_32)
117 DECODE_OPERAND_REG(VRegOrLds_32)
118 DECODE_OPERAND_REG(VS_32)
119 DECODE_OPERAND_REG(VS_64)
120 DECODE_OPERAND_REG(VS_128)
121 
122 DECODE_OPERAND_REG(VReg_64)
123 DECODE_OPERAND_REG(VReg_96)
124 DECODE_OPERAND_REG(VReg_128)
125 DECODE_OPERAND_REG(VReg_256)
126 DECODE_OPERAND_REG(VReg_512)
127 DECODE_OPERAND_REG(VReg_1024)
128 
129 DECODE_OPERAND_REG(SReg_32)
130 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
131 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
132 DECODE_OPERAND_REG(SRegOrLds_32)
133 DECODE_OPERAND_REG(SReg_64)
134 DECODE_OPERAND_REG(SReg_64_XEXEC)
135 DECODE_OPERAND_REG(SReg_128)
136 DECODE_OPERAND_REG(SReg_256)
137 DECODE_OPERAND_REG(SReg_512)
138 
139 DECODE_OPERAND_REG(AGPR_32)
140 DECODE_OPERAND_REG(AReg_64)
141 DECODE_OPERAND_REG(AReg_128)
142 DECODE_OPERAND_REG(AReg_256)
143 DECODE_OPERAND_REG(AReg_512)
144 DECODE_OPERAND_REG(AReg_1024)
145 DECODE_OPERAND_REG(AV_32)
146 DECODE_OPERAND_REG(AV_64)
147 
149  unsigned Imm,
150  uint64_t Addr,
151  const void *Decoder) {
152  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
153  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
154 }
155 
157  unsigned Imm,
158  uint64_t Addr,
159  const void *Decoder) {
160  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
161  return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
162 }
163 
165  unsigned Imm,
166  uint64_t Addr,
167  const void *Decoder) {
168  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
169  return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm));
170 }
171 
173  unsigned Imm,
174  uint64_t Addr,
175  const void *Decoder) {
176  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
177  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
178 }
179 
181  unsigned Imm,
182  uint64_t Addr,
183  const void *Decoder) {
184  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
185  return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
186 }
187 
189  unsigned Imm,
190  uint64_t Addr,
191  const void *Decoder) {
192  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
193  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512));
194 }
195 
197  unsigned Imm,
198  uint64_t Addr,
199  const void *Decoder) {
200  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
201  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
202 }
203 
205  unsigned Imm,
206  uint64_t Addr,
207  const void *Decoder) {
208  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
209  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512));
210 }
211 
213  unsigned Imm,
214  uint64_t Addr,
215  const void *Decoder) {
216  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
217  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
218 }
219 
221  unsigned Imm,
222  uint64_t Addr,
223  const void *Decoder) {
224  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
225  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
226 }
227 
229  unsigned Imm,
230  uint64_t Addr,
231  const void *Decoder) {
232  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
233  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm));
234 }
235 
237  unsigned Imm,
238  uint64_t Addr,
239  const void *Decoder) {
240  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
241  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm));
242 }
243 
245  unsigned Imm,
246  uint64_t Addr,
247  const void *Decoder) {
248  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
249  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm));
250 }
251 
253  unsigned Imm,
254  uint64_t Addr,
255  const void *Decoder) {
256  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
257  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm));
258 }
259 
261  unsigned Imm,
262  uint64_t Addr,
263  const void *Decoder) {
264  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
265  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm));
266 }
267 
268 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm,
269  uint64_t Addr, const void *Decoder) {
270  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
271  return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
272 }
273 
274 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm,
275  uint64_t Addr, const void *Decoder) {
276  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
277  return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
278 }
279 
281  uint64_t Addr,
282  const void *Decoder) {
283  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
284  return addOperand(
285  Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true));
286 }
287 
289  uint64_t Addr,
290  const void *Decoder) {
291  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
292  return addOperand(
293  Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true));
294 }
295 
296 static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
297  const MCRegisterInfo *MRI) {
298  if (OpIdx < 0)
299  return false;
300 
301  const MCOperand &Op = Inst.getOperand(OpIdx);
302  if (!Op.isReg())
303  return false;
304 
305  unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
306  auto Reg = Sub ? Sub : Op.getReg();
307  return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
308 }
309 
311  unsigned Imm,
313  const void *Decoder) {
314  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
315  if (!DAsm->isGFX90A()) {
316  Imm &= 511;
317  } else {
318  // If atomic has both vdata and vdst their register classes are tied.
319  // The bit is decoded along with the vdst, first operand. We need to
320  // change register class to AGPR if vdst was AGPR.
321  // If a DS instruction has both data0 and data1 their register classes
322  // are also tied.
323  unsigned Opc = Inst.getOpcode();
324  uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
325  uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
326  : AMDGPU::OpName::vdata;
327  const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
328  int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx);
329  if ((int)Inst.getNumOperands() == DataIdx) {
330  int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
331  if (IsAGPROperand(Inst, DstIdx, MRI))
332  Imm |= 512;
333  }
334 
335  if (TSFlags & SIInstrFlags::DS) {
336  int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
337  if ((int)Inst.getNumOperands() == Data2Idx &&
338  IsAGPROperand(Inst, DataIdx, MRI))
339  Imm |= 512;
340  }
341  }
342  return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
343 }
344 
346  unsigned Imm,
347  uint64_t Addr,
348  const void *Decoder) {
349  return decodeOperand_AVLdSt_Any(Inst, Imm,
350  AMDGPUDisassembler::OPW32, Decoder);
351 }
352 
354  unsigned Imm,
355  uint64_t Addr,
356  const void *Decoder) {
357  return decodeOperand_AVLdSt_Any(Inst, Imm,
358  AMDGPUDisassembler::OPW64, Decoder);
359 }
360 
362  unsigned Imm,
363  uint64_t Addr,
364  const void *Decoder) {
365  return decodeOperand_AVLdSt_Any(Inst, Imm,
366  AMDGPUDisassembler::OPW96, Decoder);
367 }
368 
370  unsigned Imm,
371  uint64_t Addr,
372  const void *Decoder) {
373  return decodeOperand_AVLdSt_Any(Inst, Imm,
374  AMDGPUDisassembler::OPW128, Decoder);
375 }
376 
378  unsigned Imm,
379  uint64_t Addr,
380  const void *Decoder) {
381  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
382  return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
383 }
384 
386  unsigned Imm,
387  uint64_t Addr,
388  const void *Decoder) {
389  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
390  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
391 }
392 
393 #define DECODE_SDWA(DecName) \
394 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
395 
396 DECODE_SDWA(Src32)
397 DECODE_SDWA(Src16)
398 DECODE_SDWA(VopcDst)
399 
400 #include "AMDGPUGenDisassemblerTables.inc"
401 
402 //===----------------------------------------------------------------------===//
403 //
404 //===----------------------------------------------------------------------===//
405 
406 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
407  assert(Bytes.size() >= sizeof(T));
408  const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
409  Bytes = Bytes.slice(sizeof(T));
410  return Res;
411 }
412 
414  MCInst &MI,
415  uint64_t Inst,
416  uint64_t Address) const {
417  assert(MI.getOpcode() == 0);
418  assert(MI.getNumOperands() == 0);
419  MCInst TmpInst;
420  HasLiteral = false;
421  const auto SavedBytes = Bytes;
422  if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
423  MI = TmpInst;
425  }
426  Bytes = SavedBytes;
427  return MCDisassembler::Fail;
428 }
429 
430 // The disassembler is greedy, so we need to check FI operand value to
431 // not parse a dpp if the correct literal is not set. For dpp16 the
432 // autogenerated decoder checks the dpp literal
433 static bool isValidDPP8(const MCInst &MI) {
434  using namespace llvm::AMDGPU::DPP;
435  int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
436  assert(FiIdx != -1);
437  if ((unsigned)FiIdx >= MI.getNumOperands())
438  return false;
439  unsigned Fi = MI.getOperand(FiIdx).getImm();
440  return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
441 }
442 
444  ArrayRef<uint8_t> Bytes_,
445  uint64_t Address,
446  raw_ostream &CS) const {
447  CommentStream = &CS;
448  bool IsSDWA = false;
449 
450  unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
451  Bytes = Bytes_.slice(0, MaxInstBytesNum);
452 
454  do {
455  // ToDo: better to switch encoding length using some bit predicate
456  // but it is unknown yet, so try all we can
457 
458  // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
459  // encodings
460  if (Bytes.size() >= 8) {
461  const uint64_t QW = eatBytes<uint64_t>(Bytes);
462 
463  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
464  Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
465  if (Res) {
466  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
467  == -1)
468  break;
470  break;
471  MI = MCInst(); // clear
472  }
473  }
474 
475  Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
477  break;
478 
479  MI = MCInst(); // clear
480 
481  Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
482  if (Res) break;
483 
484  Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
485  if (Res) { IsSDWA = true; break; }
486 
487  Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
488  if (Res) { IsSDWA = true; break; }
489 
490  Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
491  if (Res) { IsSDWA = true; break; }
492 
493  if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
494  Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
495  if (Res)
496  break;
497  }
498 
499  // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
500  // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
501  // table first so we print the correct name.
502  if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
503  Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
504  if (Res)
505  break;
506  }
507  }
508 
509  // Reinitialize Bytes as DPP64 could have eaten too much
510  Bytes = Bytes_.slice(0, MaxInstBytesNum);
511 
512  // Try decode 32-bit instruction
513  if (Bytes.size() < 4) break;
514  const uint32_t DW = eatBytes<uint32_t>(Bytes);
515  Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
516  if (Res) break;
517 
518  Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
519  if (Res) break;
520 
521  Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
522  if (Res) break;
523 
524  if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) {
525  Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address);
526  if (Res)
527  break;
528  }
529 
530  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
531  Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address);
532  if (Res) break;
533  }
534 
535  Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
536  if (Res) break;
537 
538  if (Bytes.size() < 4) break;
539  const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
540 
541  if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) {
542  Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address);
543  if (Res)
544  break;
545  }
546 
547  Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
548  if (Res) break;
549 
550  Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
551  if (Res) break;
552 
553  Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
554  if (Res) break;
555 
556  Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
557  } while (false);
558 
559  if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
560  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
561  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
562  MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
563  MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
564  MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
565  MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a ||
566  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
567  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
568  MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
569  MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
570  // Insert dummy unused src2_modifiers.
572  AMDGPU::OpName::src2_modifiers);
573  }
574 
575  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
577  int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
578  AMDGPU::OpName::cpol);
579  if (CPolPos != -1) {
580  unsigned CPol =
581  (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ?
582  AMDGPU::CPol::GLC : 0;
583  if (MI.getNumOperands() <= (unsigned)CPolPos) {
585  AMDGPU::OpName::cpol);
586  } else if (CPol) {
587  MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol);
588  }
589  }
590  }
591 
592  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
594  (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) {
595  // GFX90A lost TFE, its place is occupied by ACC.
596  int TFEOpIdx =
597  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);
598  if (TFEOpIdx != -1) {
599  auto TFEIter = MI.begin();
600  std::advance(TFEIter, TFEOpIdx);
601  MI.insert(TFEIter, MCOperand::createImm(0));
602  }
603  }
604 
605  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
607  int SWZOpIdx =
608  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz);
609  if (SWZOpIdx != -1) {
610  auto SWZIter = MI.begin();
611  std::advance(SWZIter, SWZOpIdx);
612  MI.insert(SWZIter, MCOperand::createImm(0));
613  }
614  }
615 
616  if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
617  int VAddr0Idx =
618  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
619  int RsrcIdx =
620  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
621  unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
622  if (VAddr0Idx >= 0 && NSAArgs > 0) {
623  unsigned NSAWords = (NSAArgs + 3) / 4;
624  if (Bytes.size() < 4 * NSAWords) {
625  Res = MCDisassembler::Fail;
626  } else {
627  for (unsigned i = 0; i < NSAArgs; ++i) {
628  MI.insert(MI.begin() + VAddr0Idx + 1 + i,
629  decodeOperand_VGPR_32(Bytes[i]));
630  }
631  Bytes = Bytes.slice(4 * NSAWords);
632  }
633  }
634 
635  if (Res)
636  Res = convertMIMGInst(MI);
637  }
638 
639  if (Res && IsSDWA)
640  Res = convertSDWAInst(MI);
641 
642  int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
643  AMDGPU::OpName::vdst_in);
644  if (VDstIn_Idx != -1) {
645  int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
647  if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
648  !MI.getOperand(VDstIn_Idx).isReg() ||
649  MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
650  if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
651  MI.erase(&MI.getOperand(VDstIn_Idx));
653  MCOperand::createReg(MI.getOperand(Tied).getReg()),
654  AMDGPU::OpName::vdst_in);
655  }
656  }
657 
658  int ImmLitIdx =
659  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);
660  if (Res && ImmLitIdx != -1)
661  Res = convertFMAanyK(MI, ImmLitIdx);
662 
663  // if the opcode was not recognized we'll assume a Size of 4 bytes
664  // (unless there are fewer bytes left)
665  Size = Res ? (MaxInstBytesNum - Bytes.size())
666  : std::min((size_t)4, Bytes_.size());
667  return Res;
668 }
669 
671  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
672  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
673  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
674  // VOPC - insert clamp
675  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
676  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
677  int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
678  if (SDst != -1) {
679  // VOPC - insert VCC register as sdst
681  AMDGPU::OpName::sdst);
682  } else {
683  // VOP1/2 - insert omod if present in instruction
684  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
685  }
686  }
688 }
689 
690 // We must check FI == literal to reject not genuine dpp8 insts, and we must
691 // first add optional MI operands to check FI
693  unsigned Opc = MI.getOpcode();
694  unsigned DescNumOps = MCII->get(Opc).getNumOperands();
695 
696  // Insert dummy unused src modifiers.
697  if (MI.getNumOperands() < DescNumOps &&
698  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
700  AMDGPU::OpName::src0_modifiers);
701 
702  if (MI.getNumOperands() < DescNumOps &&
703  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
705  AMDGPU::OpName::src1_modifiers);
706 
708 }
709 
710 // Note that before gfx10, the MIMG encoding provided no information about
711 // VADDR size. Consequently, decoded instructions always show address as if it
712 // has 1 dword, which could be not really so.
714 
715  int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
716  AMDGPU::OpName::vdst);
717 
718  int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
719  AMDGPU::OpName::vdata);
720  int VAddr0Idx =
721  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
722  int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
723  AMDGPU::OpName::dmask);
724 
725  int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
726  AMDGPU::OpName::tfe);
727  int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
728  AMDGPU::OpName::d16);
729 
730  const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
731  const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
732  AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
733 
734  assert(VDataIdx != -1);
735  if (BaseOpcode->BVH) {
736  // Add A16 operand for intersect_ray instructions
737  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) {
739  }
741  }
742 
743  bool IsAtomic = (VDstIdx != -1);
744  bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
745  bool IsNSA = false;
746  unsigned AddrSize = Info->VAddrDwords;
747 
748  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
749  unsigned DimIdx =
750  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
751  int A16Idx =
752  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16);
753  const AMDGPU::MIMGDimInfo *Dim =
754  AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
755  const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm());
756 
757  AddrSize =
758  AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI));
759 
760  IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
761  if (!IsNSA) {
762  if (AddrSize > 8)
763  AddrSize = 16;
764  } else {
765  if (AddrSize > Info->VAddrDwords) {
766  // The NSA encoding does not contain enough operands for the combination
767  // of base opcode / dimension. Should this be an error?
769  }
770  }
771  }
772 
773  unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
774  unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
775 
776  bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
777  if (D16 && AMDGPU::hasPackedD16(STI)) {
778  DstSize = (DstSize + 1) / 2;
779  }
780 
781  if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm())
782  DstSize += 1;
783 
784  if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
786 
787  int NewOpcode =
788  AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
789  if (NewOpcode == -1)
791 
792  // Widen the register to the correct number of enabled channels.
793  unsigned NewVdata = AMDGPU::NoRegister;
794  if (DstSize != Info->VDataDwords) {
795  auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
796 
797  // Get first subregister of VData
798  unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
799  unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
800  Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
801 
802  NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
803  &MRI.getRegClass(DataRCID));
804  if (NewVdata == AMDGPU::NoRegister) {
805  // It's possible to encode this such that the low register + enabled
806  // components exceeds the register count.
808  }
809  }
810 
811  unsigned NewVAddr0 = AMDGPU::NoRegister;
812  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
813  AddrSize != Info->VAddrDwords) {
814  unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
815  unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
816  VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
817 
818  auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
819  NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
820  &MRI.getRegClass(AddrRCID));
821  if (NewVAddr0 == AMDGPU::NoRegister)
823  }
824 
825  MI.setOpcode(NewOpcode);
826 
827  if (NewVdata != AMDGPU::NoRegister) {
828  MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
829 
830  if (IsAtomic) {
831  // Atomic operations have an additional operand (a copy of data)
832  MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
833  }
834  }
835 
836  if (NewVAddr0 != AMDGPU::NoRegister) {
837  MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
838  } else if (IsNSA) {
839  assert(AddrSize <= Info->VAddrDwords);
840  MI.erase(MI.begin() + VAddr0Idx + AddrSize,
841  MI.begin() + VAddr0Idx + Info->VAddrDwords);
842  }
843 
845 }
846 
848  int ImmLitIdx) const {
849  assert(HasLiteral && "Should have decoded a literal");
850  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
851  unsigned DescNumOps = Desc.getNumOperands();
852  assert(DescNumOps == MI.getNumOperands());
853  for (unsigned I = 0; I < DescNumOps; ++I) {
854  auto &Op = MI.getOperand(I);
855  auto OpType = Desc.OpInfo[I].OperandType;
856  bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED ||
858  if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST &&
859  IsDeferredOp)
860  Op.setImm(Literal);
861  }
863 }
864 
865 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
866  return getContext().getRegisterInfo()->
867  getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
868 }
869 
870 inline
872  const Twine& ErrMsg) const {
873  *CommentStream << "Error: " + ErrMsg;
874 
875  // ToDo: add support for error operands to MCInst.h
876  // return MCOperand::createError(V);
877  return MCOperand();
878 }
879 
880 inline
882  return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
883 }
884 
885 inline
887  unsigned Val) const {
888  const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
889  if (Val >= RegCl.getNumRegs())
890  return errOperand(Val, Twine(getRegClassName(RegClassID)) +
891  ": unknown register " + Twine(Val));
892  return createRegOperand(RegCl.getRegister(Val));
893 }
894 
895 inline
897  unsigned Val) const {
898  // ToDo: SI/CI have 104 SGPRs, VI - 102
899  // Valery: here we accepting as much as we can, let assembler sort it out
900  int shift = 0;
901  switch (SRegClassID) {
902  case AMDGPU::SGPR_32RegClassID:
903  case AMDGPU::TTMP_32RegClassID:
904  break;
905  case AMDGPU::SGPR_64RegClassID:
906  case AMDGPU::TTMP_64RegClassID:
907  shift = 1;
908  break;
909  case AMDGPU::SGPR_128RegClassID:
910  case AMDGPU::TTMP_128RegClassID:
911  // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
912  // this bundle?
913  case AMDGPU::SGPR_256RegClassID:
914  case AMDGPU::TTMP_256RegClassID:
915  // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
916  // this bundle?
917  case AMDGPU::SGPR_512RegClassID:
918  case AMDGPU::TTMP_512RegClassID:
919  shift = 2;
920  break;
921  // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
922  // this bundle?
923  default:
924  llvm_unreachable("unhandled register class");
925  }
926 
927  if (Val % (1 << shift)) {
928  *CommentStream << "Warning: " << getRegClassName(SRegClassID)
929  << ": scalar reg isn't aligned " << Val;
930  }
931 
932  return createRegOperand(SRegClassID, Val >> shift);
933 }
934 
936  return decodeSrcOp(OPW32, Val);
937 }
938 
940  return decodeSrcOp(OPW64, Val);
941 }
942 
944  return decodeSrcOp(OPW128, Val);
945 }
946 
948  return decodeSrcOp(OPW16, Val);
949 }
950 
952  return decodeSrcOp(OPWV216, Val);
953 }
954 
956  return decodeSrcOp(OPWV232, Val);
957 }
958 
960  // Some instructions have operand restrictions beyond what the encoding
961  // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
962  // high bit.
963  Val &= 255;
964 
965  return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
966 }
967 
969  return decodeSrcOp(OPW32, Val);
970 }
971 
973  return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
974 }
975 
977  return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255);
978 }
979 
981  return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
982 }
983 
985  return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255);
986 }
987 
989  return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
990 }
991 
993  return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
994 }
995 
997  return decodeSrcOp(OPW32, Val);
998 }
999 
1001  return decodeSrcOp(OPW64, Val);
1002 }
1003 
1005  return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
1006 }
1007 
1009  return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
1010 }
1011 
1013  return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
1014 }
1015 
1017  return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
1018 }
1019 
1021  return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
1022 }
1023 
1025  return createRegOperand(AMDGPU::VReg_1024RegClassID, Val);
1026 }
1027 
1029  // table-gen generated disassembler doesn't care about operand types
1030  // leaving only registry class so SSrc_32 operand turns into SReg_32
1031  // and therefore we accept immediates and literals here as well
1032  return decodeSrcOp(OPW32, Val);
1033 }
1034 
1036  unsigned Val) const {
1037  // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
1038  return decodeOperand_SReg_32(Val);
1039 }
1040 
1042  unsigned Val) const {
1043  // SReg_32_XM0 is SReg_32 without EXEC_HI
1044  return decodeOperand_SReg_32(Val);
1045 }
1046 
1048  // table-gen generated disassembler doesn't care about operand types
1049  // leaving only registry class so SSrc_32 operand turns into SReg_32
1050  // and therefore we accept immediates and literals here as well
1051  return decodeSrcOp(OPW32, Val);
1052 }
1053 
1055  return decodeSrcOp(OPW64, Val);
1056 }
1057 
1059  return decodeSrcOp(OPW64, Val);
1060 }
1061 
1063  return decodeSrcOp(OPW128, Val);
1064 }
1065 
1067  return decodeDstOp(OPW256, Val);
1068 }
1069 
1071  return decodeDstOp(OPW512, Val);
1072 }
1073 
1074 // Decode Literals for insts which always have a literal in the encoding
1075 MCOperand
1077  if (HasLiteral) {
1078  if (Literal != Val)
1079  return errOperand(Val, "More than one unique literal is illegal");
1080  }
1081  HasLiteral = true;
1082  Literal = Val;
1083  return MCOperand::createImm(Literal);
1084 }
1085 
1087  // For now all literal constants are supposed to be unsigned integer
1088  // ToDo: deal with signed/unsigned 64-bit integer constants
1089  // ToDo: deal with float/double constants
1090  if (!HasLiteral) {
1091  if (Bytes.size() < 4) {
1092  return errOperand(0, "cannot read literal, inst bytes left " +
1093  Twine(Bytes.size()));
1094  }
1095  HasLiteral = true;
1096  Literal = eatBytes<uint32_t>(Bytes);
1097  }
1098  return MCOperand::createImm(Literal);
1099 }
1100 
1102  using namespace AMDGPU::EncValues;
1103 
1106  (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
1107  (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
1108  // Cast prevents negative overflow.
1109 }
1110 
1111 static int64_t getInlineImmVal32(unsigned Imm) {
1112  switch (Imm) {
1113  case 240:
1114  return FloatToBits(0.5f);
1115  case 241:
1116  return FloatToBits(-0.5f);
1117  case 242:
1118  return FloatToBits(1.0f);
1119  case 243:
1120  return FloatToBits(-1.0f);
1121  case 244:
1122  return FloatToBits(2.0f);
1123  case 245:
1124  return FloatToBits(-2.0f);
1125  case 246:
1126  return FloatToBits(4.0f);
1127  case 247:
1128  return FloatToBits(-4.0f);
1129  case 248: // 1 / (2 * PI)
1130  return 0x3e22f983;
1131  default:
1132  llvm_unreachable("invalid fp inline imm");
1133  }
1134 }
1135 
1136 static int64_t getInlineImmVal64(unsigned Imm) {
1137  switch (Imm) {
1138  case 240:
1139  return DoubleToBits(0.5);
1140  case 241:
1141  return DoubleToBits(-0.5);
1142  case 242:
1143  return DoubleToBits(1.0);
1144  case 243:
1145  return DoubleToBits(-1.0);
1146  case 244:
1147  return DoubleToBits(2.0);
1148  case 245:
1149  return DoubleToBits(-2.0);
1150  case 246:
1151  return DoubleToBits(4.0);
1152  case 247:
1153  return DoubleToBits(-4.0);
1154  case 248: // 1 / (2 * PI)
1155  return 0x3fc45f306dc9c882;
1156  default:
1157  llvm_unreachable("invalid fp inline imm");
1158  }
1159 }
1160 
1161 static int64_t getInlineImmVal16(unsigned Imm) {
1162  switch (Imm) {
1163  case 240:
1164  return 0x3800;
1165  case 241:
1166  return 0xB800;
1167  case 242:
1168  return 0x3C00;
1169  case 243:
1170  return 0xBC00;
1171  case 244:
1172  return 0x4000;
1173  case 245:
1174  return 0xC000;
1175  case 246:
1176  return 0x4400;
1177  case 247:
1178  return 0xC400;
1179  case 248: // 1 / (2 * PI)
1180  return 0x3118;
1181  default:
1182  llvm_unreachable("invalid fp inline imm");
1183  }
1184 }
1185 
1189 
1190  // ToDo: case 248: 1/(2*PI) - is allowed only on VI
1191  switch (Width) {
1192  case OPW32:
1193  case OPW128: // splat constants
1194  case OPW512:
1195  case OPW1024:
1196  case OPWV232:
1198  case OPW64:
1199  case OPW256:
1201  case OPW16:
1202  case OPWV216:
1204  default:
1205  llvm_unreachable("implement me");
1206  }
1207 }
1208 
1210  using namespace AMDGPU;
1211 
1213  switch (Width) {
1214  default: // fall
1215  case OPW32:
1216  case OPW16:
1217  case OPWV216:
1218  return VGPR_32RegClassID;
1219  case OPW64:
1220  case OPWV232: return VReg_64RegClassID;
1221  case OPW96: return VReg_96RegClassID;
1222  case OPW128: return VReg_128RegClassID;
1223  case OPW160: return VReg_160RegClassID;
1224  case OPW256: return VReg_256RegClassID;
1225  case OPW512: return VReg_512RegClassID;
1226  case OPW1024: return VReg_1024RegClassID;
1227  }
1228 }
1229 
1231  using namespace AMDGPU;
1232 
1234  switch (Width) {
1235  default: // fall
1236  case OPW32:
1237  case OPW16:
1238  case OPWV216:
1239  return AGPR_32RegClassID;
1240  case OPW64:
1241  case OPWV232: return AReg_64RegClassID;
1242  case OPW96: return AReg_96RegClassID;
1243  case OPW128: return AReg_128RegClassID;
1244  case OPW160: return AReg_160RegClassID;
1245  case OPW256: return AReg_256RegClassID;
1246  case OPW512: return AReg_512RegClassID;
1247  case OPW1024: return AReg_1024RegClassID;
1248  }
1249 }
1250 
1251 
1253  using namespace AMDGPU;
1254 
1256  switch (Width) {
1257  default: // fall
1258  case OPW32:
1259  case OPW16:
1260  case OPWV216:
1261  return SGPR_32RegClassID;
1262  case OPW64:
1263  case OPWV232: return SGPR_64RegClassID;
1264  case OPW96: return SGPR_96RegClassID;
1265  case OPW128: return SGPR_128RegClassID;
1266  case OPW160: return SGPR_160RegClassID;
1267  case OPW256: return SGPR_256RegClassID;
1268  case OPW512: return SGPR_512RegClassID;
1269  }
1270 }
1271 
1273  using namespace AMDGPU;
1274 
1276  switch (Width) {
1277  default: // fall
1278  case OPW32:
1279  case OPW16:
1280  case OPWV216:
1281  return TTMP_32RegClassID;
1282  case OPW64:
1283  case OPWV232: return TTMP_64RegClassID;
1284  case OPW128: return TTMP_128RegClassID;
1285  case OPW256: return TTMP_256RegClassID;
1286  case OPW512: return TTMP_512RegClassID;
1287  }
1288 }
1289 
1290 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1291  using namespace AMDGPU::EncValues;
1292 
1293  unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1294  unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1295 
1296  return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1297 }
1298 
1300  bool MandatoryLiteral) const {
1301  using namespace AMDGPU::EncValues;
1302 
1303  assert(Val < 1024); // enum10
1304 
1305  bool IsAGPR = Val & 512;
1306  Val &= 511;
1307 
1308  if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1309  return createRegOperand(IsAGPR ? getAgprClassId(Width)
1310  : getVgprClassId(Width), Val - VGPR_MIN);
1311  }
1312  if (Val <= SGPR_MAX) {
1313  // "SGPR_MIN <= Val" is always true and causes compilation warning.
1314  static_assert(SGPR_MIN == 0, "");
1316  }
1317 
1318  int TTmpIdx = getTTmpIdx(Val);
1319  if (TTmpIdx >= 0) {
1320  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1321  }
1322 
1323  if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1324  return decodeIntImmed(Val);
1325 
1326  if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1327  return decodeFPImmed(Width, Val);
1328 
1329  if (Val == LITERAL_CONST) {
1330  if (MandatoryLiteral)
1331  // Keep a sentinel value for deferred setting
1333  else
1334  return decodeLiteralConstant();
1335  }
1336 
1337  switch (Width) {
1338  case OPW32:
1339  case OPW16:
1340  case OPWV216:
1341  return decodeSpecialReg32(Val);
1342  case OPW64:
1343  case OPWV232:
1344  return decodeSpecialReg64(Val);
1345  default:
1346  llvm_unreachable("unexpected immediate type");
1347  }
1348 }
1349 
1351  using namespace AMDGPU::EncValues;
1352 
1353  assert(Val < 128);
1354  assert(Width == OPW256 || Width == OPW512);
1355 
1356  if (Val <= SGPR_MAX) {
1357  // "SGPR_MIN <= Val" is always true and causes compilation warning.
1358  static_assert(SGPR_MIN == 0, "");
1360  }
1361 
1362  int TTmpIdx = getTTmpIdx(Val);
1363  if (TTmpIdx >= 0) {
1364  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1365  }
1366 
1367  llvm_unreachable("unknown dst register");
1368 }
1369 
1371  using namespace AMDGPU;
1372 
1373  switch (Val) {
1374  case 102: return createRegOperand(FLAT_SCR_LO);
1375  case 103: return createRegOperand(FLAT_SCR_HI);
1376  case 104: return createRegOperand(XNACK_MASK_LO);
1377  case 105: return createRegOperand(XNACK_MASK_HI);
1378  case 106: return createRegOperand(VCC_LO);
1379  case 107: return createRegOperand(VCC_HI);
1380  case 108: return createRegOperand(TBA_LO);
1381  case 109: return createRegOperand(TBA_HI);
1382  case 110: return createRegOperand(TMA_LO);
1383  case 111: return createRegOperand(TMA_HI);
1384  case 124: return createRegOperand(M0);
1385  case 125: return createRegOperand(SGPR_NULL);
1386  case 126: return createRegOperand(EXEC_LO);
1387  case 127: return createRegOperand(EXEC_HI);
1388  case 235: return createRegOperand(SRC_SHARED_BASE);
1389  case 236: return createRegOperand(SRC_SHARED_LIMIT);
1390  case 237: return createRegOperand(SRC_PRIVATE_BASE);
1391  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1392  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1393  case 251: return createRegOperand(SRC_VCCZ);
1394  case 252: return createRegOperand(SRC_EXECZ);
1395  case 253: return createRegOperand(SRC_SCC);
1396  case 254: return createRegOperand(LDS_DIRECT);
1397  default: break;
1398  }
1399  return errOperand(Val, "unknown operand encoding " + Twine(Val));
1400 }
1401 
1403  using namespace AMDGPU;
1404 
1405  switch (Val) {
1406  case 102: return createRegOperand(FLAT_SCR);
1407  case 104: return createRegOperand(XNACK_MASK);
1408  case 106: return createRegOperand(VCC);
1409  case 108: return createRegOperand(TBA);
1410  case 110: return createRegOperand(TMA);
1411  case 125: return createRegOperand(SGPR_NULL);
1412  case 126: return createRegOperand(EXEC);
1413  case 235: return createRegOperand(SRC_SHARED_BASE);
1414  case 236: return createRegOperand(SRC_SHARED_LIMIT);
1415  case 237: return createRegOperand(SRC_PRIVATE_BASE);
1416  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1417  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1418  case 251: return createRegOperand(SRC_VCCZ);
1419  case 252: return createRegOperand(SRC_EXECZ);
1420  case 253: return createRegOperand(SRC_SCC);
1421  default: break;
1422  }
1423  return errOperand(Val, "unknown operand encoding " + Twine(Val));
1424 }
1425 
1427  const unsigned Val) const {
1428  using namespace AMDGPU::SDWA;
1429  using namespace AMDGPU::EncValues;
1430 
1431  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1432  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1433  // XXX: cast to int is needed to avoid stupid warning:
1434  // compare with unsigned is always true
1435  if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1439  }
1440  if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1445  }
1446  if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1450  }
1451 
1452  const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1453 
1454  if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1455  return decodeIntImmed(SVal);
1456 
1457  if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1458  return decodeFPImmed(Width, SVal);
1459 
1460  return decodeSpecialReg32(SVal);
1461  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1462  return createRegOperand(getVgprClassId(Width), Val);
1463  }
1464  llvm_unreachable("unsupported target");
1465 }
1466 
1468  return decodeSDWASrc(OPW16, Val);
1469 }
1470 
1472  return decodeSDWASrc(OPW32, Val);
1473 }
1474 
1476  using namespace AMDGPU::SDWA;
1477 
1478  assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1479  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1480  "SDWAVopcDst should be present only on GFX9+");
1481 
1482  bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1483 
1486 
1487  int TTmpIdx = getTTmpIdx(Val);
1488  if (TTmpIdx >= 0) {
1489  auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1490  return createSRegOperand(TTmpClsId, TTmpIdx);
1491  } else if (Val > SGPR_MAX) {
1492  return IsWave64 ? decodeSpecialReg64(Val)
1493  : decodeSpecialReg32(Val);
1494  } else {
1495  return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1496  }
1497  } else {
1498  return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1499  }
1500 }
1501 
1503  return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1505 }
1506 
1508  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1509 }
1510 
1512 
1514  return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
1515 }
1516 
1518 
1520 
1522  return AMDGPU::isGFX10Plus(STI);
1523 }
1524 
1526  return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
1527 }
1528 
1529 //===----------------------------------------------------------------------===//
1530 // AMDGPU specific symbol handling
1531 //===----------------------------------------------------------------------===//
1532 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1533  do { \
1534  KdStream << Indent << DIRECTIVE " " \
1535  << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1536  } while (0)
1537 
1538 // NOLINTNEXTLINE(readability-identifier-naming)
1540  uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1541  using namespace amdhsa;
1542  StringRef Indent = "\t";
1543 
1544  // We cannot accurately backward compute #VGPRs used from
1545  // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same
1546  // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we
1547  // simply calculate the inverse of what the assembler does.
1548 
1549  uint32_t GranulatedWorkitemVGPRCount =
1550  (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >>
1551  COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT;
1552 
1553  uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) *
1555 
1556  KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n';
1557 
1558  // We cannot backward compute values used to calculate
1559  // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following
1560  // directives can't be computed:
1561  // .amdhsa_reserve_vcc
1562  // .amdhsa_reserve_flat_scratch
1563  // .amdhsa_reserve_xnack_mask
1564  // They take their respective default values if not specified in the assembly.
1565  //
1566  // GRANULATED_WAVEFRONT_SGPR_COUNT
1567  // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK)
1568  //
1569  // We compute the inverse as though all directives apart from NEXT_FREE_SGPR
1570  // are set to 0. So while disassembling we consider that:
1571  //
1572  // GRANULATED_WAVEFRONT_SGPR_COUNT
1573  // = f(NEXT_FREE_SGPR + 0 + 0 + 0)
1574  //
1575  // The disassembler cannot recover the original values of those 3 directives.
1576 
1577  uint32_t GranulatedWavefrontSGPRCount =
1578  (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
1579  COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
1580 
1581  if (isGFX10Plus() && GranulatedWavefrontSGPRCount)
1582  return MCDisassembler::Fail;
1583 
1584  uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1586 
1587  KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n';
1589  KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n';
1590  KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n';
1591  KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n";
1592 
1593  if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1594  return MCDisassembler::Fail;
1595 
1596  PRINT_DIRECTIVE(".amdhsa_float_round_mode_32",
1597  COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1598  PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64",
1599  COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1600  PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32",
1601  COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1602  PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64",
1603  COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1604 
1605  if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1606  return MCDisassembler::Fail;
1607 
1608  PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1609 
1610  if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1611  return MCDisassembler::Fail;
1612 
1613  PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1614 
1615  if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1616  return MCDisassembler::Fail;
1617 
1618  if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1619  return MCDisassembler::Fail;
1620 
1621  PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1622 
1623  if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1624  return MCDisassembler::Fail;
1625 
1626  if (isGFX10Plus()) {
1627  PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
1628  COMPUTE_PGM_RSRC1_WGP_MODE);
1629  PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1630  PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1631  }
1632  return MCDisassembler::Success;
1633 }
1634 
1635 // NOLINTNEXTLINE(readability-identifier-naming)
1637  uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1638  using namespace amdhsa;
1639  StringRef Indent = "\t";
1641  PRINT_DIRECTIVE(".amdhsa_enable_private_segment",
1642  COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1643  else
1644  PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset",
1645  COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1646  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x",
1647  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1648  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y",
1649  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1650  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z",
1651  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1652  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info",
1653  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1654  PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id",
1655  COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1656 
1657  if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1658  return MCDisassembler::Fail;
1659 
1660  if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1661  return MCDisassembler::Fail;
1662 
1663  if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1664  return MCDisassembler::Fail;
1665 
1667  ".amdhsa_exception_fp_ieee_invalid_op",
1668  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1669  PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src",
1670  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1672  ".amdhsa_exception_fp_ieee_div_zero",
1673  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1674  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow",
1675  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1676  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow",
1677  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1678  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact",
1679  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1680  PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero",
1681  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1682 
1683  if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1684  return MCDisassembler::Fail;
1685 
1686  return MCDisassembler::Success;
1687 }
1688 
1689 #undef PRINT_DIRECTIVE
1690 
1694  raw_string_ostream &KdStream) const {
1695 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1696  do { \
1697  KdStream << Indent << DIRECTIVE " " \
1698  << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1699  } while (0)
1700 
1701  uint16_t TwoByteBuffer = 0;
1702  uint32_t FourByteBuffer = 0;
1703 
1704  StringRef ReservedBytes;
1705  StringRef Indent = "\t";
1706 
1707  assert(Bytes.size() == 64);
1708  DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8);
1709 
1710  switch (Cursor.tell()) {
1712  FourByteBuffer = DE.getU32(Cursor);
1713  KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer
1714  << '\n';
1715  return MCDisassembler::Success;
1716 
1718  FourByteBuffer = DE.getU32(Cursor);
1719  KdStream << Indent << ".amdhsa_private_segment_fixed_size "
1720  << FourByteBuffer << '\n';
1721  return MCDisassembler::Success;
1722 
1724  FourByteBuffer = DE.getU32(Cursor);
1725  KdStream << Indent << ".amdhsa_kernarg_size "
1726  << FourByteBuffer << '\n';
1727  return MCDisassembler::Success;
1728 
1730  // 4 reserved bytes, must be 0.
1731  ReservedBytes = DE.getBytes(Cursor, 4);
1732  for (int I = 0; I < 4; ++I) {
1733  if (ReservedBytes[I] != 0) {
1734  return MCDisassembler::Fail;
1735  }
1736  }
1737  return MCDisassembler::Success;
1738 
1740  // KERNEL_CODE_ENTRY_BYTE_OFFSET
1741  // So far no directive controls this for Code Object V3, so simply skip for
1742  // disassembly.
1743  DE.skip(Cursor, 8);
1744  return MCDisassembler::Success;
1745 
1747  // 20 reserved bytes, must be 0.
1748  ReservedBytes = DE.getBytes(Cursor, 20);
1749  for (int I = 0; I < 20; ++I) {
1750  if (ReservedBytes[I] != 0) {
1751  return MCDisassembler::Fail;
1752  }
1753  }
1754  return MCDisassembler::Success;
1755 
1757  // COMPUTE_PGM_RSRC3
1758  // - Only set for GFX10, GFX6-9 have this to be 0.
1759  // - Currently no directives directly control this.
1760  FourByteBuffer = DE.getU32(Cursor);
1761  if (!isGFX10Plus() && FourByteBuffer) {
1762  return MCDisassembler::Fail;
1763  }
1764  return MCDisassembler::Success;
1765 
1767  FourByteBuffer = DE.getU32(Cursor);
1768  if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) ==
1770  return MCDisassembler::Fail;
1771  }
1772  return MCDisassembler::Success;
1773 
1775  FourByteBuffer = DE.getU32(Cursor);
1776  if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) ==
1778  return MCDisassembler::Fail;
1779  }
1780  return MCDisassembler::Success;
1781 
1783  using namespace amdhsa;
1784  TwoByteBuffer = DE.getU16(Cursor);
1785 
1787  PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer",
1788  KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
1789  PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr",
1790  KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
1791  PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr",
1792  KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
1793  PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr",
1794  KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
1795  PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id",
1796  KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
1798  PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init",
1799  KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
1800  PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size",
1801  KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
1802 
1803  if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
1804  return MCDisassembler::Fail;
1805 
1806  // Reserved for GFX9
1807  if (isGFX9() &&
1808  (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
1809  return MCDisassembler::Fail;
1810  } else if (isGFX10Plus()) {
1811  PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
1812  KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
1813  }
1814 
1815  if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
1816  return MCDisassembler::Fail;
1817 
1818  return MCDisassembler::Success;
1819 
1821  // 6 bytes from here are reserved, must be 0.
1822  ReservedBytes = DE.getBytes(Cursor, 6);
1823  for (int I = 0; I < 6; ++I) {
1824  if (ReservedBytes[I] != 0)
1825  return MCDisassembler::Fail;
1826  }
1827  return MCDisassembler::Success;
1828 
1829  default:
1830  llvm_unreachable("Unhandled index. Case statements cover everything.");
1831  return MCDisassembler::Fail;
1832  }
1833 #undef PRINT_DIRECTIVE
1834 }
1835 
1837  StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const {
1838  // CP microcode requires the kernel descriptor to be 64 aligned.
1839  if (Bytes.size() != 64 || KdAddress % 64 != 0)
1840  return MCDisassembler::Fail;
1841 
1842  std::string Kd;
1843  raw_string_ostream KdStream(Kd);
1844  KdStream << ".amdhsa_kernel " << KdName << '\n';
1845 
1847  while (C && C.tell() < Bytes.size()) {
1849  decodeKernelDescriptorDirective(C, Bytes, KdStream);
1850 
1851  cantFail(C.takeError());
1852 
1854  return MCDisassembler::Fail;
1855  }
1856  KdStream << ".end_amdhsa_kernel\n";
1857  outs() << KdStream.str();
1858  return MCDisassembler::Success;
1859 }
1860 
1863  ArrayRef<uint8_t> Bytes, uint64_t Address,
1864  raw_ostream &CStream) const {
1865  // Right now only kernel descriptor needs to be handled.
1866  // We ignore all other symbols for target specific handling.
1867  // TODO:
1868  // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code
1869  // Object V2 and V3 when symbols are marked protected.
1870 
1871  // amd_kernel_code_t for Code Object V2.
1872  if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) {
1873  Size = 256;
1874  return MCDisassembler::Fail;
1875  }
1876 
1877  // Code Object V3 kernel descriptors.
1878  StringRef Name = Symbol.Name;
1879  if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) {
1880  Size = 64; // Size = 64 regardless of success or failure.
1881  return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address);
1882  }
1883  return None;
1884 }
1885 
1886 //===----------------------------------------------------------------------===//
1887 // AMDGPUSymbolizer
1888 //===----------------------------------------------------------------------===//
1889 
1890 // Try to find symbol name for specified label
1892  raw_ostream &/*cStream*/, int64_t Value,
1893  uint64_t /*Address*/, bool IsBranch,
1894  uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1895 
1896  if (!IsBranch) {
1897  return false;
1898  }
1899 
1900  auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1901  if (!Symbols)
1902  return false;
1903 
1904  auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) {
1905  return Val.Addr == static_cast<uint64_t>(Value) &&
1906  Val.Type == ELF::STT_NOTYPE;
1907  });
1908  if (Result != Symbols->end()) {
1909  auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1910  const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1911  Inst.addOperand(MCOperand::createExpr(Add));
1912  return true;
1913  }
1914  // Add to list of referenced addresses, so caller can synthesize a label.
1915  ReferencedAddresses.push_back(static_cast<uint64_t>(Value));
1916  return false;
1917 }
1918 
1920  int64_t Value,
1921  uint64_t Address) {
1922  llvm_unreachable("unimplemented");
1923 }
1924 
1925 //===----------------------------------------------------------------------===//
1926 // Initialization
1927 //===----------------------------------------------------------------------===//
1928 
1930  LLVMOpInfoCallback /*GetOpInfo*/,
1931  LLVMSymbolLookupCallback /*SymbolLookUp*/,
1932  void *DisInfo,
1933  MCContext *Ctx,
1934  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1935  return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1936 }
1937 
1939  const MCSubtargetInfo &STI,
1940  MCContext &Ctx) {
1941  return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1942 }
1943 
1949 }
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::AMDGPUDisassembler::decodeSDWASrc32
MCOperand decodeSDWASrc32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1471
i
i
Definition: README.txt:29
MCFixedLenDisassembler.h
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1545
llvm::AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1058
llvm::AMDGPUDisassembler::convertDPP8Inst
DecodeStatus convertDPP8Inst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:692
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1035
DECODE_SDWA
#define DECODE_SDWA(DecName)
Definition: AMDGPUDisassembler.cpp:393
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::AMDGPUSymbolizer::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Definition: AMDGPUDisassembler.cpp:1891
llvm::AMDGPUDisassembler::decodeOperand_SReg_256
MCOperand decodeOperand_SReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1066
llvm::AMDGPU::DPP::DPP8_FI_0
@ DPP8_FI_0
Definition: SIDefines.h:734
decodeOperand_VReg_256
static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:244
llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Definition: AMDGPUDisassembler.cpp:1692
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::AMDGPUDisassembler::decodeDstOp
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1350
llvm::AMDGPUDisassembler::OpWidthTy
OpWidthTy
Definition: AMDGPUDisassembler.h:131
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:59
MCInstrDesc.h
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:53
llvm::AMDGPU::EncValues::VGPR_MIN
@ VGPR_MIN
Definition: SIDefines.h:281
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:72
llvm::SymbolInfoTy
Definition: MCDisassembler.h:33
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:425
llvm::AMDGPUDisassembler::decodeFPImmed
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1186
llvm::AMDGPUDisassembler::isVI
bool isVI() const
Definition: AMDGPUDisassembler.cpp:1507
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:625
decodeOperand_AReg_512
static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:212
llvm::AMDGPUDisassembler::getTtmpClassId
unsigned getTtmpClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1272
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::AMDGPUDisassembler::isGFX90A
bool isGFX90A() const
Definition: AMDGPUDisassembler.cpp:1513
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Definition: AMDGPUDisassembler.cpp:1539
llvm::AMDGPUDisassembler::isGFX9
bool isGFX9() const
Definition: AMDGPUDisassembler.cpp:1511
llvm::AMDGPUDisassembler::decodeOperand_VS_128
MCOperand decodeOperand_VS_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:943
llvm::AMDGPU::MIMGDimInfo
Definition: AMDGPUBaseInfo.h:304
llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET
@ KERNEL_CODE_PROPERTIES_OFFSET
Definition: AMDHSAKernelDescriptor.h:189
llvm::AMDGPU::DPP
Definition: SIDefines.h:682
llvm::AMDGPU::DPP::DPP8_FI_1
@ DPP8_FI_1
Definition: SIDefines.h:735
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX
@ INLINE_FLOATING_C_MAX
Definition: SIDefines.h:279
llvm::AMDGPUSymbolizer
Definition: AMDGPUDisassembler.h:188
llvm::AMDGPUDisassembler::convertMIMGInst
DecodeStatus convertMIMGInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:713
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
decodeOperand_VSrc16
static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:148
llvm::AMDGPUDisassembler::decodeOperand_AReg_128
MCOperand decodeOperand_AReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:980
DECODE_OPERAND_REG
#define DECODE_OPERAND_REG(RegClass)
Definition: AMDGPUDisassembler.cpp:113
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:56
llvm::MCDisassembler::SoftFail
@ SoftFail
Definition: MCDisassembler.h:102
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1041
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:663
llvm::AMDGPUSymbolizer::tryAddingPcLoadReferenceComment
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Definition: AMDGPUDisassembler.cpp:1919
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1453
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:916
llvm::AMDGPU::EncValues::LITERAL_CONST
@ LITERAL_CONST
Definition: SIDefines.h:280
llvm::Optional
Definition: APInt.h:33
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_SI
@ SRC_SGPR_MAX_SI
Definition: SIDefines.h:674
llvm::AMDGPUDisassembler::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch() const
Definition: AMDGPUDisassembler.cpp:1525
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK
@ VOPC_DST_SGPR_MASK
Definition: SIDefines.h:669
llvm::AMDGPUDisassembler::decodeSDWAVopcDst
MCOperand decodeSDWAVopcDst(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1475
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
decodeOperand_VSrcV216
static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:156
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX
@ INLINE_INTEGER_C_MAX
Definition: SIDefines.h:277
DecodeAVLdSt_128RegisterClass
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:369
llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH
bool BVH
Definition: AMDGPUBaseInfo.h:295
llvm::AMDGPUDisassembler::decodeBoolReg
MCOperand decodeBoolReg(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1502
llvm::MCRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: MCRegisterInfo.cpp:32
llvm::AMDGPU::SDWA::SRC_VGPR_MAX
@ SRC_VGPR_MAX
Definition: SIDefines.h:672
llvm::DataExtractor::skip
void skip(Cursor &C, uint64_t Length) const
Advance the Cursor position by the given number of bytes.
Definition: DataExtractor.cpp:229
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:55
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
llvm::AMDGPUDisassembler
Definition: AMDGPUDisassembler.h:34
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:162
llvm::AMDGPUDisassembler::decodeSpecialReg64
MCOperand decodeSpecialReg64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1402
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
@ KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
Definition: AMDHSAKernelDescriptor.h:184
AMDHSAKernelDescriptor.h
decodeOperand_AReg_64
static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:188
llvm::AMDGPUDisassembler::OPW512
@ OPW512
Definition: AMDGPUDisassembler.h:138
llvm::AMDGPUDisassembler::decodeOperand_AV_32
MCOperand decodeOperand_AV_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:996
llvm::AMDGPUDisassembler::decodeOperand_VReg_96
MCOperand decodeOperand_VReg_96(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1008
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:58
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:601
llvm::AMDGPUDisassembler::isGFX9Plus
bool isGFX9Plus() const
Definition: AMDGPUDisassembler.cpp:1517
decodeOperand_f16kimm
static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:274
llvm::AMDGPU::CPol::CPol
CPol
Definition: SIDefines.h:291
llvm::DataExtractor::getBytes
StringRef getBytes(uint64_t *OffsetPtr, uint64_t Length, Error *Err=nullptr) const
Extract a fixed number of bytes from the specified offset.
Definition: DataExtractor.cpp:181
llvm::MCRegisterInfo::getRegClass
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: MCRegisterInfo.h:543
llvm::AMDGPUDisassembler::OPW_LAST_
@ OPW_LAST_
Definition: AMDGPUDisassembler.h:143
decodeOperand_VS_16
static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:172
llvm::outs
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
Definition: raw_ostream.cpp:885
llvm::SymbolInfoTy::Addr
uint64_t Addr
Definition: MCDisassembler.h:34
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:42
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::AMDGPUDisassembler::getRegClassName
const char * getRegClassName(unsigned RegClassID) const
Definition: AMDGPUDisassembler.cpp:865
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:280
llvm::AMDGPUDisassembler::OPWV232
@ OPWV232
Definition: AMDGPUDisassembler.h:142
llvm::AMDGPUDisassembler::createSRegOperand
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:896
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
AMDGPUTargetInfo.h
llvm::AMDGPU::EncValues::VGPR_MAX
@ VGPR_MAX
Definition: SIDefines.h:282
llvm::AMDGPUDisassembler::OPWV216
@ OPWV216
Definition: AMDGPUDisassembler.h:141
MCContext.h
llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET
@ COMPUTE_PGM_RSRC3_OFFSET
Definition: AMDHSAKernelDescriptor.h:186
llvm::AMDGPU::SDWA::SRC_TTMP_MAX
@ SRC_TTMP_MAX
Definition: SIDefines.h:677
llvm::AMDGPUDisassembler::decodeOperand_VReg_128
MCOperand decodeOperand_VReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1012
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:103
llvm::AMDGPUDisassembler::decodeOperand_AV_64
MCOperand decodeOperand_AV_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1000
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:653
eatBytes
static T eatBytes(ArrayRef< uint8_t > &Bytes)
Definition: AMDGPUDisassembler.cpp:406
llvm::AMDGPUDisassembler::OPW_FIRST_
@ OPW_FIRST_
Definition: AMDGPUDisassembler.h:144
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:192
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::AMDGPUDisassembler::OPW16
@ OPW16
Definition: AMDGPUDisassembler.h:140
llvm::AMDGPUDisassembler::decodeOperand_AReg_256
MCOperand decodeOperand_AReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:984
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:111
decodeOperand_f32kimm
static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:268
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:371
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::amdhsa::RESERVED2_OFFSET
@ RESERVED2_OFFSET
Definition: AMDHSAKernelDescriptor.h:190
llvm::SectionSymbolsTy
std::vector< SymbolInfoTy > SectionSymbolsTy
Definition: MCDisassembler.h:66
decodeBoolReg
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:98
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AMDGPUDisassembler::decodeSDWASrc
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1426
llvm::AMDGPUDisassembler::getInstruction
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Definition: AMDGPUDisassembler.cpp:443
llvm::AMDGPUDisassembler::decodeOperand_AReg_512
MCOperand decodeOperand_AReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:988
llvm::AMDGPUDisassembler::decodeOperand_VSrcV216
MCOperand decodeOperand_VSrcV216(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:951
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:138
decodeOperand_VReg_512
static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:252
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:195
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:100
llvm::None
const NoneType None
Definition: None.h:23
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:170
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1457
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
Definition: AMDGPUDisassembler.cpp:1636
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1429
llvm::AMDGPUDisassembler::onSymbolStart
Optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
Definition: AMDGPUDisassembler.cpp:1862
llvm::AMDGPUDisassembler::decodeOperand_VSrc16
MCOperand decodeOperand_VSrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:947
llvm::AMDGPUDisassembler::decodeOperand_VS_32
MCOperand decodeOperand_VS_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:935
llvm::AMDGPUDisassembler::decodeOperand_VReg_1024
MCOperand decodeOperand_VReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1024
llvm::AMDGPUDisassembler::getSgprClassId
unsigned getSgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1252
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:122
llvm::AMDGPUDisassembler::OPW256
@ OPW256
Definition: AMDGPUDisassembler.h:137
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:150
llvm::AMDGPUDisassembler::getAgprClassId
unsigned getAgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1230
llvm::AMDGPUDisassembler::isGFX10Plus
bool isGFX10Plus() const
Definition: AMDGPUDisassembler.cpp:1521
llvm::AMDGPUDisassembler::decodeOperand_SReg_128
MCOperand decodeOperand_SReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1062
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
llvm::AMDGPUDisassembler::isGFX10
bool isGFX10() const
Definition: AMDGPUDisassembler.cpp:1519
llvm::AMDGPUDisassembler::decodeOperand_VRegOrLds_32
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:968
llvm::AMDGPU::hasG16
bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1425
AMDGPUMCTargetDesc.h
LLVMSymbolLookupCallback
const typedef char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:112
llvm::AMDGPU::SDWA::SRC_VGPR_MIN
@ SRC_VGPR_MIN
Definition: SIDefines.h:671
decodeSMEMOffset
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:86
llvm::AMDGPU::EncValues::TTMP_VI_MAX
@ TTMP_VI_MAX
Definition: SIDefines.h:272
llvm::AMDGPU::CPol::GLC
@ GLC
Definition: SIDefines.h:292
llvm::AMDGPUDisassembler::tryDecodeInst
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
Definition: AMDGPUDisassembler.cpp:413
decodeOperand_VS_32_Deferred
static DecodeStatus decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:288
uint64_t
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN
@ INLINE_INTEGER_C_MIN
Definition: SIDefines.h:275
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN
@ INLINE_FLOATING_C_MIN
Definition: SIDefines.h:278
SGPR_MAX
#define SGPR_MAX
Definition: AMDGPUDisassembler.cpp:36
llvm::amdhsa::RESERVED0_OFFSET
@ RESERVED0_OFFSET
Definition: AMDHSAKernelDescriptor.h:183
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:80
llvm::MCOperand::isValid
bool isValid() const
Definition: MCInst.h:60
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1445
llvm::AMDGPUDisassembler::convertFMAanyK
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
Definition: AMDGPUDisassembler.cpp:847
llvm::AMDGPUDisassembler::OPW64
@ OPW64
Definition: AMDGPUDisassembler.h:133
llvm::AMDGPUDisassembler::errOperand
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
Definition: AMDGPUDisassembler.cpp:871
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:76
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:95
decodeOperand_VGPR_32
static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:385
llvm::AMDGPUDisassembler::decodeOperand_SRegOrLds_32
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1047
llvm::AMDGPUDisassembler::decodeOperand_VReg_64
MCOperand decodeOperand_VReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1004
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::AMDGPUDisassembler::decodeOperand_VReg_256
MCOperand decodeOperand_VReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1016
llvm::AMDGPUDisassembler::decodeLiteralConstant
MCOperand decodeLiteralConstant() const
Definition: AMDGPUDisassembler.cpp:1086
llvm::HighlightColor::Address
@ Address
llvm::AMDGPU::EncValues::TTMP_VI_MIN
@ TTMP_VI_MIN
Definition: SIDefines.h:271
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX
@ INLINE_INTEGER_C_POSITIVE_MAX
Definition: SIDefines.h:276
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
addOperand
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Definition: AMDGPUDisassembler.cpp:54
llvm::AMDGPUDisassembler::decodeOperand_AReg_1024
MCOperand decodeOperand_AReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:992
llvm::AMDGPU::getAddrSizeMIMGOp
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:158
llvm::AMDGPUDisassembler::decodeSrcOp
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false) const
Definition: AMDGPUDisassembler.cpp:1299
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::AMDGPUDisassembler::OPW128
@ OPW128
Definition: AMDGPUDisassembler.h:135
llvm::DataExtractor::Cursor::tell
uint64_t tell() const
Return the current position of this Cursor.
Definition: DataExtractor.h:71
llvm::AMDGPUDisassembler::decodeOperand_VS_64
MCOperand decodeOperand_VS_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:939
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:206
decodeOperand_AVLdSt_Any
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:310
decodeOperand_AReg_256
static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:204
llvm::DataExtractor::Cursor
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:151
llvm::amdhsa::RESERVED1_OFFSET
@ RESERVED1_OFFSET
Definition: AMDHSAKernelDescriptor.h:185
llvm::AMDGPUDisassembler::decodeOperand_VReg_512
MCOperand decodeOperand_VReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1020
createAMDGPUDisassembler
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AMDGPUDisassembler.cpp:1938
Status
Definition: SIModeRegister.cpp:28
llvm::AMDGPU::SDWA::SRC_SGPR_MIN
@ SRC_SGPR_MIN
Definition: SIDefines.h:673
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET
@ COMPUTE_PGM_RSRC2_OFFSET
Definition: AMDHSAKernelDescriptor.h:188
llvm::ELF::STT_AMDGPU_HSA_KERNEL
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1170
llvm::AMDGPUDisassembler::decodeIntImmed
static MCOperand decodeIntImmed(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1101
llvm::AMDGPUDisassembler::decodeKernelDescriptor
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Definition: AMDGPUDisassembler.cpp:1836
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::DataExtractor::getU32
uint32_t getU32(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint32_t value from *offset_ptr.
Definition: DataExtractor.cpp:108
llvm::AMDGPUDisassembler::getVgprClassId
unsigned getVgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1209
insertNamedMCOperand
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
Definition: AMDGPUDisassembler.cpp:61
llvm::ELF::STT_OBJECT
@ STT_OBJECT
Definition: ELF.h:1157
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MIN
@ TTMP_GFX9PLUS_MIN
Definition: SIDefines.h:273
llvm::ArrayRef< uint8_t >
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:710
llvm::cantFail
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Definition: Error.h:747
uint32_t
getInlineImmVal16
static int64_t getInlineImmVal16(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1161
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
decodeOperand_VReg_1024
static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:260
DecodeAVLdSt_96RegisterClass
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:361
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:101
llvm::AMDGPU::EncValues::SGPR_MIN
@ SGPR_MIN
Definition: SIDefines.h:268
decodeOperand_VSrcV232
static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:164
llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET
@ GROUP_SEGMENT_FIXED_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:180
llvm::MCDisassembler::getContext
MCContext & getContext() const
Definition: MCDisassembler.h:186
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1449
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET
@ COMPUTE_PGM_RSRC1_OFFSET
Definition: AMDHSAKernelDescriptor.h:187
DecodeAVLdSt_64RegisterClass
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:353
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_GFX10
@ SRC_SGPR_MAX_GFX10
Definition: SIDefines.h:675
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1578
llvm::AMDGPUDisassembler::decodeSDWASrc16
MCOperand decodeSDWASrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1467
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
getInlineImmVal64
static int64_t getInlineImmVal64(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1136
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:52
uint16_t
SDWA
@ SDWA
Definition: SIInstrInfo.cpp:7690
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::AMDGPUDisassembler::decodeOperand_SReg_64
MCOperand decodeOperand_SReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1054
llvm::AMDGPUDisassembler::decodeOperand_AGPR_32
MCOperand decodeOperand_AGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:972
llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
Definition: AMDGPUDisassembler.cpp:1076
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
isValidDPP8
static bool isValidDPP8(const MCInst &MI)
Definition: AMDGPUDisassembler.cpp:433
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:359
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:385
llvm::AMDGPUDisassembler::convertSDWAInst
DecodeStatus convertSDWAInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:670
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:413
llvm::APInt::sext
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:928
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:79
decodeOperand_AReg_1024
static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:220
decodeSoppBrTarget
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:72
llvm::DataExtractor
Definition: DataExtractor.h:41
llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK
@ VOPC_DST_VCC_MASK
Definition: SIDefines.h:668
DisassemblerTypes.h
getInlineImmVal32
static int64_t getInlineImmVal32(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1111
AMDGPUDisassembler.h
llvm::AMDGPUDisassembler::OPW96
@ OPW96
Definition: AMDGPUDisassembler.h:134
llvm::amdhsa::KERNARG_SIZE_OFFSET
@ KERNARG_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:182
llvm::AMDGPUDisassembler::decodeOperand_VSrcV232
MCOperand decodeOperand_VSrcV232(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:955
IsAGPROperand
static bool IsAGPROperand(const MCInst &Inst, int OpIdx, const MCRegisterInfo *MRI)
Definition: AMDGPUDisassembler.cpp:296
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MAX
@ TTMP_GFX9PLUS_MAX
Definition: SIDefines.h:274
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:72
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::AMDGPUDisassembler::createRegOperand
MCOperand createRegOperand(unsigned int RegId) const
Definition: AMDGPUDisassembler.cpp:881
decodeOperand_VS_32
static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:180
llvm::AMDGPUDisassembler::AMDGPUDisassembler
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
Definition: AMDGPUDisassembler.cpp:42
DecodeAVLdSt_32RegisterClass
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:345
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
llvm::max
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:340
shift
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra shift
Definition: README.txt:30
llvm::SymbolInfoTy::Type
uint8_t Type
Definition: MCDisassembler.h:37
llvm::AMDGPUDisassembler::decodeOperand_SReg_32
MCOperand decodeOperand_SReg_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1028
llvm::AMDGPUDisassembler::getTTmpIdx
int getTTmpIdx(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1290
decodeOperand_VS_16_Deferred
static DecodeStatus decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:280
llvm::AMDGPUDisassembler::OPW160
@ OPW160
Definition: AMDGPUDisassembler.h:136
llvm::AMDGPUDisassembler::decodeOperand_SReg_512
MCOperand decodeOperand_SReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1070
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1006
PRINT_DIRECTIVE
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
Definition: AMDGPUDisassembler.cpp:1532
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::AMDGPU::SDWA::SRC_TTMP_MIN
@ SRC_TTMP_MIN
Definition: SIDefines.h:676
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:34
decodeOperand_VReg_64
static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:228
llvm::AMDGPUDisassembler::decodeOperand_VGPR_32
MCOperand decodeOperand_VGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:959
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:54
llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
@ PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:181
llvm::ELF::STT_NOTYPE
@ STT_NOTYPE
Definition: ELF.h:1156
createAMDGPUSymbolizer
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AMDGPUDisassembler.cpp:1929
TargetRegistry.h
llvm::raw_string_ostream::str
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
Definition: raw_ostream.h:643
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:75
llvm::AMDGPUDisassembler::decodeOperand_AReg_64
MCOperand decodeOperand_AReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:976
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:228
LLVMInitializeAMDGPUDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
Definition: AMDGPUDisassembler.cpp:1944
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::AMDGPUDisassembler::OPW32
@ OPW32
Definition: AMDGPUDisassembler.h:132
decodeOperand_SReg_32
static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:377
llvm::AMDGPUDisassembler::OPW1024
@ OPW1024
Definition: AMDGPUDisassembler.h:139
llvm::AMDGPUDisassembler::decodeSpecialReg32
MCOperand decodeSpecialReg32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1370
decodeOperand_VReg_128
static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:236
AMDGPUBaseInfo.h
llvm::DataExtractor::getU16
uint16_t getU16(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint16_t value from *offset_ptr.
Definition: DataExtractor.cpp:93
decodeOperand_AReg_128
static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:196