33 #define DEBUG_TYPE "amdgpu-disassembler" 36 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 37 : AMDGPU::EncValues::SGPR_MAX_SI) 45 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
65 std::advance(
I, OpIdx);
72 uint64_t
Addr,
const void *Decoder) {
73 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
77 APInt SignedOffset(18, Imm * 4,
true);
78 int64_t
Offset = (SignedOffset.
sext(64) + 4 +
Addr).getSExtValue();
80 if (DAsm->tryAddingSymbolicOperand(Inst,
Offset,
Addr,
true, 2, 2))
86 uint64_t
Addr,
const void *Decoder) {
87 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
92 Offset = SignExtend64<21>(Imm);
98 uint64_t
Addr,
const void *Decoder) {
99 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
100 return addOperand(Inst, DAsm->decodeBoolReg(Val));
103 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 104 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 107 const void *Decoder) { \ 108 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 109 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 112 #define DECODE_OPERAND_REG(RegClass) \ 113 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 147 const void *Decoder) {
148 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
149 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
155 const void *Decoder) {
156 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
157 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
163 const void *Decoder) {
164 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
165 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
171 const void *Decoder) {
172 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
173 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
179 const void *Decoder) {
180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
187 const void *Decoder) {
188 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
195 const void *Decoder) {
196 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
203 const void *Decoder) {
204 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
205 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
211 const void *Decoder) {
212 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
216 #define DECODE_SDWA(DecName) \ 217 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 223 #include "AMDGPUGenDisassemblerTables.inc" 231 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.
data());
232 Bytes = Bytes.
slice(
sizeof(
T));
239 uint64_t Address)
const {
244 const auto SavedBytes = Bytes;
245 if (decodeInstruction(Table, TmpInst, Inst,
Address,
this,
STI)) {
257 if ((
unsigned)FiIdx >=
MI.getNumOperands())
259 unsigned Fi =
MI.getOperand(FiIdx).getImm();
270 unsigned MaxInstBytesNum =
std::min((
size_t)TargetMaxInstBytes, Bytes_.
size());
271 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
280 if (Bytes.size() >= 8) {
281 const uint64_t QW = eatBytes<uint64_t>(Bytes);
305 if (Res) { IsSDWA =
true;
break; }
308 if (Res) { IsSDWA =
true;
break; }
311 if (Res) { IsSDWA =
true;
break; }
330 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
333 if (Bytes.size() < 4)
break;
334 const uint32_t DW = eatBytes<uint32_t>(Bytes);
352 if (Bytes.size() < 4)
break;
353 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
366 if (Res && (
MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
367 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
368 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
369 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
370 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
371 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
372 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
373 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
374 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
375 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
378 AMDGPU::OpName::src2_modifiers);
381 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
392 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
393 if (VAddr0Idx >= 0 && NSAArgs > 0) {
394 unsigned NSAWords = (NSAArgs + 3) / 4;
395 if (Bytes.size() < 4 * NSAWords) {
398 for (
unsigned i = 0; i < NSAArgs; ++i) {
399 MI.insert(
MI.begin() + VAddr0Idx + 1 + i,
402 Bytes = Bytes.slice(4 * NSAWords);
414 AMDGPU::OpName::vdst_in);
415 if (VDstIn_Idx != -1) {
416 int Tied = MCII->get(
MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
418 if (Tied != -1 && (
MI.getNumOperands() <= (
unsigned)VDstIn_Idx ||
419 !
MI.getOperand(VDstIn_Idx).isReg() ||
420 MI.getOperand(VDstIn_Idx).getReg() !=
MI.getOperand(Tied).getReg())) {
421 if (
MI.getNumOperands() > (
unsigned)VDstIn_Idx)
422 MI.erase(&
MI.getOperand(VDstIn_Idx));
425 AMDGPU::OpName::vdst_in);
431 Size = Res ? (MaxInstBytesNum - Bytes.size())
447 AMDGPU::OpName::sdst);
457 unsigned Opc =
MI.getOpcode();
458 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
461 if (
MI.getNumOperands() < DescNumOps &&
464 AMDGPU::OpName::src0_modifiers);
466 if (
MI.getNumOperands() < DescNumOps &&
469 AMDGPU::OpName::src1_modifiers);
480 AMDGPU::OpName::vdst);
483 AMDGPU::OpName::vdata);
487 AMDGPU::OpName::dmask);
490 AMDGPU::OpName::tfe);
492 AMDGPU::OpName::d16);
495 if (DMaskIdx == -1 || TFEIdx == -1) {
497 assert(
MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa ||
498 MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa ||
499 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa ||
500 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa);
507 bool IsAtomic = (VDstIdx != -1);
511 unsigned AddrSize =
Info->VAddrDwords;
521 AddrSize = BaseOpcode->NumExtraArgs +
523 (BaseOpcode->Coordinates ? Dim->
NumCoords : 0) +
524 (BaseOpcode->LodOrClampOrMip ? 1 : 0);
525 IsNSA =
Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
529 else if (AddrSize > 4)
532 if (AddrSize >
Info->VAddrDwords) {
540 unsigned DMask =
MI.getOperand(DMaskIdx).getImm() & 0xf;
543 bool D16 = D16Idx >= 0 &&
MI.getOperand(D16Idx).getImm();
545 DstSize = (DstSize + 1) / 2;
549 if (
MI.getOperand(TFEIdx).getImm())
552 if (DstSize ==
Info->VDataDwords && AddrSize ==
Info->VAddrDwords)
561 unsigned NewVdata = AMDGPU::NoRegister;
562 if (DstSize !=
Info->VDataDwords) {
563 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
566 unsigned Vdata0 =
MI.getOperand(VDataIdx).getReg();
567 unsigned VdataSub0 = MRI.
getSubReg(Vdata0, AMDGPU::sub0);
568 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
572 if (NewVdata == AMDGPU::NoRegister) {
579 unsigned NewVAddr0 = AMDGPU::NoRegister;
581 AddrSize !=
Info->VAddrDwords) {
582 unsigned VAddr0 =
MI.getOperand(VAddr0Idx).getReg();
583 unsigned VAddrSub0 = MRI.
getSubReg(VAddr0, AMDGPU::sub0);
584 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
586 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
589 if (NewVAddr0 == AMDGPU::NoRegister)
593 MI.setOpcode(NewOpcode);
595 if (NewVdata != AMDGPU::NoRegister) {
604 if (NewVAddr0 != AMDGPU::NoRegister) {
607 assert(AddrSize <= Info->VAddrDwords);
608 MI.erase(
MI.begin() + VAddr0Idx + AddrSize,
609 MI.begin() + VAddr0Idx +
Info->VAddrDwords);
622 const Twine& ErrMsg)
const {
637 unsigned Val)
const {
638 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
639 if (Val >= RegCl.getNumRegs())
641 ": unknown register " +
Twine(Val));
647 unsigned Val)
const {
651 switch (SRegClassID) {
652 case AMDGPU::SGPR_32RegClassID:
653 case AMDGPU::TTMP_32RegClassID:
655 case AMDGPU::SGPR_64RegClassID:
656 case AMDGPU::TTMP_64RegClassID:
659 case AMDGPU::SGPR_128RegClassID:
660 case AMDGPU::TTMP_128RegClassID:
663 case AMDGPU::SGPR_256RegClassID:
664 case AMDGPU::TTMP_256RegClassID:
667 case AMDGPU::SGPR_512RegClassID:
668 case AMDGPU::TTMP_512RegClassID:
677 if (Val % (1 << shift)) {
679 <<
": scalar reg isn't aligned " << Val;
770 unsigned Val)
const {
776 unsigned Val)
const {
813 if (Bytes.
size() < 4) {
814 return errOperand(0,
"cannot read literal, inst bytes left " +
818 Literal = eatBytes<uint32_t>(Bytes);
824 using namespace AMDGPU::EncValues;
877 return 0x3fc45f306dc9c882;
930 using namespace AMDGPU;
938 return VGPR_32RegClassID;
939 case OPW64:
return VReg_64RegClassID;
940 case OPW128:
return VReg_128RegClassID;
945 using namespace AMDGPU;
953 return AGPR_32RegClassID;
954 case OPW64:
return AReg_64RegClassID;
955 case OPW128:
return AReg_128RegClassID;
956 case OPW256:
return AReg_256RegClassID;
957 case OPW512:
return AReg_512RegClassID;
958 case OPW1024:
return AReg_1024RegClassID;
964 using namespace AMDGPU;
972 return SGPR_32RegClassID;
973 case OPW64:
return SGPR_64RegClassID;
974 case OPW128:
return SGPR_128RegClassID;
975 case OPW256:
return SGPR_256RegClassID;
976 case OPW512:
return SGPR_512RegClassID;
981 using namespace AMDGPU;
989 return TTMP_32RegClassID;
990 case OPW64:
return TTMP_64RegClassID;
991 case OPW128:
return TTMP_128RegClassID;
992 case OPW256:
return TTMP_256RegClassID;
993 case OPW512:
return TTMP_512RegClassID;
998 using namespace AMDGPU::EncValues;
1003 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1007 using namespace AMDGPU::EncValues;
1011 bool IsAGPR = Val & 512;
1050 using namespace AMDGPU::EncValues;
1069 using namespace AMDGPU;
1101 using namespace AMDGPU;
1125 const unsigned Val)
const {
1127 using namespace AMDGPU::EncValues;
1178 "SDWAVopcDst should be present only on GFX9+");
1222 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1224 KdStream << Indent << DIRECTIVE " " \ 1225 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1231 using namespace amdhsa;
1239 uint32_t GranulatedWorkitemVGPRCount =
1240 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >>
1241 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT;
1243 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) *
1246 KdStream << Indent <<
".amdhsa_next_free_vgpr " << NextFreeVGPR <<
'\n';
1267 uint32_t GranulatedWavefrontSGPRCount =
1268 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
1269 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
1271 if (
isGFX10Plus() && GranulatedWavefrontSGPRCount)
1274 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1277 KdStream << Indent <<
".amdhsa_reserve_vcc " << 0 <<
'\n';
1278 KdStream << Indent <<
".amdhsa_reserve_flat_scratch " << 0 <<
'\n';
1279 KdStream << Indent <<
".amdhsa_reserve_xnack_mask " << 0 <<
'\n';
1280 KdStream << Indent <<
".amdhsa_next_free_sgpr " << NextFreeSGPR <<
"\n";
1282 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1286 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1288 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1290 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1292 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1294 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1297 PRINT_DIRECTIVE(
".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1299 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1302 PRINT_DIRECTIVE(
".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1304 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1307 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1310 PRINT_DIRECTIVE(
".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1312 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1317 COMPUTE_PGM_RSRC1_WGP_MODE);
1318 PRINT_DIRECTIVE(
".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1319 PRINT_DIRECTIVE(
".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1327 using namespace amdhsa;
1330 ".amdhsa_system_sgpr_private_segment_wavefront_offset",
1331 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1333 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1335 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1337 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1339 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1341 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1343 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1346 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1349 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1353 ".amdhsa_exception_fp_ieee_invalid_op",
1354 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1356 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1358 ".amdhsa_exception_fp_ieee_div_zero",
1359 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1361 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1363 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1365 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1367 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1369 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1375 #undef PRINT_DIRECTIVE 1381 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1383 KdStream << Indent << DIRECTIVE " " \ 1384 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1389 uint64_t EightByteBuffer = 0;
1397 switch (Cursor.
tell()) {
1399 FourByteBuffer = DE.getU32(Cursor);
1400 KdStream << Indent <<
".amdhsa_group_segment_fixed_size " << FourByteBuffer
1405 FourByteBuffer = DE.getU32(Cursor);
1406 KdStream << Indent <<
".amdhsa_private_segment_fixed_size " 1407 << FourByteBuffer <<
'\n';
1412 EightByteBuffer = DE.getU64(Cursor);
1413 if (EightByteBuffer) {
1427 ReservedBytes = DE.getBytes(Cursor, 20);
1428 for (
int I = 0;
I < 20; ++
I) {
1429 if (ReservedBytes[
I] != 0) {
1439 FourByteBuffer = DE.getU32(Cursor);
1446 FourByteBuffer = DE.getU32(Cursor);
1454 FourByteBuffer = DE.getU32(Cursor);
1462 using namespace amdhsa;
1463 TwoByteBuffer = DE.getU16(Cursor);
1466 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
1468 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
1470 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
1472 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
1474 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
1476 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
1478 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
1480 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
1485 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
1489 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
1492 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
1499 ReservedBytes = DE.getBytes(Cursor, 6);
1500 for (
int I = 0;
I < 6; ++
I) {
1501 if (ReservedBytes[
I] != 0)
1510 #undef PRINT_DIRECTIVE 1516 if (Bytes.
size() != 64 || KdAddress % 64 != 0)
1521 KdStream <<
".amdhsa_kernel " << KdName <<
'\n';
1524 while (
C &&
C.tell() < Bytes.
size()) {
1533 KdStream <<
".end_amdhsa_kernel\n";
1570 uint64_t ,
bool IsBranch,
1571 uint64_t , uint64_t ) {
1577 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1582 return Val.
Addr == static_cast<uint64_t>(
Value) &&
1585 if (Result != Symbols->end()) {
1586 auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1609 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
MCOperand createRegOperand(unsigned int RegId) const
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
static int64_t getInlineImmVal16(unsigned Imm)
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Target & getTheGCNTarget()
The target for GCN GPUs.
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
bool hasPackedD16(const MCSubtargetInfo &STI)
APInt sext(unsigned width) const
Sign extend to a new width.
DecodeStatus convertDPP8Inst(MCInst &MI) const
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
#define DECODE_OPERAND_REG(RegClass)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
This class represents lattice values for constants.
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand decodeOperand_VSrcV216(unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
MCOperand decodeOperand_VS_128(unsigned Val) const
static MCOperand createExpr(const MCExpr *Val)
MCOperand decodeOperand_SReg_512(unsigned Val) const
static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Superclass for all disassemblers.
raw_ostream * CommentStream
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
bool isGFX9Plus(const MCSubtargetInfo &STI)
const char * getRegClassName(unsigned RegClassID) const
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
MCOperand decodeBoolReg(unsigned Val) const
Optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeLiteralConstant() const
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
MCOperand decodeOperand_AReg_128(unsigned Val) const
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
MCOperand decodeOperand_SReg_128(unsigned Val) const
unsigned M0(unsigned Val)
static MCOperand createReg(unsigned Reg)
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
const FeatureBitset & getFeatureBits() const
MCOperand decodeSDWAVopcDst(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeOperand_AReg_512(unsigned Val) const
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
static int64_t getInlineImmVal32(unsigned Imm)
Context object for machine code objects.
DecodeStatus convertSDWAInst(MCInst &MI) const
MCOperand decodeOperand_AReg_1024(unsigned Val) const
const MCSubtargetInfo & STI
MCOperand decodeSDWASrc32(unsigned Val) const
MCOperand decodeOperand_VReg_256(unsigned Val) const
static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Analysis containing CSE Info
Instances of this class represent a single low-level machine instruction.
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
MCOperand decodeOperand_AV_64(unsigned Val) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned const MachineRegisterInfo * MRI
MCOperand decodeOperand_VReg_128(unsigned Val) const
bool isGFX10(const MCSubtargetInfo &STI)
MCOperand decodeOperand_SReg_256(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
Symbolize and annotate disassembled instructions.
static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
size_t size() const
size - Get the array size.
DecodeStatus convertMIMGInst(MCInst &MI) const
MCOperand decodeOperand_VS_64(unsigned Val) const
Interface to description of machine instruction set.
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
MCOperand decodeOperand_VReg_512(unsigned Val) const
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static int64_t getInlineImmVal64(unsigned Imm)
std::string & str()
Flushes the stream contents to the target string and returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Triple - Helper class for working with autoconf configuration names.
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
unsigned getAgprClassId(const OpWidthTy Width) const
AMDHSA kernel descriptor definitions.
MCOperand decodeSDWASrc16(unsigned Val) const
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Align max(MaybeAlign Lhs, Align Rhs)
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
MCContext & getContext() const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static bool isValidDPP8(const MCInst &MI)
#define LLVM_EXTERNAL_VISIBILITY
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
static MCOperand decodeIntImmed(unsigned Imm)
#define DECODE_SDWA(DecName)
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
MCOperand decodeOperand_AGPR_32(unsigned Val) const
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
bool isGFX9(const MCSubtargetInfo &STI)
bool isGFX10Plus(const MCSubtargetInfo &STI)
Provides AMDGPU specific target descriptions.
static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
MCOperand decodeOperand_AV_32(unsigned Val) const
This file contains declaration for AMDGPU ISA disassembler.
MCOperand decodeOperand_VSrc16(unsigned Val) const
Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A raw_ostream that writes to an std::string.
MCOperand decodeOperand_SReg_64(unsigned Val) const
const MCRegisterInfo * getRegisterInfo() const
MCOperand decodeOperand_VReg_96(unsigned Val) const
LLVM Value Representation.
void addOperand(const MCOperand Op)
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
unsigned getTtmpClassId(const OpWidthTy Width) const
MCOperand decodeSpecialReg64(unsigned Val) const
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
This class implements an extremely fast bulk output stream that can only output to a stream.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
StringRef - Represent a constant reference to a string, i.e.
MCOperand decodeSpecialReg32(unsigned Val) const
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
int getTTmpIdx(unsigned Val) const
Instances of this class represent operands of the MCInst class.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static MCOperand createImm(int64_t Val)
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.