39#define DEBUG_TYPE "amdgpu-disassembler"
42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
43 : AMDGPU::EncValues::SGPR_MAX_SI)
50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) {
69 std::advance(
I, OpIdx);
82 APInt SignedOffset(18, Imm * 4,
true);
83 int64_t
Offset = (SignedOffset.
sext(64) + 4 +
Addr).getSExtValue();
85 if (DAsm->tryAddingSymbolicOperand(Inst,
Offset,
Addr,
true, 2, 2, 0))
94 if (DAsm->isGFX12Plus()) {
95 Offset = SignExtend64<24>(Imm);
96 }
else if (DAsm->isVI()) {
99 Offset = SignExtend64<21>(Imm);
107 return addOperand(Inst, DAsm->decodeBoolReg(Val));
110#define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
113 const MCDisassembler *Decoder) { \
114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
115 return addOperand(Inst, DAsm->DecoderName(Imm)); \
120#define DECODE_OPERAND_REG_8(RegClass) \
121 static DecodeStatus Decode##RegClass##RegisterClass( \
122 MCInst &Inst, unsigned Imm, uint64_t , \
123 const MCDisassembler *Decoder) { \
124 assert(Imm < (1 << 8) && "8-bit encoding"); \
125 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
127 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \
130#define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \
132 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t , \
133 const MCDisassembler *Decoder) { \
134 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \
135 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
136 return addOperand(Inst, \
137 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \
138 MandatoryLiteral, ImmWidth)); \
143#define DECODE_OPERAND_REG_7(RegClass, OpWidth) \
144 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0)
150#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \
151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \
152 Imm | AMDGPU::EncValues::IS_VGPR, false, 0)
155#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \
156 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0)
161#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \
162 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0)
166#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \
167 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0)
174#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \
175 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \
180#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \
181 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \
182 Imm | 512, false, ImmWidth)
184#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \
185 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \
186 OpWidth, Imm, true, ImmWidth)
270 assert(isUInt<10>(Imm) &&
"10-bit encoding expected");
271 assert((Imm & (1 << 8)) == 0 &&
"Imm{8} should not be used");
273 bool IsHi = Imm & (1 << 9);
274 unsigned RegIdx = Imm & 0xff;
276 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
282 assert(isUInt<8>(Imm) &&
"8-bit encoding expected");
284 bool IsHi = Imm & (1 << 7);
285 unsigned RegIdx = Imm & 0x7f;
287 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
293 assert(isUInt<9>(Imm) &&
"9-bit encoding expected");
296 bool IsVGPR = Imm & (1 << 8);
298 bool IsHi = Imm & (1 << 7);
299 unsigned RegIdx = Imm & 0x7f;
300 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
303 Imm & 0xFF,
false, 16));
309 assert(isUInt<10>(Imm) &&
"10-bit encoding expected");
312 bool IsVGPR = Imm & (1 << 8);
314 bool IsHi = Imm & (1 << 9);
315 unsigned RegIdx = Imm & 0xff;
316 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
319 Imm & 0xFF,
false, 16));
326 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
332 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
344 unsigned Sub =
MRI->getSubReg(
Op.getReg(), AMDGPU::sub0);
345 auto Reg = Sub ? Sub :
Op.getReg();
346 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
353 if (!DAsm->isGFX90A()) {
362 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
364 : AMDGPU::OpName::vdata;
380 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
386 assert(Imm < (1 << 9) &&
"9-bit encoding");
427#define DECODE_SDWA(DecName) \
428DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
434#include "AMDGPUGenDisassemblerTables.inc"
443 support::endian::read<T, llvm::endianness::little>(Bytes.
data());
444 Bytes = Bytes.
slice(
sizeof(
T));
451 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.
data());
452 Bytes = Bytes.
slice(8);
454 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.
data());
455 Bytes = Bytes.
slice(4);
466 if ((
unsigned)FiIdx >=
MI.getNumOperands())
468 unsigned Fi =
MI.getOperand(FiIdx).getImm();
469 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
478 unsigned MaxInstBytesNum = std::min((
size_t)TargetMaxInstBytes, Bytes_.
size());
479 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
491 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696,
496 Res =
tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696,
518 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
520 if (Bytes.
size() >= 8) {
521 const uint64_t QW = eatBytes<uint64_t>(Bytes);
541 DecoderTableDPP8GFX11_FAKE1664,
MI, QW,
Address, CS);
549 Res =
tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664,
558 if (Res) { IsSDWA =
true;
break; }
561 if (Res) { IsSDWA =
true;
break; }
564 if (Res) { IsSDWA =
true;
break; }
583 Bytes = Bytes_.
slice(0, MaxInstBytesNum);
586 if (Bytes.
size() < 4)
break;
587 const uint32_t DW = eatBytes<uint32_t>(Bytes);
611 Res =
tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632,
MI, DW,
619 if (Bytes.
size() < 4)
break;
650 Res =
tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664,
MI, QW,
661 AMDGPU::OpName::src2_modifiers);
664 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
667 AMDGPU::OpName::cpol);
672 if (
MI.getNumOperands() <= (
unsigned)CPolPos) {
674 AMDGPU::OpName::cpol);
676 MI.getOperand(CPolPos).setImm(
MI.getOperand(CPolPos).getImm() | CPol);
681 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
687 if (TFEOpIdx != -1) {
688 auto TFEIter =
MI.begin();
689 std::advance(TFEIter, TFEOpIdx);
694 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
698 if (SWZOpIdx != -1) {
699 auto SWZIter =
MI.begin();
700 std::advance(SWZIter, SWZOpIdx);
710 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
711 if (VAddr0Idx >= 0 && NSAArgs > 0) {
712 unsigned NSAWords = (NSAArgs + 3) / 4;
713 if (Bytes.
size() < 4 * NSAWords) {
716 for (
unsigned i = 0; i < NSAArgs; ++i) {
717 const unsigned VAddrIdx = VAddr0Idx + 1 + i;
719 MCII->get(
MI.getOpcode()).operands()[VAddrIdx].RegClass;
720 MI.insert(
MI.begin() + VAddrIdx,
723 Bytes = Bytes.
slice(4 * NSAWords);
731 if (Res && (MCII->get(
MI.getOpcode()).TSFlags &
745 AMDGPU::OpName::vdst_in);
746 if (VDstIn_Idx != -1) {
747 int Tied = MCII->get(
MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
749 if (Tied != -1 && (
MI.getNumOperands() <= (
unsigned)VDstIn_Idx ||
750 !
MI.getOperand(VDstIn_Idx).isReg() ||
751 MI.getOperand(VDstIn_Idx).getReg() !=
MI.getOperand(Tied).getReg())) {
752 if (
MI.getNumOperands() > (
unsigned)VDstIn_Idx)
753 MI.erase(&
MI.getOperand(VDstIn_Idx));
756 AMDGPU::OpName::vdst_in);
763 if (Res && ImmLitIdx != -1 && !IsSOPK)
768 Size = Res ? (MaxInstBytesNum - Bytes.
size())
769 : std::min((
size_t)4, Bytes_.
size());
784 if (
MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 ||
785 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 ||
786 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 ||
787 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) {
806 AMDGPU::OpName::sdst);
817 unsigned OpSelHi = 0;
826 bool IsVOP3P =
false) {
828 unsigned Opc =
MI.getOpcode();
829 const int ModOps[] = {AMDGPU::OpName::src0_modifiers,
830 AMDGPU::OpName::src1_modifiers,
831 AMDGPU::OpName::src2_modifiers};
832 for (
int J = 0; J < 3; ++J) {
837 unsigned Val =
MI.getOperand(OpIdx).getImm();
855 constexpr int DST_IDX = 0;
860 if (OldIdx != -1 &&
Desc.getOperandConstraint(
875 assert(
MI.getNumOperands() + 1 < MCII->get(
MI.getOpcode()).getNumOperands());
878 AMDGPU::OpName::src2_modifiers);
884 unsigned Opc =
MI.getOpcode();
894 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
895 if (
MI.getNumOperands() < DescNumOps &&
899 AMDGPU::OpName::op_sel);
902 if (
MI.getNumOperands() < DescNumOps &&
905 AMDGPU::OpName::src0_modifiers);
907 if (
MI.getNumOperands() < DescNumOps &&
910 AMDGPU::OpName::src1_modifiers);
920 unsigned Opc =
MI.getOpcode();
921 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
922 if (
MI.getNumOperands() < DescNumOps &&
926 AMDGPU::OpName::op_sel);
935 auto TSFlags = MCII->get(
MI.getOpcode()).TSFlags;
938 AMDGPU::OpName::vdst);
941 AMDGPU::OpName::vdata);
945 : AMDGPU::OpName::rsrc;
948 AMDGPU::OpName::dmask);
951 AMDGPU::OpName::tfe);
953 AMDGPU::OpName::d16);
960 if (BaseOpcode->
BVH) {
966 bool IsAtomic = (VDstIdx != -1);
970 bool IsPartialNSA =
false;
971 unsigned AddrSize =
Info->VAddrDwords;
980 const bool IsA16 = (A16Idx != -1 &&
MI.getOperand(A16Idx).getImm());
987 IsNSA =
Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA ||
988 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA ||
989 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12;
991 if (!IsVSample && AddrSize > 12)
994 if (AddrSize >
Info->VAddrDwords) {
1000 IsPartialNSA =
true;
1005 unsigned DMask =
MI.getOperand(DMaskIdx).getImm() & 0xf;
1006 unsigned DstSize = IsGather4 ? 4 : std::max(
llvm::popcount(DMask), 1);
1008 bool D16 = D16Idx >= 0 &&
MI.getOperand(D16Idx).getImm();
1010 DstSize = (DstSize + 1) / 2;
1013 if (TFEIdx != -1 &&
MI.getOperand(TFEIdx).getImm())
1016 if (DstSize ==
Info->VDataDwords && AddrSize ==
Info->VAddrDwords)
1021 if (NewOpcode == -1)
1025 unsigned NewVdata = AMDGPU::NoRegister;
1026 if (DstSize !=
Info->VDataDwords) {
1027 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
1030 unsigned Vdata0 =
MI.getOperand(VDataIdx).getReg();
1031 unsigned VdataSub0 = MRI.
getSubReg(Vdata0, AMDGPU::sub0);
1032 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
1036 if (NewVdata == AMDGPU::NoRegister) {
1045 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx;
1046 unsigned NewVAddrSA = AMDGPU::NoRegister;
1047 if (
STI.
hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) &&
1048 AddrSize !=
Info->VAddrDwords) {
1049 unsigned VAddrSA =
MI.getOperand(VAddrSAIdx).getReg();
1050 unsigned VAddrSubSA = MRI.
getSubReg(VAddrSA, AMDGPU::sub0);
1051 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
1053 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;
1060 MI.setOpcode(NewOpcode);
1062 if (NewVdata != AMDGPU::NoRegister) {
1074 assert(AddrSize <= Info->VAddrDwords);
1075 MI.erase(
MI.begin() + VAddr0Idx + AddrSize,
1076 MI.begin() + VAddr0Idx +
Info->VAddrDwords);
1086 unsigned Opc =
MI.getOpcode();
1087 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1090 if (
MI.getNumOperands() < DescNumOps &&
1094 if (
MI.getNumOperands() < DescNumOps &&
1097 AMDGPU::OpName::op_sel);
1098 if (
MI.getNumOperands() < DescNumOps &&
1101 AMDGPU::OpName::op_sel_hi);
1102 if (
MI.getNumOperands() < DescNumOps &&
1105 AMDGPU::OpName::neg_lo);
1106 if (
MI.getNumOperands() < DescNumOps &&
1109 AMDGPU::OpName::neg_hi);
1116 unsigned Opc =
MI.getOpcode();
1117 unsigned DescNumOps = MCII->get(Opc).getNumOperands();
1119 if (
MI.getNumOperands() < DescNumOps &&
1123 if (
MI.getNumOperands() < DescNumOps &&
1126 AMDGPU::OpName::src0_modifiers);
1128 if (
MI.getNumOperands() < DescNumOps &&
1131 AMDGPU::OpName::src1_modifiers);
1136 int ImmLitIdx)
const {
1137 assert(HasLiteral &&
"Should have decoded a literal");
1139 unsigned DescNumOps =
Desc.getNumOperands();
1141 AMDGPU::OpName::immDeferred);
1142 assert(DescNumOps ==
MI.getNumOperands());
1143 for (
unsigned I = 0;
I < DescNumOps; ++
I) {
1144 auto &
Op =
MI.getOperand(
I);
1145 auto OpType =
Desc.operands()[
I].OperandType;
1162 const Twine& ErrMsg)
const {
1177 unsigned Val)
const {
1178 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
1179 if (Val >= RegCl.getNumRegs())
1181 ": unknown register " +
Twine(Val));
1187 unsigned Val)
const {
1191 switch (SRegClassID) {
1192 case AMDGPU::SGPR_32RegClassID:
1193 case AMDGPU::TTMP_32RegClassID:
1195 case AMDGPU::SGPR_64RegClassID:
1196 case AMDGPU::TTMP_64RegClassID:
1199 case AMDGPU::SGPR_128RegClassID:
1200 case AMDGPU::TTMP_128RegClassID:
1203 case AMDGPU::SGPR_256RegClassID:
1204 case AMDGPU::TTMP_256RegClassID:
1207 case AMDGPU::SGPR_288RegClassID:
1208 case AMDGPU::TTMP_288RegClassID:
1209 case AMDGPU::SGPR_320RegClassID:
1210 case AMDGPU::TTMP_320RegClassID:
1211 case AMDGPU::SGPR_352RegClassID:
1212 case AMDGPU::TTMP_352RegClassID:
1213 case AMDGPU::SGPR_384RegClassID:
1214 case AMDGPU::TTMP_384RegClassID:
1215 case AMDGPU::SGPR_512RegClassID:
1216 case AMDGPU::TTMP_512RegClassID:
1225 if (Val % (1 << shift)) {
1227 <<
": scalar reg isn't aligned " << Val;
1236 IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID;
1246 "Should only decode multiple kimm with VOPD, check VSrc operand types");
1248 return errOperand(Val,
"More than one unique literal is illegal");
1260 if (Bytes.
size() < 4) {
1261 return errOperand(0,
"cannot read literal, inst bytes left " +
1265 Literal = Literal64 = eatBytes<uint32_t>(Bytes);
1273 using namespace AMDGPU::EncValues;
1275 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
1277 (
static_cast<int64_t
>(Imm) - INLINE_INTEGER_C_MIN) :
1278 (INLINE_INTEGER_C_POSITIVE_MAX -
static_cast<int64_t
>(Imm)));
1285 return llvm::bit_cast<uint32_t>(0.5f);
1287 return llvm::bit_cast<uint32_t>(-0.5f);
1289 return llvm::bit_cast<uint32_t>(1.0f);
1291 return llvm::bit_cast<uint32_t>(-1.0f);
1293 return llvm::bit_cast<uint32_t>(2.0f);
1295 return llvm::bit_cast<uint32_t>(-2.0f);
1297 return llvm::bit_cast<uint32_t>(4.0f);
1299 return llvm::bit_cast<uint32_t>(-4.0f);
1310 return llvm::bit_cast<uint64_t>(0.5);
1312 return llvm::bit_cast<uint64_t>(-0.5);
1314 return llvm::bit_cast<uint64_t>(1.0);
1316 return llvm::bit_cast<uint64_t>(-1.0);
1318 return llvm::bit_cast<uint64_t>(2.0);
1320 return llvm::bit_cast<uint64_t>(-2.0);
1322 return llvm::bit_cast<uint64_t>(4.0);
1324 return llvm::bit_cast<uint64_t>(-4.0);
1326 return 0x3fc45f306dc9c882;
1379 using namespace AMDGPU;
1387 return VGPR_32RegClassID;
1389 case OPWV232:
return VReg_64RegClassID;
1390 case OPW96:
return VReg_96RegClassID;
1391 case OPW128:
return VReg_128RegClassID;
1392 case OPW160:
return VReg_160RegClassID;
1393 case OPW256:
return VReg_256RegClassID;
1394 case OPW288:
return VReg_288RegClassID;
1395 case OPW320:
return VReg_320RegClassID;
1396 case OPW352:
return VReg_352RegClassID;
1397 case OPW384:
return VReg_384RegClassID;
1398 case OPW512:
return VReg_512RegClassID;
1399 case OPW1024:
return VReg_1024RegClassID;
1404 using namespace AMDGPU;
1412 return AGPR_32RegClassID;
1414 case OPWV232:
return AReg_64RegClassID;
1415 case OPW96:
return AReg_96RegClassID;
1416 case OPW128:
return AReg_128RegClassID;
1417 case OPW160:
return AReg_160RegClassID;
1418 case OPW256:
return AReg_256RegClassID;
1419 case OPW288:
return AReg_288RegClassID;
1420 case OPW320:
return AReg_320RegClassID;
1421 case OPW352:
return AReg_352RegClassID;
1422 case OPW384:
return AReg_384RegClassID;
1423 case OPW512:
return AReg_512RegClassID;
1424 case OPW1024:
return AReg_1024RegClassID;
1430 using namespace AMDGPU;
1438 return SGPR_32RegClassID;
1440 case OPWV232:
return SGPR_64RegClassID;
1441 case OPW96:
return SGPR_96RegClassID;
1442 case OPW128:
return SGPR_128RegClassID;
1443 case OPW160:
return SGPR_160RegClassID;
1444 case OPW256:
return SGPR_256RegClassID;
1445 case OPW288:
return SGPR_288RegClassID;
1446 case OPW320:
return SGPR_320RegClassID;
1447 case OPW352:
return SGPR_352RegClassID;
1448 case OPW384:
return SGPR_384RegClassID;
1449 case OPW512:
return SGPR_512RegClassID;
1454 using namespace AMDGPU;
1462 return TTMP_32RegClassID;
1464 case OPWV232:
return TTMP_64RegClassID;
1465 case OPW128:
return TTMP_128RegClassID;
1466 case OPW256:
return TTMP_256RegClassID;
1467 case OPW288:
return TTMP_288RegClassID;
1468 case OPW320:
return TTMP_320RegClassID;
1469 case OPW352:
return TTMP_352RegClassID;
1470 case OPW384:
return TTMP_384RegClassID;
1471 case OPW512:
return TTMP_512RegClassID;
1476 using namespace AMDGPU::EncValues;
1478 unsigned TTmpMin =
isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1479 unsigned TTmpMax =
isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1481 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1485 bool MandatoryLiteral,
1486 unsigned ImmWidth,
bool IsFP)
const {
1487 using namespace AMDGPU::EncValues;
1491 bool IsAGPR = Val & 512;
1494 if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1504 bool MandatoryLiteral,
1509 assert(Val < (1 << 8) &&
"9-bit Src encoding when Val{8} is 0");
1510 using namespace AMDGPU::EncValues;
1514 static_assert(SGPR_MIN == 0);
1523 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1526 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1529 if (Val == LITERAL_CONST) {
1530 if (MandatoryLiteral)
1553 unsigned Val)
const {
1559 Val |= ~XDstReg & 1;
1565 using namespace AMDGPU;
1601 using namespace AMDGPU;
1633 unsigned ImmWidth)
const {
1634 using namespace AMDGPU::SDWA;
1635 using namespace AMDGPU::EncValues;
1641 if (
int(SDWA9EncValues::SRC_VGPR_MIN) <=
int(Val) &&
1642 Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1644 Val - SDWA9EncValues::SRC_VGPR_MIN);
1646 if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1647 Val <= (
isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1648 : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1650 Val - SDWA9EncValues::SRC_SGPR_MIN);
1652 if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1653 Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1655 Val - SDWA9EncValues::SRC_TTMP_MIN);
1658 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1660 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1663 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1667 }
else if (
STI.
hasFeature(AMDGPU::FeatureVolcanicIslands)) {
1682 using namespace AMDGPU::SDWA;
1686 "SDWAVopcDst should be present only on GFX9+");
1688 bool IsWave64 =
STI.
hasFeature(AMDGPU::FeatureWavefrontSize64);
1690 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1691 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1745 return STI.
hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
1755#define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK))
1756#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1758 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \
1760#define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \
1762 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \
1763 << GET_FIELD(MASK) << '\n'; \
1769 using namespace amdhsa;
1777 uint32_t GranulatedWorkitemVGPRCount =
1778 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT);
1781 (GranulatedWorkitemVGPRCount + 1) *
1784 KdStream << Indent <<
".amdhsa_next_free_vgpr " << NextFreeVGPR <<
'\n';
1805 uint32_t GranulatedWavefrontSGPRCount =
1806 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT);
1808 if (
isGFX10Plus() && GranulatedWavefrontSGPRCount)
1811 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1814 KdStream << Indent <<
".amdhsa_reserve_vcc " << 0 <<
'\n';
1816 KdStream << Indent <<
".amdhsa_reserve_flat_scratch " << 0 <<
'\n';
1817 KdStream << Indent <<
".amdhsa_reserve_xnack_mask " << 0 <<
'\n';
1818 KdStream << Indent <<
".amdhsa_next_free_sgpr " << NextFreeSGPR <<
"\n";
1820 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1824 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1826 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1828 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1830 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1832 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1835 PRINT_DIRECTIVE(
".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1837 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1840 PRINT_DIRECTIVE(
".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1842 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1845 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1849 PRINT_DIRECTIVE(
".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL);
1852 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0)
1854 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1)
1857 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2)
1862 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE);
1863 PRINT_DIRECTIVE(
".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED);
1864 PRINT_DIRECTIVE(
".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS);
1872 using namespace amdhsa;
1876 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1878 PRINT_DIRECTIVE(
".amdhsa_system_sgpr_private_segment_wavefront_offset",
1879 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1881 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1883 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1885 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1887 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1889 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1891 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1894 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1897 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1901 ".amdhsa_exception_fp_ieee_invalid_op",
1902 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1904 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1906 ".amdhsa_exception_fp_ieee_div_zero",
1907 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1909 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1911 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1913 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1915 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1917 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1926 using namespace amdhsa;
1929 KdStream << Indent <<
".amdhsa_accum_offset "
1930 << (
GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4
1932 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0)
1934 PRINT_DIRECTIVE(
".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT);
1935 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1)
1938 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) {
1940 COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
1943 "SHARED_VGPR_COUNT", COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT);
1948 COMPUTE_PGM_RSRC3_GFX11_PLUS_INST_PREF_SIZE);
1950 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START);
1952 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_END);
1954 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED0)
1958 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED1)
1963 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START);
1965 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED2)
1968 }
else if (FourByteBuffer) {
1973#undef PRINT_PSEUDO_DIRECTIVE_COMMENT
1974#undef PRINT_DIRECTIVE
1981#define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1983 KdStream << Indent << DIRECTIVE " " \
1984 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1996 switch (Cursor.
tell()) {
1998 FourByteBuffer = DE.
getU32(Cursor);
1999 KdStream << Indent <<
".amdhsa_group_segment_fixed_size " << FourByteBuffer
2004 FourByteBuffer = DE.
getU32(Cursor);
2005 KdStream << Indent <<
".amdhsa_private_segment_fixed_size "
2006 << FourByteBuffer <<
'\n';
2010 FourByteBuffer = DE.
getU32(Cursor);
2011 KdStream << Indent <<
".amdhsa_kernarg_size "
2012 << FourByteBuffer <<
'\n';
2017 ReservedBytes = DE.
getBytes(Cursor, 4);
2018 for (
int I = 0;
I < 4; ++
I) {
2019 if (ReservedBytes[
I] != 0) {
2034 ReservedBytes = DE.
getBytes(Cursor, 20);
2035 for (
int I = 0;
I < 20; ++
I) {
2036 if (ReservedBytes[
I] != 0) {
2043 FourByteBuffer = DE.
getU32(Cursor);
2047 FourByteBuffer = DE.
getU32(Cursor);
2051 FourByteBuffer = DE.
getU32(Cursor);
2055 using namespace amdhsa;
2056 TwoByteBuffer = DE.
getU16(Cursor);
2060 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
2062 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
2064 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
2066 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
2068 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
2071 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
2073 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
2075 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
2080 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
2084 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
2089 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK);
2091 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
2097 using namespace amdhsa;
2098 TwoByteBuffer = DE.
getU16(Cursor);
2099 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) {
2101 KERNARG_PRELOAD_SPEC_LENGTH);
2104 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) {
2106 KERNARG_PRELOAD_SPEC_OFFSET);
2112 ReservedBytes = DE.
getBytes(Cursor, 4);
2113 for (
int I = 0;
I < 4; ++
I) {
2114 if (ReservedBytes[
I] != 0)
2123#undef PRINT_DIRECTIVE
2129 if (Bytes.
size() != 64 || KdAddress % 64 != 0)
2141 EnableWavefrontSize32 =
2143 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
2148 KdStream <<
".amdhsa_kernel " << KdName <<
'\n';
2151 while (
C &&
C.tell() < Bytes.
size()) {
2160 KdStream <<
".end_amdhsa_kernel\n";
2165std::optional<MCDisassembler::DecodeStatus>
2187 return std::nullopt;
2212 if (Result != Symbols->end()) {
2219 ReferencedAddresses.push_back(
static_cast<uint64_t>(
Value));
2238 std::unique_ptr<MCRelocationInfo> &&RelInfo) {
unsigned const MachineRegisterInfo * MRI
static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx, const MCRegisterInfo *MRI)
static VOPModifiers collectVOPModifiers(const MCInst &MI, bool IsVOP3P=false)
static bool isValidDPP8(const MCInst &MI)
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth)
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static DecodeStatus DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecoderUInt128 eat12Bytes(ArrayRef< uint8_t > &Bytes)
#define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK)
static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_SDWA(DecName)
static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_REG_AV10(RegClass, OpWidth)
#define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth)
#define DECODE_OPERAND_REG_8(RegClass)
#define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth)
static int64_t getInlineImmVal16(unsigned Imm)
static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static int64_t getInlineImmVal32(unsigned Imm)
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_REG_7(RegClass, OpWidth)
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
#define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth)
static int64_t getInlineImmVal64(unsigned Imm)
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth)
static DecodeStatus DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t, const MCDisassembler *Decoder)
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
#define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth)
This file contains declaration for AMDGPU ISA disassembler.
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Interface definition for SIRegisterInfo.
static constexpr uint32_t Opcode
static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm)
bool hasKernargPreload() const
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus convertSDWAInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, bool IsFP=false) const
MCOperand decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, bool IsFP=false) const
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeLiteralConstant(bool ExtendFP64) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
DecodeStatus convertMIMGInst(MCInst &MI) const
DecodeStatus convertVINTERPInst(MCInst &MI) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
DecodeStatus decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC3.
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
DecodeStatus convertEXPInst(MCInst &MI) const
bool hasArchitectedFlatScratch() const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getTtmpClassId(const OpWidthTy Width) const
std::optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth=0) const
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeSDWASrc16(unsigned Val) const
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
APInt sext(unsigned width) const
Sign extend to a new width.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This class represents an Operation in the Expression.
Context object for machine code objects.
const MCRegisterInfo * getRegisterInfo() const
MCSymbol * getOrCreateSymbol(const Twine &Name)
Lookup the symbol inside with the specified Name.
Superclass for all disassemblers.
MCContext & getContext() const
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
unsigned getNumOperands() const
unsigned getOpcode() const
void addOperand(const MCOperand Op)
const MCOperand & getOperand(unsigned i) const
Describe properties that are true of each instruction in the target description file.
Interface to description of machine instruction set.
Instances of this class represent operands of the MCInst class.
static MCOperand createReg(unsigned Reg)
static MCOperand createExpr(const MCExpr *Val)
static MCOperand createImm(int64_t Val)
unsigned getReg() const
Returns the register number.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Symbolize and annotate disassembled instructions.
StringRef - Represent a constant reference to a string, i.e.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
bool isGFX12Plus(const MCSubtargetInfo &STI)
bool hasPackedD16(const MCSubtargetInfo &STI)
bool isVOPC64DPP(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
unsigned getAmdhsaCodeObjectVersion()
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
bool isGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
@ OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
bool isGFX9Plus(const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
bool hasVOPD(const MCSubtargetInfo &STI)
@ C
The default llvm calling convention, compatible with C.
@ KERNEL_CODE_PROPERTIES_OFFSET
@ GROUP_SEGMENT_FIXED_SIZE_OFFSET
@ COMPUTE_PGM_RSRC3_OFFSET
@ KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
@ COMPUTE_PGM_RSRC1_OFFSET
@ COMPUTE_PGM_RSRC2_OFFSET
@ PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
uint16_t read16(const void *P, endianness E)
This is an optimization pass for GlobalISel generic memory operations.
int popcount(T Value) noexcept
Count the number of set bits in a value.
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Target & getTheGCNTarget()
The target for GCN GPUs.
std::vector< SymbolInfoTy > SectionSymbolsTy
unsigned M0(unsigned Val)
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Description of the encoding of one expression Op.
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.