LLVM  10.0.0svn
AMDGPUDisassembler.cpp
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1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
20 #include "AMDGPU.h"
21 #include "AMDGPURegisterInfo.h"
23 #include "SIDefines.h"
25 #include "Utils/AMDGPUBaseInfo.h"
26 #include "llvm-c/Disassembler.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/Twine.h"
30 #include "llvm/BinaryFormat/ELF.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCContext.h"
34 #include "llvm/MC/MCExpr.h"
36 #include "llvm/MC/MCInst.h"
38 #include "llvm/Support/Endian.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstddef>
46 #include <cstdint>
47 #include <iterator>
48 #include <tuple>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "amdgpu-disassembler"
54 
55 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
56  : AMDGPU::EncValues::SGPR_MAX_SI)
57 
59 
61  MCContext &Ctx,
62  MCInstrInfo const *MCII) :
63  MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
64  TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
65 
66  // ToDo: AMDGPUDisassembler supports only VI ISA.
67  if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
68  report_fatal_error("Disassembly not yet supported for subtarget");
69 }
70 
71 inline static MCDisassembler::DecodeStatus
72 addOperand(MCInst &Inst, const MCOperand& Opnd) {
73  Inst.addOperand(Opnd);
74  return Opnd.isValid() ?
77 }
78 
80  uint16_t NameIdx) {
81  int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
82  if (OpIdx != -1) {
83  auto I = MI.begin();
84  std::advance(I, OpIdx);
85  MI.insert(I, Op);
86  }
87  return OpIdx;
88 }
89 
90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
91  uint64_t Addr, const void *Decoder) {
92  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
93 
94  // Our branches take a simm16, but we need two extra bits to account for the
95  // factor of 4.
96  APInt SignedOffset(18, Imm * 4, true);
97  int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
98 
99  if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
101  return addOperand(Inst, MCOperand::createImm(Imm));
102 }
103 
104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
105  uint64_t Addr, const void *Decoder) {
106  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
107  return addOperand(Inst, DAsm->decodeBoolReg(Val));
108 }
109 
110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111 static DecodeStatus StaticDecoderName(MCInst &Inst, \
112  unsigned Imm, \
113  uint64_t /*Addr*/, \
114  const void *Decoder) { \
115  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
116  return addOperand(Inst, DAsm->DecoderName(Imm)); \
117 }
118 
119 #define DECODE_OPERAND_REG(RegClass) \
120 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
121 
122 DECODE_OPERAND_REG(VGPR_32)
123 DECODE_OPERAND_REG(VRegOrLds_32)
124 DECODE_OPERAND_REG(VS_32)
125 DECODE_OPERAND_REG(VS_64)
126 DECODE_OPERAND_REG(VS_128)
127 
128 DECODE_OPERAND_REG(VReg_64)
129 DECODE_OPERAND_REG(VReg_96)
130 DECODE_OPERAND_REG(VReg_128)
131 
132 DECODE_OPERAND_REG(SReg_32)
133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
135 DECODE_OPERAND_REG(SRegOrLds_32)
136 DECODE_OPERAND_REG(SReg_64)
137 DECODE_OPERAND_REG(SReg_64_XEXEC)
138 DECODE_OPERAND_REG(SReg_128)
139 DECODE_OPERAND_REG(SReg_256)
140 DECODE_OPERAND_REG(SReg_512)
141 
142 DECODE_OPERAND_REG(AGPR_32)
143 DECODE_OPERAND_REG(AReg_128)
144 DECODE_OPERAND_REG(AReg_512)
145 DECODE_OPERAND_REG(AReg_1024)
146 DECODE_OPERAND_REG(AV_32)
147 DECODE_OPERAND_REG(AV_64)
148 
150  unsigned Imm,
151  uint64_t Addr,
152  const void *Decoder) {
153  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
154  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
155 }
156 
158  unsigned Imm,
159  uint64_t Addr,
160  const void *Decoder) {
161  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
162  return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
163 }
164 
166  unsigned Imm,
167  uint64_t Addr,
168  const void *Decoder) {
169  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
170  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
171 }
172 
174  unsigned Imm,
175  uint64_t Addr,
176  const void *Decoder) {
177  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
178  return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
179 }
180 
182  unsigned Imm,
183  uint64_t Addr,
184  const void *Decoder) {
185  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
186  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
187 }
188 
190  unsigned Imm,
191  uint64_t Addr,
192  const void *Decoder) {
193  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
194  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
195 }
196 
198  unsigned Imm,
199  uint64_t Addr,
200  const void *Decoder) {
201  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
202  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
203 }
204 
206  unsigned Imm,
207  uint64_t Addr,
208  const void *Decoder) {
209  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
210  return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
211 }
212 
214  unsigned Imm,
215  uint64_t Addr,
216  const void *Decoder) {
217  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
218  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
219 }
220 
221 #define DECODE_SDWA(DecName) \
222 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
223 
224 DECODE_SDWA(Src32)
225 DECODE_SDWA(Src16)
226 DECODE_SDWA(VopcDst)
227 
228 #include "AMDGPUGenDisassemblerTables.inc"
229 
230 //===----------------------------------------------------------------------===//
231 //
232 //===----------------------------------------------------------------------===//
233 
234 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
235  assert(Bytes.size() >= sizeof(T));
236  const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
237  Bytes = Bytes.slice(sizeof(T));
238  return Res;
239 }
240 
242  MCInst &MI,
243  uint64_t Inst,
244  uint64_t Address) const {
245  assert(MI.getOpcode() == 0);
246  assert(MI.getNumOperands() == 0);
247  MCInst TmpInst;
248  HasLiteral = false;
249  const auto SavedBytes = Bytes;
250  if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
251  MI = TmpInst;
253  }
254  Bytes = SavedBytes;
255  return MCDisassembler::Fail;
256 }
257 
258 static bool isValidDPP8(const MCInst &MI) {
259  using namespace llvm::AMDGPU::DPP;
260  int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
261  assert(FiIdx != -1);
262  if ((unsigned)FiIdx >= MI.getNumOperands())
263  return false;
264  unsigned Fi = MI.getOperand(FiIdx).getImm();
265  return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
266 }
267 
269  ArrayRef<uint8_t> Bytes_,
270  uint64_t Address,
271  raw_ostream &WS,
272  raw_ostream &CS) const {
273  CommentStream = &CS;
274  bool IsSDWA = false;
275 
276  unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
277  Bytes = Bytes_.slice(0, MaxInstBytesNum);
278 
280  do {
281  // ToDo: better to switch encoding length using some bit predicate
282  // but it is unknown yet, so try all we can
283 
284  // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
285  // encodings
286  if (Bytes.size() >= 8) {
287  const uint64_t QW = eatBytes<uint64_t>(Bytes);
288 
289  Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
290  if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
291  break;
292 
293  MI = MCInst(); // clear
294 
295  Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
296  if (Res) break;
297 
298  Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
299  if (Res) { IsSDWA = true; break; }
300 
301  Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
302  if (Res) { IsSDWA = true; break; }
303 
304  Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
305  if (Res) { IsSDWA = true; break; }
306 
307  // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
308  // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
309  // table first so we print the correct name.
310 
311  if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
312  Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
313  if (Res) break;
314  }
315 
316  if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
317  Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
318  if (Res)
319  break;
320  }
321 
322  // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
323  // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
324  // table first so we print the correct name.
325  if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
326  Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
327  if (Res)
328  break;
329  }
330  }
331 
332  // Reinitialize Bytes as DPP64 could have eaten too much
333  Bytes = Bytes_.slice(0, MaxInstBytesNum);
334 
335  // Try decode 32-bit instruction
336  if (Bytes.size() < 4) break;
337  const uint32_t DW = eatBytes<uint32_t>(Bytes);
338  Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
339  if (Res) break;
340 
341  Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
342  if (Res) break;
343 
344  Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
345  if (Res) break;
346 
347  Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
348  if (Res) break;
349 
350  if (Bytes.size() < 4) break;
351  const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
352  Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
353  if (Res) break;
354 
355  Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
356  if (Res) break;
357 
358  Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
359  if (Res) break;
360 
361  Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
362  } while (false);
363 
364  if (Res && (MaxInstBytesNum - Bytes.size()) == 12 && (!HasLiteral ||
365  !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
366  MaxInstBytesNum = 8;
367  Bytes = Bytes_.slice(0, MaxInstBytesNum);
368  eatBytes<uint64_t>(Bytes);
369  }
370 
371  if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
372  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
373  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
374  MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
375  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
376  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
377  MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
378  // Insert dummy unused src2_modifiers.
380  AMDGPU::OpName::src2_modifiers);
381  }
382 
383  if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
384  int VAddr0Idx =
385  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
386  int RsrcIdx =
387  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
388  unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
389  if (VAddr0Idx >= 0 && NSAArgs > 0) {
390  unsigned NSAWords = (NSAArgs + 3) / 4;
391  if (Bytes.size() < 4 * NSAWords) {
392  Res = MCDisassembler::Fail;
393  } else {
394  for (unsigned i = 0; i < NSAArgs; ++i) {
395  MI.insert(MI.begin() + VAddr0Idx + 1 + i,
396  decodeOperand_VGPR_32(Bytes[i]));
397  }
398  Bytes = Bytes.slice(4 * NSAWords);
399  }
400  }
401 
402  if (Res)
403  Res = convertMIMGInst(MI);
404  }
405 
406  if (Res && IsSDWA)
407  Res = convertSDWAInst(MI);
408 
409  int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
410  AMDGPU::OpName::vdst_in);
411  if (VDstIn_Idx != -1) {
412  int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
414  if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
415  !MI.getOperand(VDstIn_Idx).isReg() ||
416  MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
417  if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
418  MI.erase(&MI.getOperand(VDstIn_Idx));
421  AMDGPU::OpName::vdst_in);
422  }
423  }
424 
425  // if the opcode was not recognized we'll assume a Size of 4 bytes
426  // (unless there are fewer bytes left)
427  Size = Res ? (MaxInstBytesNum - Bytes.size())
428  : std::min((size_t)4, Bytes_.size());
429  return Res;
430 }
431 
433  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
434  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
435  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
436  // VOPC - insert clamp
437  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
438  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
439  int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
440  if (SDst != -1) {
441  // VOPC - insert VCC register as sdst
442  insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
443  AMDGPU::OpName::sdst);
444  } else {
445  // VOP1/2 - insert omod if present in instruction
446  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
447  }
448  }
450 }
451 
453  unsigned Opc = MI.getOpcode();
454  unsigned DescNumOps = MCII->get(Opc).getNumOperands();
455 
456  // Insert dummy unused src modifiers.
457  if (MI.getNumOperands() < DescNumOps &&
458  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
460  AMDGPU::OpName::src0_modifiers);
461 
462  if (MI.getNumOperands() < DescNumOps &&
463  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
465  AMDGPU::OpName::src1_modifiers);
466 
468 }
469 
470 // Note that before gfx10, the MIMG encoding provided no information about
471 // VADDR size. Consequently, decoded instructions always show address as if it
472 // has 1 dword, which could be not really so.
474 
475  int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
476  AMDGPU::OpName::vdst);
477 
478  int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
479  AMDGPU::OpName::vdata);
480  int VAddr0Idx =
481  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
482  int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
483  AMDGPU::OpName::dmask);
484 
485  int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
486  AMDGPU::OpName::tfe);
487  int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
488  AMDGPU::OpName::d16);
489 
490  assert(VDataIdx != -1);
491  assert(DMaskIdx != -1);
492  assert(TFEIdx != -1);
493 
495  bool IsAtomic = (VDstIdx != -1);
496  bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
497 
498  bool IsNSA = false;
499  unsigned AddrSize = Info->VAddrDwords;
500 
501  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
502  unsigned DimIdx =
503  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
504  const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
506  const AMDGPU::MIMGDimInfo *Dim =
508 
509  AddrSize = BaseOpcode->NumExtraArgs +
510  (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
511  (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
512  (BaseOpcode->LodOrClampOrMip ? 1 : 0);
513  IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
514  if (!IsNSA) {
515  if (AddrSize > 8)
516  AddrSize = 16;
517  else if (AddrSize > 4)
518  AddrSize = 8;
519  } else {
520  if (AddrSize > Info->VAddrDwords) {
521  // The NSA encoding does not contain enough operands for the combination
522  // of base opcode / dimension. Should this be an error?
524  }
525  }
526  }
527 
528  unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
529  unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
530 
531  bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
532  if (D16 && AMDGPU::hasPackedD16(STI)) {
533  DstSize = (DstSize + 1) / 2;
534  }
535 
536  // FIXME: Add tfe support
537  if (MI.getOperand(TFEIdx).getImm())
539 
540  if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
542 
543  int NewOpcode =
544  AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
545  if (NewOpcode == -1)
547 
548  // Widen the register to the correct number of enabled channels.
549  unsigned NewVdata = AMDGPU::NoRegister;
550  if (DstSize != Info->VDataDwords) {
551  auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
552 
553  // Get first subregister of VData
554  unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
555  unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
556  Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
557 
558  NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
559  &MRI.getRegClass(DataRCID));
560  if (NewVdata == AMDGPU::NoRegister) {
561  // It's possible to encode this such that the low register + enabled
562  // components exceeds the register count.
564  }
565  }
566 
567  unsigned NewVAddr0 = AMDGPU::NoRegister;
568  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
569  AddrSize != Info->VAddrDwords) {
570  unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
571  unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
572  VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
573 
574  auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
575  NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
576  &MRI.getRegClass(AddrRCID));
577  if (NewVAddr0 == AMDGPU::NoRegister)
579  }
580 
581  MI.setOpcode(NewOpcode);
582 
583  if (NewVdata != AMDGPU::NoRegister) {
584  MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
585 
586  if (IsAtomic) {
587  // Atomic operations have an additional operand (a copy of data)
588  MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
589  }
590  }
591 
592  if (NewVAddr0 != AMDGPU::NoRegister) {
593  MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
594  } else if (IsNSA) {
595  assert(AddrSize <= Info->VAddrDwords);
596  MI.erase(MI.begin() + VAddr0Idx + AddrSize,
597  MI.begin() + VAddr0Idx + Info->VAddrDwords);
598  }
599 
601 }
602 
603 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
604  return getContext().getRegisterInfo()->
605  getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
606 }
607 
608 inline
610  const Twine& ErrMsg) const {
611  *CommentStream << "Error: " + ErrMsg;
612 
613  // ToDo: add support for error operands to MCInst.h
614  // return MCOperand::createError(V);
615  return MCOperand();
616 }
617 
618 inline
620  return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
621 }
622 
623 inline
625  unsigned Val) const {
626  const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
627  if (Val >= RegCl.getNumRegs())
628  return errOperand(Val, Twine(getRegClassName(RegClassID)) +
629  ": unknown register " + Twine(Val));
630  return createRegOperand(RegCl.getRegister(Val));
631 }
632 
633 inline
635  unsigned Val) const {
636  // ToDo: SI/CI have 104 SGPRs, VI - 102
637  // Valery: here we accepting as much as we can, let assembler sort it out
638  int shift = 0;
639  switch (SRegClassID) {
640  case AMDGPU::SGPR_32RegClassID:
641  case AMDGPU::TTMP_32RegClassID:
642  break;
643  case AMDGPU::SGPR_64RegClassID:
644  case AMDGPU::TTMP_64RegClassID:
645  shift = 1;
646  break;
647  case AMDGPU::SGPR_128RegClassID:
648  case AMDGPU::TTMP_128RegClassID:
649  // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
650  // this bundle?
651  case AMDGPU::SGPR_256RegClassID:
652  case AMDGPU::TTMP_256RegClassID:
653  // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
654  // this bundle?
655  case AMDGPU::SGPR_512RegClassID:
656  case AMDGPU::TTMP_512RegClassID:
657  shift = 2;
658  break;
659  // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
660  // this bundle?
661  default:
662  llvm_unreachable("unhandled register class");
663  }
664 
665  if (Val % (1 << shift)) {
666  *CommentStream << "Warning: " << getRegClassName(SRegClassID)
667  << ": scalar reg isn't aligned " << Val;
668  }
669 
670  return createRegOperand(SRegClassID, Val >> shift);
671 }
672 
674  return decodeSrcOp(OPW32, Val);
675 }
676 
678  return decodeSrcOp(OPW64, Val);
679 }
680 
682  return decodeSrcOp(OPW128, Val);
683 }
684 
686  return decodeSrcOp(OPW16, Val);
687 }
688 
690  return decodeSrcOp(OPWV216, Val);
691 }
692 
694  // Some instructions have operand restrictions beyond what the encoding
695  // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
696  // high bit.
697  Val &= 255;
698 
699  return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
700 }
701 
703  return decodeSrcOp(OPW32, Val);
704 }
705 
707  return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
708 }
709 
711  return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
712 }
713 
715  return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
716 }
717 
719  return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
720 }
721 
723  return decodeSrcOp(OPW32, Val);
724 }
725 
727  return decodeSrcOp(OPW64, Val);
728 }
729 
731  return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
732 }
733 
735  return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
736 }
737 
739  return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
740 }
741 
743  return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
744 }
745 
747  return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
748 }
749 
751  // table-gen generated disassembler doesn't care about operand types
752  // leaving only registry class so SSrc_32 operand turns into SReg_32
753  // and therefore we accept immediates and literals here as well
754  return decodeSrcOp(OPW32, Val);
755 }
756 
758  unsigned Val) const {
759  // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
760  return decodeOperand_SReg_32(Val);
761 }
762 
764  unsigned Val) const {
765  // SReg_32_XM0 is SReg_32 without EXEC_HI
766  return decodeOperand_SReg_32(Val);
767 }
768 
770  // table-gen generated disassembler doesn't care about operand types
771  // leaving only registry class so SSrc_32 operand turns into SReg_32
772  // and therefore we accept immediates and literals here as well
773  return decodeSrcOp(OPW32, Val);
774 }
775 
777  return decodeSrcOp(OPW64, Val);
778 }
779 
781  return decodeSrcOp(OPW64, Val);
782 }
783 
785  return decodeSrcOp(OPW128, Val);
786 }
787 
789  return decodeDstOp(OPW256, Val);
790 }
791 
793  return decodeDstOp(OPW512, Val);
794 }
795 
797  // For now all literal constants are supposed to be unsigned integer
798  // ToDo: deal with signed/unsigned 64-bit integer constants
799  // ToDo: deal with float/double constants
800  if (!HasLiteral) {
801  if (Bytes.size() < 4) {
802  return errOperand(0, "cannot read literal, inst bytes left " +
803  Twine(Bytes.size()));
804  }
805  HasLiteral = true;
806  Literal = eatBytes<uint32_t>(Bytes);
807  }
809 }
810 
812  using namespace AMDGPU::EncValues;
813 
816  (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
817  (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
818  // Cast prevents negative overflow.
819 }
820 
821 static int64_t getInlineImmVal32(unsigned Imm) {
822  switch (Imm) {
823  case 240:
824  return FloatToBits(0.5f);
825  case 241:
826  return FloatToBits(-0.5f);
827  case 242:
828  return FloatToBits(1.0f);
829  case 243:
830  return FloatToBits(-1.0f);
831  case 244:
832  return FloatToBits(2.0f);
833  case 245:
834  return FloatToBits(-2.0f);
835  case 246:
836  return FloatToBits(4.0f);
837  case 247:
838  return FloatToBits(-4.0f);
839  case 248: // 1 / (2 * PI)
840  return 0x3e22f983;
841  default:
842  llvm_unreachable("invalid fp inline imm");
843  }
844 }
845 
846 static int64_t getInlineImmVal64(unsigned Imm) {
847  switch (Imm) {
848  case 240:
849  return DoubleToBits(0.5);
850  case 241:
851  return DoubleToBits(-0.5);
852  case 242:
853  return DoubleToBits(1.0);
854  case 243:
855  return DoubleToBits(-1.0);
856  case 244:
857  return DoubleToBits(2.0);
858  case 245:
859  return DoubleToBits(-2.0);
860  case 246:
861  return DoubleToBits(4.0);
862  case 247:
863  return DoubleToBits(-4.0);
864  case 248: // 1 / (2 * PI)
865  return 0x3fc45f306dc9c882;
866  default:
867  llvm_unreachable("invalid fp inline imm");
868  }
869 }
870 
871 static int64_t getInlineImmVal16(unsigned Imm) {
872  switch (Imm) {
873  case 240:
874  return 0x3800;
875  case 241:
876  return 0xB800;
877  case 242:
878  return 0x3C00;
879  case 243:
880  return 0xBC00;
881  case 244:
882  return 0x4000;
883  case 245:
884  return 0xC000;
885  case 246:
886  return 0x4400;
887  case 247:
888  return 0xC400;
889  case 248: // 1 / (2 * PI)
890  return 0x3118;
891  default:
892  llvm_unreachable("invalid fp inline imm");
893  }
894 }
895 
899 
900  // ToDo: case 248: 1/(2*PI) - is allowed only on VI
901  switch (Width) {
902  case OPW32:
903  case OPW128: // splat constants
904  case OPW512:
905  case OPW1024:
907  case OPW64:
909  case OPW16:
910  case OPWV216:
912  default:
913  llvm_unreachable("implement me");
914  }
915 }
916 
918  using namespace AMDGPU;
919 
920  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
921  switch (Width) {
922  default: // fall
923  case OPW32:
924  case OPW16:
925  case OPWV216:
926  return VGPR_32RegClassID;
927  case OPW64: return VReg_64RegClassID;
928  case OPW128: return VReg_128RegClassID;
929  }
930 }
931 
933  using namespace AMDGPU;
934 
935  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
936  switch (Width) {
937  default: // fall
938  case OPW32:
939  case OPW16:
940  case OPWV216:
941  return AGPR_32RegClassID;
942  case OPW64: return AReg_64RegClassID;
943  case OPW128: return AReg_128RegClassID;
944  case OPW512: return AReg_512RegClassID;
945  case OPW1024: return AReg_1024RegClassID;
946  }
947 }
948 
949 
951  using namespace AMDGPU;
952 
953  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
954  switch (Width) {
955  default: // fall
956  case OPW32:
957  case OPW16:
958  case OPWV216:
959  return SGPR_32RegClassID;
960  case OPW64: return SGPR_64RegClassID;
961  case OPW128: return SGPR_128RegClassID;
962  case OPW256: return SGPR_256RegClassID;
963  case OPW512: return SGPR_512RegClassID;
964  }
965 }
966 
968  using namespace AMDGPU;
969 
970  assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
971  switch (Width) {
972  default: // fall
973  case OPW32:
974  case OPW16:
975  case OPWV216:
976  return TTMP_32RegClassID;
977  case OPW64: return TTMP_64RegClassID;
978  case OPW128: return TTMP_128RegClassID;
979  case OPW256: return TTMP_256RegClassID;
980  case OPW512: return TTMP_512RegClassID;
981  }
982 }
983 
984 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
985  using namespace AMDGPU::EncValues;
986 
987  unsigned TTmpMin =
989  unsigned TTmpMax =
991 
992  return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
993 }
994 
996  using namespace AMDGPU::EncValues;
997 
998  assert(Val < 1024); // enum10
999 
1000  bool IsAGPR = Val & 512;
1001  Val &= 511;
1002 
1003  if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1004  return createRegOperand(IsAGPR ? getAgprClassId(Width)
1005  : getVgprClassId(Width), Val - VGPR_MIN);
1006  }
1007  if (Val <= SGPR_MAX) {
1008  assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1009  return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1010  }
1011 
1012  int TTmpIdx = getTTmpIdx(Val);
1013  if (TTmpIdx >= 0) {
1014  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1015  }
1016 
1017  if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1018  return decodeIntImmed(Val);
1019 
1020  if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1021  return decodeFPImmed(Width, Val);
1022 
1023  if (Val == LITERAL_CONST)
1024  return decodeLiteralConstant();
1025 
1026  switch (Width) {
1027  case OPW32:
1028  case OPW16:
1029  case OPWV216:
1030  return decodeSpecialReg32(Val);
1031  case OPW64:
1032  return decodeSpecialReg64(Val);
1033  default:
1034  llvm_unreachable("unexpected immediate type");
1035  }
1036 }
1037 
1039  using namespace AMDGPU::EncValues;
1040 
1041  assert(Val < 128);
1042  assert(Width == OPW256 || Width == OPW512);
1043 
1044  if (Val <= SGPR_MAX) {
1045  assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1046  return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1047  }
1048 
1049  int TTmpIdx = getTTmpIdx(Val);
1050  if (TTmpIdx >= 0) {
1051  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1052  }
1053 
1054  llvm_unreachable("unknown dst register");
1055 }
1056 
1058  using namespace AMDGPU;
1059 
1060  switch (Val) {
1061  case 102: return createRegOperand(FLAT_SCR_LO);
1062  case 103: return createRegOperand(FLAT_SCR_HI);
1063  case 104: return createRegOperand(XNACK_MASK_LO);
1064  case 105: return createRegOperand(XNACK_MASK_HI);
1065  case 106: return createRegOperand(VCC_LO);
1066  case 107: return createRegOperand(VCC_HI);
1067  case 108: return createRegOperand(TBA_LO);
1068  case 109: return createRegOperand(TBA_HI);
1069  case 110: return createRegOperand(TMA_LO);
1070  case 111: return createRegOperand(TMA_HI);
1071  case 124: return createRegOperand(M0);
1072  case 125: return createRegOperand(SGPR_NULL);
1073  case 126: return createRegOperand(EXEC_LO);
1074  case 127: return createRegOperand(EXEC_HI);
1075  case 235: return createRegOperand(SRC_SHARED_BASE);
1076  case 236: return createRegOperand(SRC_SHARED_LIMIT);
1077  case 237: return createRegOperand(SRC_PRIVATE_BASE);
1078  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1079  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1080  case 251: return createRegOperand(SRC_VCCZ);
1081  case 252: return createRegOperand(SRC_EXECZ);
1082  case 253: return createRegOperand(SRC_SCC);
1083  case 254: return createRegOperand(LDS_DIRECT);
1084  default: break;
1085  }
1086  return errOperand(Val, "unknown operand encoding " + Twine(Val));
1087 }
1088 
1090  using namespace AMDGPU;
1091 
1092  switch (Val) {
1093  case 102: return createRegOperand(FLAT_SCR);
1094  case 104: return createRegOperand(XNACK_MASK);
1095  case 106: return createRegOperand(VCC);
1096  case 108: return createRegOperand(TBA);
1097  case 110: return createRegOperand(TMA);
1098  case 125: return createRegOperand(SGPR_NULL);
1099  case 126: return createRegOperand(EXEC);
1100  case 235: return createRegOperand(SRC_SHARED_BASE);
1101  case 236: return createRegOperand(SRC_SHARED_LIMIT);
1102  case 237: return createRegOperand(SRC_PRIVATE_BASE);
1103  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1104  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1105  case 251: return createRegOperand(SRC_VCCZ);
1106  case 252: return createRegOperand(SRC_EXECZ);
1107  case 253: return createRegOperand(SRC_SCC);
1108  default: break;
1109  }
1110  return errOperand(Val, "unknown operand encoding " + Twine(Val));
1111 }
1112 
1114  const unsigned Val) const {
1115  using namespace AMDGPU::SDWA;
1116  using namespace AMDGPU::EncValues;
1117 
1118  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1119  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1120  // XXX: cast to int is needed to avoid stupid warning:
1121  // compare with unsigned is always true
1122  if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1124  return createRegOperand(getVgprClassId(Width),
1126  }
1127  if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1130  return createSRegOperand(getSgprClassId(Width),
1132  }
1133  if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1135  return createSRegOperand(getTtmpClassId(Width),
1137  }
1138 
1139  const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1140 
1141  if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1142  return decodeIntImmed(SVal);
1143 
1144  if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1145  return decodeFPImmed(Width, SVal);
1146 
1147  return decodeSpecialReg32(SVal);
1148  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1149  return createRegOperand(getVgprClassId(Width), Val);
1150  }
1151  llvm_unreachable("unsupported target");
1152 }
1153 
1155  return decodeSDWASrc(OPW16, Val);
1156 }
1157 
1159  return decodeSDWASrc(OPW32, Val);
1160 }
1161 
1163  using namespace AMDGPU::SDWA;
1164 
1165  assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1166  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1167  "SDWAVopcDst should be present only on GFX9+");
1168 
1169  bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1170 
1173 
1174  int TTmpIdx = getTTmpIdx(Val);
1175  if (TTmpIdx >= 0) {
1176  auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1177  return createSRegOperand(TTmpClsId, TTmpIdx);
1178  } else if (Val > SGPR_MAX) {
1179  return IsWave64 ? decodeSpecialReg64(Val)
1180  : decodeSpecialReg32(Val);
1181  } else {
1182  return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1183  }
1184  } else {
1185  return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1186  }
1187 }
1188 
1190  return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1192 }
1193 
1195  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1196 }
1197 
1199  return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1200 }
1201 
1203  return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1204 }
1205 
1206 //===----------------------------------------------------------------------===//
1207 // AMDGPUSymbolizer
1208 //===----------------------------------------------------------------------===//
1209 
1210 // Try to find symbol name for specified label
1212  raw_ostream &/*cStream*/, int64_t Value,
1213  uint64_t /*Address*/, bool IsBranch,
1214  uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1215  using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
1216  using SectionSymbolsTy = std::vector<SymbolInfoTy>;
1217 
1218  if (!IsBranch) {
1219  return false;
1220  }
1221 
1222  auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1223  if (!Symbols)
1224  return false;
1225 
1226  auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1227  [Value](const SymbolInfoTy& Val) {
1228  return std::get<0>(Val) == static_cast<uint64_t>(Value)
1229  && std::get<2>(Val) == ELF::STT_NOTYPE;
1230  });
1231  if (Result != Symbols->end()) {
1232  auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
1233  const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1235  return true;
1236  }
1237  return false;
1238 }
1239 
1241  int64_t Value,
1242  uint64_t Address) {
1243  llvm_unreachable("unimplemented");
1244 }
1245 
1246 //===----------------------------------------------------------------------===//
1247 // Initialization
1248 //===----------------------------------------------------------------------===//
1249 
1251  LLVMOpInfoCallback /*GetOpInfo*/,
1252  LLVMSymbolLookupCallback /*SymbolLookUp*/,
1253  void *DisInfo,
1254  MCContext *Ctx,
1255  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1256  return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1257 }
1258 
1260  const MCSubtargetInfo &STI,
1261  MCContext &Ctx) {
1262  return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1263 }
1264 
1270 }
MCOperand createRegOperand(unsigned int RegId) const
static int64_t getInlineImmVal16(unsigned Imm)
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
MCOperand decodeOperand_VGPR_32(unsigned Val) const
iterator begin()
Definition: MCInst.h:192
Target & getTheGCNTarget()
The target for GCN GPUs.
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
bool hasPackedD16(const MCSubtargetInfo &STI)
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:888
DecodeStatus convertDPP8Inst(MCInst &MI) const
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:329
#define DECODE_OPERAND_REG(RegClass)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MCOperand decodeOperand_VReg_64(unsigned Val) const
MCOperand decodeOperand_VSrcV216(unsigned Val) const
DecodeStatus
Ternary decode status.
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
MCOperand decodeOperand_VS_128(unsigned Val) const
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:136
MCOperand decodeOperand_SReg_512(unsigned Val) const
static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
Superclass for all disassemblers.
raw_ostream * CommentStream
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
MCInstrInfo * createMCInstrInfo() const
createMCInstrInfo - Create a MCInstrInfo implementation.
const char * getRegClassName(unsigned RegClassID) const
bool isReg() const
Definition: MCInst.h:57
static T eatBytes(ArrayRef< uint8_t > &Bytes)
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
MCOperand decodeBoolReg(unsigned Val) const
MCOperand decodeOperand_VS_32(unsigned Val) const
MCOperand decodeLiteralConstant() const
MCOperand decodeOperand_AReg_128(unsigned Val) const
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
MCOperand decodeOperand_SReg_128(unsigned Val) const
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:115
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
const FeatureBitset & getFeatureBits() const
MCOperand decodeSDWAVopcDst(unsigned Val) const
void erase(iterator I)
Definition: MCInst.h:189
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
MCOperand decodeOperand_AReg_512(unsigned Val) const
LLVM_READONLY const MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t Size, int TagType, void *TagBuf)
The type for the operand information call back function.
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
This file implements a class to represent arbitrary precision integral constant values and operations...
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
TargetRegisterInfo interface that is implemented by all hw codegen targets.
static int64_t getInlineImmVal32(unsigned Imm)
Context object for machine code objects.
Definition: MCContext.h:65
DecodeStatus convertSDWAInst(MCInst &MI) const
MCOperand decodeOperand_AReg_1024(unsigned Val) const
const MCSubtargetInfo & STI
int decodeInstruction(InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode)
Decode one instruction and store the decoding results in a buffer provided by the consumer...
MCOperand decodeSDWASrc32(unsigned Val) const
MCOperand decodeOperand_VReg_256(unsigned Val) const
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
iterator insert(iterator I, const MCOperand &Op)
Definition: MCInst.h:197
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, uint64_t Inst, uint64_t Address) const
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:652
MCOperand decodeOperand_AV_64(unsigned Val) const
int64_t getImm() const
Definition: MCInst.h:75
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned const MachineRegisterInfo * MRI
MCOperand decodeOperand_VReg_128(unsigned Val) const
MCOperand decodeOperand_SReg_256(unsigned Val) const
MCOperand decodeOperand_SReg_32(unsigned Val) const
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:38
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
DecodeStatus convertMIMGInst(MCInst &MI) const
MCOperand decodeOperand_VS_64(unsigned Val) const
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
MCOperand decodeOperand_VReg_512(unsigned Val) const
unsigned getNumOperands() const
Definition: MCInst.h:181
auto find_if(R &&Range, UnaryPredicate P) -> decltype(adl_begin(Range))
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly...
Definition: STLExtras.h:1193
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const void *Decoder)
static int64_t getInlineImmVal64(unsigned Imm)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const T * data() const
Definition: ArrayRef.h:145
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
unsigned getAgprClassId(const OpWidthTy Width) const
#define SGPR_MAX
MCOperand decodeSDWASrc16(unsigned Val) const
void setOpcode(unsigned Op)
Definition: MCInst.h:170
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:556
Align max(MaybeAlign Lhs, Align Rhs)
Definition: Alignment.h:390
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
MCContext & getContext() const
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val) const
static bool isValidDPP8(const MCInst &MI)
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:642
static MCOperand decodeIntImmed(unsigned Imm)
#define DECODE_SDWA(DecName)
Target - Wrapper for Target specific information.
Class for arbitrary precision integers.
Definition: APInt.h:69
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array...
Definition: ArrayRef.h:178
MCOperand decodeOperand_AGPR_32(unsigned Val) const
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Provides AMDGPU specific target descriptions.
void LLVMInitializeAMDGPUDisassembler()
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
MCOperand decodeOperand_AV_32(unsigned Val) const
This file contains declaration for AMDGPU ISA disassembler.
MCOperand decodeOperand_VSrc16(unsigned Val) const
#define I(x, y, z)
Definition: MD5.cpp:58
Generic base class for all target subtargets.
unsigned getSgprClassId(const OpWidthTy Width) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
uint32_t Size
Definition: Profile.cpp:46
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
aarch64 promote const
MCOperand decodeOperand_SReg_64(unsigned Val) const
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:320
MCOperand decodeOperand_VReg_96(unsigned Val) const
LLVM Value Representation.
Definition: Value.h:74
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
unsigned getTtmpClassId(const OpWidthTy Width) const
MCOperand decodeSpecialReg64(unsigned Val) const
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg...
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
IRTranslator LLVM IR MI
void addOperand(const MCOperand &Op)
Definition: MCInst.h:183
bool isValid() const
Definition: MCInst.h:56
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &WS, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getOpcode() const
Definition: MCInst.h:171
MCOperand decodeSpecialReg32(unsigned Val) const
int getTTmpIdx(unsigned Val) const
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
const char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:122