LLVM  15.0.0git
AMDGPUDisassembler.cpp
Go to the documentation of this file.
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
21 #include "SIDefines.h"
22 #include "SIRegisterInfo.h"
24 #include "Utils/AMDGPUBaseInfo.h"
26 #include "llvm/BinaryFormat/ELF.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCDecoderOps.h"
30 #include "llvm/MC/MCExpr.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/MC/TargetRegistry.h"
36 
37 using namespace llvm;
38 
39 #define DEBUG_TYPE "amdgpu-disassembler"
40 
41 #define SGPR_MAX \
42  (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
43  : AMDGPU::EncValues::SGPR_MAX_SI)
44 
46 
48  MCContext &Ctx,
49  MCInstrInfo const *MCII) :
50  MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
51  TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
52 
53  // ToDo: AMDGPUDisassembler supports only VI ISA.
54  if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus())
55  report_fatal_error("Disassembly not yet supported for subtarget");
56 }
57 
58 inline static MCDisassembler::DecodeStatus
59 addOperand(MCInst &Inst, const MCOperand& Opnd) {
60  Inst.addOperand(Opnd);
61  return Opnd.isValid() ?
64 }
65 
67  uint16_t NameIdx) {
68  int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
69  if (OpIdx != -1) {
70  auto I = MI.begin();
71  std::advance(I, OpIdx);
72  MI.insert(I, Op);
73  }
74  return OpIdx;
75 }
76 
77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
78  uint64_t Addr,
79  const MCDisassembler *Decoder) {
80  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
81 
82  // Our branches take a simm16, but we need two extra bits to account for the
83  // factor of 4.
84  APInt SignedOffset(18, Imm * 4, true);
85  int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
86 
87  if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0))
89  return addOperand(Inst, MCOperand::createImm(Imm));
90 }
91 
93  const MCDisassembler *Decoder) {
94  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
95  int64_t Offset;
96  if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets.
97  Offset = Imm & 0xFFFFF;
98  } else { // GFX9+ supports 21-bit signed offsets.
99  Offset = SignExtend64<21>(Imm);
100  }
101  return addOperand(Inst, MCOperand::createImm(Offset));
102 }
103 
104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr,
105  const MCDisassembler *Decoder) {
106  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
107  return addOperand(Inst, DAsm->decodeBoolReg(Val));
108 }
109 
110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111  static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \
112  uint64_t /*Addr*/, \
113  const MCDisassembler *Decoder) { \
114  auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \
115  return addOperand(Inst, DAsm->DecoderName(Imm)); \
116  }
117 
118 #define DECODE_OPERAND_REG(RegClass) \
119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
120 
121 DECODE_OPERAND_REG(VGPR_32)
122 DECODE_OPERAND_REG(VRegOrLds_32)
123 DECODE_OPERAND_REG(VS_32)
124 DECODE_OPERAND_REG(VS_64)
125 DECODE_OPERAND_REG(VS_128)
126 
127 DECODE_OPERAND_REG(VReg_64)
128 DECODE_OPERAND_REG(VReg_96)
129 DECODE_OPERAND_REG(VReg_128)
130 DECODE_OPERAND_REG(VReg_256)
131 DECODE_OPERAND_REG(VReg_512)
132 DECODE_OPERAND_REG(VReg_1024)
133 
134 DECODE_OPERAND_REG(SReg_32)
135 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
136 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
137 DECODE_OPERAND_REG(SRegOrLds_32)
138 DECODE_OPERAND_REG(SReg_64)
139 DECODE_OPERAND_REG(SReg_64_XEXEC)
140 DECODE_OPERAND_REG(SReg_128)
141 DECODE_OPERAND_REG(SReg_256)
142 DECODE_OPERAND_REG(SReg_512)
143 
144 DECODE_OPERAND_REG(AGPR_32)
145 DECODE_OPERAND_REG(AReg_64)
146 DECODE_OPERAND_REG(AReg_128)
147 DECODE_OPERAND_REG(AReg_256)
148 DECODE_OPERAND_REG(AReg_512)
149 DECODE_OPERAND_REG(AReg_1024)
150 DECODE_OPERAND_REG(AV_32)
151 DECODE_OPERAND_REG(AV_64)
152 DECODE_OPERAND_REG(AV_128)
153 DECODE_OPERAND_REG(AVDst_128)
154 DECODE_OPERAND_REG(AVDst_512)
155 
157  uint64_t Addr,
158  const MCDisassembler *Decoder) {
159  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
160  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
161 }
162 
164  uint64_t Addr,
165  const MCDisassembler *Decoder) {
166  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
167  return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
168 }
169 
171  uint64_t Addr,
172  const MCDisassembler *Decoder) {
173  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
174  return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm));
175 }
176 
178  uint64_t Addr,
179  const MCDisassembler *Decoder) {
180  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
181  return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
182 }
183 
185  uint64_t Addr,
186  const MCDisassembler *Decoder) {
187  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
188  return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
189 }
190 
192  uint64_t Addr,
193  const MCDisassembler *Decoder) {
194  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
195  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512));
196 }
197 
199  uint64_t Addr,
200  const MCDisassembler *Decoder) {
201  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
202  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
203 }
204 
206  uint64_t Addr,
207  const MCDisassembler *Decoder) {
208  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
209  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512));
210 }
211 
213  uint64_t Addr,
214  const MCDisassembler *Decoder) {
215  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
216  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
217 }
218 
220  uint64_t Addr,
221  const MCDisassembler *Decoder) {
222  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
223  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
224 }
225 
227  uint64_t Addr,
228  const MCDisassembler *Decoder) {
229  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
230  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm));
231 }
232 
234  uint64_t Addr,
235  const MCDisassembler *Decoder) {
236  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
237  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm));
238 }
239 
241  uint64_t Addr,
242  const MCDisassembler *Decoder) {
243  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
244  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm));
245 }
246 
248  uint64_t Addr,
249  const MCDisassembler *Decoder) {
250  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
251  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm));
252 }
253 
255  uint64_t Addr,
256  const MCDisassembler *Decoder) {
257  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
258  return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm));
259 }
260 
262  uint64_t Addr,
263  const MCDisassembler *Decoder) {
264  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
265  return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
266 }
267 
269  uint64_t Addr,
270  const MCDisassembler *Decoder) {
271  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
272  return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm));
273 }
274 
275 static DecodeStatus
277  const MCDisassembler *Decoder) {
278  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
279  return addOperand(
280  Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true));
281 }
282 
283 static DecodeStatus
285  const MCDisassembler *Decoder) {
286  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
287  return addOperand(
288  Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true));
289 }
290 
291 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val,
292  uint64_t Addr, const void *Decoder) {
293  const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
294  return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val));
295 }
296 
297 static bool IsAGPROperand(const MCInst &Inst, int OpIdx,
298  const MCRegisterInfo *MRI) {
299  if (OpIdx < 0)
300  return false;
301 
302  const MCOperand &Op = Inst.getOperand(OpIdx);
303  if (!Op.isReg())
304  return false;
305 
306  unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
307  auto Reg = Sub ? Sub : Op.getReg();
308  return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255;
309 }
310 
313  const MCDisassembler *Decoder) {
314  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
315  if (!DAsm->isGFX90A()) {
316  Imm &= 511;
317  } else {
318  // If atomic has both vdata and vdst their register classes are tied.
319  // The bit is decoded along with the vdst, first operand. We need to
320  // change register class to AGPR if vdst was AGPR.
321  // If a DS instruction has both data0 and data1 their register classes
322  // are also tied.
323  unsigned Opc = Inst.getOpcode();
324  uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
325  uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
326  : AMDGPU::OpName::vdata;
327  const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
328  int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx);
329  if ((int)Inst.getNumOperands() == DataIdx) {
330  int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
331  if (IsAGPROperand(Inst, DstIdx, MRI))
332  Imm |= 512;
333  }
334 
335  if (TSFlags & SIInstrFlags::DS) {
336  int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
337  if ((int)Inst.getNumOperands() == Data2Idx &&
338  IsAGPROperand(Inst, DataIdx, MRI))
339  Imm |= 512;
340  }
341  }
342  return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256));
343 }
344 
345 static DecodeStatus
347  const MCDisassembler *Decoder) {
348  return decodeOperand_AVLdSt_Any(Inst, Imm,
349  AMDGPUDisassembler::OPW32, Decoder);
350 }
351 
352 static DecodeStatus
354  const MCDisassembler *Decoder) {
355  return decodeOperand_AVLdSt_Any(Inst, Imm,
356  AMDGPUDisassembler::OPW64, Decoder);
357 }
358 
359 static DecodeStatus
361  const MCDisassembler *Decoder) {
362  return decodeOperand_AVLdSt_Any(Inst, Imm,
363  AMDGPUDisassembler::OPW96, Decoder);
364 }
365 
366 static DecodeStatus
368  const MCDisassembler *Decoder) {
369  return decodeOperand_AVLdSt_Any(Inst, Imm,
370  AMDGPUDisassembler::OPW128, Decoder);
371 }
372 
374  uint64_t Addr,
375  const MCDisassembler *Decoder) {
376  auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
377  return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
378 }
379 
380 #define DECODE_SDWA(DecName) \
381 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
382 
383 DECODE_SDWA(Src32)
384 DECODE_SDWA(Src16)
385 DECODE_SDWA(VopcDst)
386 
387 #include "AMDGPUGenDisassemblerTables.inc"
388 
389 //===----------------------------------------------------------------------===//
390 //
391 //===----------------------------------------------------------------------===//
392 
393 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
394  assert(Bytes.size() >= sizeof(T));
395  const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
396  Bytes = Bytes.slice(sizeof(T));
397  return Res;
398 }
399 
401  assert(Bytes.size() >= 12);
402  uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>(
403  Bytes.data());
404  Bytes = Bytes.slice(8);
405  uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>(
406  Bytes.data());
407  Bytes = Bytes.slice(4);
408  return DecoderUInt128(Lo, Hi);
409 }
410 
411 // The disassembler is greedy, so we need to check FI operand value to
412 // not parse a dpp if the correct literal is not set. For dpp16 the
413 // autogenerated decoder checks the dpp literal
414 static bool isValidDPP8(const MCInst &MI) {
415  using namespace llvm::AMDGPU::DPP;
416  int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
417  assert(FiIdx != -1);
418  if ((unsigned)FiIdx >= MI.getNumOperands())
419  return false;
420  unsigned Fi = MI.getOperand(FiIdx).getImm();
421  return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
422 }
423 
425  ArrayRef<uint8_t> Bytes_,
426  uint64_t Address,
427  raw_ostream &CS) const {
428  CommentStream = &CS;
429  bool IsSDWA = false;
430 
431  unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
432  Bytes = Bytes_.slice(0, MaxInstBytesNum);
433 
435  do {
436  // ToDo: better to switch encoding length using some bit predicate
437  // but it is unknown yet, so try all we can
438 
439  // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
440  // encodings
441  if (isGFX11Plus() && Bytes.size() >= 12 ) {
442  DecoderUInt128 DecW = eat12Bytes(Bytes);
443  Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW,
444  Address);
446  break;
447  MI = MCInst(); // clear
448  Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW,
449  Address);
450  if (Res) {
451  if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P)
453  else if (AMDGPU::isVOPC64DPP(MI.getOpcode()))
455  break;
456  }
457  Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address);
458  if (Res)
459  break;
460  }
461  // Reinitialize Bytes
462  Bytes = Bytes_.slice(0, MaxInstBytesNum);
463 
464  if (Bytes.size() >= 8) {
465  const uint64_t QW = eatBytes<uint64_t>(Bytes);
466 
467  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
468  Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
469  if (Res) {
470  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
471  == -1)
472  break;
474  break;
475  MI = MCInst(); // clear
476  }
477  }
478 
479  Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
481  break;
482  MI = MCInst(); // clear
483 
484  Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address);
486  break;
487  MI = MCInst(); // clear
488 
489  Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
490  if (Res) break;
491 
492  Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address);
493  if (Res) {
494  if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC)
496  break;
497  }
498 
499  Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
500  if (Res) { IsSDWA = true; break; }
501 
502  Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
503  if (Res) { IsSDWA = true; break; }
504 
505  Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
506  if (Res) { IsSDWA = true; break; }
507 
508  if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
509  Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
510  if (Res)
511  break;
512  }
513 
514  // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
515  // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
516  // table first so we print the correct name.
517  if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
518  Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
519  if (Res)
520  break;
521  }
522  }
523 
524  // Reinitialize Bytes as DPP64 could have eaten too much
525  Bytes = Bytes_.slice(0, MaxInstBytesNum);
526 
527  // Try decode 32-bit instruction
528  if (Bytes.size() < 4) break;
529  const uint32_t DW = eatBytes<uint32_t>(Bytes);
530  Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
531  if (Res) break;
532 
533  Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
534  if (Res) break;
535 
536  Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
537  if (Res) break;
538 
539  if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) {
540  Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address);
541  if (Res)
542  break;
543  }
544 
545  if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
546  Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address);
547  if (Res) break;
548  }
549 
550  Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
551  if (Res) break;
552 
553  Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address);
554  if (Res) break;
555 
556  if (Bytes.size() < 4) break;
557  const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
558 
559  if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) {
560  Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address);
561  if (Res)
562  break;
563  }
564 
565  Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
566  if (Res) break;
567 
568  Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
569  if (Res) break;
570 
571  Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
572  if (Res) break;
573 
574  Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
575  if (Res) break;
576 
577  Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address);
578  if (Res)
579  break;
580 
581  Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address);
582  } while (false);
583 
584  if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
585  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
586  MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
587  MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
588  MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
589  MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
590  MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a ||
591  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
592  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
593  MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 ||
594  MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
595  MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
596  MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 ||
597  MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx11)) {
598  // Insert dummy unused src2_modifiers.
600  AMDGPU::OpName::src2_modifiers);
601  }
602 
603  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
605  int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
606  AMDGPU::OpName::cpol);
607  if (CPolPos != -1) {
608  unsigned CPol =
609  (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ?
610  AMDGPU::CPol::GLC : 0;
611  if (MI.getNumOperands() <= (unsigned)CPolPos) {
613  AMDGPU::OpName::cpol);
614  } else if (CPol) {
615  MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol);
616  }
617  }
618  }
619 
620  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
622  (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) {
623  // GFX90A lost TFE, its place is occupied by ACC.
624  int TFEOpIdx =
625  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe);
626  if (TFEOpIdx != -1) {
627  auto TFEIter = MI.begin();
628  std::advance(TFEIter, TFEOpIdx);
629  MI.insert(TFEIter, MCOperand::createImm(0));
630  }
631  }
632 
633  if (Res && (MCII->get(MI.getOpcode()).TSFlags &
635  int SWZOpIdx =
636  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz);
637  if (SWZOpIdx != -1) {
638  auto SWZIter = MI.begin();
639  std::advance(SWZIter, SWZOpIdx);
640  MI.insert(SWZIter, MCOperand::createImm(0));
641  }
642  }
643 
644  if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
645  int VAddr0Idx =
646  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
647  int RsrcIdx =
648  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
649  unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
650  if (VAddr0Idx >= 0 && NSAArgs > 0) {
651  unsigned NSAWords = (NSAArgs + 3) / 4;
652  if (Bytes.size() < 4 * NSAWords) {
653  Res = MCDisassembler::Fail;
654  } else {
655  for (unsigned i = 0; i < NSAArgs; ++i) {
656  const unsigned VAddrIdx = VAddr0Idx + 1 + i;
657  auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass;
658  MI.insert(MI.begin() + VAddrIdx,
659  createRegOperand(VAddrRCID, Bytes[i]));
660  }
661  Bytes = Bytes.slice(4 * NSAWords);
662  }
663  }
664 
665  if (Res)
666  Res = convertMIMGInst(MI);
667  }
668 
669  if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP))
670  Res = convertEXPInst(MI);
671 
672  if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP))
673  Res = convertVINTERPInst(MI);
674 
675  if (Res && IsSDWA)
676  Res = convertSDWAInst(MI);
677 
678  int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
679  AMDGPU::OpName::vdst_in);
680  if (VDstIn_Idx != -1) {
681  int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
683  if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
684  !MI.getOperand(VDstIn_Idx).isReg() ||
685  MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
686  if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
687  MI.erase(&MI.getOperand(VDstIn_Idx));
689  MCOperand::createReg(MI.getOperand(Tied).getReg()),
690  AMDGPU::OpName::vdst_in);
691  }
692  }
693 
694  int ImmLitIdx =
695  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);
696  if (Res && ImmLitIdx != -1)
697  Res = convertFMAanyK(MI, ImmLitIdx);
698 
699  // if the opcode was not recognized we'll assume a Size of 4 bytes
700  // (unless there are fewer bytes left)
701  Size = Res ? (MaxInstBytesNum - Bytes.size())
702  : std::min((size_t)4, Bytes_.size());
703  return Res;
704 }
705 
707  if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) {
708  // The MCInst still has these fields even though they are no longer encoded
709  // in the GFX11 instruction.
710  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm);
711  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr);
712  }
714 }
715 
717  if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 ||
718  MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 ||
719  MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 ||
720  MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) {
721  // The MCInst has this field that is not directly encoded in the
722  // instruction.
723  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel);
724  }
726 }
727 
729  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
730  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
731  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
732  // VOPC - insert clamp
734  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
735  int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
736  if (SDst != -1) {
737  // VOPC - insert VCC register as sdst
739  AMDGPU::OpName::sdst);
740  } else {
741  // VOP1/2 - insert omod if present in instruction
742  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
743  }
744  }
746 }
747 
748 // We must check FI == literal to reject not genuine dpp8 insts, and we must
749 // first add optional MI operands to check FI
751  unsigned Opc = MI.getOpcode();
752  unsigned DescNumOps = MCII->get(Opc).getNumOperands();
753  if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) {
755  } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) ||
756  AMDGPU::isVOPC64DPP(Opc)) {
758  } else {
759  // Insert dummy unused src modifiers.
760  if (MI.getNumOperands() < DescNumOps &&
761  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
763  AMDGPU::OpName::src0_modifiers);
764 
765  if (MI.getNumOperands() < DescNumOps &&
766  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
768  AMDGPU::OpName::src1_modifiers);
769  }
771 }
772 
773 // Note that before gfx10, the MIMG encoding provided no information about
774 // VADDR size. Consequently, decoded instructions always show address as if it
775 // has 1 dword, which could be not really so.
777 
778  int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
779  AMDGPU::OpName::vdst);
780 
781  int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
782  AMDGPU::OpName::vdata);
783  int VAddr0Idx =
784  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
785  int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
786  AMDGPU::OpName::dmask);
787 
788  int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
789  AMDGPU::OpName::tfe);
790  int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
791  AMDGPU::OpName::d16);
792 
793  const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
794  const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
795  AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
796 
797  assert(VDataIdx != -1);
798  if (BaseOpcode->BVH) {
799  // Add A16 operand for intersect_ray instructions
800  if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) {
802  }
804  }
805 
806  bool IsAtomic = (VDstIdx != -1);
807  bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
808  bool IsNSA = false;
809  unsigned AddrSize = Info->VAddrDwords;
810 
811  if (isGFX10Plus()) {
812  unsigned DimIdx =
813  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
814  int A16Idx =
815  AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16);
816  const AMDGPU::MIMGDimInfo *Dim =
817  AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
818  const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm());
819 
820  AddrSize =
821  AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI));
822 
823  IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA ||
824  Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA;
825  if (!IsNSA) {
826  if (AddrSize > 8)
827  AddrSize = 16;
828  } else {
829  if (AddrSize > Info->VAddrDwords) {
830  // The NSA encoding does not contain enough operands for the combination
831  // of base opcode / dimension. Should this be an error?
833  }
834  }
835  }
836 
837  unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
838  unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
839 
840  bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
841  if (D16 && AMDGPU::hasPackedD16(STI)) {
842  DstSize = (DstSize + 1) / 2;
843  }
844 
845  if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm())
846  DstSize += 1;
847 
848  if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
850 
851  int NewOpcode =
852  AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
853  if (NewOpcode == -1)
855 
856  // Widen the register to the correct number of enabled channels.
857  unsigned NewVdata = AMDGPU::NoRegister;
858  if (DstSize != Info->VDataDwords) {
859  auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
860 
861  // Get first subregister of VData
862  unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
863  unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
864  Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
865 
866  NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
867  &MRI.getRegClass(DataRCID));
868  if (NewVdata == AMDGPU::NoRegister) {
869  // It's possible to encode this such that the low register + enabled
870  // components exceeds the register count.
872  }
873  }
874 
875  // If not using NSA on GFX10+, widen address register to correct size.
876  unsigned NewVAddr0 = AMDGPU::NoRegister;
877  if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) {
878  unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
879  unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
880  VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
881 
882  auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
883  NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
884  &MRI.getRegClass(AddrRCID));
885  if (NewVAddr0 == AMDGPU::NoRegister)
887  }
888 
889  MI.setOpcode(NewOpcode);
890 
891  if (NewVdata != AMDGPU::NoRegister) {
892  MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
893 
894  if (IsAtomic) {
895  // Atomic operations have an additional operand (a copy of data)
896  MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
897  }
898  }
899 
900  if (NewVAddr0 != AMDGPU::NoRegister) {
901  MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
902  } else if (IsNSA) {
903  assert(AddrSize <= Info->VAddrDwords);
904  MI.erase(MI.begin() + VAddr0Idx + AddrSize,
905  MI.begin() + VAddr0Idx + Info->VAddrDwords);
906  }
907 
909 }
910 
911 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen
912 // decoder only adds to src_modifiers, so manually add the bits to the other
913 // operands.
915  unsigned Opc = MI.getOpcode();
916  unsigned DescNumOps = MCII->get(Opc).getNumOperands();
917 
918  if (MI.getNumOperands() < DescNumOps &&
919  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1)
920  insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in);
921 
922  const int ModOps[] = {AMDGPU::OpName::src0_modifiers,
923  AMDGPU::OpName::src1_modifiers,
924  AMDGPU::OpName::src2_modifiers};
925  unsigned OpSel = 0;
926  unsigned OpSelHi = 0;
927  unsigned NegLo = 0;
928  unsigned NegHi = 0;
929  for (int J = 0; J < 3; ++J) {
930  int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
931  if (OpIdx == -1)
932  break;
933  unsigned Val = MI.getOperand(OpIdx).getImm();
934 
935  OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J;
936  OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J;
937  NegLo |= !!(Val & SISrcMods::NEG) << J;
938  NegHi |= !!(Val & SISrcMods::NEG_HI) << J;
939  }
940 
941  if (MI.getNumOperands() < DescNumOps &&
942  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1)
944  AMDGPU::OpName::op_sel);
945  if (MI.getNumOperands() < DescNumOps &&
946  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1)
948  AMDGPU::OpName::op_sel_hi);
949  if (MI.getNumOperands() < DescNumOps &&
950  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1)
952  AMDGPU::OpName::neg_lo);
953  if (MI.getNumOperands() < DescNumOps &&
954  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1)
956  AMDGPU::OpName::neg_hi);
957 
959 }
960 
961 // Create dummy old operand and insert optional operands
963  unsigned Opc = MI.getOpcode();
964  unsigned DescNumOps = MCII->get(Opc).getNumOperands();
965 
966  if (MI.getNumOperands() < DescNumOps &&
969 
970  if (MI.getNumOperands() < DescNumOps &&
971  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
973  AMDGPU::OpName::src0_modifiers);
974 
975  if (MI.getNumOperands() < DescNumOps &&
976  AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
978  AMDGPU::OpName::src1_modifiers);
980 }
981 
983  int ImmLitIdx) const {
984  assert(HasLiteral && "Should have decoded a literal");
985  const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
986  unsigned DescNumOps = Desc.getNumOperands();
988  AMDGPU::OpName::immDeferred);
989  assert(DescNumOps == MI.getNumOperands());
990  for (unsigned I = 0; I < DescNumOps; ++I) {
991  auto &Op = MI.getOperand(I);
992  auto OpType = Desc.OpInfo[I].OperandType;
993  bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED ||
995  if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST &&
996  IsDeferredOp)
997  Op.setImm(Literal);
998  }
1000 }
1001 
1002 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
1003  return getContext().getRegisterInfo()->
1004  getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
1005 }
1006 
1007 inline
1009  const Twine& ErrMsg) const {
1010  *CommentStream << "Error: " + ErrMsg;
1011 
1012  // ToDo: add support for error operands to MCInst.h
1013  // return MCOperand::createError(V);
1014  return MCOperand();
1015 }
1016 
1017 inline
1019  return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
1020 }
1021 
1022 inline
1024  unsigned Val) const {
1025  const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
1026  if (Val >= RegCl.getNumRegs())
1027  return errOperand(Val, Twine(getRegClassName(RegClassID)) +
1028  ": unknown register " + Twine(Val));
1029  return createRegOperand(RegCl.getRegister(Val));
1030 }
1031 
1032 inline
1034  unsigned Val) const {
1035  // ToDo: SI/CI have 104 SGPRs, VI - 102
1036  // Valery: here we accepting as much as we can, let assembler sort it out
1037  int shift = 0;
1038  switch (SRegClassID) {
1039  case AMDGPU::SGPR_32RegClassID:
1040  case AMDGPU::TTMP_32RegClassID:
1041  break;
1042  case AMDGPU::SGPR_64RegClassID:
1043  case AMDGPU::TTMP_64RegClassID:
1044  shift = 1;
1045  break;
1046  case AMDGPU::SGPR_128RegClassID:
1047  case AMDGPU::TTMP_128RegClassID:
1048  // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
1049  // this bundle?
1050  case AMDGPU::SGPR_256RegClassID:
1051  case AMDGPU::TTMP_256RegClassID:
1052  // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
1053  // this bundle?
1054  case AMDGPU::SGPR_512RegClassID:
1055  case AMDGPU::TTMP_512RegClassID:
1056  shift = 2;
1057  break;
1058  // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
1059  // this bundle?
1060  default:
1061  llvm_unreachable("unhandled register class");
1062  }
1063 
1064  if (Val % (1 << shift)) {
1065  *CommentStream << "Warning: " << getRegClassName(SRegClassID)
1066  << ": scalar reg isn't aligned " << Val;
1067  }
1068 
1069  return createRegOperand(SRegClassID, Val >> shift);
1070 }
1071 
1073  return decodeSrcOp(OPW32, Val);
1074 }
1075 
1077  return decodeSrcOp(OPW64, Val);
1078 }
1079 
1081  return decodeSrcOp(OPW128, Val);
1082 }
1083 
1085  return decodeSrcOp(OPW16, Val);
1086 }
1087 
1089  return decodeSrcOp(OPWV216, Val);
1090 }
1091 
1093  return decodeSrcOp(OPWV232, Val);
1094 }
1095 
1097  // Some instructions have operand restrictions beyond what the encoding
1098  // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
1099  // high bit.
1100  Val &= 255;
1101 
1102  return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
1103 }
1104 
1106  return decodeSrcOp(OPW32, Val);
1107 }
1108 
1110  return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
1111 }
1112 
1114  return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255);
1115 }
1116 
1118  return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
1119 }
1120 
1122  return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255);
1123 }
1124 
1126  return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
1127 }
1128 
1130  return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
1131 }
1132 
1134  return decodeSrcOp(OPW32, Val);
1135 }
1136 
1138  return decodeSrcOp(OPW64, Val);
1139 }
1140 
1142  return decodeSrcOp(OPW128, Val);
1143 }
1144 
1146  using namespace AMDGPU::EncValues;
1147  assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1.
1148  return decodeSrcOp(OPW128, Val | IS_VGPR);
1149 }
1150 
1152  using namespace AMDGPU::EncValues;
1153  assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1.
1154  return decodeSrcOp(OPW512, Val | IS_VGPR);
1155 }
1156 
1158  return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
1159 }
1160 
1162  return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
1163 }
1164 
1166  return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
1167 }
1168 
1170  return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
1171 }
1172 
1174  return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
1175 }
1176 
1178  return createRegOperand(AMDGPU::VReg_1024RegClassID, Val);
1179 }
1180 
1182  // table-gen generated disassembler doesn't care about operand types
1183  // leaving only registry class so SSrc_32 operand turns into SReg_32
1184  // and therefore we accept immediates and literals here as well
1185  return decodeSrcOp(OPW32, Val);
1186 }
1187 
1189  unsigned Val) const {
1190  // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
1191  return decodeOperand_SReg_32(Val);
1192 }
1193 
1195  unsigned Val) const {
1196  // SReg_32_XM0 is SReg_32 without EXEC_HI
1197  return decodeOperand_SReg_32(Val);
1198 }
1199 
1201  // table-gen generated disassembler doesn't care about operand types
1202  // leaving only registry class so SSrc_32 operand turns into SReg_32
1203  // and therefore we accept immediates and literals here as well
1204  return decodeSrcOp(OPW32, Val);
1205 }
1206 
1208  return decodeSrcOp(OPW64, Val);
1209 }
1210 
1212  return decodeSrcOp(OPW64, Val);
1213 }
1214 
1216  return decodeSrcOp(OPW128, Val);
1217 }
1218 
1220  return decodeDstOp(OPW256, Val);
1221 }
1222 
1224  return decodeDstOp(OPW512, Val);
1225 }
1226 
1227 // Decode Literals for insts which always have a literal in the encoding
1228 MCOperand
1230  if (HasLiteral) {
1231  assert(
1232  AMDGPU::hasVOPD(STI) &&
1233  "Should only decode multiple kimm with VOPD, check VSrc operand types");
1234  if (Literal != Val)
1235  return errOperand(Val, "More than one unique literal is illegal");
1236  }
1237  HasLiteral = true;
1238  Literal = Val;
1239  return MCOperand::createImm(Literal);
1240 }
1241 
1243  // For now all literal constants are supposed to be unsigned integer
1244  // ToDo: deal with signed/unsigned 64-bit integer constants
1245  // ToDo: deal with float/double constants
1246  if (!HasLiteral) {
1247  if (Bytes.size() < 4) {
1248  return errOperand(0, "cannot read literal, inst bytes left " +
1249  Twine(Bytes.size()));
1250  }
1251  HasLiteral = true;
1252  Literal = eatBytes<uint32_t>(Bytes);
1253  }
1254  return MCOperand::createImm(Literal);
1255 }
1256 
1258  using namespace AMDGPU::EncValues;
1259 
1262  (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
1263  (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
1264  // Cast prevents negative overflow.
1265 }
1266 
1267 static int64_t getInlineImmVal32(unsigned Imm) {
1268  switch (Imm) {
1269  case 240:
1270  return FloatToBits(0.5f);
1271  case 241:
1272  return FloatToBits(-0.5f);
1273  case 242:
1274  return FloatToBits(1.0f);
1275  case 243:
1276  return FloatToBits(-1.0f);
1277  case 244:
1278  return FloatToBits(2.0f);
1279  case 245:
1280  return FloatToBits(-2.0f);
1281  case 246:
1282  return FloatToBits(4.0f);
1283  case 247:
1284  return FloatToBits(-4.0f);
1285  case 248: // 1 / (2 * PI)
1286  return 0x3e22f983;
1287  default:
1288  llvm_unreachable("invalid fp inline imm");
1289  }
1290 }
1291 
1292 static int64_t getInlineImmVal64(unsigned Imm) {
1293  switch (Imm) {
1294  case 240:
1295  return DoubleToBits(0.5);
1296  case 241:
1297  return DoubleToBits(-0.5);
1298  case 242:
1299  return DoubleToBits(1.0);
1300  case 243:
1301  return DoubleToBits(-1.0);
1302  case 244:
1303  return DoubleToBits(2.0);
1304  case 245:
1305  return DoubleToBits(-2.0);
1306  case 246:
1307  return DoubleToBits(4.0);
1308  case 247:
1309  return DoubleToBits(-4.0);
1310  case 248: // 1 / (2 * PI)
1311  return 0x3fc45f306dc9c882;
1312  default:
1313  llvm_unreachable("invalid fp inline imm");
1314  }
1315 }
1316 
1317 static int64_t getInlineImmVal16(unsigned Imm) {
1318  switch (Imm) {
1319  case 240:
1320  return 0x3800;
1321  case 241:
1322  return 0xB800;
1323  case 242:
1324  return 0x3C00;
1325  case 243:
1326  return 0xBC00;
1327  case 244:
1328  return 0x4000;
1329  case 245:
1330  return 0xC000;
1331  case 246:
1332  return 0x4400;
1333  case 247:
1334  return 0xC400;
1335  case 248: // 1 / (2 * PI)
1336  return 0x3118;
1337  default:
1338  llvm_unreachable("invalid fp inline imm");
1339  }
1340 }
1341 
1345 
1346  // ToDo: case 248: 1/(2*PI) - is allowed only on VI
1347  switch (Width) {
1348  case OPW32:
1349  case OPW128: // splat constants
1350  case OPW512:
1351  case OPW1024:
1352  case OPWV232:
1354  case OPW64:
1355  case OPW256:
1357  case OPW16:
1358  case OPWV216:
1360  default:
1361  llvm_unreachable("implement me");
1362  }
1363 }
1364 
1366  using namespace AMDGPU;
1367 
1369  switch (Width) {
1370  default: // fall
1371  case OPW32:
1372  case OPW16:
1373  case OPWV216:
1374  return VGPR_32RegClassID;
1375  case OPW64:
1376  case OPWV232: return VReg_64RegClassID;
1377  case OPW96: return VReg_96RegClassID;
1378  case OPW128: return VReg_128RegClassID;
1379  case OPW160: return VReg_160RegClassID;
1380  case OPW256: return VReg_256RegClassID;
1381  case OPW512: return VReg_512RegClassID;
1382  case OPW1024: return VReg_1024RegClassID;
1383  }
1384 }
1385 
1387  using namespace AMDGPU;
1388 
1390  switch (Width) {
1391  default: // fall
1392  case OPW32:
1393  case OPW16:
1394  case OPWV216:
1395  return AGPR_32RegClassID;
1396  case OPW64:
1397  case OPWV232: return AReg_64RegClassID;
1398  case OPW96: return AReg_96RegClassID;
1399  case OPW128: return AReg_128RegClassID;
1400  case OPW160: return AReg_160RegClassID;
1401  case OPW256: return AReg_256RegClassID;
1402  case OPW512: return AReg_512RegClassID;
1403  case OPW1024: return AReg_1024RegClassID;
1404  }
1405 }
1406 
1407 
1409  using namespace AMDGPU;
1410 
1412  switch (Width) {
1413  default: // fall
1414  case OPW32:
1415  case OPW16:
1416  case OPWV216:
1417  return SGPR_32RegClassID;
1418  case OPW64:
1419  case OPWV232: return SGPR_64RegClassID;
1420  case OPW96: return SGPR_96RegClassID;
1421  case OPW128: return SGPR_128RegClassID;
1422  case OPW160: return SGPR_160RegClassID;
1423  case OPW256: return SGPR_256RegClassID;
1424  case OPW512: return SGPR_512RegClassID;
1425  }
1426 }
1427 
1429  using namespace AMDGPU;
1430 
1432  switch (Width) {
1433  default: // fall
1434  case OPW32:
1435  case OPW16:
1436  case OPWV216:
1437  return TTMP_32RegClassID;
1438  case OPW64:
1439  case OPWV232: return TTMP_64RegClassID;
1440  case OPW128: return TTMP_128RegClassID;
1441  case OPW256: return TTMP_256RegClassID;
1442  case OPW512: return TTMP_512RegClassID;
1443  }
1444 }
1445 
1446 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1447  using namespace AMDGPU::EncValues;
1448 
1449  unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN;
1450  unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX;
1451 
1452  return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1453 }
1454 
1456  bool MandatoryLiteral) const {
1457  using namespace AMDGPU::EncValues;
1458 
1459  assert(Val < 1024); // enum10
1460 
1461  bool IsAGPR = Val & 512;
1462  Val &= 511;
1463 
1464  if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1465  return createRegOperand(IsAGPR ? getAgprClassId(Width)
1466  : getVgprClassId(Width), Val - VGPR_MIN);
1467  }
1468  if (Val <= SGPR_MAX) {
1469  // "SGPR_MIN <= Val" is always true and causes compilation warning.
1470  static_assert(SGPR_MIN == 0, "");
1472  }
1473 
1474  int TTmpIdx = getTTmpIdx(Val);
1475  if (TTmpIdx >= 0) {
1476  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1477  }
1478 
1479  if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1480  return decodeIntImmed(Val);
1481 
1482  if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1483  return decodeFPImmed(Width, Val);
1484 
1485  if (Val == LITERAL_CONST) {
1486  if (MandatoryLiteral)
1487  // Keep a sentinel value for deferred setting
1489  else
1490  return decodeLiteralConstant();
1491  }
1492 
1493  switch (Width) {
1494  case OPW32:
1495  case OPW16:
1496  case OPWV216:
1497  return decodeSpecialReg32(Val);
1498  case OPW64:
1499  case OPWV232:
1500  return decodeSpecialReg64(Val);
1501  default:
1502  llvm_unreachable("unexpected immediate type");
1503  }
1504 }
1505 
1507  using namespace AMDGPU::EncValues;
1508 
1509  assert(Val < 128);
1510  assert(Width == OPW256 || Width == OPW512);
1511 
1512  if (Val <= SGPR_MAX) {
1513  // "SGPR_MIN <= Val" is always true and causes compilation warning.
1514  static_assert(SGPR_MIN == 0, "");
1516  }
1517 
1518  int TTmpIdx = getTTmpIdx(Val);
1519  if (TTmpIdx >= 0) {
1520  return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1521  }
1522 
1523  llvm_unreachable("unknown dst register");
1524 }
1525 
1526 // Bit 0 of DstY isn't stored in the instruction, because it's always the
1527 // opposite of bit 0 of DstX.
1529  unsigned Val) const {
1530  int VDstXInd =
1531  AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX);
1532  assert(VDstXInd != -1);
1533  assert(Inst.getOperand(VDstXInd).isReg());
1534  unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg());
1535  Val |= ~XDstReg & 1;
1537  return createRegOperand(getVgprClassId(Width), Val);
1538 }
1539 
1541  using namespace AMDGPU;
1542 
1543  switch (Val) {
1544  case 102: return createRegOperand(FLAT_SCR_LO);
1545  case 103: return createRegOperand(FLAT_SCR_HI);
1546  case 104: return createRegOperand(XNACK_MASK_LO);
1547  case 105: return createRegOperand(XNACK_MASK_HI);
1548  case 106: return createRegOperand(VCC_LO);
1549  case 107: return createRegOperand(VCC_HI);
1550  case 108: return createRegOperand(TBA_LO);
1551  case 109: return createRegOperand(TBA_HI);
1552  case 110: return createRegOperand(TMA_LO);
1553  case 111: return createRegOperand(TMA_HI);
1554  case 124:
1555  return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0);
1556  case 125:
1557  return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL);
1558  case 126: return createRegOperand(EXEC_LO);
1559  case 127: return createRegOperand(EXEC_HI);
1560  case 235: return createRegOperand(SRC_SHARED_BASE);
1561  case 236: return createRegOperand(SRC_SHARED_LIMIT);
1562  case 237: return createRegOperand(SRC_PRIVATE_BASE);
1563  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1564  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1565  case 251: return createRegOperand(SRC_VCCZ);
1566  case 252: return createRegOperand(SRC_EXECZ);
1567  case 253: return createRegOperand(SRC_SCC);
1568  case 254: return createRegOperand(LDS_DIRECT);
1569  default: break;
1570  }
1571  return errOperand(Val, "unknown operand encoding " + Twine(Val));
1572 }
1573 
1575  using namespace AMDGPU;
1576 
1577  switch (Val) {
1578  case 102: return createRegOperand(FLAT_SCR);
1579  case 104: return createRegOperand(XNACK_MASK);
1580  case 106: return createRegOperand(VCC);
1581  case 108: return createRegOperand(TBA);
1582  case 110: return createRegOperand(TMA);
1583  case 124:
1584  if (isGFX11Plus())
1585  return createRegOperand(SGPR_NULL);
1586  break;
1587  case 125:
1588  if (!isGFX11Plus())
1589  return createRegOperand(SGPR_NULL);
1590  break;
1591  case 126: return createRegOperand(EXEC);
1592  case 235: return createRegOperand(SRC_SHARED_BASE);
1593  case 236: return createRegOperand(SRC_SHARED_LIMIT);
1594  case 237: return createRegOperand(SRC_PRIVATE_BASE);
1595  case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1596  case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1597  case 251: return createRegOperand(SRC_VCCZ);
1598  case 252: return createRegOperand(SRC_EXECZ);
1599  case 253: return createRegOperand(SRC_SCC);
1600  default: break;
1601  }
1602  return errOperand(Val, "unknown operand encoding " + Twine(Val));
1603 }
1604 
1606  const unsigned Val) const {
1607  using namespace AMDGPU::SDWA;
1608  using namespace AMDGPU::EncValues;
1609 
1610  if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1611  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1612  // XXX: cast to int is needed to avoid stupid warning:
1613  // compare with unsigned is always true
1614  if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1618  }
1619  if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1624  }
1625  if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1629  }
1630 
1631  const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1632 
1633  if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1634  return decodeIntImmed(SVal);
1635 
1636  if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1637  return decodeFPImmed(Width, SVal);
1638 
1639  return decodeSpecialReg32(SVal);
1640  } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1641  return createRegOperand(getVgprClassId(Width), Val);
1642  }
1643  llvm_unreachable("unsupported target");
1644 }
1645 
1647  return decodeSDWASrc(OPW16, Val);
1648 }
1649 
1651  return decodeSDWASrc(OPW32, Val);
1652 }
1653 
1655  using namespace AMDGPU::SDWA;
1656 
1657  assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1658  STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1659  "SDWAVopcDst should be present only on GFX9+");
1660 
1661  bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1662 
1665 
1666  int TTmpIdx = getTTmpIdx(Val);
1667  if (TTmpIdx >= 0) {
1668  auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1669  return createSRegOperand(TTmpClsId, TTmpIdx);
1670  } else if (Val > SGPR_MAX) {
1671  return IsWave64 ? decodeSpecialReg64(Val)
1672  : decodeSpecialReg32(Val);
1673  } else {
1674  return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1675  }
1676  } else {
1677  return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1678  }
1679 }
1680 
1682  return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1684 }
1685 
1687  return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1688 }
1689 
1691 
1693  return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts];
1694 }
1695 
1697 
1699 
1701  return AMDGPU::isGFX10Plus(STI);
1702 }
1703 
1705  return STI.getFeatureBits()[AMDGPU::FeatureGFX11];
1706 }
1707 
1709  return AMDGPU::isGFX11Plus(STI);
1710 }
1711 
1712 
1714  return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
1715 }
1716 
1717 //===----------------------------------------------------------------------===//
1718 // AMDGPU specific symbol handling
1719 //===----------------------------------------------------------------------===//
1720 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1721  do { \
1722  KdStream << Indent << DIRECTIVE " " \
1723  << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1724  } while (0)
1725 
1726 // NOLINTNEXTLINE(readability-identifier-naming)
1728  uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1729  using namespace amdhsa;
1730  StringRef Indent = "\t";
1731 
1732  // We cannot accurately backward compute #VGPRs used from
1733  // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same
1734  // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we
1735  // simply calculate the inverse of what the assembler does.
1736 
1737  uint32_t GranulatedWorkitemVGPRCount =
1738  (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >>
1739  COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT;
1740 
1741  uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) *
1743 
1744  KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n';
1745 
1746  // We cannot backward compute values used to calculate
1747  // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following
1748  // directives can't be computed:
1749  // .amdhsa_reserve_vcc
1750  // .amdhsa_reserve_flat_scratch
1751  // .amdhsa_reserve_xnack_mask
1752  // They take their respective default values if not specified in the assembly.
1753  //
1754  // GRANULATED_WAVEFRONT_SGPR_COUNT
1755  // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK)
1756  //
1757  // We compute the inverse as though all directives apart from NEXT_FREE_SGPR
1758  // are set to 0. So while disassembling we consider that:
1759  //
1760  // GRANULATED_WAVEFRONT_SGPR_COUNT
1761  // = f(NEXT_FREE_SGPR + 0 + 0 + 0)
1762  //
1763  // The disassembler cannot recover the original values of those 3 directives.
1764 
1765  uint32_t GranulatedWavefrontSGPRCount =
1766  (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
1767  COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
1768 
1769  if (isGFX10Plus() && GranulatedWavefrontSGPRCount)
1770  return MCDisassembler::Fail;
1771 
1772  uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1774 
1775  KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n';
1777  KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n';
1778  KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n';
1779  KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n";
1780 
1781  if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1782  return MCDisassembler::Fail;
1783 
1784  PRINT_DIRECTIVE(".amdhsa_float_round_mode_32",
1785  COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1786  PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64",
1787  COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1788  PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32",
1789  COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1790  PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64",
1791  COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1792 
1793  if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1794  return MCDisassembler::Fail;
1795 
1796  PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1797 
1798  if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1799  return MCDisassembler::Fail;
1800 
1801  PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1802 
1803  if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1804  return MCDisassembler::Fail;
1805 
1806  if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1807  return MCDisassembler::Fail;
1808 
1809  PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1810 
1811  if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1812  return MCDisassembler::Fail;
1813 
1814  if (isGFX10Plus()) {
1815  PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
1816  COMPUTE_PGM_RSRC1_WGP_MODE);
1817  PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1818  PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1819  }
1820  return MCDisassembler::Success;
1821 }
1822 
1823 // NOLINTNEXTLINE(readability-identifier-naming)
1825  uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1826  using namespace amdhsa;
1827  StringRef Indent = "\t";
1829  PRINT_DIRECTIVE(".amdhsa_enable_private_segment",
1830  COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1831  else
1832  PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset",
1833  COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT);
1834  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x",
1835  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1836  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y",
1837  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1838  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z",
1839  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1840  PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info",
1841  COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1842  PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id",
1843  COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1844 
1845  if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1846  return MCDisassembler::Fail;
1847 
1848  if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1849  return MCDisassembler::Fail;
1850 
1851  if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1852  return MCDisassembler::Fail;
1853 
1855  ".amdhsa_exception_fp_ieee_invalid_op",
1856  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1857  PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src",
1858  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1860  ".amdhsa_exception_fp_ieee_div_zero",
1861  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1862  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow",
1863  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1864  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow",
1865  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1866  PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact",
1867  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1868  PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero",
1869  COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1870 
1871  if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1872  return MCDisassembler::Fail;
1873 
1874  return MCDisassembler::Success;
1875 }
1876 
1877 #undef PRINT_DIRECTIVE
1878 
1882  raw_string_ostream &KdStream) const {
1883 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \
1884  do { \
1885  KdStream << Indent << DIRECTIVE " " \
1886  << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \
1887  } while (0)
1888 
1889  uint16_t TwoByteBuffer = 0;
1890  uint32_t FourByteBuffer = 0;
1891 
1892  StringRef ReservedBytes;
1893  StringRef Indent = "\t";
1894 
1895  assert(Bytes.size() == 64);
1896  DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8);
1897 
1898  switch (Cursor.tell()) {
1900  FourByteBuffer = DE.getU32(Cursor);
1901  KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer
1902  << '\n';
1903  return MCDisassembler::Success;
1904 
1906  FourByteBuffer = DE.getU32(Cursor);
1907  KdStream << Indent << ".amdhsa_private_segment_fixed_size "
1908  << FourByteBuffer << '\n';
1909  return MCDisassembler::Success;
1910 
1912  FourByteBuffer = DE.getU32(Cursor);
1913  KdStream << Indent << ".amdhsa_kernarg_size "
1914  << FourByteBuffer << '\n';
1915  return MCDisassembler::Success;
1916 
1918  // 4 reserved bytes, must be 0.
1919  ReservedBytes = DE.getBytes(Cursor, 4);
1920  for (int I = 0; I < 4; ++I) {
1921  if (ReservedBytes[I] != 0) {
1922  return MCDisassembler::Fail;
1923  }
1924  }
1925  return MCDisassembler::Success;
1926 
1928  // KERNEL_CODE_ENTRY_BYTE_OFFSET
1929  // So far no directive controls this for Code Object V3, so simply skip for
1930  // disassembly.
1931  DE.skip(Cursor, 8);
1932  return MCDisassembler::Success;
1933 
1935  // 20 reserved bytes, must be 0.
1936  ReservedBytes = DE.getBytes(Cursor, 20);
1937  for (int I = 0; I < 20; ++I) {
1938  if (ReservedBytes[I] != 0) {
1939  return MCDisassembler::Fail;
1940  }
1941  }
1942  return MCDisassembler::Success;
1943 
1945  // COMPUTE_PGM_RSRC3
1946  // - Only set for GFX10, GFX6-9 have this to be 0.
1947  // - Currently no directives directly control this.
1948  FourByteBuffer = DE.getU32(Cursor);
1949  if (!isGFX10Plus() && FourByteBuffer) {
1950  return MCDisassembler::Fail;
1951  }
1952  return MCDisassembler::Success;
1953 
1955  FourByteBuffer = DE.getU32(Cursor);
1956  if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) ==
1958  return MCDisassembler::Fail;
1959  }
1960  return MCDisassembler::Success;
1961 
1963  FourByteBuffer = DE.getU32(Cursor);
1964  if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) ==
1966  return MCDisassembler::Fail;
1967  }
1968  return MCDisassembler::Success;
1969 
1971  using namespace amdhsa;
1972  TwoByteBuffer = DE.getU16(Cursor);
1973 
1975  PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer",
1976  KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
1977  PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr",
1978  KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
1979  PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr",
1980  KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
1981  PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr",
1982  KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
1983  PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id",
1984  KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
1986  PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init",
1987  KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
1988  PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size",
1989  KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
1990 
1991  if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
1992  return MCDisassembler::Fail;
1993 
1994  // Reserved for GFX9
1995  if (isGFX9() &&
1996  (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
1997  return MCDisassembler::Fail;
1998  } else if (isGFX10Plus()) {
1999  PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
2000  KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
2001  }
2002 
2003  if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
2004  return MCDisassembler::Fail;
2005 
2006  return MCDisassembler::Success;
2007 
2009  // 6 bytes from here are reserved, must be 0.
2010  ReservedBytes = DE.getBytes(Cursor, 6);
2011  for (int I = 0; I < 6; ++I) {
2012  if (ReservedBytes[I] != 0)
2013  return MCDisassembler::Fail;
2014  }
2015  return MCDisassembler::Success;
2016 
2017  default:
2018  llvm_unreachable("Unhandled index. Case statements cover everything.");
2019  return MCDisassembler::Fail;
2020  }
2021 #undef PRINT_DIRECTIVE
2022 }
2023 
2025  StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const {
2026  // CP microcode requires the kernel descriptor to be 64 aligned.
2027  if (Bytes.size() != 64 || KdAddress % 64 != 0)
2028  return MCDisassembler::Fail;
2029 
2030  std::string Kd;
2031  raw_string_ostream KdStream(Kd);
2032  KdStream << ".amdhsa_kernel " << KdName << '\n';
2033 
2035  while (C && C.tell() < Bytes.size()) {
2037  decodeKernelDescriptorDirective(C, Bytes, KdStream);
2038 
2039  cantFail(C.takeError());
2040 
2042  return MCDisassembler::Fail;
2043  }
2044  KdStream << ".end_amdhsa_kernel\n";
2045  outs() << KdStream.str();
2046  return MCDisassembler::Success;
2047 }
2048 
2051  ArrayRef<uint8_t> Bytes, uint64_t Address,
2052  raw_ostream &CStream) const {
2053  // Right now only kernel descriptor needs to be handled.
2054  // We ignore all other symbols for target specific handling.
2055  // TODO:
2056  // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code
2057  // Object V2 and V3 when symbols are marked protected.
2058 
2059  // amd_kernel_code_t for Code Object V2.
2060  if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) {
2061  Size = 256;
2062  return MCDisassembler::Fail;
2063  }
2064 
2065  // Code Object V3 kernel descriptors.
2066  StringRef Name = Symbol.Name;
2067  if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) {
2068  Size = 64; // Size = 64 regardless of success or failure.
2069  return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address);
2070  }
2071  return None;
2072 }
2073 
2074 //===----------------------------------------------------------------------===//
2075 // AMDGPUSymbolizer
2076 //===----------------------------------------------------------------------===//
2077 
2078 // Try to find symbol name for specified label
2080  MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value,
2081  uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/,
2082  uint64_t /*OpSize*/, uint64_t /*InstSize*/) {
2083 
2084  if (!IsBranch) {
2085  return false;
2086  }
2087 
2088  auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
2089  if (!Symbols)
2090  return false;
2091 
2092  auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) {
2093  return Val.Addr == static_cast<uint64_t>(Value) &&
2094  Val.Type == ELF::STT_NOTYPE;
2095  });
2096  if (Result != Symbols->end()) {
2097  auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
2098  const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
2099  Inst.addOperand(MCOperand::createExpr(Add));
2100  return true;
2101  }
2102  // Add to list of referenced addresses, so caller can synthesize a label.
2103  ReferencedAddresses.push_back(static_cast<uint64_t>(Value));
2104  return false;
2105 }
2106 
2108  int64_t Value,
2109  uint64_t Address) {
2110  llvm_unreachable("unimplemented");
2111 }
2112 
2113 //===----------------------------------------------------------------------===//
2114 // Initialization
2115 //===----------------------------------------------------------------------===//
2116 
2118  LLVMOpInfoCallback /*GetOpInfo*/,
2119  LLVMSymbolLookupCallback /*SymbolLookUp*/,
2120  void *DisInfo,
2121  MCContext *Ctx,
2122  std::unique_ptr<MCRelocationInfo> &&RelInfo) {
2123  return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
2124 }
2125 
2127  const MCSubtargetInfo &STI,
2128  MCContext &Ctx) {
2129  return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
2130 }
2131 
2137 }
llvm::AMDGPUDisassembler::decodeSDWASrc32
MCOperand decodeSDWASrc32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1650
i
i
Definition: README.txt:29
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MAX
@ INLINE_INTEGER_C_MAX
Definition: SIDefines.h:288
llvm::AMDGPUSymbolizer::tryAddingSymbolicOperand
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
Definition: AMDGPUDisassembler.cpp:2079
llvm::AMDGPU::getMCReg
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
Definition: AMDGPUBaseInfo.cpp:1909
llvm::AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC
MCOperand decodeOperand_SReg_64_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1211
llvm::SIInstrFlags::MIMG
@ MIMG
Definition: SIDefines.h:57
llvm::AMDGPUDisassembler::convertDPP8Inst
DecodeStatus convertDPP8Inst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:750
llvm::AMDGPU::getMIMGDimInfoByEncoding
const LLVM_READONLY MIMGDimInfo * getMIMGDimInfoByEncoding(uint8_t DimEnc)
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC
MCOperand decodeOperand_SReg_32_XM0_XEXEC(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1188
DECODE_SDWA
#define DECODE_SDWA(DecName)
Definition: AMDGPUDisassembler.cpp:380
llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
@ KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
Definition: AMDHSAKernelDescriptor.h:188
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
decodeOperand_VReg_512
static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:247
llvm::AMDGPUDisassembler::decodeOperand_SReg_256
MCOperand decodeOperand_SReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1219
llvm::AMDGPUDisassembler::convertVINTERPInst
DecodeStatus convertVINTERPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:716
llvm::AMDGPU::DPP::DPP8_FI_0
@ DPP8_FI_0
Definition: SIDefines.h:850
llvm::AMDGPU::hasVOPD
bool hasVOPD(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1834
llvm::AMDGPUDisassembler::decodeKernelDescriptorDirective
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
Definition: AMDGPUDisassembler.cpp:1880
llvm::MCOperand::createExpr
static MCOperand createExpr(const MCExpr *Val)
Definition: MCInst.h:162
llvm::AMDGPUDisassembler::decodeDstOp
MCOperand decodeDstOp(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1506
llvm::AMDGPUDisassembler::OpWidthTy
OpWidthTy
Definition: AMDGPUDisassembler.h:207
llvm::AMDGPU::isGFX11Plus
bool isGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1786
llvm::MCOperand::isReg
bool isReg() const
Definition: MCInst.h:61
MCInstrDesc.h
T
llvm::MCOperand::createImm
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
llvm::MCContext
Context object for machine code objects.
Definition: MCContext.h:76
llvm::SymbolInfoTy
Definition: MCDisassembler.h:33
llvm::MCContext::getRegisterInfo
const MCRegisterInfo * getRegisterInfo() const
Definition: MCContext.h:448
llvm::AMDGPUDisassembler::decodeFPImmed
static MCOperand decodeFPImmed(OpWidthTy Width, unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1342
llvm::AMDGPUDisassembler::isVI
bool isVI() const
Definition: AMDGPUDisassembler.cpp:1686
llvm::MCRegisterInfo::getMatchingSuperReg
MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg.
Definition: MCRegisterInfo.cpp:24
llvm::raw_string_ostream
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:632
decodeOperand_VS_16
static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:177
llvm::AMDGPUDisassembler::getTtmpClassId
unsigned getTtmpClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1428
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::AMDGPUDisassembler::isGFX90A
bool isGFX90A() const
Definition: AMDGPUDisassembler.cpp:1692
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Definition: AMDGPUDisassembler.cpp:1727
llvm::AMDGPUDisassembler::isGFX9
bool isGFX9() const
Definition: AMDGPUDisassembler.cpp:1690
llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET
@ KERNEL_CODE_PROPERTIES_OFFSET
Definition: AMDHSAKernelDescriptor.h:193
llvm::AMDGPUDisassembler::decodeOperand_VS_128
MCOperand decodeOperand_VS_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1080
llvm::AMDGPU::MIMGDimInfo
Definition: AMDGPUBaseInfo.h:324
decodeOperandVOPDDstY
static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, uint64_t Addr, const void *Decoder)
Definition: AMDGPUDisassembler.cpp:291
decodeOperand_f16kimm
static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:268
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::AMDGPU::DPP
Definition: SIDefines.h:798
llvm::AMDGPU::DPP::DPP8_FI_1
@ DPP8_FI_1
Definition: SIDefines.h:851
llvm::AMDGPUSymbolizer
Definition: AMDGPUDisassembler.h:267
llvm::AMDGPUDisassembler::convertMIMGInst
DecodeStatus convertMIMGInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:776
DecodeAVLdSt_32RegisterClass
static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:346
decodeBoolReg
static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:104
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
decodeOperand_VSrc16
static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:156
llvm::SISrcMods::OP_SEL_0
@ OP_SEL_0
Definition: SIDefines.h:223
llvm::SIInstrFlags::VOPC
@ VOPC
Definition: SIDefines.h:42
llvm::AMDGPU::VOP3PEncoding::OpSel
OpSel
Definition: SIDefines.h:888
llvm::AMDGPUDisassembler::decodeOperand_AReg_128
MCOperand decodeOperand_AReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1117
llvm::MCRegisterInfo::getEncodingValue
uint16_t getEncodingValue(MCRegister RegNo) const
Returns the encoding for RegNo.
Definition: MCRegisterInfo.h:553
DECODE_OPERAND_REG
#define DECODE_OPERAND_REG(RegClass)
Definition: AMDGPUDisassembler.cpp:118
llvm::MCDisassembler::SoftFail
@ SoftFail
Definition: MCDisassembler.h:111
llvm::AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI
MCOperand decodeOperand_SReg_32_XEXEC_HI(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1194
llvm::FloatToBits
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
Definition: MathExtras.h:690
llvm::AMDGPUSymbolizer::tryAddingPcLoadReferenceComment
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Definition: AMDGPUDisassembler.cpp:2107
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1774
llvm::TargetRegistry::RegisterMCDisassembler
static void RegisterMCDisassembler(Target &T, Target::MCDisassemblerCtorTy Fn)
RegisterMCDisassembler - Register a MCDisassembler implementation for the given target.
Definition: TargetRegistry.h:951
llvm::Optional
Definition: APInt.h:33
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_SI
@ SRC_SGPR_MAX_SI
Definition: SIDefines.h:790
llvm::AMDGPUDisassembler::hasArchitectedFlatScratch
bool hasArchitectedFlatScratch() const
Definition: AMDGPUDisassembler.cpp:1713
llvm::AMDGPU::EncValues::VGPR_MAX
@ VGPR_MAX
Definition: SIDefines.h:293
decodeOperand_AReg_256
static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:205
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MIN
@ TTMP_GFX9PLUS_MIN
Definition: SIDefines.h:284
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::AMDGPU::SDWA::VOPC_DST_SGPR_MASK
@ VOPC_DST_SGPR_MASK
Definition: SIDefines.h:785
llvm::AMDGPUDisassembler::decodeSDWAVopcDst
MCOperand decodeSDWAVopcDst(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1654
llvm::SPIRV::Dim
Dim
Definition: SPIRVBaseInfo.h:279
llvm::AMDGPU::getNamedOperandIdx
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
llvm::SISrcMods::OP_SEL_1
@ OP_SEL_1
Definition: SIDefines.h:224
MCDecoderOps.h
llvm::AMDGPUDisassembler::decodeOperand_AVDst_512
MCOperand decodeOperand_AVDst_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1151
llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH
bool BVH
Definition: AMDGPUBaseInfo.h:315
llvm::AMDGPUDisassembler::decodeBoolReg
MCOperand decodeBoolReg(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1681
llvm::MCRegisterInfo::getSubReg
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
Definition: MCRegisterInfo.cpp:32
llvm::AMDGPU::SDWA::SRC_VGPR_MAX
@ SRC_VGPR_MAX
Definition: SIDefines.h:788
llvm::DataExtractor::skip
void skip(Cursor &C, uint64_t Length) const
Advance the Cursor position by the given number of bytes.
Definition: DataExtractor.cpp:228
llvm::MCInst::getNumOperands
unsigned getNumOperands() const
Definition: MCInst.h:208
llvm::AMDGPUDisassembler
Definition: AMDGPUDisassembler.h:90
llvm::SISrcMods::NEG
@ NEG
Definition: SIDefines.h:219
llvm::ArrayRef::data
const T * data() const
Definition: ArrayRef.h:161
llvm::AMDGPUDisassembler::decodeSpecialReg64
MCOperand decodeSpecialReg64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1574
llvm::MCSymbolizer
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
AMDHSAKernelDescriptor.h
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_MIN
@ INLINE_INTEGER_C_MIN
Definition: SIDefines.h:286
llvm::AMDGPUDisassembler::OPW512
@ OPW512
Definition: AMDGPUDisassembler.h:214
llvm::AMDGPUDisassembler::decodeOperand_AV_32
MCOperand decodeOperand_AV_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1133
llvm::AMDGPUDisassembler::decodeOperand_VReg_96
MCOperand decodeOperand_VReg_96(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1161
llvm::AMDGPU::IsaInfo::getSGPREncodingGranule
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
Definition: AMDGPUBaseInfo.cpp:733
llvm::AMDGPUDisassembler::isGFX9Plus
bool isGFX9Plus() const
Definition: AMDGPUDisassembler.cpp:1696
llvm::AMDGPU::CPol::CPol
CPol
Definition: SIDefines.h:303
llvm::DataExtractor::getBytes
StringRef getBytes(uint64_t *OffsetPtr, uint64_t Length, Error *Err=nullptr) const
Extract a fixed number of bytes from the specified offset.
Definition: DataExtractor.cpp:180
llvm::MCRegisterInfo::getRegClass
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
Definition: MCRegisterInfo.h:543
llvm::AMDGPUDisassembler::OPW_LAST_
@ OPW_LAST_
Definition: AMDGPUDisassembler.h:219
ELF.h
llvm::outs
raw_fd_ostream & outs()
This returns a reference to a raw_fd_ostream for standard output.
Definition: raw_ostream.cpp:885
llvm::SymbolInfoTy::Addr
uint64_t Addr
Definition: MCDisassembler.h:34
LLVMSymbolLookupCallback
const typedef char *(* LLVMSymbolLookupCallback)(void *DisInfo, uint64_t ReferenceValue, uint64_t *ReferenceType, uint64_t ReferencePC, const char **ReferenceName)
The type for the symbol lookup function.
Definition: DisassemblerTypes.h:118
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::AMDGPUDisassembler::getRegClassName
const char * getRegClassName(unsigned RegClassID) const
Definition: AMDGPUDisassembler.cpp:1002
llvm::AMDGPU::MIMGBaseOpcodeInfo
Definition: AMDGPUBaseInfo.h:300
decodeOperand_AReg_128
static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:198
llvm::AMDGPUDisassembler::OPWV232
@ OPWV232
Definition: AMDGPUDisassembler.h:218
llvm::AMDGPUDisassembler::createSRegOperand
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1033
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::AMDGPUDisassembler::convertVOPCDPPInst
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:962
AMDGPUTargetInfo.h
llvm::AMDGPUDisassembler::decodeVOPDDstYOp
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1528
llvm::AMDGPUDisassembler::OPWV216
@ OPWV216
Definition: AMDGPUDisassembler.h:217
MCContext.h
llvm::AMDGPU::EncValues::TTMP_GFX9PLUS_MAX
@ TTMP_GFX9PLUS_MAX
Definition: SIDefines.h:285
old
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n old
Definition: README.txt:123
llvm::AMDGPU::SDWA::SRC_TTMP_MAX
@ SRC_TTMP_MAX
Definition: SIDefines.h:793
llvm::AMDGPUDisassembler::decodeOperand_VReg_128
MCOperand decodeOperand_VReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1165
llvm::MCDisassembler::Success
@ Success
Definition: MCDisassembler.h:112
llvm::amdhsa::RESERVED2_OFFSET
@ RESERVED2_OFFSET
Definition: AMDHSAKernelDescriptor.h:194
llvm::AMDGPUDisassembler::decodeOperand_AV_64
MCOperand decodeOperand_AV_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1137
llvm::DoubleToBits
uint64_t DoubleToBits(double Double)
This function takes a double and returns the bit equivalent 64-bit integer.
Definition: MathExtras.h:680
eatBytes
static T eatBytes(ArrayRef< uint8_t > &Bytes)
Definition: AMDGPUDisassembler.cpp:393
llvm::AMDGPUDisassembler::OPW_FIRST_
@ OPW_FIRST_
Definition: AMDGPUDisassembler.h:220
llvm::MCDisassembler::CommentStream
raw_ostream * CommentStream
Definition: MCDisassembler.h:200
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::AMDGPUDisassembler::OPW16
@ OPW16
Definition: AMDGPUDisassembler.h:216
llvm::AMDGPUDisassembler::decodeOperand_AReg_256
MCOperand decodeOperand_AReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1121
MCSubtargetInfo.h
decodeOperand_VReg_256
static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:240
llvm::MCSubtargetInfo::getFeatureBits
const FeatureBitset & getFeatureBits() const
Definition: MCSubtargetInfo.h:112
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::M0
unsigned M0(unsigned Val)
Definition: VE.h:369
llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET
@ COMPUTE_PGM_RSRC1_OFFSET
Definition: AMDHSAKernelDescriptor.h:191
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::AMDGPUDisassembler::isGFX11
bool isGFX11() const
Definition: AMDGPUDisassembler.cpp:1704
llvm::SIInstrFlags::VOP3P
@ VOP3P
Definition: SIDefines.h:46
llvm::SectionSymbolsTy
std::vector< SymbolInfoTy > SectionSymbolsTy
Definition: MCDisassembler.h:75
decodeOperand_AReg_512
static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:212
llvm::SIInstrFlags::SMRD
@ SMRD
Definition: SIDefines.h:56
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::AMDGPUDisassembler::decodeSDWASrc
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1605
llvm::AMDGPUDisassembler::getInstruction
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
Definition: AMDGPUDisassembler.cpp:424
llvm::AMDGPUDisassembler::decodeOperand_AReg_512
MCOperand decodeOperand_AReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1125
llvm::AMDGPUDisassembler::decodeOperand_VSrcV216
MCOperand decodeOperand_VSrcV216(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1088
llvm::AMDGPU::getMIMGOpcode
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
Definition: AMDGPUBaseInfo.cpp:199
llvm::ArrayRef::slice
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:194
llvm::MCDisassembler::DecodeStatus
DecodeStatus
Ternary decode status.
Definition: MCDisassembler.h:109
llvm::None
const NoneType None
Definition: None.h:24
llvm::MCDisassembler::STI
const MCSubtargetInfo & STI
Definition: MCDisassembler.h:179
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1778
llvm::AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
Definition: AMDGPUDisassembler.cpp:1824
llvm::MCInst::addOperand
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
llvm::AMDGPU::hasPackedD16
bool hasPackedD16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1737
llvm::AMDGPUDisassembler::onSymbolStart
Optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
Definition: AMDGPUDisassembler.cpp:2050
llvm::AMDGPUDisassembler::decodeOperand_VSrc16
MCOperand decodeOperand_VSrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1084
llvm::AMDGPUDisassembler::decodeOperand_VS_32
MCOperand decodeOperand_VS_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1072
llvm::SIInstrFlags::EXP
@ EXP
Definition: SIDefines.h:58
llvm::AMDGPUDisassembler::decodeOperand_VReg_1024
MCOperand decodeOperand_VReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1177
llvm::AMDGPUDisassembler::getSgprClassId
unsigned getSgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1408
llvm::AMDGPUDisassembler::OPW256
@ OPW256
Definition: AMDGPUDisassembler.h:213
llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:160
llvm::AMDGPUDisassembler::getAgprClassId
unsigned getAgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1386
llvm::AMDGPU::EncValues::VGPR_MIN
@ VGPR_MIN
Definition: SIDefines.h:292
llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
@ PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:185
llvm::AMDGPUDisassembler::isGFX10Plus
bool isGFX10Plus() const
Definition: AMDGPUDisassembler.cpp:1700
llvm::AMDGPUDisassembler::decodeOperand_SReg_128
MCOperand decodeOperand_SReg_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1215
llvm::countPopulation
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Definition: MathExtras.h:567
decodeSMEMOffset
static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:92
llvm::AMDGPUDisassembler::isGFX10
bool isGFX10() const
Definition: AMDGPUDisassembler.cpp:1698
llvm::AMDGPUDisassembler::decodeOperand_VRegOrLds_32
MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1105
decodeOperand_VS_16_Deferred
static DecodeStatus decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:276
llvm::AMDGPU::hasG16
bool hasG16(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1733
AMDGPUMCTargetDesc.h
llvm::AMDGPU::SDWA::SRC_VGPR_MIN
@ SRC_VGPR_MIN
Definition: SIDefines.h:787
llvm::AMDGPU::CPol::GLC
@ GLC
Definition: SIDefines.h:304
uint64_t
SGPR_MAX
#define SGPR_MAX
Definition: AMDGPUDisassembler.cpp:41
llvm::ELF::STT_NOTYPE
@ STT_NOTYPE
Definition: ELF.h:1203
llvm::AMDGPU::isVOPC64DPP
bool isVOPC64DPP(unsigned Opc)
Definition: AMDGPUBaseInfo.cpp:403
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
Addr
uint64_t Addr
Definition: ELFObjHandler.cpp:78
llvm::MCOperand::isValid
bool isValid() const
Definition: MCInst.h:60
eat12Bytes
static DecoderUInt128 eat12Bytes(ArrayRef< uint8_t > &Bytes)
Definition: AMDGPUDisassembler.cpp:400
llvm::AMDGPU::isGFX9
bool isGFX9(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1754
llvm::AMDGPUDisassembler::convertFMAanyK
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
Definition: AMDGPUDisassembler.cpp:982
decodeOperand_SReg_32
static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:373
llvm::AMDGPUDisassembler::OPW64
@ OPW64
Definition: AMDGPUDisassembler.h:209
llvm::AMDGPUDisassembler::errOperand
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
Definition: AMDGPUDisassembler.cpp:1008
DecodeAVLdSt_64RegisterClass
static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:353
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::MCDisassembler
Superclass for all disassemblers.
Definition: MCDisassembler.h:85
llvm::MCOperandInfo::OperandType
uint8_t OperandType
Information about the type of the operand.
Definition: MCInstrDesc.h:96
decodeOperand_VReg_1024
static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:254
llvm::AMDGPUDisassembler::decodeOperand_SRegOrLds_32
MCOperand decodeOperand_SRegOrLds_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1200
llvm::AMDGPUDisassembler::decodeOperand_VReg_64
MCOperand decodeOperand_VReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1157
I
#define I(x, y, z)
Definition: MD5.cpp:58
decodeOperand_VS_32_Deferred
static DecodeStatus decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:284
llvm::AMDGPUDisassembler::decodeOperand_VReg_256
MCOperand decodeOperand_VReg_256(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1169
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN
@ INLINE_FLOATING_C_MIN
Definition: SIDefines.h:289
MCRegisterInfo.h
llvm::AMDGPUDisassembler::decodeLiteralConstant
MCOperand decodeLiteralConstant() const
Definition: AMDGPUDisassembler.cpp:1242
llvm::AMDGPU::EncValues::TTMP_VI_MAX
@ TTMP_VI_MAX
Definition: SIDefines.h:283
llvm::AMDGPUDisassembler::convertEXPInst
DecodeStatus convertEXPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:706
llvm::AMDGPU::EncValues::LITERAL_CONST
@ LITERAL_CONST
Definition: SIDefines.h:291
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
addOperand
static MCDisassembler::DecodeStatus addOperand(MCInst &Inst, const MCOperand &Opnd)
Definition: AMDGPUDisassembler.cpp:59
llvm::AMDGPUDisassembler::decodeOperand_AReg_1024
MCOperand decodeOperand_AReg_1024(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1129
llvm::AMDGPU::getAddrSizeMIMGOp
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
Definition: AMDGPUBaseInfo.cpp:219
llvm::AMDGPUDisassembler::decodeSrcOp
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false) const
Definition: AMDGPUDisassembler.cpp:1455
llvm::getTheGCNTarget
Target & getTheGCNTarget()
The target for GCN GPUs.
Definition: AMDGPUTargetInfo.cpp:25
llvm::AMDGPUDisassembler::OPW128
@ OPW128
Definition: AMDGPUDisassembler.h:211
llvm::DataExtractor::Cursor::tell
uint64_t tell() const
Return the current position of this Cursor.
Definition: DataExtractor.h:71
llvm::AMDGPUDisassembler::decodeOperand_VS_64
MCOperand decodeOperand_VS_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1076
llvm::MCInstrDesc::OpInfo
const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::DataExtractor::Cursor
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET
@ COMPUTE_PGM_RSRC2_OFFSET
Definition: AMDHSAKernelDescriptor.h:192
llvm::AMDGPU::getMIMGInfo
const LLVM_READONLY MIMGInfo * getMIMGInfo(unsigned Opc)
llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:161
llvm::AMDGPUDisassembler::convertVOP3PDPPInst
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:914
llvm::AMDGPUDisassembler::decodeOperand_VReg_512
MCOperand decodeOperand_VReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1173
decodeOperand_VReg_64
static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:226
createAMDGPUDisassembler
static MCDisassembler * createAMDGPUDisassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx)
Definition: AMDGPUDisassembler.cpp:2126
Status
Definition: SIModeRegister.cpp:29
llvm::AMDGPU::SDWA::SRC_SGPR_MIN
@ SRC_SGPR_MIN
Definition: SIDefines.h:789
llvm::SIInstrFlags::DS
@ DS
Definition: SIDefines.h:60
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::AMDGPUDisassembler::decodeIntImmed
static MCOperand decodeIntImmed(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1257
llvm::DecoderUInt128
Definition: AMDGPUDisassembler.h:34
llvm::AMDGPUDisassembler::decodeKernelDescriptor
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
Definition: AMDGPUDisassembler.cpp:2024
llvm::AMDGPU::getMIMGBaseOpcodeInfo
const LLVM_READONLY MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
llvm::DataExtractor::getU32
uint32_t getU32(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint32_t value from *offset_ptr.
Definition: DataExtractor.cpp:107
llvm::AMDGPUDisassembler::getVgprClassId
unsigned getVgprClassId(const OpWidthTy Width) const
Definition: AMDGPUDisassembler.cpp:1365
llvm::SISrcMods::NEG_HI
@ NEG_HI
Definition: SIDefines.h:222
insertNamedMCOperand
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, uint16_t NameIdx)
Definition: AMDGPUDisassembler.cpp:66
llvm::AMDGPU::EncValues::SGPR_MIN
@ SGPR_MIN
Definition: SIDefines.h:279
llvm::AMDGPUDisassembler::isGFX11Plus
bool isGFX11Plus() const
Definition: AMDGPUDisassembler.cpp:1708
llvm::ArrayRef< uint8_t >
llvm::min
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
MCAsmInfo.h
decodeOperand_VS_32
static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:184
llvm::AMDGPUDisassembler::decodeOperand_AVDst_128
MCOperand decodeOperand_AVDst_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1145
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
decodeOperand_VSrcV216
static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:163
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::MCOperand::createReg
static MCOperand createReg(unsigned Reg)
Definition: MCInst.h:134
llvm::AMDGPU::IsaInfo::getVGPREncodingGranule
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, Optional< bool > EnableWavefrontSize32)
Definition: AMDGPUBaseInfo.cpp:842
llvm::cantFail
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
Definition: Error.h:745
decodeSoppBrTarget
static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:77
uint32_t
llvm::SIInstrFlags::FLAT
@ FLAT
Definition: SIDefines.h:59
llvm::SIInstrFlags::Gather4
@ Gather4
Definition: SIDefines.h:79
decodeOperand_f32kimm
static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:261
getInlineImmVal16
static int64_t getInlineImmVal16(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1317
decodeOperand_AReg_64
static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:191
llvm::MCRegisterInfo
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Definition: MCRegisterInfo.h:135
llvm::MCDisassembler::Fail
@ Fail
Definition: MCDisassembler.h:110
llvm::MCDisassembler::getContext
MCContext & getContext() const
Definition: MCDisassembler.h:194
llvm::AMDGPU::EncValues::INLINE_INTEGER_C_POSITIVE_MAX
@ INLINE_INTEGER_C_POSITIVE_MAX
Definition: SIDefines.h:287
llvm::SIInstrFlags::MTBUF
@ MTBUF
Definition: SIDefines.h:55
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1770
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::AMDGPU::SDWA::SRC_SGPR_MAX_GFX10
@ SRC_SGPR_MAX_GFX10
Definition: SIDefines.h:791
llvm::find_if
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1644
decodeOperand_AVLdSt_Any
static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, AMDGPUDisassembler::OpWidthTy Opw, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:311
decodeOperand_VSrcV232
static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:170
llvm::AMDGPU::EncValues::TTMP_VI_MIN
@ TTMP_VI_MIN
Definition: SIDefines.h:282
llvm::SIInstrFlags::IsAtomicRet
@ IsAtomicRet
Definition: SIDefines.h:129
llvm::AMDGPUDisassembler::decodeSDWASrc16
MCOperand decodeSDWASrc16(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1646
llvm::Twine
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:83
llvm::amdhsa::KERNARG_SIZE_OFFSET
@ KERNARG_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:186
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
getInlineImmVal64
static int64_t getInlineImmVal64(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1292
llvm::GraphProgram::Name
Name
Definition: GraphWriter.h:50
uint16_t
SDWA
@ SDWA
Definition: SIInstrInfo.cpp:7854
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
SIDefines.h
llvm::amdhsa::RESERVED1_OFFSET
@ RESERVED1_OFFSET
Definition: AMDHSAKernelDescriptor.h:189
llvm::ELF::STT_OBJECT
@ STT_OBJECT
Definition: ELF.h:1204
llvm::AMDGPUDisassembler::decodeOperand_SReg_64
MCOperand decodeOperand_SReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1207
llvm::misexpect::clamp
uint32_t clamp(uint64_t value, uint32_t low, uint32_t hi)
Definition: MisExpect.cpp:150
llvm::AMDGPUDisassembler::decodeOperand_AGPR_32
MCOperand decodeOperand_AGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1109
llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
Definition: AMDGPUDisassembler.cpp:1229
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET
@ COMPUTE_PGM_RSRC3_OFFSET
Definition: AMDHSAKernelDescriptor.h:190
isValidDPP8
static bool isValidDPP8(const MCInst &MI)
Definition: AMDGPUDisassembler.cpp:414
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::AMDGPU::MIMGInfo
Definition: AMDGPUBaseInfo.h:400
llvm::MCSymbolRefExpr::create
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:386
DecodeAVLdSt_96RegisterClass
static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:360
llvm::ELF::STT_AMDGPU_HSA_KERNEL
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1217
llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX
@ INLINE_FLOATING_C_MAX
Definition: SIDefines.h:290
llvm::AMDGPUDisassembler::convertSDWAInst
DecodeStatus convertSDWAInst(MCInst &MI) const
Definition: AMDGPUDisassembler.cpp:728
llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET
@ GROUP_SEGMENT_FIXED_SIZE_OFFSET
Definition: AMDHSAKernelDescriptor.h:184
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:439
llvm::APInt::sext
APInt sext(unsigned width) const
Sign extend to a new width.
Definition: APInt.cpp:946
llvm::ARMBuildAttrs::Symbol
@ Symbol
Definition: ARMBuildAttributes.h:83
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::DataExtractor
Definition: DataExtractor.h:41
llvm::AMDGPU::SDWA::VOPC_DST_VCC_MASK
@ VOPC_DST_VCC_MASK
Definition: SIDefines.h:784
DisassemblerTypes.h
getInlineImmVal32
static int64_t getInlineImmVal32(unsigned Imm)
Definition: AMDGPUDisassembler.cpp:1267
AMDGPUDisassembler.h
llvm::AMDGPUDisassembler::OPW96
@ OPW96
Definition: AMDGPUDisassembler.h:210
llvm::AMDGPUDisassembler::decodeOperand_VSrcV232
MCOperand decodeOperand_VSrcV232(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1092
IsAGPROperand
static bool IsAGPROperand(const MCInst &Inst, int OpIdx, const MCRegisterInfo *MRI)
Definition: AMDGPUDisassembler.cpp:297
llvm::MCInst::getOperand
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
llvm::AMDGPUDisassembler::createRegOperand
MCOperand createRegOperand(unsigned int RegId) const
Definition: AMDGPUDisassembler.cpp:1018
llvm::AMDGPUDisassembler::AMDGPUDisassembler
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, MCInstrInfo const *MCII)
Definition: AMDGPUDisassembler.cpp:47
llvm::ArrayRef::size
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:164
decodeOperand_AReg_1024
static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:219
shift
http eax xorl edx cl sete al setne dl sall eax sall edx But that requires good bit subreg support this might be better It s an extra shift
Definition: README.txt:30
llvm::SymbolInfoTy::Type
uint8_t Type
Definition: MCDisassembler.h:37
llvm::AMDGPUDisassembler::decodeOperand_SReg_32
MCOperand decodeOperand_SReg_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1181
llvm::AMDGPUDisassembler::getTTmpIdx
int getTTmpIdx(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1446
llvm::AMDGPUDisassembler::OPW160
@ OPW160
Definition: AMDGPUDisassembler.h:212
llvm::AMDGPUDisassembler::decodeOperand_SReg_512
MCOperand decodeOperand_SReg_512(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1223
llvm::TargetRegistry::RegisterMCSymbolizer
static void RegisterMCSymbolizer(Target &T, Target::MCSymbolizerCtorTy Fn)
RegisterMCSymbolizer - Register an MCSymbolizer implementation for the given target.
Definition: TargetRegistry.h:1049
PRINT_DIRECTIVE
#define PRINT_DIRECTIVE(DIRECTIVE, MASK)
Definition: AMDGPUDisassembler.cpp:1720
llvm::MCOperand
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
llvm::AMDGPU::SDWA::SRC_TTMP_MIN
@ SRC_TTMP_MIN
Definition: SIDefines.h:792
llvm::MCOI::TIED_TO
@ TIED_TO
Definition: MCInstrDesc.h:35
llvm::AMDGPUDisassembler::decodeOperand_VGPR_32
MCOperand decodeOperand_VGPR_32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1096
decodeOperand_VReg_128
static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:233
createAMDGPUSymbolizer
static MCSymbolizer * createAMDGPUSymbolizer(const Triple &, LLVMOpInfoCallback, LLVMSymbolLookupCallback, void *DisInfo, MCContext *Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo)
Definition: AMDGPUDisassembler.cpp:2117
llvm::AMDGPUDisassembler::tryDecodeInst
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address) const
Definition: AMDGPUDisassembler.h:117
llvm::SIInstrFlags::MUBUF
@ MUBUF
Definition: SIDefines.h:54
llvm::AMDGPU::EncValues::IS_VGPR
@ IS_VGPR
Definition: SIDefines.h:294
TargetRegistry.h
llvm::raw_string_ostream::str
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:650
MCExpr.h
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
llvm::AMDGPUDisassembler::decodeOperand_AReg_64
MCOperand decodeOperand_AReg_64(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1113
llvm::MCInstrDesc::getNumOperands
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:230
LLVMInitializeAMDGPUDisassembler
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler()
Definition: AMDGPUDisassembler.cpp:2132
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
SIRegisterInfo.h
DecodeAVLdSt_128RegisterClass
static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, const MCDisassembler *Decoder)
Definition: AMDGPUDisassembler.cpp:367
llvm::AMDGPUDisassembler::OPW32
@ OPW32
Definition: AMDGPUDisassembler.h:208
llvm::AMDGPUDisassembler::OPW1024
@ OPW1024
Definition: AMDGPUDisassembler.h:215
llvm::AMDGPUDisassembler::decodeOperand_AV_128
MCOperand decodeOperand_AV_128(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1141
llvm::amdhsa::RESERVED0_OFFSET
@ RESERVED0_OFFSET
Definition: AMDHSAKernelDescriptor.h:187
llvm::AMDGPUDisassembler::decodeSpecialReg32
MCOperand decodeSpecialReg32(unsigned Val) const
Definition: AMDGPUDisassembler.cpp:1540
AMDGPUBaseInfo.h
llvm::DataExtractor::getU16
uint16_t getU16(uint64_t *offset_ptr, Error *Err=nullptr) const
Extract a uint16_t value from *offset_ptr.
Definition: DataExtractor.cpp:92
llvm::MCOperand::getReg
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:69
LLVMOpInfoCallback
int(* LLVMOpInfoCallback)(void *DisInfo, uint64_t PC, uint64_t Offset, uint64_t OpSize, uint64_t InstSize, int TagType, void *TagBuf)
The type for the operand information call back function.
Definition: DisassemblerTypes.h:48
llvm::SIInstrFlags::VINTERP
@ VINTERP
Definition: SIDefines.h:70