22#ifndef LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
23#define LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
30#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE*)0)->MEMBER)
35#ifndef AMDHSA_BITS_ENUM_ENTRY
36#define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) \
37 NAME ## _SHIFT = (SHIFT), \
38 NAME ## _WIDTH = (WIDTH), \
39 NAME = (((1 << (WIDTH)) - 1) << (SHIFT))
43#ifndef AMDHSA_BITS_GET
44#define AMDHSA_BITS_GET(SRC, MSK) ((SRC & MSK) >> MSK ## _SHIFT)
48#ifndef AMDHSA_BITS_SET
49#define AMDHSA_BITS_SET(DST, MSK, VAL) \
51 DST |= ((VAL << MSK ## _SHIFT) & MSK)
83#define COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) \
84 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH)
86#define COMPUTE_PGM_RSRC1_GFX6_GFX8(NAME, SHIFT, WIDTH) \
87 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX8_ ## NAME, SHIFT, WIDTH)
89#define COMPUTE_PGM_RSRC1_GFX6_GFX9(NAME, SHIFT, WIDTH) \
90 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX6_GFX9_ ## NAME, SHIFT, WIDTH)
92#define COMPUTE_PGM_RSRC1_GFX9_PLUS(NAME, SHIFT, WIDTH) \
93 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX9_PLUS_ ## NAME, SHIFT, WIDTH)
95#define COMPUTE_PGM_RSRC1_GFX10_PLUS(NAME, SHIFT, WIDTH) \
96 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_GFX10_PLUS_ ## NAME, SHIFT, WIDTH)
119#undef COMPUTE_PGM_RSRC1
122#define COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) \
123 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH)
145#undef COMPUTE_PGM_RSRC2
149#define COMPUTE_PGM_RSRC3_GFX90A(NAME, SHIFT, WIDTH) \
150 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX90A_ ## NAME, SHIFT, WIDTH)
157#undef COMPUTE_PGM_RSRC3_GFX90A
162#define COMPUTE_PGM_RSRC3_GFX10(NAME, SHIFT, WIDTH) \
163 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_ ## NAME, SHIFT, WIDTH)
165#define COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH) \
166 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_PLUS_ ## NAME, SHIFT, WIDTH)
168#define COMPUTE_PGM_RSRC3_GFX11_PLUS(NAME, SHIFT, WIDTH) \
169 AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX11_PLUS_ ## NAME, SHIFT, WIDTH)
180#undef COMPUTE_PGM_RSRC3_GFX10_PLUS
183#define KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) \
184 AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH)
198#undef KERNEL_CODE_PROPERTY
201#define KERNARG_PRELOAD_SPEC(NAME, SHIFT, WIDTH) \
202 AMDHSA_BITS_ENUM_ENTRY(KERNARG_PRELOAD_SPEC_##NAME, SHIFT, WIDTH)
207#undef KERNARG_PRELOAD_SPEC
241 sizeof(kernel_descriptor_t) == 64,
242 "invalid size for kernel_descriptor_t");
243static_assert(
offsetof(kernel_descriptor_t, group_segment_fixed_size) ==
245 "invalid offset for group_segment_fixed_size");
246static_assert(
offsetof(kernel_descriptor_t, private_segment_fixed_size) ==
248 "invalid offset for private_segment_fixed_size");
249static_assert(
offsetof(kernel_descriptor_t, kernarg_size) ==
251 "invalid offset for kernarg_size");
253 "invalid offset for reserved0");
254static_assert(
offsetof(kernel_descriptor_t, kernel_code_entry_byte_offset) ==
256 "invalid offset for kernel_code_entry_byte_offset");
258 "invalid offset for reserved1");
259static_assert(
offsetof(kernel_descriptor_t, compute_pgm_rsrc3) ==
261 "invalid offset for compute_pgm_rsrc3");
262static_assert(
offsetof(kernel_descriptor_t, compute_pgm_rsrc1) ==
264 "invalid offset for compute_pgm_rsrc1");
265static_assert(
offsetof(kernel_descriptor_t, compute_pgm_rsrc2) ==
267 "invalid offset for compute_pgm_rsrc2");
268static_assert(
offsetof(kernel_descriptor_t, kernel_code_properties) ==
270 "invalid offset for kernel_code_properties");
271static_assert(
offsetof(kernel_descriptor_t, kernarg_preload) ==
273 "invalid offset for kernarg_preload");
275 "invalid offset for reserved3");
#define offsetof(TYPE, MEMBER)
@ COMPUTE_PGM_RSRC1_GFX10_PLUS
@ COMPUTE_PGM_RSRC1_GFX6_GFX8
@ COMPUTE_PGM_RSRC1_GFX6_GFX9
@ COMPUTE_PGM_RSRC1_GFX9_PLUS
@ KERNEL_CODE_PROPERTIES_OFFSET
@ GROUP_SEGMENT_FIXED_SIZE_OFFSET
@ COMPUTE_PGM_RSRC3_OFFSET
@ KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET
@ COMPUTE_PGM_RSRC1_OFFSET
@ COMPUTE_PGM_RSRC2_OFFSET
@ PRIVATE_SEGMENT_FIXED_SIZE_OFFSET
@ COMPUTE_PGM_RSRC3_GFX90A
@ COMPUTE_PGM_RSRC3_GFX10
@ COMPUTE_PGM_RSRC3_GFX10_PLUS
@ COMPUTE_PGM_RSRC3_GFX11_PLUS
@ FLOAT_DENORM_MODE_FLUSH_SRC
@ FLOAT_DENORM_MODE_FLUSH_DST
@ FLOAT_DENORM_MODE_FLUSH_SRC_DST
@ FLOAT_DENORM_MODE_FLUSH_NONE
@ FLOAT_ROUND_MODE_PLUS_INFINITY
@ FLOAT_ROUND_MODE_NEAR_EVEN
@ FLOAT_ROUND_MODE_MINUS_INFINITY
@ SYSTEM_VGPR_WORKITEM_ID_UNDEFINED
@ SYSTEM_VGPR_WORKITEM_ID_X
@ SYSTEM_VGPR_WORKITEM_ID_X_Y
@ SYSTEM_VGPR_WORKITEM_ID_X_Y_Z
This is an optimization pass for GlobalISel generic memory operations.
uint32_t group_segment_fixed_size
uint32_t compute_pgm_rsrc1
uint32_t private_segment_fixed_size
uint32_t compute_pgm_rsrc2
uint16_t kernel_code_properties
uint32_t compute_pgm_rsrc3
int64_t kernel_code_entry_byte_offset