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#define | offsetof(TYPE, MEMBER) ((size_t)&((TYPE*)0)->MEMBER) |
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#define | AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) |
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#define | AMDHSA_BITS_GET(SRC, MSK) ((SRC & MSK) >> MSK ## _SHIFT) |
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#define | AMDHSA_BITS_SET(DST, MSK, VAL) |
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#define | COMPUTE_PGM_RSRC1(NAME, SHIFT, WIDTH) AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC1_ ## NAME, SHIFT, WIDTH) |
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#define | COMPUTE_PGM_RSRC2(NAME, SHIFT, WIDTH) AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC2_ ## NAME, SHIFT, WIDTH) |
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#define | COMPUTE_PGM_RSRC3_GFX90A(NAME, SHIFT, WIDTH) AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX90A_ ## NAME, SHIFT, WIDTH) |
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#define | COMPUTE_PGM_RSRC3_GFX10_PLUS(NAME, SHIFT, WIDTH) AMDHSA_BITS_ENUM_ENTRY(COMPUTE_PGM_RSRC3_GFX10_PLUS_ ## NAME, SHIFT, WIDTH) |
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#define | KERNEL_CODE_PROPERTY(NAME, SHIFT, WIDTH) AMDHSA_BITS_ENUM_ENTRY(KERNEL_CODE_PROPERTY_ ## NAME, SHIFT, WIDTH) |
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enum | : uint8_t { llvm::amdhsa::FLOAT_ROUND_MODE_NEAR_EVEN = 0
, llvm::amdhsa::FLOAT_ROUND_MODE_PLUS_INFINITY = 1
, llvm::amdhsa::FLOAT_ROUND_MODE_MINUS_INFINITY = 2
, llvm::amdhsa::FLOAT_ROUND_MODE_ZERO = 3
} |
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enum | : uint8_t { llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_SRC_DST = 0
, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_DST = 1
, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_SRC = 2
, llvm::amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE = 3
} |
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enum | : uint8_t { llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X = 0
, llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X_Y = 1
, llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_X_Y_Z = 2
, llvm::amdhsa::SYSTEM_VGPR_WORKITEM_ID_UNDEFINED = 3
} |
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enum | : int32_t {
llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
,
llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
,
llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
,
llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
,
llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC1 =(GRANULATED_WORKITEM_VGPR_COUNT, 0, 6)
} |
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enum | : int32_t {
llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
,
llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
,
llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
,
llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
,
llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
, llvm::amdhsa::COMPUTE_PGM_RSRC2 =(ENABLE_PRIVATE_SEGMENT, 0, 1)
} |
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enum | : int32_t { llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6)
, llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX90A =(ACCUM_OFFSET, 0, 6)
} |
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enum | : int32_t {
llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(SHARED_VGPR_COUNT, 0, 4)
, llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(SHARED_VGPR_COUNT, 0, 4)
, llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(SHARED_VGPR_COUNT, 0, 4)
, llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(SHARED_VGPR_COUNT, 0, 4)
,
llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(SHARED_VGPR_COUNT, 0, 4)
, llvm::amdhsa::COMPUTE_PGM_RSRC3_GFX10_PLUS =(SHARED_VGPR_COUNT, 0, 4)
} |
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enum | : int32_t {
llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
, llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
, llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
, llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
,
llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
, llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
, llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
, llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
,
llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
, llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
, llvm::amdhsa::KERNEL_CODE_PROPERTY =(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1)
} |
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enum | : uint32_t {
llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET = 0
, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET = 4
, llvm::amdhsa::KERNARG_SIZE_OFFSET = 8
, llvm::amdhsa::RESERVED0_OFFSET = 12
,
llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET = 16
, llvm::amdhsa::RESERVED1_OFFSET = 24
, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET = 44
, llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET = 48
,
llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET = 52
, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET = 56
, llvm::amdhsa::RESERVED2_OFFSET = 58
} |
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AMDHSA kernel descriptor definitions.
For more information, visit https://llvm.org/docs/AMDGPUUsage.html#kernel-descriptor
Definition in file AMDHSAKernelDescriptor.h.