LLVM 18.0.0git
|
#include "Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"
Public Types | |
enum | OpWidthTy { OPW32 , OPW64 , OPW96 , OPW128 , OPW160 , OPW256 , OPW288 , OPW320 , OPW352 , OPW384 , OPW512 , OPW1024 , OPW16 , OPWV216 , OPWV232 , OPW_LAST_ , OPW_FIRST_ = OPW32 } |
![]() | |
enum | DecodeStatus { Fail = 0 , SoftFail = 1 , Success = 3 } |
Ternary decode status. More... | |
Static Public Member Functions | |
static MCOperand | decodeIntImmed (unsigned Imm) |
static MCOperand | decodeFPImmed (unsigned ImmWidth, unsigned Imm) |
Additional Inherited Members | |
![]() | |
raw_ostream * | CommentStream = nullptr |
![]() | |
const MCSubtargetInfo & | STI |
std::unique_ptr< MCSymbolizer > | Symbolizer |
Definition at line 92 of file AMDGPUDisassembler.h.
Enumerator | |
---|---|
OPW32 | |
OPW64 | |
OPW96 | |
OPW128 | |
OPW160 | |
OPW256 | |
OPW288 | |
OPW320 | |
OPW352 | |
OPW384 | |
OPW512 | |
OPW1024 | |
OPW16 | |
OPWV216 | |
OPWV232 | |
OPW_LAST_ | |
OPW_FIRST_ |
Definition at line 203 of file AMDGPUDisassembler.h.
AMDGPUDisassembler::AMDGPUDisassembler | ( | const MCSubtargetInfo & | STI, |
MCContext & | Ctx, | ||
MCInstrInfo const * | MCII | ||
) |
Definition at line 47 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm::report_fatal_error(), and llvm::MCDisassembler::STI.
|
overridedefault |
DecodeStatus AMDGPUDisassembler::convertDPP8Inst | ( | MCInst & | MI | ) | const |
Definition at line 855 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), convertMacDPPInst(), convertVOP3PDPPInst(), convertVOPCDPPInst(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), isMacDPP(), isValidDPP8(), llvm::AMDGPU::isVOPC64DPP(), MI, llvm::MCDisassembler::SoftFail, llvm::MCDisassembler::Success, llvm::SIInstrFlags::VOP3P, and llvm::SIInstrFlags::VOPC.
Referenced by getInstruction().
DecodeStatus AMDGPUDisassembler::convertEXPInst | ( | MCInst & | MI | ) | const |
Definition at line 745 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCSubtargetInfo::hasFeature(), insertNamedMCOperand(), MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.
Referenced by getInstruction().
DecodeStatus AMDGPUDisassembler::convertFMAanyK | ( | MCInst & | MI, |
int | ImmLitIdx | ||
) | const |
Definition at line 1101 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), I, insertNamedMCOperand(), llvm::AMDGPU::EncValues::LITERAL_CONST, MI, llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED, and llvm::MCDisassembler::Success.
Referenced by getInstruction().
void AMDGPUDisassembler::convertMacDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 846 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), insertNamedMCOperand(), and MI.
Referenced by convertDPP8Inst(), and convertVOP3DPPInst().
DecodeStatus AMDGPUDisassembler::convertMIMGInst | ( | MCInst & | MI | ) | const |
Definition at line 906 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::MIMGBaseOpcodeInfo::A16, addOperand(), assert(), llvm::AMDGPU::MIMGBaseOpcodeInfo::BVH, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::SIInstrFlags::Gather4, llvm::AMDGPU::getAddrSizeMIMGOp(), llvm::MCRegisterInfo::getMatchingSuperReg(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getMIMGOpcode(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasG16(), llvm::AMDGPU::hasPackedD16(), Info, isGFX10Plus(), MI, llvm::popcount(), llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, and TSFlags.
Referenced by getInstruction().
DecodeStatus AMDGPUDisassembler::convertSDWAInst | ( | MCInst & | MI | ) | const |
Definition at line 767 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), createRegOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCSubtargetInfo::hasFeature(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.
Referenced by getInstruction().
DecodeStatus AMDGPUDisassembler::convertVINTERPInst | ( | MCInst & | MI | ) | const |
Definition at line 755 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::Success.
Referenced by getInstruction().
DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst | ( | MCInst & | MI | ) | const |
Definition at line 888 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), convertMacDPPInst(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), isMacDPP(), MI, and llvm::MCDisassembler::Success.
Referenced by getInstruction().
DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1051 of file AMDGPUDisassembler.cpp.
References collectVOPModifiers(), llvm::MCOperand::createImm(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::Success.
Referenced by convertDPP8Inst(), and getInstruction().
DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst | ( | MCInst & | MI | ) | const |
Definition at line 1081 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::AMDGPU::hasNamedOperand(), insertNamedMCOperand(), MI, and llvm::MCDisassembler::Success.
Referenced by convertDPP8Inst(), and getInstruction().
Definition at line 1137 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createReg(), llvm::AMDGPU::getMCReg(), and llvm::MCDisassembler::STI.
Referenced by convertSDWAInst(), createRegOperand(), createSRegOperand(), createVGPR16Operand(), decodeSDWASrc(), decodeSDWAVopcDst(), decodeSpecialReg32(), decodeSpecialReg64(), decodeSrcOp(), decodeVOPDDstYOp(), and getInstruction().
Definition at line 1142 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), and getRegClassName().
Definition at line 1152 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::CommentStream, createRegOperand(), getRegClassName(), and llvm_unreachable.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1199 of file AMDGPUDisassembler.cpp.
References createRegOperand().
Definition at line 1670 of file AMDGPUDisassembler.cpp.
References decodeSrcOp(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, and llvm::MCDisassembler::STI.
MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream | ||
) | const |
Decode as directives that handle COMPUTE_PGM_RSRC1.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC1. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 1726 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::Fail, GET_FIELD, llvm::AMDGPU::IsaInfo::getSGPREncodingGranule(), llvm::AMDGPU::IsaInfo::getVGPREncodingGranule(), hasArchitectedFlatScratch(), isGFX10Plus(), PRINT_DIRECTIVE, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.
Referenced by decodeKernelDescriptorDirective().
MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream | ||
) | const |
Decode as directives that handle COMPUTE_PGM_RSRC2.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC2. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 1822 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::Fail, hasArchitectedFlatScratch(), PRINT_DIRECTIVE, and llvm::MCDisassembler::Success.
Referenced by decodeKernelDescriptorDirective().
MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3 | ( | uint32_t | FourByteBuffer, |
raw_string_ostream & | KdStream | ||
) | const |
Decode as directives that handle COMPUTE_PGM_RSRC3.
FourByteBuffer | - Bytes holding contents of COMPUTE_PGM_RSRC3. |
KdStream | - Stream to write the disassembled directives to. |
Definition at line 1876 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::Fail, GET_FIELD, isGFX10Plus(), isGFX90A(), PRINT_DIRECTIVE, PRINT_PSEUDO_DIRECTIVE_COMMENT, and llvm::MCDisassembler::Success.
Referenced by decodeKernelDescriptorDirective().
Definition at line 1321 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), getInlineImmVal16(), getInlineImmVal32(), getInlineImmVal64(), llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MAX, llvm::AMDGPU::EncValues::INLINE_FLOATING_C_MIN, and llvm_unreachable.
Referenced by decodeNonVGPRSrcOp(), and decodeSDWASrc().
Definition at line 1236 of file AMDGPUDisassembler.cpp.
References assert(), and llvm::MCOperand::createImm().
Referenced by decodeNonVGPRSrcOp(), and decodeSDWASrc().
MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor | ( | StringRef | KdName, |
ArrayRef< uint8_t > | Bytes, | ||
uint64_t | KdAddress | ||
) | const |
Definition at line 2065 of file AMDGPUDisassembler.cpp.
References AMDHSA_BITS_GET, llvm::CallingConv::C, llvm::cantFail(), decodeKernelDescriptorDirective(), llvm::MCDisassembler::Fail, isGFX10Plus(), llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm::outs(), llvm::support::endian::read16(), llvm::ArrayRef< T >::size(), llvm::raw_string_ostream::str(), and llvm::MCDisassembler::Success.
Referenced by onSymbolStart().
MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptorDirective | ( | DataExtractor::Cursor & | Cursor, |
ArrayRef< uint8_t > | Bytes, | ||
raw_string_ostream & | KdStream | ||
) | const |
Definition at line 1917 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::AMDHSA_COV5, assert(), llvm::amdhsa::COMPUTE_PGM_RSRC1_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC2_OFFSET, llvm::amdhsa::COMPUTE_PGM_RSRC3_OFFSET, decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), decodeCOMPUTE_PGM_RSRC3(), llvm::MCDisassembler::Fail, llvm::AMDGPU::getAmdhsaCodeObjectVersion(), llvm::DataExtractor::getBytes(), llvm::DataExtractor::getU16(), llvm::DataExtractor::getU32(), llvm::amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET, hasArchitectedFlatScratch(), I, isGFX10Plus(), isGFX9(), llvm::amdhsa::KERNARG_PRELOAD_OFFSET, llvm::amdhsa::KERNARG_SIZE_OFFSET, llvm::amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET, llvm::amdhsa::KERNEL_CODE_PROPERTIES_OFFSET, llvm_unreachable, PRINT_DIRECTIVE, llvm::amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET, llvm::amdhsa::RESERVED0_OFFSET, llvm::amdhsa::RESERVED1_OFFSET, llvm::amdhsa::RESERVED3_OFFSET, llvm::ArrayRef< T >::size(), llvm::DataExtractor::skip(), llvm::MCDisassembler::Success, and llvm::DataExtractor::Cursor::tell().
Referenced by decodeKernelDescriptor().
MCOperand AMDGPUDisassembler::decodeLiteralConstant | ( | ) | const |
Definition at line 1221 of file AMDGPUDisassembler.cpp.
References llvm::MCOperand::createImm(), errOperand(), and llvm::ArrayRef< T >::size().
Referenced by decodeNonVGPRSrcOp().
Definition at line 1208 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), errOperand(), llvm::AMDGPU::hasVOPD(), and llvm::MCDisassembler::STI.
MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp | ( | const OpWidthTy | Width, |
unsigned | Val, | ||
bool | MandatoryLiteral = false , |
||
unsigned | ImmWidth = 0 |
||
) | const |
Definition at line 1465 of file AMDGPUDisassembler.cpp.
References assert(), llvm::MCOperand::createImm(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeLiteralConstant(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm_unreachable, OPW16, OPW32, OPW64, OPWV216, OPWV232, and SGPR_MAX.
Referenced by decodeSrcOp().
MCOperand AMDGPUDisassembler::decodeSDWASrc | ( | const OpWidthTy | Width, |
unsigned | Val, | ||
unsigned | ImmWidth = 0 |
||
) | const |
Definition at line 1593 of file AMDGPUDisassembler.cpp.
References createRegOperand(), createSRegOperand(), decodeFPImmed(), decodeIntImmed(), decodeSpecialReg32(), getSgprClassId(), getTtmpClassId(), getVgprClassId(), llvm::MCSubtargetInfo::hasFeature(), isGFX10Plus(), llvm_unreachable, and llvm::MCDisassembler::STI.
Referenced by decodeSDWASrc16(), and decodeSDWASrc32().
Definition at line 1635 of file AMDGPUDisassembler.cpp.
References decodeSDWASrc(), and OPW16.
Definition at line 1639 of file AMDGPUDisassembler.cpp.
References decodeSDWASrc(), and OPW32.
Definition at line 1643 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), createSRegOperand(), decodeSpecialReg32(), decodeSpecialReg64(), getSgprClassId(), getTtmpClassId(), getTTmpIdx(), llvm::MCSubtargetInfo::hasFeature(), OPW32, OPW64, SGPR_MAX, and llvm::MCDisassembler::STI.
Definition at line 1526 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), isGFX11Plus(), and llvm::M0().
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1562 of file AMDGPUDisassembler.cpp.
References createRegOperand(), errOperand(), and isGFX11Plus().
Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().
MCOperand AMDGPUDisassembler::decodeSrcOp | ( | const OpWidthTy | Width, |
unsigned | Val, | ||
bool | MandatoryLiteral = false , |
||
unsigned | ImmWidth = 0 |
||
) | const |
Definition at line 1448 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), decodeNonVGPRSrcOp(), getAgprClassId(), and getVgprClassId().
Referenced by decodeBoolReg().
Definition at line 1514 of file AMDGPUDisassembler.cpp.
References assert(), createRegOperand(), llvm::MCRegisterInfo::getEncodingValue(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), getVgprClassId(), llvm::MCOperand::isReg(), and OPW32.
Definition at line 1127 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::CommentStream.
Referenced by createRegOperand(), decodeLiteralConstant(), decodeMandatoryLiteralConstant(), decodeSpecialReg32(), and decodeSpecialReg64().
|
overridevirtual |
Returns the disassembly of a single instruction.
Instr | - An MCInst to populate with the contents of the instruction. |
Size | - A value to populate with the size of the instruction, or the number of bytes consumed while attempting to decode an invalid instruction. |
Address | - The address, in the memory space of region, of the first byte of the instruction. |
Bytes | - A reference to the actual bytes of the instruction. |
CStream | - The stream to print comments and annotations on. |
Implements llvm::MCDisassembler.
Definition at line 460 of file AMDGPUDisassembler.cpp.
References llvm::Address, assert(), convertDPP8Inst(), convertEXPInst(), convertFMAanyK(), convertMIMGInst(), convertSDWAInst(), convertVINTERPInst(), convertVOP3DPPInst(), convertVOP3PDPPInst(), convertVOPCDPPInst(), llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), createRegOperand(), eat12Bytes(), llvm::SIInstrFlags::EXP, llvm::MCDisassembler::Fail, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::CPol::GLC, llvm::MCSubtargetInfo::hasFeature(), insertNamedMCOperand(), llvm::SIInstrFlags::IsAtomicRet, isGFX11Plus(), llvm::AMDGPU::isMAC(), llvm::AMDGPU::isVOPC64DPP(), MI, llvm::SIInstrFlags::MIMG, llvm::SIInstrFlags::MTBUF, llvm::SIInstrFlags::MUBUF, llvm::ArrayRef< T >::size(), Size, llvm::ArrayRef< T >::slice(), llvm::SIInstrFlags::SMRD, llvm::SIInstrFlags::SOPK, llvm::MCDisassembler::STI, llvm::MCDisassembler::Success, llvm::MCOI::TIED_TO, tryDecodeInst(), llvm::SIInstrFlags::VINTERP, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, and llvm::SIInstrFlags::VOPC.
|
inline |
Definition at line 256 of file AMDGPUDisassembler.h.
References llvm::MCInstrInfo::get().
Definition at line 1121 of file AMDGPUDisassembler.cpp.
References llvm::MCDisassembler::getContext(), getRegClassName(), and llvm::MCContext::getRegisterInfo().
Referenced by createRegOperand(), createSRegOperand(), and getRegClassName().
Definition at line 1393 of file AMDGPUDisassembler.cpp.
References assert(), OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
Definition at line 1417 of file AMDGPUDisassembler.cpp.
References assert(), OPW128, OPW16, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.
Referenced by decodeNonVGPRSrcOp(), decodeSDWASrc(), and decodeSDWAVopcDst().
int AMDGPUDisassembler::getTTmpIdx | ( | unsigned | Val | ) | const |
Definition at line 1439 of file AMDGPUDisassembler.cpp.
References isGFX9Plus().
Referenced by decodeNonVGPRSrcOp(), and decodeSDWAVopcDst().
Definition at line 1342 of file AMDGPUDisassembler.cpp.
References assert(), OPW1024, OPW128, OPW16, OPW160, OPW256, OPW288, OPW32, OPW320, OPW352, OPW384, OPW512, OPW64, OPW96, OPW_FIRST_, OPW_LAST_, OPWV216, and OPWV232.
Referenced by decodeSDWASrc(), decodeSrcOp(), and decodeVOPDDstYOp().
bool AMDGPUDisassembler::hasArchitectedFlatScratch | ( | ) | const |
Definition at line 1703 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC2(), and decodeKernelDescriptorDirective().
bool AMDGPUDisassembler::hasKernargPreload | ( | ) | const |
Definition at line 1707 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::hasKernargPreload(), and llvm::MCDisassembler::STI.
bool AMDGPUDisassembler::isGFX10 | ( | ) | const |
Definition at line 1688 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX10(), and llvm::MCDisassembler::STI.
bool AMDGPUDisassembler::isGFX10Plus | ( | ) | const |
Definition at line 1690 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX10Plus(), and llvm::MCDisassembler::STI.
Referenced by AMDGPUDisassembler(), convertMIMGInst(), decodeCOMPUTE_PGM_RSRC1(), decodeCOMPUTE_PGM_RSRC3(), decodeKernelDescriptor(), decodeKernelDescriptorDirective(), and decodeSDWASrc().
bool AMDGPUDisassembler::isGFX11 | ( | ) | const |
Definition at line 1694 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
bool AMDGPUDisassembler::isGFX11Plus | ( | ) | const |
Definition at line 1698 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX11Plus(), and llvm::MCDisassembler::STI.
Referenced by decodeSpecialReg32(), decodeSpecialReg64(), and getInstruction().
bool AMDGPUDisassembler::isGFX9 | ( | ) | const |
Definition at line 1680 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX9(), and llvm::MCDisassembler::STI.
Referenced by decodeKernelDescriptorDirective().
bool AMDGPUDisassembler::isGFX90A | ( | ) | const |
Definition at line 1682 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
Referenced by decodeCOMPUTE_PGM_RSRC3().
bool AMDGPUDisassembler::isGFX9Plus | ( | ) | const |
Definition at line 1686 of file AMDGPUDisassembler.cpp.
References llvm::AMDGPU::isGFX9Plus(), and llvm::MCDisassembler::STI.
Referenced by getTTmpIdx().
Definition at line 826 of file AMDGPUDisassembler.cpp.
References assert(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), MI, and llvm::MCOI::TIED_TO.
Referenced by convertDPP8Inst(), and convertVOP3DPPInst().
bool AMDGPUDisassembler::isVI | ( | ) | const |
Definition at line 1676 of file AMDGPUDisassembler.cpp.
References llvm::MCSubtargetInfo::hasFeature(), and llvm::MCDisassembler::STI.
|
overridevirtual |
Used to perform separate target specific disassembly for a particular symbol.
May parse any prelude that precedes instructions after the start of a symbol, or the entire symbol. This is used for example by WebAssembly to decode preludes.
Base implementation returns std::nullopt. So all targets by default ignore to treat symbols separately.
Symbol | - The symbol. |
Size | - The number of bytes consumed. |
Address | - The address, in the memory space of region, of the first byte of the symbol. |
Bytes | - A reference to the actual bytes at the symbol location. |
CStream | - The stream to print comments and annotations on. |
Reimplemented from llvm::MCDisassembler.
Definition at line 2105 of file AMDGPUDisassembler.cpp.
References llvm::Address, decodeKernelDescriptor(), llvm::MCDisassembler::Fail, Name, Size, llvm::ELF::STT_AMDGPU_HSA_KERNEL, and llvm::ELF::STT_OBJECT.
|
inline |
Definition at line 122 of file AMDGPUDisassembler.h.
References llvm::Address, assert(), llvm::MCDisassembler::CommentStream, llvm::MCDisassembler::Fail, MI, llvm::MCDisassembler::STI, and llvm::MCDisassembler::Success.
Referenced by getInstruction(), and tryDecodeInst().
|
inline |
Definition at line 149 of file AMDGPUDisassembler.h.
References llvm::Address, llvm::MCDisassembler::Fail, MI, and tryDecodeInst().