Go to the documentation of this file.
21 #include "llvm/IR/IntrinsicsSPIRV.h"
31 for (
unsigned WordIndex = 0; WordIndex < 4; ++WordIndex) {
32 unsigned StrIndex =
i + WordIndex;
33 uint8_t CharToAdd = 0;
34 if (StrIndex < Str.size()) {
35 CharToAdd = Str[StrIndex];
37 Word |= (CharToAdd << (WordIndex * 8));
44 const size_t Len = Str.size() + 1;
45 return (Len % 4 == 0) ? Len : Len + (4 - (Len % 4));
50 for (
unsigned i = 0;
i < PaddedLen;
i += 4) {
57 std::vector<Value *> &
Args) {
59 for (
unsigned i = 0;
i < PaddedLen;
i += 4) {
70 const auto Bitwidth =
Imm.getBitWidth();
81 uint32_t LowBits = FullImm & 0xffffffff;
82 uint32_t HighBits = (FullImm >> 32) & 0xffffffff;
100 const std::vector<uint32_t> &DecArgs,
104 for (
const auto &DecArg : DecArgs)
110 const std::vector<uint32_t> &DecArgs,
StringRef StrImm) {
111 auto MIB = MIRBuilder.
buildInstr(SPIRV::OpDecorate)
119 const std::vector<uint32_t> &DecArgs,
StringRef StrImm) {
121 auto MIB =
BuildMI(
MBB,
I,
I.getDebugLoc(),
TII.get(SPIRV::OpDecorate))
188 if (ConstInstr->
getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS &&
192 }
else if (ConstInstr->
getOpcode() == SPIRV::ASSIGN_TYPE) {
201 assert(
MI &&
MI->getOpcode() == TargetOpcode::G_CONSTANT);
202 return MI->getOperand(1).getCImm()->getValue().getZExtValue();
206 return cast<ValueAsMetadata>(
N->getOperand(
I))->getType();
static uint32_t convertCharsToWord(const StringRef &Str, unsigned i)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Target - Wrapper for Target specific information.
Reg
All possible values of the reg field in the ModR/M byte.
The instances of the Type class are immutable: once they are created, they are never changed.
MachineInstr * getDefInstrMaybeConstant(Register &ConstReg, const MachineRegisterInfo *MRI)
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
const MachineOperand & getOperand(unsigned i) const
const HexagonInstrInfo * TII
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
unsigned getIntrinsicID() const
Returns the Intrinsic::ID for this instruction.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
void addStringImm(const StringRef &Str, MachineInstrBuilder &MIB)
SPIRV::MemorySemantics getMemSemanticsForStorageClass(SPIRV::StorageClass SC)
SPIRV::StorageClass addressSpaceToStorageClass(unsigned AddrSpace)
static void finishBuildOpDecorate(MachineInstrBuilder &MIB, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
Helper class to build MachineInstr.
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Representation of each machine instruction.
unsigned storageClassToAddressSpace(SPIRV::StorageClass SC)
void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::string getSPIRVStringOperand(const InstType &MI, unsigned StartIndex)
void buildOpDecorate(Register Reg, MachineIRBuilder &MIRBuilder, llvm::SPIRV::Decoration Dec, const std::vector< uint32_t > &DecArgs, StringRef StrImm)
const MachineInstrBuilder & addUse(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register use operand.
Register getReg() const
getReg - Returns the register number.
support::ulittle32_t Word
Class for arbitrary precision integers.
MachineInstrBuilder buildInstr(unsigned Opcode)
Build and insert <empty> = Opcode <empty>.
StringRef - Represent a constant reference to a string, i.e.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void buildOpName(Register Target, const StringRef &Name, MachineIRBuilder &MIRBuilder)
unsigned const MachineRegisterInfo * MRI
Wrapper class representing virtual and physical registers.
static size_t getPaddedLen(const StringRef &Str)
std::string getStringImm(const MachineInstr &MI, unsigned StartIndex)
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t getIConstVal(Register ConstReg, const MachineRegisterInfo *MRI)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Type * getMDOperandAsType(const MDNode *N, unsigned I)