LLVM 19.0.0git
AMDGPUDisassembler.h
Go to the documentation of this file.
1//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This file contains declaration for AMDGPU ISA disassembler
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17
18#include "SIDefines.h"
19#include "llvm/ADT/APInt.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
25#include <memory>
26
27namespace llvm {
28
29class MCAsmInfo;
30class MCInst;
31class MCOperand;
32class MCSubtargetInfo;
33class Twine;
34
35// Exposes an interface expected by autogenerated code in
36// FixedLenDecoderEmitter
38private:
39 uint64_t Lo = 0;
40 uint64_t Hi = 0;
41
42public:
43 DecoderUInt128() = default;
45 operator bool() const { return Lo || Hi; }
46 void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits) {
47 assert(NumBits && NumBits <= 64);
48 assert(SubBits >> 1 >> (NumBits - 1) == 0);
49 assert(BitPosition < 128);
50 if (BitPosition < 64) {
51 Lo |= SubBits << BitPosition;
52 Hi |= SubBits >> 1 >> (63 - BitPosition);
53 } else {
54 Hi |= SubBits << (BitPosition - 64);
55 }
56 }
58 unsigned BitPosition) const {
59 assert(NumBits && NumBits <= 64);
60 assert(BitPosition < 128);
61 uint64_t Val;
62 if (BitPosition < 64)
63 Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition);
64 else
65 Val = Hi >> (BitPosition - 64);
66 return Val & ((uint64_t(2) << (NumBits - 1)) - 1);
67 }
69 return DecoderUInt128(Lo & RHS.Lo, Hi & RHS.Hi);
70 }
72 return *this & DecoderUInt128(RHS);
73 }
76 return Lo == RHS.Lo && Hi == RHS.Hi;
77 }
79 return Lo != RHS.Lo || Hi != RHS.Hi;
80 }
81 bool operator!=(const int &RHS) {
82 return *this != DecoderUInt128(RHS);
83 }
85 return OS << APInt(128, {RHS.Lo, RHS.Hi});
86 }
87};
88
89//===----------------------------------------------------------------------===//
90// AMDGPUDisassembler
91//===----------------------------------------------------------------------===//
92
94private:
95 std::unique_ptr<MCInstrInfo const> const MCII;
96 const MCRegisterInfo &MRI;
97 const MCAsmInfo &MAI;
98 const unsigned TargetMaxInstBytes;
99 mutable ArrayRef<uint8_t> Bytes;
100 mutable uint32_t Literal;
101 mutable uint64_t Literal64;
102 mutable bool HasLiteral;
103 mutable std::optional<bool> EnableWavefrontSize32;
104 unsigned CodeObjectVersion;
105
106public:
108 MCInstrInfo const *MCII);
109 ~AMDGPUDisassembler() override = default;
110
111 void setABIVersion(unsigned Version) override;
112
115 raw_ostream &CS) const override;
116
117 const char* getRegClassName(unsigned RegClassID) const;
118
119 MCOperand createRegOperand(unsigned int RegId) const;
120 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
121 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
122 MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const;
123
124 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
125
126 template <typename InsnType>
127 DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
128 uint64_t Address, raw_ostream &Comments) const {
129 assert(MI.getOpcode() == 0);
130 assert(MI.getNumOperands() == 0);
131 MCInst TmpInst;
132 HasLiteral = false;
133 const auto SavedBytes = Bytes;
134
135 SmallString<64> LocalComments;
136 raw_svector_ostream LocalCommentStream(LocalComments);
137 CommentStream = &LocalCommentStream;
138
139 DecodeStatus Res =
140 decodeInstruction(Table, TmpInst, Inst, Address, this, STI);
141
142 CommentStream = nullptr;
143
144 if (Res != Fail) {
145 MI = TmpInst;
146 Comments << LocalComments;
148 }
149 Bytes = SavedBytes;
151 }
152
153 template <typename InsnType>
154 DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
155 MCInst &MI, InsnType Inst, uint64_t Address,
156 raw_ostream &Comments) const {
157 for (const uint8_t *T : {Table1, Table2}) {
158 if (DecodeStatus Res = tryDecodeInst(T, MI, Inst, Address, Comments))
159 return Res;
160 }
162 }
163
165 ArrayRef<uint8_t> Bytes,
166 uint64_t Address) const override;
167
169 ArrayRef<uint8_t> Bytes,
170 uint64_t KdAddress) const;
171
174 ArrayRef<uint8_t> Bytes,
175 raw_string_ostream &KdStream) const;
176
177 /// Decode as directives that handle COMPUTE_PGM_RSRC1.
178 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
179 /// \param KdStream - Stream to write the disassembled directives to.
180 // NOLINTNEXTLINE(readability-identifier-naming)
182 raw_string_ostream &KdStream) const;
183
184 /// Decode as directives that handle COMPUTE_PGM_RSRC2.
185 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
186 /// \param KdStream - Stream to write the disassembled directives to.
187 // NOLINTNEXTLINE(readability-identifier-naming)
189 raw_string_ostream &KdStream) const;
190
191 /// Decode as directives that handle COMPUTE_PGM_RSRC3.
192 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC3.
193 /// \param KdStream - Stream to write the disassembled directives to.
194 // NOLINTNEXTLINE(readability-identifier-naming)
196 raw_string_ostream &KdStream) const;
197
198 void convertEXPInst(MCInst &MI) const;
199 void convertVINTERPInst(MCInst &MI) const;
200 void convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
201 void convertSDWAInst(MCInst &MI) const;
202 void convertDPP8Inst(MCInst &MI) const;
203 void convertMIMGInst(MCInst &MI) const;
204 void convertVOP3DPPInst(MCInst &MI) const;
205 void convertVOP3PDPPInst(MCInst &MI) const;
206 void convertVOPCDPPInst(MCInst &MI) const;
207 void convertMacDPPInst(MCInst &MI) const;
208 void convertTrue16OpSel(MCInst &MI) const;
209
228 };
229
230 unsigned getVgprClassId(const OpWidthTy Width) const;
231 unsigned getAgprClassId(const OpWidthTy Width) const;
232 unsigned getSgprClassId(const OpWidthTy Width) const;
233 unsigned getTtmpClassId(const OpWidthTy Width) const;
234
235 static MCOperand decodeIntImmed(unsigned Imm);
236 static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm,
238
239 MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
240 MCOperand decodeLiteralConstant(bool ExtendFP64) const;
241
243 const OpWidthTy Width, unsigned Val, bool MandatoryLiteral = false,
244 unsigned ImmWidth = 0,
246
248 const OpWidthTy Width, unsigned Val, bool MandatoryLiteral = false,
249 unsigned ImmWidth = 0,
251
252 MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
253 MCOperand decodeSpecialReg32(unsigned Val) const;
254 MCOperand decodeSpecialReg64(unsigned Val) const;
255
256 MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val,
257 unsigned ImmWidth,
258 AMDGPU::OperandSemantics Sema) const;
259 MCOperand decodeSDWASrc16(unsigned Val) const;
260 MCOperand decodeSDWASrc32(unsigned Val) const;
261 MCOperand decodeSDWAVopcDst(unsigned Val) const;
262
263 MCOperand decodeBoolReg(unsigned Val) const;
264 MCOperand decodeSplitBarrier(unsigned Val) const;
265 MCOperand decodeDpp8FI(unsigned Val) const;
266
267 int getTTmpIdx(unsigned Val) const;
268
269 const MCInstrInfo *getMCII() const { return MCII.get(); }
270
271 bool isVI() const;
272 bool isGFX9() const;
273 bool isGFX90A() const;
274 bool isGFX9Plus() const;
275 bool isGFX10() const;
276 bool isGFX10Plus() const;
277 bool isGFX11() const;
278 bool isGFX11Plus() const;
279 bool isGFX12() const;
280 bool isGFX12Plus() const;
281
282 bool hasArchitectedFlatScratch() const;
283 bool hasKernargPreload() const;
284
285 bool isMacDPP(MCInst &MI) const;
286};
287
288//===----------------------------------------------------------------------===//
289// AMDGPUSymbolizer
290//===----------------------------------------------------------------------===//
291
293private:
294 void *DisInfo;
295 std::vector<uint64_t> ReferencedAddresses;
296
297public:
298 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
299 void *disInfo)
300 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
301
302 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
303 int64_t Value, uint64_t Address, bool IsBranch,
304 uint64_t Offset, uint64_t OpSize,
305 uint64_t InstSize) override;
306
308 int64_t Value,
309 uint64_t Address) override;
310
312 return ReferencedAddresses;
313 }
314};
315
316} // end namespace llvm
317
318#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
This file implements a class to represent arbitrary precision integral constant values and operations...
uint64_t Size
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file defines the SmallString class.
Value * RHS
support::ulittle16_t & Lo
Definition: aarch32.cpp:206
support::ulittle16_t & Hi
Definition: aarch32.cpp:205
const MCInstrInfo * getMCII() const
void convertEXPInst(MCInst &MI) const
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
Expected< bool > decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
Expected< bool > decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
void convertVOPCDPPInst(MCInst &MI) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
void setABIVersion(unsigned Version) override
ELF-specific, set the ABI version from the object header.
Expected< bool > decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
MCOperand decodeDpp8FI(unsigned Val) const
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
void convertDPP8Inst(MCInst &MI) const
MCOperand createVGPR16Operand(unsigned RegIdx, bool IsHi) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth, AMDGPU::OperandSemantics Sema) const
Expected< bool > decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeSplitBarrier(unsigned Val) const
void convertVOP3DPPInst(MCInst &MI) const
void convertTrue16OpSel(MCInst &MI) const
void convertFMAanyK(MCInst &MI, int ImmLitIdx) const
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
MCOperand decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) const
Expected< bool > decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC3.
static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm, AMDGPU::OperandSemantics Sema)
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0, AMDGPU::OperandSemantics Sema=AMDGPU::OperandSemantics::INT) const
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeLiteralConstant(bool ExtendFP64) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
~AMDGPUDisassembler() override=default
void convertVINTERPInst(MCInst &MI) const
void convertSDWAInst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getTtmpClassId(const OpWidthTy Width) const
void convertMIMGInst(MCInst &MI) const
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
void convertVOP3PDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
MCOperand decodeSDWASrc16(unsigned Val) const
Expected< bool > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address) const override
Used to perform separate target specific disassembly for a particular symbol.
ArrayRef< uint64_t > getReferencedAddresses() const override
Get the MCSymbolizer's list of addresses that were referenced by symbolizable operands but not resolv...
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
Definition: APInt.h:77
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
bool operator==(const DecoderUInt128 &RHS)
DecoderUInt128 operator~() const
bool operator!=(const DecoderUInt128 &RHS)
DecoderUInt128 operator&(const uint64_t &RHS) const
DecoderUInt128 operator&(const DecoderUInt128 &RHS) const
DecoderUInt128(uint64_t Lo, uint64_t Hi=0)
DecoderUInt128()=default
uint64_t extractBitsAsZExtValue(unsigned NumBits, unsigned BitPosition) const
friend raw_ostream & operator<<(raw_ostream &OS, const DecoderUInt128 &RHS)
bool operator!=(const int &RHS)
void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits)
Tagged union holding either a T or a Error.
Definition: Error.h:474
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
Context object for machine code objects.
Definition: MCContext.h:81
Superclass for all disassemblers.
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
std::unique_ptr< MCRelocationInfo > RelInfo
Definition: MCSymbolizer.h:42
MCContext & Ctx
Definition: MCSymbolizer.h:41
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:661
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:691
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1849
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858