LLVM 18.0.0git
AMDGPUDisassembler.h
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1//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This file contains declaration for AMDGPU ISA disassembler
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17
18#include "llvm/ADT/APInt.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrInfo.h"
24#include <memory>
25
26namespace llvm {
27
28class MCAsmInfo;
29class MCInst;
30class MCOperand;
31class MCSubtargetInfo;
32class Twine;
33
34// Exposes an interface expected by autogenerated code in
35// FixedLenDecoderEmitter
37private:
38 uint64_t Lo = 0;
39 uint64_t Hi = 0;
40
41public:
42 DecoderUInt128() = default;
43 DecoderUInt128(uint64_t Lo, uint64_t Hi = 0) : Lo(Lo), Hi(Hi) {}
44 operator bool() const { return Lo || Hi; }
45 void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits) {
46 assert(NumBits && NumBits <= 64);
47 assert(SubBits >> 1 >> (NumBits - 1) == 0);
48 assert(BitPosition < 128);
49 if (BitPosition < 64) {
50 Lo |= SubBits << BitPosition;
51 Hi |= SubBits >> 1 >> (63 - BitPosition);
52 } else {
53 Hi |= SubBits << (BitPosition - 64);
54 }
55 }
57 unsigned BitPosition) const {
58 assert(NumBits && NumBits <= 64);
59 assert(BitPosition < 128);
60 uint64_t Val;
61 if (BitPosition < 64)
62 Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition);
63 else
64 Val = Hi >> (BitPosition - 64);
65 return Val & ((uint64_t(2) << (NumBits - 1)) - 1);
66 }
68 return DecoderUInt128(Lo & RHS.Lo, Hi & RHS.Hi);
69 }
71 return *this & DecoderUInt128(RHS);
72 }
73 DecoderUInt128 operator~() const { return DecoderUInt128(~Lo, ~Hi); }
75 return Lo == RHS.Lo && Hi == RHS.Hi;
76 }
78 return Lo != RHS.Lo || Hi != RHS.Hi;
79 }
80 bool operator!=(const int &RHS) {
81 return *this != DecoderUInt128(RHS);
82 }
84 return OS << APInt(128, {RHS.Lo, RHS.Hi});
85 }
86};
87
88//===----------------------------------------------------------------------===//
89// AMDGPUDisassembler
90//===----------------------------------------------------------------------===//
91
93private:
94 std::unique_ptr<MCInstrInfo const> const MCII;
95 const MCRegisterInfo &MRI;
96 const MCAsmInfo &MAI;
97 const unsigned TargetMaxInstBytes;
98 mutable ArrayRef<uint8_t> Bytes;
99 mutable uint32_t Literal;
100 mutable bool HasLiteral;
101 mutable std::optional<bool> EnableWavefrontSize32;
102
103public:
105 MCInstrInfo const *MCII);
106 ~AMDGPUDisassembler() override = default;
107
110 raw_ostream &CS) const override;
111
112 const char* getRegClassName(unsigned RegClassID) const;
113
114 MCOperand createRegOperand(unsigned int RegId) const;
115 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
116 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
117
118 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
119
120 template <typename InsnType>
121 DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
122 uint64_t Address, raw_ostream &Comments) const {
123 assert(MI.getOpcode() == 0);
124 assert(MI.getNumOperands() == 0);
125 MCInst TmpInst;
126 HasLiteral = false;
127 const auto SavedBytes = Bytes;
128
129 SmallString<64> LocalComments;
130 raw_svector_ostream LocalCommentStream(LocalComments);
131 CommentStream = &LocalCommentStream;
132
133 DecodeStatus Res =
134 decodeInstruction(Table, TmpInst, Inst, Address, this, STI);
135
136 CommentStream = nullptr;
137
138 if (Res != Fail) {
139 MI = TmpInst;
140 Comments << LocalComments;
142 }
143 Bytes = SavedBytes;
145 }
146
147 template <typename InsnType>
148 DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2,
149 MCInst &MI, InsnType Inst, uint64_t Address,
150 raw_ostream &Comments) const {
151 for (const uint8_t *T : {Table1, Table2}) {
152 if (DecodeStatus Res = tryDecodeInst(T, MI, Inst, Address, Comments))
153 return Res;
154 }
156 }
157
158 std::optional<DecodeStatus>
160 uint64_t Address, raw_ostream &CStream) const override;
161
163 uint64_t KdAddress) const;
164
167 ArrayRef<uint8_t> Bytes,
168 raw_string_ostream &KdStream) const;
169
170 /// Decode as directives that handle COMPUTE_PGM_RSRC1.
171 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
172 /// \param KdStream - Stream to write the disassembled directives to.
173 // NOLINTNEXTLINE(readability-identifier-naming)
175 raw_string_ostream &KdStream) const;
176
177 /// Decode as directives that handle COMPUTE_PGM_RSRC2.
178 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
179 /// \param KdStream - Stream to write the disassembled directives to.
180 // NOLINTNEXTLINE(readability-identifier-naming)
182 raw_string_ostream &KdStream) const;
183
184 /// Decode as directives that handle COMPUTE_PGM_RSRC3.
185 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC3.
186 /// \param KdStream - Stream to write the disassembled directives to.
187 // NOLINTNEXTLINE(readability-identifier-naming)
189 raw_string_ostream &KdStream) const;
190
193 DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
200 void convertMacDPPInst(MCInst &MI) const;
201
220 };
221
222 unsigned getVgprClassId(const OpWidthTy Width) const;
223 unsigned getAgprClassId(const OpWidthTy Width) const;
224 unsigned getSgprClassId(const OpWidthTy Width) const;
225 unsigned getTtmpClassId(const OpWidthTy Width) const;
226
227 static MCOperand decodeIntImmed(unsigned Imm);
228 static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm);
229
230 MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
232
233 MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val,
234 bool MandatoryLiteral = false,
235 unsigned ImmWidth = 0) const;
236
237 MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
238 MCOperand decodeSpecialReg32(unsigned Val) const;
239 MCOperand decodeSpecialReg64(unsigned Val) const;
240
241 MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val,
242 unsigned ImmWidth = 0) const;
243 MCOperand decodeSDWASrc16(unsigned Val) const;
244 MCOperand decodeSDWASrc32(unsigned Val) const;
245 MCOperand decodeSDWAVopcDst(unsigned Val) const;
246
247 MCOperand decodeBoolReg(unsigned Val) const;
248
249 int getTTmpIdx(unsigned Val) const;
250
251 const MCInstrInfo *getMCII() const { return MCII.get(); }
252
253 bool isVI() const;
254 bool isGFX9() const;
255 bool isGFX90A() const;
256 bool isGFX9Plus() const;
257 bool isGFX10() const;
258 bool isGFX10Plus() const;
259 bool isGFX11() const;
260 bool isGFX11Plus() const;
261
262 bool hasArchitectedFlatScratch() const;
263 bool hasKernargPreload() const;
264
265 bool isMacDPP(MCInst &MI) const;
266};
267
268//===----------------------------------------------------------------------===//
269// AMDGPUSymbolizer
270//===----------------------------------------------------------------------===//
271
273private:
274 void *DisInfo;
275 std::vector<uint64_t> ReferencedAddresses;
276
277public:
278 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
279 void *disInfo)
280 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
281
282 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
283 int64_t Value, uint64_t Address, bool IsBranch,
284 uint64_t Offset, uint64_t OpSize,
285 uint64_t InstSize) override;
286
288 int64_t Value,
289 uint64_t Address) override;
290
292 return ReferencedAddresses;
293 }
294};
295
296} // end namespace llvm
297
298#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
MCDisassembler::DecodeStatus DecodeStatus
This file implements a class to represent arbitrary precision integral constant values and operations...
uint64_t Size
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file defines the SmallString class.
Value * RHS
const MCInstrInfo * getMCII() const
static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm)
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeLiteralConstant() const
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus convertSDWAInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
~AMDGPUDisassembler() override=default
DecodeStatus convertMIMGInst(MCInst &MI) const
DecodeStatus convertVINTERPInst(MCInst &MI) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
DecodeStatus decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC3.
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
DecodeStatus convertEXPInst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getTtmpClassId(const OpWidthTy Width) const
std::optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth=0) const
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeSDWASrc16(unsigned Val) const
ArrayRef< uint64_t > getReferencedAddresses() const override
Get the MCSymbolizer's list of addresses that were referenced by symbolizable operands but not resolv...
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
Definition: APInt.h:76
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
bool operator==(const DecoderUInt128 &RHS)
DecoderUInt128 operator~() const
bool operator!=(const DecoderUInt128 &RHS)
DecoderUInt128 operator&(const uint64_t &RHS) const
DecoderUInt128 operator&(const DecoderUInt128 &RHS) const
DecoderUInt128(uint64_t Lo, uint64_t Hi=0)
DecoderUInt128()=default
uint64_t extractBitsAsZExtValue(unsigned NumBits, unsigned BitPosition) const
friend raw_ostream & operator<<(raw_ostream &OS, const DecoderUInt128 &RHS)
bool operator!=(const int &RHS)
void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
std::unique_ptr< MCRelocationInfo > RelInfo
Definition: MCSymbolizer.h:42
MCContext & Ctx
Definition: MCSymbolizer.h:41
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
A raw_ostream that writes to an SmallVector or SmallString.
Definition: raw_ostream.h:672
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:440
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1854
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858