15#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
44 operator bool()
const {
return Lo || Hi; }
46 assert(NumBits && NumBits <= 64);
47 assert(SubBits >> 1 >> (NumBits - 1) == 0);
49 if (BitPosition < 64) {
50 Lo |= SubBits << BitPosition;
51 Hi |= SubBits >> 1 >> (63 - BitPosition);
53 Hi |= SubBits << (BitPosition - 64);
57 unsigned BitPosition)
const {
58 assert(NumBits && NumBits <= 64);
62 Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition);
64 Val = Hi >> (BitPosition - 64);
65 return Val & ((
uint64_t(2) << (NumBits - 1)) - 1);
75 return Lo ==
RHS.Lo && Hi ==
RHS.Hi;
78 return Lo !=
RHS.Lo || Hi !=
RHS.Hi;
94 std::unique_ptr<MCInstrInfo const>
const MCII;
97 const unsigned TargetMaxInstBytes;
100 mutable bool HasLiteral;
101 mutable std::optional<bool> EnableWavefrontSize32;
120 template <
typename InsnType>
127 const auto SavedBytes = Bytes;
134 decodeInstruction(Table, TmpInst, Inst,
Address,
this,
STI);
140 Comments << LocalComments;
147 template <
typename InsnType>
151 for (
const uint8_t *
T : {Table1, Table2}) {
158 std::optional<DecodeStatus>
234 bool MandatoryLiteral =
false,
235 unsigned ImmWidth = 0)
const;
242 unsigned ImmWidth = 0)
const;
275 std::vector<uint64_t> ReferencedAddresses;
292 return ReferencedAddresses;
MCDisassembler::DecodeStatus DecodeStatus
This file implements a class to represent arbitrary precision integral constant values and operations...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallString class.
const MCInstrInfo * getMCII() const
static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm)
bool hasKernargPreload() const
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeLiteralConstant() const
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus convertSDWAInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
~AMDGPUDisassembler() override=default
DecodeStatus convertMIMGInst(MCInst &MI) const
DecodeStatus convertVINTERPInst(MCInst &MI) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
DecodeStatus decodeCOMPUTE_PGM_RSRC3(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC3.
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
DecodeStatus convertEXPInst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table1, const uint8_t *Table2, MCInst &MI, InsnType Inst, uint64_t Address, raw_ostream &Comments) const
bool hasArchitectedFlatScratch() const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getTtmpClassId(const OpWidthTy Width) const
std::optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth=0) const
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeSDWASrc16(unsigned Val) const
ArrayRef< uint64_t > getReferencedAddresses() const override
Get the MCSymbolizer's list of addresses that were referenced by symbolizable operands but not resolv...
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool operator==(const DecoderUInt128 &RHS)
DecoderUInt128 operator~() const
bool operator!=(const DecoderUInt128 &RHS)
DecoderUInt128 operator&(const uint64_t &RHS) const
DecoderUInt128 operator&(const DecoderUInt128 &RHS) const
DecoderUInt128(uint64_t Lo, uint64_t Hi=0)
uint64_t extractBitsAsZExtValue(unsigned NumBits, unsigned BitPosition) const
friend raw_ostream & operator<<(raw_ostream &OS, const DecoderUInt128 &RHS)
bool operator!=(const int &RHS)
void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Context object for machine code objects.
Superclass for all disassemblers.
const MCSubtargetInfo & STI
raw_ostream * CommentStream
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Interface to description of machine instruction set.
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Instances of this class represent operands of the MCInst class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Symbolize and annotate disassembled instructions.
std::unique_ptr< MCRelocationInfo > RelInfo
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef - Represent a constant reference to a string, i.e.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an std::string.
A raw_ostream that writes to an SmallVector or SmallString.
This is an optimization pass for GlobalISel generic memory operations.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Implement std::hash so that hash_code can be used in STL containers.