LLVM 17.0.0git
AMDGPUDisassembler.h
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1//===- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// This file contains declaration for AMDGPU ISA disassembler
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
16#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
17
18#include "llvm/ADT/APInt.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCInst.h"
23#include <memory>
24
25namespace llvm {
26
27class MCInst;
28class MCOperand;
29class MCSubtargetInfo;
30class Twine;
31
32// Exposes an interface expected by autogenerated code in
33// FixedLenDecoderEmitter
35private:
36 uint64_t Lo = 0;
37 uint64_t Hi = 0;
38
39public:
40 DecoderUInt128() = default;
41 DecoderUInt128(uint64_t Lo, uint64_t Hi = 0) : Lo(Lo), Hi(Hi) {}
42 operator bool() const { return Lo || Hi; }
43 void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits) {
44 assert(NumBits && NumBits <= 64);
45 assert(SubBits >> 1 >> (NumBits - 1) == 0);
46 assert(BitPosition < 128);
47 if (BitPosition < 64) {
48 Lo |= SubBits << BitPosition;
49 Hi |= SubBits >> 1 >> (63 - BitPosition);
50 } else {
51 Hi |= SubBits << (BitPosition - 64);
52 }
53 }
55 unsigned BitPosition) const {
56 assert(NumBits && NumBits <= 64);
57 assert(BitPosition < 128);
58 uint64_t Val;
59 if (BitPosition < 64)
60 Val = Lo >> BitPosition | Hi << 1 << (63 - BitPosition);
61 else
62 Val = Hi >> (BitPosition - 64);
63 return Val & ((uint64_t(2) << (NumBits - 1)) - 1);
64 }
66 return DecoderUInt128(Lo & RHS.Lo, Hi & RHS.Hi);
67 }
69 return *this & DecoderUInt128(RHS);
70 }
71 DecoderUInt128 operator~() const { return DecoderUInt128(~Lo, ~Hi); }
73 return Lo == RHS.Lo && Hi == RHS.Hi;
74 }
76 return Lo != RHS.Lo || Hi != RHS.Hi;
77 }
78 bool operator!=(const int &RHS) {
79 return *this != DecoderUInt128(RHS);
80 }
82 return OS << APInt(128, {RHS.Lo, RHS.Hi});
83 }
84};
85
86//===----------------------------------------------------------------------===//
87// AMDGPUDisassembler
88//===----------------------------------------------------------------------===//
89
91private:
92 std::unique_ptr<MCInstrInfo const> const MCII;
93 const MCRegisterInfo &MRI;
94 const unsigned TargetMaxInstBytes;
95 mutable ArrayRef<uint8_t> Bytes;
96 mutable uint32_t Literal;
97 mutable bool HasLiteral;
98
99public:
101 MCInstrInfo const *MCII);
102 ~AMDGPUDisassembler() override = default;
103
106 raw_ostream &CS) const override;
107
108 const char* getRegClassName(unsigned RegClassID) const;
109
110 MCOperand createRegOperand(unsigned int RegId) const;
111 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
112 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
113
114 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
115
116 template <typename InsnType>
117 DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst,
118 uint64_t Address) const {
119 assert(MI.getOpcode() == 0);
120 assert(MI.getNumOperands() == 0);
121 MCInst TmpInst;
122 HasLiteral = false;
123 const auto SavedBytes = Bytes;
124 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
125 MI = TmpInst;
127 }
128 Bytes = SavedBytes;
130 }
131
132 std::optional<DecodeStatus>
134 uint64_t Address, raw_ostream &CStream) const override;
135
137 uint64_t KdAddress) const;
138
141 ArrayRef<uint8_t> Bytes,
142 raw_string_ostream &KdStream) const;
143
144 /// Decode as directives that handle COMPUTE_PGM_RSRC1.
145 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC1.
146 /// \param KdStream - Stream to write the disassembled directives to.
147 // NOLINTNEXTLINE(readability-identifier-naming)
149 raw_string_ostream &KdStream) const;
150
151 /// Decode as directives that handle COMPUTE_PGM_RSRC2.
152 /// \param FourByteBuffer - Bytes holding contents of COMPUTE_PGM_RSRC2.
153 /// \param KdStream - Stream to write the disassembled directives to.
154 // NOLINTNEXTLINE(readability-identifier-naming)
156 raw_string_ostream &KdStream) const;
157
160 DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const;
167 void convertMacDPPInst(MCInst &MI) const;
168
187 };
188
189 unsigned getVgprClassId(const OpWidthTy Width) const;
190 unsigned getAgprClassId(const OpWidthTy Width) const;
191 unsigned getSgprClassId(const OpWidthTy Width) const;
192 unsigned getTtmpClassId(const OpWidthTy Width) const;
193
194 static MCOperand decodeIntImmed(unsigned Imm);
195 static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm);
196
197 MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const;
199
200 MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val,
201 bool MandatoryLiteral = false,
202 unsigned ImmWidth = 0) const;
203
204 MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const;
205 MCOperand decodeSpecialReg32(unsigned Val) const;
206 MCOperand decodeSpecialReg64(unsigned Val) const;
207
208 MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val,
209 unsigned ImmWidth = 0) const;
210 MCOperand decodeSDWASrc16(unsigned Val) const;
211 MCOperand decodeSDWASrc32(unsigned Val) const;
212 MCOperand decodeSDWAVopcDst(unsigned Val) const;
213
214 MCOperand decodeBoolReg(unsigned Val) const;
215
216 int getTTmpIdx(unsigned Val) const;
217
218 const MCInstrInfo *getMCII() const { return MCII.get(); }
219
220 bool isVI() const;
221 bool isGFX9() const;
222 bool isGFX90A() const;
223 bool isGFX9Plus() const;
224 bool isGFX10() const;
225 bool isGFX10Plus() const;
226 bool isGFX11() const;
227 bool isGFX11Plus() const;
228
229 bool hasArchitectedFlatScratch() const;
230
231 bool isMacDPP(MCInst &MI) const;
232};
233
234//===----------------------------------------------------------------------===//
235// AMDGPUSymbolizer
236//===----------------------------------------------------------------------===//
237
239private:
240 void *DisInfo;
241 std::vector<uint64_t> ReferencedAddresses;
242
243public:
244 AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr<MCRelocationInfo> &&RelInfo,
245 void *disInfo)
246 : MCSymbolizer(Ctx, std::move(RelInfo)), DisInfo(disInfo) {}
247
248 bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream,
249 int64_t Value, uint64_t Address, bool IsBranch,
250 uint64_t Offset, uint64_t OpSize,
251 uint64_t InstSize) override;
252
254 int64_t Value,
255 uint64_t Address) override;
256
258 return ReferencedAddresses;
259 }
260};
261
262} // end namespace llvm
263
264#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
MCDisassembler::DecodeStatus DecodeStatus
This file implements a class to represent arbitrary precision integral constant values and operations...
uint64_t Size
IRTranslator LLVM IR MI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
Value * RHS
const MCInstrInfo * getMCII() const
static MCOperand decodeFPImmed(unsigned ImmWidth, unsigned Imm)
MCOperand createRegOperand(unsigned int RegId) const
MCOperand decodeSpecialReg64(unsigned Val) const
const char * getRegClassName(unsigned RegClassID) const
MCOperand decodeLiteralConstant() const
DecodeStatus convertFMAanyK(MCInst &MI, int ImmLitIdx) const
unsigned getVgprClassId(const OpWidthTy Width) const
unsigned getAgprClassId(const OpWidthTy Width) const
MCOperand decodeSDWASrc32(unsigned Val) const
DecodeStatus decodeKernelDescriptorDirective(DataExtractor::Cursor &Cursor, ArrayRef< uint8_t > Bytes, raw_string_ostream &KdStream) const
DecodeStatus convertSDWAInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC2(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC2.
void convertMacDPPInst(MCInst &MI) const
MCOperand decodeVOPDDstYOp(MCInst &Inst, unsigned Val) const
MCOperand decodeBoolReg(unsigned Val) const
MCOperand errOperand(unsigned V, const Twine &ErrMsg) const
DecodeStatus convertVOP3DPPInst(MCInst &MI) const
DecodeStatus decodeCOMPUTE_PGM_RSRC1(uint32_t FourByteBuffer, raw_string_ostream &KdStream) const
Decode as directives that handle COMPUTE_PGM_RSRC1.
MCOperand decodeMandatoryLiteralConstant(unsigned Imm) const
MCOperand decodeSpecialReg32(unsigned Val) const
MCOperand decodeSrcOp(const OpWidthTy Width, unsigned Val, bool MandatoryLiteral=false, unsigned ImmWidth=0) const
MCOperand decodeSDWAVopcDst(unsigned Val) const
~AMDGPUDisassembler() override=default
DecodeStatus convertMIMGInst(MCInst &MI) const
DecodeStatus convertVINTERPInst(MCInst &MI) const
DecodeStatus convertDPP8Inst(MCInst &MI) const
unsigned getSgprClassId(const OpWidthTy Width) const
static MCOperand decodeIntImmed(unsigned Imm)
DecodeStatus convertEXPInst(MCInst &MI) const
DecodeStatus tryDecodeInst(const uint8_t *Table, MCInst &MI, InsnType Inst, uint64_t Address) const
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CS) const override
Returns the disassembly of a single instruction.
unsigned getTtmpClassId(const OpWidthTy Width) const
std::optional< DecodeStatus > onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef< uint8_t > Bytes, uint64_t Address, raw_ostream &CStream) const override
Used to perform separate target specific disassembly for a particular symbol.
bool isMacDPP(MCInst &MI) const
int getTTmpIdx(unsigned Val) const
MCOperand decodeSDWASrc(const OpWidthTy Width, unsigned Val, unsigned ImmWidth=0) const
DecodeStatus convertVOP3PDPPInst(MCInst &MI) const
DecodeStatus convertVOPCDPPInst(MCInst &MI) const
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const
DecodeStatus decodeKernelDescriptor(StringRef KdName, ArrayRef< uint8_t > Bytes, uint64_t KdAddress) const
MCOperand decodeSDWASrc16(unsigned Val) const
ArrayRef< uint64_t > getReferencedAddresses() const override
Get the MCSymbolizer's list of addresses that were referenced by symbolizable operands but not resolv...
bool tryAddingSymbolicOperand(MCInst &Inst, raw_ostream &cStream, int64_t Value, uint64_t Address, bool IsBranch, uint64_t Offset, uint64_t OpSize, uint64_t InstSize) override
Try to add a symbolic operand instead of Value to the MCInst.
AMDGPUSymbolizer(MCContext &Ctx, std::unique_ptr< MCRelocationInfo > &&RelInfo, void *disInfo)
void tryAddingPcLoadReferenceComment(raw_ostream &cStream, int64_t Value, uint64_t Address) override
Try to add a comment on the PC-relative load.
Class for arbitrary precision integers.
Definition: APInt.h:75
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A class representing a position in a DataExtractor, as well as any error encountered during extractio...
Definition: DataExtractor.h:54
bool operator==(const DecoderUInt128 &RHS)
DecoderUInt128 operator~() const
bool operator!=(const DecoderUInt128 &RHS)
DecoderUInt128 operator&(const uint64_t &RHS) const
DecoderUInt128 operator&(const DecoderUInt128 &RHS) const
DecoderUInt128(uint64_t Lo, uint64_t Hi=0)
DecoderUInt128()=default
uint64_t extractBitsAsZExtValue(unsigned NumBits, unsigned BitPosition) const
friend raw_ostream & operator<<(raw_ostream &OS, const DecoderUInt128 &RHS)
bool operator!=(const int &RHS)
void insertBits(uint64_t SubBits, unsigned BitPosition, unsigned NumBits)
Context object for machine code objects.
Definition: MCContext.h:76
Superclass for all disassemblers.
const MCSubtargetInfo & STI
DecodeStatus
Ternary decode status.
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
Symbolize and annotate disassembled instructions.
Definition: MCSymbolizer.h:39
std::unique_ptr< MCRelocationInfo > RelInfo
Definition: MCSymbolizer.h:42
MCContext & Ctx
Definition: MCSymbolizer.h:41
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:642
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:406
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1946
Definition: BitVector.h:858