LLVM  15.0.0git
AMDGPUAsmUtils.cpp
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1 //===-- AMDGPUAsmUtils.cpp - AsmParser/InstPrinter common -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 #include "AMDGPUAsmUtils.h"
9 #include "AMDGPUBaseInfo.h"
10 #include "SIDefines.h"
11 
12 namespace llvm {
13 namespace AMDGPU {
14 
15 namespace DepCtr {
16 
17 // NOLINTBEGIN
19  // Name max dflt offset width constraint
20  {{"depctr_hold_cnt"}, 1, 1, 7, 1, isGFX10_BEncoding},
21  {{"depctr_sa_sdst"}, 1, 1, 0, 1},
22  {{"depctr_va_vdst"}, 15, 15, 12, 4},
23  {{"depctr_va_sdst"}, 7, 7, 9, 3},
24  {{"depctr_va_ssrc"}, 1, 1, 8, 1},
25  {{"depctr_va_vcc"}, 1, 1, 1, 1},
26  {{"depctr_vm_vsrc"}, 7, 7, 2, 3},
27 };
28 // NOLINTEND
29 
30 const int DEP_CTR_SIZE =
31  static_cast<int>(sizeof(DepCtrInfo) / sizeof(CustomOperandVal));
32 
33 } // namespace DepCtr
34 
35 namespace SendMsg {
36 
37 // Disable lint checking for this block since it makes the table unreadable.
38 // NOLINTBEGIN
40  {{""}},
41  {{"MSG_INTERRUPT"}, ID_INTERRUPT},
42  {{"MSG_GS"}, ID_GS_PreGFX11, isNotGFX11Plus},
43  {{"MSG_GS_DONE"}, ID_GS_DONE_PreGFX11, isNotGFX11Plus},
44  {{"MSG_SAVEWAVE"}, ID_SAVEWAVE, isGFX8_GFX9_GFX10},
45  {{"MSG_STALL_WAVE_GEN"}, ID_STALL_WAVE_GEN, isGFX9Plus},
46  {{"MSG_HALT_WAVES"}, ID_HALT_WAVES, isGFX9Plus},
47  {{"MSG_ORDERED_PS_DONE"}, ID_ORDERED_PS_DONE, isGFX9Plus},
48  {{"MSG_EARLY_PRIM_DEALLOC"}, ID_EARLY_PRIM_DEALLOC, isGFX9_GFX10},
49  {{"MSG_GS_ALLOC_REQ"}, ID_GS_ALLOC_REQ, isGFX9Plus},
50  {{"MSG_GET_DOORBELL"}, ID_GET_DOORBELL, isGFX9_GFX10},
51  {{"MSG_GET_DDID"}, ID_GET_DDID, isGFX10},
52  {{"MSG_HS_TESSFACTOR"}, ID_HS_TESSFACTOR_GFX11Plus, isGFX11Plus},
53  {{"MSG_DEALLOC_VGPRS"}, ID_DEALLOC_VGPRS_GFX11Plus, isGFX11Plus},
54  {{""}},
55  {{"MSG_SYSMSG"}, ID_SYSMSG},
56  {{"MSG_RTN_GET_DOORBELL"}, ID_RTN_GET_DOORBELL, isGFX11Plus},
57  {{"MSG_RTN_GET_DDID"}, ID_RTN_GET_DDID, isGFX11Plus},
58  {{"MSG_RTN_GET_TMA"}, ID_RTN_GET_TMA, isGFX11Plus},
59  {{"MSG_RTN_GET_REALTIME"}, ID_RTN_GET_REALTIME, isGFX11Plus},
60  {{"MSG_RTN_SAVE_WAVE"}, ID_RTN_SAVE_WAVE, isGFX11Plus},
61  {{"MSG_RTN_GET_TBA"}, ID_RTN_GET_TBA, isGFX11Plus},
62 };
63 // NOLINTEND
64 
65 const int MSG_SIZE = static_cast<int>(
67 
68 // These two must be in sync with llvm::AMDGPU::SendMsg::Op enum members, see SIDefines.h.
69 const char *const OpSysSymbolic[OP_SYS_LAST_] = {
70  nullptr,
71  "SYSMSG_OP_ECC_ERR_INTERRUPT",
72  "SYSMSG_OP_REG_RD",
73  "SYSMSG_OP_HOST_TRAP_ACK",
74  "SYSMSG_OP_TTRACE_PC"
75 };
76 
77 const char *const OpGsSymbolic[OP_GS_LAST_] = {
78  "GS_OP_NOP",
79  "GS_OP_CUT",
80  "GS_OP_EMIT",
81  "GS_OP_EMIT_CUT"
82 };
83 
84 } // namespace SendMsg
85 
86 namespace Hwreg {
87 
88 // Disable lint checking for this block since it makes the table unreadable.
89 // NOLINTBEGIN
91  {{""}},
92  {{"HW_REG_MODE"}, ID_MODE},
93  {{"HW_REG_STATUS"}, ID_STATUS},
94  {{"HW_REG_TRAPSTS"}, ID_TRAPSTS},
95  {{"HW_REG_HW_ID"}, ID_HW_ID, isNotGFX10Plus},
96  {{"HW_REG_GPR_ALLOC"}, ID_GPR_ALLOC},
97  {{"HW_REG_LDS_ALLOC"}, ID_LDS_ALLOC},
98  {{"HW_REG_IB_STS"}, ID_IB_STS},
99  {{""}},
100  {{""}},
101  {{""}},
102  {{""}},
103  {{""}},
104  {{""}},
105  {{""}},
106  {{"HW_REG_SH_MEM_BASES"}, ID_MEM_BASES, isGFX9Plus},
107  {{"HW_REG_TBA_LO"}, ID_TBA_LO, isGFX9_GFX10},
108  {{"HW_REG_TBA_HI"}, ID_TBA_HI, isGFX9_GFX10},
109  {{"HW_REG_TMA_LO"}, ID_TMA_LO, isGFX9_GFX10},
110  {{"HW_REG_TMA_HI"}, ID_TMA_HI, isGFX9_GFX10},
111  {{"HW_REG_FLAT_SCR_LO"}, ID_FLAT_SCR_LO, isGFX10Plus},
112  {{"HW_REG_FLAT_SCR_HI"}, ID_FLAT_SCR_HI, isGFX10Plus},
113  {{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK, isGFX10Before1030},
114  {{"HW_REG_HW_ID1"}, ID_HW_ID1, isGFX10Plus},
115  {{"HW_REG_HW_ID2"}, ID_HW_ID2, isGFX10Plus},
116  {{"HW_REG_POPS_PACKER"}, ID_POPS_PACKER, isGFX10},
117  {{""}},
118  {{""}},
119  {{""}},
120  {{"HW_REG_SHADER_CYCLES"}, ID_SHADER_CYCLES, isGFX10_BEncoding},
121 
122  // GFX940 specific registers
123  {{"HW_REG_XCC_ID"}, ID_XCC_ID, isGFX940},
124  {{"HW_REG_SQ_PERF_SNAPSHOT_DATA"}, ID_SQ_PERF_SNAPSHOT_DATA, isGFX940},
125  {{"HW_REG_SQ_PERF_SNAPSHOT_DATA1"}, ID_SQ_PERF_SNAPSHOT_DATA1, isGFX940},
126  {{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940},
127  {{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940},
128 
129  // Aliases
130  {{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10},
131 };
132 // NOLINTEND
133 
134 const int OPR_SIZE = static_cast<int>(
135  sizeof(Opr) / sizeof(CustomOperand<const MCSubtargetInfo &>));
136 
137 } // namespace Hwreg
138 
139 namespace MTBUFFormat {
140 
142  "BUF_DATA_FORMAT_INVALID",
143  "BUF_DATA_FORMAT_8",
144  "BUF_DATA_FORMAT_16",
145  "BUF_DATA_FORMAT_8_8",
146  "BUF_DATA_FORMAT_32",
147  "BUF_DATA_FORMAT_16_16",
148  "BUF_DATA_FORMAT_10_11_11",
149  "BUF_DATA_FORMAT_11_11_10",
150  "BUF_DATA_FORMAT_10_10_10_2",
151  "BUF_DATA_FORMAT_2_10_10_10",
152  "BUF_DATA_FORMAT_8_8_8_8",
153  "BUF_DATA_FORMAT_32_32",
154  "BUF_DATA_FORMAT_16_16_16_16",
155  "BUF_DATA_FORMAT_32_32_32",
156  "BUF_DATA_FORMAT_32_32_32_32",
157  "BUF_DATA_FORMAT_RESERVED_15"
158 };
159 
161  "BUF_NUM_FORMAT_UNORM",
162  "BUF_NUM_FORMAT_SNORM",
163  "BUF_NUM_FORMAT_USCALED",
164  "BUF_NUM_FORMAT_SSCALED",
165  "BUF_NUM_FORMAT_UINT",
166  "BUF_NUM_FORMAT_SINT",
167  "",
168  "BUF_NUM_FORMAT_FLOAT"
169 };
170 
172  "BUF_NUM_FORMAT_UNORM",
173  "BUF_NUM_FORMAT_SNORM",
174  "BUF_NUM_FORMAT_USCALED",
175  "BUF_NUM_FORMAT_SSCALED",
176  "BUF_NUM_FORMAT_UINT",
177  "BUF_NUM_FORMAT_SINT",
178  "BUF_NUM_FORMAT_SNORM_OGL",
179  "BUF_NUM_FORMAT_FLOAT"
180 };
181 
182 StringLiteral const NfmtSymbolicVI[] = { // VI and GFX9
183  "BUF_NUM_FORMAT_UNORM",
184  "BUF_NUM_FORMAT_SNORM",
185  "BUF_NUM_FORMAT_USCALED",
186  "BUF_NUM_FORMAT_SSCALED",
187  "BUF_NUM_FORMAT_UINT",
188  "BUF_NUM_FORMAT_SINT",
189  "BUF_NUM_FORMAT_RESERVED_6",
190  "BUF_NUM_FORMAT_FLOAT"
191 };
192 
194  "BUF_FMT_INVALID",
195 
196  "BUF_FMT_8_UNORM",
197  "BUF_FMT_8_SNORM",
198  "BUF_FMT_8_USCALED",
199  "BUF_FMT_8_SSCALED",
200  "BUF_FMT_8_UINT",
201  "BUF_FMT_8_SINT",
202 
203  "BUF_FMT_16_UNORM",
204  "BUF_FMT_16_SNORM",
205  "BUF_FMT_16_USCALED",
206  "BUF_FMT_16_SSCALED",
207  "BUF_FMT_16_UINT",
208  "BUF_FMT_16_SINT",
209  "BUF_FMT_16_FLOAT",
210 
211  "BUF_FMT_8_8_UNORM",
212  "BUF_FMT_8_8_SNORM",
213  "BUF_FMT_8_8_USCALED",
214  "BUF_FMT_8_8_SSCALED",
215  "BUF_FMT_8_8_UINT",
216  "BUF_FMT_8_8_SINT",
217 
218  "BUF_FMT_32_UINT",
219  "BUF_FMT_32_SINT",
220  "BUF_FMT_32_FLOAT",
221 
222  "BUF_FMT_16_16_UNORM",
223  "BUF_FMT_16_16_SNORM",
224  "BUF_FMT_16_16_USCALED",
225  "BUF_FMT_16_16_SSCALED",
226  "BUF_FMT_16_16_UINT",
227  "BUF_FMT_16_16_SINT",
228  "BUF_FMT_16_16_FLOAT",
229 
230  "BUF_FMT_10_11_11_UNORM",
231  "BUF_FMT_10_11_11_SNORM",
232  "BUF_FMT_10_11_11_USCALED",
233  "BUF_FMT_10_11_11_SSCALED",
234  "BUF_FMT_10_11_11_UINT",
235  "BUF_FMT_10_11_11_SINT",
236  "BUF_FMT_10_11_11_FLOAT",
237 
238  "BUF_FMT_11_11_10_UNORM",
239  "BUF_FMT_11_11_10_SNORM",
240  "BUF_FMT_11_11_10_USCALED",
241  "BUF_FMT_11_11_10_SSCALED",
242  "BUF_FMT_11_11_10_UINT",
243  "BUF_FMT_11_11_10_SINT",
244  "BUF_FMT_11_11_10_FLOAT",
245 
246  "BUF_FMT_10_10_10_2_UNORM",
247  "BUF_FMT_10_10_10_2_SNORM",
248  "BUF_FMT_10_10_10_2_USCALED",
249  "BUF_FMT_10_10_10_2_SSCALED",
250  "BUF_FMT_10_10_10_2_UINT",
251  "BUF_FMT_10_10_10_2_SINT",
252 
253  "BUF_FMT_2_10_10_10_UNORM",
254  "BUF_FMT_2_10_10_10_SNORM",
255  "BUF_FMT_2_10_10_10_USCALED",
256  "BUF_FMT_2_10_10_10_SSCALED",
257  "BUF_FMT_2_10_10_10_UINT",
258  "BUF_FMT_2_10_10_10_SINT",
259 
260  "BUF_FMT_8_8_8_8_UNORM",
261  "BUF_FMT_8_8_8_8_SNORM",
262  "BUF_FMT_8_8_8_8_USCALED",
263  "BUF_FMT_8_8_8_8_SSCALED",
264  "BUF_FMT_8_8_8_8_UINT",
265  "BUF_FMT_8_8_8_8_SINT",
266 
267  "BUF_FMT_32_32_UINT",
268  "BUF_FMT_32_32_SINT",
269  "BUF_FMT_32_32_FLOAT",
270 
271  "BUF_FMT_16_16_16_16_UNORM",
272  "BUF_FMT_16_16_16_16_SNORM",
273  "BUF_FMT_16_16_16_16_USCALED",
274  "BUF_FMT_16_16_16_16_SSCALED",
275  "BUF_FMT_16_16_16_16_UINT",
276  "BUF_FMT_16_16_16_16_SINT",
277  "BUF_FMT_16_16_16_16_FLOAT",
278 
279  "BUF_FMT_32_32_32_UINT",
280  "BUF_FMT_32_32_32_SINT",
281  "BUF_FMT_32_32_32_FLOAT",
282  "BUF_FMT_32_32_32_32_UINT",
283  "BUF_FMT_32_32_32_32_SINT",
284  "BUF_FMT_32_32_32_32_FLOAT"
285 };
286 
287 unsigned const DfmtNfmt2UFmtGFX10[] = {
289 
294  DFMT_8 | (NFMT_UINT << NFMT_SHIFT),
295  DFMT_8 | (NFMT_SINT << NFMT_SHIFT),
296 
304 
311 
315 
323 
331 
339 
346 
353 
360 
364 
372 
379 };
380 
382  "BUF_FMT_INVALID",
383 
384  "BUF_FMT_8_UNORM",
385  "BUF_FMT_8_SNORM",
386  "BUF_FMT_8_USCALED",
387  "BUF_FMT_8_SSCALED",
388  "BUF_FMT_8_UINT",
389  "BUF_FMT_8_SINT",
390 
391  "BUF_FMT_16_UNORM",
392  "BUF_FMT_16_SNORM",
393  "BUF_FMT_16_USCALED",
394  "BUF_FMT_16_SSCALED",
395  "BUF_FMT_16_UINT",
396  "BUF_FMT_16_SINT",
397  "BUF_FMT_16_FLOAT",
398 
399  "BUF_FMT_8_8_UNORM",
400  "BUF_FMT_8_8_SNORM",
401  "BUF_FMT_8_8_USCALED",
402  "BUF_FMT_8_8_SSCALED",
403  "BUF_FMT_8_8_UINT",
404  "BUF_FMT_8_8_SINT",
405 
406  "BUF_FMT_32_UINT",
407  "BUF_FMT_32_SINT",
408  "BUF_FMT_32_FLOAT",
409 
410  "BUF_FMT_16_16_UNORM",
411  "BUF_FMT_16_16_SNORM",
412  "BUF_FMT_16_16_USCALED",
413  "BUF_FMT_16_16_SSCALED",
414  "BUF_FMT_16_16_UINT",
415  "BUF_FMT_16_16_SINT",
416  "BUF_FMT_16_16_FLOAT",
417 
418  "BUF_FMT_10_11_11_FLOAT",
419 
420  "BUF_FMT_11_11_10_FLOAT",
421 
422  "BUF_FMT_10_10_10_2_UNORM",
423  "BUF_FMT_10_10_10_2_SNORM",
424  "BUF_FMT_10_10_10_2_UINT",
425  "BUF_FMT_10_10_10_2_SINT",
426 
427  "BUF_FMT_2_10_10_10_UNORM",
428  "BUF_FMT_2_10_10_10_SNORM",
429  "BUF_FMT_2_10_10_10_USCALED",
430  "BUF_FMT_2_10_10_10_SSCALED",
431  "BUF_FMT_2_10_10_10_UINT",
432  "BUF_FMT_2_10_10_10_SINT",
433 
434  "BUF_FMT_8_8_8_8_UNORM",
435  "BUF_FMT_8_8_8_8_SNORM",
436  "BUF_FMT_8_8_8_8_USCALED",
437  "BUF_FMT_8_8_8_8_SSCALED",
438  "BUF_FMT_8_8_8_8_UINT",
439  "BUF_FMT_8_8_8_8_SINT",
440 
441  "BUF_FMT_32_32_UINT",
442  "BUF_FMT_32_32_SINT",
443  "BUF_FMT_32_32_FLOAT",
444 
445  "BUF_FMT_16_16_16_16_UNORM",
446  "BUF_FMT_16_16_16_16_SNORM",
447  "BUF_FMT_16_16_16_16_USCALED",
448  "BUF_FMT_16_16_16_16_SSCALED",
449  "BUF_FMT_16_16_16_16_UINT",
450  "BUF_FMT_16_16_16_16_SINT",
451  "BUF_FMT_16_16_16_16_FLOAT",
452 
453  "BUF_FMT_32_32_32_UINT",
454  "BUF_FMT_32_32_32_SINT",
455  "BUF_FMT_32_32_32_FLOAT",
456  "BUF_FMT_32_32_32_32_UINT",
457  "BUF_FMT_32_32_32_32_SINT",
458  "BUF_FMT_32_32_32_32_FLOAT"
459 };
460 
461 unsigned const DfmtNfmt2UFmtGFX11[] = {
463 
468  DFMT_8 | (NFMT_UINT << NFMT_SHIFT),
469  DFMT_8 | (NFMT_SINT << NFMT_SHIFT),
470 
478 
485 
489 
497 
499 
501 
506 
513 
520 
524 
532 
539 };
540 
541 } // namespace MTBUFFormat
542 
543 namespace Swizzle {
544 
545 // This must be in sync with llvm::AMDGPU::Swizzle::Id enum members, see SIDefines.h.
546 const char* const IdSymbolic[] = {
547  "QUAD_PERM",
548  "BITMASK_PERM",
549  "SWAP",
550  "REVERSE",
551  "BROADCAST",
552 };
553 
554 } // namespace Swizzle
555 
556 namespace VGPRIndexMode {
557 
558 // This must be in sync with llvm::AMDGPU::VGPRIndexMode::Id enum members, see SIDefines.h.
559 const char* const IdSymbolic[] = {
560  "SRC0",
561  "SRC1",
562  "SRC2",
563  "DST",
564 };
565 
566 } // namespace VGPRIndexMode
567 
568 } // namespace AMDGPU
569 } // namespace llvm
llvm::AMDGPU::Hwreg::OPR_SIZE
const int OPR_SIZE
Definition: AMDGPUAsmUtils.cpp:134
llvm::AMDGPU::SendMsg::ID_RTN_GET_DDID
@ ID_RTN_GET_DDID
Definition: SIDefines.h:335
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::AMDGPU::SendMsg::ID_RTN_GET_DOORBELL
@ ID_RTN_GET_DOORBELL
Definition: SIDefines.h:334
llvm::AMDGPU::MTBUFFormat::DFMT_2_10_10_10
@ DFMT_2_10_10_10
Definition: SIDefines.h:476
llvm::AMDGPU::isGFX11Plus
bool isGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1738
llvm::AMDGPU::MTBUFFormat::DFMT_32
@ DFMT_32
Definition: SIDefines.h:471
llvm::AMDGPU::MTBUFFormat::DFMT_8_8
@ DFMT_8_8
Definition: SIDefines.h:470
llvm::AMDGPU::SendMsg::OpGsSymbolic
const char *const OpGsSymbolic[OP_GS_LAST_]
Definition: AMDGPUAsmUtils.cpp:77
llvm::AMDGPU::Hwreg::ID_LDS_ALLOC
@ ID_LDS_ALLOC
Definition: SIDefines.h:388
llvm::AMDGPU::MTBUFFormat::DFMT_10_10_10_2
@ DFMT_10_10_10_2
Definition: SIDefines.h:475
llvm::AMDGPU::SendMsg::ID_STALL_WAVE_GEN
@ ID_STALL_WAVE_GEN
Definition: SIDefines.h:325
llvm::AMDGPU::isGFX10_BEncoding
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1762
llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32
@ DFMT_32_32_32
Definition: SIDefines.h:480
llvm::AMDGPU::MTBUFFormat::DFMT_8
@ DFMT_8
Definition: SIDefines.h:468
llvm::AMDGPU::SendMsg::OpSysSymbolic
const char *const OpSysSymbolic[OP_SYS_LAST_]
Definition: AMDGPUAsmUtils.cpp:69
llvm::AMDGPU::SendMsg::OP_GS_LAST_
@ OP_GS_LAST_
Definition: SIDefines.h:357
llvm::AMDGPU::SendMsg::ID_HS_TESSFACTOR_GFX11Plus
@ ID_HS_TESSFACTOR_GFX11Plus
Definition: SIDefines.h:321
llvm::AMDGPU::MTBUFFormat::DFMT_11_11_10
@ DFMT_11_11_10
Definition: SIDefines.h:474
llvm::AMDGPU::isGFX10
bool isGFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1726
llvm::AMDGPU::SendMsg::ID_EARLY_PRIM_DEALLOC
@ ID_EARLY_PRIM_DEALLOC
Definition: SIDefines.h:328
llvm::AMDGPU::VGPRIndexMode::IdSymbolic
const char *const IdSymbolic[]
Definition: AMDGPUAsmUtils.cpp:559
llvm::AMDGPU::MTBUFFormat::NFMT_SNORM
@ NFMT_SNORM
Definition: SIDefines.h:496
llvm::AMDGPU::Hwreg::ID_HW_ID1
@ ID_HW_ID1
Definition: SIDefines.h:403
AMDGPUAsmUtils.h
Swizzle
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
Definition: R600InstrInfo.cpp:350
llvm::AMDGPU::SendMsg::MSG_SIZE
const int MSG_SIZE
Definition: AMDGPUAsmUtils.cpp:65
llvm::AMDGPU::Hwreg::ID_IB_STS
@ ID_IB_STS
Definition: SIDefines.h:389
llvm::AMDGPU::SendMsg::ID_SAVEWAVE
@ ID_SAVEWAVE
Definition: SIDefines.h:324
llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_PC_LO
@ ID_SQ_PERF_SNAPSHOT_PC_LO
Definition: SIDefines.h:398
llvm::AMDGPU::Hwreg::ID_TBA_HI
@ ID_TBA_HI
Definition: SIDefines.h:392
llvm::AMDGPU::SendMsg::ID_DEALLOC_VGPRS_GFX11Plus
@ ID_DEALLOC_VGPRS_GFX11Plus
Definition: SIDefines.h:322
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicVI
const StringLiteral NfmtSymbolicVI[]
Definition: AMDGPUAsmUtils.cpp:182
llvm::AMDGPU::SendMsg::ID_GET_DOORBELL
@ ID_GET_DOORBELL
Definition: SIDefines.h:330
llvm::AMDGPU::MTBUFFormat::UfmtSymbolicGFX11
const StringLiteral UfmtSymbolicGFX11[]
Definition: AMDGPUAsmUtils.cpp:381
llvm::StringLiteral
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:914
llvm::AMDGPU::MTBUFFormat::DFMT_32_32_32_32
@ DFMT_32_32_32_32
Definition: SIDefines.h:481
llvm::AMDGPU::SendMsg::ID_RTN_SAVE_WAVE
@ ID_RTN_SAVE_WAVE
Definition: SIDefines.h:338
llvm::AMDGPU::Hwreg::ID_MODE
@ ID_MODE
Definition: SIDefines.h:383
llvm::AMDGPU::SendMsg::OP_SYS_LAST_
@ OP_SYS_LAST_
Definition: SIDefines.h:364
llvm::AMDGPU::SendMsg::ID_GS_ALLOC_REQ
@ ID_GS_ALLOC_REQ
Definition: SIDefines.h:329
llvm::AMDGPU::Hwreg::ID_POPS_PACKER
@ ID_POPS_PACKER
Definition: SIDefines.h:405
llvm::AMDGPU::MTBUFFormat::DfmtSymbolic
const StringLiteral DfmtSymbolic[]
Definition: AMDGPUAsmUtils.cpp:141
llvm::AMDGPU::isGFX940
bool isGFX940(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1774
llvm::AMDGPU::SendMsg::ID_SYSMSG
@ ID_SYSMSG
Definition: SIDefines.h:332
llvm::AMDGPU::MTBUFFormat::DFMT_16_16_16_16
@ DFMT_16_16_16_16
Definition: SIDefines.h:479
llvm::AMDGPU::MTBUFFormat::DFMT_16
@ DFMT_16
Definition: SIDefines.h:469
AMDGPU
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:114
llvm::AMDGPU::MTBUFFormat::DFMT_8_8_8_8
@ DFMT_8_8_8_8
Definition: SIDefines.h:477
llvm::AMDGPU::Hwreg::ID_TBA_LO
@ ID_TBA_LO
Definition: SIDefines.h:391
llvm::AMDGPU::MTBUFFormat::DFMT_INVALID
@ DFMT_INVALID
Definition: SIDefines.h:467
llvm::AMDGPU::Hwreg::ID_TMA_LO
@ ID_TMA_LO
Definition: SIDefines.h:393
llvm::AMDGPU::SendMsg::ID_RTN_GET_REALTIME
@ ID_RTN_GET_REALTIME
Definition: SIDefines.h:337
llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_DATA
@ ID_SQ_PERF_SNAPSHOT_DATA
Definition: SIDefines.h:396
llvm::AMDGPU::isGFX10Plus
bool isGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1730
llvm::AMDGPU::SendMsg::ID_ORDERED_PS_DONE
@ ID_ORDERED_PS_DONE
Definition: SIDefines.h:327
llvm::AMDGPU::DepCtr::DepCtrInfo
const CustomOperandVal DepCtrInfo[]
Definition: AMDGPUAsmUtils.cpp:18
llvm::AMDGPU::Swizzle::IdSymbolic
const char *const IdSymbolic[]
Definition: AMDGPUAsmUtils.cpp:546
llvm::AMDGPU::Hwreg::ID_FLAT_SCR_HI
@ ID_FLAT_SCR_HI
Definition: SIDefines.h:401
llvm::AMDGPU::SendMsg::ID_RTN_GET_TBA
@ ID_RTN_GET_TBA
Definition: SIDefines.h:339
llvm::AMDGPU::MTBUFFormat::DFMT_32_32
@ DFMT_32_32
Definition: SIDefines.h:478
llvm::AMDGPU::Hwreg::ID_HW_ID
@ ID_HW_ID
Definition: SIDefines.h:386
llvm::AMDGPU::SendMsg::ID_INTERRUPT
@ ID_INTERRUPT
Definition: SIDefines.h:316
llvm::AMDGPU::isGFX9_GFX10
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1710
llvm::AMDGPU::Hwreg::ID_MEM_BASES
@ ID_MEM_BASES
Definition: SIDefines.h:390
llvm::AMDGPU::isGFX10Before1030
bool isGFX10Before1030(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1750
llvm::AMDGPU::CustomOperand
Definition: AMDGPUAsmUtils.h:28
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicGFX10
const StringLiteral NfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:160
llvm::AMDGPU::DepCtr::DEP_CTR_SIZE
const int DEP_CTR_SIZE
Definition: AMDGPUAsmUtils.cpp:30
llvm::AMDGPU::Hwreg::ID_XNACK_MASK
@ ID_XNACK_MASK
Definition: SIDefines.h:402
llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_PC_HI
@ ID_SQ_PERF_SNAPSHOT_PC_HI
Definition: SIDefines.h:399
llvm::AMDGPU::isNotGFX10Plus
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1746
llvm::AMDGPU::MTBUFFormat::UfmtSymbolicGFX10
const StringLiteral UfmtSymbolicGFX10[]
Definition: AMDGPUAsmUtils.cpp:193
llvm::AMDGPU::isGFX8_GFX9_GFX10
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1714
llvm::AMDGPU::isGFX9Plus
bool isGFX9Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1722
llvm::AMDGPU::SendMsg::Msg
const CustomOperand< const MCSubtargetInfo & > Msg[]
Definition: AMDGPUAsmUtils.cpp:39
llvm::AMDGPU::MTBUFFormat::NFMT_UINT
@ NFMT_UINT
Definition: SIDefines.h:499
llvm::AMDGPU::Hwreg::ID_SHADER_CYCLES
@ ID_SHADER_CYCLES
Definition: SIDefines.h:406
llvm::AMDGPU::Hwreg::Opr
const CustomOperand< const MCSubtargetInfo & > Opr[]
Definition: AMDGPUAsmUtils.cpp:90
llvm::AMDGPU::MTBUFFormat::DFMT_10_11_11
@ DFMT_10_11_11
Definition: SIDefines.h:473
SIDefines.h
llvm::AMDGPU::MTBUFFormat::NFMT_SSCALED
@ NFMT_SSCALED
Definition: SIDefines.h:498
llvm::AMDGPU::SendMsg::ID_GET_DDID
@ ID_GET_DDID
Definition: SIDefines.h:331
llvm::AMDGPU::MTBUFFormat::NFMT_SINT
@ NFMT_SINT
Definition: SIDefines.h:500
llvm::AMDGPU::Hwreg::ID_GPR_ALLOC
@ ID_GPR_ALLOC
Definition: SIDefines.h:387
llvm::AMDGPU::MTBUFFormat::NfmtSymbolicSICI
const StringLiteral NfmtSymbolicSICI[]
Definition: AMDGPUAsmUtils.cpp:171
llvm::AMDGPU::MTBUFFormat::NFMT_SHIFT
@ NFMT_SHIFT
Definition: SIDefines.h:511
llvm::AMDGPU::MTBUFFormat::NFMT_UNORM
@ NFMT_UNORM
Definition: SIDefines.h:495
llvm::AMDGPU::Hwreg::ID_TMA_HI
@ ID_TMA_HI
Definition: SIDefines.h:394
llvm::AMDGPU::isNotGFX11Plus
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
Definition: AMDGPUBaseInfo.cpp:1742
llvm::AMDGPU::Hwreg::ID_XCC_ID
@ ID_XCC_ID
Definition: SIDefines.h:395
llvm::AMDGPU::SendMsg::ID_GS_DONE_PreGFX11
@ ID_GS_DONE_PreGFX11
Definition: SIDefines.h:319
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmtGFX10
const unsigned DfmtNfmt2UFmtGFX10[]
Definition: AMDGPUAsmUtils.cpp:287
llvm::AMDGPU::Hwreg::ID_STATUS
@ ID_STATUS
Definition: SIDefines.h:384
llvm::AMDGPU::MTBUFFormat::NFMT_FLOAT
@ NFMT_FLOAT
Definition: SIDefines.h:503
llvm::AMDGPU::Hwreg::ID_FLAT_SCR_LO
@ ID_FLAT_SCR_LO
Definition: SIDefines.h:400
llvm::AMDGPU::Hwreg::ID_TRAPSTS
@ ID_TRAPSTS
Definition: SIDefines.h:385
llvm::AMDGPU::SendMsg::ID_RTN_GET_TMA
@ ID_RTN_GET_TMA
Definition: SIDefines.h:336
llvm::AMDGPU::Hwreg::ID_SQ_PERF_SNAPSHOT_DATA1
@ ID_SQ_PERF_SNAPSHOT_DATA1
Definition: SIDefines.h:397
llvm::AMDGPU::MTBUFFormat::DfmtNfmt2UFmtGFX11
const unsigned DfmtNfmt2UFmtGFX11[]
Definition: AMDGPUAsmUtils.cpp:461
llvm::AMDGPU::CustomOperandVal
Definition: AMDGPUAsmUtils.h:34
llvm::AMDGPU::SendMsg::ID_GS_PreGFX11
@ ID_GS_PreGFX11
Definition: SIDefines.h:318
llvm::AMDGPU::SendMsg::ID_HALT_WAVES
@ ID_HALT_WAVES
Definition: SIDefines.h:326
llvm::AMDGPU::MTBUFFormat::NFMT_USCALED
@ NFMT_USCALED
Definition: SIDefines.h:497
llvm::AMDGPU::MTBUFFormat::DFMT_16_16
@ DFMT_16_16
Definition: SIDefines.h:472
AMDGPUBaseInfo.h
llvm::AMDGPU::Hwreg::ID_HW_ID2
@ ID_HW_ID2
Definition: SIDefines.h:404