22 #define GET_INSTRINFO_CTOR_DTOR 23 #include "R600GenDFAPacketizer.inc" 25 #define GET_INSTRINFO_CTOR_DTOR 26 #define GET_INSTRMAP_INFO 27 #define GET_INSTRINFO_NAMED_OPS 28 #include "R600GenInstrInfo.inc" 41 unsigned VectorComponents = 0;
42 if ((R600::R600_Reg128RegClass.
contains(DestReg) ||
43 R600::R600_Reg128VerticalRegClass.
contains(DestReg)) &&
44 (R600::R600_Reg128RegClass.
contains(SrcReg) ||
45 R600::R600_Reg128VerticalRegClass.
contains(SrcReg))) {
47 }
else if((R600::R600_Reg64RegClass.
contains(DestReg) ||
48 R600::R600_Reg64VerticalRegClass.
contains(DestReg)) &&
49 (R600::R600_Reg64RegClass.
contains(SrcReg) ||
50 R600::R600_Reg64VerticalRegClass.
contains(SrcReg))) {
54 if (VectorComponents > 0) {
55 for (
unsigned I = 0;
I < VectorComponents;
I++) {
58 RI.getSubReg(DestReg, SubRegIndex),
59 RI.getSubReg(SrcReg, SubRegIndex))
75 E =
MBBI->operands_end();
I !=
E; ++
I) {
76 if (
I->isReg() && !
I->getReg().isVirtual() &&
I->isUse() &&
88 case R600::MOV_IMM_F32:
89 case R600::MOV_IMM_I32:
100 default:
return false;
101 case R600::CUBE_r600_pseudo:
102 case R600::CUBE_r600_real:
103 case R600::CUBE_eg_pseudo:
104 case R600::CUBE_eg_real:
110 unsigned TargetFlags = get(Opcode).TSFlags;
116 unsigned TargetFlags = get(Opcode).TSFlags;
124 unsigned TargetFlags = get(Opcode).TSFlags;
140 switch (
MI.getOpcode()) {
142 case R600::INTERP_PAIR_XY:
143 case R600::INTERP_PAIR_ZW:
144 case R600::INTERP_VEC_LOAD:
156 return (get(Opcode).getSchedClass() == R600::Sched::TransALU);
164 return (get(Opcode).getSchedClass() == R600::Sched::VecALU);
199 case R600::GROUP_BARRIER:
207 return MI.findRegisterUseOperandIdx(R600::AR_X,
false, &RI) != -1;
211 return MI.findRegisterDefOperandIdx(R600::AR_X,
false,
false, &RI) != -1;
219 E =
MI.operands_end();
221 if (!
I->isReg() || !
I->isUse() ||
I->getReg().isVirtual())
224 if (R600::R600_LDS_SRC_REGRegClass.
contains(
I->getReg()))
231 static const unsigned SrcSelTable[][2] = {
232 {R600::OpName::src0, R600::OpName::src0_sel},
233 {R600::OpName::src1, R600::OpName::src1_sel},
234 {R600::OpName::src2, R600::OpName::src2_sel},
235 {R600::OpName::src0_X, R600::OpName::src0_sel_X},
236 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
237 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
238 {R600::OpName::src0_W, R600::OpName::src0_sel_W},
239 {R600::OpName::src1_X, R600::OpName::src1_sel_X},
240 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
241 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
242 {R600::OpName::src1_W, R600::OpName::src1_sel_W}
245 for (
const auto &Row : SrcSelTable) {
257 if (
MI.getOpcode() == R600::DOT_4) {
258 static const unsigned OpTable[8][2] = {
259 {R600::OpName::src0_X, R600::OpName::src0_sel_X},
260 {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
261 {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
262 {R600::OpName::src0_W, R600::OpName::src0_sel_W},
263 {R600::OpName::src1_X, R600::OpName::src1_sel_X},
264 {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
265 {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
266 {R600::OpName::src1_W, R600::OpName::src1_sel_W},
269 for (
unsigned j = 0; j < 8; j++) {
273 if (
Reg == R600::ALU_CONST) {
276 Result.push_back(std::make_pair(&MO, Sel.
getImm()));
284 static const unsigned OpTable[3][2] = {
285 {R600::OpName::src0, R600::OpName::src0_sel},
286 {R600::OpName::src1, R600::OpName::src1_sel},
287 {R600::OpName::src2, R600::OpName::src2_sel},
290 for (
unsigned j = 0; j < 3; j++) {
296 if (
Reg == R600::ALU_CONST) {
299 Result.push_back(std::make_pair(&MO, Sel.
getImm()));
302 if (
Reg == R600::ALU_LITERAL_X) {
305 if (Operand.
isImm()) {
306 Result.push_back(std::make_pair(&MO, Operand.
getImm()));
311 Result.push_back(std::make_pair(&MO, 0));
316 std::vector<std::pair<int, unsigned>>
319 unsigned &ConstCount)
const {
321 const std::pair<int, unsigned> DummyPair(-1, 0);
322 std::vector<std::pair<int, unsigned>> Result;
327 int Index = RI.getEncodingValue(
Reg) & 0xff;
328 if (
Reg == R600::OQAP) {
329 Result.push_back(std::make_pair(
Index, 0U));
333 Result.push_back(std::make_pair(255, 0U));
338 Result.push_back(DummyPair);
345 Result.push_back(DummyPair);
349 static std::vector<std::pair<int, unsigned>>
352 if (Src[0] == Src[1])
379 assert(
Op < 3 &&
"Out of range swizzle index");
382 unsigned Cycles[3] = { 2, 1, 0};
386 unsigned Cycles[3] = { 1, 2, 2};
390 unsigned Cycles[3] = { 2, 1, 2};
394 unsigned Cycles[3] = { 2, 2, 1};
407 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
408 const std::vector<std::pair<int, unsigned>> &TransSrcs,
412 for (
unsigned i = 0,
e = IGSrcs.size(); i <
e; i++) {
413 const std::vector<std::pair<int, unsigned>> &Srcs =
415 for (
unsigned j = 0; j < 3; j++) {
416 const std::pair<int, unsigned> &Src = Srcs[j];
417 if (Src.first < 0 || Src.first == 255)
419 if (Src.first ==
GET_REG_INDEX(RI.getEncodingValue(R600::OQAP))) {
429 if (
Vector[Src.second][j] < 0)
430 Vector[Src.second][j] = Src.first;
431 if (
Vector[Src.second][j] != Src.first)
436 for (
unsigned i = 0,
e = TransSrcs.size(); i <
e; ++i) {
437 const std::pair<int, unsigned> &Src = TransSrcs[i];
441 if (Src.first == 255)
443 if (
Vector[Src.second][Cycle] < 0)
444 Vector[Src.second][Cycle] = Src.first;
445 if (
Vector[Src.second][Cycle] != Src.first)
446 return IGSrcs.size() - 1;
448 return IGSrcs.size();
456 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
458 assert(Idx < SwzCandidate.size());
462 for (
unsigned i = ResetIdx + 1,
e = SwzCandidate.size(); i <
e; i++) {
467 int NextSwizzle = SwzCandidate[ResetIdx] + 1;
476 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
477 const std::vector<std::pair<int, unsigned>> &TransSrcs,
479 unsigned ValidUpTo = 0;
481 ValidUpTo =
isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
482 if (ValidUpTo == IGSrcs.size())
492 const std::vector<std::pair<int, unsigned>> &TransOps,
493 unsigned ConstCount) {
497 for (
unsigned i = 0,
e = TransOps.size(); i <
e; ++i) {
498 const std::pair<int, unsigned> &Src = TransOps[i];
502 if (ConstCount > 0 && Cycle == 0)
504 if (ConstCount > 1 && Cycle == 1)
513 std::vector<BankSwizzle> &ValidSwizzle,
518 std::vector<std::vector<std::pair<int, unsigned>>> IGSrcs;
519 ValidSwizzle.clear();
522 for (
unsigned i = 0,
e = IG.size(); i <
e; ++i) {
523 IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount));
525 R600::OpName::bank_swizzle);
527 IG[i]->getOperand(
Op).getImm());
529 std::vector<std::pair<int, unsigned>> TransOps;
535 ValidSwizzle.pop_back();
543 for (
unsigned i = 0; i < 4; i++) {
544 TransBS = TransSwz[i];
550 ValidSwizzle.push_back(TransBS);
561 assert (Consts.size() <= 12 &&
"Too many operands in instructions group");
562 unsigned Pair1 = 0, Pair2 = 0;
563 for (
unsigned i = 0, n = Consts.size(); i < n; ++i) {
564 unsigned ReadConstHalf = Consts[i] & 2;
565 unsigned ReadConstIndex = Consts[i] & (~3);
566 unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
568 Pair1 = ReadHalfConst;
571 if (Pair1 == ReadHalfConst)
574 Pair2 = ReadHalfConst;
577 if (Pair2 != ReadHalfConst)
586 std::vector<unsigned> Consts;
588 for (
unsigned i = 0, n = MIs.size(); i < n; i++) {
594 if (Src.first->getReg() == R600::ALU_LITERAL_X)
595 Literals.
insert(Src.second);
596 if (Literals.
size() > 4)
598 if (Src.first->getReg() == R600::ALU_CONST)
599 Consts.push_back(Src.second);
600 if (R600::R600_KC0RegClass.
contains(Src.first->getReg()) ||
601 R600::R600_KC1RegClass.
contains(Src.first->getReg())) {
602 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
604 Consts.push_back((
Index << 2) | Chan);
614 return static_cast<const R600Subtarget &>(STI).createDFAPacketizer(II);
642 return Opcode == R600::JUMP || Opcode == R600::JUMP_COND;
646 return Opcode == R600::BRANCH || Opcode == R600::BRANCH_COND_i32 ||
647 Opcode == R600::BRANCH_COND_f32;
654 bool AllowModify)
const {
671 while (
I !=
MBB.
begin() && std::prev(
I)->getOpcode() == R600::JUMP) {
674 I->removeFromParent();
682 if (LastOpc == R600::JUMP) {
685 }
else if (LastOpc == R600::JUMP_COND) {
691 Cond.push_back(predSet->getOperand(1));
692 Cond.push_back(predSet->getOperand(2));
701 unsigned SecondLastOpc = SecondLastInst.
getOpcode();
704 if (SecondLastOpc == R600::JUMP_COND && LastOpc == R600::JUMP) {
711 Cond.push_back(predSet->getOperand(1));
712 Cond.push_back(predSet->getOperand(2));
725 if (It->getOpcode() == R600::CF_ALU ||
726 It->getOpcode() == R600::CF_ALU_PUSH_BEFORE)
737 int *BytesAdded)
const {
738 assert(TBB &&
"insertBranch must not be told to insert a fallthrough");
739 assert(!BytesAdded &&
"code size not handled");
747 assert(PredSet &&
"No previous predicate !");
757 assert (CfAlu->getOpcode() == R600::CF_ALU);
758 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
763 assert(PredSet &&
"No previous predicate !");
773 assert (CfAlu->getOpcode() == R600::CF_ALU);
774 CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
780 int *BytesRemoved)
const {
781 assert(!BytesRemoved &&
"code size not handled");
792 switch (
I->getOpcode()) {
795 case R600::JUMP_COND: {
798 I->eraseFromParent();
802 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
803 CfAlu->setDesc(get(R600::CF_ALU));
807 I->eraseFromParent();
816 switch (
I->getOpcode()) {
820 case R600::JUMP_COND: {
823 I->eraseFromParent();
827 assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE);
828 CfAlu->setDesc(get(R600::CF_ALU));
832 I->eraseFromParent();
839 int idx =
MI.findFirstPredOperandIdx();
845 default:
return false;
846 case R600::PRED_SEL_ONE:
847 case R600::PRED_SEL_ZERO:
848 case R600::PREDICATE_BIT:
859 if (
MI.getOpcode() == R600::KILLGT) {
861 }
else if (
MI.getOpcode() == R600::CF_ALU) {
867 return MI.getOperand(3).getImm() == 0 &&
MI.getOperand(4).getImm() == 0;
878 unsigned ExtraPredCycles,
886 unsigned ExtraTCycles,
889 unsigned ExtraFCycles,
912 case R600::PRED_SETE_INT:
913 MO.
setImm(R600::PRED_SETNE_INT);
915 case R600::PRED_SETNE_INT:
916 MO.
setImm(R600::PRED_SETE_INT);
918 case R600::PRED_SETE:
919 MO.
setImm(R600::PRED_SETNE);
921 case R600::PRED_SETNE:
922 MO.
setImm(R600::PRED_SETE);
930 case R600::PRED_SEL_ZERO:
931 MO2.
setReg(R600::PRED_SEL_ONE);
933 case R600::PRED_SEL_ONE:
934 MO2.
setReg(R600::PRED_SEL_ZERO);
943 std::vector<MachineOperand> &Pred,
944 bool SkipDead)
const {
950 int PIdx =
MI.findFirstPredOperandIdx();
952 if (
MI.getOpcode() == R600::CF_ALU) {
953 MI.getOperand(8).setImm(0);
957 if (
MI.getOpcode() == R600::DOT_4) {
959 .setReg(Pred[2].
getReg());
961 .setReg(Pred[2].
getReg());
963 .setReg(Pred[2].
getReg());
965 .setReg(Pred[2].
getReg());
988 unsigned *PredCost)
const {
995 unsigned Channel)
const {
1001 switch (
MI.getOpcode()) {
1008 int RegOpIdx = OffsetOpIdx + 1;
1014 unsigned RegIndex =
MI.getOperand(RegOpIdx).getImm();
1015 unsigned Channel =
MI.getOperand(ChanOpIdx).getImm();
1017 Register OffsetReg =
MI.getOperand(OffsetOpIdx).getReg();
1018 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1022 buildIndirectRead(
MBB,
MI,
MI.getOperand(DstOpIdx).getReg(),
Address,
1028 unsigned RegIndex =
MI.getOperand(RegOpIdx).getImm();
1029 unsigned Channel =
MI.getOperand(ChanOpIdx).getImm();
1031 Register OffsetReg =
MI.getOperand(OffsetOpIdx).getReg();
1032 if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
1034 MI.getOperand(ValOpIdx).getReg());
1036 buildIndirectWrite(
MBB,
MI,
MI.getOperand(ValOpIdx).getReg(),
1047 case R600::R600_EXTRACT_ELT_V2:
1048 case R600::R600_EXTRACT_ELT_V4:
1049 buildIndirectRead(
MI.getParent(),
MI,
MI.getOperand(0).getReg(),
1051 MI.getOperand(2).getReg(),
1054 case R600::R600_INSERT_ELT_V2:
1055 case R600::R600_INSERT_ELT_V4:
1056 buildIndirectWrite(
MI.getParent(),
MI,
MI.getOperand(2).getReg(),
1058 MI.getOperand(3).getReg(),
1062 MI.eraseFromParent();
1072 unsigned StackWidth = TFL->getStackWidth(MF);
1079 for (
unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1080 unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 *
Index) + Chan);
1081 TRI.reserveRegisterTuples(Reserved,
Reg);
1087 return &R600::R600_TReg32_XRegClass;
1092 unsigned ValueReg,
unsigned Address,
1093 unsigned OffsetReg)
const {
1094 return buildIndirectWrite(
MBB,
I, ValueReg,
Address, OffsetReg, 0);
1099 unsigned ValueReg,
unsigned Address,
1101 unsigned AddrChan)
const {
1105 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(
Address);
break;
1106 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(
Address);
break;
1107 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(
Address);
break;
1108 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(
Address);
break;
1111 R600::AR_X, OffsetReg);
1124 unsigned ValueReg,
unsigned Address,
1125 unsigned OffsetReg)
const {
1126 return buildIndirectRead(
MBB,
I, ValueReg,
Address, OffsetReg, 0);
1131 unsigned ValueReg,
unsigned Address,
1133 unsigned AddrChan)
const {
1137 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(
Address);
break;
1138 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(
Address);
break;
1139 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(
Address);
break;
1140 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(
Address);
break;
1165 if (
MRI.livein_empty()) {
1170 for (std::pair<unsigned, unsigned> LI :
MRI.liveins()) {
1177 for (RegIndex = 0, RegEnd = IndirectRC->
getNumRegs(); RegIndex != RegEnd;
1205 Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg).getFixed();
1219 unsigned Src1Reg)
const {
1248 .
addReg(R600::PRED_SEL_OFF)
1255 #define OPERAND_CASE(Label) \ 1257 static const unsigned Ops[] = \ 1296 assert (
MI->getOpcode() == R600::DOT_4 &&
"Not Implemented");
1299 Opcode = R600::DOT4_r600;
1301 Opcode = R600::DOT4_eg;
1309 static const unsigned Operands[14] = {
1310 R600::OpName::update_exec_mask,
1311 R600::OpName::update_pred,
1314 R600::OpName::dst_rel,
1315 R600::OpName::clamp,
1316 R600::OpName::src0_neg,
1317 R600::OpName::src0_rel,
1318 R600::OpName::src0_abs,
1319 R600::OpName::src0_sel,
1320 R600::OpName::src1_neg,
1321 R600::OpName::src1_rel,
1322 R600::OpName::src1_abs,
1323 R600::OpName::src1_sel,
1331 for (
unsigned i = 0; i < 14; i++) {
1344 uint64_t Imm)
const {
1346 R600::ALU_LITERAL_X);
1353 unsigned DstReg,
unsigned SrcReg)
const {
1366 int64_t Imm)
const {
1368 assert(Idx != -1 &&
"Operand not supported for this instruction.");
1369 assert(
MI.getOperand(Idx).isImm());
1370 MI.getOperand(Idx).setImm(Imm);
1378 unsigned Flag)
const {
1379 unsigned TargetFlags = get(
MI.getOpcode()).TSFlags;
1413 assert(!IsOP3 &&
"Cannot set absolute value modifier for OP3 " 1430 assert(FlagIndex != -1 &&
"Flag not supported for this instruction");
1434 "Instruction flags not supported for this instruction");
1443 unsigned Flag)
const {
1444 unsigned TargetFlags = get(
MI.getOpcode()).TSFlags;
1464 unsigned Flag)
const {
1465 unsigned TargetFlags = get(
MI.getOpcode()).TSFlags;
1471 unsigned InstFlags = FlagOp.
getImm();
1473 FlagOp.
setImm(InstFlags);
1478 unsigned Kind)
const {
bool isMov(unsigned Opcode) const
bool usesAddressRegister(MachineInstr &MI) const
unsigned int getPredicationCost(const MachineInstr &) const override
bool isPhysRegLiveAcrossClauses(Register Reg) const
MCRegister getRegister(unsigned i) const
Return the specified register in the class.
AMDGPU specific subclass of TargetSubtarget.
Wrapper class representing physical registers. Should be passed by value.
MachineBasicBlock * getMBB() const
This class represents lattice values for constants.
unsigned getNumRegs() const
Return the number of registers in this class.
unsigned getNumObjects() const
Return the number of objects.
Interface definition for R600InstrInfo.
Not emitted register (e.g. carry, or temporary result).
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Address space for constant memory (VTX2).
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
static std::vector< std::pair< int, unsigned > > Swizzle(std::vector< std::pair< int, unsigned >> Src, R600InstrInfo::BankSwizzle Swz)
bool isPredicated(const MachineInstr &MI) const override
static unsigned getSlotedOps(unsigned Op, unsigned Slot)
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
bool expandPostRAPseudo(MachineInstr &MI) const override
unsigned const TargetRegisterInfo * TRI
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
MachineInstrBundleIterator< const MachineInstr > const_iterator
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
The last use of a register.
Generation getGeneration() const
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
return AArch64::GPR64RegClass contains(Reg)
Function & getFunction()
Return the LLVM function that this machine code represents.
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
static MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB)
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op)
R600InstrInfo(const R600Subtarget &)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
mir Rename Register Operands
bool isRegisterLoad(const MachineInstr &MI) const
#define HAS_NATIVE_OPERANDS(Flags)
static bool isJump(unsigned Opcode)
bool hasInstrModifiers(unsigned Opcode) const
unsigned getMaxAlusPerClause() const
bool isRegisterStore(const MachineInstr &MI) const
bool contains(Register Reg) const
Return true if the specified register is included in this register class.
bool usesVertexCache(unsigned Opcode) const
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
bool mustBeLastInClause(unsigned Opcode) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
reverse_iterator getReverse() const
Get a reverse iterator to the same node.
Itinerary data supplied by a subtarget to be used by a target.
iterator getLastNonDebugInstr()
Returns an iterator to the last non-debug instruction in the basic block, or end().
void setReg(Register Reg)
Change the register this operand corresponds to.
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
Address space for private memory.
const TargetRegisterClass * getIndirectAddrRegClass() const
reverse_iterator rbegin()
bool isPredicable(const MachineInstr &MI) const override
virtual const InstrItineraryData * getInstrItineraryData() const
getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.
bool isExport(unsigned Opcode) const
Flag
These should be considered private to the implementation of the MCInstrDesc class.
iterator find(const_arg_type_t< KeyT > Val)
unsigned getHWRegIndex(unsigned Reg) const
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const override
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isCompute(CallingConv::ID cc)
unsigned const MachineRegisterInfo * MRI
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
DebugLoc findDebugLoc(instr_iterator MBBI)
Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE and DBG_LABEL instructions.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
bool isLDSInstr(unsigned Opcode) const
void setImm(int64_t immVal)
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
bool isVectorOnly(unsigned Opcode) const
static MachineInstr * findFirstPredicateSetterFrom(MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static void write(bool isBE, void *P, T V)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool hasVertexCache() const
void setIsKill(bool Val=true)
bool isTransOnly(unsigned Opcode) const
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
static bool NextPossibleSolution(std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, unsigned Idx)
Given a swizzle sequence SwzCandidate and an index Idx, returns the next (in lexicographic term) swiz...
Align max(MaybeAlign Lhs, Align Rhs)
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
MachineOperand class - Representation of each machine instruction operand.
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
#define OPERAND_CASE(Label)
bool hasCaymanISA() const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
bool isALUInstr(unsigned Opcode) const
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
static bool isPredicateSetter(unsigned Opcode)
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
static unsigned getSubRegFromChannel(unsigned Channel)
bool readsLDSSrcReg(const MachineInstr &MI) const
bool isLDSRetInstr(unsigned Opcode) const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
TargetSubtargetInfo - Generic base class for all target subtargets.
static bool isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, const std::vector< std::pair< int, unsigned >> &TransOps, unsigned ConstCount)
Instructions in Trans slot can't read gpr at cycle 0 if they also read a const, and can't read a gpr ...
Representation of each machine instruction.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
static Optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
bool isReductionOp(unsigned opcode) const
#define GET_FLAG_OPERAND_IDX(Flags)
Helper for getting the operand index for the instruction flags operand.
int getIndirectIndexBegin(const MachineFunction &MF) const
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
int getIndirectIndexEnd(const MachineFunction &MF) const
SmallVector< MachineOperand, 4 > Cond
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool canBeConsideredALU(const MachineInstr &MI) const
static bool isBranch(unsigned Opcode)
#define GET_REG_INDEX(reg)
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Register getReg() const
getReg - Returns the register number.
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
const MachineOperand & getOperand(unsigned i) const
bool usesTextureCache(unsigned Opcode) const
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accesed using indirect addressing.
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
MachineBasicBlock MachineBasicBlock::iterator MBBI
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
bool definesAddressRegister(MachineInstr &MI) const
Wrapper class representing virtual and physical registers.
bool isCubeOp(unsigned opcode) const
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override