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14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
17 #define GET_REGINFO_HEADER
18 #include "R600GenRegisterInfo.inc"
51 unsigned FIOperandNum,
This is an optimization pass for GlobalISel generic memory operations.
Reg
All possible values of the reg field in the ModR/M byte.
static unsigned getSubRegFromChannel(unsigned Channel)
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
Register getFrameRegister(const MachineFunction &MF) const override
unsigned getHWRegIndex(unsigned Reg) const
Wrapper class representing virtual and physical registers.
BitVector getReservedRegs(const MachineFunction &MF) const override
bool isPhysRegLiveAcrossClauses(Register Reg) const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.