LLVM 20.0.0git
R600RegisterInfo.h
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1//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition for R600RegisterInfo
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
16
17#define GET_REGINFO_HEADER
18#include "R600GenRegisterInfo.inc"
19
20namespace llvm {
21
24
25 /// \returns the sub reg enum value for the given \p Channel
26 /// (e.g. getSubRegFromChannel(0) -> R600::sub0)
27 static unsigned getSubRegFromChannel(unsigned Channel);
28
29 BitVector getReservedRegs(const MachineFunction &MF) const override;
30 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
31 Register getFrameRegister(const MachineFunction &MF) const override;
32
33 /// get the HW encoding for a register's channel.
34 unsigned getHWRegChan(unsigned reg) const;
35
36 unsigned getHWRegIndex(unsigned Reg) const;
37
38 /// get the register class of the specified type to use in the
39 /// CFGStructurizer
41
42 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
43 return false;
44 }
45
46 // \returns true if \p Reg can be defined in one ALU clause and used in
47 // another.
49
51 unsigned FIOperandNum,
52 RegScavenger *RS = nullptr) const override;
53
54 void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
55};
56
57} // End namespace llvm
58
59#endif
IRTranslator LLVM IR MI
unsigned Reg
Machine Value Type.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
unsigned getHWRegIndex(unsigned Reg) const
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
BitVector getReservedRegs(const MachineFunction &MF) const override
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register's channel.
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override
static unsigned getSubRegFromChannel(unsigned Channel)
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
bool isPhysRegLiveAcrossClauses(Register Reg) const
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
Register getFrameRegister(const MachineFunction &MF) const override