LLVM  10.0.0svn
R600RegisterInfo.cpp
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1 //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// R600 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "R600RegisterInfo.h"
15 #include "AMDGPUTargetMachine.h"
16 #include "R600Defines.h"
17 #include "R600InstrInfo.h"
20 
21 using namespace llvm;
22 
24  RCW.RegWeight = 0;
25  RCW.WeightLimit = 0;
26 }
27 
28 #define GET_REGINFO_TARGET_DESC
29 #include "R600GenRegisterInfo.inc"
30 
32  BitVector Reserved(getNumRegs());
33 
35  const R600InstrInfo *TII = ST.getInstrInfo();
36 
37  reserveRegisterTuples(Reserved, R600::ZERO);
38  reserveRegisterTuples(Reserved, R600::HALF);
39  reserveRegisterTuples(Reserved, R600::ONE);
40  reserveRegisterTuples(Reserved, R600::ONE_INT);
41  reserveRegisterTuples(Reserved, R600::NEG_HALF);
42  reserveRegisterTuples(Reserved, R600::NEG_ONE);
43  reserveRegisterTuples(Reserved, R600::PV_X);
44  reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
45  reserveRegisterTuples(Reserved, R600::ALU_CONST);
46  reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
47  reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
48  reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
49  reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
50  reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
51 
52  for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
53  E = R600::R600_AddrRegClass.end(); I != E; ++I) {
54  reserveRegisterTuples(Reserved, *I);
55  }
56 
57  TII->reserveIndirectRegisters(Reserved, MF, *this);
58 
59  return Reserved;
60 }
61 
62 // Dummy to not crash RegisterClassInfo.
63 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
64 
66  const MachineFunction *) const {
67  return &CalleeSavedReg;
68 }
69 
71  return R600::NoRegister;
72 }
73 
74 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
75  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
76 }
77 
78 unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
79  return GET_REG_INDEX(getEncodingValue(Reg));
80 }
81 
83  MVT VT) const {
84  switch(VT.SimpleTy) {
85  default:
86  case MVT::i32: return &R600::R600_TReg32RegClass;
87  }
88 }
89 
91  const TargetRegisterClass *RC) const {
92  return RCW;
93 }
94 
97 
98  switch (Reg) {
99  case R600::OQAP:
100  case R600::OQBP:
101  case R600::AR_X:
102  return false;
103  default:
104  return true;
105  }
106 }
107 
109  int SPAdj,
110  unsigned FIOperandNum,
111  RegScavenger *RS) const {
112  llvm_unreachable("Subroutines not supported yet");
113 }
114 
115 void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
116  MCRegAliasIterator R(Reg, this, true);
117 
118  for (; R.isValid(); ++R)
119  Reserved.set(*R);
120 }
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
BitVector & set()
Definition: BitVector.h:397
Register getFrameRegister(const MachineFunction &MF) const override
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Interface definition for R600InstrInfo.
unsigned Reg
Interface definition for R600RegisterInfo.
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override
Each TargetRegisterClass has a per register weight, and weight limit which must be less than the limi...
const HexagonInstrInfo * TII
#define HW_CHAN_SHIFT
Definition: R600Defines.h:56
const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const
get the register class of the specified type to use in the CFGStructurizer
SimpleValueType SimpleTy
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Definition: MCRegister.h:19
unsigned getHWRegIndex(unsigned Reg) const
Machine Value Type.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
MCRegAliasIterator enumerates all registers aliasing Reg.
const R600InstrInfo * getInstrInfo() const override
static const MCPhysReg CalleeSavedReg
const MCPhysReg * getCalleeSavedRegs(const MachineFunction *MF) const override
The AMDGPU TargetMachine interface definition for hw codgen targets.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool isPhysRegLiveAcrossClauses(unsigned Reg) const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register&#39;s channel.
void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const
Provides AMDGPU specific target descriptions.
const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const override
BitVector getReservedRegs(const MachineFunction &MF) const override
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:69
#define GET_REG_INDEX(reg)
Definition: R600Defines.h:59
IRTranslator LLVM IR MI
Wrapper class representing virtual and physical registers.
Definition: Register.h:19