LLVM  14.0.0git
R600InstrInfo.h
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1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for R600InstrInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16 
17 #include "R600RegisterInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "R600GenInstrInfo.inc"
22 
23 namespace llvm {
24 
25 namespace R600InstrFlags {
26 enum : uint64_t {
27  REGISTER_STORE = UINT64_C(1) << 62,
28  REGISTER_LOAD = UINT64_C(1) << 63
29 };
30 }
31 
32 class AMDGPUTargetMachine;
33 class DFAPacketizer;
34 class MachineFunction;
35 class MachineInstr;
36 class MachineInstrBuilder;
37 class R600Subtarget;
38 
39 class R600InstrInfo final : public R600GenInstrInfo {
40 private:
41  const R600RegisterInfo RI;
42  const R600Subtarget &ST;
43 
44  std::vector<std::pair<int, unsigned>>
45  ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
46  unsigned &ConstCount) const;
47 
48  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
50  unsigned ValueReg, unsigned Address,
51  unsigned OffsetReg,
52  unsigned AddrChan) const;
53 
54  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
56  unsigned ValueReg, unsigned Address,
57  unsigned OffsetReg,
58  unsigned AddrChan) const;
59 public:
60  enum BankSwizzle {
67  };
68 
69  explicit R600InstrInfo(const R600Subtarget &);
70 
72  return RI;
73  }
74 
76  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
77  bool KillSrc) const override;
79  MachineBasicBlock::iterator MBBI) const override;
80 
81  bool isReductionOp(unsigned opcode) const;
82  bool isCubeOp(unsigned opcode) const;
83 
84  /// \returns true if this \p Opcode represents an ALU instruction.
85  bool isALUInstr(unsigned Opcode) const;
86  bool hasInstrModifiers(unsigned Opcode) const;
87  bool isLDSInstr(unsigned Opcode) const;
88  bool isLDSRetInstr(unsigned Opcode) const;
89 
90  /// \returns true if this \p Opcode represents an ALU instruction or an
91  /// instruction that will be lowered in ExpandSpecialInstrs Pass.
92  bool canBeConsideredALU(const MachineInstr &MI) const;
93 
94  bool isTransOnly(unsigned Opcode) const;
95  bool isTransOnly(const MachineInstr &MI) const;
96  bool isVectorOnly(unsigned Opcode) const;
97  bool isVectorOnly(const MachineInstr &MI) const;
98  bool isExport(unsigned Opcode) const;
99 
100  bool usesVertexCache(unsigned Opcode) const;
101  bool usesVertexCache(const MachineInstr &MI) const;
102  bool usesTextureCache(unsigned Opcode) const;
103  bool usesTextureCache(const MachineInstr &MI) const;
104 
105  bool mustBeLastInClause(unsigned Opcode) const;
106  bool usesAddressRegister(MachineInstr &MI) const;
108  bool readsLDSSrcReg(const MachineInstr &MI) const;
109 
110  /// \returns The operand Index for the Sel operand given an index to one
111  /// of the instruction's src operands.
112  int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
113 
114  /// \returns a pair for each src of an ALU instructions.
115  /// The first member of a pair is the register id.
116  /// If register is ALU_CONST, second member is SEL.
117  /// If register is ALU_LITERAL, second member is IMM.
118  /// Otherwise, second member value is undefined.
120  getSrcs(MachineInstr &MI) const;
121 
122  unsigned isLegalUpTo(
123  const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
124  const std::vector<R600InstrInfo::BankSwizzle> &Swz,
125  const std::vector<std::pair<int, unsigned> > &TransSrcs,
126  R600InstrInfo::BankSwizzle TransSwz) const;
127 
129  const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
130  std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
131  const std::vector<std::pair<int, unsigned> > &TransSrcs,
132  R600InstrInfo::BankSwizzle TransSwz) const;
133 
134  /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
135  /// returns true and the first (in lexical order) BankSwizzle affectation
136  /// starting from the one already provided in the Instruction Group MIs that
137  /// fits Read Port limitations in BS if available. Otherwise returns false
138  /// and undefined content in BS.
139  /// isLastAluTrans should be set if the last Alu of MIs will be executed on
140  /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
141  /// apply to the last instruction.
142  /// PV holds GPR to PV registers in the Instruction Group MIs.
143  bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
145  std::vector<BankSwizzle> &BS,
146  bool isLastAluTrans) const;
147 
148  /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
149  /// from KCache bank on R700+. This function check if MI set in input meet
150  /// this limitations
151  bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
152  /// Same but using const index set instead of MI set.
153  bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
154 
155  /// Vector instructions are instructions that must fill all
156  /// instruction slots within an instruction group.
157  bool isVector(const MachineInstr &MI) const;
158 
159  bool isMov(unsigned Opcode) const;
160 
161  DFAPacketizer *
162  CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
163 
165  SmallVectorImpl<MachineOperand> &Cond) const override;
166 
168  MachineBasicBlock *&FBB,
170  bool AllowModify) const override;
171 
174  const DebugLoc &DL,
175  int *BytesAdded = nullptr) const override;
176 
178  int *BytesRemvoed = nullptr) const override;
179 
180  bool isPredicated(const MachineInstr &MI) const override;
181 
182  bool isPredicable(const MachineInstr &MI) const override;
183 
184  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
185  BranchProbability Probability) const override;
186 
187  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
188  unsigned ExtraPredCycles,
189  BranchProbability Probability) const override ;
190 
192  unsigned NumTCycles, unsigned ExtraTCycles,
193  MachineBasicBlock &FMBB,
194  unsigned NumFCycles, unsigned ExtraFCycles,
195  BranchProbability Probability) const override;
196 
197  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
198  bool SkipDead) const override;
199 
201  MachineBasicBlock &FMBB) const override;
202 
204  ArrayRef<MachineOperand> Pred) const override;
205 
206  unsigned int getPredicationCost(const MachineInstr &) const override;
207 
208  unsigned int getInstrLatency(const InstrItineraryData *ItinData,
209  const MachineInstr &MI,
210  unsigned *PredCost = nullptr) const override;
211 
212  bool expandPostRAPseudo(MachineInstr &MI) const override;
213 
214  /// Reserve the registers that may be accessed using indirect addressing.
215  void reserveIndirectRegisters(BitVector &Reserved,
216  const MachineFunction &MF,
217  const R600RegisterInfo &TRI) const;
218 
219  /// Calculate the "Indirect Address" for the given \p RegIndex and
220  /// \p Channel
221  ///
222  /// We model indirect addressing using a virtual address space that can be
223  /// accessed with loads and stores. The "Indirect Address" is the memory
224  /// address in this virtual address space that maps to the given \p RegIndex
225  /// and \p Channel.
226  unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
227 
228 
229  /// \returns The register class to be used for loading and storing values
230  /// from an "Indirect Address" .
232 
233  /// \returns the smallest register index that will be accessed by an indirect
234  /// read or write or -1 if indirect addressing is not used by this program.
235  int getIndirectIndexBegin(const MachineFunction &MF) const;
236 
237  /// \returns the largest register index that will be accessed by an indirect
238  /// read or write or -1 if indirect addressing is not used by this program.
239  int getIndirectIndexEnd(const MachineFunction &MF) const;
240 
241  /// Build instruction(s) for an indirect register write.
242  ///
243  /// \returns The instruction that performs the indirect register write
244  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
246  unsigned ValueReg, unsigned Address,
247  unsigned OffsetReg) const;
248 
249  /// Build instruction(s) for an indirect register read.
250  ///
251  /// \returns The instruction that performs the indirect register read
252  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
254  unsigned ValueReg, unsigned Address,
255  unsigned OffsetReg) const;
256 
257  unsigned getMaxAlusPerClause() const;
258 
259  /// buildDefaultInstruction - This function returns a MachineInstr with all
260  /// the instruction modifiers initialized to their default values. You can
261  /// use this function to avoid manually specifying each instruction modifier
262  /// operand when building a new instruction.
263  ///
264  /// \returns a MachineInstr with all the instruction modifiers initialized
265  /// to their default values.
268  unsigned Opcode,
269  unsigned DstReg,
270  unsigned Src0Reg,
271  unsigned Src1Reg = 0) const;
272 
274  MachineInstr *MI,
275  unsigned Slot,
276  unsigned DstReg) const;
277 
280  unsigned DstReg,
281  uint64_t Imm) const;
282 
285  unsigned DstReg, unsigned SrcReg) const;
286 
287  /// Get the index of Op in the MachineInstr.
288  ///
289  /// \returns -1 if the Instruction does not contain the specified \p Op.
290  int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
291 
292  /// Get the index of \p Op for the given Opcode.
293  ///
294  /// \returns -1 if the Instruction does not contain the specified \p Op.
295  int getOperandIdx(unsigned Opcode, unsigned Op) const;
296 
297  /// Helper function for setting instruction flag values.
298  void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
299 
300  ///Add one of the MO_FLAG* flags to the specified \p Operand.
301  void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
302 
303  ///Determine if the specified \p Flag is set on this \p Operand.
304  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
305 
306  /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
307  /// \param Flag The flag being set.
308  ///
309  /// \returns the operand containing the flags for this instruction.
310  MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
311  unsigned Flag = 0) const;
312 
313  /// Clear the specified flag on the instruction.
314  void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
315 
316  // Helper functions that check the opcode for status information
317  bool isRegisterStore(const MachineInstr &MI) const {
318  return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
319  }
320 
321  bool isRegisterLoad(const MachineInstr &MI) const {
322  return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
323  }
324 
326  unsigned Kind) const override;
327 };
328 
329 namespace R600 {
330 
331 int getLDSNoRetOp(uint16_t Opcode);
332 
333 } //End namespace AMDGPU
334 
335 } // End llvm namespace
336 
337 #endif
llvm::R600InstrInfo::isALUInstr
bool isALUInstr(unsigned Opcode) const
Definition: R600InstrInfo.cpp:111
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::R600InstrInfo::setImmOperand
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
Definition: R600InstrInfo.cpp:1367
llvm::R600InstrInfo::fitsReadPortLimitations
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
Definition: R600InstrInfo.cpp:513
llvm::R600InstrInfo::isVectorOnly
bool isVectorOnly(unsigned Opcode) const
Definition: R600InstrInfo.cpp:165
llvm::R600InstrInfo::getIndirectIndexEnd
int getIndirectIndexEnd(const MachineFunction &MF) const
Definition: R600InstrInfo.cpp:1190
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::R600InstrInfo::isFlagSet
bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const
Determine if the specified Flag is set on this Operand.
llvm::R600InstrInfo::getOperandIdx
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
Definition: R600InstrInfo.cpp:1359
TargetInstrInfo.h
llvm::R600InstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: R600InstrInfo.cpp:878
llvm::R600InstrInfo::isRegisterLoad
bool isRegisterLoad(const MachineInstr &MI) const
Definition: R600InstrInfo.h:321
llvm::R600InstrInfo::isLegalUpTo
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
Definition: R600InstrInfo.cpp:407
llvm::R600InstrInfo::isLDSInstr
bool isLDSInstr(unsigned Opcode) const
Definition: R600InstrInfo.cpp:125
llvm::R600InstrInfo::usesVertexCache
bool usesVertexCache(unsigned Opcode) const
Definition: R600InstrInfo.cpp:177
llvm::R600InstrInfo::canBeConsideredALU
bool canBeConsideredALU(const MachineInstr &MI) const
Definition: R600InstrInfo.cpp:137
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::R600InstrInfo::readsLDSSrcReg
bool readsLDSSrcReg(const MachineInstr &MI) const
Definition: R600InstrInfo.cpp:216
R600GenInstrInfo
llvm::R600RegisterInfo
Definition: R600RegisterInfo.h:22
llvm::R600InstrInfo::ALU_VEC_102_SCL_221
@ ALU_VEC_102_SCL_221
Definition: R600InstrInfo.h:64
llvm::R600InstrInfo::buildMovImm
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
Definition: R600InstrInfo.cpp:1343
llvm::R600InstrInfo::isExport
bool isExport(unsigned Opcode) const
Definition: R600InstrInfo.cpp:173
llvm::R600InstrInfo::buildMovInstr
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
Definition: R600InstrInfo.cpp:1353
llvm::R600InstrInfo::definesAddressRegister
bool definesAddressRegister(MachineInstr &MI) const
Definition: R600InstrInfo.cpp:212
llvm::R600InstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: R600InstrInfo.cpp:950
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::DFAPacketizer
Definition: DFAPacketizer.h:49
llvm::R600InstrInfo::getInstrLatency
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: R600InstrInfo.cpp:988
llvm::R600InstrInfo::isVector
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
Definition: R600InstrInfo.cpp:35
llvm::R600InstrInfo::CreateTargetScheduleState
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
Definition: R600InstrInfo.cpp:614
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:146
llvm::R600InstrInfo::hasInstrModifiers
bool hasInstrModifiers(unsigned Opcode) const
Definition: R600InstrInfo.cpp:117
llvm::R600InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: R600InstrInfo.cpp:1002
llvm::BitVector
Definition: BitVector.h:74
llvm::R600InstrFlags::REGISTER_STORE
@ REGISTER_STORE
Definition: R600InstrInfo.h:27
llvm::R600InstrInfo::isReductionOp
bool isReductionOp(unsigned opcode) const
Definition: R600InstrInfo.cpp:96
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::R600InstrInfo::reserveIndirectRegisters
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accessed using indirect addressing.
Definition: R600InstrInfo.cpp:1068
llvm::R600InstrInfo::usesTextureCache
bool usesTextureCache(unsigned Opcode) const
Definition: R600InstrInfo.cpp:187
llvm::R600InstrInfo::isProfitableToUnpredicate
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: R600InstrInfo.cpp:905
llvm::R600InstrInfo::getIndirectAddrRegClass
const TargetRegisterClass * getIndirectAddrRegClass() const
Definition: R600InstrInfo.cpp:1088
llvm::R600Subtarget
Definition: R600Subtarget.h:35
llvm::R600InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: R600InstrInfo.cpp:39
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
llvm::R600InstrInfo::clearFlag
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
Definition: R600InstrInfo.cpp:1465
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::R600InstrInfo::FindSwizzleForVectorSlot
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
Definition: R600InstrInfo.cpp:476
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::R600::getLDSNoRetOp
int getLDSNoRetOp(uint16_t Opcode)
llvm::HighlightColor::Address
@ Address
llvm::R600InstrInfo::getRegisterInfo
const R600RegisterInfo & getRegisterInfo() const
Definition: R600InstrInfo.h:71
llvm::R600InstrFlags::REGISTER_LOAD
@ REGISTER_LOAD
Definition: R600InstrInfo.h:28
R600RegisterInfo.h
llvm::R600InstrInfo::isCubeOp
bool isCubeOp(unsigned opcode) const
Definition: R600InstrInfo.cpp:100
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::R600InstrInfo::getFlagOp
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
Definition: R600InstrInfo.cpp:1379
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::R600InstrInfo::getAddressSpaceForPseudoSourceKind
unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const override
Definition: R600InstrInfo.cpp:1479
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::R600InstrInfo::isLDSRetInstr
bool isLDSRetInstr(unsigned Opcode) const
Definition: R600InstrInfo.cpp:133
llvm::R600InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: R600InstrInfo.cpp:734
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::R600InstrInfo::ALU_VEC_012_SCL_210
@ ALU_VEC_012_SCL_210
Definition: R600InstrInfo.h:61
llvm::R600InstrInfo::mustBeLastInClause
bool mustBeLastInClause(unsigned Opcode) const
Definition: R600InstrInfo.cpp:198
llvm::R600InstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
Definition: R600InstrInfo.cpp:855
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::R600InstrInfo::isTransOnly
bool isTransOnly(unsigned Opcode) const
Definition: R600InstrInfo.cpp:155
llvm::R600InstrInfo::calculateIndirectAddress
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
Definition: R600InstrInfo.cpp:996
uint16_t
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::R600InstrInfo::R600InstrInfo
R600InstrInfo(const R600Subtarget &)
Definition: R600InstrInfo.cpp:32
llvm::R600InstrInfo::fitsConstReadLimitations
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
Definition: R600InstrInfo.cpp:586
llvm::R600InstrInfo::getSrcs
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
Definition: R600InstrInfo.cpp:256
llvm::R600InstrInfo::addFlag
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
Definition: R600InstrInfo.cpp:1444
llvm::R600InstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: R600InstrInfo.cpp:897
llvm::R600InstrInfo::BankSwizzle
BankSwizzle
Definition: R600InstrInfo.h:60
llvm::R600InstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Definition: R600InstrInfo.cpp:840
llvm::R600InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: R600InstrInfo.cpp:652
llvm::R600InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: R600InstrInfo.cpp:911
llvm::R600InstrInfo
Definition: R600InstrInfo.h:39
llvm::R600InstrInfo::buildSlotOfVectorInstruction
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
Definition: R600InstrInfo.cpp:1295
llvm::R600InstrInfo::getMaxAlusPerClause
unsigned getMaxAlusPerClause() const
Definition: R600InstrInfo.cpp:1212
llvm::R600InstrInfo::isRegisterStore
bool isRegisterStore(const MachineInstr &MI) const
Definition: R600InstrInfo.h:317
llvm::R600InstrInfo::getSelIdx
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
Definition: R600InstrInfo.cpp:232
llvm::R600InstrInfo::isLegalToSplitMBBAt
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Definition: R600InstrInfo.cpp:74
llvm::R600InstrInfo::buildDefaultInstruction
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
Definition: R600InstrInfo.cpp:1216
llvm::R600InstrInfo::ALU_VEC_201
@ ALU_VEC_201
Definition: R600InstrInfo.h:65
llvm::R600InstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
Definition: R600InstrInfo.cpp:944
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::R600InstrInfo::ALU_VEC_120_SCL_212
@ ALU_VEC_120_SCL_212
Definition: R600InstrInfo.h:63
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::R600InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const override
Definition: R600InstrInfo.cpp:781
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::R600InstrInfo::getPredicationCost
unsigned int getPredicationCost(const MachineInstr &) const override
Definition: R600InstrInfo.cpp:984
llvm::R600InstrInfo::getIndirectIndexBegin
int getIndirectIndexBegin(const MachineFunction &MF) const
Definition: R600InstrInfo.cpp:1158
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::R600InstrInfo::ALU_VEC_210
@ ALU_VEC_210
Definition: R600InstrInfo.h:66
llvm::R600InstrInfo::isMov
bool isMov(unsigned Opcode) const
Definition: R600InstrInfo.cpp:85
llvm::R600InstrInfo::usesAddressRegister
bool usesAddressRegister(MachineInstr &MI) const
Definition: R600InstrInfo.cpp:208
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::R600InstrInfo::ALU_VEC_021_SCL_122
@ ALU_VEC_021_SCL_122
Definition: R600InstrInfo.h:62