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14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
20 #define GET_INSTRINFO_HEADER
21 #include "R600GenInstrInfo.inc"
25 namespace R600InstrFlags {
33 class MachineFunction;
35 class MachineInstrBuilder;
43 std::vector<std::pair<int, unsigned>>
45 unsigned &ConstCount)
const;
49 unsigned ValueReg,
unsigned Address,
51 unsigned AddrChan)
const;
55 unsigned ValueReg,
unsigned Address,
57 unsigned AddrChan)
const;
76 bool KillSrc)
const override;
81 bool isCubeOp(
unsigned opcode)
const;
97 bool isExport(
unsigned Opcode)
const;
111 int getSelIdx(
unsigned Opcode,
unsigned SrcIdx)
const;
122 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
123 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
124 const std::vector<std::pair<int, unsigned> > &TransSrcs,
128 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
129 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
130 const std::vector<std::pair<int, unsigned> > &TransSrcs,
144 std::vector<BankSwizzle> &BS,
145 bool isLastAluTrans)
const;
158 bool isMov(
unsigned Opcode)
const;
169 bool AllowModify)
const override;
174 int *BytesAdded =
nullptr)
const override;
177 int *BytesRemoved =
nullptr)
const override;
187 unsigned ExtraPredCycles,
191 unsigned NumTCycles,
unsigned ExtraTCycles,
193 unsigned NumFCycles,
unsigned ExtraFCycles,
197 bool SkipDead)
const override;
209 unsigned *PredCost =
nullptr)
const override;
245 unsigned ValueReg,
unsigned Address,
246 unsigned OffsetReg)
const;
253 unsigned ValueReg,
unsigned Address,
254 unsigned OffsetReg)
const;
270 unsigned Src1Reg = 0)
const;
275 unsigned DstReg)
const;
284 unsigned DstReg,
unsigned SrcReg)
const;
310 unsigned Flag = 0)
const;
bool isALUInstr(unsigned Opcode) const
This is an optimization pass for GlobalISel generic memory operations.
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
bool isVectorOnly(unsigned Opcode) const
int getIndirectIndexEnd(const MachineFunction &MF) const
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const
Determine if the specified Flag is set on this Operand.
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isRegisterLoad(const MachineInstr &MI) const
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
bool isLDSInstr(unsigned Opcode) const
bool usesVertexCache(unsigned Opcode) const
bool canBeConsideredALU(const MachineInstr &MI) const
unsigned const TargetRegisterInfo * TRI
bool readsLDSSrcReg(const MachineInstr &MI) const
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
bool isExport(unsigned Opcode) const
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
bool definesAddressRegister(MachineInstr &MI) const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
MachineOperand class - Representation of each machine instruction operand.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
bool hasInstrModifiers(unsigned Opcode) const
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isReductionOp(unsigned opcode) const
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accessed using indirect addressing.
bool usesTextureCache(unsigned Opcode) const
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
const TargetRegisterClass * getIndirectAddrRegClass() const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Representation of each machine instruction.
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
int getLDSNoRetOp(uint16_t Opcode)
const R600RegisterInfo & getRegisterInfo() const
bool isCubeOp(unsigned opcode) const
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
SmallVector< MachineOperand, 4 > Cond
MachineBasicBlock MachineBasicBlock::iterator MBBI
bool isLDSRetInstr(unsigned Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
TargetSubtargetInfo - Generic base class for all target subtargets.
bool mustBeLastInClause(unsigned Opcode) const
bool isPredicable(const MachineInstr &MI) const override
bool isTransOnly(unsigned Opcode) const
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
Should compile to something r4 addze r3 instead we get
R600InstrInfo(const R600Subtarget &)
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool isPredicated(const MachineInstr &MI) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
unsigned getMaxAlusPerClause() const
bool isRegisterStore(const MachineInstr &MI) const
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
unsigned int getPredicationCost(const MachineInstr &) const override
int getIndirectIndexBegin(const MachineFunction &MF) const
bool isMov(unsigned Opcode) const
bool usesAddressRegister(MachineInstr &MI) const
Itinerary data supplied by a subtarget to be used by a target.
Wrapper class representing physical registers. Should be passed by value.