LLVM 22.0.0git
R600InstrInfo.h
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1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Interface definition for R600InstrInfo
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16
17#include "R600RegisterInfo.h"
19
20#define GET_INSTRINFO_HEADER
21#define GET_INSTRINFO_OPERAND_ENUM
22#include "R600GenInstrInfo.inc"
23
24namespace llvm {
25
26namespace R600InstrFlags {
27enum : uint64_t {
28 REGISTER_STORE = UINT64_C(1) << 62,
29 REGISTER_LOAD = UINT64_C(1) << 63
30};
31}
32
33class DFAPacketizer;
34class MachineFunction;
35class MachineInstr;
36class MachineInstrBuilder;
37class R600Subtarget;
38
39class R600InstrInfo final : public R600GenInstrInfo {
40private:
41 const R600RegisterInfo RI;
42 const R600Subtarget &ST;
43
44 std::vector<std::pair<int, unsigned>>
45 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
46 unsigned &ConstCount) const;
47
48 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
50 unsigned ValueReg, unsigned Address,
51 unsigned OffsetReg,
52 unsigned AddrChan) const;
53
54 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
56 unsigned ValueReg, unsigned Address,
57 unsigned OffsetReg,
58 unsigned AddrChan) const;
59public:
67 };
68
69 explicit R600InstrInfo(const R600Subtarget &);
70
72 return RI;
73 }
74
76 const DebugLoc &DL, Register DestReg, Register SrcReg,
77 bool KillSrc, bool RenamableDest = false,
78 bool RenamableSrc = false) const override;
80 MachineBasicBlock::iterator MBBI) const override;
81
82 bool isReductionOp(unsigned opcode) const;
83 bool isCubeOp(unsigned opcode) const;
84
85 /// \returns true if this \p Opcode represents an ALU instruction.
86 bool isALUInstr(unsigned Opcode) const;
87 bool hasInstrModifiers(unsigned Opcode) const;
88 bool isLDSInstr(unsigned Opcode) const;
89 bool isLDSRetInstr(unsigned Opcode) const;
90
91 /// \returns true if this \p Opcode represents an ALU instruction or an
92 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
93 bool canBeConsideredALU(const MachineInstr &MI) const;
94
95 bool isTransOnly(unsigned Opcode) const;
96 bool isTransOnly(const MachineInstr &MI) const;
97 bool isVectorOnly(unsigned Opcode) const;
98 bool isVectorOnly(const MachineInstr &MI) const;
99 bool isExport(unsigned Opcode) const;
100
101 bool usesVertexCache(unsigned Opcode) const;
102 bool usesVertexCache(const MachineInstr &MI) const;
103 bool usesTextureCache(unsigned Opcode) const;
104 bool usesTextureCache(const MachineInstr &MI) const;
105
106 bool mustBeLastInClause(unsigned Opcode) const;
109 bool readsLDSSrcReg(const MachineInstr &MI) const;
110
111 /// \returns The operand Index for the Sel operand given an index to one
112 /// of the instruction's src operands.
113 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
114
115 /// \returns a pair for each src of an ALU instructions.
116 /// The first member of a pair is the register id.
117 /// If register is ALU_CONST, second member is SEL.
118 /// If register is ALU_LITERAL, second member is IMM.
119 /// Otherwise, second member value is undefined.
121 getSrcs(MachineInstr &MI) const;
122
123 unsigned isLegalUpTo(
124 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
125 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
126 const std::vector<std::pair<int, unsigned> > &TransSrcs,
127 R600InstrInfo::BankSwizzle TransSwz) const;
128
130 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
131 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
132 const std::vector<std::pair<int, unsigned> > &TransSrcs,
133 R600InstrInfo::BankSwizzle TransSwz) const;
134
135 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
136 /// returns true and the first (in lexical order) BankSwizzle affectation
137 /// starting from the one already provided in the Instruction Group MIs that
138 /// fits Read Port limitations in BS if available. Otherwise returns false
139 /// and undefined content in BS.
140 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
141 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
142 /// apply to the last instruction.
143 /// PV holds GPR to PV registers in the Instruction Group MIs.
144 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
146 std::vector<BankSwizzle> &BS,
147 bool isLastAluTrans) const;
148
149 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
150 /// from KCache bank on R700+. This function check if MI set in input meet
151 /// this limitations
152 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
153 /// Same but using const index set instead of MI set.
154 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
155
156 /// Vector instructions are instructions that must fill all
157 /// instruction slots within an instruction group.
158 bool isVector(const MachineInstr &MI) const;
159
160 bool isMov(unsigned Opcode) const;
161
163 CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
164
166 SmallVectorImpl<MachineOperand> &Cond) const override;
167
169 MachineBasicBlock *&FBB,
171 bool AllowModify) const override;
172
175 const DebugLoc &DL,
176 int *BytesAdded = nullptr) const override;
177
179 int *BytesRemoved = nullptr) const override;
180
181 bool isPredicated(const MachineInstr &MI) const override;
182
183 bool isPredicable(const MachineInstr &MI) const override;
184
185 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
186 BranchProbability Probability) const override;
187
188 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
189 unsigned ExtraPredCycles,
190 BranchProbability Probability) const override ;
191
193 unsigned NumTCycles, unsigned ExtraTCycles,
194 MachineBasicBlock &FMBB,
195 unsigned NumFCycles, unsigned ExtraFCycles,
196 BranchProbability Probability) const override;
197
198 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
199 bool SkipDead) const override;
200
202 MachineBasicBlock &FMBB) const override;
203
205 ArrayRef<MachineOperand> Pred) const override;
206
207 unsigned int getPredicationCost(const MachineInstr &) const override;
208
209 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
210 const MachineInstr &MI,
211 unsigned *PredCost = nullptr) const override;
212
213 bool expandPostRAPseudo(MachineInstr &MI) const override;
214
215 /// Reserve the registers that may be accessed using indirect addressing.
217 const MachineFunction &MF,
218 const R600RegisterInfo &TRI) const;
219
220 /// Calculate the "Indirect Address" for the given \p RegIndex and
221 /// \p Channel
222 ///
223 /// We model indirect addressing using a virtual address space that can be
224 /// accessed with loads and stores. The "Indirect Address" is the memory
225 /// address in this virtual address space that maps to the given \p RegIndex
226 /// and \p Channel.
227 unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
228
229
230 /// \returns The register class to be used for loading and storing values
231 /// from an "Indirect Address" .
233
234 /// \returns the smallest register index that will be accessed by an indirect
235 /// read or write or -1 if indirect addressing is not used by this program.
236 int getIndirectIndexBegin(const MachineFunction &MF) const;
237
238 /// \returns the largest register index that will be accessed by an indirect
239 /// read or write or -1 if indirect addressing is not used by this program.
240 int getIndirectIndexEnd(const MachineFunction &MF) const;
241
242 /// Build instruction(s) for an indirect register write.
243 ///
244 /// \returns The instruction that performs the indirect register write
245 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
247 unsigned ValueReg, unsigned Address,
248 unsigned OffsetReg) const;
249
250 /// Build instruction(s) for an indirect register read.
251 ///
252 /// \returns The instruction that performs the indirect register read
253 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
255 unsigned ValueReg, unsigned Address,
256 unsigned OffsetReg) const;
257
258 unsigned getMaxAlusPerClause() const;
259
260 /// buildDefaultInstruction - This function returns a MachineInstr with all
261 /// the instruction modifiers initialized to their default values. You can
262 /// use this function to avoid manually specifying each instruction modifier
263 /// operand when building a new instruction.
264 ///
265 /// \returns a MachineInstr with all the instruction modifiers initialized
266 /// to their default values.
269 unsigned Opcode,
270 unsigned DstReg,
271 unsigned Src0Reg,
272 unsigned Src1Reg = 0) const;
273
276 unsigned Slot,
277 unsigned DstReg) const;
278
281 unsigned DstReg,
282 uint64_t Imm) const;
283
286 unsigned DstReg, unsigned SrcReg) const;
287
288 /// Get the index of Op in the MachineInstr.
289 ///
290 /// \returns -1 if the Instruction does not contain the specified \p Op.
291 int getOperandIdx(const MachineInstr &MI, R600::OpName Op) const;
292
293 /// Get the index of \p Op for the given Opcode.
294 ///
295 /// \returns -1 if the Instruction does not contain the specified \p Op.
296 int getOperandIdx(unsigned Opcode, R600::OpName Op) const;
297
298 /// Helper function for setting instruction flag values.
299 void setImmOperand(MachineInstr &MI, R600::OpName Op, int64_t Imm) const;
300
301 /// Add one of the MO_FLAG* flags to the operand at \p SrcIdx.
302 void addFlag(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const;
303
304 /// Determine if the specified \p Flag is set on operand at \p SrcIdx.
305 bool isFlagSet(const MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const;
306
307 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
308 /// \param Flag The flag being set.
309 ///
310 /// \returns the operand containing the flags for this instruction.
311 MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
312 unsigned Flag = 0) const;
313
314 /// Clear the specified flag on the instruction.
315 void clearFlag(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const;
316
317 // Helper functions that check the opcode for status information
318 bool isRegisterStore(const MachineInstr &MI) const {
319 return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
320 }
321
322 bool isRegisterLoad(const MachineInstr &MI) const {
323 return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
324 }
325};
326
327namespace R600 {
328
330
331} //End namespace AMDGPU
332
333} // End llvm namespace
334
335#endif
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
IRTranslator LLVM IR MI
#define I(x, y, z)
Definition: MD5.cpp:58
Register const TargetRegisterInfo * TRI
Interface definition for R600RegisterInfo.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:124
Itinerary data supplied by a subtarget to be used by a target.
Representation of each machine instruction.
Definition: MachineInstr.h:72
MachineOperand class - Representation of each machine instruction operand.
bool usesVertexCache(unsigned Opcode) const
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void addFlag(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Add one of the MO_FLAG* flags to the operand at SrcIdx.
bool usesAddressRegister(MachineInstr &MI) const
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
bool hasInstrModifiers(unsigned Opcode) const
const R600RegisterInfo & getRegisterInfo() const
Definition: R600InstrInfo.h:71
bool isMov(unsigned Opcode) const
bool isRegisterLoad(const MachineInstr &MI) const
int getIndirectIndexBegin(const MachineFunction &MF) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool usesTextureCache(unsigned Opcode) const
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
const TargetRegisterClass * getIndirectAddrRegClass() const
void clearFlag(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Clear the specified flag on the instruction.
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
bool definesAddressRegister(MachineInstr &MI) const
unsigned getMaxAlusPerClause() const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
int getOperandIdx(const MachineInstr &MI, R600::OpName Op) const
Get the index of Op in the MachineInstr.
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
bool canBeConsideredALU(const MachineInstr &MI) const
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
bool isFlagSet(const MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Determine if the specified Flag is set on operand at SrcIdx.
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool mustBeLastInClause(unsigned Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
int getIndirectIndexEnd(const MachineFunction &MF) const
bool isTransOnly(unsigned Opcode) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
bool isReductionOp(unsigned opcode) const
bool isRegisterStore(const MachineInstr &MI) const
bool isCubeOp(unsigned opcode) const
bool isLDSInstr(unsigned Opcode) const
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accessed using indirect addressing.
void setImmOperand(MachineInstr &MI, R600::OpName Op, int64_t Imm) const
Helper function for setting instruction flag values.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isPredicable(const MachineInstr &MI) const override
bool isPredicated(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isLDSRetInstr(unsigned Opcode) const
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
unsigned int getPredicationCost(const MachineInstr &) const override
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
bool readsLDSSrcReg(const MachineInstr &MI) const
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool isALUInstr(unsigned Opcode) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
bool isVectorOnly(unsigned Opcode) const
bool isExport(unsigned Opcode) const
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:574
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1197
TargetSubtargetInfo - Generic base class for all target subtargets.
int getLDSNoRetOp(uint16_t Opcode)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)