14#ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
15#define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
20#define GET_INSTRINFO_HEADER
21#define GET_INSTRINFO_OPERAND_ENUM
22#include "R600GenInstrInfo.inc"
26namespace R600InstrFlags {
36class MachineInstrBuilder;
44 std::vector<std::pair<int, unsigned>>
46 unsigned &ConstCount)
const;
50 unsigned ValueReg,
unsigned Address,
52 unsigned AddrChan)
const;
56 unsigned ValueReg,
unsigned Address,
58 unsigned AddrChan)
const;
77 bool KillSrc,
bool RenamableDest =
false,
78 bool RenamableSrc =
false)
const override;
83 bool isCubeOp(
unsigned opcode)
const;
99 bool isExport(
unsigned Opcode)
const;
113 int getSelIdx(
unsigned Opcode,
unsigned SrcIdx)
const;
124 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
125 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
126 const std::vector<std::pair<int, unsigned> > &TransSrcs,
130 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
131 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
132 const std::vector<std::pair<int, unsigned> > &TransSrcs,
146 std::vector<BankSwizzle> &BS,
147 bool isLastAluTrans)
const;
160 bool isMov(
unsigned Opcode)
const;
171 bool AllowModify)
const override;
176 int *BytesAdded =
nullptr)
const override;
179 int *BytesRemoved =
nullptr)
const override;
189 unsigned ExtraPredCycles,
193 unsigned NumTCycles,
unsigned ExtraTCycles,
195 unsigned NumFCycles,
unsigned ExtraFCycles,
199 bool SkipDead)
const override;
211 unsigned *PredCost =
nullptr)
const override;
247 unsigned ValueReg,
unsigned Address,
248 unsigned OffsetReg)
const;
255 unsigned ValueReg,
unsigned Address,
256 unsigned OffsetReg)
const;
272 unsigned Src1Reg = 0)
const;
277 unsigned DstReg)
const;
286 unsigned DstReg,
unsigned SrcReg)
const;
312 unsigned Flag = 0)
const;
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
Register const TargetRegisterInfo * TRI
Interface definition for R600RegisterInfo.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
This class represents an Operation in the Expression.
Itinerary data supplied by a subtarget to be used by a target.
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
bool usesVertexCache(unsigned Opcode) const
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
void addFlag(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Add one of the MO_FLAG* flags to the operand at SrcIdx.
bool usesAddressRegister(MachineInstr &MI) const
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
bool hasInstrModifiers(unsigned Opcode) const
const R600RegisterInfo & getRegisterInfo() const
bool isMov(unsigned Opcode) const
bool isRegisterLoad(const MachineInstr &MI) const
int getIndirectIndexBegin(const MachineFunction &MF) const
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
bool usesTextureCache(unsigned Opcode) const
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
const TargetRegisterClass * getIndirectAddrRegClass() const
void clearFlag(MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Clear the specified flag on the instruction.
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
bool definesAddressRegister(MachineInstr &MI) const
unsigned getMaxAlusPerClause() const
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
int getOperandIdx(const MachineInstr &MI, R600::OpName Op) const
Get the index of Op in the MachineInstr.
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
bool canBeConsideredALU(const MachineInstr &MI) const
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
bool isFlagSet(const MachineInstr &MI, unsigned SrcIdx, unsigned Flag) const
Determine if the specified Flag is set on operand at SrcIdx.
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
bool mustBeLastInClause(unsigned Opcode) const
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
int getIndirectIndexEnd(const MachineFunction &MF) const
bool isTransOnly(unsigned Opcode) const
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
bool isReductionOp(unsigned opcode) const
bool isRegisterStore(const MachineInstr &MI) const
bool isCubeOp(unsigned opcode) const
bool isLDSInstr(unsigned Opcode) const
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accessed using indirect addressing.
void setImmOperand(MachineInstr &MI, R600::OpName Op, int64_t Imm) const
Helper function for setting instruction flag values.
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
bool isPredicable(const MachineInstr &MI) const override
bool isPredicated(const MachineInstr &MI) const override
bool expandPostRAPseudo(MachineInstr &MI) const override
bool isLDSRetInstr(unsigned Opcode) const
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
unsigned int getPredicationCost(const MachineInstr &) const override
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
bool readsLDSSrcReg(const MachineInstr &MI) const
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
bool isALUInstr(unsigned Opcode) const
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, Register SrcReg, bool KillSrc, bool RenamableDest=false, bool RenamableSrc=false) const override
bool isVectorOnly(unsigned Opcode) const
bool isExport(unsigned Opcode) const
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetSubtargetInfo - Generic base class for all target subtargets.
int getLDSNoRetOp(uint16_t Opcode)
This is an optimization pass for GlobalISel generic memory operations.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)