LLVM  15.0.0git
R600InstrInfo.h
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1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Interface definition for R600InstrInfo
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
15 #define LLVM_LIB_TARGET_AMDGPU_R600INSTRINFO_H
16 
17 #include "R600RegisterInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "R600GenInstrInfo.inc"
22 
23 namespace llvm {
24 
25 namespace R600InstrFlags {
26 enum : uint64_t {
27  REGISTER_STORE = UINT64_C(1) << 62,
28  REGISTER_LOAD = UINT64_C(1) << 63
29 };
30 }
31 
32 class DFAPacketizer;
33 class MachineFunction;
34 class MachineInstr;
35 class MachineInstrBuilder;
36 class R600Subtarget;
37 
38 class R600InstrInfo final : public R600GenInstrInfo {
39 private:
40  const R600RegisterInfo RI;
41  const R600Subtarget &ST;
42 
43  std::vector<std::pair<int, unsigned>>
44  ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
45  unsigned &ConstCount) const;
46 
47  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
49  unsigned ValueReg, unsigned Address,
50  unsigned OffsetReg,
51  unsigned AddrChan) const;
52 
53  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
55  unsigned ValueReg, unsigned Address,
56  unsigned OffsetReg,
57  unsigned AddrChan) const;
58 public:
59  enum BankSwizzle {
66  };
67 
68  explicit R600InstrInfo(const R600Subtarget &);
69 
71  return RI;
72  }
73 
75  const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
76  bool KillSrc) const override;
78  MachineBasicBlock::iterator MBBI) const override;
79 
80  bool isReductionOp(unsigned opcode) const;
81  bool isCubeOp(unsigned opcode) const;
82 
83  /// \returns true if this \p Opcode represents an ALU instruction.
84  bool isALUInstr(unsigned Opcode) const;
85  bool hasInstrModifiers(unsigned Opcode) const;
86  bool isLDSInstr(unsigned Opcode) const;
87  bool isLDSRetInstr(unsigned Opcode) const;
88 
89  /// \returns true if this \p Opcode represents an ALU instruction or an
90  /// instruction that will be lowered in ExpandSpecialInstrs Pass.
91  bool canBeConsideredALU(const MachineInstr &MI) const;
92 
93  bool isTransOnly(unsigned Opcode) const;
94  bool isTransOnly(const MachineInstr &MI) const;
95  bool isVectorOnly(unsigned Opcode) const;
96  bool isVectorOnly(const MachineInstr &MI) const;
97  bool isExport(unsigned Opcode) const;
98 
99  bool usesVertexCache(unsigned Opcode) const;
100  bool usesVertexCache(const MachineInstr &MI) const;
101  bool usesTextureCache(unsigned Opcode) const;
102  bool usesTextureCache(const MachineInstr &MI) const;
103 
104  bool mustBeLastInClause(unsigned Opcode) const;
105  bool usesAddressRegister(MachineInstr &MI) const;
107  bool readsLDSSrcReg(const MachineInstr &MI) const;
108 
109  /// \returns The operand Index for the Sel operand given an index to one
110  /// of the instruction's src operands.
111  int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
112 
113  /// \returns a pair for each src of an ALU instructions.
114  /// The first member of a pair is the register id.
115  /// If register is ALU_CONST, second member is SEL.
116  /// If register is ALU_LITERAL, second member is IMM.
117  /// Otherwise, second member value is undefined.
119  getSrcs(MachineInstr &MI) const;
120 
121  unsigned isLegalUpTo(
122  const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
123  const std::vector<R600InstrInfo::BankSwizzle> &Swz,
124  const std::vector<std::pair<int, unsigned> > &TransSrcs,
125  R600InstrInfo::BankSwizzle TransSwz) const;
126 
128  const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
129  std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
130  const std::vector<std::pair<int, unsigned> > &TransSrcs,
131  R600InstrInfo::BankSwizzle TransSwz) const;
132 
133  /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
134  /// returns true and the first (in lexical order) BankSwizzle affectation
135  /// starting from the one already provided in the Instruction Group MIs that
136  /// fits Read Port limitations in BS if available. Otherwise returns false
137  /// and undefined content in BS.
138  /// isLastAluTrans should be set if the last Alu of MIs will be executed on
139  /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
140  /// apply to the last instruction.
141  /// PV holds GPR to PV registers in the Instruction Group MIs.
142  bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
144  std::vector<BankSwizzle> &BS,
145  bool isLastAluTrans) const;
146 
147  /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
148  /// from KCache bank on R700+. This function check if MI set in input meet
149  /// this limitations
150  bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
151  /// Same but using const index set instead of MI set.
152  bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
153 
154  /// Vector instructions are instructions that must fill all
155  /// instruction slots within an instruction group.
156  bool isVector(const MachineInstr &MI) const;
157 
158  bool isMov(unsigned Opcode) const;
159 
160  DFAPacketizer *
161  CreateTargetScheduleState(const TargetSubtargetInfo &) const override;
162 
164  SmallVectorImpl<MachineOperand> &Cond) const override;
165 
167  MachineBasicBlock *&FBB,
169  bool AllowModify) const override;
170 
173  const DebugLoc &DL,
174  int *BytesAdded = nullptr) const override;
175 
177  int *BytesRemoved = nullptr) const override;
178 
179  bool isPredicated(const MachineInstr &MI) const override;
180 
181  bool isPredicable(const MachineInstr &MI) const override;
182 
183  bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
184  BranchProbability Probability) const override;
185 
186  bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
187  unsigned ExtraPredCycles,
188  BranchProbability Probability) const override ;
189 
191  unsigned NumTCycles, unsigned ExtraTCycles,
192  MachineBasicBlock &FMBB,
193  unsigned NumFCycles, unsigned ExtraFCycles,
194  BranchProbability Probability) const override;
195 
196  bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
197  bool SkipDead) const override;
198 
200  MachineBasicBlock &FMBB) const override;
201 
203  ArrayRef<MachineOperand> Pred) const override;
204 
205  unsigned int getPredicationCost(const MachineInstr &) const override;
206 
207  unsigned int getInstrLatency(const InstrItineraryData *ItinData,
208  const MachineInstr &MI,
209  unsigned *PredCost = nullptr) const override;
210 
211  bool expandPostRAPseudo(MachineInstr &MI) const override;
212 
213  /// Reserve the registers that may be accessed using indirect addressing.
214  void reserveIndirectRegisters(BitVector &Reserved,
215  const MachineFunction &MF,
216  const R600RegisterInfo &TRI) const;
217 
218  /// Calculate the "Indirect Address" for the given \p RegIndex and
219  /// \p Channel
220  ///
221  /// We model indirect addressing using a virtual address space that can be
222  /// accessed with loads and stores. The "Indirect Address" is the memory
223  /// address in this virtual address space that maps to the given \p RegIndex
224  /// and \p Channel.
225  unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const;
226 
227 
228  /// \returns The register class to be used for loading and storing values
229  /// from an "Indirect Address" .
231 
232  /// \returns the smallest register index that will be accessed by an indirect
233  /// read or write or -1 if indirect addressing is not used by this program.
234  int getIndirectIndexBegin(const MachineFunction &MF) const;
235 
236  /// \returns the largest register index that will be accessed by an indirect
237  /// read or write or -1 if indirect addressing is not used by this program.
238  int getIndirectIndexEnd(const MachineFunction &MF) const;
239 
240  /// Build instruction(s) for an indirect register write.
241  ///
242  /// \returns The instruction that performs the indirect register write
243  MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
245  unsigned ValueReg, unsigned Address,
246  unsigned OffsetReg) const;
247 
248  /// Build instruction(s) for an indirect register read.
249  ///
250  /// \returns The instruction that performs the indirect register read
251  MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
253  unsigned ValueReg, unsigned Address,
254  unsigned OffsetReg) const;
255 
256  unsigned getMaxAlusPerClause() const;
257 
258  /// buildDefaultInstruction - This function returns a MachineInstr with all
259  /// the instruction modifiers initialized to their default values. You can
260  /// use this function to avoid manually specifying each instruction modifier
261  /// operand when building a new instruction.
262  ///
263  /// \returns a MachineInstr with all the instruction modifiers initialized
264  /// to their default values.
267  unsigned Opcode,
268  unsigned DstReg,
269  unsigned Src0Reg,
270  unsigned Src1Reg = 0) const;
271 
273  MachineInstr *MI,
274  unsigned Slot,
275  unsigned DstReg) const;
276 
279  unsigned DstReg,
280  uint64_t Imm) const;
281 
284  unsigned DstReg, unsigned SrcReg) const;
285 
286  /// Get the index of Op in the MachineInstr.
287  ///
288  /// \returns -1 if the Instruction does not contain the specified \p Op.
289  int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
290 
291  /// Get the index of \p Op for the given Opcode.
292  ///
293  /// \returns -1 if the Instruction does not contain the specified \p Op.
294  int getOperandIdx(unsigned Opcode, unsigned Op) const;
295 
296  /// Helper function for setting instruction flag values.
297  void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const;
298 
299  ///Add one of the MO_FLAG* flags to the specified \p Operand.
300  void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
301 
302  ///Determine if the specified \p Flag is set on this \p Operand.
303  bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
304 
305  /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
306  /// \param Flag The flag being set.
307  ///
308  /// \returns the operand containing the flags for this instruction.
309  MachineOperand &getFlagOp(MachineInstr &MI, unsigned SrcIdx = 0,
310  unsigned Flag = 0) const;
311 
312  /// Clear the specified flag on the instruction.
313  void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const;
314 
315  // Helper functions that check the opcode for status information
316  bool isRegisterStore(const MachineInstr &MI) const {
317  return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_STORE;
318  }
319 
320  bool isRegisterLoad(const MachineInstr &MI) const {
321  return get(MI.getOpcode()).TSFlags & R600InstrFlags::REGISTER_LOAD;
322  }
323 };
324 
325 namespace R600 {
326 
327 int getLDSNoRetOp(uint16_t Opcode);
328 
329 } //End namespace AMDGPU
330 
331 } // End llvm namespace
332 
333 #endif
llvm::R600InstrInfo::isALUInstr
bool isALUInstr(unsigned Opcode) const
Definition: R600InstrInfo.cpp:112
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::R600InstrInfo::setImmOperand
void setImmOperand(MachineInstr &MI, unsigned Op, int64_t Imm) const
Helper function for setting instruction flag values.
Definition: R600InstrInfo.cpp:1362
llvm::R600InstrInfo::fitsReadPortLimitations
bool fitsReadPortLimitations(const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first ...
Definition: R600InstrInfo.cpp:511
llvm::R600InstrInfo::isVectorOnly
bool isVectorOnly(unsigned Opcode) const
Definition: R600InstrInfo.cpp:166
llvm::R600InstrInfo::getIndirectIndexEnd
int getIndirectIndexEnd(const MachineFunction &MF) const
Definition: R600InstrInfo.cpp:1185
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::R600InstrInfo::isFlagSet
bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const
Determine if the specified Flag is set on this Operand.
llvm::R600InstrInfo::removeBranch
unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
Definition: R600InstrInfo.cpp:776
llvm::R600InstrInfo::getOperandIdx
int getOperandIdx(const MachineInstr &MI, unsigned Op) const
Get the index of Op in the MachineInstr.
Definition: R600InstrInfo.cpp:1354
TargetInstrInfo.h
llvm::R600InstrInfo::isProfitableToIfCvt
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override
Definition: R600InstrInfo.cpp:873
llvm::R600InstrInfo::isRegisterLoad
bool isRegisterLoad(const MachineInstr &MI) const
Definition: R600InstrInfo.h:320
llvm::R600InstrInfo::isLegalUpTo
unsigned isLegalUpTo(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction G...
Definition: R600InstrInfo.cpp:405
llvm::R600InstrInfo::isLDSInstr
bool isLDSInstr(unsigned Opcode) const
Definition: R600InstrInfo.cpp:126
llvm::R600InstrInfo::usesVertexCache
bool usesVertexCache(unsigned Opcode) const
Definition: R600InstrInfo.cpp:178
llvm::R600InstrInfo::canBeConsideredALU
bool canBeConsideredALU(const MachineInstr &MI) const
Definition: R600InstrInfo.cpp:138
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::R600InstrInfo::readsLDSSrcReg
bool readsLDSSrcReg(const MachineInstr &MI) const
Definition: R600InstrInfo.cpp:217
R600GenInstrInfo
llvm::R600RegisterInfo
Definition: R600RegisterInfo.h:22
llvm::R600InstrInfo::ALU_VEC_102_SCL_221
@ ALU_VEC_102_SCL_221
Definition: R600InstrInfo.h:63
llvm::R600InstrInfo::buildMovImm
MachineInstr * buildMovImm(MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const
Definition: R600InstrInfo.cpp:1338
llvm::R600InstrInfo::isExport
bool isExport(unsigned Opcode) const
Definition: R600InstrInfo.cpp:174
llvm::R600InstrInfo::buildMovInstr
MachineInstr * buildMovInstr(MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const
Definition: R600InstrInfo.cpp:1348
llvm::R600InstrFlags::REGISTER_LOAD
@ REGISTER_LOAD
Definition: R600InstrInfo.h:28
llvm::R600InstrInfo::definesAddressRegister
bool definesAddressRegister(MachineInstr &MI) const
Definition: R600InstrInfo.cpp:213
llvm::R600InstrInfo::PredicateInstruction
bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override
Definition: R600InstrInfo.cpp:945
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::DFAPacketizer
Definition: DFAPacketizer.h:48
llvm::R600InstrInfo::getInstrLatency
unsigned int getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override
Definition: R600InstrInfo.cpp:983
llvm::R600InstrInfo::isVector
bool isVector(const MachineInstr &MI) const
Vector instructions are instructions that must fill all instruction slots within an instruction group...
Definition: R600InstrInfo.cpp:36
llvm::R600InstrInfo::CreateTargetScheduleState
DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const override
Definition: R600InstrInfo.cpp:609
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::MCID::Flag
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:147
llvm::R600InstrInfo::hasInstrModifiers
bool hasInstrModifiers(unsigned Opcode) const
Definition: R600InstrInfo.cpp:118
llvm::R600InstrInfo::expandPostRAPseudo
bool expandPostRAPseudo(MachineInstr &MI) const override
Definition: R600InstrInfo.cpp:997
llvm::BitVector
Definition: BitVector.h:75
llvm::R600InstrInfo::isReductionOp
bool isReductionOp(unsigned opcode) const
Definition: R600InstrInfo.cpp:97
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::R600InstrInfo::reserveIndirectRegisters
void reserveIndirectRegisters(BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
Reserve the registers that may be accessed using indirect addressing.
Definition: R600InstrInfo.cpp:1063
llvm::R600InstrInfo::usesTextureCache
bool usesTextureCache(unsigned Opcode) const
Definition: R600InstrInfo.cpp:188
llvm::R600InstrInfo::isProfitableToUnpredicate
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override
Definition: R600InstrInfo.cpp:900
llvm::R600InstrInfo::getIndirectAddrRegClass
const TargetRegisterClass * getIndirectAddrRegClass() const
Definition: R600InstrInfo.cpp:1083
llvm::R600Subtarget
Definition: R600Subtarget.h:29
llvm::R600InstrInfo::copyPhysReg
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override
Definition: R600InstrInfo.cpp:40
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::R600InstrInfo::clearFlag
void clearFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Clear the specified flag on the instruction.
Definition: R600InstrInfo.cpp:1460
llvm::MachineInstrBuilder
Definition: MachineInstrBuilder.h:69
uint64_t
llvm::R600InstrInfo::FindSwizzleForVectorSlot
bool FindSwizzleForVectorSlot(const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
Definition: R600InstrInfo.cpp:474
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::R600::getLDSNoRetOp
int getLDSNoRetOp(uint16_t Opcode)
llvm::R600InstrInfo::getRegisterInfo
const R600RegisterInfo & getRegisterInfo() const
Definition: R600InstrInfo.h:70
R600RegisterInfo.h
llvm::R600InstrInfo::isCubeOp
bool isCubeOp(unsigned opcode) const
Definition: R600InstrInfo.cpp:101
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::R600InstrFlags::REGISTER_STORE
@ REGISTER_STORE
Definition: R600InstrInfo.h:27
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::R600InstrInfo::getFlagOp
MachineOperand & getFlagOp(MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const
Definition: R600InstrInfo.cpp:1374
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:137
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::R600InstrInfo::isLDSRetInstr
bool isLDSRetInstr(unsigned Opcode) const
Definition: R600InstrInfo.cpp:134
llvm::R600InstrInfo::insertBranch
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
Definition: R600InstrInfo.cpp:729
llvm::BranchProbability
Definition: BranchProbability.h:30
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::R600InstrInfo::ALU_VEC_012_SCL_210
@ ALU_VEC_012_SCL_210
Definition: R600InstrInfo.h:60
llvm::R600InstrInfo::mustBeLastInClause
bool mustBeLastInClause(unsigned Opcode) const
Definition: R600InstrInfo.cpp:199
llvm::R600InstrInfo::isPredicable
bool isPredicable(const MachineInstr &MI) const override
Definition: R600InstrInfo.cpp:850
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::R600InstrInfo::isTransOnly
bool isTransOnly(unsigned Opcode) const
Definition: R600InstrInfo.cpp:156
llvm::R600InstrInfo::calculateIndirectAddress
unsigned calculateIndirectAddress(unsigned RegIndex, unsigned Channel) const
Calculate the "Indirect Address" for the given RegIndex and Channel.
Definition: R600InstrInfo.cpp:991
uint16_t
get
Should compile to something r4 addze r3 instead we get
Definition: README.txt:24
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:348
llvm::R600InstrInfo::R600InstrInfo
R600InstrInfo(const R600Subtarget &)
Definition: R600InstrInfo.cpp:33
llvm::R600InstrInfo::fitsConstReadLimitations
bool fitsConstReadLimitations(const std::vector< MachineInstr * > &) const
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
Definition: R600InstrInfo.cpp:582
llvm::R600InstrInfo::getSrcs
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > getSrcs(MachineInstr &MI) const
Definition: R600InstrInfo.cpp:257
llvm::R600InstrInfo::addFlag
void addFlag(MachineInstr &MI, unsigned Operand, unsigned Flag) const
Add one of the MO_FLAG* flags to the specified Operand.
Definition: R600InstrInfo.cpp:1439
llvm::R600InstrInfo::isProfitableToDupForIfCvt
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override
Definition: R600InstrInfo.cpp:892
llvm::R600InstrInfo::BankSwizzle
BankSwizzle
Definition: R600InstrInfo.h:59
llvm::R600InstrInfo::isPredicated
bool isPredicated(const MachineInstr &MI) const override
Definition: R600InstrInfo.cpp:835
llvm::R600InstrInfo::analyzeBranch
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Definition: R600InstrInfo.cpp:647
llvm::R600InstrInfo::reverseBranchCondition
bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override
Definition: R600InstrInfo.cpp:906
llvm::R600InstrInfo
Definition: R600InstrInfo.h:38
llvm::R600InstrInfo::buildSlotOfVectorInstruction
MachineInstr * buildSlotOfVectorInstruction(MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const
Definition: R600InstrInfo.cpp:1290
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::R600InstrInfo::getMaxAlusPerClause
unsigned getMaxAlusPerClause() const
Definition: R600InstrInfo.cpp:1207
llvm::R600InstrInfo::isRegisterStore
bool isRegisterStore(const MachineInstr &MI) const
Definition: R600InstrInfo.h:316
llvm::R600InstrInfo::getSelIdx
int getSelIdx(unsigned Opcode, unsigned SrcIdx) const
Definition: R600InstrInfo.cpp:233
llvm::R600InstrInfo::isLegalToSplitMBBAt
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override
Definition: R600InstrInfo.cpp:75
llvm::R600InstrInfo::buildDefaultInstruction
MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers ini...
Definition: R600InstrInfo.cpp:1211
llvm::R600InstrInfo::ALU_VEC_201
@ ALU_VEC_201
Definition: R600InstrInfo.h:64
llvm::R600InstrInfo::ClobbersPredicate
bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override
Definition: R600InstrInfo.cpp:939
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::R600InstrInfo::ALU_VEC_120_SCL_212
@ ALU_VEC_120_SCL_212
Definition: R600InstrInfo.h:62
BB
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM BB
Definition: README.txt:39
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::R600InstrInfo::getPredicationCost
unsigned int getPredicationCost(const MachineInstr &) const override
Definition: R600InstrInfo.cpp:979
llvm::R600InstrInfo::getIndirectIndexBegin
int getIndirectIndexBegin(const MachineFunction &MF) const
Definition: R600InstrInfo.cpp:1153
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::R600InstrInfo::ALU_VEC_210
@ ALU_VEC_210
Definition: R600InstrInfo.h:65
llvm::R600InstrInfo::isMov
bool isMov(unsigned Opcode) const
Definition: R600InstrInfo.cpp:86
llvm::R600InstrInfo::usesAddressRegister
bool usesAddressRegister(MachineInstr &MI) const
Definition: R600InstrInfo.cpp:209
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::R600InstrInfo::ALU_VEC_021_SCL_122
@ ALU_VEC_021_SCL_122
Definition: R600InstrInfo.h:61