LLVM
15.0.0git
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#include "Target/AMDGPU/R600InstrInfo.h"
Public Types | |
enum | BankSwizzle { ALU_VEC_012_SCL_210 = 0, ALU_VEC_021_SCL_122, ALU_VEC_120_SCL_212, ALU_VEC_102_SCL_221, ALU_VEC_201, ALU_VEC_210 } |
Public Member Functions | |
R600InstrInfo (const R600Subtarget &) | |
const R600RegisterInfo & | getRegisterInfo () const |
void | copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override |
bool | isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override |
bool | isReductionOp (unsigned opcode) const |
bool | isCubeOp (unsigned opcode) const |
bool | isALUInstr (unsigned Opcode) const |
bool | hasInstrModifiers (unsigned Opcode) const |
bool | isLDSInstr (unsigned Opcode) const |
bool | isLDSRetInstr (unsigned Opcode) const |
bool | canBeConsideredALU (const MachineInstr &MI) const |
bool | isTransOnly (unsigned Opcode) const |
bool | isTransOnly (const MachineInstr &MI) const |
bool | isVectorOnly (unsigned Opcode) const |
bool | isVectorOnly (const MachineInstr &MI) const |
bool | isExport (unsigned Opcode) const |
bool | usesVertexCache (unsigned Opcode) const |
bool | usesVertexCache (const MachineInstr &MI) const |
bool | usesTextureCache (unsigned Opcode) const |
bool | usesTextureCache (const MachineInstr &MI) const |
bool | mustBeLastInClause (unsigned Opcode) const |
bool | usesAddressRegister (MachineInstr &MI) const |
bool | definesAddressRegister (MachineInstr &MI) const |
bool | readsLDSSrcReg (const MachineInstr &MI) const |
int | getSelIdx (unsigned Opcode, unsigned SrcIdx) const |
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > | getSrcs (MachineInstr &MI) const |
unsigned | isLegalUpTo (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const |
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence. More... | |
bool | FindSwizzleForVectorSlot (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const |
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements. More... | |
bool | fitsReadPortLimitations (const std::vector< MachineInstr * > &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const |
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available. More... | |
bool | fitsConstReadLimitations (const std::vector< MachineInstr * > &) const |
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+. More... | |
bool | fitsConstReadLimitations (const std::vector< unsigned > &) const |
Same but using const index set instead of MI set. More... | |
bool | isVector (const MachineInstr &MI) const |
Vector instructions are instructions that must fill all instruction slots within an instruction group. More... | |
bool | isMov (unsigned Opcode) const |
DFAPacketizer * | CreateTargetScheduleState (const TargetSubtargetInfo &) const override |
bool | reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override |
bool | analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override |
unsigned | insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override |
unsigned | removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override |
bool | isPredicated (const MachineInstr &MI) const override |
bool | isPredicable (const MachineInstr &MI) const override |
bool | isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override |
bool | isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override |
bool | isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override |
bool | ClobbersPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const override |
bool | isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override |
bool | PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override |
unsigned int | getPredicationCost (const MachineInstr &) const override |
unsigned int | getInstrLatency (const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const override |
bool | expandPostRAPseudo (MachineInstr &MI) const override |
void | reserveIndirectRegisters (BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const |
Reserve the registers that may be accessed using indirect addressing. More... | |
unsigned | calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const |
Calculate the "Indirect Address" for the given RegIndex and Channel . More... | |
const TargetRegisterClass * | getIndirectAddrRegClass () const |
int | getIndirectIndexBegin (const MachineFunction &MF) const |
int | getIndirectIndexEnd (const MachineFunction &MF) const |
MachineInstrBuilder | buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const |
Build instruction(s) for an indirect register write. More... | |
MachineInstrBuilder | buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const |
Build instruction(s) for an indirect register read. More... | |
unsigned | getMaxAlusPerClause () const |
MachineInstrBuilder | buildDefaultInstruction (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const |
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values. More... | |
MachineInstr * | buildSlotOfVectorInstruction (MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const |
MachineInstr * | buildMovImm (MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const |
MachineInstr * | buildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const |
int | getOperandIdx (const MachineInstr &MI, unsigned Op) const |
Get the index of Op in the MachineInstr. More... | |
int | getOperandIdx (unsigned Opcode, unsigned Op) const |
Get the index of Op for the given Opcode. More... | |
void | setImmOperand (MachineInstr &MI, unsigned Op, int64_t Imm) const |
Helper function for setting instruction flag values. More... | |
void | addFlag (MachineInstr &MI, unsigned Operand, unsigned Flag) const |
Add one of the MO_FLAG* flags to the specified Operand . More... | |
bool | isFlagSet (const MachineInstr &MI, unsigned Operand, unsigned Flag) const |
Determine if the specified Flag is set on this Operand . More... | |
MachineOperand & | getFlagOp (MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const |
void | clearFlag (MachineInstr &MI, unsigned Operand, unsigned Flag) const |
Clear the specified flag on the instruction. More... | |
bool | isRegisterStore (const MachineInstr &MI) const |
bool | isRegisterLoad (const MachineInstr &MI) const |
unsigned | getAddressSpaceForPseudoSourceKind (unsigned Kind) const override |
Definition at line 38 of file R600InstrInfo.h.
Enumerator | |
---|---|
ALU_VEC_012_SCL_210 | |
ALU_VEC_021_SCL_122 | |
ALU_VEC_120_SCL_212 | |
ALU_VEC_102_SCL_221 | |
ALU_VEC_201 | |
ALU_VEC_210 |
Definition at line 59 of file R600InstrInfo.h.
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explicit |
Definition at line 33 of file R600InstrInfo.cpp.
void R600InstrInfo::addFlag | ( | MachineInstr & | MI, |
unsigned | Operand, | ||
unsigned | Flag | ||
) | const |
Add one of the MO_FLAG* flags to the specified Operand
.
Definition at line 1439 of file R600InstrInfo.cpp.
References clearFlag(), get, getFlagOp(), llvm::MachineOperand::getImm(), HAS_NATIVE_OPERANDS, MI, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NOT_LAST, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().
Referenced by insertBranch().
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override |
Definition at line 647 of file R600InstrInfo.cpp.
References llvm::MachineBasicBlock::begin(), Cond, llvm::MachineOperand::CreateReg(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getLastNonDebugInstr(), llvm::MachineOperand::getMBB(), getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, isBranch(), isJump(), isPredicateSetter(), and MBB.
MachineInstrBuilder R600InstrInfo::buildDefaultInstruction | ( | MachineBasicBlock & | MBB, |
MachineBasicBlock::iterator | I, | ||
unsigned | Opcode, | ||
unsigned | DstReg, | ||
unsigned | Src0Reg, | ||
unsigned | Src1Reg = 0 |
||
) | const |
buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values.
You can use this function to avoid manually specifying each instruction modifier operand when building a new instruction.
Definition at line 1211 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), get, I, and MBB.
Referenced by buildMovImm(), buildMovInstr(), buildSlotOfVectorInstruction(), and copyPhysReg().
MachineInstrBuilder R600InstrInfo::buildIndirectRead | ( | MachineBasicBlock * | MBB, |
MachineBasicBlock::iterator | I, | ||
unsigned | ValueReg, | ||
unsigned | Address, | ||
unsigned | OffsetReg | ||
) | const |
Build instruction(s) for an indirect register read.
Definition at line 1119 of file R600InstrInfo.cpp.
MachineInstrBuilder R600InstrInfo::buildIndirectWrite | ( | MachineBasicBlock * | MBB, |
MachineBasicBlock::iterator | I, | ||
unsigned | ValueReg, | ||
unsigned | Address, | ||
unsigned | OffsetReg | ||
) | const |
Build instruction(s) for an indirect register write.
Definition at line 1087 of file R600InstrInfo.cpp.
MachineInstr * R600InstrInfo::buildMovImm | ( | MachineBasicBlock & | BB, |
MachineBasicBlock::iterator | I, | ||
unsigned | DstReg, | ||
uint64_t | Imm | ||
) | const |
Definition at line 1338 of file R600InstrInfo.cpp.
References BB, buildDefaultInstruction(), I, and setImmOperand().
MachineInstr * R600InstrInfo::buildMovInstr | ( | MachineBasicBlock * | MBB, |
MachineBasicBlock::iterator | I, | ||
unsigned | DstReg, | ||
unsigned | SrcReg | ||
) | const |
Definition at line 1348 of file R600InstrInfo.cpp.
References buildDefaultInstruction(), I, and MBB.
Referenced by expandPostRAPseudo().
MachineInstr * R600InstrInfo::buildSlotOfVectorInstruction | ( | MachineBasicBlock & | MBB, |
MachineInstr * | MI, | ||
unsigned | Slot, | ||
unsigned | DstReg | ||
) | const |
Definition at line 1290 of file R600InstrInfo.cpp.
References assert(), buildDefaultInstruction(), llvm::misexpect::clamp(), llvm::R600Subtarget::getGeneration(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), getSlotedOps(), I, llvm::MachineOperand::isImm(), MBB, MI, Operands, llvm::AMDGPUSubtarget::R700, llvm::MachineOperand::setImm(), setImmOperand(), llvm::MachineOperand::setReg(), and write().
unsigned R600InstrInfo::calculateIndirectAddress | ( | unsigned | RegIndex, |
unsigned | Channel | ||
) | const |
Calculate the "Indirect Address" for the given RegIndex
and Channel
.
We model indirect addressing using a virtual address space that can be accessed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex
and Channel
.
Definition at line 991 of file R600InstrInfo.cpp.
References assert().
Referenced by expandPostRAPseudo().
bool R600InstrInfo::canBeConsideredALU | ( | const MachineInstr & | MI | ) | const |
Opcode
represents an ALU instruction or an instruction that will be lowered in ExpandSpecialInstrs Pass. Definition at line 138 of file R600InstrInfo.cpp.
References isALUInstr(), isCubeOp(), isVector(), and MI.
void R600InstrInfo::clearFlag | ( | MachineInstr & | MI, |
unsigned | Operand, | ||
unsigned | Flag | ||
) | const |
Clear the specified flag on the instruction.
Definition at line 1460 of file R600InstrInfo.cpp.
References get, getFlagOp(), llvm::MachineOperand::getImm(), HAS_NATIVE_OPERANDS, MI, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().
Referenced by addFlag(), and removeBranch().
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Definition at line 939 of file R600InstrInfo.cpp.
References isPredicateSetter(), and MI.
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Definition at line 40 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), buildDefaultInstruction(), contains(), llvm::RegState::Define, llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::R600RegisterInfo::getSubRegFromChannel(), I, llvm::RegState::Implicit, MBB, MI, and llvm::MachineOperand::setIsKill().
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Definition at line 609 of file R600InstrInfo.cpp.
References llvm::TargetSubtargetInfo::getInstrItineraryData().
bool R600InstrInfo::definesAddressRegister | ( | MachineInstr & | MI | ) | const |
Definition at line 213 of file R600InstrInfo.cpp.
References MI.
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Definition at line 997 of file R600InstrInfo.cpp.
References buildMovInstr(), calculateIndirectAddress(), llvm::MachineBasicBlock::erase(), llvm::R600RegisterInfo::getHWRegChan(), llvm::R600RegisterInfo::getHWRegIndex(), getIndirectAddrRegClass(), llvm::AMDGPU::getNamedOperandIdx(), isRegisterLoad(), isRegisterStore(), MBB, MI, and val.
bool R600InstrInfo::FindSwizzleForVectorSlot | ( | const std::vector< std::vector< std::pair< int, unsigned > > > & | IGSrcs, |
std::vector< R600InstrInfo::BankSwizzle > & | SwzCandidate, | ||
const std::vector< std::pair< int, unsigned > > & | TransSrcs, | ||
R600InstrInfo::BankSwizzle | TransSwz | ||
) | const |
Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.
Definition at line 474 of file R600InstrInfo.cpp.
References isLegalUpTo(), and NextPossibleSolution().
Referenced by fitsReadPortLimitations().
bool R600InstrInfo::fitsConstReadLimitations | ( | const std::vector< MachineInstr * > & | MIs | ) | const |
An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.
This function check if MI set in input meet this limitations
Definition at line 582 of file R600InstrInfo.cpp.
References contains(), llvm::R600RegisterInfo::getHWRegChan(), getSrcs(), llvm::SmallSet< T, N, C >::insert(), isALUInstr(), MI, and llvm::SmallSet< T, N, C >::size().
bool R600InstrInfo::fitsConstReadLimitations | ( | const std::vector< unsigned > & | Consts | ) | const |
Same but using const index set instead of MI set.
Definition at line 557 of file R600InstrInfo.cpp.
References assert().
bool R600InstrInfo::fitsReadPortLimitations | ( | const std::vector< MachineInstr * > & | MIs, |
const DenseMap< unsigned, unsigned > & | PV, | ||
std::vector< BankSwizzle > & | BS, | ||
bool | isLastAluTrans | ||
) | const |
Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available.
Otherwise returns false and undefined content in BS. isLastAluTrans should be set if the last Alu of MIs will be executed on Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to apply to the last instruction. PV holds GPR to PV registers in the Instruction Group MIs.
Definition at line 511 of file R600InstrInfo.cpp.
References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, ALU_VEC_102_SCL_221, ALU_VEC_120_SCL_212, FindSwizzleForVectorSlot(), getOperandIdx(), isConstCompatible(), MI, and move.
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Definition at line 1474 of file R600InstrInfo.cpp.
References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::PseudoSourceValue::ConstantPool, llvm::PseudoSourceValue::ExternalSymbolCallEntry, llvm::PseudoSourceValue::FixedStack, llvm::PseudoSourceValue::GlobalValueCallEntry, llvm::PseudoSourceValue::GOT, llvm::PseudoSourceValue::JumpTable, llvm_unreachable, llvm::AMDGPUAS::PRIVATE_ADDRESS, llvm::PseudoSourceValue::Stack, and llvm::PseudoSourceValue::TargetCustom.
MachineOperand & R600InstrInfo::getFlagOp | ( | MachineInstr & | MI, |
unsigned | SrcIdx = 0 , |
||
unsigned | Flag = 0 |
||
) | const |
SrcIdx | The register source to set the flag on (e.g src0, src1, src2) |
Flag | The flag being set. |
Definition at line 1374 of file R600InstrInfo.cpp.
References assert(), llvm::misexpect::clamp(), get, GET_FLAG_OPERAND_IDX, getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), llvm::binaryformat::last, MI, MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, R600_InstFlag::OP3, and write().
Referenced by addFlag(), and clearFlag().
const TargetRegisterClass * R600InstrInfo::getIndirectAddrRegClass | ( | ) | const |
Definition at line 1083 of file R600InstrInfo.cpp.
Referenced by expandPostRAPseudo(), and getIndirectIndexBegin().
int R600InstrInfo::getIndirectIndexBegin | ( | const MachineFunction & | MF | ) | const |
Definition at line 1153 of file R600InstrInfo.cpp.
References llvm::TargetRegisterClass::contains(), llvm::MachineFunction::getFrameInfo(), getIndirectAddrRegClass(), llvm::MachineFrameInfo::getNumObjects(), llvm::TargetRegisterClass::getNumRegs(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getRegister(), llvm::MachineRegisterInfo::livein_empty(), llvm::MachineRegisterInfo::liveins(), llvm::max(), and MRI.
Referenced by getIndirectIndexEnd().
int R600InstrInfo::getIndirectIndexEnd | ( | const MachineFunction & | MF | ) | const |
Definition at line 1185 of file R600InstrInfo.cpp.
References llvm::MachineFunction::getFrameInfo(), getIndirectIndexBegin(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineFunction::getSubtarget(), and llvm::MachineFrameInfo::hasVarSizedObjects().
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override |
Definition at line 983 of file R600InstrInfo.cpp.
unsigned R600InstrInfo::getMaxAlusPerClause | ( | ) | const |
Definition at line 1207 of file R600InstrInfo.cpp.
int R600InstrInfo::getOperandIdx | ( | const MachineInstr & | MI, |
unsigned | Op | ||
) | const |
Get the index of Op in the MachineInstr.
Op
. Definition at line 1354 of file R600InstrInfo.cpp.
References MI.
Referenced by buildSlotOfVectorInstruction(), copyPhysReg(), fitsReadPortLimitations(), getFlagOp(), getSelIdx(), getSrcs(), isLDSRetInstr(), PredicateInstruction(), and setImmOperand().
int R600InstrInfo::getOperandIdx | ( | unsigned | Opcode, |
unsigned | Op | ||
) | const |
Get the index of Op
for the given Opcode.
Op
. Definition at line 1358 of file R600InstrInfo.cpp.
References llvm::AMDGPU::getNamedOperandIdx().
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Definition at line 979 of file R600InstrInfo.cpp.
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inline |
Definition at line 70 of file R600InstrInfo.h.
Referenced by llvm::R600Subtarget::getRegisterInfo().
int R600InstrInfo::getSelIdx | ( | unsigned | Opcode, |
unsigned | SrcIdx | ||
) | const |
Definition at line 233 of file R600InstrInfo.cpp.
References getOperandIdx().
SmallVector< std::pair< MachineOperand *, int64_t >, 3 > R600InstrInfo::getSrcs | ( | MachineInstr & | MI | ) | const |
Definition at line 257 of file R600InstrInfo.cpp.
References assert(), llvm::MachineOperand::getImm(), getOperandIdx(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), and MI.
Referenced by fitsConstReadLimitations().
bool R600InstrInfo::hasInstrModifiers | ( | unsigned | Opcode | ) | const |
Definition at line 118 of file R600InstrInfo.cpp.
References get, R600_InstFlag::OP1, R600_InstFlag::OP2, and R600_InstFlag::OP3.
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override |
Definition at line 729 of file R600InstrInfo.cpp.
References addFlag(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), Cond, DL, llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), get, llvm::MachineInstr::getOperand(), llvm::RegState::Kill, MBB, MO_FLAG_PUSH, and llvm::MachineOperand::setImm().
bool R600InstrInfo::isALUInstr | ( | unsigned | Opcode | ) | const |
Opcode
represents an ALU instruction. Definition at line 112 of file R600InstrInfo.cpp.
References R600_InstFlag::ALU_INST, and get.
Referenced by canBeConsideredALU(), fitsConstReadLimitations(), and readsLDSSrcReg().
bool R600InstrInfo::isCubeOp | ( | unsigned | opcode | ) | const |
Definition at line 101 of file R600InstrInfo.cpp.
Referenced by canBeConsideredALU().
bool R600InstrInfo::isExport | ( | unsigned | Opcode | ) | const |
Definition at line 174 of file R600InstrInfo.cpp.
References get, and R600_InstFlag::IS_EXPORT.
bool llvm::R600InstrInfo::isFlagSet | ( | const MachineInstr & | MI, |
unsigned | Operand, | ||
unsigned | Flag | ||
) | const |
Determine if the specified Flag
is set on this Operand
.
bool R600InstrInfo::isLDSInstr | ( | unsigned | Opcode | ) | const |
Definition at line 126 of file R600InstrInfo.cpp.
References get, R600_InstFlag::LDS_1A, R600_InstFlag::LDS_1A1D, and R600_InstFlag::LDS_1A2D.
Referenced by isLDSRetInstr().
bool R600InstrInfo::isLDSRetInstr | ( | unsigned | Opcode | ) | const |
Definition at line 134 of file R600InstrInfo.cpp.
References getOperandIdx(), and isLDSInstr().
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MBBI
can be moved into a new basic. Definition at line 75 of file R600InstrInfo.cpp.
References E, I, llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), and MBBI.
unsigned R600InstrInfo::isLegalUpTo | ( | const std::vector< std::vector< std::pair< int, unsigned > > > & | IGSrcs, |
const std::vector< R600InstrInfo::BankSwizzle > & | Swz, | ||
const std::vector< std::pair< int, unsigned > > & | TransSrcs, | ||
R600InstrInfo::BankSwizzle | TransSwz | ||
) | const |
returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.
Definition at line 405 of file R600InstrInfo.cpp.
References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, llvm::numbers::e, GET_REG_INDEX, getTransSwizzle(), i, j(), Swizzle(), and Vector.
Referenced by FindSwizzleForVectorSlot().
bool R600InstrInfo::isMov | ( | unsigned | Opcode | ) | const |
Definition at line 86 of file R600InstrInfo.cpp.
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Definition at line 850 of file R600InstrInfo.cpp.
References llvm::TargetInstrInfo::isPredicable(), isVector(), and MI.
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Definition at line 835 of file R600InstrInfo.cpp.
References MI.
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Definition at line 892 of file R600InstrInfo.cpp.
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Definition at line 873 of file R600InstrInfo.cpp.
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Definition at line 881 of file R600InstrInfo.cpp.
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Definition at line 900 of file R600InstrInfo.cpp.
bool R600InstrInfo::isReductionOp | ( | unsigned | opcode | ) | const |
Definition at line 97 of file R600InstrInfo.cpp.
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inline |
Definition at line 320 of file R600InstrInfo.h.
References get, MI, and llvm::R600InstrFlags::REGISTER_LOAD.
Referenced by expandPostRAPseudo().
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inline |
Definition at line 316 of file R600InstrInfo.h.
References get, MI, and llvm::R600InstrFlags::REGISTER_STORE.
Referenced by expandPostRAPseudo().
bool R600InstrInfo::isTransOnly | ( | const MachineInstr & | MI | ) | const |
Definition at line 162 of file R600InstrInfo.cpp.
References isTransOnly(), and MI.
bool R600InstrInfo::isTransOnly | ( | unsigned | Opcode | ) | const |
Definition at line 156 of file R600InstrInfo.cpp.
References get, and llvm::R600Subtarget::hasCaymanISA().
Referenced by isTransOnly().
bool R600InstrInfo::isVector | ( | const MachineInstr & | MI | ) | const |
Vector instructions are instructions that must fill all instruction slots within an instruction group.
Definition at line 36 of file R600InstrInfo.cpp.
References get, MI, and R600_InstFlag::VECTOR.
Referenced by canBeConsideredALU(), and isPredicable().
bool R600InstrInfo::isVectorOnly | ( | const MachineInstr & | MI | ) | const |
Definition at line 170 of file R600InstrInfo.cpp.
References isVectorOnly(), and MI.
bool R600InstrInfo::isVectorOnly | ( | unsigned | Opcode | ) | const |
bool R600InstrInfo::mustBeLastInClause | ( | unsigned | Opcode | ) | const |
Definition at line 199 of file R600InstrInfo.cpp.
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Definition at line 945 of file R600InstrInfo.cpp.
References llvm::MachineInstrBuilder::addReg(), getOperandIdx(), getReg(), llvm::RegState::Implicit, MI, and llvm::MachineOperand::setReg().
bool R600InstrInfo::readsLDSSrcReg | ( | const MachineInstr & | MI | ) | const |
Definition at line 217 of file R600InstrInfo.cpp.
References contains(), E, I, isALUInstr(), and MI.
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override |
Definition at line 776 of file R600InstrInfo.cpp.
References assert(), llvm::MachineBasicBlock::begin(), clearFlag(), llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), get, I, MBB, and MO_FLAG_PUSH.
void R600InstrInfo::reserveIndirectRegisters | ( | BitVector & | Reserved, |
const MachineFunction & | MF, | ||
const R600RegisterInfo & | TRI | ||
) | const |
Reserve the registers that may be accessed using indirect addressing.
Definition at line 1063 of file R600InstrInfo.cpp.
References llvm::MachineFunction::getSubtarget().
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override |
Definition at line 906 of file R600InstrInfo.cpp.
References Cond, llvm::MachineOperand::getImm(), llvm::MachineOperand::getReg(), llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().
void R600InstrInfo::setImmOperand | ( | MachineInstr & | MI, |
unsigned | Op, | ||
int64_t | Imm | ||
) | const |
Helper function for setting instruction flag values.
Definition at line 1362 of file R600InstrInfo.cpp.
References assert(), getOperandIdx(), and MI.
Referenced by buildMovImm(), and buildSlotOfVectorInstruction().
bool R600InstrInfo::usesAddressRegister | ( | MachineInstr & | MI | ) | const |
Definition at line 209 of file R600InstrInfo.cpp.
References MI.
bool R600InstrInfo::usesTextureCache | ( | const MachineInstr & | MI | ) | const |
Definition at line 192 of file R600InstrInfo.cpp.
References llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::AMDGPU::isCompute(), MI, usesTextureCache(), and usesVertexCache().
bool R600InstrInfo::usesTextureCache | ( | unsigned | Opcode | ) | const |
Definition at line 188 of file R600InstrInfo.cpp.
References get, llvm::R600Subtarget::hasVertexCache(), IS_TEX, and IS_VTX.
Referenced by usesTextureCache().
bool R600InstrInfo::usesVertexCache | ( | const MachineInstr & | MI | ) | const |
Definition at line 182 of file R600InstrInfo.cpp.
References llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::AMDGPU::isCompute(), MI, and usesVertexCache().
bool R600InstrInfo::usesVertexCache | ( | unsigned | Opcode | ) | const |
Definition at line 178 of file R600InstrInfo.cpp.
References get, llvm::R600Subtarget::hasVertexCache(), and IS_VTX.
Referenced by usesTextureCache(), and usesVertexCache().