#include "Target/AMDGPU/R600InstrInfo.h"

Inheritance diagram for llvm::R600InstrInfo:

Collaboration diagram for llvm::R600InstrInfo:

Public Types
enum	BankSwizzle { ALU_VEC_012_SCL_210 = 0, ALU_VEC_021_SCL_122, ALU_VEC_120_SCL_212, ALU_VEC_102_SCL_221, ALU_VEC_201, ALU_VEC_210 }

Public Member Functions
	R600InstrInfo (const R600Subtarget &)

const R600RegisterInfo &	getRegisterInfo () const

void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override

bool	isLegalToSplitMBBAt (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const override

bool	isReductionOp (unsigned opcode) const

bool	isCubeOp (unsigned opcode) const

bool	isALUInstr (unsigned Opcode) const

bool	hasInstrModifiers (unsigned Opcode) const

bool	isLDSInstr (unsigned Opcode) const

bool	isLDSRetInstr (unsigned Opcode) const

bool	canBeConsideredALU (const MachineInstr &MI) const

bool	isTransOnly (unsigned Opcode) const

bool	isTransOnly (const MachineInstr &MI) const

bool	isVectorOnly (unsigned Opcode) const

bool	isVectorOnly (const MachineInstr &MI) const

bool	isExport (unsigned Opcode) const

bool	usesVertexCache (unsigned Opcode) const

bool	usesVertexCache (const MachineInstr &MI) const

bool	usesTextureCache (unsigned Opcode) const

bool	usesTextureCache (const MachineInstr &MI) const

bool	mustBeLastInClause (unsigned Opcode) const

bool	usesAddressRegister (MachineInstr &MI) const

bool	definesAddressRegister (MachineInstr &MI) const

bool	readsLDSSrcReg (const MachineInstr &MI) const

int	getSelIdx (unsigned Opcode, unsigned SrcIdx) const

SmallVector< std::pair< MachineOperand *, int64_t >, 3 >	getSrcs (MachineInstr &MI) const

unsigned	isLegalUpTo (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, const std::vector< R600InstrInfo::BankSwizzle > &Swz, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
	returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence. More...

bool	FindSwizzleForVectorSlot (const std::vector< std::vector< std::pair< int, unsigned > > > &IGSrcs, std::vector< R600InstrInfo::BankSwizzle > &SwzCandidate, const std::vector< std::pair< int, unsigned > > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const
	Enumerate all possible Swizzle sequence to find one that can meet all read port requirements. More...

bool	fitsReadPortLimitations (const std::vector< MachineInstr *> &MIs, const DenseMap< unsigned, unsigned > &PV, std::vector< BankSwizzle > &BS, bool isLastAluTrans) const
	Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available. More...

bool	fitsConstReadLimitations (const std::vector< MachineInstr *> &) const
	An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+. More...

bool	fitsConstReadLimitations (const std::vector< unsigned > &) const
	Same but using const index set instead of MI set. More...

bool	isVector (const MachineInstr &MI) const
	Vector instructions are instructions that must fill all instruction slots within an instruction group. More...

bool	isMov (unsigned Opcode) const

DFAPacketizer *	CreateTargetScheduleState (const TargetSubtargetInfo &) const override

bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override

bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override

unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemvoed=nullptr) const override

bool	isPredicated (const MachineInstr &MI) const override

bool	isPredicable (const MachineInstr &MI) const override

bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const override

bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const override

bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const override

bool	DefinesPredicate (MachineInstr &MI, std::vector< MachineOperand > &Pred) const override

bool	isProfitableToUnpredicate (MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override

bool	PredicateInstruction (MachineInstr &MI, ArrayRef< MachineOperand > Pred) const override

unsigned int	getPredicationCost (const MachineInstr &) const override

unsigned int	getInstrLatency (const InstrItineraryData ItinData, const MachineInstr &MI, unsigned PredCost=nullptr) const override

bool	expandPostRAPseudo (MachineInstr &MI) const override

void	reserveIndirectRegisters (BitVector &Reserved, const MachineFunction &MF, const R600RegisterInfo &TRI) const
	Reserve the registers that may be accesed using indirect addressing. More...

unsigned	calculateIndirectAddress (unsigned RegIndex, unsigned Channel) const
	Calculate the "Indirect Address" for the given `RegIndex` and `Channel`. More...

const TargetRegisterClass *	getIndirectAddrRegClass () const

int	getIndirectIndexBegin (const MachineFunction &MF) const

int	getIndirectIndexEnd (const MachineFunction &MF) const

MachineInstrBuilder	buildIndirectWrite (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const
	Build instruction(s) for an indirect register write. More...

MachineInstrBuilder	buildIndirectRead (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned ValueReg, unsigned Address, unsigned OffsetReg) const
	Build instruction(s) for an indirect register read. More...

unsigned	getMaxAlusPerClause () const

MachineInstrBuilder	buildDefaultInstruction (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned Opcode, unsigned DstReg, unsigned Src0Reg, unsigned Src1Reg=0) const
	buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values. More...

MachineInstr *	buildSlotOfVectorInstruction (MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) const

MachineInstr *	buildMovImm (MachineBasicBlock &BB, MachineBasicBlock::iterator I, unsigned DstReg, uint64_t Imm) const

MachineInstr *	buildMovInstr (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, unsigned DstReg, unsigned SrcReg) const

int	getOperandIdx (const MachineInstr &MI, unsigned Op) const
	Get the index of Op in the MachineInstr. More...

int	getOperandIdx (unsigned Opcode, unsigned Op) const
	Get the index of `Op` for the given Opcode. More...

void	setImmOperand (MachineInstr &MI, unsigned Op, int64_t Imm) const
	Helper function for setting instruction flag values. More...

void	addFlag (MachineInstr &MI, unsigned Operand, unsigned Flag) const
	Add one of the MO_FLAG* flags to the specified `Operand`. More...

bool	isFlagSet (const MachineInstr &MI, unsigned Operand, unsigned Flag) const
	Determine if the specified `Flag` is set on this `Operand`. More...

MachineOperand &	getFlagOp (MachineInstr &MI, unsigned SrcIdx=0, unsigned Flag=0) const

void	clearFlag (MachineInstr &MI, unsigned Operand, unsigned Flag) const
	Clear the specified flag on the instruction. More...

bool	isRegisterStore (const MachineInstr &MI) const

bool	isRegisterLoad (const MachineInstr &MI) const

unsigned	getAddressSpaceForPseudoSourceKind (unsigned Kind) const override

Detailed Description

Definition at line 39 of file R600InstrInfo.h.

Member Enumeration Documentation

◆ BankSwizzle

enum llvm::R600InstrInfo::BankSwizzle

Enumerator
ALU_VEC_012_SCL_210
ALU_VEC_021_SCL_122
ALU_VEC_120_SCL_212
ALU_VEC_102_SCL_221
ALU_VEC_201
ALU_VEC_210

Definition at line 60 of file R600InstrInfo.h.

Constructor & Destructor Documentation

◆ R600InstrInfo()

R600InstrInfo::R600InstrInfo ( const R600Subtarget & ST )

explicit

Definition at line 54 of file R600InstrInfo.cpp.

Member Function Documentation

◆ addFlag()

void R600InstrInfo::addFlag	(	MachineInstr &	MI,
		unsigned	Operand,
		unsigned	Flag
	)		const

Add one of the MO_FLAG* flags to the specified Operand.

Definition at line 1465 of file R600InstrInfo.cpp.

References clearFlag(), getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NOT_LAST, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().

Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().

◆ analyzeBranch()

bool R600InstrInfo::analyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify
	)		const

override

Definition at line 674 of file R600InstrInfo.cpp.

◆ buildDefaultInstruction()

MachineInstrBuilder R600InstrInfo::buildDefaultInstruction	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		unsigned	Opcode,
		unsigned	DstReg,
		unsigned	Src0Reg,
		unsigned	Src1Reg = `0`
	)		const

buildDefaultInstruction - This function returns a MachineInstr with all the instruction modifiers initialized to their default values.

You can use this function to avoid manually specifying each instruction modifier operand when building a new instruction.

Returns: a MachineInstr with all the instruction modifiers initialized to their default values.

Definition at line 1237 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().

Referenced by buildIndirectRead(), buildIndirectWrite(), buildMovImm(), buildMovInstr(), buildSlotOfVectorInstruction(), copyPhysReg(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().

◆ buildIndirectRead()

MachineInstrBuilder R600InstrInfo::buildIndirectRead	(	MachineBasicBlock *	MBB,
		MachineBasicBlock::iterator	I,
		unsigned	ValueReg,
		unsigned	Address,
		unsigned	OffsetReg
	)		const

Build instruction(s) for an indirect register read.

Returns: The instruction that performs the indirect register read

Definition at line 1145 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), buildDefaultInstruction(), llvm::RegState::Implicit, llvm::RegState::Kill, llvm_unreachable, setImmOperand(), and write().

◆ buildIndirectWrite()

MachineInstrBuilder R600InstrInfo::buildIndirectWrite	(	MachineBasicBlock *	MBB,
		MachineBasicBlock::iterator	I,
		unsigned	ValueReg,
		unsigned	Address,
		unsigned	OffsetReg
	)		const

Build instruction(s) for an indirect register write.

Returns: The instruction that performs the indirect register write

Definition at line 1113 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::Address, buildDefaultInstruction(), I, llvm::RegState::Implicit, llvm::RegState::Kill, llvm_unreachable, setImmOperand(), and write().

◆ buildMovImm()

MachineInstr * R600InstrInfo::buildMovImm	(	MachineBasicBlock &	BB,
		MachineBasicBlock::iterator	I,
		unsigned	DstReg,
		uint64_t	Imm
	)		const

Definition at line 1364 of file R600InstrInfo.cpp.

References buildDefaultInstruction(), and setImmOperand().

Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().

◆ buildMovInstr()

MachineInstr * R600InstrInfo::buildMovInstr	(	MachineBasicBlock *	MBB,
		MachineBasicBlock::iterator	I,
		unsigned	DstReg,
		unsigned	SrcReg
	)		const

Definition at line 1374 of file R600InstrInfo.cpp.

References buildDefaultInstruction().

Referenced by expandPostRAPseudo().

◆ buildSlotOfVectorInstruction()

MachineInstr * R600InstrInfo::buildSlotOfVectorInstruction	(	MachineBasicBlock &	MBB,
		MachineInstr *	MI,
		unsigned	Slot,
		unsigned	DstReg
	)		const

Definition at line 1316 of file R600InstrInfo.cpp.

References assert(), buildDefaultInstruction(), llvm::R600Subtarget::getGeneration(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), getSlotedOps(), llvm::MachineOperand::isImm(), MI, Operands, llvm::AMDGPUSubtarget::R700, llvm::MachineOperand::setImm(), setImmOperand(), llvm::MachineOperand::setReg(), and write().

◆ calculateIndirectAddress()

unsigned R600InstrInfo::calculateIndirectAddress	(	unsigned	RegIndex,
		unsigned	Channel
	)		const

Calculate the "Indirect Address" for the given RegIndex and Channel.

We model indirect addressing using a virtual address space that can be accesed with loads and stores. The "Indirect Address" is the memory address in this virtual address space that maps to the given RegIndex and Channel.

Definition at line 1017 of file R600InstrInfo.cpp.

References assert().

Referenced by expandPostRAPseudo().

◆ canBeConsideredALU()

bool R600InstrInfo::canBeConsideredALU ( const MachineInstr & MI ) const

Returns: true if this Opcode represents an ALU instruction or an instruction that will be lowered in ExpandSpecialInstrs Pass.

Definition at line 159 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), isALUInstr(), isCubeOp(), and isVector().

◆ clearFlag()

void R600InstrInfo::clearFlag	(	MachineInstr &	MI,
		unsigned	Operand,
		unsigned	Flag
	)		const

Clear the specified flag on the instruction.

Definition at line 1486 of file R600InstrInfo.cpp.

References getFlagOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), HAS_NATIVE_OPERANDS, NUM_MO_FLAGS, and llvm::MachineOperand::setImm().

Referenced by addFlag(), and removeBranch().

◆ copyPhysReg()

void R600InstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc
	)		const

override

Definition at line 61 of file R600InstrInfo.cpp.

References buildDefaultInstruction(), contains(), llvm::RegState::Define, llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::AMDGPURegisterInfo::getSubRegFromChannel(), I, llvm::RegState::Implicit, and llvm::MachineOperand::setIsKill().

◆ CreateTargetScheduleState()

DFAPacketizer * R600InstrInfo::CreateTargetScheduleState ( const TargetSubtargetInfo & STI ) const

override

Definition at line 636 of file R600InstrInfo.cpp.

References llvm::TargetSubtargetInfo::getInstrItineraryData().

◆ definesAddressRegister()

bool R600InstrInfo::definesAddressRegister ( MachineInstr & MI ) const

Definition at line 234 of file R600InstrInfo.cpp.

References llvm::MachineInstr::findRegisterDefOperandIdx().

◆ DefinesPredicate()

bool R600InstrInfo::DefinesPredicate	(	MachineInstr &	MI,
		std::vector< MachineOperand > &	Pred
	)		const

override

Definition at line 966 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isPredicateSetter().

◆ expandPostRAPseudo()

bool R600InstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

◆ FindSwizzleForVectorSlot()

bool R600InstrInfo::FindSwizzleForVectorSlot	(	const std::vector< std::vector< std::pair< int, unsigned > > > &	IGSrcs,
		std::vector< R600InstrInfo::BankSwizzle > &	SwzCandidate,
		const std::vector< std::pair< int, unsigned > > &	TransSrcs,
		R600InstrInfo::BankSwizzle	TransSwz
	)		const

Enumerate all possible Swizzle sequence to find one that can meet all read port requirements.

Definition at line 498 of file R600InstrInfo.cpp.

References isLegalUpTo(), and NextPossibleSolution().

Referenced by fitsReadPortLimitations().

◆ fitsConstReadLimitations() [1/2]

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< MachineInstr *> & MIs ) const

An instruction group can only access 2 channel pair (either [XY] or [ZW]) from KCache bank on R700+.

This function check if MI set in input meet this limitations

Definition at line 608 of file R600InstrInfo.cpp.

References contains(), llvm::R600RegisterInfo::getHWRegChan(), llvm::MachineInstr::getOpcode(), getSrcs(), llvm::SmallSet< T, N, C >::insert(), isALUInstr(), and llvm::SmallSet< T, N, C >::size().

Referenced by llvm::R600TargetLowering::PerformDAGCombine(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ fitsConstReadLimitations() [2/2]

bool R600InstrInfo::fitsConstReadLimitations ( const std::vector< unsigned > & Consts ) const

Same but using const index set instead of MI set.

Definition at line 583 of file R600InstrInfo.cpp.

References assert().

◆ fitsReadPortLimitations()

bool R600InstrInfo::fitsReadPortLimitations	(	const std::vector< MachineInstr *> &	MIs,
		const DenseMap< unsigned, unsigned > &	PV,
		std::vector< BankSwizzle > &	BS,
		bool	isLastAluTrans
	)		const

Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210 returns true and the first (in lexical order) BankSwizzle affectation starting from the one already provided in the Instruction Group MIs that fits Read Port limitations in BS if available.

Otherwise returns false and undefined content in BS. isLastAluTrans should be set if the last Alu of MIs will be executed on Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to apply to the last instruction. PV holds GPR to PV registers in the Instruction Group MIs.

Definition at line 535 of file R600InstrInfo.cpp.

References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, ALU_VEC_102_SCL_221, ALU_VEC_120_SCL_212, FindSwizzleForVectorSlot(), getOpcode(), getOperandIdx(), and isConstCompatible().

◆ getAddressSpaceForPseudoSourceKind()

unsigned R600InstrInfo::getAddressSpaceForPseudoSourceKind ( unsigned Kind ) const

override

Definition at line 1500 of file R600InstrInfo.cpp.

References AMDGPUAS::CONSTANT_ADDRESS, llvm::PseudoSourceValue::ConstantPool, llvm::PseudoSourceValue::ExternalSymbolCallEntry, llvm::PseudoSourceValue::FixedStack, llvm::PseudoSourceValue::GlobalValueCallEntry, llvm::PseudoSourceValue::GOT, llvm::PseudoSourceValue::JumpTable, llvm_unreachable, AMDGPUAS::PRIVATE_ADDRESS, llvm::PseudoSourceValue::Stack, and llvm::PseudoSourceValue::TargetCustom.

◆ getFlagOp()

MachineOperand & R600InstrInfo::getFlagOp	(	MachineInstr &	MI,
		unsigned	SrcIdx = `0`,
		unsigned	Flag = `0`
	)		const

Parameters

SrcIdx	The register source to set the flag on (e.g src0, src1, src2)
Flag	The flag being set.

Returns: the operand containing the flags for this instruction.

Definition at line 1400 of file R600InstrInfo.cpp.

References assert(), GET_FLAG_OPERAND_IDX, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), HAS_NATIVE_OPERANDS, llvm::MachineOperand::isImm(), MO_FLAG_ABS, MO_FLAG_CLAMP, MO_FLAG_LAST, MO_FLAG_MASK, MO_FLAG_NEG, MO_FLAG_NOT_LAST, R600_InstFlag::OP3, and write().

Referenced by addFlag(), and clearFlag().

◆ getIndirectAddrRegClass()

const TargetRegisterClass * R600InstrInfo::getIndirectAddrRegClass ( ) const

Returns: The register class to be used for loading and storing values from an "Indirect Address" .

Definition at line 1109 of file R600InstrInfo.cpp.

Referenced by expandPostRAPseudo(), and getIndirectIndexBegin().

◆ getIndirectIndexBegin()

int R600InstrInfo::getIndirectIndexBegin ( const MachineFunction & MF ) const

Returns: the smallest register index that will be accessed by an indirect read or write or -1 if indirect addressing is not used by this program.

Definition at line 1179 of file R600InstrInfo.cpp.

References llvm::TargetRegisterClass::contains(), llvm::MachineFunction::getFrameInfo(), getIndirectAddrRegClass(), llvm::MachineFrameInfo::getNumObjects(), llvm::TargetRegisterClass::getNumRegs(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::getRegister(), llvm::Register::isVirtualRegister(), llvm::MachineRegisterInfo::livein_empty(), llvm::MachineRegisterInfo::liveins(), llvm::max(), MRI, and Reg.

Referenced by getIndirectIndexEnd().

◆ getIndirectIndexEnd()

int R600InstrInfo::getIndirectIndexEnd ( const MachineFunction & MF ) const

Returns: the largest register index that will be accessed by an indirect read or write or -1 if indirect addressing is not used by this program.

Definition at line 1211 of file R600InstrInfo.cpp.

References llvm::R600FrameLowering::getFrameIndexReference(), llvm::MachineFunction::getFrameInfo(), llvm::R600Subtarget::getFrameLowering(), getIndirectIndexBegin(), llvm::MachineFrameInfo::getNumObjects(), llvm::MachineFunction::getSubtarget(), and llvm::MachineFrameInfo::hasVarSizedObjects().

◆ getInstrLatency()

unsigned int R600InstrInfo::getInstrLatency	(	const InstrItineraryData *	ItinData,
		const MachineInstr &	MI,
		unsigned *	PredCost = `nullptr`
	)		const

override

Definition at line 1009 of file R600InstrInfo.cpp.

◆ getMaxAlusPerClause()

unsigned R600InstrInfo::getMaxAlusPerClause ( ) const

Definition at line 1233 of file R600InstrInfo.cpp.

◆ getOperandIdx() [1/2]

int R600InstrInfo::getOperandIdx	(	const MachineInstr &	MI,
		unsigned	Op
	)		const

Get the index of Op in the MachineInstr.

Returns: -1 if the Instruction does not contain the specified Op.

Definition at line 1380 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by buildSlotOfVectorInstruction(), copyPhysReg(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), fitsReadPortLimitations(), getFlagOp(), getSelIdx(), getSrcs(), isLDSRetInstr(), llvm::R600TargetLowering::PerformDAGCombine(), PredicateInstruction(), llvm::R600SchedStrategy::releaseBottomNode(), and setImmOperand().

◆ getOperandIdx() [2/2]

int R600InstrInfo::getOperandIdx	(	unsigned	Opcode,
		unsigned	Op
	)		const

Get the index of Op for the given Opcode.

Returns: -1 if the Instruction does not contain the specified Op.

Definition at line 1384 of file R600InstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

◆ getPredicationCost()

unsigned int R600InstrInfo::getPredicationCost ( const MachineInstr & ) const

override

Definition at line 1005 of file R600InstrInfo.cpp.

◆ getRegisterInfo()

const R600RegisterInfo& llvm::R600InstrInfo::getRegisterInfo ( ) const

inline

Definition at line 71 of file R600InstrInfo.h.

References llvm::LegalityPredicates::isVector().

Referenced by llvm::createR600ISelDag(), and llvm::R600Subtarget::getRegisterInfo().

◆ getSelIdx()

int R600InstrInfo::getSelIdx	(	unsigned	Opcode,
		unsigned	SrcIdx
	)		const

Returns: The operand Index for the Sel operand given an index to one of the instruction's src operands.

Definition at line 254 of file R600InstrInfo.cpp.

References getOperandIdx().

Referenced by llvm::R600TargetLowering::PerformDAGCombine().

◆ getSrcs()

SmallVector< std::pair< MachineOperand *, int64_t >, 3 > R600InstrInfo::getSrcs ( MachineInstr & MI ) const

Returns: a pair for each src of an ALU instructions. The first member of a pair is the register id. If register is ALU_CONST, second member is SEL. If register is ALU_LITERAL, second member is IMM. Otherwise, second member value is undefined.

Definition at line 278 of file R600InstrInfo.cpp.

References assert(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::find(), llvm::R600RegisterInfo::getHWRegChan(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), MI, llvm::SmallVectorTemplateBase< T >::push_back(), and Reg.

Referenced by fitsConstReadLimitations().

◆ hasInstrModifiers()

bool R600InstrInfo::hasInstrModifiers ( unsigned Opcode ) const

Definition at line 139 of file R600InstrInfo.cpp.

References R600_InstFlag::OP1, R600_InstFlag::OP2, and R600_InstFlag::OP3.

◆ insertBranch()

unsigned R600InstrInfo::insertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		ArrayRef< MachineOperand >	Cond,
		const DebugLoc &	DL,
		int *	BytesAdded = `nullptr`
	)		const

override

Definition at line 756 of file R600InstrInfo.cpp.

◆ isALUInstr()

bool R600InstrInfo::isALUInstr ( unsigned Opcode ) const

Returns: true if this Opcode represents an ALU instruction.

Definition at line 133 of file R600InstrInfo.cpp.

References R600_InstFlag::ALU_INST.

Referenced by canBeConsideredALU(), fitsConstReadLimitations(), readsLDSSrcReg(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isCubeOp()

bool R600InstrInfo::isCubeOp ( unsigned opcode ) const

Definition at line 122 of file R600InstrInfo.cpp.

Referenced by canBeConsideredALU(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isExport()

bool R600InstrInfo::isExport ( unsigned Opcode ) const

Definition at line 195 of file R600InstrInfo.cpp.

References R600_InstFlag::IS_EXPORT.

◆ isFlagSet()

bool llvm::R600InstrInfo::isFlagSet	(	const MachineInstr &	MI,
		unsigned	Operand,
		unsigned	Flag
	)		const

Determine if the specified Flag is set on this Operand.

◆ isLDSInstr()

bool R600InstrInfo::isLDSInstr ( unsigned Opcode ) const

Definition at line 147 of file R600InstrInfo.cpp.

References R600_InstFlag::LDS_1A, R600_InstFlag::LDS_1A1D, and R600_InstFlag::LDS_1A2D.

Referenced by isLDSRetInstr(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isLDSRetInstr()

bool R600InstrInfo::isLDSRetInstr ( unsigned Opcode ) const

Definition at line 155 of file R600InstrInfo.cpp.

References getOperandIdx(), and isLDSInstr().

Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().

◆ isLegalToSplitMBBAt()

bool R600InstrInfo::isLegalToSplitMBBAt	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI
	)		const

override

Returns: true if MBBI can be moved into a new basic.

Definition at line 96 of file R600InstrInfo.cpp.

References E, I, llvm::R600RegisterInfo::isPhysRegLiveAcrossClauses(), and llvm::Register::isVirtualRegister().

◆ isLegalUpTo()

unsigned R600InstrInfo::isLegalUpTo	(	const std::vector< std::vector< std::pair< int, unsigned > > > &	IGSrcs,
		const std::vector< R600InstrInfo::BankSwizzle > &	Swz,
		const std::vector< std::pair< int, unsigned > > &	TransSrcs,
		R600InstrInfo::BankSwizzle	TransSwz
	)		const

returns how many MIs (whose inputs are represented by IGSrcs) can be packed in the same Instruction Group while meeting read port limitations given a Swz swizzle sequence.

Definition at line 429 of file R600InstrInfo.cpp.

References ALU_VEC_012_SCL_210, ALU_VEC_021_SCL_122, GET_REG_INDEX, getTransSwizzle(), and Swizzle().

Referenced by FindSwizzleForVectorSlot().

◆ isMov()

bool R600InstrInfo::isMov ( unsigned Opcode ) const

Definition at line 107 of file R600InstrInfo.cpp.

◆ isPredicable()

bool R600InstrInfo::isPredicable ( const MachineInstr & MI ) const

override

Definition at line 877 of file R600InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::TargetInstrInfo::isPredicable(), and isVector().

◆ isPredicated()

bool R600InstrInfo::isPredicated ( const MachineInstr & MI ) const

override

Definition at line 862 of file R600InstrInfo.cpp.

References llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), and Reg.

◆ isProfitableToDupForIfCvt()

bool R600InstrInfo::isProfitableToDupForIfCvt	(	MachineBasicBlock &	MBB,
		unsigned	NumCycles,
		BranchProbability	Probability
	)		const

override

Definition at line 919 of file R600InstrInfo.cpp.

◆ isProfitableToIfCvt() [1/2]

bool R600InstrInfo::isProfitableToIfCvt	(	MachineBasicBlock &	MBB,
		unsigned	NumCycles,
		unsigned	ExtraPredCycles,
		BranchProbability	Probability
	)		const

override

Definition at line 900 of file R600InstrInfo.cpp.

◆ isProfitableToIfCvt() [2/2]

bool R600InstrInfo::isProfitableToIfCvt	(	MachineBasicBlock &	TMBB,
		unsigned	NumTCycles,
		unsigned	ExtraTCycles,
		MachineBasicBlock &	FMBB,
		unsigned	NumFCycles,
		unsigned	ExtraFCycles,
		BranchProbability	Probability
	)		const

override

Definition at line 908 of file R600InstrInfo.cpp.

◆ isProfitableToUnpredicate()

bool R600InstrInfo::isProfitableToUnpredicate	(	MachineBasicBlock &	TMBB,
		MachineBasicBlock &	FMBB
	)		const

override

Definition at line 927 of file R600InstrInfo.cpp.

◆ isReductionOp()

bool R600InstrInfo::isReductionOp ( unsigned opcode ) const

Definition at line 118 of file R600InstrInfo.cpp.

Referenced by llvm::R600SchedStrategy::releaseBottomNode().

◆ isRegisterLoad()

bool llvm::R600InstrInfo::isRegisterLoad ( const MachineInstr & MI ) const

inline

Definition at line 321 of file R600InstrInfo.h.

References llvm::MachineInstr::getOpcode(), and llvm::R600InstrFlags::REGISTER_LOAD.

Referenced by expandPostRAPseudo().

◆ isRegisterStore()

bool llvm::R600InstrInfo::isRegisterStore ( const MachineInstr & MI ) const

inline

Definition at line 317 of file R600InstrInfo.h.

References llvm::MachineInstr::getOpcode(), and llvm::R600InstrFlags::REGISTER_STORE.

Referenced by expandPostRAPseudo().

◆ isTransOnly() [1/2]

bool R600InstrInfo::isTransOnly ( unsigned Opcode ) const

Definition at line 177 of file R600InstrInfo.cpp.

References llvm::R600Subtarget::hasCaymanISA().

Referenced by isTransOnly(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isTransOnly() [2/2]

bool R600InstrInfo::isTransOnly ( const MachineInstr & MI ) const

Definition at line 183 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isTransOnly().

◆ isVector()

bool R600InstrInfo::isVector ( const MachineInstr & MI ) const

Vector instructions are instructions that must fill all instruction slots within an instruction group.

Definition at line 57 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and R600_InstFlag::VECTOR.

Referenced by canBeConsideredALU(), isPredicable(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isVectorOnly() [1/2]

bool R600InstrInfo::isVectorOnly ( unsigned Opcode ) const

Definition at line 187 of file R600InstrInfo.cpp.

Referenced by isVectorOnly(), and llvm::R600SchedStrategy::releaseBottomNode().

◆ isVectorOnly() [2/2]

bool R600InstrInfo::isVectorOnly ( const MachineInstr & MI ) const

Definition at line 191 of file R600InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isVectorOnly().

◆ mustBeLastInClause()

bool R600InstrInfo::mustBeLastInClause ( unsigned Opcode ) const

Definition at line 220 of file R600InstrInfo.cpp.

◆ PredicateInstruction()

bool R600InstrInfo::PredicateInstruction	(	MachineInstr &	MI,
		ArrayRef< MachineOperand >	Pred
	)		const

override

Definition at line 971 of file R600InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::findFirstPredOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), getReg(), llvm::RegState::Implicit, MI, llvm::MachineOperand::setImm(), and llvm::MachineOperand::setReg().

◆ readsLDSSrcReg()

bool R600InstrInfo::readsLDSSrcReg ( const MachineInstr & MI ) const

Definition at line 238 of file R600InstrInfo.cpp.

References contains(), E, llvm::MachineInstr::getOpcode(), I, isALUInstr(), llvm::Register::isVirtualRegister(), llvm::MachineInstr::operands_begin(), and llvm::MachineInstr::operands_end().

Referenced by llvm::R600SchedStrategy::releaseBottomNode().

◆ removeBranch()

unsigned R600InstrInfo::removeBranch	(	MachineBasicBlock &	MBB,
		int *	BytesRemvoed = `nullptr`
	)		const

override

Definition at line 803 of file R600InstrInfo.cpp.

References assert(), llvm::MachineBasicBlock::begin(), clearFlag(), llvm::MachineBasicBlock::end(), findFirstPredicateSetterFrom(), FindLastAluClause(), I, and MO_FLAG_PUSH.

◆ reserveIndirectRegisters()

void R600InstrInfo::reserveIndirectRegisters	(	BitVector &	Reserved,
		const MachineFunction &	MF,
		const R600RegisterInfo &	TRI
	)		const

Reserve the registers that may be accesed using indirect addressing.

Definition at line 1089 of file R600InstrInfo.cpp.

References llvm::R600Subtarget::getFrameLowering(), llvm::AMDGPUFrameLowering::getStackWidth(), and llvm::MachineFunction::getSubtarget().

◆ reverseBranchCondition()

bool R600InstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

override

Definition at line 933 of file R600InstrInfo.cpp.

◆ setImmOperand()

void R600InstrInfo::setImmOperand	(	MachineInstr &	MI,
		unsigned	Op,
		int64_t	Imm
	)		const

Helper function for setting instruction flag values.

Definition at line 1388 of file R600InstrInfo.cpp.

References assert(), llvm::MachineInstr::getOperand(), getOperandIdx(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::setImm().

Referenced by buildIndirectRead(), buildIndirectWrite(), buildMovImm(), buildSlotOfVectorInstruction(), and llvm::R600TargetLowering::EmitInstrWithCustomInserter().

◆ usesAddressRegister()

bool R600InstrInfo::usesAddressRegister ( MachineInstr & MI ) const

Definition at line 230 of file R600InstrInfo.cpp.

References llvm::MachineInstr::findRegisterUseOperandIdx().

◆ usesTextureCache() [1/2]

bool R600InstrInfo::usesTextureCache ( unsigned Opcode ) const

Definition at line 209 of file R600InstrInfo.cpp.

References llvm::R600Subtarget::hasVertexCache(), IS_TEX, and IS_VTX.

Referenced by llvm::R600SchedStrategy::releaseBottomNode(), and usesTextureCache().

◆ usesTextureCache() [2/2]

bool R600InstrInfo::usesTextureCache ( const MachineInstr & MI ) const

Definition at line 213 of file R600InstrInfo.cpp.

References llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::AMDGPU::isCompute(), usesTextureCache(), and usesVertexCache().

◆ usesVertexCache() [1/2]

bool R600InstrInfo::usesVertexCache ( unsigned Opcode ) const

Definition at line 199 of file R600InstrInfo.cpp.

References llvm::R600Subtarget::hasVertexCache(), and IS_VTX.

Referenced by llvm::R600SchedStrategy::releaseBottomNode(), usesTextureCache(), and usesVertexCache().

◆ usesVertexCache() [2/2]

bool R600InstrInfo::usesVertexCache ( const MachineInstr & MI ) const

Definition at line 203 of file R600InstrInfo.cpp.

References llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::AMDGPU::isCompute(), and usesVertexCache().

The documentation for this class was generated from the following files:

lib/Target/AMDGPU/R600InstrInfo.h
lib/Target/AMDGPU/R600InstrInfo.cpp

Public Types

Public Member Functions

Detailed Description

Member Enumeration Documentation

◆ BankSwizzle

Constructor & Destructor Documentation

◆ R600InstrInfo()

Member Function Documentation

◆ addFlag()

◆ analyzeBranch()

◆ buildDefaultInstruction()

◆ buildIndirectRead()

◆ buildIndirectWrite()

◆ buildMovImm()

◆ buildMovInstr()

◆ buildSlotOfVectorInstruction()

◆ calculateIndirectAddress()

◆ canBeConsideredALU()

◆ clearFlag()

◆ copyPhysReg()

◆ CreateTargetScheduleState()

◆ definesAddressRegister()

◆ DefinesPredicate()

◆ expandPostRAPseudo()

◆ FindSwizzleForVectorSlot()

◆ fitsConstReadLimitations() [1/2]

◆ fitsConstReadLimitations() [2/2]

◆ fitsReadPortLimitations()

◆ getAddressSpaceForPseudoSourceKind()

◆ getFlagOp()

◆ getIndirectAddrRegClass()

◆ getIndirectIndexBegin()

◆ getIndirectIndexEnd()

◆ getInstrLatency()

◆ getMaxAlusPerClause()

◆ getOperandIdx() [1/2]

◆ getOperandIdx() [2/2]

◆ getPredicationCost()

◆ getRegisterInfo()

◆ getSelIdx()

◆ getSrcs()

◆ hasInstrModifiers()

◆ insertBranch()

◆ isALUInstr()

◆ isCubeOp()

◆ isExport()

◆ isFlagSet()

◆ isLDSInstr()

◆ isLDSRetInstr()

◆ isLegalToSplitMBBAt()

◆ isLegalUpTo()

◆ isMov()

◆ isPredicable()

◆ isPredicated()

◆ isProfitableToDupForIfCvt()

◆ isProfitableToIfCvt() [1/2]

◆ isProfitableToIfCvt() [2/2]

◆ isProfitableToUnpredicate()

◆ isReductionOp()

◆ isRegisterLoad()

◆ isRegisterStore()

◆ isTransOnly() [1/2]

◆ isTransOnly() [2/2]

◆ isVector()

◆ isVectorOnly() [1/2]

◆ isVectorOnly() [2/2]

◆ mustBeLastInClause()

◆ PredicateInstruction()

◆ readsLDSSrcReg()

◆ removeBranch()

◆ reserveIndirectRegisters()

◆ reverseBranchCondition()

◆ setImmOperand()

◆ usesAddressRegister()

◆ usesTextureCache() [1/2]

◆ usesTextureCache() [2/2]

◆ usesVertexCache() [1/2]

◆ usesVertexCache() [2/2]