LLVM  9.0.0svn
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
14 #define LLVM_TARGET_TARGETINSTRINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
30 #include "llvm/MC/MCInstrInfo.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <utility>
37 #include <vector>
38 
39 namespace llvm {
40 
41 class DFAPacketizer;
42 class InstrItineraryData;
43 class LiveIntervals;
44 class LiveVariables;
45 class MachineMemOperand;
46 class MachineRegisterInfo;
47 class MCAsmInfo;
48 class MCInst;
49 struct MCSchedModel;
50 class Module;
51 class ScheduleDAG;
52 class ScheduleHazardRecognizer;
53 class SDNode;
54 class SelectionDAG;
55 class RegScavenger;
56 class TargetRegisterClass;
57 class TargetRegisterInfo;
58 class TargetSchedModel;
59 class TargetSubtargetInfo;
60 
61 template <class T> class SmallVectorImpl;
62 
63 //---------------------------------------------------------------------------
64 ///
65 /// TargetInstrInfo - Interface to description of machine instruction set
66 ///
67 class TargetInstrInfo : public MCInstrInfo {
68 public:
69  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
70  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
71  : CallFrameSetupOpcode(CFSetupOpcode),
72  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
73  ReturnOpcode(ReturnOpcode) {}
74  TargetInstrInfo(const TargetInstrInfo &) = delete;
75  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
76  virtual ~TargetInstrInfo();
77 
78  static bool isGenericOpcode(unsigned Opc) {
79  return Opc <= TargetOpcode::GENERIC_OP_END;
80  }
81 
82  /// Given a machine instruction descriptor, returns the register
83  /// class constraint for OpNum, or NULL.
84  virtual
85  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
86  const TargetRegisterInfo *TRI,
87  const MachineFunction &MF) const;
88 
89  /// Return true if the instruction is trivially rematerializable, meaning it
90  /// has no side effects and requires no operands that aren't always available.
91  /// This means the only allowed uses are constants and unallocatable physical
92  /// registers so that the instructions result is independent of the place
93  /// in the function.
95  AliasAnalysis *AA = nullptr) const {
96  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
97  (MI.getDesc().isRematerializable() &&
99  isReallyTriviallyReMaterializableGeneric(MI, AA)));
100  }
101 
102 protected:
103  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
104  /// set, this hook lets the target specify whether the instruction is actually
105  /// trivially rematerializable, taking into consideration its operands. This
106  /// predicate must return false if the instruction has any side effects other
107  /// than producing a value, or if it requres any address registers that are
108  /// not always available.
109  /// Requirements must be check as stated in isTriviallyReMaterializable() .
111  AliasAnalysis *AA) const {
112  return false;
113  }
114 
115  /// This method commutes the operands of the given machine instruction MI.
116  /// The operands to be commuted are specified by their indices OpIdx1 and
117  /// OpIdx2.
118  ///
119  /// If a target has any instructions that are commutable but require
120  /// converting to different instructions or making non-trivial changes
121  /// to commute them, this method can be overloaded to do that.
122  /// The default implementation simply swaps the commutable operands.
123  ///
124  /// If NewMI is false, MI is modified in place and returned; otherwise, a
125  /// new machine instruction is created and returned.
126  ///
127  /// Do not call this method for a non-commutable instruction.
128  /// Even though the instruction is commutable, the method may still
129  /// fail to commute the operands, null pointer is returned in such cases.
130  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
131  unsigned OpIdx1,
132  unsigned OpIdx2) const;
133 
134  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
135  /// operand indices to (ResultIdx1, ResultIdx2).
136  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
137  /// predefined to some indices or be undefined (designated by the special
138  /// value 'CommuteAnyOperandIndex').
139  /// The predefined result indices cannot be re-defined.
140  /// The function returns true iff after the result pair redefinition
141  /// the fixed result pair is equal to or equivalent to the source pair of
142  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
143  /// the pairs (x,y) and (y,x) are equivalent.
144  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
145  unsigned CommutableOpIdx1,
146  unsigned CommutableOpIdx2);
147 
148 private:
149  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
150  /// set and the target hook isReallyTriviallyReMaterializable returns false,
151  /// this function does target-independent tests to determine if the
152  /// instruction is really trivially rematerializable.
153  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
154  AliasAnalysis *AA) const;
155 
156 public:
157  /// These methods return the opcode of the frame setup/destroy instructions
158  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
159  /// order to abstract away the difference between operating with a frame
160  /// pointer and operating without, through the use of these two instructions.
161  ///
162  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
163  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
164 
165  /// Returns true if the argument is a frame pseudo instruction.
166  bool isFrameInstr(const MachineInstr &I) const {
167  return I.getOpcode() == getCallFrameSetupOpcode() ||
169  }
170 
171  /// Returns true if the argument is a frame setup pseudo instruction.
172  bool isFrameSetup(const MachineInstr &I) const {
173  return I.getOpcode() == getCallFrameSetupOpcode();
174  }
175 
176  /// Returns size of the frame associated with the given frame instruction.
177  /// For frame setup instruction this is frame that is set up space set up
178  /// after the instruction. For frame destroy instruction this is the frame
179  /// freed by the caller.
180  /// Note, in some cases a call frame (or a part of it) may be prepared prior
181  /// to the frame setup instruction. It occurs in the calls that involve
182  /// inalloca arguments. This function reports only the size of the frame part
183  /// that is set up between the frame setup and destroy pseudo instructions.
184  int64_t getFrameSize(const MachineInstr &I) const {
185  assert(isFrameInstr(I) && "Not a frame instruction");
186  assert(I.getOperand(0).getImm() >= 0);
187  return I.getOperand(0).getImm();
188  }
189 
190  /// Returns the total frame size, which is made up of the space set up inside
191  /// the pair of frame start-stop instructions and the space that is set up
192  /// prior to the pair.
193  int64_t getFrameTotalSize(const MachineInstr &I) const {
194  if (isFrameSetup(I)) {
195  assert(I.getOperand(1).getImm() >= 0 &&
196  "Frame size must not be negative");
197  return getFrameSize(I) + I.getOperand(1).getImm();
198  }
199  return getFrameSize(I);
200  }
201 
202  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
203  unsigned getReturnOpcode() const { return ReturnOpcode; }
204 
205  /// Returns the actual stack pointer adjustment made by an instruction
206  /// as part of a call sequence. By default, only call frame setup/destroy
207  /// instructions adjust the stack, but targets may want to override this
208  /// to enable more fine-grained adjustment, or adjust by a different value.
209  virtual int getSPAdjust(const MachineInstr &MI) const;
210 
211  /// Return true if the instruction is a "coalescable" extension instruction.
212  /// That is, it's like a copy where it's legal for the source to overlap the
213  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
214  /// expected the pre-extension value is available as a subreg of the result
215  /// register. This also returns the sub-register index in SubIdx.
216  virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
217  unsigned &DstReg, unsigned &SubIdx) const {
218  return false;
219  }
220 
221  /// If the specified machine instruction is a direct
222  /// load from a stack slot, return the virtual or physical register number of
223  /// the destination along with the FrameIndex of the loaded stack slot. If
224  /// not, return 0. This predicate must return 0 if the instruction has
225  /// any side effects other than loading from the stack slot.
226  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
227  int &FrameIndex) const {
228  return 0;
229  }
230 
231  /// Optional extension of isLoadFromStackSlot that returns the number of
232  /// bytes loaded from the stack. This must be implemented if a backend
233  /// supports partial stack slot spills/loads to further disambiguate
234  /// what the load does.
235  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
236  int &FrameIndex,
237  unsigned &MemBytes) const {
238  MemBytes = 0;
239  return isLoadFromStackSlot(MI, FrameIndex);
240  }
241 
242  /// Check for post-frame ptr elimination stack locations as well.
243  /// This uses a heuristic so it isn't reliable for correctness.
244  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
245  int &FrameIndex) const {
246  return 0;
247  }
248 
249  /// If the specified machine instruction has a load from a stack slot,
250  /// return true along with the FrameIndices of the loaded stack slot and the
251  /// machine mem operands containing the reference.
252  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
253  /// any instructions that loads from the stack. This is just a hint, as some
254  /// cases may be missed.
255  virtual bool hasLoadFromStackSlot(
256  const MachineInstr &MI,
258 
259  /// If the specified machine instruction is a direct
260  /// store to a stack slot, return the virtual or physical register number of
261  /// the source reg along with the FrameIndex of the loaded stack slot. If
262  /// not, return 0. This predicate must return 0 if the instruction has
263  /// any side effects other than storing to the stack slot.
264  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
265  int &FrameIndex) const {
266  return 0;
267  }
268 
269  /// Optional extension of isStoreToStackSlot that returns the number of
270  /// bytes stored to the stack. This must be implemented if a backend
271  /// supports partial stack slot spills/loads to further disambiguate
272  /// what the store does.
273  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
274  int &FrameIndex,
275  unsigned &MemBytes) const {
276  MemBytes = 0;
277  return isStoreToStackSlot(MI, FrameIndex);
278  }
279 
280  /// Check for post-frame ptr elimination stack locations as well.
281  /// This uses a heuristic, so it isn't reliable for correctness.
282  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
283  int &FrameIndex) const {
284  return 0;
285  }
286 
287  /// If the specified machine instruction has a store to a stack slot,
288  /// return true along with the FrameIndices of the loaded stack slot and the
289  /// machine mem operands containing the reference.
290  /// If not, return false. Unlike isStoreToStackSlot,
291  /// this returns true for any instructions that stores to the
292  /// stack. This is just a hint, as some cases may be missed.
293  virtual bool hasStoreToStackSlot(
294  const MachineInstr &MI,
296 
297  /// Return true if the specified machine instruction
298  /// is a copy of one stack slot to another and has no other effect.
299  /// Provide the identity of the two frame indices.
300  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
301  int &SrcFrameIndex) const {
302  return false;
303  }
304 
305  /// Compute the size in bytes and offset within a stack slot of a spilled
306  /// register or subregister.
307  ///
308  /// \param [out] Size in bytes of the spilled value.
309  /// \param [out] Offset in bytes within the stack slot.
310  /// \returns true if both Size and Offset are successfully computed.
311  ///
312  /// Not all subregisters have computable spill slots. For example,
313  /// subregisters registers may not be byte-sized, and a pair of discontiguous
314  /// subregisters has no single offset.
315  ///
316  /// Targets with nontrivial bigendian implementations may need to override
317  /// this, particularly to support spilled vector registers.
318  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
319  unsigned &Size, unsigned &Offset,
320  const MachineFunction &MF) const;
321 
322  /// Returns the size in bytes of the specified MachineInstr, or ~0U
323  /// when this function is not implemented by a target.
324  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
325  return ~0U;
326  }
327 
328  /// Return true if the instruction is as cheap as a move instruction.
329  ///
330  /// Targets for different archs need to override this, and different
331  /// micro-architectures can also be finely tuned inside.
332  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
333  return MI.isAsCheapAsAMove();
334  }
335 
336  /// Return true if the instruction should be sunk by MachineSink.
337  ///
338  /// MachineSink determines on its own whether the instruction is safe to sink;
339  /// this gives the target a hook to override the default behavior with regards
340  /// to which instructions should be sunk.
341  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
342 
343  /// Re-issue the specified 'original' instruction at the
344  /// specific location targeting a new destination register.
345  /// The register in Orig->getOperand(0).getReg() will be substituted by
346  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
347  /// SubIdx.
348  virtual void reMaterialize(MachineBasicBlock &MBB,
349  MachineBasicBlock::iterator MI, unsigned DestReg,
350  unsigned SubIdx, const MachineInstr &Orig,
351  const TargetRegisterInfo &TRI) const;
352 
353  /// Clones instruction or the whole instruction bundle \p Orig and
354  /// insert into \p MBB before \p InsertBefore. The target may update operands
355  /// that are required to be unique.
356  ///
357  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
359  MachineBasicBlock::iterator InsertBefore,
360  const MachineInstr &Orig) const;
361 
362  /// This method must be implemented by targets that
363  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
364  /// may be able to convert a two-address instruction into one or more true
365  /// three-address instructions on demand. This allows the X86 target (for
366  /// example) to convert ADD and SHL instructions into LEA instructions if they
367  /// would require register copies due to two-addressness.
368  ///
369  /// This method returns a null pointer if the transformation cannot be
370  /// performed, otherwise it returns the last new instruction.
371  ///
373  MachineInstr &MI,
374  LiveVariables *LV) const {
375  return nullptr;
376  }
377 
378  // This constant can be used as an input value of operand index passed to
379  // the method findCommutedOpIndices() to tell the method that the
380  // corresponding operand index is not pre-defined and that the method
381  // can pick any commutable operand.
382  static const unsigned CommuteAnyOperandIndex = ~0U;
383 
384  /// This method commutes the operands of the given machine instruction MI.
385  ///
386  /// The operands to be commuted are specified by their indices OpIdx1 and
387  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
388  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
389  /// any arbitrarily chosen commutable operand. If both arguments are set to
390  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
391  /// operands; then commutes them if such operands could be found.
392  ///
393  /// If NewMI is false, MI is modified in place and returned; otherwise, a
394  /// new machine instruction is created and returned.
395  ///
396  /// Do not call this method for a non-commutable instruction or
397  /// for non-commuable operands.
398  /// Even though the instruction is commutable, the method may still
399  /// fail to commute the operands, null pointer is returned in such cases.
400  MachineInstr *
401  commuteInstruction(MachineInstr &MI, bool NewMI = false,
402  unsigned OpIdx1 = CommuteAnyOperandIndex,
403  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
404 
405  /// Returns true iff the routine could find two commutable operands in the
406  /// given machine instruction.
407  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
408  /// If any of the INPUT values is set to the special value
409  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
410  /// operand, then returns its index in the corresponding argument.
411  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
412  /// looks for 2 commutable operands.
413  /// If INPUT values refer to some operands of MI, then the method simply
414  /// returns true if the corresponding operands are commutable and returns
415  /// false otherwise.
416  ///
417  /// For example, calling this method this way:
418  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
419  /// findCommutedOpIndices(MI, Op1, Op2);
420  /// can be interpreted as a query asking to find an operand that would be
421  /// commutable with the operand#1.
422  virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
423  unsigned &SrcOpIdx2) const;
424 
425  /// A pair composed of a register and a sub-register index.
426  /// Used to give some type checking when modeling Reg:SubReg.
427  struct RegSubRegPair {
428  unsigned Reg;
429  unsigned SubReg;
430 
431  RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
432  : Reg(Reg), SubReg(SubReg) {}
433 
434  bool operator==(const RegSubRegPair& P) const {
435  return Reg == P.Reg && SubReg == P.SubReg;
436  }
437  bool operator!=(const RegSubRegPair& P) const {
438  return !(*this == P);
439  }
440  };
441 
442  /// A pair composed of a pair of a register and a sub-register index,
443  /// and another sub-register index.
444  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
446  unsigned SubIdx;
447 
448  RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
449  unsigned SubIdx = 0)
450  : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
451  };
452 
453  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
454  /// and \p DefIdx.
455  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
456  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
457  /// flag are not added to this list.
458  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
459  /// two elements:
460  /// - %1:sub1, sub0
461  /// - %2<:0>, sub1
462  ///
463  /// \returns true if it is possible to build such an input sequence
464  /// with the pair \p MI, \p DefIdx. False otherwise.
465  ///
466  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
467  ///
468  /// \note The generic implementation does not provide any support for
469  /// MI.isRegSequenceLike(). In other words, one has to override
470  /// getRegSequenceLikeInputs for target specific instructions.
471  bool
472  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
473  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
474 
475  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
476  /// and \p DefIdx.
477  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
478  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
479  /// - %1:sub1, sub0
480  ///
481  /// \returns true if it is possible to build such an input sequence
482  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
483  /// False otherwise.
484  ///
485  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
486  ///
487  /// \note The generic implementation does not provide any support for
488  /// MI.isExtractSubregLike(). In other words, one has to override
489  /// getExtractSubregLikeInputs for target specific instructions.
490  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
491  RegSubRegPairAndIdx &InputReg) const;
492 
493  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
494  /// and \p DefIdx.
495  /// \p [out] BaseReg and \p [out] InsertedReg contain
496  /// the equivalent inputs of INSERT_SUBREG.
497  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
498  /// - BaseReg: %0:sub0
499  /// - InsertedReg: %1:sub1, sub3
500  ///
501  /// \returns true if it is possible to build such an input sequence
502  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
503  /// False otherwise.
504  ///
505  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
506  ///
507  /// \note The generic implementation does not provide any support for
508  /// MI.isInsertSubregLike(). In other words, one has to override
509  /// getInsertSubregLikeInputs for target specific instructions.
510  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
511  RegSubRegPair &BaseReg,
512  RegSubRegPairAndIdx &InsertedReg) const;
513 
514  /// Return true if two machine instructions would produce identical values.
515  /// By default, this is only true when the two instructions
516  /// are deemed identical except for defs. If this function is called when the
517  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
518  /// aggressive checks.
519  virtual bool produceSameValue(const MachineInstr &MI0,
520  const MachineInstr &MI1,
521  const MachineRegisterInfo *MRI = nullptr) const;
522 
523  /// \returns true if a branch from an instruction with opcode \p BranchOpc
524  /// bytes is capable of jumping to a position \p BrOffset bytes away.
525  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
526  int64_t BrOffset) const {
527  llvm_unreachable("target did not implement");
528  }
529 
530  /// \returns The block that branch instruction \p MI jumps to.
532  llvm_unreachable("target did not implement");
533  }
534 
535  /// Insert an unconditional indirect branch at the end of \p MBB to \p
536  /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
537  /// the offset of the position to insert the new branch.
538  ///
539  /// \returns The number of bytes added to the block.
541  MachineBasicBlock &NewDestBB,
542  const DebugLoc &DL,
543  int64_t BrOffset = 0,
544  RegScavenger *RS = nullptr) const {
545  llvm_unreachable("target did not implement");
546  }
547 
548  /// Analyze the branching code at the end of MBB, returning
549  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
550  /// implemented for a target). Upon success, this returns false and returns
551  /// with the following information in various cases:
552  ///
553  /// 1. If this block ends with no branches (it just falls through to its succ)
554  /// just return false, leaving TBB/FBB null.
555  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
556  /// the destination block.
557  /// 3. If this block ends with a conditional branch and it falls through to a
558  /// successor block, it sets TBB to be the branch destination block and a
559  /// list of operands that evaluate the condition. These operands can be
560  /// passed to other TargetInstrInfo methods to create new branches.
561  /// 4. If this block ends with a conditional branch followed by an
562  /// unconditional branch, it returns the 'true' destination in TBB, the
563  /// 'false' destination in FBB, and a list of operands that evaluate the
564  /// condition. These operands can be passed to other TargetInstrInfo
565  /// methods to create new branches.
566  ///
567  /// Note that removeBranch and insertBranch must be implemented to support
568  /// cases where this method returns success.
569  ///
570  /// If AllowModify is true, then this routine is allowed to modify the basic
571  /// block (e.g. delete instructions after the unconditional branch).
572  ///
573  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
574  /// before calling this function.
576  MachineBasicBlock *&FBB,
578  bool AllowModify = false) const {
579  return true;
580  }
581 
582  /// Represents a predicate at the MachineFunction level. The control flow a
583  /// MachineBranchPredicate represents is:
584  ///
585  /// Reg = LHS `Predicate` RHS == ConditionDef
586  /// if Reg then goto TrueDest else goto FalseDest
587  ///
590  PRED_EQ, // True if two values are equal
591  PRED_NE, // True if two values are not equal
592  PRED_INVALID // Sentinel value
593  };
594 
595  ComparePredicate Predicate = PRED_INVALID;
598  MachineBasicBlock *TrueDest = nullptr;
599  MachineBasicBlock *FalseDest = nullptr;
600  MachineInstr *ConditionDef = nullptr;
601 
602  /// SingleUseCondition is true if ConditionDef is dead except for the
603  /// branch(es) at the end of the basic block.
604  ///
605  bool SingleUseCondition = false;
606 
607  explicit MachineBranchPredicate() = default;
608  };
609 
610  /// Analyze the branching code at the end of MBB and parse it into the
611  /// MachineBranchPredicate structure if possible. Returns false on success
612  /// and true on failure.
613  ///
614  /// If AllowModify is true, then this routine is allowed to modify the basic
615  /// block (e.g. delete instructions after the unconditional branch).
616  ///
619  bool AllowModify = false) const {
620  return true;
621  }
622 
623  /// Remove the branching code at the end of the specific MBB.
624  /// This is only invoked in cases where AnalyzeBranch returns success. It
625  /// returns the number of instructions that were removed.
626  /// If \p BytesRemoved is non-null, report the change in code size from the
627  /// removed instructions.
628  virtual unsigned removeBranch(MachineBasicBlock &MBB,
629  int *BytesRemoved = nullptr) const {
630  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
631  }
632 
633  /// Insert branch code into the end of the specified MachineBasicBlock. The
634  /// operands to this method are the same as those returned by AnalyzeBranch.
635  /// This is only invoked in cases where AnalyzeBranch returns success. It
636  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
637  /// report the change in code size from the added instructions.
638  ///
639  /// It is also invoked by tail merging to add unconditional branches in
640  /// cases where AnalyzeBranch doesn't apply because there was no original
641  /// branch to analyze. At least this much must be implemented, else tail
642  /// merging needs to be disabled.
643  ///
644  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
645  /// before calling this function.
646  virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
647  MachineBasicBlock *FBB,
649  const DebugLoc &DL,
650  int *BytesAdded = nullptr) const {
651  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
652  }
653 
655  MachineBasicBlock *DestBB,
656  const DebugLoc &DL,
657  int *BytesAdded = nullptr) const {
658  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
659  BytesAdded);
660  }
661 
662  /// Analyze the loop code, return true if it cannot be understoo. Upon
663  /// success, this function returns false and returns information about the
664  /// induction variable and compare instruction used at the end.
665  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
666  MachineInstr *&CmpInst) const {
667  return true;
668  }
669 
670  /// Generate code to reduce the loop iteration by one and check if the loop
671  /// is finished. Return the value/register of the new loop count. We need
672  /// this function when peeling off one or more iterations of a loop. This
673  /// function assumes the nth iteration is peeled first.
674  virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
675  MachineBasicBlock &PreHeader,
676  MachineInstr *IndVar, MachineInstr &Cmp,
679  unsigned Iter, unsigned MaxIter) const {
680  llvm_unreachable("Target didn't implement ReduceLoopCount");
681  }
682 
683  /// Delete the instruction OldInst and everything after it, replacing it with
684  /// an unconditional branch to NewDest. This is used by the tail merging pass.
686  MachineBasicBlock *NewDest) const;
687 
688  /// Return true if it's legal to split the given basic
689  /// block at the specified instruction (i.e. instruction would be the start
690  /// of a new basic block).
692  MachineBasicBlock::iterator MBBI) const {
693  return true;
694  }
695 
696  /// Return true if it's profitable to predicate
697  /// instructions with accumulated instruction latency of "NumCycles"
698  /// of the specified basic block, where the probability of the instructions
699  /// being executed is given by Probability, and Confidence is a measure
700  /// of our confidence that it will be properly predicted.
701  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
702  unsigned ExtraPredCycles,
703  BranchProbability Probability) const {
704  return false;
705  }
706 
707  /// Second variant of isProfitableToIfCvt. This one
708  /// checks for the case where two basic blocks from true and false path
709  /// of a if-then-else (diamond) are predicated on mutally exclusive
710  /// predicates, where the probability of the true path being taken is given
711  /// by Probability, and Confidence is a measure of our confidence that it
712  /// will be properly predicted.
713  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
714  unsigned ExtraTCycles,
715  MachineBasicBlock &FMBB, unsigned NumFCycles,
716  unsigned ExtraFCycles,
717  BranchProbability Probability) const {
718  return false;
719  }
720 
721  /// Return true if it's profitable for if-converter to duplicate instructions
722  /// of specified accumulated instruction latencies in the specified MBB to
723  /// enable if-conversion.
724  /// The probability of the instructions being executed is given by
725  /// Probability, and Confidence is a measure of our confidence that it
726  /// will be properly predicted.
728  unsigned NumCycles,
729  BranchProbability Probability) const {
730  return false;
731  }
732 
733  /// Return true if it's profitable to unpredicate
734  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
735  /// exclusive predicates.
736  /// e.g.
737  /// subeq r0, r1, #1
738  /// addne r0, r1, #1
739  /// =>
740  /// sub r0, r1, #1
741  /// addne r0, r1, #1
742  ///
743  /// This may be profitable is conditional instructions are always executed.
745  MachineBasicBlock &FMBB) const {
746  return false;
747  }
748 
749  /// Return true if it is possible to insert a select
750  /// instruction that chooses between TrueReg and FalseReg based on the
751  /// condition code in Cond.
752  ///
753  /// When successful, also return the latency in cycles from TrueReg,
754  /// FalseReg, and Cond to the destination register. In most cases, a select
755  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
756  ///
757  /// Some x86 implementations have 2-cycle cmov instructions.
758  ///
759  /// @param MBB Block where select instruction would be inserted.
760  /// @param Cond Condition returned by AnalyzeBranch.
761  /// @param TrueReg Virtual register to select when Cond is true.
762  /// @param FalseReg Virtual register to select when Cond is false.
763  /// @param CondCycles Latency from Cond+Branch to select output.
764  /// @param TrueCycles Latency from TrueReg to select output.
765  /// @param FalseCycles Latency from FalseReg to select output.
766  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
767  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
768  unsigned FalseReg, int &CondCycles,
769  int &TrueCycles, int &FalseCycles) const {
770  return false;
771  }
772 
773  /// Insert a select instruction into MBB before I that will copy TrueReg to
774  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
775  ///
776  /// This function can only be called after canInsertSelect() returned true.
777  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
778  /// that the same flags or registers required by Cond are available at the
779  /// insertion point.
780  ///
781  /// @param MBB Block where select instruction should be inserted.
782  /// @param I Insertion point.
783  /// @param DL Source location for debugging.
784  /// @param DstReg Virtual register to be defined by select instruction.
785  /// @param Cond Condition as computed by AnalyzeBranch.
786  /// @param TrueReg Virtual register to copy when Cond is true.
787  /// @param FalseReg Virtual register to copy when Cons is false.
788  virtual void insertSelect(MachineBasicBlock &MBB,
790  unsigned DstReg, ArrayRef<MachineOperand> Cond,
791  unsigned TrueReg, unsigned FalseReg) const {
792  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
793  }
794 
795  /// Analyze the given select instruction, returning true if
796  /// it cannot be understood. It is assumed that MI->isSelect() is true.
797  ///
798  /// When successful, return the controlling condition and the operands that
799  /// determine the true and false result values.
800  ///
801  /// Result = SELECT Cond, TrueOp, FalseOp
802  ///
803  /// Some targets can optimize select instructions, for example by predicating
804  /// the instruction defining one of the operands. Such targets should set
805  /// Optimizable.
806  ///
807  /// @param MI Select instruction to analyze.
808  /// @param Cond Condition controlling the select.
809  /// @param TrueOp Operand number of the value selected when Cond is true.
810  /// @param FalseOp Operand number of the value selected when Cond is false.
811  /// @param Optimizable Returned as true if MI is optimizable.
812  /// @returns False on success.
813  virtual bool analyzeSelect(const MachineInstr &MI,
815  unsigned &TrueOp, unsigned &FalseOp,
816  bool &Optimizable) const {
817  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
818  return true;
819  }
820 
821  /// Given a select instruction that was understood by
822  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
823  /// merging it with one of its operands. Returns NULL on failure.
824  ///
825  /// When successful, returns the new select instruction. The client is
826  /// responsible for deleting MI.
827  ///
828  /// If both sides of the select can be optimized, PreferFalse is used to pick
829  /// a side.
830  ///
831  /// @param MI Optimizable select instruction.
832  /// @param NewMIs Set that record all MIs in the basic block up to \p
833  /// MI. Has to be updated with any newly created MI or deleted ones.
834  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
835  /// @returns Optimized instruction or NULL.
838  bool PreferFalse = false) const {
839  // This function must be implemented if Optimizable is ever set.
840  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
841  }
842 
843  /// Emit instructions to copy a pair of physical registers.
844  ///
845  /// This function should support copies within any legal register class as
846  /// well as any cross-class copies created during instruction selection.
847  ///
848  /// The source and destination registers may overlap, which may require a
849  /// careful implementation when multiple copy instructions are required for
850  /// large registers. See for example the ARM target.
851  virtual void copyPhysReg(MachineBasicBlock &MBB,
853  unsigned DestReg, unsigned SrcReg,
854  bool KillSrc) const {
855  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
856  }
857 
858 protected:
859  /// Target-dependent implemenation for IsCopyInstr.
860  /// If the specific machine instruction is a instruction that moves/copies
861  /// value from one register to another register return true along with
862  /// @Source machine operand and @Destination machine operand.
863  virtual bool isCopyInstrImpl(const MachineInstr &MI,
864  const MachineOperand *&Source,
865  const MachineOperand *&Destination) const {
866  return false;
867  }
868 
869 public:
870  /// If the specific machine instruction is a instruction that moves/copies
871  /// value from one register to another register return true along with
872  /// @Source machine operand and @Destination machine operand.
873  /// For COPY-instruction the method naturally returns true, for all other
874  /// instructions the method calls target-dependent implementation.
876  const MachineOperand *&Destination) const {
877  if (MI.isCopy()) {
878  Destination = &MI.getOperand(0);
879  Source = &MI.getOperand(1);
880  return true;
881  }
882  return isCopyInstrImpl(MI, Source, Destination);
883  }
884 
885  /// Store the specified register of the given register class to the specified
886  /// stack frame index. The store instruction is to be added to the given
887  /// machine basic block before the specified machine instruction. If isKill
888  /// is true, the register operand is the last use and must be marked kill.
891  unsigned SrcReg, bool isKill, int FrameIndex,
892  const TargetRegisterClass *RC,
893  const TargetRegisterInfo *TRI) const {
894  llvm_unreachable("Target didn't implement "
895  "TargetInstrInfo::storeRegToStackSlot!");
896  }
897 
898  /// Load the specified register of the given register class from the specified
899  /// stack frame index. The load instruction is to be added to the given
900  /// machine basic block before the specified machine instruction.
903  unsigned DestReg, int FrameIndex,
904  const TargetRegisterClass *RC,
905  const TargetRegisterInfo *TRI) const {
906  llvm_unreachable("Target didn't implement "
907  "TargetInstrInfo::loadRegFromStackSlot!");
908  }
909 
910  /// This function is called for all pseudo instructions
911  /// that remain after register allocation. Many pseudo instructions are
912  /// created to help register allocation. This is the place to convert them
913  /// into real instructions. The target can edit MI in place, or it can insert
914  /// new instructions and erase MI. The function should return true if
915  /// anything was changed.
916  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
917 
918  /// Check whether the target can fold a load that feeds a subreg operand
919  /// (or a subreg operand that feeds a store).
920  /// For example, X86 may want to return true if it can fold
921  /// movl (%esp), %eax
922  /// subb, %al, ...
923  /// Into:
924  /// subb (%esp), ...
925  ///
926  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
927  /// reject subregs - but since this behavior used to be enforced in the
928  /// target-independent code, moving this responsibility to the targets
929  /// has the potential of causing nasty silent breakage in out-of-tree targets.
930  virtual bool isSubregFoldable() const { return false; }
931 
932  /// Attempt to fold a load or store of the specified stack
933  /// slot into the specified machine instruction for the specified operand(s).
934  /// If this is possible, a new instruction is returned with the specified
935  /// operand folded, otherwise NULL is returned.
936  /// The new instruction is inserted before MI, and the client is responsible
937  /// for removing the old instruction.
938  /// If VRM is passed, the assigned physregs can be inspected by target to
939  /// decide on using an opcode (note that those assignments can still change).
941  int FI,
942  LiveIntervals *LIS = nullptr,
943  VirtRegMap *VRM = nullptr) const;
944 
945  /// Same as the previous version except it allows folding of any load and
946  /// store from / to any address, not just from a specific stack slot.
948  MachineInstr &LoadMI,
949  LiveIntervals *LIS = nullptr) const;
950 
951  /// Return true when there is potentially a faster code sequence
952  /// for an instruction chain ending in \p Root. All potential patterns are
953  /// returned in the \p Pattern vector. Pattern should be sorted in priority
954  /// order since the pattern evaluator stops checking as soon as it finds a
955  /// faster sequence.
956  /// \param Root - Instruction that could be combined with one of its operands
957  /// \param Patterns - Vector of possible combination patterns
958  virtual bool getMachineCombinerPatterns(
959  MachineInstr &Root,
961 
962  /// Return true when a code sequence can improve throughput. It
963  /// should be called only for instructions in loops.
964  /// \param Pattern - combiner pattern
965  virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
966 
967  /// Return true if the input \P Inst is part of a chain of dependent ops
968  /// that are suitable for reassociation, otherwise return false.
969  /// If the instruction's operands must be commuted to have a previous
970  /// instruction of the same type define the first source operand, \P Commuted
971  /// will be set to true.
972  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
973 
974  /// Return true when \P Inst is both associative and commutative.
975  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
976  return false;
977  }
978 
979  /// Return true when \P Inst has reassociable operands in the same \P MBB.
980  virtual bool hasReassociableOperands(const MachineInstr &Inst,
981  const MachineBasicBlock *MBB) const;
982 
983  /// Return true when \P Inst has reassociable sibling.
984  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
985 
986  /// When getMachineCombinerPatterns() finds patterns, this function generates
987  /// the instructions that could replace the original code sequence. The client
988  /// has to decide whether the actual replacement is beneficial or not.
989  /// \param Root - Instruction that could be combined with one of its operands
990  /// \param Pattern - Combination pattern for Root
991  /// \param InsInstrs - Vector of new instructions that implement P
992  /// \param DelInstrs - Old instructions, including Root, that could be
993  /// replaced by InsInstr
994  /// \param InstIdxForVirtReg - map of virtual register to instruction in
995  /// InsInstr that defines it
996  virtual void genAlternativeCodeSequence(
997  MachineInstr &Root, MachineCombinerPattern Pattern,
1000  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1001 
1002  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1003  /// reduce critical path length.
1004  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1005  MachineCombinerPattern Pattern,
1008  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1009 
1010  /// This is an architecture-specific helper function of reassociateOps.
1011  /// Set special operand attributes for new instructions after reassociation.
1012  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1013  MachineInstr &NewMI1,
1014  MachineInstr &NewMI2) const {}
1015 
1016  /// Return true when a target supports MachineCombiner.
1017  virtual bool useMachineCombiner() const { return false; }
1018 
1019  /// Return true if the given SDNode can be copied during scheduling
1020  /// even if it has glue.
1021  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1022 
1023 protected:
1024  /// Target-dependent implementation for foldMemoryOperand.
1025  /// Target-independent code in foldMemoryOperand will
1026  /// take care of adding a MachineMemOperand to the newly created instruction.
1027  /// The instruction and any auxiliary instructions necessary will be inserted
1028  /// at InsertPt.
1029  virtual MachineInstr *
1031  ArrayRef<unsigned> Ops,
1033  LiveIntervals *LIS = nullptr,
1034  VirtRegMap *VRM = nullptr) const {
1035  return nullptr;
1036  }
1037 
1038  /// Target-dependent implementation for foldMemoryOperand.
1039  /// Target-independent code in foldMemoryOperand will
1040  /// take care of adding a MachineMemOperand to the newly created instruction.
1041  /// The instruction and any auxiliary instructions necessary will be inserted
1042  /// at InsertPt.
1045  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1046  LiveIntervals *LIS = nullptr) const {
1047  return nullptr;
1048  }
1049 
1050  /// Target-dependent implementation of getRegSequenceInputs.
1051  ///
1052  /// \returns true if it is possible to build the equivalent
1053  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1054  ///
1055  /// \pre MI.isRegSequenceLike().
1056  ///
1057  /// \see TargetInstrInfo::getRegSequenceInputs.
1059  const MachineInstr &MI, unsigned DefIdx,
1060  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1061  return false;
1062  }
1063 
1064  /// Target-dependent implementation of getExtractSubregInputs.
1065  ///
1066  /// \returns true if it is possible to build the equivalent
1067  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1068  ///
1069  /// \pre MI.isExtractSubregLike().
1070  ///
1071  /// \see TargetInstrInfo::getExtractSubregInputs.
1073  unsigned DefIdx,
1074  RegSubRegPairAndIdx &InputReg) const {
1075  return false;
1076  }
1077 
1078  /// Target-dependent implementation of getInsertSubregInputs.
1079  ///
1080  /// \returns true if it is possible to build the equivalent
1081  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1082  ///
1083  /// \pre MI.isInsertSubregLike().
1084  ///
1085  /// \see TargetInstrInfo::getInsertSubregInputs.
1086  virtual bool
1087  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1088  RegSubRegPair &BaseReg,
1089  RegSubRegPairAndIdx &InsertedReg) const {
1090  return false;
1091  }
1092 
1093 public:
1094  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1095  /// (e.g. stack) the target returns the corresponding address space.
1096  virtual unsigned
1098  return 0;
1099  }
1100 
1101  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1102  /// a store or a load and a store into two or more instruction. If this is
1103  /// possible, returns true as well as the new instructions by reference.
1104  virtual bool
1106  bool UnfoldLoad, bool UnfoldStore,
1107  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1108  return false;
1109  }
1110 
1112  SmallVectorImpl<SDNode *> &NewNodes) const {
1113  return false;
1114  }
1115 
1116  /// Returns the opcode of the would be new
1117  /// instruction after load / store are unfolded from an instruction of the
1118  /// specified opcode. It returns zero if the specified unfolding is not
1119  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1120  /// index of the operand which will hold the register holding the loaded
1121  /// value.
1122  virtual unsigned
1123  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1124  unsigned *LoadRegIndex = nullptr) const {
1125  return 0;
1126  }
1127 
1128  /// This is used by the pre-regalloc scheduler to determine if two loads are
1129  /// loading from the same base address. It should only return true if the base
1130  /// pointers are the same and the only differences between the two addresses
1131  /// are the offset. It also returns the offsets by reference.
1132  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1133  int64_t &Offset1,
1134  int64_t &Offset2) const {
1135  return false;
1136  }
1137 
1138  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1139  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1140  /// On some targets if two loads are loading from
1141  /// addresses in the same cache line, it's better if they are scheduled
1142  /// together. This function takes two integers that represent the load offsets
1143  /// from the common base address. It returns true if it decides it's desirable
1144  /// to schedule the two loads together. "NumLoads" is the number of loads that
1145  /// have already been scheduled after Load1.
1146  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1147  int64_t Offset1, int64_t Offset2,
1148  unsigned NumLoads) const {
1149  return false;
1150  }
1151 
1152  /// Get the base operand and byte offset of an instruction that reads/writes
1153  /// memory.
1154  virtual bool getMemOperandWithOffset(const MachineInstr &MI,
1155  const MachineOperand *&BaseOp,
1156  int64_t &Offset,
1157  const TargetRegisterInfo *TRI) const {
1158  return false;
1159  }
1160 
1161  /// Return true if the instruction contains a base register and offset. If
1162  /// true, the function also sets the operand position in the instruction
1163  /// for the base register and offset.
1164  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1165  unsigned &BasePos,
1166  unsigned &OffsetPos) const {
1167  return false;
1168  }
1169 
1170  /// If the instruction is an increment of a constant value, return the amount.
1171  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1172  return false;
1173  }
1174 
1175  /// Returns true if the two given memory operations should be scheduled
1176  /// adjacent. Note that you have to add:
1177  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1178  /// or
1179  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1180  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1181  virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1,
1182  const MachineOperand &BaseOp2,
1183  unsigned NumLoads) const {
1184  llvm_unreachable("target did not implement shouldClusterMemOps()");
1185  }
1186 
1187  /// Reverses the branch condition of the specified condition list,
1188  /// returning false on success and true if it cannot be reversed.
1189  virtual bool
1191  return true;
1192  }
1193 
1194  /// Insert a noop into the instruction stream at the specified point.
1195  virtual void insertNoop(MachineBasicBlock &MBB,
1196  MachineBasicBlock::iterator MI) const;
1197 
1198  /// Return the noop instruction to use for a noop.
1199  virtual void getNoop(MCInst &NopInst) const;
1200 
1201  /// Return true for post-incremented instructions.
1202  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1203 
1204  /// Returns true if the instruction is already predicated.
1205  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1206 
1207  /// Returns true if the instruction is a
1208  /// terminator instruction that has not been predicated.
1209  virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1210 
1211  /// Returns true if MI is an unconditional tail call.
1212  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1213  return false;
1214  }
1215 
1216  /// Returns true if the tail call can be made conditional on BranchCond.
1218  const MachineInstr &TailCall) const {
1219  return false;
1220  }
1221 
1222  /// Replace the conditional branch in MBB with a conditional tail call.
1225  const MachineInstr &TailCall) const {
1226  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1227  }
1228 
1229  /// Convert the instruction into a predicated instruction.
1230  /// It returns true if the operation was successful.
1231  virtual bool PredicateInstruction(MachineInstr &MI,
1232  ArrayRef<MachineOperand> Pred) const;
1233 
1234  /// Returns true if the first specified predicate
1235  /// subsumes the second, e.g. GE subsumes GT.
1237  ArrayRef<MachineOperand> Pred2) const {
1238  return false;
1239  }
1240 
1241  /// If the specified instruction defines any predicate
1242  /// or condition code register(s) used for predication, returns true as well
1243  /// as the definition predicate(s) by reference.
1244  virtual bool DefinesPredicate(MachineInstr &MI,
1245  std::vector<MachineOperand> &Pred) const {
1246  return false;
1247  }
1248 
1249  /// Return true if the specified instruction can be predicated.
1250  /// By default, this returns true for every instruction with a
1251  /// PredicateOperand.
1252  virtual bool isPredicable(const MachineInstr &MI) const {
1253  return MI.getDesc().isPredicable();
1254  }
1255 
1256  /// Return true if it's safe to move a machine
1257  /// instruction that defines the specified register class.
1258  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1259  return true;
1260  }
1261 
1262  /// Test if the given instruction should be considered a scheduling boundary.
1263  /// This primarily includes labels and terminators.
1264  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1265  const MachineBasicBlock *MBB,
1266  const MachineFunction &MF) const;
1267 
1268  /// Measure the specified inline asm to determine an approximation of its
1269  /// length.
1270  virtual unsigned getInlineAsmLength(
1271  const char *Str, const MCAsmInfo &MAI,
1272  const TargetSubtargetInfo *STI = nullptr) const;
1273 
1274  /// Allocate and return a hazard recognizer to use for this target when
1275  /// scheduling the machine instructions before register allocation.
1276  virtual ScheduleHazardRecognizer *
1278  const ScheduleDAG *DAG) const;
1279 
1280  /// Allocate and return a hazard recognizer to use for this target when
1281  /// scheduling the machine instructions before register allocation.
1282  virtual ScheduleHazardRecognizer *
1284  const ScheduleDAG *DAG) const;
1285 
1286  /// Allocate and return a hazard recognizer to use for this target when
1287  /// scheduling the machine instructions after register allocation.
1288  virtual ScheduleHazardRecognizer *
1290  const ScheduleDAG *DAG) const;
1291 
1292  /// Allocate and return a hazard recognizer to use for by non-scheduling
1293  /// passes.
1294  virtual ScheduleHazardRecognizer *
1296  return nullptr;
1297  }
1298 
1299  /// Provide a global flag for disabling the PreRA hazard recognizer that
1300  /// targets may choose to honor.
1301  bool usePreRAHazardRecognizer() const;
1302 
1303  /// For a comparison instruction, return the source registers
1304  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1305  /// compares against in CmpValue. Return true if the comparison instruction
1306  /// can be analyzed.
1307  virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1308  unsigned &SrcReg2, int &Mask, int &Value) const {
1309  return false;
1310  }
1311 
1312  /// See if the comparison instruction can be converted
1313  /// into something more efficient. E.g., on ARM most instructions can set the
1314  /// flags register, obviating the need for a separate CMP.
1315  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1316  unsigned SrcReg2, int Mask, int Value,
1317  const MachineRegisterInfo *MRI) const {
1318  return false;
1319  }
1320  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1321 
1322  /// Try to remove the load by folding it to a register operand at the use.
1323  /// We fold the load instructions if and only if the
1324  /// def and use are in the same BB. We only look at one load and see
1325  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1326  /// defined by the load we are trying to fold. DefMI returns the machine
1327  /// instruction that defines FoldAsLoadDefReg, and the function returns
1328  /// the machine instruction generated due to folding.
1330  const MachineRegisterInfo *MRI,
1331  unsigned &FoldAsLoadDefReg,
1332  MachineInstr *&DefMI) const {
1333  return nullptr;
1334  }
1335 
1336  /// 'Reg' is known to be defined by a move immediate instruction,
1337  /// try to fold the immediate into the use instruction.
1338  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1339  /// then the caller may assume that DefMI has been erased from its parent
1340  /// block. The caller may assume that it will not be erased by this
1341  /// function otherwise.
1343  unsigned Reg, MachineRegisterInfo *MRI) const {
1344  return false;
1345  }
1346 
1347  /// Return the number of u-operations the given machine
1348  /// instruction will be decoded to on the target cpu. The itinerary's
1349  /// IssueWidth is the number of microops that can be dispatched each
1350  /// cycle. An instruction with zero microops takes no dispatch resources.
1351  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1352  const MachineInstr &MI) const;
1353 
1354  /// Return true for pseudo instructions that don't consume any
1355  /// machine resources in their current form. These are common cases that the
1356  /// scheduler should consider free, rather than conservatively handling them
1357  /// as instructions with no itinerary.
1358  bool isZeroCost(unsigned Opcode) const {
1359  return Opcode <= TargetOpcode::COPY;
1360  }
1361 
1362  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1363  SDNode *DefNode, unsigned DefIdx,
1364  SDNode *UseNode, unsigned UseIdx) const;
1365 
1366  /// Compute and return the use operand latency of a given pair of def and use.
1367  /// In most cases, the static scheduling itinerary was enough to determine the
1368  /// operand latency. But it may not be possible for instructions with variable
1369  /// number of defs / uses.
1370  ///
1371  /// This is a raw interface to the itinerary that may be directly overridden
1372  /// by a target. Use computeOperandLatency to get the best estimate of
1373  /// latency.
1374  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1375  const MachineInstr &DefMI, unsigned DefIdx,
1376  const MachineInstr &UseMI,
1377  unsigned UseIdx) const;
1378 
1379  /// Compute the instruction latency of a given instruction.
1380  /// If the instruction has higher cost when predicated, it's returned via
1381  /// PredCost.
1382  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1383  const MachineInstr &MI,
1384  unsigned *PredCost = nullptr) const;
1385 
1386  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1387 
1388  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1389  SDNode *Node) const;
1390 
1391  /// Return the default expected latency for a def based on its opcode.
1392  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1393  const MachineInstr &DefMI) const;
1394 
1395  int computeDefOperandLatency(const InstrItineraryData *ItinData,
1396  const MachineInstr &DefMI) const;
1397 
1398  /// Return true if this opcode has high latency to its result.
1399  virtual bool isHighLatencyDef(int opc) const { return false; }
1400 
1401  /// Compute operand latency between a def of 'Reg'
1402  /// and a use in the current loop. Return true if the target considered
1403  /// it 'high'. This is used by optimization passes such as machine LICM to
1404  /// determine whether it makes sense to hoist an instruction out even in a
1405  /// high register pressure situation.
1406  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1407  const MachineRegisterInfo *MRI,
1408  const MachineInstr &DefMI, unsigned DefIdx,
1409  const MachineInstr &UseMI,
1410  unsigned UseIdx) const {
1411  return false;
1412  }
1413 
1414  /// Compute operand latency of a def of 'Reg'. Return true
1415  /// if the target considered it 'low'.
1416  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1417  const MachineInstr &DefMI,
1418  unsigned DefIdx) const;
1419 
1420  /// Perform target-specific instruction verification.
1421  virtual bool verifyInstruction(const MachineInstr &MI,
1422  StringRef &ErrInfo) const {
1423  return true;
1424  }
1425 
1426  /// Return the current execution domain and bit mask of
1427  /// possible domains for instruction.
1428  ///
1429  /// Some micro-architectures have multiple execution domains, and multiple
1430  /// opcodes that perform the same operation in different domains. For
1431  /// example, the x86 architecture provides the por, orps, and orpd
1432  /// instructions that all do the same thing. There is a latency penalty if a
1433  /// register is written in one domain and read in another.
1434  ///
1435  /// This function returns a pair (domain, mask) containing the execution
1436  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1437  /// function can be used to change the opcode to one of the domains in the
1438  /// bit mask. Instructions whose execution domain can't be changed should
1439  /// return a 0 mask.
1440  ///
1441  /// The execution domain numbers don't have any special meaning except domain
1442  /// 0 is used for instructions that are not associated with any interesting
1443  /// execution domain.
1444  ///
1445  virtual std::pair<uint16_t, uint16_t>
1447  return std::make_pair(0, 0);
1448  }
1449 
1450  /// Change the opcode of MI to execute in Domain.
1451  ///
1452  /// The bit (1 << Domain) must be set in the mask returned from
1453  /// getExecutionDomain(MI).
1454  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1455 
1456  /// Returns the preferred minimum clearance
1457  /// before an instruction with an unwanted partial register update.
1458  ///
1459  /// Some instructions only write part of a register, and implicitly need to
1460  /// read the other parts of the register. This may cause unwanted stalls
1461  /// preventing otherwise unrelated instructions from executing in parallel in
1462  /// an out-of-order CPU.
1463  ///
1464  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1465  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1466  /// the instruction needs to wait for the old value of the register to become
1467  /// available:
1468  ///
1469  /// addps %xmm1, %xmm0
1470  /// movaps %xmm0, (%rax)
1471  /// cvtsi2ss %rbx, %xmm0
1472  ///
1473  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1474  /// instruction before it can issue, even though the high bits of %xmm0
1475  /// probably aren't needed.
1476  ///
1477  /// This hook returns the preferred clearance before MI, measured in
1478  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1479  /// instructions before MI. It should only return a positive value for
1480  /// unwanted dependencies. If the old bits of the defined register have
1481  /// useful values, or if MI is determined to otherwise read the dependency,
1482  /// the hook should return 0.
1483  ///
1484  /// The unwanted dependency may be handled by:
1485  ///
1486  /// 1. Allocating the same register for an MI def and use. That makes the
1487  /// unwanted dependency identical to a required dependency.
1488  ///
1489  /// 2. Allocating a register for the def that has no defs in the previous N
1490  /// instructions.
1491  ///
1492  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1493  /// allows the target to insert a dependency breaking instruction.
1494  ///
1495  virtual unsigned
1496  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1497  const TargetRegisterInfo *TRI) const {
1498  // The default implementation returns 0 for no partial register dependency.
1499  return 0;
1500  }
1501 
1502  /// Return the minimum clearance before an instruction that reads an
1503  /// unused register.
1504  ///
1505  /// For example, AVX instructions may copy part of a register operand into
1506  /// the unused high bits of the destination register.
1507  ///
1508  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1509  ///
1510  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1511  /// false dependence on any previous write to %xmm0.
1512  ///
1513  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1514  /// does not take an operand index. Instead sets \p OpNum to the index of the
1515  /// unused register.
1516  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1517  const TargetRegisterInfo *TRI) const {
1518  // The default implementation returns 0 for no undef register dependency.
1519  return 0;
1520  }
1521 
1522  /// Insert a dependency-breaking instruction
1523  /// before MI to eliminate an unwanted dependency on OpNum.
1524  ///
1525  /// If it wasn't possible to avoid a def in the last N instructions before MI
1526  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1527  /// unwanted dependency.
1528  ///
1529  /// On x86, an xorps instruction can be used as a dependency breaker:
1530  ///
1531  /// addps %xmm1, %xmm0
1532  /// movaps %xmm0, (%rax)
1533  /// xorps %xmm0, %xmm0
1534  /// cvtsi2ss %rbx, %xmm0
1535  ///
1536  /// An <imp-kill> operand should be added to MI if an instruction was
1537  /// inserted. This ties the instructions together in the post-ra scheduler.
1538  ///
1539  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1540  const TargetRegisterInfo *TRI) const {}
1541 
1542  /// Create machine specific model for scheduling.
1543  virtual DFAPacketizer *
1545  return nullptr;
1546  }
1547 
1548  /// Sometimes, it is possible for the target
1549  /// to tell, even without aliasing information, that two MIs access different
1550  /// memory addresses. This function returns true if two MIs access different
1551  /// memory addresses and false otherwise.
1552  ///
1553  /// Assumes any physical registers used to compute addresses have the same
1554  /// value for both instructions. (This is the most useful assumption for
1555  /// post-RA scheduling.)
1556  ///
1557  /// See also MachineInstr::mayAlias, which is implemented on top of this
1558  /// function.
1559  virtual bool
1561  const MachineInstr &MIb,
1562  AliasAnalysis *AA = nullptr) const {
1563  assert((MIa.mayLoad() || MIa.mayStore()) &&
1564  "MIa must load from or modify a memory location");
1565  assert((MIb.mayLoad() || MIb.mayStore()) &&
1566  "MIb must load from or modify a memory location");
1567  return false;
1568  }
1569 
1570  /// Return the value to use for the MachineCSE's LookAheadLimit,
1571  /// which is a heuristic used for CSE'ing phys reg defs.
1572  virtual unsigned getMachineCSELookAheadLimit() const {
1573  // The default lookahead is small to prevent unprofitable quadratic
1574  // behavior.
1575  return 5;
1576  }
1577 
1578  /// Return an array that contains the ids of the target indices (used for the
1579  /// TargetIndex machine operand) and their names.
1580  ///
1581  /// MIR Serialization is able to serialize only the target indices that are
1582  /// defined by this method.
1585  return None;
1586  }
1587 
1588  /// Decompose the machine operand's target flags into two values - the direct
1589  /// target flag value and any of bit flags that are applied.
1590  virtual std::pair<unsigned, unsigned>
1591  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1592  return std::make_pair(0u, 0u);
1593  }
1594 
1595  /// Return an array that contains the direct target flag values and their
1596  /// names.
1597  ///
1598  /// MIR Serialization is able to serialize only the target flags that are
1599  /// defined by this method.
1602  return None;
1603  }
1604 
1605  /// Return an array that contains the bitmask target flag values and their
1606  /// names.
1607  ///
1608  /// MIR Serialization is able to serialize only the target flags that are
1609  /// defined by this method.
1612  return None;
1613  }
1614 
1615  /// Return an array that contains the MMO target flag values and their
1616  /// names.
1617  ///
1618  /// MIR Serialization is able to serialize only the MMO target flags that are
1619  /// defined by this method.
1622  return None;
1623  }
1624 
1625  /// Determines whether \p Inst is a tail call instruction. Override this
1626  /// method on targets that do not properly set MCID::Return and MCID::Call on
1627  /// tail call instructions."
1628  virtual bool isTailCall(const MachineInstr &Inst) const {
1629  return Inst.isReturn() && Inst.isCall();
1630  }
1631 
1632  /// True if the instruction is bound to the top of its basic block and no
1633  /// other instructions shall be inserted before it. This can be implemented
1634  /// to prevent register allocator to insert spills before such instructions.
1635  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1636  return false;
1637  }
1638 
1639  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1640  /// information for a set of outlining candidates.
1642  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1644  "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1645  }
1646 
1647  /// Returns how or if \p MI should be outlined.
1648  virtual outliner::InstrType
1649  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1651  "Target didn't implement TargetInstrInfo::getOutliningType!");
1652  }
1653 
1654  /// Optional target hook that returns true if \p MBB is safe to outline from,
1655  /// and returns any target-specific information in \p Flags.
1657  unsigned &Flags) const {
1658  return true;
1659  }
1660 
1661  /// Insert a custom frame for outlined functions.
1663  const outliner::OutlinedFunction &OF) const {
1665  "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1666  }
1667 
1668  /// Insert a call to an outlined function into the program.
1669  /// Returns an iterator to the spot where we inserted the call. This must be
1670  /// implemented by the target.
1674  const outliner::Candidate &C) const {
1676  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1677  }
1678 
1679  /// Return true if the function can safely be outlined from.
1680  /// A function \p MF is considered safe for outlining if an outlined function
1681  /// produced from instructions in F will produce a program which produces the
1682  /// same output for any set of given inputs.
1684  bool OutlineFromLinkOnceODRs) const {
1685  llvm_unreachable("Target didn't implement "
1686  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1687  }
1688 
1689  /// Return true if the function should be outlined from by default.
1691  return false;
1692  }
1693 
1694 private:
1695  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1696  unsigned CatchRetOpcode;
1697  unsigned ReturnOpcode;
1698 };
1699 
1700 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1703 
1705  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1706  RegInfo::getEmptyKey());
1707  }
1708 
1710  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1711  RegInfo::getTombstoneKey());
1712  }
1713 
1714  /// Reuse getHashValue implementation from
1715  /// std::pair<unsigned, unsigned>.
1716  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1717  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1718  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1719  }
1720 
1721  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1722  const TargetInstrInfo::RegSubRegPair &RHS) {
1723  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1724  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1725  }
1726 };
1727 
1728 } // end namespace llvm
1729 
1730 #endif // LLVM_TARGET_TARGETINSTRINFO_H
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
uint64_t CallInst * C
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:635
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true...
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it&#39;s safe to move a machine instruction that defines the specified register class...
virtual bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const
Target-dependent implemenation for IsCopyInstr.
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
RegSubRegPair(unsigned Reg=0, unsigned SubReg=0)
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
virtual bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient. ...
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:164
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore...
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when Inst has reassociable operands in the same MBB.
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned getCallFrameDestroyOpcode() const
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
static bool isGenericOpcode(unsigned Opc)
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
An individual sequence of instructions to be replaced with a call to an outlined function.
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Represents a predicate at the MachineFunction level.
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE&#39;s LookAheadLimit, which is a heuristic used for CSE&#39;ing ph...
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack...
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified &#39;original&#39; instruction at the specific location targeting a new destination re...
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const
Insert a call to an outlined function into the program.
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Provide an instruction scheduling machine model to CodeGen passes.
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const
&#39;Reg&#39; is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool operator!=(const RegSubRegPair &P) const
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of &#39;Reg&#39;.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
virtual MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
unsigned getCatchReturnOpcode() const
virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const
Returns true if the two given memory operations should be scheduled adjacent.
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:321
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
static bool isEqual(const Function &Caller, const Function &Callee)
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:486
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it&#39;s profitable to predicate instructions with accumulated instruction latency of "Num...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Itinerary data supplied by a subtarget to be used by a target.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
RegSubRegPairAndIdx(unsigned Reg=0, unsigned SubReg=0, unsigned SubIdx=0)
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
BasicBlockListType::iterator iterator
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:625
virtual void getNoop(MCInst &NopInst) const
Return the noop instruction to use for a noop.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
TargetInstrInfo::RegSubRegPair RegSubRegPair
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
bool operator==(const RegSubRegPair &P) const
static const unsigned CommuteAnyOperandIndex
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:822
#define P(N)
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
unsigned const MachineRegisterInfo * MRI
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
virtual unsigned getPredicationCost(const MachineInstr &MI) const
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
InstrType
Represents how an instruction should be mapped by the outliner.
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
MachineInstrBuilder & UseMI
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it&#39;s legal to split the given basic block at the specified instruction (i...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack...
The information necessary to create an outlined function for some class of candidate.
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
Contains all data structures shared between the outliner implemented in MachineOutliner.cpp and target implementations of the outliner.
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input Inst is part of a chain of dependent ops that are suitable for reassociatio...
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
A set of register units.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:308
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
bool isCopy() const
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
virtual bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
virtual unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
virtual bool optimizeCondBranch(MachineInstr &MI) const
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate Root and Prev according to Pattern to reduce critical path length...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
MachineOperand class - Representation of each machine instruction operand.
A pair composed of a register and a sub-register index.
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of &#39;Reg&#39; and a use in the current loop.
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Represents one node in the SelectionDAG.
virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
int64_t getImm() const
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
unsigned getReturnOpcode() const
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Representation of each machine instruction.
Definition: MachineInstr.h:64
static TargetInstrInfo::RegSubRegPair getEmptyKey()
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understoo.
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1...
bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum...
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don&#39;t consume any machine resources in their current form...
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
uint32_t Size
Definition: Profile.cpp:46
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:809
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
LLVM Value Representation.
Definition: Value.h:72
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when Inst has reassociable sibling.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when Inst is both associative and commutative.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
IRTranslator LLVM IR MI
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it&#39;s profitable to unpredicate one side of a &#39;diamond&#39;, i.e.
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:919
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register. ...
A pair composed of a pair of a register and a sub-register index, and another sub-register index...