LLVM  10.0.0svn
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_TARGET_TARGETINSTRINFO_H
14 #define LLVM_TARGET_TARGETINSTRINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
31 #include "llvm/MC/MCInstrInfo.h"
34 #include <cassert>
35 #include <cstddef>
36 #include <cstdint>
37 #include <utility>
38 #include <vector>
39 
40 namespace llvm {
41 
42 class DFAPacketizer;
43 class InstrItineraryData;
44 class LiveIntervals;
45 class LiveVariables;
46 class MachineMemOperand;
47 class MachineRegisterInfo;
48 class MCAsmInfo;
49 class MCInst;
50 struct MCSchedModel;
51 class Module;
52 class ScheduleDAG;
53 class ScheduleHazardRecognizer;
54 class SDNode;
55 class SelectionDAG;
56 class RegScavenger;
57 class TargetRegisterClass;
58 class TargetRegisterInfo;
59 class TargetSchedModel;
60 class TargetSubtargetInfo;
61 
62 template <class T> class SmallVectorImpl;
63 
64 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
65 
66 //---------------------------------------------------------------------------
67 ///
68 /// TargetInstrInfo - Interface to description of machine instruction set
69 ///
70 class TargetInstrInfo : public MCInstrInfo {
71 public:
72  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
73  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
74  : CallFrameSetupOpcode(CFSetupOpcode),
75  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
76  ReturnOpcode(ReturnOpcode) {}
77  TargetInstrInfo(const TargetInstrInfo &) = delete;
78  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
79  virtual ~TargetInstrInfo();
80 
81  static bool isGenericOpcode(unsigned Opc) {
82  return Opc <= TargetOpcode::GENERIC_OP_END;
83  }
84 
85  /// Given a machine instruction descriptor, returns the register
86  /// class constraint for OpNum, or NULL.
87  virtual
88  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
89  const TargetRegisterInfo *TRI,
90  const MachineFunction &MF) const;
91 
92  /// Return true if the instruction is trivially rematerializable, meaning it
93  /// has no side effects and requires no operands that aren't always available.
94  /// This means the only allowed uses are constants and unallocatable physical
95  /// registers so that the instructions result is independent of the place
96  /// in the function.
98  AliasAnalysis *AA = nullptr) const {
99  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
100  (MI.getDesc().isRematerializable() &&
102  isReallyTriviallyReMaterializableGeneric(MI, AA)));
103  }
104 
105 protected:
106  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
107  /// set, this hook lets the target specify whether the instruction is actually
108  /// trivially rematerializable, taking into consideration its operands. This
109  /// predicate must return false if the instruction has any side effects other
110  /// than producing a value, or if it requres any address registers that are
111  /// not always available.
112  /// Requirements must be check as stated in isTriviallyReMaterializable() .
114  AliasAnalysis *AA) const {
115  return false;
116  }
117 
118  /// This method commutes the operands of the given machine instruction MI.
119  /// The operands to be commuted are specified by their indices OpIdx1 and
120  /// OpIdx2.
121  ///
122  /// If a target has any instructions that are commutable but require
123  /// converting to different instructions or making non-trivial changes
124  /// to commute them, this method can be overloaded to do that.
125  /// The default implementation simply swaps the commutable operands.
126  ///
127  /// If NewMI is false, MI is modified in place and returned; otherwise, a
128  /// new machine instruction is created and returned.
129  ///
130  /// Do not call this method for a non-commutable instruction.
131  /// Even though the instruction is commutable, the method may still
132  /// fail to commute the operands, null pointer is returned in such cases.
133  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
134  unsigned OpIdx1,
135  unsigned OpIdx2) const;
136 
137  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
138  /// operand indices to (ResultIdx1, ResultIdx2).
139  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
140  /// predefined to some indices or be undefined (designated by the special
141  /// value 'CommuteAnyOperandIndex').
142  /// The predefined result indices cannot be re-defined.
143  /// The function returns true iff after the result pair redefinition
144  /// the fixed result pair is equal to or equivalent to the source pair of
145  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
146  /// the pairs (x,y) and (y,x) are equivalent.
147  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
148  unsigned CommutableOpIdx1,
149  unsigned CommutableOpIdx2);
150 
151 private:
152  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
153  /// set and the target hook isReallyTriviallyReMaterializable returns false,
154  /// this function does target-independent tests to determine if the
155  /// instruction is really trivially rematerializable.
156  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
157  AliasAnalysis *AA) const;
158 
159 public:
160  /// These methods return the opcode of the frame setup/destroy instructions
161  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
162  /// order to abstract away the difference between operating with a frame
163  /// pointer and operating without, through the use of these two instructions.
164  ///
165  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
166  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
167 
168  /// Returns true if the argument is a frame pseudo instruction.
169  bool isFrameInstr(const MachineInstr &I) const {
170  return I.getOpcode() == getCallFrameSetupOpcode() ||
172  }
173 
174  /// Returns true if the argument is a frame setup pseudo instruction.
175  bool isFrameSetup(const MachineInstr &I) const {
176  return I.getOpcode() == getCallFrameSetupOpcode();
177  }
178 
179  /// Returns size of the frame associated with the given frame instruction.
180  /// For frame setup instruction this is frame that is set up space set up
181  /// after the instruction. For frame destroy instruction this is the frame
182  /// freed by the caller.
183  /// Note, in some cases a call frame (or a part of it) may be prepared prior
184  /// to the frame setup instruction. It occurs in the calls that involve
185  /// inalloca arguments. This function reports only the size of the frame part
186  /// that is set up between the frame setup and destroy pseudo instructions.
187  int64_t getFrameSize(const MachineInstr &I) const {
188  assert(isFrameInstr(I) && "Not a frame instruction");
189  assert(I.getOperand(0).getImm() >= 0);
190  return I.getOperand(0).getImm();
191  }
192 
193  /// Returns the total frame size, which is made up of the space set up inside
194  /// the pair of frame start-stop instructions and the space that is set up
195  /// prior to the pair.
196  int64_t getFrameTotalSize(const MachineInstr &I) const {
197  if (isFrameSetup(I)) {
198  assert(I.getOperand(1).getImm() >= 0 &&
199  "Frame size must not be negative");
200  return getFrameSize(I) + I.getOperand(1).getImm();
201  }
202  return getFrameSize(I);
203  }
204 
205  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
206  unsigned getReturnOpcode() const { return ReturnOpcode; }
207 
208  /// Returns the actual stack pointer adjustment made by an instruction
209  /// as part of a call sequence. By default, only call frame setup/destroy
210  /// instructions adjust the stack, but targets may want to override this
211  /// to enable more fine-grained adjustment, or adjust by a different value.
212  virtual int getSPAdjust(const MachineInstr &MI) const;
213 
214  /// Return true if the instruction is a "coalescable" extension instruction.
215  /// That is, it's like a copy where it's legal for the source to overlap the
216  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
217  /// expected the pre-extension value is available as a subreg of the result
218  /// register. This also returns the sub-register index in SubIdx.
219  virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
220  unsigned &DstReg, unsigned &SubIdx) const {
221  return false;
222  }
223 
224  /// If the specified machine instruction is a direct
225  /// load from a stack slot, return the virtual or physical register number of
226  /// the destination along with the FrameIndex of the loaded stack slot. If
227  /// not, return 0. This predicate must return 0 if the instruction has
228  /// any side effects other than loading from the stack slot.
229  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
230  int &FrameIndex) const {
231  return 0;
232  }
233 
234  /// Optional extension of isLoadFromStackSlot that returns the number of
235  /// bytes loaded from the stack. This must be implemented if a backend
236  /// supports partial stack slot spills/loads to further disambiguate
237  /// what the load does.
238  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
239  int &FrameIndex,
240  unsigned &MemBytes) const {
241  MemBytes = 0;
242  return isLoadFromStackSlot(MI, FrameIndex);
243  }
244 
245  /// Check for post-frame ptr elimination stack locations as well.
246  /// This uses a heuristic so it isn't reliable for correctness.
247  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
248  int &FrameIndex) const {
249  return 0;
250  }
251 
252  /// If the specified machine instruction has a load from a stack slot,
253  /// return true along with the FrameIndices of the loaded stack slot and the
254  /// machine mem operands containing the reference.
255  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
256  /// any instructions that loads from the stack. This is just a hint, as some
257  /// cases may be missed.
258  virtual bool hasLoadFromStackSlot(
259  const MachineInstr &MI,
261 
262  /// If the specified machine instruction is a direct
263  /// store to a stack slot, return the virtual or physical register number of
264  /// the source reg along with the FrameIndex of the loaded stack slot. If
265  /// not, return 0. This predicate must return 0 if the instruction has
266  /// any side effects other than storing to the stack slot.
267  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
268  int &FrameIndex) const {
269  return 0;
270  }
271 
272  /// Optional extension of isStoreToStackSlot that returns the number of
273  /// bytes stored to the stack. This must be implemented if a backend
274  /// supports partial stack slot spills/loads to further disambiguate
275  /// what the store does.
276  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
277  int &FrameIndex,
278  unsigned &MemBytes) const {
279  MemBytes = 0;
280  return isStoreToStackSlot(MI, FrameIndex);
281  }
282 
283  /// Check for post-frame ptr elimination stack locations as well.
284  /// This uses a heuristic, so it isn't reliable for correctness.
285  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
286  int &FrameIndex) const {
287  return 0;
288  }
289 
290  /// If the specified machine instruction has a store to a stack slot,
291  /// return true along with the FrameIndices of the loaded stack slot and the
292  /// machine mem operands containing the reference.
293  /// If not, return false. Unlike isStoreToStackSlot,
294  /// this returns true for any instructions that stores to the
295  /// stack. This is just a hint, as some cases may be missed.
296  virtual bool hasStoreToStackSlot(
297  const MachineInstr &MI,
299 
300  /// Return true if the specified machine instruction
301  /// is a copy of one stack slot to another and has no other effect.
302  /// Provide the identity of the two frame indices.
303  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
304  int &SrcFrameIndex) const {
305  return false;
306  }
307 
308  /// Compute the size in bytes and offset within a stack slot of a spilled
309  /// register or subregister.
310  ///
311  /// \param [out] Size in bytes of the spilled value.
312  /// \param [out] Offset in bytes within the stack slot.
313  /// \returns true if both Size and Offset are successfully computed.
314  ///
315  /// Not all subregisters have computable spill slots. For example,
316  /// subregisters registers may not be byte-sized, and a pair of discontiguous
317  /// subregisters has no single offset.
318  ///
319  /// Targets with nontrivial bigendian implementations may need to override
320  /// this, particularly to support spilled vector registers.
321  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
322  unsigned &Size, unsigned &Offset,
323  const MachineFunction &MF) const;
324 
325  /// Returns the size in bytes of the specified MachineInstr, or ~0U
326  /// when this function is not implemented by a target.
327  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
328  return ~0U;
329  }
330 
331  /// Return true if the instruction is as cheap as a move instruction.
332  ///
333  /// Targets for different archs need to override this, and different
334  /// micro-architectures can also be finely tuned inside.
335  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
336  return MI.isAsCheapAsAMove();
337  }
338 
339  /// Return true if the instruction should be sunk by MachineSink.
340  ///
341  /// MachineSink determines on its own whether the instruction is safe to sink;
342  /// this gives the target a hook to override the default behavior with regards
343  /// to which instructions should be sunk.
344  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
345 
346  /// Re-issue the specified 'original' instruction at the
347  /// specific location targeting a new destination register.
348  /// The register in Orig->getOperand(0).getReg() will be substituted by
349  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
350  /// SubIdx.
351  virtual void reMaterialize(MachineBasicBlock &MBB,
352  MachineBasicBlock::iterator MI, unsigned DestReg,
353  unsigned SubIdx, const MachineInstr &Orig,
354  const TargetRegisterInfo &TRI) const;
355 
356  /// Clones instruction or the whole instruction bundle \p Orig and
357  /// insert into \p MBB before \p InsertBefore. The target may update operands
358  /// that are required to be unique.
359  ///
360  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
362  MachineBasicBlock::iterator InsertBefore,
363  const MachineInstr &Orig) const;
364 
365  /// This method must be implemented by targets that
366  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
367  /// may be able to convert a two-address instruction into one or more true
368  /// three-address instructions on demand. This allows the X86 target (for
369  /// example) to convert ADD and SHL instructions into LEA instructions if they
370  /// would require register copies due to two-addressness.
371  ///
372  /// This method returns a null pointer if the transformation cannot be
373  /// performed, otherwise it returns the last new instruction.
374  ///
376  MachineInstr &MI,
377  LiveVariables *LV) const {
378  return nullptr;
379  }
380 
381  // This constant can be used as an input value of operand index passed to
382  // the method findCommutedOpIndices() to tell the method that the
383  // corresponding operand index is not pre-defined and that the method
384  // can pick any commutable operand.
385  static const unsigned CommuteAnyOperandIndex = ~0U;
386 
387  /// This method commutes the operands of the given machine instruction MI.
388  ///
389  /// The operands to be commuted are specified by their indices OpIdx1 and
390  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
391  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
392  /// any arbitrarily chosen commutable operand. If both arguments are set to
393  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
394  /// operands; then commutes them if such operands could be found.
395  ///
396  /// If NewMI is false, MI is modified in place and returned; otherwise, a
397  /// new machine instruction is created and returned.
398  ///
399  /// Do not call this method for a non-commutable instruction or
400  /// for non-commuable operands.
401  /// Even though the instruction is commutable, the method may still
402  /// fail to commute the operands, null pointer is returned in such cases.
403  MachineInstr *
404  commuteInstruction(MachineInstr &MI, bool NewMI = false,
405  unsigned OpIdx1 = CommuteAnyOperandIndex,
406  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
407 
408  /// Returns true iff the routine could find two commutable operands in the
409  /// given machine instruction.
410  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
411  /// If any of the INPUT values is set to the special value
412  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
413  /// operand, then returns its index in the corresponding argument.
414  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
415  /// looks for 2 commutable operands.
416  /// If INPUT values refer to some operands of MI, then the method simply
417  /// returns true if the corresponding operands are commutable and returns
418  /// false otherwise.
419  ///
420  /// For example, calling this method this way:
421  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
422  /// findCommutedOpIndices(MI, Op1, Op2);
423  /// can be interpreted as a query asking to find an operand that would be
424  /// commutable with the operand#1.
425  virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
426  unsigned &SrcOpIdx2) const;
427 
428  /// A pair composed of a register and a sub-register index.
429  /// Used to give some type checking when modeling Reg:SubReg.
430  struct RegSubRegPair {
431  unsigned Reg;
432  unsigned SubReg;
433 
434  RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
435  : Reg(Reg), SubReg(SubReg) {}
436 
437  bool operator==(const RegSubRegPair& P) const {
438  return Reg == P.Reg && SubReg == P.SubReg;
439  }
440  bool operator!=(const RegSubRegPair& P) const {
441  return !(*this == P);
442  }
443  };
444 
445  /// A pair composed of a pair of a register and a sub-register index,
446  /// and another sub-register index.
447  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
449  unsigned SubIdx;
450 
451  RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
452  unsigned SubIdx = 0)
453  : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
454  };
455 
456  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
457  /// and \p DefIdx.
458  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
459  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
460  /// flag are not added to this list.
461  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
462  /// two elements:
463  /// - %1:sub1, sub0
464  /// - %2<:0>, sub1
465  ///
466  /// \returns true if it is possible to build such an input sequence
467  /// with the pair \p MI, \p DefIdx. False otherwise.
468  ///
469  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
470  ///
471  /// \note The generic implementation does not provide any support for
472  /// MI.isRegSequenceLike(). In other words, one has to override
473  /// getRegSequenceLikeInputs for target specific instructions.
474  bool
475  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
476  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
477 
478  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
479  /// and \p DefIdx.
480  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
481  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
482  /// - %1:sub1, sub0
483  ///
484  /// \returns true if it is possible to build such an input sequence
485  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
486  /// False otherwise.
487  ///
488  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
489  ///
490  /// \note The generic implementation does not provide any support for
491  /// MI.isExtractSubregLike(). In other words, one has to override
492  /// getExtractSubregLikeInputs for target specific instructions.
493  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
494  RegSubRegPairAndIdx &InputReg) const;
495 
496  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
497  /// and \p DefIdx.
498  /// \p [out] BaseReg and \p [out] InsertedReg contain
499  /// the equivalent inputs of INSERT_SUBREG.
500  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
501  /// - BaseReg: %0:sub0
502  /// - InsertedReg: %1:sub1, sub3
503  ///
504  /// \returns true if it is possible to build such an input sequence
505  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
506  /// False otherwise.
507  ///
508  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
509  ///
510  /// \note The generic implementation does not provide any support for
511  /// MI.isInsertSubregLike(). In other words, one has to override
512  /// getInsertSubregLikeInputs for target specific instructions.
513  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
514  RegSubRegPair &BaseReg,
515  RegSubRegPairAndIdx &InsertedReg) const;
516 
517  /// Return true if two machine instructions would produce identical values.
518  /// By default, this is only true when the two instructions
519  /// are deemed identical except for defs. If this function is called when the
520  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
521  /// aggressive checks.
522  virtual bool produceSameValue(const MachineInstr &MI0,
523  const MachineInstr &MI1,
524  const MachineRegisterInfo *MRI = nullptr) const;
525 
526  /// \returns true if a branch from an instruction with opcode \p BranchOpc
527  /// bytes is capable of jumping to a position \p BrOffset bytes away.
528  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
529  int64_t BrOffset) const {
530  llvm_unreachable("target did not implement");
531  }
532 
533  /// \returns The block that branch instruction \p MI jumps to.
535  llvm_unreachable("target did not implement");
536  }
537 
538  /// Insert an unconditional indirect branch at the end of \p MBB to \p
539  /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
540  /// the offset of the position to insert the new branch.
541  ///
542  /// \returns The number of bytes added to the block.
544  MachineBasicBlock &NewDestBB,
545  const DebugLoc &DL,
546  int64_t BrOffset = 0,
547  RegScavenger *RS = nullptr) const {
548  llvm_unreachable("target did not implement");
549  }
550 
551  /// Analyze the branching code at the end of MBB, returning
552  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
553  /// implemented for a target). Upon success, this returns false and returns
554  /// with the following information in various cases:
555  ///
556  /// 1. If this block ends with no branches (it just falls through to its succ)
557  /// just return false, leaving TBB/FBB null.
558  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
559  /// the destination block.
560  /// 3. If this block ends with a conditional branch and it falls through to a
561  /// successor block, it sets TBB to be the branch destination block and a
562  /// list of operands that evaluate the condition. These operands can be
563  /// passed to other TargetInstrInfo methods to create new branches.
564  /// 4. If this block ends with a conditional branch followed by an
565  /// unconditional branch, it returns the 'true' destination in TBB, the
566  /// 'false' destination in FBB, and a list of operands that evaluate the
567  /// condition. These operands can be passed to other TargetInstrInfo
568  /// methods to create new branches.
569  ///
570  /// Note that removeBranch and insertBranch must be implemented to support
571  /// cases where this method returns success.
572  ///
573  /// If AllowModify is true, then this routine is allowed to modify the basic
574  /// block (e.g. delete instructions after the unconditional branch).
575  ///
576  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
577  /// before calling this function.
579  MachineBasicBlock *&FBB,
581  bool AllowModify = false) const {
582  return true;
583  }
584 
585  /// Represents a predicate at the MachineFunction level. The control flow a
586  /// MachineBranchPredicate represents is:
587  ///
588  /// Reg = LHS `Predicate` RHS == ConditionDef
589  /// if Reg then goto TrueDest else goto FalseDest
590  ///
593  PRED_EQ, // True if two values are equal
594  PRED_NE, // True if two values are not equal
595  PRED_INVALID // Sentinel value
596  };
597 
598  ComparePredicate Predicate = PRED_INVALID;
601  MachineBasicBlock *TrueDest = nullptr;
602  MachineBasicBlock *FalseDest = nullptr;
603  MachineInstr *ConditionDef = nullptr;
604 
605  /// SingleUseCondition is true if ConditionDef is dead except for the
606  /// branch(es) at the end of the basic block.
607  ///
608  bool SingleUseCondition = false;
609 
610  explicit MachineBranchPredicate() = default;
611  };
612 
613  /// Analyze the branching code at the end of MBB and parse it into the
614  /// MachineBranchPredicate structure if possible. Returns false on success
615  /// and true on failure.
616  ///
617  /// If AllowModify is true, then this routine is allowed to modify the basic
618  /// block (e.g. delete instructions after the unconditional branch).
619  ///
622  bool AllowModify = false) const {
623  return true;
624  }
625 
626  /// Remove the branching code at the end of the specific MBB.
627  /// This is only invoked in cases where AnalyzeBranch returns success. It
628  /// returns the number of instructions that were removed.
629  /// If \p BytesRemoved is non-null, report the change in code size from the
630  /// removed instructions.
631  virtual unsigned removeBranch(MachineBasicBlock &MBB,
632  int *BytesRemoved = nullptr) const {
633  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
634  }
635 
636  /// Insert branch code into the end of the specified MachineBasicBlock. The
637  /// operands to this method are the same as those returned by AnalyzeBranch.
638  /// This is only invoked in cases where AnalyzeBranch returns success. It
639  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
640  /// report the change in code size from the added instructions.
641  ///
642  /// It is also invoked by tail merging to add unconditional branches in
643  /// cases where AnalyzeBranch doesn't apply because there was no original
644  /// branch to analyze. At least this much must be implemented, else tail
645  /// merging needs to be disabled.
646  ///
647  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
648  /// before calling this function.
649  virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
650  MachineBasicBlock *FBB,
652  const DebugLoc &DL,
653  int *BytesAdded = nullptr) const {
654  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
655  }
656 
658  MachineBasicBlock *DestBB,
659  const DebugLoc &DL,
660  int *BytesAdded = nullptr) const {
661  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
662  BytesAdded);
663  }
664 
665  /// Object returned by analyzeLoopForPipelining. Allows software pipelining
666  /// implementations to query attributes of the loop being pipelined and to
667  /// apply target-specific updates to the loop once pipelining is complete.
669  public:
670  virtual ~PipelinerLoopInfo();
671  /// Return true if the given instruction should not be pipelined and should
672  /// be ignored. An example could be a loop comparison, or induction variable
673  /// update with no users being pipelined.
674  virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
675 
676  /// Create a condition to determine if the trip count of the loop is greater
677  /// than TC.
678  ///
679  /// If the trip count is statically known to be greater than TC, return
680  /// true. If the trip count is statically known to be not greater than TC,
681  /// return false. Otherwise return nullopt and fill out Cond with the test
682  /// condition.
683  virtual Optional<bool>
684  createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
686 
687  /// Modify the loop such that the trip count is
688  /// OriginalTC + TripCountAdjust.
689  virtual void adjustTripCount(int TripCountAdjust) = 0;
690 
691  /// Called when the loop's preheader has been modified to NewPreheader.
692  virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
693 
694  /// Called when the loop is being removed. Any instructions in the preheader
695  /// should be removed.
696  ///
697  /// Once this function is called, no other functions on this object are
698  /// valid; the loop has been removed.
699  virtual void disposed() = 0;
700  };
701 
702  /// Analyze loop L, which must be a single-basic-block loop, and if the
703  /// conditions can be understood enough produce a PipelinerLoopInfo object.
704  virtual std::unique_ptr<PipelinerLoopInfo>
706  return nullptr;
707  }
708 
709  /// Analyze the loop code, return true if it cannot be understoo. Upon
710  /// success, this function returns false and returns information about the
711  /// induction variable and compare instruction used at the end.
712  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
713  MachineInstr *&CmpInst) const {
714  return true;
715  }
716 
717  /// Generate code to reduce the loop iteration by one and check if the loop
718  /// is finished. Return the value/register of the new loop count. We need
719  /// this function when peeling off one or more iterations of a loop. This
720  /// function assumes the nth iteration is peeled first.
721  virtual unsigned reduceLoopCount(MachineBasicBlock &MBB,
722  MachineBasicBlock &PreHeader,
723  MachineInstr *IndVar, MachineInstr &Cmp,
726  unsigned Iter, unsigned MaxIter) const {
727  llvm_unreachable("Target didn't implement ReduceLoopCount");
728  }
729 
730  /// Delete the instruction OldInst and everything after it, replacing it with
731  /// an unconditional branch to NewDest. This is used by the tail merging pass.
733  MachineBasicBlock *NewDest) const;
734 
735  /// Return true if it's legal to split the given basic
736  /// block at the specified instruction (i.e. instruction would be the start
737  /// of a new basic block).
739  MachineBasicBlock::iterator MBBI) const {
740  return true;
741  }
742 
743  /// Return true if it's profitable to predicate
744  /// instructions with accumulated instruction latency of "NumCycles"
745  /// of the specified basic block, where the probability of the instructions
746  /// being executed is given by Probability, and Confidence is a measure
747  /// of our confidence that it will be properly predicted.
748  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
749  unsigned ExtraPredCycles,
750  BranchProbability Probability) const {
751  return false;
752  }
753 
754  /// Second variant of isProfitableToIfCvt. This one
755  /// checks for the case where two basic blocks from true and false path
756  /// of a if-then-else (diamond) are predicated on mutally exclusive
757  /// predicates, where the probability of the true path being taken is given
758  /// by Probability, and Confidence is a measure of our confidence that it
759  /// will be properly predicted.
760  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
761  unsigned ExtraTCycles,
762  MachineBasicBlock &FMBB, unsigned NumFCycles,
763  unsigned ExtraFCycles,
764  BranchProbability Probability) const {
765  return false;
766  }
767 
768  /// Return true if it's profitable for if-converter to duplicate instructions
769  /// of specified accumulated instruction latencies in the specified MBB to
770  /// enable if-conversion.
771  /// The probability of the instructions being executed is given by
772  /// Probability, and Confidence is a measure of our confidence that it
773  /// will be properly predicted.
775  unsigned NumCycles,
776  BranchProbability Probability) const {
777  return false;
778  }
779 
780  /// Return true if it's profitable to unpredicate
781  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
782  /// exclusive predicates.
783  /// e.g.
784  /// subeq r0, r1, #1
785  /// addne r0, r1, #1
786  /// =>
787  /// sub r0, r1, #1
788  /// addne r0, r1, #1
789  ///
790  /// This may be profitable is conditional instructions are always executed.
792  MachineBasicBlock &FMBB) const {
793  return false;
794  }
795 
796  /// Return true if it is possible to insert a select
797  /// instruction that chooses between TrueReg and FalseReg based on the
798  /// condition code in Cond.
799  ///
800  /// When successful, also return the latency in cycles from TrueReg,
801  /// FalseReg, and Cond to the destination register. In most cases, a select
802  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
803  ///
804  /// Some x86 implementations have 2-cycle cmov instructions.
805  ///
806  /// @param MBB Block where select instruction would be inserted.
807  /// @param Cond Condition returned by AnalyzeBranch.
808  /// @param TrueReg Virtual register to select when Cond is true.
809  /// @param FalseReg Virtual register to select when Cond is false.
810  /// @param CondCycles Latency from Cond+Branch to select output.
811  /// @param TrueCycles Latency from TrueReg to select output.
812  /// @param FalseCycles Latency from FalseReg to select output.
813  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
814  ArrayRef<MachineOperand> Cond, unsigned TrueReg,
815  unsigned FalseReg, int &CondCycles,
816  int &TrueCycles, int &FalseCycles) const {
817  return false;
818  }
819 
820  /// Insert a select instruction into MBB before I that will copy TrueReg to
821  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
822  ///
823  /// This function can only be called after canInsertSelect() returned true.
824  /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
825  /// that the same flags or registers required by Cond are available at the
826  /// insertion point.
827  ///
828  /// @param MBB Block where select instruction should be inserted.
829  /// @param I Insertion point.
830  /// @param DL Source location for debugging.
831  /// @param DstReg Virtual register to be defined by select instruction.
832  /// @param Cond Condition as computed by AnalyzeBranch.
833  /// @param TrueReg Virtual register to copy when Cond is true.
834  /// @param FalseReg Virtual register to copy when Cons is false.
835  virtual void insertSelect(MachineBasicBlock &MBB,
837  unsigned DstReg, ArrayRef<MachineOperand> Cond,
838  unsigned TrueReg, unsigned FalseReg) const {
839  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
840  }
841 
842  /// Analyze the given select instruction, returning true if
843  /// it cannot be understood. It is assumed that MI->isSelect() is true.
844  ///
845  /// When successful, return the controlling condition and the operands that
846  /// determine the true and false result values.
847  ///
848  /// Result = SELECT Cond, TrueOp, FalseOp
849  ///
850  /// Some targets can optimize select instructions, for example by predicating
851  /// the instruction defining one of the operands. Such targets should set
852  /// Optimizable.
853  ///
854  /// @param MI Select instruction to analyze.
855  /// @param Cond Condition controlling the select.
856  /// @param TrueOp Operand number of the value selected when Cond is true.
857  /// @param FalseOp Operand number of the value selected when Cond is false.
858  /// @param Optimizable Returned as true if MI is optimizable.
859  /// @returns False on success.
860  virtual bool analyzeSelect(const MachineInstr &MI,
862  unsigned &TrueOp, unsigned &FalseOp,
863  bool &Optimizable) const {
864  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
865  return true;
866  }
867 
868  /// Given a select instruction that was understood by
869  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
870  /// merging it with one of its operands. Returns NULL on failure.
871  ///
872  /// When successful, returns the new select instruction. The client is
873  /// responsible for deleting MI.
874  ///
875  /// If both sides of the select can be optimized, PreferFalse is used to pick
876  /// a side.
877  ///
878  /// @param MI Optimizable select instruction.
879  /// @param NewMIs Set that record all MIs in the basic block up to \p
880  /// MI. Has to be updated with any newly created MI or deleted ones.
881  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
882  /// @returns Optimized instruction or NULL.
885  bool PreferFalse = false) const {
886  // This function must be implemented if Optimizable is ever set.
887  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
888  }
889 
890  /// Emit instructions to copy a pair of physical registers.
891  ///
892  /// This function should support copies within any legal register class as
893  /// well as any cross-class copies created during instruction selection.
894  ///
895  /// The source and destination registers may overlap, which may require a
896  /// careful implementation when multiple copy instructions are required for
897  /// large registers. See for example the ARM target.
898  virtual void copyPhysReg(MachineBasicBlock &MBB,
900  unsigned DestReg, unsigned SrcReg,
901  bool KillSrc) const {
902  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
903  }
904 
905 protected:
906  /// Target-dependent implemenation for IsCopyInstr.
907  /// If the specific machine instruction is a instruction that moves/copies
908  /// value from one register to another register return true along with
909  /// @Source machine operand and @Destination machine operand.
910  virtual bool isCopyInstrImpl(const MachineInstr &MI,
911  const MachineOperand *&Source,
912  const MachineOperand *&Destination) const {
913  return false;
914  }
915 
916 public:
917  /// If the specific machine instruction is a instruction that moves/copies
918  /// value from one register to another register return true along with
919  /// @Source machine operand and @Destination machine operand.
920  /// For COPY-instruction the method naturally returns true, for all other
921  /// instructions the method calls target-dependent implementation.
923  const MachineOperand *&Destination) const {
924  if (MI.isCopy()) {
925  Destination = &MI.getOperand(0);
926  Source = &MI.getOperand(1);
927  return true;
928  }
929  return isCopyInstrImpl(MI, Source, Destination);
930  }
931 
932  /// Store the specified register of the given register class to the specified
933  /// stack frame index. The store instruction is to be added to the given
934  /// machine basic block before the specified machine instruction. If isKill
935  /// is true, the register operand is the last use and must be marked kill.
938  unsigned SrcReg, bool isKill, int FrameIndex,
939  const TargetRegisterClass *RC,
940  const TargetRegisterInfo *TRI) const {
941  llvm_unreachable("Target didn't implement "
942  "TargetInstrInfo::storeRegToStackSlot!");
943  }
944 
945  /// Load the specified register of the given register class from the specified
946  /// stack frame index. The load instruction is to be added to the given
947  /// machine basic block before the specified machine instruction.
950  unsigned DestReg, int FrameIndex,
951  const TargetRegisterClass *RC,
952  const TargetRegisterInfo *TRI) const {
953  llvm_unreachable("Target didn't implement "
954  "TargetInstrInfo::loadRegFromStackSlot!");
955  }
956 
957  /// This function is called for all pseudo instructions
958  /// that remain after register allocation. Many pseudo instructions are
959  /// created to help register allocation. This is the place to convert them
960  /// into real instructions. The target can edit MI in place, or it can insert
961  /// new instructions and erase MI. The function should return true if
962  /// anything was changed.
963  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
964 
965  /// Check whether the target can fold a load that feeds a subreg operand
966  /// (or a subreg operand that feeds a store).
967  /// For example, X86 may want to return true if it can fold
968  /// movl (%esp), %eax
969  /// subb, %al, ...
970  /// Into:
971  /// subb (%esp), ...
972  ///
973  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
974  /// reject subregs - but since this behavior used to be enforced in the
975  /// target-independent code, moving this responsibility to the targets
976  /// has the potential of causing nasty silent breakage in out-of-tree targets.
977  virtual bool isSubregFoldable() const { return false; }
978 
979  /// Attempt to fold a load or store of the specified stack
980  /// slot into the specified machine instruction for the specified operand(s).
981  /// If this is possible, a new instruction is returned with the specified
982  /// operand folded, otherwise NULL is returned.
983  /// The new instruction is inserted before MI, and the client is responsible
984  /// for removing the old instruction.
985  /// If VRM is passed, the assigned physregs can be inspected by target to
986  /// decide on using an opcode (note that those assignments can still change).
988  int FI,
989  LiveIntervals *LIS = nullptr,
990  VirtRegMap *VRM = nullptr) const;
991 
992  /// Same as the previous version except it allows folding of any load and
993  /// store from / to any address, not just from a specific stack slot.
995  MachineInstr &LoadMI,
996  LiveIntervals *LIS = nullptr) const;
997 
998  /// Return true when there is potentially a faster code sequence
999  /// for an instruction chain ending in \p Root. All potential patterns are
1000  /// returned in the \p Pattern vector. Pattern should be sorted in priority
1001  /// order since the pattern evaluator stops checking as soon as it finds a
1002  /// faster sequence.
1003  /// \param Root - Instruction that could be combined with one of its operands
1004  /// \param Patterns - Vector of possible combination patterns
1005  virtual bool getMachineCombinerPatterns(
1006  MachineInstr &Root,
1007  SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
1008 
1009  /// Return true when a code sequence can improve throughput. It
1010  /// should be called only for instructions in loops.
1011  /// \param Pattern - combiner pattern
1012  virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
1013 
1014  /// Return true if the input \P Inst is part of a chain of dependent ops
1015  /// that are suitable for reassociation, otherwise return false.
1016  /// If the instruction's operands must be commuted to have a previous
1017  /// instruction of the same type define the first source operand, \P Commuted
1018  /// will be set to true.
1019  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1020 
1021  /// Return true when \P Inst is both associative and commutative.
1022  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
1023  return false;
1024  }
1025 
1026  /// Return true when \P Inst has reassociable operands in the same \P MBB.
1027  virtual bool hasReassociableOperands(const MachineInstr &Inst,
1028  const MachineBasicBlock *MBB) const;
1029 
1030  /// Return true when \P Inst has reassociable sibling.
1031  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
1032 
1033  /// When getMachineCombinerPatterns() finds patterns, this function generates
1034  /// the instructions that could replace the original code sequence. The client
1035  /// has to decide whether the actual replacement is beneficial or not.
1036  /// \param Root - Instruction that could be combined with one of its operands
1037  /// \param Pattern - Combination pattern for Root
1038  /// \param InsInstrs - Vector of new instructions that implement P
1039  /// \param DelInstrs - Old instructions, including Root, that could be
1040  /// replaced by InsInstr
1041  /// \param InstIdxForVirtReg - map of virtual register to instruction in
1042  /// InsInstr that defines it
1043  virtual void genAlternativeCodeSequence(
1044  MachineInstr &Root, MachineCombinerPattern Pattern,
1047  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1048 
1049  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1050  /// reduce critical path length.
1051  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1052  MachineCombinerPattern Pattern,
1055  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1056 
1057  /// This is an architecture-specific helper function of reassociateOps.
1058  /// Set special operand attributes for new instructions after reassociation.
1059  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1060  MachineInstr &NewMI1,
1061  MachineInstr &NewMI2) const {}
1062 
1063  /// Return true when a target supports MachineCombiner.
1064  virtual bool useMachineCombiner() const { return false; }
1065 
1066  /// Return true if the given SDNode can be copied during scheduling
1067  /// even if it has glue.
1068  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1069 
1070 protected:
1071  /// Target-dependent implementation for foldMemoryOperand.
1072  /// Target-independent code in foldMemoryOperand will
1073  /// take care of adding a MachineMemOperand to the newly created instruction.
1074  /// The instruction and any auxiliary instructions necessary will be inserted
1075  /// at InsertPt.
1076  virtual MachineInstr *
1078  ArrayRef<unsigned> Ops,
1080  LiveIntervals *LIS = nullptr,
1081  VirtRegMap *VRM = nullptr) const {
1082  return nullptr;
1083  }
1084 
1085  /// Target-dependent implementation for foldMemoryOperand.
1086  /// Target-independent code in foldMemoryOperand will
1087  /// take care of adding a MachineMemOperand to the newly created instruction.
1088  /// The instruction and any auxiliary instructions necessary will be inserted
1089  /// at InsertPt.
1092  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1093  LiveIntervals *LIS = nullptr) const {
1094  return nullptr;
1095  }
1096 
1097  /// Target-dependent implementation of getRegSequenceInputs.
1098  ///
1099  /// \returns true if it is possible to build the equivalent
1100  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1101  ///
1102  /// \pre MI.isRegSequenceLike().
1103  ///
1104  /// \see TargetInstrInfo::getRegSequenceInputs.
1106  const MachineInstr &MI, unsigned DefIdx,
1107  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1108  return false;
1109  }
1110 
1111  /// Target-dependent implementation of getExtractSubregInputs.
1112  ///
1113  /// \returns true if it is possible to build the equivalent
1114  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1115  ///
1116  /// \pre MI.isExtractSubregLike().
1117  ///
1118  /// \see TargetInstrInfo::getExtractSubregInputs.
1120  unsigned DefIdx,
1121  RegSubRegPairAndIdx &InputReg) const {
1122  return false;
1123  }
1124 
1125  /// Target-dependent implementation of getInsertSubregInputs.
1126  ///
1127  /// \returns true if it is possible to build the equivalent
1128  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1129  ///
1130  /// \pre MI.isInsertSubregLike().
1131  ///
1132  /// \see TargetInstrInfo::getInsertSubregInputs.
1133  virtual bool
1134  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1135  RegSubRegPair &BaseReg,
1136  RegSubRegPairAndIdx &InsertedReg) const {
1137  return false;
1138  }
1139 
1140 public:
1141  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1142  /// (e.g. stack) the target returns the corresponding address space.
1143  virtual unsigned
1145  return 0;
1146  }
1147 
1148  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1149  /// a store or a load and a store into two or more instruction. If this is
1150  /// possible, returns true as well as the new instructions by reference.
1151  virtual bool
1153  bool UnfoldLoad, bool UnfoldStore,
1154  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1155  return false;
1156  }
1157 
1159  SmallVectorImpl<SDNode *> &NewNodes) const {
1160  return false;
1161  }
1162 
1163  /// Returns the opcode of the would be new
1164  /// instruction after load / store are unfolded from an instruction of the
1165  /// specified opcode. It returns zero if the specified unfolding is not
1166  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1167  /// index of the operand which will hold the register holding the loaded
1168  /// value.
1169  virtual unsigned
1170  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1171  unsigned *LoadRegIndex = nullptr) const {
1172  return 0;
1173  }
1174 
1175  /// This is used by the pre-regalloc scheduler to determine if two loads are
1176  /// loading from the same base address. It should only return true if the base
1177  /// pointers are the same and the only differences between the two addresses
1178  /// are the offset. It also returns the offsets by reference.
1179  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1180  int64_t &Offset1,
1181  int64_t &Offset2) const {
1182  return false;
1183  }
1184 
1185  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1186  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1187  /// On some targets if two loads are loading from
1188  /// addresses in the same cache line, it's better if they are scheduled
1189  /// together. This function takes two integers that represent the load offsets
1190  /// from the common base address. It returns true if it decides it's desirable
1191  /// to schedule the two loads together. "NumLoads" is the number of loads that
1192  /// have already been scheduled after Load1.
1193  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1194  int64_t Offset1, int64_t Offset2,
1195  unsigned NumLoads) const {
1196  return false;
1197  }
1198 
1199  /// Get the base operand and byte offset of an instruction that reads/writes
1200  /// memory.
1201  virtual bool getMemOperandWithOffset(const MachineInstr &MI,
1202  const MachineOperand *&BaseOp,
1203  int64_t &Offset,
1204  const TargetRegisterInfo *TRI) const {
1205  return false;
1206  }
1207 
1208  /// Return true if the instruction contains a base register and offset. If
1209  /// true, the function also sets the operand position in the instruction
1210  /// for the base register and offset.
1211  virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1212  unsigned &BasePos,
1213  unsigned &OffsetPos) const {
1214  return false;
1215  }
1216 
1217  /// If the instruction is an increment of a constant value, return the amount.
1218  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1219  return false;
1220  }
1221 
1222  /// Returns true if the two given memory operations should be scheduled
1223  /// adjacent. Note that you have to add:
1224  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1225  /// or
1226  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1227  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1228  virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1,
1229  const MachineOperand &BaseOp2,
1230  unsigned NumLoads) const {
1231  llvm_unreachable("target did not implement shouldClusterMemOps()");
1232  }
1233 
1234  /// Reverses the branch condition of the specified condition list,
1235  /// returning false on success and true if it cannot be reversed.
1236  virtual bool
1238  return true;
1239  }
1240 
1241  /// Insert a noop into the instruction stream at the specified point.
1242  virtual void insertNoop(MachineBasicBlock &MBB,
1243  MachineBasicBlock::iterator MI) const;
1244 
1245  /// Return the noop instruction to use for a noop.
1246  virtual void getNoop(MCInst &NopInst) const;
1247 
1248  /// Return true for post-incremented instructions.
1249  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1250 
1251  /// Returns true if the instruction is already predicated.
1252  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1253 
1254  /// Returns true if the instruction is a
1255  /// terminator instruction that has not been predicated.
1256  virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1257 
1258  /// Returns true if MI is an unconditional tail call.
1259  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1260  return false;
1261  }
1262 
1263  /// Returns true if the tail call can be made conditional on BranchCond.
1265  const MachineInstr &TailCall) const {
1266  return false;
1267  }
1268 
1269  /// Replace the conditional branch in MBB with a conditional tail call.
1272  const MachineInstr &TailCall) const {
1273  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1274  }
1275 
1276  /// Convert the instruction into a predicated instruction.
1277  /// It returns true if the operation was successful.
1278  virtual bool PredicateInstruction(MachineInstr &MI,
1279  ArrayRef<MachineOperand> Pred) const;
1280 
1281  /// Returns true if the first specified predicate
1282  /// subsumes the second, e.g. GE subsumes GT.
1284  ArrayRef<MachineOperand> Pred2) const {
1285  return false;
1286  }
1287 
1288  /// If the specified instruction defines any predicate
1289  /// or condition code register(s) used for predication, returns true as well
1290  /// as the definition predicate(s) by reference.
1291  virtual bool DefinesPredicate(MachineInstr &MI,
1292  std::vector<MachineOperand> &Pred) const {
1293  return false;
1294  }
1295 
1296  /// Return true if the specified instruction can be predicated.
1297  /// By default, this returns true for every instruction with a
1298  /// PredicateOperand.
1299  virtual bool isPredicable(const MachineInstr &MI) const {
1300  return MI.getDesc().isPredicable();
1301  }
1302 
1303  /// Return true if it's safe to move a machine
1304  /// instruction that defines the specified register class.
1305  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1306  return true;
1307  }
1308 
1309  /// Test if the given instruction should be considered a scheduling boundary.
1310  /// This primarily includes labels and terminators.
1311  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1312  const MachineBasicBlock *MBB,
1313  const MachineFunction &MF) const;
1314 
1315  /// Measure the specified inline asm to determine an approximation of its
1316  /// length.
1317  virtual unsigned getInlineAsmLength(
1318  const char *Str, const MCAsmInfo &MAI,
1319  const TargetSubtargetInfo *STI = nullptr) const;
1320 
1321  /// Allocate and return a hazard recognizer to use for this target when
1322  /// scheduling the machine instructions before register allocation.
1323  virtual ScheduleHazardRecognizer *
1325  const ScheduleDAG *DAG) const;
1326 
1327  /// Allocate and return a hazard recognizer to use for this target when
1328  /// scheduling the machine instructions before register allocation.
1329  virtual ScheduleHazardRecognizer *
1331  const ScheduleDAG *DAG) const;
1332 
1333  /// Allocate and return a hazard recognizer to use for this target when
1334  /// scheduling the machine instructions after register allocation.
1335  virtual ScheduleHazardRecognizer *
1337  const ScheduleDAG *DAG) const;
1338 
1339  /// Allocate and return a hazard recognizer to use for by non-scheduling
1340  /// passes.
1341  virtual ScheduleHazardRecognizer *
1343  return nullptr;
1344  }
1345 
1346  /// Provide a global flag for disabling the PreRA hazard recognizer that
1347  /// targets may choose to honor.
1348  bool usePreRAHazardRecognizer() const;
1349 
1350  /// For a comparison instruction, return the source registers
1351  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1352  /// compares against in CmpValue. Return true if the comparison instruction
1353  /// can be analyzed.
1354  virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1355  unsigned &SrcReg2, int &Mask, int &Value) const {
1356  return false;
1357  }
1358 
1359  /// See if the comparison instruction can be converted
1360  /// into something more efficient. E.g., on ARM most instructions can set the
1361  /// flags register, obviating the need for a separate CMP.
1362  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1363  unsigned SrcReg2, int Mask, int Value,
1364  const MachineRegisterInfo *MRI) const {
1365  return false;
1366  }
1367  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1368 
1369  /// Try to remove the load by folding it to a register operand at the use.
1370  /// We fold the load instructions if and only if the
1371  /// def and use are in the same BB. We only look at one load and see
1372  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1373  /// defined by the load we are trying to fold. DefMI returns the machine
1374  /// instruction that defines FoldAsLoadDefReg, and the function returns
1375  /// the machine instruction generated due to folding.
1377  const MachineRegisterInfo *MRI,
1378  unsigned &FoldAsLoadDefReg,
1379  MachineInstr *&DefMI) const {
1380  return nullptr;
1381  }
1382 
1383  /// 'Reg' is known to be defined by a move immediate instruction,
1384  /// try to fold the immediate into the use instruction.
1385  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1386  /// then the caller may assume that DefMI has been erased from its parent
1387  /// block. The caller may assume that it will not be erased by this
1388  /// function otherwise.
1390  unsigned Reg, MachineRegisterInfo *MRI) const {
1391  return false;
1392  }
1393 
1394  /// Return the number of u-operations the given machine
1395  /// instruction will be decoded to on the target cpu. The itinerary's
1396  /// IssueWidth is the number of microops that can be dispatched each
1397  /// cycle. An instruction with zero microops takes no dispatch resources.
1398  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1399  const MachineInstr &MI) const;
1400 
1401  /// Return true for pseudo instructions that don't consume any
1402  /// machine resources in their current form. These are common cases that the
1403  /// scheduler should consider free, rather than conservatively handling them
1404  /// as instructions with no itinerary.
1405  bool isZeroCost(unsigned Opcode) const {
1406  return Opcode <= TargetOpcode::COPY;
1407  }
1408 
1409  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1410  SDNode *DefNode, unsigned DefIdx,
1411  SDNode *UseNode, unsigned UseIdx) const;
1412 
1413  /// Compute and return the use operand latency of a given pair of def and use.
1414  /// In most cases, the static scheduling itinerary was enough to determine the
1415  /// operand latency. But it may not be possible for instructions with variable
1416  /// number of defs / uses.
1417  ///
1418  /// This is a raw interface to the itinerary that may be directly overridden
1419  /// by a target. Use computeOperandLatency to get the best estimate of
1420  /// latency.
1421  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1422  const MachineInstr &DefMI, unsigned DefIdx,
1423  const MachineInstr &UseMI,
1424  unsigned UseIdx) const;
1425 
1426  /// Compute the instruction latency of a given instruction.
1427  /// If the instruction has higher cost when predicated, it's returned via
1428  /// PredCost.
1429  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1430  const MachineInstr &MI,
1431  unsigned *PredCost = nullptr) const;
1432 
1433  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1434 
1435  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1436  SDNode *Node) const;
1437 
1438  /// Return the default expected latency for a def based on its opcode.
1439  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1440  const MachineInstr &DefMI) const;
1441 
1442  int computeDefOperandLatency(const InstrItineraryData *ItinData,
1443  const MachineInstr &DefMI) const;
1444 
1445  /// Return true if this opcode has high latency to its result.
1446  virtual bool isHighLatencyDef(int opc) const { return false; }
1447 
1448  /// Compute operand latency between a def of 'Reg'
1449  /// and a use in the current loop. Return true if the target considered
1450  /// it 'high'. This is used by optimization passes such as machine LICM to
1451  /// determine whether it makes sense to hoist an instruction out even in a
1452  /// high register pressure situation.
1453  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1454  const MachineRegisterInfo *MRI,
1455  const MachineInstr &DefMI, unsigned DefIdx,
1456  const MachineInstr &UseMI,
1457  unsigned UseIdx) const {
1458  return false;
1459  }
1460 
1461  /// Compute operand latency of a def of 'Reg'. Return true
1462  /// if the target considered it 'low'.
1463  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1464  const MachineInstr &DefMI,
1465  unsigned DefIdx) const;
1466 
1467  /// Perform target-specific instruction verification.
1468  virtual bool verifyInstruction(const MachineInstr &MI,
1469  StringRef &ErrInfo) const {
1470  return true;
1471  }
1472 
1473  /// Return the current execution domain and bit mask of
1474  /// possible domains for instruction.
1475  ///
1476  /// Some micro-architectures have multiple execution domains, and multiple
1477  /// opcodes that perform the same operation in different domains. For
1478  /// example, the x86 architecture provides the por, orps, and orpd
1479  /// instructions that all do the same thing. There is a latency penalty if a
1480  /// register is written in one domain and read in another.
1481  ///
1482  /// This function returns a pair (domain, mask) containing the execution
1483  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1484  /// function can be used to change the opcode to one of the domains in the
1485  /// bit mask. Instructions whose execution domain can't be changed should
1486  /// return a 0 mask.
1487  ///
1488  /// The execution domain numbers don't have any special meaning except domain
1489  /// 0 is used for instructions that are not associated with any interesting
1490  /// execution domain.
1491  ///
1492  virtual std::pair<uint16_t, uint16_t>
1494  return std::make_pair(0, 0);
1495  }
1496 
1497  /// Change the opcode of MI to execute in Domain.
1498  ///
1499  /// The bit (1 << Domain) must be set in the mask returned from
1500  /// getExecutionDomain(MI).
1501  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1502 
1503  /// Returns the preferred minimum clearance
1504  /// before an instruction with an unwanted partial register update.
1505  ///
1506  /// Some instructions only write part of a register, and implicitly need to
1507  /// read the other parts of the register. This may cause unwanted stalls
1508  /// preventing otherwise unrelated instructions from executing in parallel in
1509  /// an out-of-order CPU.
1510  ///
1511  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1512  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1513  /// the instruction needs to wait for the old value of the register to become
1514  /// available:
1515  ///
1516  /// addps %xmm1, %xmm0
1517  /// movaps %xmm0, (%rax)
1518  /// cvtsi2ss %rbx, %xmm0
1519  ///
1520  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1521  /// instruction before it can issue, even though the high bits of %xmm0
1522  /// probably aren't needed.
1523  ///
1524  /// This hook returns the preferred clearance before MI, measured in
1525  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1526  /// instructions before MI. It should only return a positive value for
1527  /// unwanted dependencies. If the old bits of the defined register have
1528  /// useful values, or if MI is determined to otherwise read the dependency,
1529  /// the hook should return 0.
1530  ///
1531  /// The unwanted dependency may be handled by:
1532  ///
1533  /// 1. Allocating the same register for an MI def and use. That makes the
1534  /// unwanted dependency identical to a required dependency.
1535  ///
1536  /// 2. Allocating a register for the def that has no defs in the previous N
1537  /// instructions.
1538  ///
1539  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1540  /// allows the target to insert a dependency breaking instruction.
1541  ///
1542  virtual unsigned
1543  getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1544  const TargetRegisterInfo *TRI) const {
1545  // The default implementation returns 0 for no partial register dependency.
1546  return 0;
1547  }
1548 
1549  /// Return the minimum clearance before an instruction that reads an
1550  /// unused register.
1551  ///
1552  /// For example, AVX instructions may copy part of a register operand into
1553  /// the unused high bits of the destination register.
1554  ///
1555  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1556  ///
1557  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1558  /// false dependence on any previous write to %xmm0.
1559  ///
1560  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1561  /// does not take an operand index. Instead sets \p OpNum to the index of the
1562  /// unused register.
1563  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1564  const TargetRegisterInfo *TRI) const {
1565  // The default implementation returns 0 for no undef register dependency.
1566  return 0;
1567  }
1568 
1569  /// Insert a dependency-breaking instruction
1570  /// before MI to eliminate an unwanted dependency on OpNum.
1571  ///
1572  /// If it wasn't possible to avoid a def in the last N instructions before MI
1573  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1574  /// unwanted dependency.
1575  ///
1576  /// On x86, an xorps instruction can be used as a dependency breaker:
1577  ///
1578  /// addps %xmm1, %xmm0
1579  /// movaps %xmm0, (%rax)
1580  /// xorps %xmm0, %xmm0
1581  /// cvtsi2ss %rbx, %xmm0
1582  ///
1583  /// An <imp-kill> operand should be added to MI if an instruction was
1584  /// inserted. This ties the instructions together in the post-ra scheduler.
1585  ///
1586  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1587  const TargetRegisterInfo *TRI) const {}
1588 
1589  /// Create machine specific model for scheduling.
1590  virtual DFAPacketizer *
1592  return nullptr;
1593  }
1594 
1595  /// Sometimes, it is possible for the target
1596  /// to tell, even without aliasing information, that two MIs access different
1597  /// memory addresses. This function returns true if two MIs access different
1598  /// memory addresses and false otherwise.
1599  ///
1600  /// Assumes any physical registers used to compute addresses have the same
1601  /// value for both instructions. (This is the most useful assumption for
1602  /// post-RA scheduling.)
1603  ///
1604  /// See also MachineInstr::mayAlias, which is implemented on top of this
1605  /// function.
1606  virtual bool
1608  const MachineInstr &MIb,
1609  AliasAnalysis *AA = nullptr) const {
1610  assert((MIa.mayLoad() || MIa.mayStore()) &&
1611  "MIa must load from or modify a memory location");
1612  assert((MIb.mayLoad() || MIb.mayStore()) &&
1613  "MIb must load from or modify a memory location");
1614  return false;
1615  }
1616 
1617  /// Return the value to use for the MachineCSE's LookAheadLimit,
1618  /// which is a heuristic used for CSE'ing phys reg defs.
1619  virtual unsigned getMachineCSELookAheadLimit() const {
1620  // The default lookahead is small to prevent unprofitable quadratic
1621  // behavior.
1622  return 5;
1623  }
1624 
1625  /// Return an array that contains the ids of the target indices (used for the
1626  /// TargetIndex machine operand) and their names.
1627  ///
1628  /// MIR Serialization is able to serialize only the target indices that are
1629  /// defined by this method.
1632  return None;
1633  }
1634 
1635  /// Decompose the machine operand's target flags into two values - the direct
1636  /// target flag value and any of bit flags that are applied.
1637  virtual std::pair<unsigned, unsigned>
1638  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1639  return std::make_pair(0u, 0u);
1640  }
1641 
1642  /// Return an array that contains the direct target flag values and their
1643  /// names.
1644  ///
1645  /// MIR Serialization is able to serialize only the target flags that are
1646  /// defined by this method.
1649  return None;
1650  }
1651 
1652  /// Return an array that contains the bitmask target flag values and their
1653  /// names.
1654  ///
1655  /// MIR Serialization is able to serialize only the target flags that are
1656  /// defined by this method.
1659  return None;
1660  }
1661 
1662  /// Return an array that contains the MMO target flag values and their
1663  /// names.
1664  ///
1665  /// MIR Serialization is able to serialize only the MMO target flags that are
1666  /// defined by this method.
1669  return None;
1670  }
1671 
1672  /// Determines whether \p Inst is a tail call instruction. Override this
1673  /// method on targets that do not properly set MCID::Return and MCID::Call on
1674  /// tail call instructions."
1675  virtual bool isTailCall(const MachineInstr &Inst) const {
1676  return Inst.isReturn() && Inst.isCall();
1677  }
1678 
1679  /// True if the instruction is bound to the top of its basic block and no
1680  /// other instructions shall be inserted before it. This can be implemented
1681  /// to prevent register allocator to insert spills before such instructions.
1682  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1683  return false;
1684  }
1685 
1686  /// During PHI eleimination lets target to make necessary checks and
1687  /// insert the copy to the PHI destination register in a target specific
1688  /// manner.
1691  const DebugLoc &DL, Register Src, Register Dst) const {
1692  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1693  .addReg(Src);
1694  }
1695 
1696  /// During PHI eleimination lets target to make necessary checks and
1697  /// insert the copy to the PHI destination register in a target specific
1698  /// manner.
1701  const DebugLoc &DL, Register Src,
1702  Register SrcSubReg,
1703  Register Dst) const {
1704  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1705  .addReg(Src, 0, SrcSubReg);
1706  }
1707 
1708  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1709  /// information for a set of outlining candidates.
1711  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1713  "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1714  }
1715 
1716  /// Returns how or if \p MI should be outlined.
1717  virtual outliner::InstrType
1718  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1720  "Target didn't implement TargetInstrInfo::getOutliningType!");
1721  }
1722 
1723  /// Optional target hook that returns true if \p MBB is safe to outline from,
1724  /// and returns any target-specific information in \p Flags.
1726  unsigned &Flags) const {
1727  return true;
1728  }
1729 
1730  /// Insert a custom frame for outlined functions.
1732  const outliner::OutlinedFunction &OF) const {
1734  "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1735  }
1736 
1737  /// Insert a call to an outlined function into the program.
1738  /// Returns an iterator to the spot where we inserted the call. This must be
1739  /// implemented by the target.
1743  const outliner::Candidate &C) const {
1745  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1746  }
1747 
1748  /// Return true if the function can safely be outlined from.
1749  /// A function \p MF is considered safe for outlining if an outlined function
1750  /// produced from instructions in F will produce a program which produces the
1751  /// same output for any set of given inputs.
1753  bool OutlineFromLinkOnceODRs) const {
1754  llvm_unreachable("Target didn't implement "
1755  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1756  }
1757 
1758  /// Return true if the function should be outlined from by default.
1760  return false;
1761  }
1762 
1763  /// Produce the expression describing the \p MI loading a value into
1764  /// the parameter's forwarding register.
1766  describeLoadedValue(const MachineInstr &MI) const;
1767 
1768 private:
1769  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1770  unsigned CatchRetOpcode;
1771  unsigned ReturnOpcode;
1772 };
1773 
1774 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1777 
1779  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1780  RegInfo::getEmptyKey());
1781  }
1782 
1784  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1785  RegInfo::getTombstoneKey());
1786  }
1787 
1788  /// Reuse getHashValue implementation from
1789  /// std::pair<unsigned, unsigned>.
1790  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1791  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1792  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1793  }
1794 
1795  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1796  const TargetInstrInfo::RegSubRegPair &RHS) {
1797  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1798  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1799  }
1800 };
1801 
1802 } // end namespace llvm
1803 
1804 #endif // LLVM_TARGET_TARGETINSTRINFO_H
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand&#39;s target flags into two values - the direct target flag value and any o...
uint64_t CallInst * C
virtual std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:722
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:651
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true...
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it&#39;s safe to move a machine instruction that defines the specified register class...
virtual bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const
Target-dependent implemenation for IsCopyInstr.
Object returned by analyzeLoopForPipelining.
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr *> &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
RegSubRegPair(unsigned Reg=0, unsigned SubReg=0)
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
virtual bool DefinesPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient. ...
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:178
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore...
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when Inst has reassociable operands in the same MBB.
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
unsigned const TargetRegisterInfo * TRI
A debug info location.
Definition: DebugLoc.h:33
unsigned getCallFrameDestroyOpcode() const
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
static bool isGenericOpcode(unsigned Opc)
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
An individual sequence of instructions to be replaced with a call to an outlined function.
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Represents a predicate at the MachineFunction level.
virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE&#39;s LookAheadLimit, which is a heuristic used for CSE&#39;ing ph...
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack...
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified &#39;original&#39; instruction at the specific location targeting a new destination re...
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const
Insert a call to an outlined function into the program.
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Provide an instruction scheduling machine model to CodeGen passes.
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum...
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const
&#39;Reg&#39; is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr *> &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
bool operator!=(const RegSubRegPair &P) const
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of &#39;Reg&#39;.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
virtual MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
unsigned getCatchReturnOpcode() const
virtual bool shouldClusterMemOps(const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const
Returns true if the two given memory operations should be scheduled adjacent.
bool isSelect() const
Return true if this is a select instruction.
Definition: MCInstrDesc.h:335
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:408
static bool isEqual(const Function &Caller, const Function &Callee)
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode *> &NewNodes) const
bool isRematerializable() const
Returns true if this instruction is a candidate for remat.
Definition: MCInstrDesc.h:500
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it&#39;s profitable to predicate instructions with accumulated instruction latency of "Num...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Itinerary data supplied by a subtarget to be used by a target.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
RegSubRegPairAndIdx(unsigned Reg=0, unsigned SubReg=0, unsigned SubIdx=0)
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr *> &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true...
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
BasicBlockListType::iterator iterator
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
TargetInstrInfo - Interface to description of machine instruction set.
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:641
virtual void getNoop(MCInst &NopInst) const
Return the noop instruction to use for a noop.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
TargetInstrInfo::RegSubRegPair RegSubRegPair
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor...
bool operator==(const RegSubRegPair &P) const
static const unsigned CommuteAnyOperandIndex
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
Definition: MachineInstr.h:838
#define P(N)
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
virtual MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
unsigned const MachineRegisterInfo * MRI
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
virtual unsigned getPredicationCost(const MachineInstr &MI) const
HazardRecognizer - This determines whether or not an instruction can be issued this cycle...
InstrType
Represents how an instruction should be mapped by the outliner.
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
MachineInstrBuilder & UseMI
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it&#39;s legal to split the given basic block at the specified instruction (i...
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack...
The information necessary to create an outlined function for some class of candidate.
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu...
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
Contains all data structures shared between the outliner implemented in MachineOutliner.cpp and target implementations of the outliner.
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise)...
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input Inst is part of a chain of dependent ops that are suitable for reassociatio...
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
A set of register units.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:322
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister...
bool isCopy() const
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e...
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
virtual bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
virtual unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
virtual bool optimizeCondBranch(MachineInstr &MI) const
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate Root and Prev according to Pattern to reduce critical path length...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:221
MachineOperand class - Representation of each machine instruction operand.
A pair composed of a register and a sub-register index.
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of &#39;Reg&#39; and a use in the current loop.
MachineInstrBuilder MachineInstrBuilder & DefMI
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
Definition: PPCPredicates.h:26
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it&#39;s profitable for if-converter to duplicate instructions of specified accumulated in...
virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Represents one node in the SelectionDAG.
virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
int64_t getImm() const
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction...
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const
Sometimes, it is possible for the target to tell, even without aliasing information, that two MIs access different memory addresses.
virtual MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register SrcSubReg, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
unsigned getReturnOpcode() const
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index...
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI) const
Produce the expression describing the MI loading a value into the parameter&#39;s forwarding register...
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Representation of each machine instruction.
Definition: MachineInstr.h:64
static TargetInstrInfo::RegSubRegPair getEmptyKey()
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understoo.
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1...
bool isCopyInstr(const MachineInstr &MI, const MachineOperand *&Source, const MachineOperand *&Destination) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand *> &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum...
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr *> &InsInstrs, SmallVectorImpl< MachineInstr *> &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
static MachineOperand CreateImm(int64_t Val)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don&#39;t consume any machine resources in their current form...
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
uint32_t Size
Definition: Profile.cpp:46
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:825
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
LLVM Value Representation.
Definition: Value.h:73
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when Inst has reassociable sibling.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when Inst is both associative and commutative.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
IRTranslator LLVM IR MI
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
bool isTriviallyReMaterializable(const MachineInstr &MI, AliasAnalysis *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it&#39;s profitable to unpredicate one side of a &#39;diamond&#39;, i.e.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
int computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr &DefMI) const
If we can determine the operand latency from the def only, without itinerary lookup, do so.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index...
bool isAsCheapAsAMove(QueryType Type=AllInBundle) const
Returns true if this instruction has the same cost (or less) than a move instruction.
Definition: MachineInstr.h:935
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence...
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register. ...
A pair composed of a pair of a register and a sub-register index, and another sub-register index...