LLVM  15.0.0git
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETINSTRINFO_H
14 #define LLVM_CODEGEN_TARGETINSTRINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
30 #include "llvm/MC/MCInstrInfo.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <utility>
37 #include <vector>
38 
39 namespace llvm {
40 
41 class AAResults;
42 class DFAPacketizer;
43 class InstrItineraryData;
44 class LiveIntervals;
45 class LiveVariables;
46 class MachineLoop;
47 class MachineMemOperand;
48 class MachineRegisterInfo;
49 class MCAsmInfo;
50 class MCInst;
51 struct MCSchedModel;
52 class Module;
53 class ScheduleDAG;
54 class ScheduleDAGMI;
55 class ScheduleHazardRecognizer;
56 class SDNode;
57 class SelectionDAG;
58 class RegScavenger;
59 class TargetRegisterClass;
60 class TargetRegisterInfo;
61 class TargetSchedModel;
62 class TargetSubtargetInfo;
63 
64 template <class T> class SmallVectorImpl;
65 
66 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
67 
71 
72  DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
73  : Destination(&Dest), Source(&Src) {}
74 };
75 
76 /// Used to describe a register and immediate addition.
77 struct RegImmPair {
79  int64_t Imm;
80 
81  RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {}
82 };
83 
84 /// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
85 /// It holds the register values, the scale value and the displacement.
86 struct ExtAddrMode {
89  int64_t Scale;
90  int64_t Displacement;
91 };
92 
93 //---------------------------------------------------------------------------
94 ///
95 /// TargetInstrInfo - Interface to description of machine instruction set
96 ///
97 class TargetInstrInfo : public MCInstrInfo {
98 public:
99  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
100  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
101  : CallFrameSetupOpcode(CFSetupOpcode),
102  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
103  ReturnOpcode(ReturnOpcode) {}
104  TargetInstrInfo(const TargetInstrInfo &) = delete;
105  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
106  virtual ~TargetInstrInfo();
107 
108  static bool isGenericOpcode(unsigned Opc) {
109  return Opc <= TargetOpcode::GENERIC_OP_END;
110  }
111 
112  /// Given a machine instruction descriptor, returns the register
113  /// class constraint for OpNum, or NULL.
114  virtual
115  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
116  const TargetRegisterInfo *TRI,
117  const MachineFunction &MF) const;
118 
119  /// Return true if the instruction is trivially rematerializable, meaning it
120  /// has no side effects and requires no operands that aren't always available.
121  /// This means the only allowed uses are constants and unallocatable physical
122  /// registers so that the instructions result is independent of the place
123  /// in the function.
125  AAResults *AA = nullptr) const {
126  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
127  (MI.getDesc().isRematerializable() &&
129  isReallyTriviallyReMaterializableGeneric(MI, AA)));
130  }
131 
132  /// Given \p MO is a PhysReg use return if it can be ignored for the purpose
133  /// of instruction rematerialization or sinking.
134  virtual bool isIgnorableUse(const MachineOperand &MO) const {
135  return false;
136  }
137 
138 protected:
139  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
140  /// set, this hook lets the target specify whether the instruction is actually
141  /// trivially rematerializable, taking into consideration its operands. This
142  /// predicate must return false if the instruction has any side effects other
143  /// than producing a value, or if it requres any address registers that are
144  /// not always available.
145  /// Requirements must be check as stated in isTriviallyReMaterializable() .
147  AAResults *AA) const {
148  return false;
149  }
150 
151  /// This method commutes the operands of the given machine instruction MI.
152  /// The operands to be commuted are specified by their indices OpIdx1 and
153  /// OpIdx2.
154  ///
155  /// If a target has any instructions that are commutable but require
156  /// converting to different instructions or making non-trivial changes
157  /// to commute them, this method can be overloaded to do that.
158  /// The default implementation simply swaps the commutable operands.
159  ///
160  /// If NewMI is false, MI is modified in place and returned; otherwise, a
161  /// new machine instruction is created and returned.
162  ///
163  /// Do not call this method for a non-commutable instruction.
164  /// Even though the instruction is commutable, the method may still
165  /// fail to commute the operands, null pointer is returned in such cases.
166  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
167  unsigned OpIdx1,
168  unsigned OpIdx2) const;
169 
170  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
171  /// operand indices to (ResultIdx1, ResultIdx2).
172  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
173  /// predefined to some indices or be undefined (designated by the special
174  /// value 'CommuteAnyOperandIndex').
175  /// The predefined result indices cannot be re-defined.
176  /// The function returns true iff after the result pair redefinition
177  /// the fixed result pair is equal to or equivalent to the source pair of
178  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
179  /// the pairs (x,y) and (y,x) are equivalent.
180  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
181  unsigned CommutableOpIdx1,
182  unsigned CommutableOpIdx2);
183 
184 private:
185  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
186  /// set and the target hook isReallyTriviallyReMaterializable returns false,
187  /// this function does target-independent tests to determine if the
188  /// instruction is really trivially rematerializable.
189  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
190  AAResults *AA) const;
191 
192 public:
193  /// These methods return the opcode of the frame setup/destroy instructions
194  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
195  /// order to abstract away the difference between operating with a frame
196  /// pointer and operating without, through the use of these two instructions.
197  ///
198  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
199  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
200 
201  /// Returns true if the argument is a frame pseudo instruction.
202  bool isFrameInstr(const MachineInstr &I) const {
203  return I.getOpcode() == getCallFrameSetupOpcode() ||
204  I.getOpcode() == getCallFrameDestroyOpcode();
205  }
206 
207  /// Returns true if the argument is a frame setup pseudo instruction.
208  bool isFrameSetup(const MachineInstr &I) const {
209  return I.getOpcode() == getCallFrameSetupOpcode();
210  }
211 
212  /// Returns size of the frame associated with the given frame instruction.
213  /// For frame setup instruction this is frame that is set up space set up
214  /// after the instruction. For frame destroy instruction this is the frame
215  /// freed by the caller.
216  /// Note, in some cases a call frame (or a part of it) may be prepared prior
217  /// to the frame setup instruction. It occurs in the calls that involve
218  /// inalloca arguments. This function reports only the size of the frame part
219  /// that is set up between the frame setup and destroy pseudo instructions.
220  int64_t getFrameSize(const MachineInstr &I) const {
221  assert(isFrameInstr(I) && "Not a frame instruction");
222  assert(I.getOperand(0).getImm() >= 0);
223  return I.getOperand(0).getImm();
224  }
225 
226  /// Returns the total frame size, which is made up of the space set up inside
227  /// the pair of frame start-stop instructions and the space that is set up
228  /// prior to the pair.
229  int64_t getFrameTotalSize(const MachineInstr &I) const {
230  if (isFrameSetup(I)) {
231  assert(I.getOperand(1).getImm() >= 0 &&
232  "Frame size must not be negative");
233  return getFrameSize(I) + I.getOperand(1).getImm();
234  }
235  return getFrameSize(I);
236  }
237 
238  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
239  unsigned getReturnOpcode() const { return ReturnOpcode; }
240 
241  /// Returns the actual stack pointer adjustment made by an instruction
242  /// as part of a call sequence. By default, only call frame setup/destroy
243  /// instructions adjust the stack, but targets may want to override this
244  /// to enable more fine-grained adjustment, or adjust by a different value.
245  virtual int getSPAdjust(const MachineInstr &MI) const;
246 
247  /// Return true if the instruction is a "coalescable" extension instruction.
248  /// That is, it's like a copy where it's legal for the source to overlap the
249  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
250  /// expected the pre-extension value is available as a subreg of the result
251  /// register. This also returns the sub-register index in SubIdx.
252  virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
253  Register &DstReg, unsigned &SubIdx) const {
254  return false;
255  }
256 
257  /// If the specified machine instruction is a direct
258  /// load from a stack slot, return the virtual or physical register number of
259  /// the destination along with the FrameIndex of the loaded stack slot. If
260  /// not, return 0. This predicate must return 0 if the instruction has
261  /// any side effects other than loading from the stack slot.
262  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
263  int &FrameIndex) const {
264  return 0;
265  }
266 
267  /// Optional extension of isLoadFromStackSlot that returns the number of
268  /// bytes loaded from the stack. This must be implemented if a backend
269  /// supports partial stack slot spills/loads to further disambiguate
270  /// what the load does.
271  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
272  int &FrameIndex,
273  unsigned &MemBytes) const {
274  MemBytes = 0;
276  }
277 
278  /// Check for post-frame ptr elimination stack locations as well.
279  /// This uses a heuristic so it isn't reliable for correctness.
280  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
281  int &FrameIndex) const {
282  return 0;
283  }
284 
285  /// If the specified machine instruction has a load from a stack slot,
286  /// return true along with the FrameIndices of the loaded stack slot and the
287  /// machine mem operands containing the reference.
288  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
289  /// any instructions that loads from the stack. This is just a hint, as some
290  /// cases may be missed.
291  virtual bool hasLoadFromStackSlot(
292  const MachineInstr &MI,
294 
295  /// If the specified machine instruction is a direct
296  /// store to a stack slot, return the virtual or physical register number of
297  /// the source reg along with the FrameIndex of the loaded stack slot. If
298  /// not, return 0. This predicate must return 0 if the instruction has
299  /// any side effects other than storing to the stack slot.
300  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
301  int &FrameIndex) const {
302  return 0;
303  }
304 
305  /// Optional extension of isStoreToStackSlot that returns the number of
306  /// bytes stored to the stack. This must be implemented if a backend
307  /// supports partial stack slot spills/loads to further disambiguate
308  /// what the store does.
309  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
310  int &FrameIndex,
311  unsigned &MemBytes) const {
312  MemBytes = 0;
314  }
315 
316  /// Check for post-frame ptr elimination stack locations as well.
317  /// This uses a heuristic, so it isn't reliable for correctness.
318  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
319  int &FrameIndex) const {
320  return 0;
321  }
322 
323  /// If the specified machine instruction has a store to a stack slot,
324  /// return true along with the FrameIndices of the loaded stack slot and the
325  /// machine mem operands containing the reference.
326  /// If not, return false. Unlike isStoreToStackSlot,
327  /// this returns true for any instructions that stores to the
328  /// stack. This is just a hint, as some cases may be missed.
329  virtual bool hasStoreToStackSlot(
330  const MachineInstr &MI,
332 
333  /// Return true if the specified machine instruction
334  /// is a copy of one stack slot to another and has no other effect.
335  /// Provide the identity of the two frame indices.
336  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
337  int &SrcFrameIndex) const {
338  return false;
339  }
340 
341  /// Compute the size in bytes and offset within a stack slot of a spilled
342  /// register or subregister.
343  ///
344  /// \param [out] Size in bytes of the spilled value.
345  /// \param [out] Offset in bytes within the stack slot.
346  /// \returns true if both Size and Offset are successfully computed.
347  ///
348  /// Not all subregisters have computable spill slots. For example,
349  /// subregisters registers may not be byte-sized, and a pair of discontiguous
350  /// subregisters has no single offset.
351  ///
352  /// Targets with nontrivial bigendian implementations may need to override
353  /// this, particularly to support spilled vector registers.
354  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
355  unsigned &Size, unsigned &Offset,
356  const MachineFunction &MF) const;
357 
358  /// Return true if the given instruction is terminator that is unspillable,
359  /// according to isUnspillableTerminatorImpl.
361  return MI->isTerminator() && isUnspillableTerminatorImpl(MI);
362  }
363 
364  /// Returns the size in bytes of the specified MachineInstr, or ~0U
365  /// when this function is not implemented by a target.
366  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
367  return ~0U;
368  }
369 
370  /// Return true if the instruction is as cheap as a move instruction.
371  ///
372  /// Targets for different archs need to override this, and different
373  /// micro-architectures can also be finely tuned inside.
374  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
375  return MI.isAsCheapAsAMove();
376  }
377 
378  /// Return true if the instruction should be sunk by MachineSink.
379  ///
380  /// MachineSink determines on its own whether the instruction is safe to sink;
381  /// this gives the target a hook to override the default behavior with regards
382  /// to which instructions should be sunk.
383  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
384 
385  /// Return false if the instruction should not be hoisted by MachineLICM.
386  ///
387  /// MachineLICM determines on its own whether the instruction is safe to
388  /// hoist; this gives the target a hook to extend this assessment and prevent
389  /// an instruction being hoisted from a given loop for target specific
390  /// reasons.
391  virtual bool shouldHoist(const MachineInstr &MI,
392  const MachineLoop *FromLoop) const {
393  return true;
394  }
395 
396  /// Re-issue the specified 'original' instruction at the
397  /// specific location targeting a new destination register.
398  /// The register in Orig->getOperand(0).getReg() will be substituted by
399  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
400  /// SubIdx.
401  virtual void reMaterialize(MachineBasicBlock &MBB,
403  unsigned SubIdx, const MachineInstr &Orig,
404  const TargetRegisterInfo &TRI) const;
405 
406  /// Clones instruction or the whole instruction bundle \p Orig and
407  /// insert into \p MBB before \p InsertBefore. The target may update operands
408  /// that are required to be unique.
409  ///
410  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
412  MachineBasicBlock::iterator InsertBefore,
413  const MachineInstr &Orig) const;
414 
415  /// This method must be implemented by targets that
416  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
417  /// may be able to convert a two-address instruction into one or more true
418  /// three-address instructions on demand. This allows the X86 target (for
419  /// example) to convert ADD and SHL instructions into LEA instructions if they
420  /// would require register copies due to two-addressness.
421  ///
422  /// This method returns a null pointer if the transformation cannot be
423  /// performed, otherwise it returns the last new instruction.
424  ///
425  /// If \p LIS is not nullptr, the LiveIntervals info should be updated for
426  /// replacing \p MI with new instructions, even though this function does not
427  /// remove MI.
429  LiveVariables *LV,
430  LiveIntervals *LIS) const {
431  return nullptr;
432  }
433 
434  // This constant can be used as an input value of operand index passed to
435  // the method findCommutedOpIndices() to tell the method that the
436  // corresponding operand index is not pre-defined and that the method
437  // can pick any commutable operand.
438  static const unsigned CommuteAnyOperandIndex = ~0U;
439 
440  /// This method commutes the operands of the given machine instruction MI.
441  ///
442  /// The operands to be commuted are specified by their indices OpIdx1 and
443  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
444  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
445  /// any arbitrarily chosen commutable operand. If both arguments are set to
446  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
447  /// operands; then commutes them if such operands could be found.
448  ///
449  /// If NewMI is false, MI is modified in place and returned; otherwise, a
450  /// new machine instruction is created and returned.
451  ///
452  /// Do not call this method for a non-commutable instruction or
453  /// for non-commuable operands.
454  /// Even though the instruction is commutable, the method may still
455  /// fail to commute the operands, null pointer is returned in such cases.
456  MachineInstr *
457  commuteInstruction(MachineInstr &MI, bool NewMI = false,
458  unsigned OpIdx1 = CommuteAnyOperandIndex,
459  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
460 
461  /// Returns true iff the routine could find two commutable operands in the
462  /// given machine instruction.
463  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
464  /// If any of the INPUT values is set to the special value
465  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
466  /// operand, then returns its index in the corresponding argument.
467  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
468  /// looks for 2 commutable operands.
469  /// If INPUT values refer to some operands of MI, then the method simply
470  /// returns true if the corresponding operands are commutable and returns
471  /// false otherwise.
472  ///
473  /// For example, calling this method this way:
474  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
475  /// findCommutedOpIndices(MI, Op1, Op2);
476  /// can be interpreted as a query asking to find an operand that would be
477  /// commutable with the operand#1.
478  virtual bool findCommutedOpIndices(const MachineInstr &MI,
479  unsigned &SrcOpIdx1,
480  unsigned &SrcOpIdx2) const;
481 
482  /// Returns true if the target has a preference on the operands order of
483  /// the given machine instruction. And specify if \p Commute is required to
484  /// get the desired operands order.
485  virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
486  return false;
487  }
488 
489  /// A pair composed of a register and a sub-register index.
490  /// Used to give some type checking when modeling Reg:SubReg.
491  struct RegSubRegPair {
493  unsigned SubReg;
494 
496  : Reg(Reg), SubReg(SubReg) {}
497 
498  bool operator==(const RegSubRegPair& P) const {
499  return Reg == P.Reg && SubReg == P.SubReg;
500  }
501  bool operator!=(const RegSubRegPair& P) const {
502  return !(*this == P);
503  }
504  };
505 
506  /// A pair composed of a pair of a register and a sub-register index,
507  /// and another sub-register index.
508  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
510  unsigned SubIdx;
511 
513  unsigned SubIdx = 0)
515  };
516 
517  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
518  /// and \p DefIdx.
519  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
520  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
521  /// flag are not added to this list.
522  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
523  /// two elements:
524  /// - %1:sub1, sub0
525  /// - %2<:0>, sub1
526  ///
527  /// \returns true if it is possible to build such an input sequence
528  /// with the pair \p MI, \p DefIdx. False otherwise.
529  ///
530  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
531  ///
532  /// \note The generic implementation does not provide any support for
533  /// MI.isRegSequenceLike(). In other words, one has to override
534  /// getRegSequenceLikeInputs for target specific instructions.
535  bool
536  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
537  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
538 
539  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
540  /// and \p DefIdx.
541  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
542  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
543  /// - %1:sub1, sub0
544  ///
545  /// \returns true if it is possible to build such an input sequence
546  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
547  /// False otherwise.
548  ///
549  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
550  ///
551  /// \note The generic implementation does not provide any support for
552  /// MI.isExtractSubregLike(). In other words, one has to override
553  /// getExtractSubregLikeInputs for target specific instructions.
554  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
555  RegSubRegPairAndIdx &InputReg) const;
556 
557  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
558  /// and \p DefIdx.
559  /// \p [out] BaseReg and \p [out] InsertedReg contain
560  /// the equivalent inputs of INSERT_SUBREG.
561  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
562  /// - BaseReg: %0:sub0
563  /// - InsertedReg: %1:sub1, sub3
564  ///
565  /// \returns true if it is possible to build such an input sequence
566  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
567  /// False otherwise.
568  ///
569  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
570  ///
571  /// \note The generic implementation does not provide any support for
572  /// MI.isInsertSubregLike(). In other words, one has to override
573  /// getInsertSubregLikeInputs for target specific instructions.
574  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
575  RegSubRegPair &BaseReg,
576  RegSubRegPairAndIdx &InsertedReg) const;
577 
578  /// Return true if two machine instructions would produce identical values.
579  /// By default, this is only true when the two instructions
580  /// are deemed identical except for defs. If this function is called when the
581  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
582  /// aggressive checks.
583  virtual bool produceSameValue(const MachineInstr &MI0,
584  const MachineInstr &MI1,
585  const MachineRegisterInfo *MRI = nullptr) const;
586 
587  /// \returns true if a branch from an instruction with opcode \p BranchOpc
588  /// bytes is capable of jumping to a position \p BrOffset bytes away.
589  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
590  int64_t BrOffset) const {
591  llvm_unreachable("target did not implement");
592  }
593 
594  /// \returns The block that branch instruction \p MI jumps to.
596  llvm_unreachable("target did not implement");
597  }
598 
599  /// Insert an unconditional indirect branch at the end of \p MBB to \p
600  /// NewDestBB. Optionally, insert the clobbered register restoring in \p
601  /// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to
602  /// the offset of the position to insert the new branch.
604  MachineBasicBlock &NewDestBB,
605  MachineBasicBlock &RestoreBB,
606  const DebugLoc &DL, int64_t BrOffset = 0,
607  RegScavenger *RS = nullptr) const {
608  llvm_unreachable("target did not implement");
609  }
610 
611  /// Analyze the branching code at the end of MBB, returning
612  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
613  /// implemented for a target). Upon success, this returns false and returns
614  /// with the following information in various cases:
615  ///
616  /// 1. If this block ends with no branches (it just falls through to its succ)
617  /// just return false, leaving TBB/FBB null.
618  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
619  /// the destination block.
620  /// 3. If this block ends with a conditional branch and it falls through to a
621  /// successor block, it sets TBB to be the branch destination block and a
622  /// list of operands that evaluate the condition. These operands can be
623  /// passed to other TargetInstrInfo methods to create new branches.
624  /// 4. If this block ends with a conditional branch followed by an
625  /// unconditional branch, it returns the 'true' destination in TBB, the
626  /// 'false' destination in FBB, and a list of operands that evaluate the
627  /// condition. These operands can be passed to other TargetInstrInfo
628  /// methods to create new branches.
629  ///
630  /// Note that removeBranch and insertBranch must be implemented to support
631  /// cases where this method returns success.
632  ///
633  /// If AllowModify is true, then this routine is allowed to modify the basic
634  /// block (e.g. delete instructions after the unconditional branch).
635  ///
636  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
637  /// before calling this function.
639  MachineBasicBlock *&FBB,
641  bool AllowModify = false) const {
642  return true;
643  }
644 
645  /// Represents a predicate at the MachineFunction level. The control flow a
646  /// MachineBranchPredicate represents is:
647  ///
648  /// Reg = LHS `Predicate` RHS == ConditionDef
649  /// if Reg then goto TrueDest else goto FalseDest
650  ///
653  PRED_EQ, // True if two values are equal
654  PRED_NE, // True if two values are not equal
655  PRED_INVALID // Sentinel value
656  };
657 
664 
665  /// SingleUseCondition is true if ConditionDef is dead except for the
666  /// branch(es) at the end of the basic block.
667  ///
668  bool SingleUseCondition = false;
669 
670  explicit MachineBranchPredicate() = default;
671  };
672 
673  /// Analyze the branching code at the end of MBB and parse it into the
674  /// MachineBranchPredicate structure if possible. Returns false on success
675  /// and true on failure.
676  ///
677  /// If AllowModify is true, then this routine is allowed to modify the basic
678  /// block (e.g. delete instructions after the unconditional branch).
679  ///
682  bool AllowModify = false) const {
683  return true;
684  }
685 
686  /// Remove the branching code at the end of the specific MBB.
687  /// This is only invoked in cases where analyzeBranch returns success. It
688  /// returns the number of instructions that were removed.
689  /// If \p BytesRemoved is non-null, report the change in code size from the
690  /// removed instructions.
691  virtual unsigned removeBranch(MachineBasicBlock &MBB,
692  int *BytesRemoved = nullptr) const {
693  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
694  }
695 
696  /// Insert branch code into the end of the specified MachineBasicBlock. The
697  /// operands to this method are the same as those returned by analyzeBranch.
698  /// This is only invoked in cases where analyzeBranch returns success. It
699  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
700  /// report the change in code size from the added instructions.
701  ///
702  /// It is also invoked by tail merging to add unconditional branches in
703  /// cases where analyzeBranch doesn't apply because there was no original
704  /// branch to analyze. At least this much must be implemented, else tail
705  /// merging needs to be disabled.
706  ///
707  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
708  /// before calling this function.
710  MachineBasicBlock *FBB,
712  const DebugLoc &DL,
713  int *BytesAdded = nullptr) const {
714  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
715  }
716 
718  MachineBasicBlock *DestBB,
719  const DebugLoc &DL,
720  int *BytesAdded = nullptr) const {
721  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
722  BytesAdded);
723  }
724 
725  /// Object returned by analyzeLoopForPipelining. Allows software pipelining
726  /// implementations to query attributes of the loop being pipelined and to
727  /// apply target-specific updates to the loop once pipelining is complete.
729  public:
730  virtual ~PipelinerLoopInfo();
731  /// Return true if the given instruction should not be pipelined and should
732  /// be ignored. An example could be a loop comparison, or induction variable
733  /// update with no users being pipelined.
734  virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
735 
736  /// Create a condition to determine if the trip count of the loop is greater
737  /// than TC, where TC is always one more than for the previous prologue or
738  /// 0 if this is being called for the outermost prologue.
739  ///
740  /// If the trip count is statically known to be greater than TC, return
741  /// true. If the trip count is statically known to be not greater than TC,
742  /// return false. Otherwise return nullopt and fill out Cond with the test
743  /// condition.
744  ///
745  /// Note: This hook is guaranteed to be called from the innermost to the
746  /// outermost prologue of the loop being software pipelined.
747  virtual Optional<bool>
750 
751  /// Modify the loop such that the trip count is
752  /// OriginalTC + TripCountAdjust.
753  virtual void adjustTripCount(int TripCountAdjust) = 0;
754 
755  /// Called when the loop's preheader has been modified to NewPreheader.
756  virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
757 
758  /// Called when the loop is being removed. Any instructions in the preheader
759  /// should be removed.
760  ///
761  /// Once this function is called, no other functions on this object are
762  /// valid; the loop has been removed.
763  virtual void disposed() = 0;
764  };
765 
766  /// Analyze loop L, which must be a single-basic-block loop, and if the
767  /// conditions can be understood enough produce a PipelinerLoopInfo object.
768  virtual std::unique_ptr<PipelinerLoopInfo>
770  return nullptr;
771  }
772 
773  /// Analyze the loop code, return true if it cannot be understood. Upon
774  /// success, this function returns false and returns information about the
775  /// induction variable and compare instruction used at the end.
776  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
777  MachineInstr *&CmpInst) const {
778  return true;
779  }
780 
781  /// Generate code to reduce the loop iteration by one and check if the loop
782  /// is finished. Return the value/register of the new loop count. We need
783  /// this function when peeling off one or more iterations of a loop. This
784  /// function assumes the nth iteration is peeled first.
786  MachineBasicBlock &PreHeader,
787  MachineInstr *IndVar, MachineInstr &Cmp,
790  unsigned Iter, unsigned MaxIter) const {
791  llvm_unreachable("Target didn't implement ReduceLoopCount");
792  }
793 
794  /// Delete the instruction OldInst and everything after it, replacing it with
795  /// an unconditional branch to NewDest. This is used by the tail merging pass.
797  MachineBasicBlock *NewDest) const;
798 
799  /// Return true if it's legal to split the given basic
800  /// block at the specified instruction (i.e. instruction would be the start
801  /// of a new basic block).
804  return true;
805  }
806 
807  /// Return true if it's profitable to predicate
808  /// instructions with accumulated instruction latency of "NumCycles"
809  /// of the specified basic block, where the probability of the instructions
810  /// being executed is given by Probability, and Confidence is a measure
811  /// of our confidence that it will be properly predicted.
812  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
813  unsigned ExtraPredCycles,
814  BranchProbability Probability) const {
815  return false;
816  }
817 
818  /// Second variant of isProfitableToIfCvt. This one
819  /// checks for the case where two basic blocks from true and false path
820  /// of a if-then-else (diamond) are predicated on mutually exclusive
821  /// predicates, where the probability of the true path being taken is given
822  /// by Probability, and Confidence is a measure of our confidence that it
823  /// will be properly predicted.
824  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
825  unsigned ExtraTCycles,
826  MachineBasicBlock &FMBB, unsigned NumFCycles,
827  unsigned ExtraFCycles,
828  BranchProbability Probability) const {
829  return false;
830  }
831 
832  /// Return true if it's profitable for if-converter to duplicate instructions
833  /// of specified accumulated instruction latencies in the specified MBB to
834  /// enable if-conversion.
835  /// The probability of the instructions being executed is given by
836  /// Probability, and Confidence is a measure of our confidence that it
837  /// will be properly predicted.
839  unsigned NumCycles,
840  BranchProbability Probability) const {
841  return false;
842  }
843 
844  /// Return the increase in code size needed to predicate a contiguous run of
845  /// NumInsts instructions.
847  unsigned NumInsts) const {
848  return 0;
849  }
850 
851  /// Return an estimate for the code size reduction (in bytes) which will be
852  /// caused by removing the given branch instruction during if-conversion.
853  virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {
854  return getInstSizeInBytes(MI);
855  }
856 
857  /// Return true if it's profitable to unpredicate
858  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
859  /// exclusive predicates.
860  /// e.g.
861  /// subeq r0, r1, #1
862  /// addne r0, r1, #1
863  /// =>
864  /// sub r0, r1, #1
865  /// addne r0, r1, #1
866  ///
867  /// This may be profitable is conditional instructions are always executed.
869  MachineBasicBlock &FMBB) const {
870  return false;
871  }
872 
873  /// Return true if it is possible to insert a select
874  /// instruction that chooses between TrueReg and FalseReg based on the
875  /// condition code in Cond.
876  ///
877  /// When successful, also return the latency in cycles from TrueReg,
878  /// FalseReg, and Cond to the destination register. In most cases, a select
879  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
880  ///
881  /// Some x86 implementations have 2-cycle cmov instructions.
882  ///
883  /// @param MBB Block where select instruction would be inserted.
884  /// @param Cond Condition returned by analyzeBranch.
885  /// @param DstReg Virtual dest register that the result should write to.
886  /// @param TrueReg Virtual register to select when Cond is true.
887  /// @param FalseReg Virtual register to select when Cond is false.
888  /// @param CondCycles Latency from Cond+Branch to select output.
889  /// @param TrueCycles Latency from TrueReg to select output.
890  /// @param FalseCycles Latency from FalseReg to select output.
891  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
893  Register TrueReg, Register FalseReg,
894  int &CondCycles, int &TrueCycles,
895  int &FalseCycles) const {
896  return false;
897  }
898 
899  /// Insert a select instruction into MBB before I that will copy TrueReg to
900  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
901  ///
902  /// This function can only be called after canInsertSelect() returned true.
903  /// The condition in Cond comes from analyzeBranch, and it can be assumed
904  /// that the same flags or registers required by Cond are available at the
905  /// insertion point.
906  ///
907  /// @param MBB Block where select instruction should be inserted.
908  /// @param I Insertion point.
909  /// @param DL Source location for debugging.
910  /// @param DstReg Virtual register to be defined by select instruction.
911  /// @param Cond Condition as computed by analyzeBranch.
912  /// @param TrueReg Virtual register to copy when Cond is true.
913  /// @param FalseReg Virtual register to copy when Cons is false.
917  Register TrueReg, Register FalseReg) const {
918  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
919  }
920 
921  /// Analyze the given select instruction, returning true if
922  /// it cannot be understood. It is assumed that MI->isSelect() is true.
923  ///
924  /// When successful, return the controlling condition and the operands that
925  /// determine the true and false result values.
926  ///
927  /// Result = SELECT Cond, TrueOp, FalseOp
928  ///
929  /// Some targets can optimize select instructions, for example by predicating
930  /// the instruction defining one of the operands. Such targets should set
931  /// Optimizable.
932  ///
933  /// @param MI Select instruction to analyze.
934  /// @param Cond Condition controlling the select.
935  /// @param TrueOp Operand number of the value selected when Cond is true.
936  /// @param FalseOp Operand number of the value selected when Cond is false.
937  /// @param Optimizable Returned as true if MI is optimizable.
938  /// @returns False on success.
939  virtual bool analyzeSelect(const MachineInstr &MI,
941  unsigned &TrueOp, unsigned &FalseOp,
942  bool &Optimizable) const {
943  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
944  return true;
945  }
946 
947  /// Given a select instruction that was understood by
948  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
949  /// merging it with one of its operands. Returns NULL on failure.
950  ///
951  /// When successful, returns the new select instruction. The client is
952  /// responsible for deleting MI.
953  ///
954  /// If both sides of the select can be optimized, PreferFalse is used to pick
955  /// a side.
956  ///
957  /// @param MI Optimizable select instruction.
958  /// @param NewMIs Set that record all MIs in the basic block up to \p
959  /// MI. Has to be updated with any newly created MI or deleted ones.
960  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
961  /// @returns Optimized instruction or NULL.
964  bool PreferFalse = false) const {
965  // This function must be implemented if Optimizable is ever set.
966  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
967  }
968 
969  /// Emit instructions to copy a pair of physical registers.
970  ///
971  /// This function should support copies within any legal register class as
972  /// well as any cross-class copies created during instruction selection.
973  ///
974  /// The source and destination registers may overlap, which may require a
975  /// careful implementation when multiple copy instructions are required for
976  /// large registers. See for example the ARM target.
979  MCRegister DestReg, MCRegister SrcReg,
980  bool KillSrc) const {
981  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
982  }
983 
984  /// Allow targets to tell MachineVerifier whether a specific register
985  /// MachineOperand can be used as part of PC-relative addressing.
986  /// PC-relative addressing modes in many CISC architectures contain
987  /// (non-PC) registers as offsets or scaling values, which inherently
988  /// tags the corresponding MachineOperand with OPERAND_PCREL.
989  ///
990  /// @param MO The MachineOperand in question. MO.isReg() should always
991  /// be true.
992  /// @return Whether this operand is allowed to be used PC-relatively.
993  virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const {
994  return false;
995  }
996 
997 protected:
998  /// Target-dependent implementation for IsCopyInstr.
999  /// If the specific machine instruction is a instruction that moves/copies
1000  /// value from one register to another register return destination and source
1001  /// registers as machine operands.
1002  virtual Optional<DestSourcePair>
1004  return None;
1005  }
1006 
1007  /// Return true if the given terminator MI is not expected to spill. This
1008  /// sets the live interval as not spillable and adjusts phi node lowering to
1009  /// not introduce copies after the terminator. Use with care, these are
1010  /// currently used for hardware loop intrinsics in very controlled situations,
1011  /// created prior to registry allocation in loops that only have single phi
1012  /// users for the terminators value. They may run out of registers if not used
1013  /// carefully.
1014  virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const {
1015  return false;
1016  }
1017 
1018 public:
1019  /// If the specific machine instruction is a instruction that moves/copies
1020  /// value from one register to another register return destination and source
1021  /// registers as machine operands.
1022  /// For COPY-instruction the method naturally returns destination and source
1023  /// registers as machine operands, for all other instructions the method calls
1024  /// target-dependent implementation.
1026  if (MI.isCopy()) {
1027  return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1028  }
1029  return isCopyInstrImpl(MI);
1030  }
1031 
1032  /// If the specific machine instruction is an instruction that adds an
1033  /// immediate value and a physical register, and stores the result in
1034  /// the given physical register \c Reg, return a pair of the source
1035  /// register and the offset which has been added.
1037  Register Reg) const {
1038  return None;
1039  }
1040 
1041  /// Returns true if MI is an instruction that defines Reg to have a constant
1042  /// value and the value is recorded in ImmVal. The ImmVal is a result that
1043  /// should be interpreted as modulo size of Reg.
1045  const Register Reg,
1046  int64_t &ImmVal) const {
1047  return false;
1048  }
1049 
1050  /// Store the specified register of the given register class to the specified
1051  /// stack frame index. The store instruction is to be added to the given
1052  /// machine basic block before the specified machine instruction. If isKill
1053  /// is true, the register operand is the last use and must be marked kill.
1056  Register SrcReg, bool isKill, int FrameIndex,
1057  const TargetRegisterClass *RC,
1058  const TargetRegisterInfo *TRI) const {
1059  llvm_unreachable("Target didn't implement "
1060  "TargetInstrInfo::storeRegToStackSlot!");
1061  }
1062 
1063  /// Load the specified register of the given register class from the specified
1064  /// stack frame index. The load instruction is to be added to the given
1065  /// machine basic block before the specified machine instruction.
1068  Register DestReg, int FrameIndex,
1069  const TargetRegisterClass *RC,
1070  const TargetRegisterInfo *TRI) const {
1071  llvm_unreachable("Target didn't implement "
1072  "TargetInstrInfo::loadRegFromStackSlot!");
1073  }
1074 
1075  /// This function is called for all pseudo instructions
1076  /// that remain after register allocation. Many pseudo instructions are
1077  /// created to help register allocation. This is the place to convert them
1078  /// into real instructions. The target can edit MI in place, or it can insert
1079  /// new instructions and erase MI. The function should return true if
1080  /// anything was changed.
1081  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
1082 
1083  /// Check whether the target can fold a load that feeds a subreg operand
1084  /// (or a subreg operand that feeds a store).
1085  /// For example, X86 may want to return true if it can fold
1086  /// movl (%esp), %eax
1087  /// subb, %al, ...
1088  /// Into:
1089  /// subb (%esp), ...
1090  ///
1091  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
1092  /// reject subregs - but since this behavior used to be enforced in the
1093  /// target-independent code, moving this responsibility to the targets
1094  /// has the potential of causing nasty silent breakage in out-of-tree targets.
1095  virtual bool isSubregFoldable() const { return false; }
1096 
1097  /// For a patchpoint, stackmap, or statepoint intrinsic, return the range of
1098  /// operands which can't be folded into stack references. Operands outside
1099  /// of the range are most likely foldable but it is not guaranteed.
1100  /// These instructions are unique in that stack references for some operands
1101  /// have the same execution cost (e.g. none) as the unfolded register forms.
1102  /// The ranged return is guaranteed to include all operands which can't be
1103  /// folded at zero cost.
1104  virtual std::pair<unsigned, unsigned>
1106 
1107  /// Attempt to fold a load or store of the specified stack
1108  /// slot into the specified machine instruction for the specified operand(s).
1109  /// If this is possible, a new instruction is returned with the specified
1110  /// operand folded, otherwise NULL is returned.
1111  /// The new instruction is inserted before MI, and the client is responsible
1112  /// for removing the old instruction.
1113  /// If VRM is passed, the assigned physregs can be inspected by target to
1114  /// decide on using an opcode (note that those assignments can still change).
1116  int FI,
1117  LiveIntervals *LIS = nullptr,
1118  VirtRegMap *VRM = nullptr) const;
1119 
1120  /// Same as the previous version except it allows folding of any load and
1121  /// store from / to any address, not just from a specific stack slot.
1123  MachineInstr &LoadMI,
1124  LiveIntervals *LIS = nullptr) const;
1125 
1126  /// Return true when there is potentially a faster code sequence
1127  /// for an instruction chain ending in \p Root. All potential patterns are
1128  /// returned in the \p Pattern vector. Pattern should be sorted in priority
1129  /// order since the pattern evaluator stops checking as soon as it finds a
1130  /// faster sequence.
1131  /// \param Root - Instruction that could be combined with one of its operands
1132  /// \param Patterns - Vector of possible combination patterns
1133  virtual bool
1136  bool DoRegPressureReduce) const;
1137 
1138  /// Return true if target supports reassociation of instructions in machine
1139  /// combiner pass to reduce register pressure for a given BB.
1140  virtual bool
1142  RegisterClassInfo *RegClassInfo) const {
1143  return false;
1144  }
1145 
1146  /// Fix up the placeholder we may add in genAlternativeCodeSequence().
1147  virtual void
1149  SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
1150 
1151  /// Return true when a code sequence can improve throughput. It
1152  /// should be called only for instructions in loops.
1153  /// \param Pattern - combiner pattern
1155 
1156  /// Return true if the input \P Inst is part of a chain of dependent ops
1157  /// that are suitable for reassociation, otherwise return false.
1158  /// If the instruction's operands must be commuted to have a previous
1159  /// instruction of the same type define the first source operand, \P Commuted
1160  /// will be set to true.
1161  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1162 
1163  /// Return true when \P Inst is both associative and commutative.
1164  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
1165  return false;
1166  }
1167 
1168  /// Return true when \P Inst has reassociable operands in the same \P MBB.
1169  virtual bool hasReassociableOperands(const MachineInstr &Inst,
1170  const MachineBasicBlock *MBB) const;
1171 
1172  /// Return true when \P Inst has reassociable sibling.
1173  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
1174 
1175  /// When getMachineCombinerPatterns() finds patterns, this function generates
1176  /// the instructions that could replace the original code sequence. The client
1177  /// has to decide whether the actual replacement is beneficial or not.
1178  /// \param Root - Instruction that could be combined with one of its operands
1179  /// \param Pattern - Combination pattern for Root
1180  /// \param InsInstrs - Vector of new instructions that implement P
1181  /// \param DelInstrs - Old instructions, including Root, that could be
1182  /// replaced by InsInstr
1183  /// \param InstIdxForVirtReg - map of virtual register to instruction in
1184  /// InsInstr that defines it
1185  virtual void genAlternativeCodeSequence(
1189  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1190 
1191  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1192  /// reduce critical path length.
1193  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1197  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1198 
1199  /// The limit on resource length extension we accept in MachineCombiner Pass.
1200  virtual int getExtendResourceLenLimit() const { return 0; }
1201 
1202  /// This is an architecture-specific helper function of reassociateOps.
1203  /// Set special operand attributes for new instructions after reassociation.
1204  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1205  MachineInstr &NewMI1,
1206  MachineInstr &NewMI2) const {}
1207 
1208  /// Return true when a target supports MachineCombiner.
1209  virtual bool useMachineCombiner() const { return false; }
1210 
1211  /// Return true if the given SDNode can be copied during scheduling
1212  /// even if it has glue.
1213  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1214 
1215 protected:
1216  /// Target-dependent implementation for foldMemoryOperand.
1217  /// Target-independent code in foldMemoryOperand will
1218  /// take care of adding a MachineMemOperand to the newly created instruction.
1219  /// The instruction and any auxiliary instructions necessary will be inserted
1220  /// at InsertPt.
1221  virtual MachineInstr *
1223  ArrayRef<unsigned> Ops,
1225  LiveIntervals *LIS = nullptr,
1226  VirtRegMap *VRM = nullptr) const {
1227  return nullptr;
1228  }
1229 
1230  /// Target-dependent implementation for foldMemoryOperand.
1231  /// Target-independent code in foldMemoryOperand will
1232  /// take care of adding a MachineMemOperand to the newly created instruction.
1233  /// The instruction and any auxiliary instructions necessary will be inserted
1234  /// at InsertPt.
1237  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1238  LiveIntervals *LIS = nullptr) const {
1239  return nullptr;
1240  }
1241 
1242  /// Target-dependent implementation of getRegSequenceInputs.
1243  ///
1244  /// \returns true if it is possible to build the equivalent
1245  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1246  ///
1247  /// \pre MI.isRegSequenceLike().
1248  ///
1249  /// \see TargetInstrInfo::getRegSequenceInputs.
1251  const MachineInstr &MI, unsigned DefIdx,
1252  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1253  return false;
1254  }
1255 
1256  /// Target-dependent implementation of getExtractSubregInputs.
1257  ///
1258  /// \returns true if it is possible to build the equivalent
1259  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1260  ///
1261  /// \pre MI.isExtractSubregLike().
1262  ///
1263  /// \see TargetInstrInfo::getExtractSubregInputs.
1265  unsigned DefIdx,
1266  RegSubRegPairAndIdx &InputReg) const {
1267  return false;
1268  }
1269 
1270  /// Target-dependent implementation of getInsertSubregInputs.
1271  ///
1272  /// \returns true if it is possible to build the equivalent
1273  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1274  ///
1275  /// \pre MI.isInsertSubregLike().
1276  ///
1277  /// \see TargetInstrInfo::getInsertSubregInputs.
1278  virtual bool
1279  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1280  RegSubRegPair &BaseReg,
1281  RegSubRegPairAndIdx &InsertedReg) const {
1282  return false;
1283  }
1284 
1285 public:
1286  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1287  /// (e.g. stack) the target returns the corresponding address space.
1288  virtual unsigned
1290  return 0;
1291  }
1292 
1293  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1294  /// a store or a load and a store into two or more instruction. If this is
1295  /// possible, returns true as well as the new instructions by reference.
1296  virtual bool
1298  bool UnfoldLoad, bool UnfoldStore,
1299  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1300  return false;
1301  }
1302 
1304  SmallVectorImpl<SDNode *> &NewNodes) const {
1305  return false;
1306  }
1307 
1308  /// Returns the opcode of the would be new
1309  /// instruction after load / store are unfolded from an instruction of the
1310  /// specified opcode. It returns zero if the specified unfolding is not
1311  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1312  /// index of the operand which will hold the register holding the loaded
1313  /// value.
1314  virtual unsigned
1315  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1316  unsigned *LoadRegIndex = nullptr) const {
1317  return 0;
1318  }
1319 
1320  /// This is used by the pre-regalloc scheduler to determine if two loads are
1321  /// loading from the same base address. It should only return true if the base
1322  /// pointers are the same and the only differences between the two addresses
1323  /// are the offset. It also returns the offsets by reference.
1324  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1325  int64_t &Offset1,
1326  int64_t &Offset2) const {
1327  return false;
1328  }
1329 
1330  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1331  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1332  /// On some targets if two loads are loading from
1333  /// addresses in the same cache line, it's better if they are scheduled
1334  /// together. This function takes two integers that represent the load offsets
1335  /// from the common base address. It returns true if it decides it's desirable
1336  /// to schedule the two loads together. "NumLoads" is the number of loads that
1337  /// have already been scheduled after Load1.
1338  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1339  int64_t Offset1, int64_t Offset2,
1340  unsigned NumLoads) const {
1341  return false;
1342  }
1343 
1344  /// Get the base operand and byte offset of an instruction that reads/writes
1345  /// memory. This is a convenience function for callers that are only prepared
1346  /// to handle a single base operand.
1348  const MachineOperand *&BaseOp, int64_t &Offset,
1349  bool &OffsetIsScalable,
1350  const TargetRegisterInfo *TRI) const;
1351 
1352  /// Get zero or more base operands and the byte offset of an instruction that
1353  /// reads/writes memory. Note that there may be zero base operands if the
1354  /// instruction accesses a constant address.
1355  /// It returns false if MI does not read/write memory.
1356  /// It returns false if base operands and offset could not be determined.
1357  /// It is not guaranteed to always recognize base operands and offsets in all
1358  /// cases.
1361  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
1362  const TargetRegisterInfo *TRI) const {
1363  return false;
1364  }
1365 
1366  /// Return true if the instruction contains a base register and offset. If
1367  /// true, the function also sets the operand position in the instruction
1368  /// for the base register and offset.
1370  unsigned &BasePos,
1371  unsigned &OffsetPos) const {
1372  return false;
1373  }
1374 
1375  /// Target dependent implementation to get the values constituting the address
1376  /// MachineInstr that is accessing memory. These values are returned as a
1377  /// struct ExtAddrMode which contains all relevant information to make up the
1378  /// address.
1379  virtual Optional<ExtAddrMode>
1381  const TargetRegisterInfo *TRI) const {
1382  return None;
1383  }
1384 
1385  /// Returns true if MI's Def is NullValueReg, and the MI
1386  /// does not change the Zero value. i.e. cases such as rax = shr rax, X where
1387  /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this
1388  /// function can return true even if becomes zero. Specifically cases such as
1389  /// NullValueReg = shl NullValueReg, 63.
1391  const Register NullValueReg,
1392  const TargetRegisterInfo *TRI) const {
1393  return false;
1394  }
1395 
1396  /// If the instruction is an increment of a constant value, return the amount.
1397  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1398  return false;
1399  }
1400 
1401  /// Returns true if the two given memory operations should be scheduled
1402  /// adjacent. Note that you have to add:
1403  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1404  /// or
1405  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1406  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1407  ///
1408  /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.
1409  /// \p NumLoads is the number of loads that will be in the cluster if this
1410  /// hook returns true.
1411  /// \p NumBytes is the number of bytes that will be loaded from all the
1412  /// clustered loads if this hook returns true.
1415  unsigned NumLoads, unsigned NumBytes) const {
1416  llvm_unreachable("target did not implement shouldClusterMemOps()");
1417  }
1418 
1419  /// Reverses the branch condition of the specified condition list,
1420  /// returning false on success and true if it cannot be reversed.
1421  virtual bool
1423  return true;
1424  }
1425 
1426  /// Insert a noop into the instruction stream at the specified point.
1427  virtual void insertNoop(MachineBasicBlock &MBB,
1429 
1430  /// Insert noops into the instruction stream at the specified point.
1431  virtual void insertNoops(MachineBasicBlock &MBB,
1433  unsigned Quantity) const;
1434 
1435  /// Return the noop instruction to use for a noop.
1436  virtual MCInst getNop() const;
1437 
1438  /// Return true for post-incremented instructions.
1439  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1440 
1441  /// Returns true if the instruction is already predicated.
1442  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1443 
1444  // Returns a MIRPrinter comment for this machine operand.
1445  virtual std::string
1447  unsigned OpIdx, const TargetRegisterInfo *TRI) const;
1448 
1449  /// Returns true if the instruction is a
1450  /// terminator instruction that has not been predicated.
1451  bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1452 
1453  /// Returns true if MI is an unconditional tail call.
1454  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1455  return false;
1456  }
1457 
1458  /// Returns true if the tail call can be made conditional on BranchCond.
1460  const MachineInstr &TailCall) const {
1461  return false;
1462  }
1463 
1464  /// Replace the conditional branch in MBB with a conditional tail call.
1467  const MachineInstr &TailCall) const {
1468  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1469  }
1470 
1471  /// Convert the instruction into a predicated instruction.
1472  /// It returns true if the operation was successful.
1473  virtual bool PredicateInstruction(MachineInstr &MI,
1474  ArrayRef<MachineOperand> Pred) const;
1475 
1476  /// Returns true if the first specified predicate
1477  /// subsumes the second, e.g. GE subsumes GT.
1479  ArrayRef<MachineOperand> Pred2) const {
1480  return false;
1481  }
1482 
1483  /// If the specified instruction defines any predicate
1484  /// or condition code register(s) used for predication, returns true as well
1485  /// as the definition predicate(s) by reference.
1486  /// SkipDead should be set to false at any point that dead
1487  /// predicate instructions should be considered as being defined.
1488  /// A dead predicate instruction is one that is guaranteed to be removed
1489  /// after a call to PredicateInstruction.
1491  std::vector<MachineOperand> &Pred,
1492  bool SkipDead) const {
1493  return false;
1494  }
1495 
1496  /// Return true if the specified instruction can be predicated.
1497  /// By default, this returns true for every instruction with a
1498  /// PredicateOperand.
1499  virtual bool isPredicable(const MachineInstr &MI) const {
1500  return MI.getDesc().isPredicable();
1501  }
1502 
1503  /// Return true if it's safe to move a machine
1504  /// instruction that defines the specified register class.
1505  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1506  return true;
1507  }
1508 
1509  /// Test if the given instruction should be considered a scheduling boundary.
1510  /// This primarily includes labels and terminators.
1511  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1512  const MachineBasicBlock *MBB,
1513  const MachineFunction &MF) const;
1514 
1515  /// Measure the specified inline asm to determine an approximation of its
1516  /// length.
1517  virtual unsigned getInlineAsmLength(
1518  const char *Str, const MCAsmInfo &MAI,
1519  const TargetSubtargetInfo *STI = nullptr) const;
1520 
1521  /// Allocate and return a hazard recognizer to use for this target when
1522  /// scheduling the machine instructions before register allocation.
1523  virtual ScheduleHazardRecognizer *
1525  const ScheduleDAG *DAG) const;
1526 
1527  /// Allocate and return a hazard recognizer to use for this target when
1528  /// scheduling the machine instructions before register allocation.
1529  virtual ScheduleHazardRecognizer *
1531  const ScheduleDAGMI *DAG) const;
1532 
1533  /// Allocate and return a hazard recognizer to use for this target when
1534  /// scheduling the machine instructions after register allocation.
1535  virtual ScheduleHazardRecognizer *
1537  const ScheduleDAG *DAG) const;
1538 
1539  /// Allocate and return a hazard recognizer to use for by non-scheduling
1540  /// passes.
1541  virtual ScheduleHazardRecognizer *
1543  return nullptr;
1544  }
1545 
1546  /// Provide a global flag for disabling the PreRA hazard recognizer that
1547  /// targets may choose to honor.
1548  bool usePreRAHazardRecognizer() const;
1549 
1550  /// For a comparison instruction, return the source registers
1551  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1552  /// compares against in CmpValue. Return true if the comparison instruction
1553  /// can be analyzed.
1554  virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1555  Register &SrcReg2, int64_t &Mask,
1556  int64_t &Value) const {
1557  return false;
1558  }
1559 
1560  /// See if the comparison instruction can be converted
1561  /// into something more efficient. E.g., on ARM most instructions can set the
1562  /// flags register, obviating the need for a separate CMP.
1563  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1564  Register SrcReg2, int64_t Mask,
1565  int64_t Value,
1566  const MachineRegisterInfo *MRI) const {
1567  return false;
1568  }
1569  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1570 
1571  /// Try to remove the load by folding it to a register operand at the use.
1572  /// We fold the load instructions if and only if the
1573  /// def and use are in the same BB. We only look at one load and see
1574  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1575  /// defined by the load we are trying to fold. DefMI returns the machine
1576  /// instruction that defines FoldAsLoadDefReg, and the function returns
1577  /// the machine instruction generated due to folding.
1579  const MachineRegisterInfo *MRI,
1580  Register &FoldAsLoadDefReg,
1581  MachineInstr *&DefMI) const {
1582  return nullptr;
1583  }
1584 
1585  /// 'Reg' is known to be defined by a move immediate instruction,
1586  /// try to fold the immediate into the use instruction.
1587  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1588  /// then the caller may assume that DefMI has been erased from its parent
1589  /// block. The caller may assume that it will not be erased by this
1590  /// function otherwise.
1592  Register Reg, MachineRegisterInfo *MRI) const {
1593  return false;
1594  }
1595 
1596  /// Return the number of u-operations the given machine
1597  /// instruction will be decoded to on the target cpu. The itinerary's
1598  /// IssueWidth is the number of microops that can be dispatched each
1599  /// cycle. An instruction with zero microops takes no dispatch resources.
1600  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1601  const MachineInstr &MI) const;
1602 
1603  /// Return true for pseudo instructions that don't consume any
1604  /// machine resources in their current form. These are common cases that the
1605  /// scheduler should consider free, rather than conservatively handling them
1606  /// as instructions with no itinerary.
1607  bool isZeroCost(unsigned Opcode) const {
1608  return Opcode <= TargetOpcode::COPY;
1609  }
1610 
1611  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1612  SDNode *DefNode, unsigned DefIdx,
1613  SDNode *UseNode, unsigned UseIdx) const;
1614 
1615  /// Compute and return the use operand latency of a given pair of def and use.
1616  /// In most cases, the static scheduling itinerary was enough to determine the
1617  /// operand latency. But it may not be possible for instructions with variable
1618  /// number of defs / uses.
1619  ///
1620  /// This is a raw interface to the itinerary that may be directly overridden
1621  /// by a target. Use computeOperandLatency to get the best estimate of
1622  /// latency.
1623  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1624  const MachineInstr &DefMI, unsigned DefIdx,
1625  const MachineInstr &UseMI,
1626  unsigned UseIdx) const;
1627 
1628  /// Compute the instruction latency of a given instruction.
1629  /// If the instruction has higher cost when predicated, it's returned via
1630  /// PredCost.
1631  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1632  const MachineInstr &MI,
1633  unsigned *PredCost = nullptr) const;
1634 
1635  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1636 
1637  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1638  SDNode *Node) const;
1639 
1640  /// Return the default expected latency for a def based on its opcode.
1641  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1642  const MachineInstr &DefMI) const;
1643 
1644  /// Return true if this opcode has high latency to its result.
1645  virtual bool isHighLatencyDef(int opc) const { return false; }
1646 
1647  /// Compute operand latency between a def of 'Reg'
1648  /// and a use in the current loop. Return true if the target considered
1649  /// it 'high'. This is used by optimization passes such as machine LICM to
1650  /// determine whether it makes sense to hoist an instruction out even in a
1651  /// high register pressure situation.
1652  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1653  const MachineRegisterInfo *MRI,
1654  const MachineInstr &DefMI, unsigned DefIdx,
1655  const MachineInstr &UseMI,
1656  unsigned UseIdx) const {
1657  return false;
1658  }
1659 
1660  /// Compute operand latency of a def of 'Reg'. Return true
1661  /// if the target considered it 'low'.
1662  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1663  const MachineInstr &DefMI,
1664  unsigned DefIdx) const;
1665 
1666  /// Perform target-specific instruction verification.
1667  virtual bool verifyInstruction(const MachineInstr &MI,
1668  StringRef &ErrInfo) const {
1669  return true;
1670  }
1671 
1672  /// Return the current execution domain and bit mask of
1673  /// possible domains for instruction.
1674  ///
1675  /// Some micro-architectures have multiple execution domains, and multiple
1676  /// opcodes that perform the same operation in different domains. For
1677  /// example, the x86 architecture provides the por, orps, and orpd
1678  /// instructions that all do the same thing. There is a latency penalty if a
1679  /// register is written in one domain and read in another.
1680  ///
1681  /// This function returns a pair (domain, mask) containing the execution
1682  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1683  /// function can be used to change the opcode to one of the domains in the
1684  /// bit mask. Instructions whose execution domain can't be changed should
1685  /// return a 0 mask.
1686  ///
1687  /// The execution domain numbers don't have any special meaning except domain
1688  /// 0 is used for instructions that are not associated with any interesting
1689  /// execution domain.
1690  ///
1691  virtual std::pair<uint16_t, uint16_t>
1693  return std::make_pair(0, 0);
1694  }
1695 
1696  /// Change the opcode of MI to execute in Domain.
1697  ///
1698  /// The bit (1 << Domain) must be set in the mask returned from
1699  /// getExecutionDomain(MI).
1700  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1701 
1702  /// Returns the preferred minimum clearance
1703  /// before an instruction with an unwanted partial register update.
1704  ///
1705  /// Some instructions only write part of a register, and implicitly need to
1706  /// read the other parts of the register. This may cause unwanted stalls
1707  /// preventing otherwise unrelated instructions from executing in parallel in
1708  /// an out-of-order CPU.
1709  ///
1710  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1711  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1712  /// the instruction needs to wait for the old value of the register to become
1713  /// available:
1714  ///
1715  /// addps %xmm1, %xmm0
1716  /// movaps %xmm0, (%rax)
1717  /// cvtsi2ss %rbx, %xmm0
1718  ///
1719  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1720  /// instruction before it can issue, even though the high bits of %xmm0
1721  /// probably aren't needed.
1722  ///
1723  /// This hook returns the preferred clearance before MI, measured in
1724  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1725  /// instructions before MI. It should only return a positive value for
1726  /// unwanted dependencies. If the old bits of the defined register have
1727  /// useful values, or if MI is determined to otherwise read the dependency,
1728  /// the hook should return 0.
1729  ///
1730  /// The unwanted dependency may be handled by:
1731  ///
1732  /// 1. Allocating the same register for an MI def and use. That makes the
1733  /// unwanted dependency identical to a required dependency.
1734  ///
1735  /// 2. Allocating a register for the def that has no defs in the previous N
1736  /// instructions.
1737  ///
1738  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1739  /// allows the target to insert a dependency breaking instruction.
1740  ///
1741  virtual unsigned
1743  const TargetRegisterInfo *TRI) const {
1744  // The default implementation returns 0 for no partial register dependency.
1745  return 0;
1746  }
1747 
1748  /// Return the minimum clearance before an instruction that reads an
1749  /// unused register.
1750  ///
1751  /// For example, AVX instructions may copy part of a register operand into
1752  /// the unused high bits of the destination register.
1753  ///
1754  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1755  ///
1756  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1757  /// false dependence on any previous write to %xmm0.
1758  ///
1759  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1760  /// does not take an operand index. Instead sets \p OpNum to the index of the
1761  /// unused register.
1762  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
1763  const TargetRegisterInfo *TRI) const {
1764  // The default implementation returns 0 for no undef register dependency.
1765  return 0;
1766  }
1767 
1768  /// Insert a dependency-breaking instruction
1769  /// before MI to eliminate an unwanted dependency on OpNum.
1770  ///
1771  /// If it wasn't possible to avoid a def in the last N instructions before MI
1772  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1773  /// unwanted dependency.
1774  ///
1775  /// On x86, an xorps instruction can be used as a dependency breaker:
1776  ///
1777  /// addps %xmm1, %xmm0
1778  /// movaps %xmm0, (%rax)
1779  /// xorps %xmm0, %xmm0
1780  /// cvtsi2ss %rbx, %xmm0
1781  ///
1782  /// An <imp-kill> operand should be added to MI if an instruction was
1783  /// inserted. This ties the instructions together in the post-ra scheduler.
1784  ///
1785  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1786  const TargetRegisterInfo *TRI) const {}
1787 
1788  /// Create machine specific model for scheduling.
1789  virtual DFAPacketizer *
1791  return nullptr;
1792  }
1793 
1794  /// Sometimes, it is possible for the target
1795  /// to tell, even without aliasing information, that two MIs access different
1796  /// memory addresses. This function returns true if two MIs access different
1797  /// memory addresses and false otherwise.
1798  ///
1799  /// Assumes any physical registers used to compute addresses have the same
1800  /// value for both instructions. (This is the most useful assumption for
1801  /// post-RA scheduling.)
1802  ///
1803  /// See also MachineInstr::mayAlias, which is implemented on top of this
1804  /// function.
1805  virtual bool
1807  const MachineInstr &MIb) const {
1808  assert(MIa.mayLoadOrStore() &&
1809  "MIa must load from or modify a memory location");
1810  assert(MIb.mayLoadOrStore() &&
1811  "MIb must load from or modify a memory location");
1812  return false;
1813  }
1814 
1815  /// Return the value to use for the MachineCSE's LookAheadLimit,
1816  /// which is a heuristic used for CSE'ing phys reg defs.
1817  virtual unsigned getMachineCSELookAheadLimit() const {
1818  // The default lookahead is small to prevent unprofitable quadratic
1819  // behavior.
1820  return 5;
1821  }
1822 
1823  /// Return the maximal number of alias checks on memory operands. For
1824  /// instructions with more than one memory operands, the alias check on a
1825  /// single MachineInstr pair has quadratic overhead and results in
1826  /// unacceptable performance in the worst case. The limit here is to clamp
1827  /// that maximal checks performed. Usually, that's the product of memory
1828  /// operand numbers from that pair of MachineInstr to be checked. For
1829  /// instance, with two MachineInstrs with 4 and 5 memory operands
1830  /// correspondingly, a total of 20 checks are required. With this limit set to
1831  /// 16, their alias check is skipped. We choose to limit the product instead
1832  /// of the individual instruction as targets may have special MachineInstrs
1833  /// with a considerably high number of memory operands, such as `ldm` in ARM.
1834  /// Setting this limit per MachineInstr would result in either too high
1835  /// overhead or too rigid restriction.
1836  virtual unsigned getMemOperandAACheckLimit() const { return 16; }
1837 
1838  /// Return an array that contains the ids of the target indices (used for the
1839  /// TargetIndex machine operand) and their names.
1840  ///
1841  /// MIR Serialization is able to serialize only the target indices that are
1842  /// defined by this method.
1845  return None;
1846  }
1847 
1848  /// Decompose the machine operand's target flags into two values - the direct
1849  /// target flag value and any of bit flags that are applied.
1850  virtual std::pair<unsigned, unsigned>
1851  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1852  return std::make_pair(0u, 0u);
1853  }
1854 
1855  /// Return an array that contains the direct target flag values and their
1856  /// names.
1857  ///
1858  /// MIR Serialization is able to serialize only the target flags that are
1859  /// defined by this method.
1862  return None;
1863  }
1864 
1865  /// Return an array that contains the bitmask target flag values and their
1866  /// names.
1867  ///
1868  /// MIR Serialization is able to serialize only the target flags that are
1869  /// defined by this method.
1872  return None;
1873  }
1874 
1875  /// Return an array that contains the MMO target flag values and their
1876  /// names.
1877  ///
1878  /// MIR Serialization is able to serialize only the MMO target flags that are
1879  /// defined by this method.
1882  return None;
1883  }
1884 
1885  /// Determines whether \p Inst is a tail call instruction. Override this
1886  /// method on targets that do not properly set MCID::Return and MCID::Call on
1887  /// tail call instructions."
1888  virtual bool isTailCall(const MachineInstr &Inst) const {
1889  return Inst.isReturn() && Inst.isCall();
1890  }
1891 
1892  /// True if the instruction is bound to the top of its basic block and no
1893  /// other instructions shall be inserted before it. This can be implemented
1894  /// to prevent register allocator to insert spills before such instructions.
1895  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1896  return false;
1897  }
1898 
1899  /// During PHI eleimination lets target to make necessary checks and
1900  /// insert the copy to the PHI destination register in a target specific
1901  /// manner.
1904  const DebugLoc &DL, Register Src, Register Dst) const {
1905  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1906  .addReg(Src);
1907  }
1908 
1909  /// During PHI eleimination lets target to make necessary checks and
1910  /// insert the copy to the PHI destination register in a target specific
1911  /// manner.
1914  const DebugLoc &DL, Register Src,
1915  unsigned SrcSubReg,
1916  Register Dst) const {
1917  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1918  .addReg(Src, 0, SrcSubReg);
1919  }
1920 
1921  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1922  /// information for a set of outlining candidates.
1924  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1926  "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1927  }
1928 
1929  /// Optional target hook to create the LLVM IR attributes for the outlined
1930  /// function. If overridden, the overriding function must call the default
1931  /// implementation.
1932  virtual void mergeOutliningCandidateAttributes(
1933  Function &F, std::vector<outliner::Candidate> &Candidates) const;
1934 
1935  /// Returns how or if \p MI should be outlined.
1936  virtual outliner::InstrType
1937  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1939  "Target didn't implement TargetInstrInfo::getOutliningType!");
1940  }
1941 
1942  /// Optional target hook that returns true if \p MBB is safe to outline from,
1943  /// and returns any target-specific information in \p Flags.
1945  unsigned &Flags) const;
1946 
1947  /// Insert a custom frame for outlined functions.
1949  const outliner::OutlinedFunction &OF) const {
1951  "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1952  }
1953 
1954  /// Insert a call to an outlined function into the program.
1955  /// Returns an iterator to the spot where we inserted the call. This must be
1956  /// implemented by the target.
1960  outliner::Candidate &C) const {
1962  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1963  }
1964 
1965  /// Return true if the function can safely be outlined from.
1966  /// A function \p MF is considered safe for outlining if an outlined function
1967  /// produced from instructions in F will produce a program which produces the
1968  /// same output for any set of given inputs.
1970  bool OutlineFromLinkOnceODRs) const {
1971  llvm_unreachable("Target didn't implement "
1972  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1973  }
1974 
1975  /// Return true if the function should be outlined from by default.
1977  return false;
1978  }
1979 
1980  /// Produce the expression describing the \p MI loading a value into
1981  /// the physical register \p Reg. This hook should only be used with
1982  /// \p MIs belonging to VReg-less functions.
1984  Register Reg) const;
1985 
1986  /// Given the generic extension instruction \p ExtMI, returns true if this
1987  /// extension is a likely candidate for being folded into an another
1988  /// instruction.
1990  MachineRegisterInfo &MRI) const {
1991  return false;
1992  }
1993 
1994  /// Return MIR formatter to format/parse MIR operands. Target can override
1995  /// this virtual function and return target specific MIR formatter.
1996  virtual const MIRFormatter *getMIRFormatter() const {
1997  if (!Formatter.get())
1998  Formatter = std::make_unique<MIRFormatter>();
1999  return Formatter.get();
2000  }
2001 
2002  /// Returns the target-specific default value for tail duplication.
2003  /// This value will be used if the tail-dup-placement-threshold argument is
2004  /// not provided.
2005  virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const {
2006  return OptLevel >= CodeGenOpt::Aggressive ? 4 : 2;
2007  }
2008 
2009  /// Returns the callee operand from the given \p MI.
2010  virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const {
2011  return MI.getOperand(0);
2012  }
2013 
2014 private:
2015  mutable std::unique_ptr<MIRFormatter> Formatter;
2016  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
2017  unsigned CatchRetOpcode;
2018  unsigned ReturnOpcode;
2019 };
2020 
2021 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
2024 
2026  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
2027  RegInfo::getEmptyKey());
2028  }
2029 
2031  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
2032  RegInfo::getTombstoneKey());
2033  }
2034 
2035  /// Reuse getHashValue implementation from
2036  /// std::pair<unsigned, unsigned>.
2037  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
2038  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2039  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
2040  }
2041 
2044  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
2045  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
2046  }
2047 };
2048 
2049 } // end namespace llvm
2050 
2051 #endif // LLVM_CODEGEN_TARGETINSTRINFO_H
llvm::TargetInstrInfo::getConstValDefinedInReg
virtual bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const
Returns true if MI is an instruction that defines Reg to have a constant value and the value is recor...
Definition: TargetInstrInfo.h:1044
llvm::TargetInstrInfo::hasReassociableSibling
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
Definition: TargetInstrInfo.cpp:717
llvm::TargetInstrInfo::getMemOperandWithOffset
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.cpp:1070
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::TargetInstrInfo::isSafeToMoveRegClassDefs
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it's safe to move a machine instruction that defines the specified register class.
Definition: TargetInstrInfo.h:1505
llvm::TargetInstrInfo::insertIndirectBranch
virtual void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
Definition: TargetInstrInfo.h:603
llvm::TargetInstrInfo::analyzeCompare
virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition: TargetInstrInfo.h:1554
llvm::TargetInstrInfo::insertSelect
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true,...
Definition: TargetInstrInfo.h:914
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::TargetInstrInfo::isSubregFoldable
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: TargetInstrInfo.h:1095
llvm::TargetInstrInfo::duplicate
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
Definition: TargetInstrInfo.cpp:433
llvm::TargetInstrInfo::areLoadsFromSameBasePtr
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
Definition: TargetInstrInfo.h:1324
llvm::TargetInstrInfo::CreateTargetHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1050
llvm::DenseMapInfo< unsigned >
Definition: DenseMapInfo.h:123
llvm::TargetInstrInfo::replaceBranchWithTailCall
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
Definition: TargetInstrInfo.h:1465
llvm::TargetInstrInfo::getCatchReturnOpcode
unsigned getCatchReturnOpcode() const
Definition: TargetInstrInfo.h:238
llvm::TargetInstrInfo::unfoldMemoryOperand
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
Definition: TargetInstrInfo.h:1297
llvm::TargetInstrInfo::useMachineCombiner
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
Definition: TargetInstrInfo.h:1209
llvm::TargetInstrInfo::analyzeBranchPredicate
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
Definition: TargetInstrInfo.h:680
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::TargetInstrInfo::MachineBranchPredicate
Represents a predicate at the MachineFunction level.
Definition: TargetInstrInfo.h:651
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1036
llvm::RegImmPair::Imm
int64_t Imm
Definition: TargetInstrInfo.h:79
llvm::Function
Definition: Function.h:60
llvm::TargetInstrInfo::getReturnOpcode
unsigned getReturnOpcode() const
Definition: TargetInstrInfo.h:239
llvm::TargetInstrInfo::isThroughputPattern
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
Definition: TargetInstrInfo.cpp:799
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::TargetInstrInfo::canInsertSelect
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
Definition: TargetInstrInfo.h:891
llvm::TargetInstrInfo::getExtractSubregInputs
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1293
llvm::TargetInstrInfo::createPHIDestinationCopy
virtual MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition: TargetInstrInfo.h:1902
llvm::TargetInstrInfo::RegSubRegPairAndIdx
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
Definition: TargetInstrInfo.h:509
llvm::TargetInstrInfo::getMachineCombinerPatterns
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: TargetInstrInfo.cpp:775
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.
Definition: TargetInstrInfo.h:271
llvm::TargetInstrInfo::getUndefRegClearance
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register.
Definition: TargetInstrInfo.h:1762
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::TargetInstrInfo::isCopyInstrImpl
virtual Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const
Target-dependent implementation for IsCopyInstr.
Definition: TargetInstrInfo.h:1003
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::isEqual
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
Definition: TargetInstrInfo.h:2042
llvm::TargetInstrInfo::copyPhysReg
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
Definition: TargetInstrInfo.h:977
llvm::TargetInstrInfo::isGenericOpcode
static bool isGenericOpcode(unsigned Opc)
Definition: TargetInstrInfo.h:108
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:454
RegisterClassInfo.h
llvm::TargetInstrInfo::optimizeCondBranch
virtual bool optimizeCondBranch(MachineInstr &MI) const
Definition: TargetInstrInfo.h:1569
MachineBasicBlock.h
llvm::TargetInstrInfo::getAddressSpaceForPseudoSourceKind
virtual unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
Definition: TargetInstrInfo.h:1289
llvm::TargetInstrInfo::MachineBranchPredicate::RHS
MachineOperand RHS
Definition: TargetInstrInfo.h:660
llvm::TargetInstrInfo::getCalleeOperand
virtual const MachineOperand & getCalleeOperand(const MachineInstr &MI) const
Returns the callee operand from the given MI.
Definition: TargetInstrInfo.h:2010
llvm::TargetInstrInfo::isUnspillableTerminator
bool isUnspillableTerminator(const MachineInstr *MI) const
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTer...
Definition: TargetInstrInfo.h:360
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::TargetInstrInfo::insertNoops
virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
Insert noops into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:72
llvm::TargetInstrInfo::getIncrementValue
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
Definition: TargetInstrInfo.h:1397
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:33
llvm::TargetInstrInfo::ReplaceTailWithBranchTo
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
Definition: TargetInstrInfo.cpp:139
DenseMap.h
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::TargetInstrInfo::MachineBranchPredicate::FalseDest
MachineBasicBlock * FalseDest
Definition: TargetInstrInfo.h:662
llvm::TargetInstrInfo::getOutliningCandidateInfo
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Definition: TargetInstrInfo.h:1923
llvm::TargetInstrInfo::CreateTargetScheduleState
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
Definition: TargetInstrInfo.h:1790
llvm::Optional< bool >
llvm::DestSourcePair::Destination
const MachineOperand * Destination
Definition: TargetInstrInfo.h:69
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1025
llvm::TargetInstrInfo::getNop
virtual MCInst getNop() const
Return the noop instruction to use for a noop.
Definition: TargetInstrInfo.cpp:473
llvm::ExtAddrMode::ScaledReg
Register ScaledReg
Definition: TargetInstrInfo.h:88
llvm::TargetInstrInfo::isBranchOffsetInRange
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
Definition: TargetInstrInfo.h:589
llvm::TargetInstrInfo::hasHighOperandLatency
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of 'Reg' and a use in the current loop.
Definition: TargetInstrInfo.h:1652
llvm::TargetInstrInfo::isPredicable
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
Definition: TargetInstrInfo.h:1499
llvm::TargetInstrInfo::insertOutlinedCall
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const
Insert a call to an outlined function into the program.
Definition: TargetInstrInfo.h:1958
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:214
llvm::TargetInstrInfo::getInsertSubregInputs
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1318
llvm::TargetInstrInfo::hasCommutePreference
virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const
Returns true if the target has a preference on the operands order of the given machine instruction.
Definition: TargetInstrInfo.h:485
llvm::TargetInstrInfo::decomposeMachineOperandsTargetFlags
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: TargetInstrInfo.h:1851
llvm::TargetInstrInfo::RegSubRegPair::operator!=
bool operator!=(const RegSubRegPair &P) const
Definition: TargetInstrInfo.h:501
llvm::TargetInstrInfo::unfoldMemoryOperand
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
Definition: TargetInstrInfo.h:1303
llvm::TargetInstrInfo::shouldClusterMemOps
virtual bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const
Returns true if the two given memory operations should be scheduled adjacent.
Definition: TargetInstrInfo.h:1413
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1618
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1235
llvm::TargetInstrInfo::getPartialRegUpdateClearance
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Definition: TargetInstrInfo.h:1742
llvm::TargetInstrInfo::isHighLatencyDef
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Definition: TargetInstrInfo.h:1645
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:491
llvm::ExtAddrMode
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
Definition: TargetInstrInfo.h:86
llvm::RegImmPair::Reg
Register Reg
Definition: TargetInstrInfo.h:78
llvm::TargetInstrInfo::insertBranch
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
Definition: TargetInstrInfo.h:709
llvm::TargetInstrInfo::getMachineCSELookAheadLimit
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing ph...
Definition: TargetInstrInfo.h:1817
llvm::TargetInstrInfo::RegSubRegPair::operator==
bool operator==(const RegSubRegPair &P) const
Definition: TargetInstrInfo.h:498
llvm::TargetInstrInfo::isZeroCost
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don't consume any machine resources in their current form.
Definition: TargetInstrInfo.h:1607
llvm::TargetInstrInfo::getFrameSize
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
Definition: TargetInstrInfo.h:220
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetInstrInfo::PipelinerLoopInfo
Object returned by analyzeLoopForPipelining.
Definition: TargetInstrInfo.h:728
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:45
llvm::DenseMapInfo
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: APInt.h:34
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_NE
@ PRED_NE
Definition: TargetInstrInfo.h:654
llvm::TargetInstrInfo::usePreRAHazardRecognizer
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition: TargetInstrInfo.cpp:1044
llvm::TargetInstrInfo::getFrameTotalSize
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Definition: TargetInstrInfo.h:229
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:831
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetInstrInfo::removeBranch
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
Definition: TargetInstrInfo.h:691
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:165
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:220
llvm::TargetInstrInfo::loadRegFromStackSlot
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index.
Definition: TargetInstrInfo.h:1066
llvm::AAResults
Definition: AliasAnalysis.h:511
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:782
llvm::TargetInstrInfo::MachineBranchPredicate::ConditionDef
MachineInstr * ConditionDef
Definition: TargetInstrInfo.h:663
llvm::TargetInstrInfo::canCopyGluedNodeDuringSchedule
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
Definition: TargetInstrInfo.h:1213
llvm::TargetInstrInfo::verifyInstruction
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
Definition: TargetInstrInfo.h:1667
llvm::TargetInstrInfo::getInsertSubregLikeInputs
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
Definition: TargetInstrInfo.h:1279
llvm::TargetInstrInfo::PipelinerLoopInfo::adjustTripCount
virtual void adjustTripCount(int TripCountAdjust)=0
Modify the loop such that the trip count is OriginalTC + TripCountAdjust.
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetInstrInfo::optimizeLoadInstr
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
Definition: TargetInstrInfo.h:1578
llvm::TargetInstrInfo::setSpecialOperandAttr
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
Definition: TargetInstrInfo.h:1204
llvm::TargetInstrInfo::FoldImmediate
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
Definition: TargetInstrInfo.h:1591
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
llvm::TargetInstrInfo::buildOutlinedFrame
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
Definition: TargetInstrInfo.h:1948
llvm::TargetInstrInfo::getExtendResourceLenLimit
virtual int getExtendResourceLenLimit() const
The limit on resource length extension we accept in MachineCombiner Pass.
Definition: TargetInstrInfo.h:1200
MCInstrInfo.h
llvm::DFAPacketizer
Definition: DFAPacketizer.h:48
llvm::TargetInstrInfo::RegSubRegPairAndIdx::RegSubRegPairAndIdx
RegSubRegPairAndIdx(Register Reg=Register(), unsigned SubReg=0, unsigned SubIdx=0)
Definition: TargetInstrInfo.h:512
llvm::TargetInstrInfo::getRegSequenceLikeInputs
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
Definition: TargetInstrInfo.h:1250
llvm::TargetInstrInfo::isReassociationCandidate
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...
Definition: TargetInstrInfo.cpp:747
llvm::TargetInstrInfo::shouldOutlineFromFunctionByDefault
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
Definition: TargetInstrInfo.h:1976
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:710
llvm::TargetInstrInfo::expandPostRAPseudo
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
Definition: TargetInstrInfo.h:1081
llvm::TargetInstrInfo::insertNoop
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:65
llvm::TargetInstrInfo::getNumMicroOps
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
Definition: TargetInstrInfo.cpp:1119
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:197
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::TargetInstrInfo::isTailCall
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
Definition: TargetInstrInfo.h:1888
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_INVALID
@ PRED_INVALID
Definition: TargetInstrInfo.h:655
llvm::TargetInstrInfo::~TargetInstrInfo
virtual ~TargetInstrInfo()
llvm::TargetInstrInfo::analyzeSelect
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
Definition: TargetInstrInfo.h:939
llvm::TargetInstrInfo::isProfitableToDupForIfCvt
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
Definition: TargetInstrInfo.h:838
llvm::TargetInstrInfo::shouldScheduleLoadsNear
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
Definition: TargetInstrInfo.h:1338
llvm::TargetInstrInfo::mergeOutliningCandidateAttributes
virtual void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const
Optional target hook to create the LLVM IR attributes for the outlined function.
Definition: TargetInstrInfo.cpp:1404
MachineCombinerPattern.h
llvm::TargetInstrInfo::isStackSlotCopy
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
Definition: TargetInstrInfo.h:336
llvm::TargetInstrInfo::reverseBranchCondition
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition: TargetInstrInfo.h:1422
llvm::TargetInstrInfo::defaultDefLatency
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
Definition: TargetInstrInfo.cpp:1135
llvm::TargetInstrInfo::PipelinerLoopInfo::disposed
virtual void disposed()=0
Called when the loop is being removed.
llvm::TargetInstrInfo::isMBBSafeToOutlineFrom
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
Definition: TargetInstrInfo.cpp:1422
llvm::TargetInstrInfo::shouldSink
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
Definition: TargetInstrInfo.h:383
llvm::None
const NoneType None
Definition: None.h:24
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::TargetInstrInfo::optimizeSelect
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true,...
Definition: TargetInstrInfo.h:962
BranchProbability.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::TargetInstrInfo::isExtendLikelyToBeFolded
virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const
Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate f...
Definition: TargetInstrInfo.h:1989
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_EQ
@ PRED_EQ
Definition: TargetInstrInfo.h:653
llvm::TargetInstrInfo::hasReassociableOperands
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
Definition: TargetInstrInfo.cpp:698
llvm::TargetInstrInfo::isCoalescableExtInstr
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition: TargetInstrInfo.h:252
llvm::TargetInstrInfo::getBranchDestBlock
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
Definition: TargetInstrInfo.h:595
llvm::TargetInstrInfo::analyzeLoopForPipelining
virtual std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: TargetInstrInfo.h:769
llvm::TargetInstrInfo::MachineBranchPredicate::SingleUseCondition
bool SingleUseCondition
SingleUseCondition is true if ConditionDef is dead except for the branch(es) at the end of the basic ...
Definition: TargetInstrInfo.h:668
llvm::TargetInstrInfo::RegSubRegPair::RegSubRegPair
RegSubRegPair(Register Reg=Register(), unsigned SubReg=0)
Definition: TargetInstrInfo.h:495
llvm::TargetInstrInfo::convertToThreeAddress
virtual MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
Definition: TargetInstrInfo.h:428
llvm::TargetInstrInfo::getBaseAndOffsetPosition
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
Definition: TargetInstrInfo.h:1369
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:709
llvm::TargetInstrInfo::createMIROperandComment
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
Definition: TargetInstrInfo.cpp:1347
llvm::TargetInstrInfo::isStoreToStackSlot
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.
Definition: TargetInstrInfo.h:309
llvm::TargetInstrInfo::isStoreToStackSlot
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: TargetInstrInfo.h:300
llvm::TargetInstrInfo::getOutliningType
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
Definition: TargetInstrInfo.h:1937
llvm::TargetInstrInfo::isAssociativeAndCommutative
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when \P Inst is both associative and commutative.
Definition: TargetInstrInfo.h:1164
llvm::TargetInstrInfo::PredicateInstruction
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
Definition: TargetInstrInfo.cpp:329
llvm::TargetInstrInfo::canMakeTailCallConditional
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
Definition: TargetInstrInfo.h:1459
llvm::TargetInstrInfo::shouldHoist
virtual bool shouldHoist(const MachineInstr &MI, const MachineLoop *FromLoop) const
Return false if the instruction should not be hoisted by MachineLICM.
Definition: TargetInstrInfo.h:391
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getHashValue
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
Definition: TargetInstrInfo.h:2037
llvm::TargetInstrInfo::getStackSlotRange
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
Definition: TargetInstrInfo.cpp:387
llvm::TargetInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
Definition: TargetInstrInfo.h:1871
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::TargetInstrInfo::RegSubRegPair::Reg
Register Reg
Definition: TargetInstrInfo.h:492
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:30
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
VirtRegMap.h
llvm::ExtAddrMode::BaseReg
Register BaseReg
Definition: TargetInstrInfo.h:87
llvm::TargetInstrInfo::isPredicated
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Definition: TargetInstrInfo.h:1442
llvm::TargetInstrInfo::getAddrModeFromMemoryOp
virtual Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const
Target dependent implementation to get the values constituting the address MachineInstr that is acces...
Definition: TargetInstrInfo.h:1380
llvm::TargetInstrInfo::TargetInstrInfo
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
Definition: TargetInstrInfo.h:99
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:37
llvm::TargetInstrInfo::breakPartialRegDependency
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
Definition: TargetInstrInfo.h:1785
llvm::DenseMap< unsigned, unsigned >
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetInstrInfo::hasStoreToStackSlot
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
Definition: TargetInstrInfo.cpp:373
ArrayRef.h
llvm::TargetInstrInfo::isStoreToStackSlotPostFE
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition: TargetInstrInfo.h:318
llvm::ParamLoadedValue
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition: TargetInstrInfo.h:66
llvm::TargetInstrInfo::commuteInstruction
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:248
llvm::TargetInstrInfo::isAsCheapAsAMove
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Definition: TargetInstrInfo.h:374
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:100
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetInstrInfo::getInstSizeInBytes
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
Definition: TargetInstrInfo.h:366
llvm::TargetInstrInfo::insertUnconditionalBranch
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
Definition: TargetInstrInfo.h:717
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::TargetInstrInfo::describeLoadedValue
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
Definition: TargetInstrInfo.cpp:1174
llvm::TargetInstrInfo::MachineBranchPredicate::ComparePredicate
ComparePredicate
Definition: TargetInstrInfo.h:652
llvm::TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo
virtual ~PipelinerLoopInfo()
llvm::TargetInstrInfo::isLoadFromStackSlotPostFE
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition: TargetInstrInfo.h:280
MIRFormatter.h
llvm::TargetInstrInfo::getSerializableMachineMemOperandTargetFlags
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
Definition: TargetInstrInfo.h:1881
llvm::TargetInstrInfo::isPCRelRegisterOperandLegal
virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part ...
Definition: TargetInstrInfo.h:993
llvm::TargetInstrInfo::produceSameValue
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
Definition: TargetInstrInfo.cpp:427
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::TargetInstrInfo::createPHISourceCopy
virtual MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition: TargetInstrInfo.h:1912
llvm::RegImmPair
Used to describe a register and immediate addition.
Definition: TargetInstrInfo.h:77
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:821
llvm::TargetInstrInfo::getPatchpointUnfoldableRange
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...
Definition: TargetInstrInfo.cpp:476
llvm::TargetInstrInfo::MachineBranchPredicate::Predicate
ComparePredicate Predicate
Definition: TargetInstrInfo.h:658
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::TargetInstrInfo::isLegalToSplitMBBAt
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it's legal to split the given basic block at the specified instruction (i....
Definition: TargetInstrInfo.h:802
llvm::TargetInstrInfo::analyzeLoop
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understood.
Definition: TargetInstrInfo.h:776
llvm::TargetInstrInfo::getSPAdjust
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
Definition: TargetInstrInfo.cpp:997
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::TargetInstrInfo::getPredicationCost
virtual unsigned getPredicationCost(const MachineInstr &MI) const
Definition: TargetInstrInfo.cpp:1146
llvm::TargetInstrInfo::hasLoadFromStackSlot
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Definition: TargetInstrInfo.cpp:359
llvm::TargetInstrInfo::ClobbersPredicate
virtual bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
Definition: TargetInstrInfo.h:1490
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::TargetInstrInfo::RegSubRegPair::SubReg
unsigned SubReg
Definition: TargetInstrInfo.h:493
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:178
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::TargetInstrInfo::getTailDuplicateSize
virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const
Returns the target-specific default value for tail duplication.
Definition: TargetInstrInfo.h:2005
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:417
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::TargetInstrInfo::storeRegToStackSlot
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index.
Definition: TargetInstrInfo.h:1054
llvm::BranchProbability
Definition: BranchProbability.h:29
llvm::TargetInstrInfo::extraSizeToPredicateInstructions
virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const
Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.
Definition: TargetInstrInfo.h:846
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
Module
Machine Check Debug Module
Definition: MachineCheckDebugify.cpp:122
Node
Definition: ItaniumDemangle.h:155
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::TargetInstrInfo::isUnpredicatedTerminator
bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
Definition: TargetInstrInfo.cpp:318
llvm::MipsISD::TailCall
@ TailCall
Definition: MipsISelLowering.h:65
llvm::TargetInstrInfo::isFrameInstr
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
Definition: TargetInstrInfo.h:202
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getEmptyKey
static TargetInstrInfo::RegSubRegPair getEmptyKey()
Definition: TargetInstrInfo.h:2025
llvm::TargetInstrInfo::predictBranchSizeForIfCvt
virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const
Return an estimate for the code size reduction (in bytes) which will be caused by removing the given ...
Definition: TargetInstrInfo.h:853
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetInstrInfo::fixCommutedOpIndices
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...
Definition: TargetInstrInfo.cpp:263
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetInstrInfo::isTriviallyReMaterializable
bool isTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
Definition: TargetInstrInfo.h:124
llvm::TargetInstrInfo::isProfitableToUnpredicate
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
Definition: TargetInstrInfo.h:868
llvm::TargetInstrInfo::isSchedulingBoundary
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
Definition: TargetInstrInfo.cpp:1021
llvm::TargetInstrInfo::isFunctionSafeToOutlineFrom
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
Definition: TargetInstrInfo.h:1969
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::TargetInstrInfo::reduceLoopCount
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
Definition: TargetInstrInfo.h:785
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
llvm::TargetInstrInfo::getCallFrameDestroyOpcode
unsigned getCallFrameDestroyOpcode() const
Definition: TargetInstrInfo.h:199
llvm::TargetInstrInfo::getExecutionDomain
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
Definition: TargetInstrInfo.h:1692
llvm::TargetInstrInfo::isIgnorableUse
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
Definition: TargetInstrInfo.h:134
llvm::TargetInstrInfo::isUnconditionalTailCall
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
Definition: TargetInstrInfo.h:1454
llvm::TargetInstrInfo::isProfitableToIfCvt
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
Definition: TargetInstrInfo.h:812
llvm::TargetInstrInfo::isPostIncrement
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
Definition: TargetInstrInfo.h:1439
llvm::DestSourcePair
Definition: TargetInstrInfo.h:68
llvm::TargetInstrInfo::preservesZeroValueInReg
virtual bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const
Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value.
Definition: TargetInstrInfo.h:1390
llvm::TargetInstrInfo::operator=
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:338
llvm::TargetInstrInfo::getMemOperandsWithOffsetWidth
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.h:1359
llvm::TargetInstrInfo::analyzeBranch
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: TargetInstrInfo.h:638
llvm::TargetInstrInfo::reassociateOps
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
Definition: TargetInstrInfo.cpp:805
llvm::TargetInstrInfo::getRegSequenceInputs
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1266
llvm::TargetInstrInfo::PipelinerLoopInfo::createTripCountGreaterCondition
virtual Optional< bool > createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond)=0
Create a condition to determine if the trip count of the loop is greater than TC, where TC is always ...
llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1057
llvm::ExtAddrMode::Displacement
int64_t Displacement
Definition: TargetInstrInfo.h:90
llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const
Sometimes, it is possible for the target to tell, even without aliasing information,...
Definition: TargetInstrInfo.h:1806
llvm::ExtAddrMode::Scale
int64_t Scale
Definition: TargetInstrInfo.h:89
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::TargetInstrInfo::getInstrLatency
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Definition: TargetInstrInfo.cpp:1150
llvm::LiveIntervals
Definition: LiveIntervals.h:54
isEqual
static bool isEqual(const Function &Caller, const Function &Callee)
Definition: Attributes.cpp:1834
llvm::TargetInstrInfo::isBasicBlockPrologue
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
Definition: TargetInstrInfo.h:1895
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:429
llvm::TargetInstrInfo::optimizeCompareInstr
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient.
Definition: TargetInstrInfo.h:1563
llvm::TargetInstrInfo::hasLowDefLatency
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
Definition: TargetInstrInfo.cpp:1161
llvm::TargetInstrInfo::MachineBranchPredicate::LHS
MachineOperand LHS
Definition: TargetInstrInfo.h:659
llvm::TargetInstrInfo::getCallFrameSetupOpcode
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Definition: TargetInstrInfo.h:198
llvm::TargetInstrInfo::isUnspillableTerminatorImpl
virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const
Return true if the given terminator MI is not expected to spill.
Definition: TargetInstrInfo.h:1014
llvm::TargetInstrInfo::getMIRFormatter
virtual const MIRFormatter * getMIRFormatter() const
Return MIR formatter to format/parse MIR operands.
Definition: TargetInstrInfo.h:1996
AA
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:28
llvm::TargetInstrInfo::shouldReduceRegisterPressure
virtual bool shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const
Return true if target supports reassociation of instructions in machine combiner pass to reduce regis...
Definition: TargetInstrInfo.h:1141
llvm::TargetInstrInfo::PipelinerLoopInfo::setPreheader
virtual void setPreheader(MachineBasicBlock *NewPreheader)=0
Called when the loop's preheader has been modified to NewPreheader.
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1222
llvm::DestSourcePair::Source
const MachineOperand * Source
Definition: TargetInstrInfo.h:70
llvm::TargetInstrInfo::getMemOperandAACheckLimit
virtual unsigned getMemOperandAACheckLimit() const
Return the maximal number of alias checks on memory operands.
Definition: TargetInstrInfo.h:1836
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:558
MachineInstrBuilder.h
llvm::TargetInstrInfo::findCommutedOpIndices
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: TargetInstrInfo.cpp:294
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::TargetInstrInfo::genAlternativeCodeSequence
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: TargetInstrInfo.cpp:891
llvm::TargetInstrInfo::getOperandLatency
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Definition: TargetInstrInfo.cpp:1088
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getTombstoneKey
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
Definition: TargetInstrInfo.h:2030
llvm::TargetInstrInfo::isFrameSetup
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
Definition: TargetInstrInfo.h:208
llvm::TargetInstrInfo::PipelinerLoopInfo::shouldIgnoreForPipelining
virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const =0
Return true if the given instruction should not be pipelined and should be ignored.
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
Definition: TargetInstrInfo.h:1542
llvm::RegImmPair::RegImmPair
RegImmPair(Register Reg, int64_t Imm)
Definition: TargetInstrInfo.h:81
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1064
llvm::TargetInstrInfo::setExecutionDomain
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
Definition: TargetInstrInfo.h:1700
MachineOperand.h
DenseMapInfo.h
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:344
llvm::TargetInstrInfo::MachineBranchPredicate::TrueDest
MachineBasicBlock * TrueDest
Definition: TargetInstrInfo.h:661
llvm::LiveVariables
Definition: LiveVariables.h:47
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::DestSourcePair::DestSourcePair
DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
Definition: TargetInstrInfo.h:72
llvm::TargetInstrInfo::getSerializableDirectMachineOperandTargetFlags
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
Definition: TargetInstrInfo.h:1861
llvm::TargetInstrInfo::getOpcodeAfterMemoryUnfold
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
Definition: TargetInstrInfo.h:1315
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::TargetInstrInfo::CommuteAnyOperandIndex
static const unsigned CommuteAnyOperandIndex
Definition: TargetInstrInfo.h:438
llvm::TargetInstrInfo::isReallyTriviallyReMaterializable
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
Definition: TargetInstrInfo.h:146
MachineFunction.h
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::TargetInstrInfo::isAddImmediate
virtual Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a physical reg...
Definition: TargetInstrInfo.h:1036
llvm::TargetInstrInfo::finalizeInsInstrs
virtual void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const
Fix up the placeholder we may add in genAlternativeCodeSequence().
Definition: TargetInstrInfo.h:1148
llvm::TargetInstrInfo::MachineBranchPredicate::MachineBranchPredicate
MachineBranchPredicate()=default
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetInstrInfo::SubsumesPredicate
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
Definition: TargetInstrInfo.h:1478
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::TargetInstrInfo::isProfitableToIfCvt
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
Definition: TargetInstrInfo.h:824
llvm::TargetInstrInfo::getExtractSubregLikeInputs
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Definition: TargetInstrInfo.h:1264
llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx
unsigned SubIdx
Definition: TargetInstrInfo.h:510
llvm::TargetInstrInfo::getInlineAsmLength
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
Definition: TargetInstrInfo.cpp:98
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
Definition: TargetInstrInfo.h:262
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24
llvm::TargetInstrInfo::getSerializableTargetIndices
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
Definition: TargetInstrInfo.h:1844
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
MachineOutliner.h