LLVM 20.0.0git
TargetInstrInfo.h
Go to the documentation of this file.
1//===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the target machine instruction set to the code generator.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_TARGETINSTRINFO_H
14#define LLVM_CODEGEN_TARGETINSTRINFO_H
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/Uniformity.h"
31#include "llvm/MC/MCInstrInfo.h"
34#include <array>
35#include <cassert>
36#include <cstddef>
37#include <cstdint>
38#include <utility>
39#include <vector>
40
41namespace llvm {
42
43class DFAPacketizer;
44class InstrItineraryData;
45class LiveIntervals;
46class LiveVariables;
47class MachineLoop;
48class MachineMemOperand;
49class MachineModuleInfo;
50class MachineRegisterInfo;
51class MCAsmInfo;
52class MCInst;
53struct MCSchedModel;
54class Module;
55class ScheduleDAG;
56class ScheduleDAGMI;
57class ScheduleHazardRecognizer;
58class SDNode;
59class SelectionDAG;
60class SMSchedule;
61class SwingSchedulerDAG;
62class RegScavenger;
63class TargetRegisterClass;
64class TargetRegisterInfo;
65class TargetSchedModel;
66class TargetSubtargetInfo;
67enum class MachineTraceStrategy;
68
69template <class T> class SmallVectorImpl;
70
71using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
72
76
78 : Destination(&Dest), Source(&Src) {}
79};
80
81/// Used to describe a register and immediate addition.
82struct RegImmPair {
84 int64_t Imm;
85
86 RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {}
87};
88
89/// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
90/// It holds the register values, the scale value and the displacement.
91/// It also holds a descriptor for the expression used to calculate the address
92/// from the operands.
94 enum class Formula {
95 Basic = 0, // BaseReg + ScaledReg * Scale + Displacement
96 SExtScaledReg = 1, // BaseReg + sext(ScaledReg) * Scale + Displacement
97 ZExtScaledReg = 2 // BaseReg + zext(ScaledReg) * Scale + Displacement
98 };
99
102 int64_t Scale = 0;
103 int64_t Displacement = 0;
105 ExtAddrMode() = default;
106};
107
108//---------------------------------------------------------------------------
109///
110/// TargetInstrInfo - Interface to description of machine instruction set
111///
113public:
114 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
115 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
116 : CallFrameSetupOpcode(CFSetupOpcode),
117 CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
118 ReturnOpcode(ReturnOpcode) {}
122
123 static bool isGenericOpcode(unsigned Opc) {
124 return Opc <= TargetOpcode::GENERIC_OP_END;
125 }
126
127 static bool isGenericAtomicRMWOpcode(unsigned Opc) {
128 return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START &&
129 Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END;
130 }
131
132 /// Given a machine instruction descriptor, returns the register
133 /// class constraint for OpNum, or NULL.
134 virtual
135 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
136 const TargetRegisterInfo *TRI,
137 const MachineFunction &MF) const;
138
139 /// Return true if the instruction is trivially rematerializable, meaning it
140 /// has no side effects and requires no operands that aren't always available.
141 /// This means the only allowed uses are constants and unallocatable physical
142 /// registers so that the instructions result is independent of the place
143 /// in the function.
145 return (MI.getOpcode() == TargetOpcode::IMPLICIT_DEF &&
146 MI.getNumOperands() == 1) ||
147 (MI.getDesc().isRematerializable() &&
149 }
150
151 /// Given \p MO is a PhysReg use return if it can be ignored for the purpose
152 /// of instruction rematerialization or sinking.
153 virtual bool isIgnorableUse(const MachineOperand &MO) const {
154 return false;
155 }
156
157 virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo,
158 MachineCycleInfo *CI) const {
159 return true;
160 }
161
162protected:
163 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
164 /// set, this hook lets the target specify whether the instruction is actually
165 /// trivially rematerializable, taking into consideration its operands. This
166 /// predicate must return false if the instruction has any side effects other
167 /// than producing a value, or if it requres any address registers that are
168 /// not always available.
169 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const;
170
171 /// This method commutes the operands of the given machine instruction MI.
172 /// The operands to be commuted are specified by their indices OpIdx1 and
173 /// OpIdx2.
174 ///
175 /// If a target has any instructions that are commutable but require
176 /// converting to different instructions or making non-trivial changes
177 /// to commute them, this method can be overloaded to do that.
178 /// The default implementation simply swaps the commutable operands.
179 ///
180 /// If NewMI is false, MI is modified in place and returned; otherwise, a
181 /// new machine instruction is created and returned.
182 ///
183 /// Do not call this method for a non-commutable instruction.
184 /// Even though the instruction is commutable, the method may still
185 /// fail to commute the operands, null pointer is returned in such cases.
187 unsigned OpIdx1,
188 unsigned OpIdx2) const;
189
190 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
191 /// operand indices to (ResultIdx1, ResultIdx2).
192 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
193 /// predefined to some indices or be undefined (designated by the special
194 /// value 'CommuteAnyOperandIndex').
195 /// The predefined result indices cannot be re-defined.
196 /// The function returns true iff after the result pair redefinition
197 /// the fixed result pair is equal to or equivalent to the source pair of
198 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
199 /// the pairs (x,y) and (y,x) are equivalent.
200 static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
201 unsigned CommutableOpIdx1,
202 unsigned CommutableOpIdx2);
203
204public:
205 /// These methods return the opcode of the frame setup/destroy instructions
206 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
207 /// order to abstract away the difference between operating with a frame
208 /// pointer and operating without, through the use of these two instructions.
209 /// A FrameSetup MI in MF implies MFI::AdjustsStack.
210 ///
211 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
212 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
213
214 /// Returns true if the argument is a frame pseudo instruction.
215 bool isFrameInstr(const MachineInstr &I) const {
216 return I.getOpcode() == getCallFrameSetupOpcode() ||
217 I.getOpcode() == getCallFrameDestroyOpcode();
218 }
219
220 /// Returns true if the argument is a frame setup pseudo instruction.
221 bool isFrameSetup(const MachineInstr &I) const {
222 return I.getOpcode() == getCallFrameSetupOpcode();
223 }
224
225 /// Returns size of the frame associated with the given frame instruction.
226 /// For frame setup instruction this is frame that is set up space set up
227 /// after the instruction. For frame destroy instruction this is the frame
228 /// freed by the caller.
229 /// Note, in some cases a call frame (or a part of it) may be prepared prior
230 /// to the frame setup instruction. It occurs in the calls that involve
231 /// inalloca arguments. This function reports only the size of the frame part
232 /// that is set up between the frame setup and destroy pseudo instructions.
233 int64_t getFrameSize(const MachineInstr &I) const {
234 assert(isFrameInstr(I) && "Not a frame instruction");
235 assert(I.getOperand(0).getImm() >= 0);
236 return I.getOperand(0).getImm();
237 }
238
239 /// Returns the total frame size, which is made up of the space set up inside
240 /// the pair of frame start-stop instructions and the space that is set up
241 /// prior to the pair.
242 int64_t getFrameTotalSize(const MachineInstr &I) const {
243 if (isFrameSetup(I)) {
244 assert(I.getOperand(1).getImm() >= 0 &&
245 "Frame size must not be negative");
246 return getFrameSize(I) + I.getOperand(1).getImm();
247 }
248 return getFrameSize(I);
249 }
250
251 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
252 unsigned getReturnOpcode() const { return ReturnOpcode; }
253
254 /// Returns the actual stack pointer adjustment made by an instruction
255 /// as part of a call sequence. By default, only call frame setup/destroy
256 /// instructions adjust the stack, but targets may want to override this
257 /// to enable more fine-grained adjustment, or adjust by a different value.
258 virtual int getSPAdjust(const MachineInstr &MI) const;
259
260 /// Return true if the instruction is a "coalescable" extension instruction.
261 /// That is, it's like a copy where it's legal for the source to overlap the
262 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
263 /// expected the pre-extension value is available as a subreg of the result
264 /// register. This also returns the sub-register index in SubIdx.
265 virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
266 Register &DstReg, unsigned &SubIdx) const {
267 return false;
268 }
269
270 /// If the specified machine instruction is a direct
271 /// load from a stack slot, return the virtual or physical register number of
272 /// the destination along with the FrameIndex of the loaded stack slot. If
273 /// not, return 0. This predicate must return 0 if the instruction has
274 /// any side effects other than loading from the stack slot.
276 int &FrameIndex) const {
277 return 0;
278 }
279
280 /// Optional extension of isLoadFromStackSlot that returns the number of
281 /// bytes loaded from the stack. This must be implemented if a backend
282 /// supports partial stack slot spills/loads to further disambiguate
283 /// what the load does.
285 int &FrameIndex,
286 unsigned &MemBytes) const {
287 MemBytes = 0;
288 return isLoadFromStackSlot(MI, FrameIndex);
289 }
290
291 /// Check for post-frame ptr elimination stack locations as well.
292 /// This uses a heuristic so it isn't reliable for correctness.
294 int &FrameIndex) const {
295 return 0;
296 }
297
298 /// If the specified machine instruction has a load from a stack slot,
299 /// return true along with the FrameIndices of the loaded stack slot and the
300 /// machine mem operands containing the reference.
301 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
302 /// any instructions that loads from the stack. This is just a hint, as some
303 /// cases may be missed.
304 virtual bool hasLoadFromStackSlot(
305 const MachineInstr &MI,
307
308 /// If the specified machine instruction is a direct
309 /// store to a stack slot, return the virtual or physical register number of
310 /// the source reg along with the FrameIndex of the loaded stack slot. If
311 /// not, return 0. This predicate must return 0 if the instruction has
312 /// any side effects other than storing to the stack slot.
314 int &FrameIndex) const {
315 return 0;
316 }
317
318 /// Optional extension of isStoreToStackSlot that returns the number of
319 /// bytes stored to the stack. This must be implemented if a backend
320 /// supports partial stack slot spills/loads to further disambiguate
321 /// what the store does.
323 int &FrameIndex,
324 unsigned &MemBytes) const {
325 MemBytes = 0;
326 return isStoreToStackSlot(MI, FrameIndex);
327 }
328
329 /// Check for post-frame ptr elimination stack locations as well.
330 /// This uses a heuristic, so it isn't reliable for correctness.
332 int &FrameIndex) const {
333 return 0;
334 }
335
336 /// If the specified machine instruction has a store to a stack slot,
337 /// return true along with the FrameIndices of the loaded stack slot and the
338 /// machine mem operands containing the reference.
339 /// If not, return false. Unlike isStoreToStackSlot,
340 /// this returns true for any instructions that stores to the
341 /// stack. This is just a hint, as some cases may be missed.
342 virtual bool hasStoreToStackSlot(
343 const MachineInstr &MI,
345
346 /// Return true if the specified machine instruction
347 /// is a copy of one stack slot to another and has no other effect.
348 /// Provide the identity of the two frame indices.
349 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
350 int &SrcFrameIndex) const {
351 return false;
352 }
353
354 /// Compute the size in bytes and offset within a stack slot of a spilled
355 /// register or subregister.
356 ///
357 /// \param [out] Size in bytes of the spilled value.
358 /// \param [out] Offset in bytes within the stack slot.
359 /// \returns true if both Size and Offset are successfully computed.
360 ///
361 /// Not all subregisters have computable spill slots. For example,
362 /// subregisters registers may not be byte-sized, and a pair of discontiguous
363 /// subregisters has no single offset.
364 ///
365 /// Targets with nontrivial bigendian implementations may need to override
366 /// this, particularly to support spilled vector registers.
367 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
368 unsigned &Size, unsigned &Offset,
369 const MachineFunction &MF) const;
370
371 /// Return true if the given instruction is terminator that is unspillable,
372 /// according to isUnspillableTerminatorImpl.
374 return MI->isTerminator() && isUnspillableTerminatorImpl(MI);
375 }
376
377 /// Returns the size in bytes of the specified MachineInstr, or ~0U
378 /// when this function is not implemented by a target.
379 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
380 return ~0U;
381 }
382
383 /// Return true if the instruction is as cheap as a move instruction.
384 ///
385 /// Targets for different archs need to override this, and different
386 /// micro-architectures can also be finely tuned inside.
387 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
388 return MI.isAsCheapAsAMove();
389 }
390
391 /// Return true if the instruction should be sunk by MachineSink.
392 ///
393 /// MachineSink determines on its own whether the instruction is safe to sink;
394 /// this gives the target a hook to override the default behavior with regards
395 /// to which instructions should be sunk.
396 virtual bool shouldSink(const MachineInstr &MI) const { return true; }
397
398 /// Return false if the instruction should not be hoisted by MachineLICM.
399 ///
400 /// MachineLICM determines on its own whether the instruction is safe to
401 /// hoist; this gives the target a hook to extend this assessment and prevent
402 /// an instruction being hoisted from a given loop for target specific
403 /// reasons.
404 virtual bool shouldHoist(const MachineInstr &MI,
405 const MachineLoop *FromLoop) const {
406 return true;
407 }
408
409 /// Re-issue the specified 'original' instruction at the
410 /// specific location targeting a new destination register.
411 /// The register in Orig->getOperand(0).getReg() will be substituted by
412 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
413 /// SubIdx.
414 virtual void reMaterialize(MachineBasicBlock &MBB,
416 unsigned SubIdx, const MachineInstr &Orig,
417 const TargetRegisterInfo &TRI) const;
418
419 /// Clones instruction or the whole instruction bundle \p Orig and
420 /// insert into \p MBB before \p InsertBefore. The target may update operands
421 /// that are required to be unique.
422 ///
423 /// \p Orig must not return true for MachineInstr::isNotDuplicable().
425 MachineBasicBlock::iterator InsertBefore,
426 const MachineInstr &Orig) const;
427
428 /// This method must be implemented by targets that
429 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
430 /// may be able to convert a two-address instruction into one or more true
431 /// three-address instructions on demand. This allows the X86 target (for
432 /// example) to convert ADD and SHL instructions into LEA instructions if they
433 /// would require register copies due to two-addressness.
434 ///
435 /// This method returns a null pointer if the transformation cannot be
436 /// performed, otherwise it returns the last new instruction.
437 ///
438 /// If \p LIS is not nullptr, the LiveIntervals info should be updated for
439 /// replacing \p MI with new instructions, even though this function does not
440 /// remove MI.
442 LiveVariables *LV,
443 LiveIntervals *LIS) const {
444 return nullptr;
445 }
446
447 // This constant can be used as an input value of operand index passed to
448 // the method findCommutedOpIndices() to tell the method that the
449 // corresponding operand index is not pre-defined and that the method
450 // can pick any commutable operand.
451 static const unsigned CommuteAnyOperandIndex = ~0U;
452
453 /// This method commutes the operands of the given machine instruction MI.
454 ///
455 /// The operands to be commuted are specified by their indices OpIdx1 and
456 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
457 /// 'CommuteAnyOperandIndex', which means that the method is free to choose
458 /// any arbitrarily chosen commutable operand. If both arguments are set to
459 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
460 /// operands; then commutes them if such operands could be found.
461 ///
462 /// If NewMI is false, MI is modified in place and returned; otherwise, a
463 /// new machine instruction is created and returned.
464 ///
465 /// Do not call this method for a non-commutable instruction or
466 /// for non-commuable operands.
467 /// Even though the instruction is commutable, the method may still
468 /// fail to commute the operands, null pointer is returned in such cases.
470 commuteInstruction(MachineInstr &MI, bool NewMI = false,
471 unsigned OpIdx1 = CommuteAnyOperandIndex,
472 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
473
474 /// Returns true iff the routine could find two commutable operands in the
475 /// given machine instruction.
476 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
477 /// If any of the INPUT values is set to the special value
478 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
479 /// operand, then returns its index in the corresponding argument.
480 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
481 /// looks for 2 commutable operands.
482 /// If INPUT values refer to some operands of MI, then the method simply
483 /// returns true if the corresponding operands are commutable and returns
484 /// false otherwise.
485 ///
486 /// For example, calling this method this way:
487 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
488 /// findCommutedOpIndices(MI, Op1, Op2);
489 /// can be interpreted as a query asking to find an operand that would be
490 /// commutable with the operand#1.
491 virtual bool findCommutedOpIndices(const MachineInstr &MI,
492 unsigned &SrcOpIdx1,
493 unsigned &SrcOpIdx2) const;
494
495 /// Returns true if the target has a preference on the operands order of
496 /// the given machine instruction. And specify if \p Commute is required to
497 /// get the desired operands order.
498 virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
499 return false;
500 }
501
502 /// A pair composed of a register and a sub-register index.
503 /// Used to give some type checking when modeling Reg:SubReg.
506 unsigned SubReg;
507
509 : Reg(Reg), SubReg(SubReg) {}
510
511 bool operator==(const RegSubRegPair& P) const {
512 return Reg == P.Reg && SubReg == P.SubReg;
513 }
514 bool operator!=(const RegSubRegPair& P) const {
515 return !(*this == P);
516 }
517 };
518
519 /// A pair composed of a pair of a register and a sub-register index,
520 /// and another sub-register index.
521 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
523 unsigned SubIdx;
524
526 unsigned SubIdx = 0)
528 };
529
530 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
531 /// and \p DefIdx.
532 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
533 /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
534 /// flag are not added to this list.
535 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
536 /// two elements:
537 /// - %1:sub1, sub0
538 /// - %2<:0>, sub1
539 ///
540 /// \returns true if it is possible to build such an input sequence
541 /// with the pair \p MI, \p DefIdx. False otherwise.
542 ///
543 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
544 ///
545 /// \note The generic implementation does not provide any support for
546 /// MI.isRegSequenceLike(). In other words, one has to override
547 /// getRegSequenceLikeInputs for target specific instructions.
548 bool
549 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
550 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
551
552 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
553 /// and \p DefIdx.
554 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
555 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
556 /// - %1:sub1, sub0
557 ///
558 /// \returns true if it is possible to build such an input sequence
559 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
560 /// False otherwise.
561 ///
562 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
563 ///
564 /// \note The generic implementation does not provide any support for
565 /// MI.isExtractSubregLike(). In other words, one has to override
566 /// getExtractSubregLikeInputs for target specific instructions.
567 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
568 RegSubRegPairAndIdx &InputReg) const;
569
570 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
571 /// and \p DefIdx.
572 /// \p [out] BaseReg and \p [out] InsertedReg contain
573 /// the equivalent inputs of INSERT_SUBREG.
574 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
575 /// - BaseReg: %0:sub0
576 /// - InsertedReg: %1:sub1, sub3
577 ///
578 /// \returns true if it is possible to build such an input sequence
579 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
580 /// False otherwise.
581 ///
582 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
583 ///
584 /// \note The generic implementation does not provide any support for
585 /// MI.isInsertSubregLike(). In other words, one has to override
586 /// getInsertSubregLikeInputs for target specific instructions.
587 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
588 RegSubRegPair &BaseReg,
589 RegSubRegPairAndIdx &InsertedReg) const;
590
591 /// Return true if two machine instructions would produce identical values.
592 /// By default, this is only true when the two instructions
593 /// are deemed identical except for defs. If this function is called when the
594 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
595 /// aggressive checks.
596 virtual bool produceSameValue(const MachineInstr &MI0,
597 const MachineInstr &MI1,
598 const MachineRegisterInfo *MRI = nullptr) const;
599
600 /// \returns true if a branch from an instruction with opcode \p BranchOpc
601 /// bytes is capable of jumping to a position \p BrOffset bytes away.
602 virtual bool isBranchOffsetInRange(unsigned BranchOpc,
603 int64_t BrOffset) const {
604 llvm_unreachable("target did not implement");
605 }
606
607 /// \returns The block that branch instruction \p MI jumps to.
609 llvm_unreachable("target did not implement");
610 }
611
612 /// Insert an unconditional indirect branch at the end of \p MBB to \p
613 /// NewDestBB. Optionally, insert the clobbered register restoring in \p
614 /// RestoreBB. \p BrOffset indicates the offset of \p NewDestBB relative to
615 /// the offset of the position to insert the new branch.
617 MachineBasicBlock &NewDestBB,
618 MachineBasicBlock &RestoreBB,
619 const DebugLoc &DL, int64_t BrOffset = 0,
620 RegScavenger *RS = nullptr) const {
621 llvm_unreachable("target did not implement");
622 }
623
624 /// Analyze the branching code at the end of MBB, returning
625 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
626 /// implemented for a target). Upon success, this returns false and returns
627 /// with the following information in various cases:
628 ///
629 /// 1. If this block ends with no branches (it just falls through to its succ)
630 /// just return false, leaving TBB/FBB null.
631 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
632 /// the destination block.
633 /// 3. If this block ends with a conditional branch and it falls through to a
634 /// successor block, it sets TBB to be the branch destination block and a
635 /// list of operands that evaluate the condition. These operands can be
636 /// passed to other TargetInstrInfo methods to create new branches.
637 /// 4. If this block ends with a conditional branch followed by an
638 /// unconditional branch, it returns the 'true' destination in TBB, the
639 /// 'false' destination in FBB, and a list of operands that evaluate the
640 /// condition. These operands can be passed to other TargetInstrInfo
641 /// methods to create new branches.
642 ///
643 /// Note that removeBranch and insertBranch must be implemented to support
644 /// cases where this method returns success.
645 ///
646 /// If AllowModify is true, then this routine is allowed to modify the basic
647 /// block (e.g. delete instructions after the unconditional branch).
648 ///
649 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
650 /// before calling this function.
652 MachineBasicBlock *&FBB,
654 bool AllowModify = false) const {
655 return true;
656 }
657
658 /// Represents a predicate at the MachineFunction level. The control flow a
659 /// MachineBranchPredicate represents is:
660 ///
661 /// Reg = LHS `Predicate` RHS == ConditionDef
662 /// if Reg then goto TrueDest else goto FalseDest
663 ///
666 PRED_EQ, // True if two values are equal
667 PRED_NE, // True if two values are not equal
668 PRED_INVALID // Sentinel value
669 };
670
677
678 /// SingleUseCondition is true if ConditionDef is dead except for the
679 /// branch(es) at the end of the basic block.
680 ///
681 bool SingleUseCondition = false;
682
683 explicit MachineBranchPredicate() = default;
684 };
685
686 /// Analyze the branching code at the end of MBB and parse it into the
687 /// MachineBranchPredicate structure if possible. Returns false on success
688 /// and true on failure.
689 ///
690 /// If AllowModify is true, then this routine is allowed to modify the basic
691 /// block (e.g. delete instructions after the unconditional branch).
692 ///
695 bool AllowModify = false) const {
696 return true;
697 }
698
699 /// Remove the branching code at the end of the specific MBB.
700 /// This is only invoked in cases where analyzeBranch returns success. It
701 /// returns the number of instructions that were removed.
702 /// If \p BytesRemoved is non-null, report the change in code size from the
703 /// removed instructions.
705 int *BytesRemoved = nullptr) const {
706 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
707 }
708
709 /// Insert branch code into the end of the specified MachineBasicBlock. The
710 /// operands to this method are the same as those returned by analyzeBranch.
711 /// This is only invoked in cases where analyzeBranch returns success. It
712 /// returns the number of instructions inserted. If \p BytesAdded is non-null,
713 /// report the change in code size from the added instructions.
714 ///
715 /// It is also invoked by tail merging to add unconditional branches in
716 /// cases where analyzeBranch doesn't apply because there was no original
717 /// branch to analyze. At least this much must be implemented, else tail
718 /// merging needs to be disabled.
719 ///
720 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
721 /// before calling this function.
725 const DebugLoc &DL,
726 int *BytesAdded = nullptr) const {
727 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
728 }
729
731 MachineBasicBlock *DestBB,
732 const DebugLoc &DL,
733 int *BytesAdded = nullptr) const {
734 return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
735 BytesAdded);
736 }
737
738 /// Object returned by analyzeLoopForPipelining. Allows software pipelining
739 /// implementations to query attributes of the loop being pipelined and to
740 /// apply target-specific updates to the loop once pipelining is complete.
742 public:
744 /// Return true if the given instruction should not be pipelined and should
745 /// be ignored. An example could be a loop comparison, or induction variable
746 /// update with no users being pipelined.
747 virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
748
749 /// Return true if the proposed schedule should used. Otherwise return
750 /// false to not pipeline the loop. This function should be used to ensure
751 /// that pipelined loops meet target-specific quality heuristics.
753 return true;
754 }
755
756 /// Create a condition to determine if the trip count of the loop is greater
757 /// than TC, where TC is always one more than for the previous prologue or
758 /// 0 if this is being called for the outermost prologue.
759 ///
760 /// If the trip count is statically known to be greater than TC, return
761 /// true. If the trip count is statically known to be not greater than TC,
762 /// return false. Otherwise return nullopt and fill out Cond with the test
763 /// condition.
764 ///
765 /// Note: This hook is guaranteed to be called from the innermost to the
766 /// outermost prologue of the loop being software pipelined.
767 virtual std::optional<bool>
770
771 /// Create a condition to determine if the remaining trip count for a phase
772 /// is greater than TC. Some instructions such as comparisons may be
773 /// inserted at the bottom of MBB. All instructions expanded for the
774 /// phase must be inserted in MBB before calling this function.
775 /// LastStage0Insts is the map from the original instructions scheduled at
776 /// stage#0 to the expanded instructions for the last iteration of the
777 /// kernel. LastStage0Insts is intended to obtain the instruction that
778 /// refers the latest loop counter value.
779 ///
780 /// MBB can also be a predecessor of the prologue block. Then
781 /// LastStage0Insts must be empty and the compared value is the initial
782 /// value of the trip count.
787 "Target didn't implement "
788 "PipelinerLoopInfo::createRemainingIterationsGreaterCondition!");
789 }
790
791 /// Modify the loop such that the trip count is
792 /// OriginalTC + TripCountAdjust.
793 virtual void adjustTripCount(int TripCountAdjust) = 0;
794
795 /// Called when the loop's preheader has been modified to NewPreheader.
796 virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
797
798 /// Called when the loop is being removed. Any instructions in the preheader
799 /// should be removed.
800 ///
801 /// Once this function is called, no other functions on this object are
802 /// valid; the loop has been removed.
803 virtual void disposed() = 0;
804
805 /// Return true if the target can expand pipelined schedule with modulo
806 /// variable expansion.
807 virtual bool isMVEExpanderSupported() { return false; }
808 };
809
810 /// Analyze loop L, which must be a single-basic-block loop, and if the
811 /// conditions can be understood enough produce a PipelinerLoopInfo object.
812 virtual std::unique_ptr<PipelinerLoopInfo>
814 return nullptr;
815 }
816
817 /// Analyze the loop code, return true if it cannot be understood. Upon
818 /// success, this function returns false and returns information about the
819 /// induction variable and compare instruction used at the end.
820 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
821 MachineInstr *&CmpInst) const {
822 return true;
823 }
824
825 /// Generate code to reduce the loop iteration by one and check if the loop
826 /// is finished. Return the value/register of the new loop count. We need
827 /// this function when peeling off one or more iterations of a loop. This
828 /// function assumes the nth iteration is peeled first.
830 MachineBasicBlock &PreHeader,
831 MachineInstr *IndVar, MachineInstr &Cmp,
834 unsigned Iter, unsigned MaxIter) const {
835 llvm_unreachable("Target didn't implement ReduceLoopCount");
836 }
837
838 /// Delete the instruction OldInst and everything after it, replacing it with
839 /// an unconditional branch to NewDest. This is used by the tail merging pass.
841 MachineBasicBlock *NewDest) const;
842
843 /// Return true if it's legal to split the given basic
844 /// block at the specified instruction (i.e. instruction would be the start
845 /// of a new basic block).
848 return true;
849 }
850
851 /// Return true if it's profitable to predicate
852 /// instructions with accumulated instruction latency of "NumCycles"
853 /// of the specified basic block, where the probability of the instructions
854 /// being executed is given by Probability, and Confidence is a measure
855 /// of our confidence that it will be properly predicted.
856 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
857 unsigned ExtraPredCycles,
858 BranchProbability Probability) const {
859 return false;
860 }
861
862 /// Second variant of isProfitableToIfCvt. This one
863 /// checks for the case where two basic blocks from true and false path
864 /// of a if-then-else (diamond) are predicated on mutually exclusive
865 /// predicates, where the probability of the true path being taken is given
866 /// by Probability, and Confidence is a measure of our confidence that it
867 /// will be properly predicted.
868 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
869 unsigned ExtraTCycles,
870 MachineBasicBlock &FMBB, unsigned NumFCycles,
871 unsigned ExtraFCycles,
872 BranchProbability Probability) const {
873 return false;
874 }
875
876 /// Return true if it's profitable for if-converter to duplicate instructions
877 /// of specified accumulated instruction latencies in the specified MBB to
878 /// enable if-conversion.
879 /// The probability of the instructions being executed is given by
880 /// Probability, and Confidence is a measure of our confidence that it
881 /// will be properly predicted.
883 unsigned NumCycles,
884 BranchProbability Probability) const {
885 return false;
886 }
887
888 /// Return the increase in code size needed to predicate a contiguous run of
889 /// NumInsts instructions.
891 unsigned NumInsts) const {
892 return 0;
893 }
894
895 /// Return an estimate for the code size reduction (in bytes) which will be
896 /// caused by removing the given branch instruction during if-conversion.
897 virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {
898 return getInstSizeInBytes(MI);
899 }
900
901 /// Return true if it's profitable to unpredicate
902 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
903 /// exclusive predicates.
904 /// e.g.
905 /// subeq r0, r1, #1
906 /// addne r0, r1, #1
907 /// =>
908 /// sub r0, r1, #1
909 /// addne r0, r1, #1
910 ///
911 /// This may be profitable is conditional instructions are always executed.
913 MachineBasicBlock &FMBB) const {
914 return false;
915 }
916
917 /// Return true if it is possible to insert a select
918 /// instruction that chooses between TrueReg and FalseReg based on the
919 /// condition code in Cond.
920 ///
921 /// When successful, also return the latency in cycles from TrueReg,
922 /// FalseReg, and Cond to the destination register. In most cases, a select
923 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
924 ///
925 /// Some x86 implementations have 2-cycle cmov instructions.
926 ///
927 /// @param MBB Block where select instruction would be inserted.
928 /// @param Cond Condition returned by analyzeBranch.
929 /// @param DstReg Virtual dest register that the result should write to.
930 /// @param TrueReg Virtual register to select when Cond is true.
931 /// @param FalseReg Virtual register to select when Cond is false.
932 /// @param CondCycles Latency from Cond+Branch to select output.
933 /// @param TrueCycles Latency from TrueReg to select output.
934 /// @param FalseCycles Latency from FalseReg to select output.
937 Register TrueReg, Register FalseReg,
938 int &CondCycles, int &TrueCycles,
939 int &FalseCycles) const {
940 return false;
941 }
942
943 /// Insert a select instruction into MBB before I that will copy TrueReg to
944 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
945 ///
946 /// This function can only be called after canInsertSelect() returned true.
947 /// The condition in Cond comes from analyzeBranch, and it can be assumed
948 /// that the same flags or registers required by Cond are available at the
949 /// insertion point.
950 ///
951 /// @param MBB Block where select instruction should be inserted.
952 /// @param I Insertion point.
953 /// @param DL Source location for debugging.
954 /// @param DstReg Virtual register to be defined by select instruction.
955 /// @param Cond Condition as computed by analyzeBranch.
956 /// @param TrueReg Virtual register to copy when Cond is true.
957 /// @param FalseReg Virtual register to copy when Cons is false.
961 Register TrueReg, Register FalseReg) const {
962 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
963 }
964
965 /// Analyze the given select instruction, returning true if
966 /// it cannot be understood. It is assumed that MI->isSelect() is true.
967 ///
968 /// When successful, return the controlling condition and the operands that
969 /// determine the true and false result values.
970 ///
971 /// Result = SELECT Cond, TrueOp, FalseOp
972 ///
973 /// Some targets can optimize select instructions, for example by predicating
974 /// the instruction defining one of the operands. Such targets should set
975 /// Optimizable.
976 ///
977 /// @param MI Select instruction to analyze.
978 /// @param Cond Condition controlling the select.
979 /// @param TrueOp Operand number of the value selected when Cond is true.
980 /// @param FalseOp Operand number of the value selected when Cond is false.
981 /// @param Optimizable Returned as true if MI is optimizable.
982 /// @returns False on success.
983 virtual bool analyzeSelect(const MachineInstr &MI,
985 unsigned &TrueOp, unsigned &FalseOp,
986 bool &Optimizable) const {
987 assert(MI.getDesc().isSelect() && "MI must be a select instruction");
988 return true;
989 }
990
991 /// Given a select instruction that was understood by
992 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
993 /// merging it with one of its operands. Returns NULL on failure.
994 ///
995 /// When successful, returns the new select instruction. The client is
996 /// responsible for deleting MI.
997 ///
998 /// If both sides of the select can be optimized, PreferFalse is used to pick
999 /// a side.
1000 ///
1001 /// @param MI Optimizable select instruction.
1002 /// @param NewMIs Set that record all MIs in the basic block up to \p
1003 /// MI. Has to be updated with any newly created MI or deleted ones.
1004 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
1005 /// @returns Optimized instruction or NULL.
1008 bool PreferFalse = false) const {
1009 // This function must be implemented if Optimizable is ever set.
1010 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
1011 }
1012
1013 /// Emit instructions to copy a pair of physical registers.
1014 ///
1015 /// This function should support copies within any legal register class as
1016 /// well as any cross-class copies created during instruction selection.
1017 ///
1018 /// The source and destination registers may overlap, which may require a
1019 /// careful implementation when multiple copy instructions are required for
1020 /// large registers. See for example the ARM target.
1023 MCRegister DestReg, MCRegister SrcReg,
1024 bool KillSrc) const {
1025 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
1026 }
1027
1028 /// Allow targets to tell MachineVerifier whether a specific register
1029 /// MachineOperand can be used as part of PC-relative addressing.
1030 /// PC-relative addressing modes in many CISC architectures contain
1031 /// (non-PC) registers as offsets or scaling values, which inherently
1032 /// tags the corresponding MachineOperand with OPERAND_PCREL.
1033 ///
1034 /// @param MO The MachineOperand in question. MO.isReg() should always
1035 /// be true.
1036 /// @return Whether this operand is allowed to be used PC-relatively.
1037 virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const {
1038 return false;
1039 }
1040
1041 /// Return an index for MachineJumpTableInfo if \p insn is an indirect jump
1042 /// using a jump table, otherwise -1.
1043 virtual int getJumpTableIndex(const MachineInstr &MI) const { return -1; }
1044
1045protected:
1046 /// Target-dependent implementation for IsCopyInstr.
1047 /// If the specific machine instruction is a instruction that moves/copies
1048 /// value from one register to another register return destination and source
1049 /// registers as machine operands.
1050 virtual std::optional<DestSourcePair>
1052 return std::nullopt;
1053 }
1054
1055 virtual std::optional<DestSourcePair>
1057 return std::nullopt;
1058 }
1059
1060 /// Return true if the given terminator MI is not expected to spill. This
1061 /// sets the live interval as not spillable and adjusts phi node lowering to
1062 /// not introduce copies after the terminator. Use with care, these are
1063 /// currently used for hardware loop intrinsics in very controlled situations,
1064 /// created prior to registry allocation in loops that only have single phi
1065 /// users for the terminators value. They may run out of registers if not used
1066 /// carefully.
1067 virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const {
1068 return false;
1069 }
1070
1071public:
1072 /// If the specific machine instruction is a instruction that moves/copies
1073 /// value from one register to another register return destination and source
1074 /// registers as machine operands.
1075 /// For COPY-instruction the method naturally returns destination and source
1076 /// registers as machine operands, for all other instructions the method calls
1077 /// target-dependent implementation.
1078 std::optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const {
1079 if (MI.isCopy()) {
1080 return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1081 }
1082 return isCopyInstrImpl(MI);
1083 }
1084
1085 // Similar to `isCopyInstr`, but adds non-copy semantics on MIR, but
1086 // ultimately generates a copy instruction.
1087 std::optional<DestSourcePair> isCopyLikeInstr(const MachineInstr &MI) const {
1088 if (auto IsCopyInstr = isCopyInstr(MI))
1089 return IsCopyInstr;
1090 return isCopyLikeInstrImpl(MI);
1091 }
1092
1093 bool isFullCopyInstr(const MachineInstr &MI) const {
1094 auto DestSrc = isCopyInstr(MI);
1095 if (!DestSrc)
1096 return false;
1097
1098 const MachineOperand *DestRegOp = DestSrc->Destination;
1099 const MachineOperand *SrcRegOp = DestSrc->Source;
1100 return !DestRegOp->getSubReg() && !SrcRegOp->getSubReg();
1101 }
1102
1103 /// If the specific machine instruction is an instruction that adds an
1104 /// immediate value and a register, and stores the result in the given
1105 /// register \c Reg, return a pair of the source register and the offset
1106 /// which has been added.
1107 virtual std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
1108 Register Reg) const {
1109 return std::nullopt;
1110 }
1111
1112 /// Returns true if MI is an instruction that defines Reg to have a constant
1113 /// value and the value is recorded in ImmVal. The ImmVal is a result that
1114 /// should be interpreted as modulo size of Reg.
1116 const Register Reg,
1117 int64_t &ImmVal) const {
1118 return false;
1119 }
1120
1121 /// Store the specified register of the given register class to the specified
1122 /// stack frame index. The store instruction is to be added to the given
1123 /// machine basic block before the specified machine instruction. If isKill
1124 /// is true, the register operand is the last use and must be marked kill. If
1125 /// \p SrcReg is being directly spilled as part of assigning a virtual
1126 /// register, \p VReg is the register being assigned. This additional register
1127 /// argument is needed for certain targets when invoked from RegAllocFast to
1128 /// map the spilled physical register to its virtual register. A null register
1129 /// can be passed elsewhere.
1132 Register SrcReg, bool isKill, int FrameIndex,
1133 const TargetRegisterClass *RC,
1134 const TargetRegisterInfo *TRI,
1135 Register VReg) const {
1136 llvm_unreachable("Target didn't implement "
1137 "TargetInstrInfo::storeRegToStackSlot!");
1138 }
1139
1140 /// Load the specified register of the given register class from the specified
1141 /// stack frame index. The load instruction is to be added to the given
1142 /// machine basic block before the specified machine instruction. If \p
1143 /// DestReg is being directly reloaded as part of assigning a virtual
1144 /// register, \p VReg is the register being assigned. This additional register
1145 /// argument is needed for certain targets when invoked from RegAllocFast to
1146 /// map the loaded physical register to its virtual register. A null register
1147 /// can be passed elsewhere.
1150 Register DestReg, int FrameIndex,
1151 const TargetRegisterClass *RC,
1152 const TargetRegisterInfo *TRI,
1153 Register VReg) const {
1154 llvm_unreachable("Target didn't implement "
1155 "TargetInstrInfo::loadRegFromStackSlot!");
1156 }
1157
1158 /// This function is called for all pseudo instructions
1159 /// that remain after register allocation. Many pseudo instructions are
1160 /// created to help register allocation. This is the place to convert them
1161 /// into real instructions. The target can edit MI in place, or it can insert
1162 /// new instructions and erase MI. The function should return true if
1163 /// anything was changed.
1164 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
1165
1166 /// Check whether the target can fold a load that feeds a subreg operand
1167 /// (or a subreg operand that feeds a store).
1168 /// For example, X86 may want to return true if it can fold
1169 /// movl (%esp), %eax
1170 /// subb, %al, ...
1171 /// Into:
1172 /// subb (%esp), ...
1173 ///
1174 /// Ideally, we'd like the target implementation of foldMemoryOperand() to
1175 /// reject subregs - but since this behavior used to be enforced in the
1176 /// target-independent code, moving this responsibility to the targets
1177 /// has the potential of causing nasty silent breakage in out-of-tree targets.
1178 virtual bool isSubregFoldable() const { return false; }
1179
1180 /// For a patchpoint, stackmap, or statepoint intrinsic, return the range of
1181 /// operands which can't be folded into stack references. Operands outside
1182 /// of the range are most likely foldable but it is not guaranteed.
1183 /// These instructions are unique in that stack references for some operands
1184 /// have the same execution cost (e.g. none) as the unfolded register forms.
1185 /// The ranged return is guaranteed to include all operands which can't be
1186 /// folded at zero cost.
1187 virtual std::pair<unsigned, unsigned>
1189
1190 /// Attempt to fold a load or store of the specified stack
1191 /// slot into the specified machine instruction for the specified operand(s).
1192 /// If this is possible, a new instruction is returned with the specified
1193 /// operand folded, otherwise NULL is returned.
1194 /// The new instruction is inserted before MI, and the client is responsible
1195 /// for removing the old instruction.
1196 /// If VRM is passed, the assigned physregs can be inspected by target to
1197 /// decide on using an opcode (note that those assignments can still change).
1199 int FI,
1200 LiveIntervals *LIS = nullptr,
1201 VirtRegMap *VRM = nullptr) const;
1202
1203 /// Same as the previous version except it allows folding of any load and
1204 /// store from / to any address, not just from a specific stack slot.
1206 MachineInstr &LoadMI,
1207 LiveIntervals *LIS = nullptr) const;
1208
1209 /// This function defines the logic to lower COPY instruction to
1210 /// target specific instruction(s).
1211 void lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const;
1212
1213 /// Return true when there is potentially a faster code sequence
1214 /// for an instruction chain ending in \p Root. All potential patterns are
1215 /// returned in the \p Pattern vector. Pattern should be sorted in priority
1216 /// order since the pattern evaluator stops checking as soon as it finds a
1217 /// faster sequence.
1218 /// \param Root - Instruction that could be combined with one of its operands
1219 /// \param Patterns - Vector of possible combination patterns
1220 virtual bool getMachineCombinerPatterns(MachineInstr &Root,
1221 SmallVectorImpl<unsigned> &Patterns,
1222 bool DoRegPressureReduce) const;
1223
1224 /// Return true if target supports reassociation of instructions in machine
1225 /// combiner pass to reduce register pressure for a given BB.
1226 virtual bool
1228 const RegisterClassInfo *RegClassInfo) const {
1229 return false;
1230 }
1231
1232 /// Fix up the placeholder we may add in genAlternativeCodeSequence().
1233 virtual void
1235 SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
1236
1237 /// Return true when a code sequence can improve throughput. It
1238 /// should be called only for instructions in loops.
1239 /// \param Pattern - combiner pattern
1240 virtual bool isThroughputPattern(unsigned Pattern) const;
1241
1242 /// Return the objective of a combiner pattern.
1243 /// \param Pattern - combiner pattern
1244 virtual CombinerObjective getCombinerObjective(unsigned Pattern) const;
1245
1246 /// Return true if the input \P Inst is part of a chain of dependent ops
1247 /// that are suitable for reassociation, otherwise return false.
1248 /// If the instruction's operands must be commuted to have a previous
1249 /// instruction of the same type define the first source operand, \P Commuted
1250 /// will be set to true.
1251 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1252
1253 /// Return true when \P Inst is both associative and commutative. If \P Invert
1254 /// is true, then the inverse of \P Inst operation must be tested.
1256 bool Invert = false) const {
1257 return false;
1258 }
1259
1260 /// Return the inverse operation opcode if it exists for \P Opcode (e.g. add
1261 /// for sub and vice versa).
1262 virtual std::optional<unsigned> getInverseOpcode(unsigned Opcode) const {
1263 return std::nullopt;
1264 }
1265
1266 /// Return true when \P Opcode1 or its inversion is equal to \P Opcode2.
1267 bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const;
1268
1269 /// Return true when \P Inst has reassociable operands in the same \P MBB.
1270 virtual bool hasReassociableOperands(const MachineInstr &Inst,
1271 const MachineBasicBlock *MBB) const;
1272
1273 /// Return true when \P Inst has reassociable sibling.
1274 virtual bool hasReassociableSibling(const MachineInstr &Inst,
1275 bool &Commuted) const;
1276
1277 /// When getMachineCombinerPatterns() finds patterns, this function generates
1278 /// the instructions that could replace the original code sequence. The client
1279 /// has to decide whether the actual replacement is beneficial or not.
1280 /// \param Root - Instruction that could be combined with one of its operands
1281 /// \param Pattern - Combination pattern for Root
1282 /// \param InsInstrs - Vector of new instructions that implement P
1283 /// \param DelInstrs - Old instructions, including Root, that could be
1284 /// replaced by InsInstr
1285 /// \param InstIdxForVirtReg - map of virtual register to instruction in
1286 /// InsInstr that defines it
1287 virtual void genAlternativeCodeSequence(
1288 MachineInstr &Root, unsigned Pattern,
1291 DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1292
1293 /// When calculate the latency of the root instruction, accumulate the
1294 /// latency of the sequence to the root latency.
1295 /// \param Root - Instruction that could be combined with one of its operands
1297 return true;
1298 }
1299
1300 /// The returned array encodes the operand index for each parameter because
1301 /// the operands may be commuted; the operand indices for associative
1302 /// operations might also be target-specific. Each element specifies the index
1303 /// of {Prev, A, B, X, Y}.
1304 virtual void
1306 std::array<unsigned, 5> &OperandIndices) const;
1307
1308 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1309 /// reduce critical path length.
1310 void reassociateOps(MachineInstr &Root, MachineInstr &Prev, unsigned Pattern,
1314 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1315
1316 /// Reassociation of some instructions requires inverse operations (e.g.
1317 /// (X + A) - Y => (X - Y) + A). This method returns a pair of new opcodes
1318 /// (new root opcode, new prev opcode) that must be used to reassociate \P
1319 /// Root and \P Prev accoring to \P Pattern.
1320 std::pair<unsigned, unsigned>
1321 getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root,
1322 const MachineInstr &Prev) const;
1323
1324 /// The limit on resource length extension we accept in MachineCombiner Pass.
1325 virtual int getExtendResourceLenLimit() const { return 0; }
1326
1327 /// This is an architecture-specific helper function of reassociateOps.
1328 /// Set special operand attributes for new instructions after reassociation.
1329 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1330 MachineInstr &NewMI1,
1331 MachineInstr &NewMI2) const {}
1332
1333 /// Return true when a target supports MachineCombiner.
1334 virtual bool useMachineCombiner() const { return false; }
1335
1336 /// Return a strategy that MachineCombiner must use when creating traces.
1338
1339 /// Return true if the given SDNode can be copied during scheduling
1340 /// even if it has glue.
1341 virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1342
1343protected:
1344 /// Target-dependent implementation for foldMemoryOperand.
1345 /// Target-independent code in foldMemoryOperand will
1346 /// take care of adding a MachineMemOperand to the newly created instruction.
1347 /// The instruction and any auxiliary instructions necessary will be inserted
1348 /// at InsertPt.
1349 virtual MachineInstr *
1352 MachineBasicBlock::iterator InsertPt, int FrameIndex,
1353 LiveIntervals *LIS = nullptr,
1354 VirtRegMap *VRM = nullptr) const {
1355 return nullptr;
1356 }
1357
1358 /// Target-dependent implementation for foldMemoryOperand.
1359 /// Target-independent code in foldMemoryOperand will
1360 /// take care of adding a MachineMemOperand to the newly created instruction.
1361 /// The instruction and any auxiliary instructions necessary will be inserted
1362 /// at InsertPt.
1365 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1366 LiveIntervals *LIS = nullptr) const {
1367 return nullptr;
1368 }
1369
1370 /// Target-dependent implementation of getRegSequenceInputs.
1371 ///
1372 /// \returns true if it is possible to build the equivalent
1373 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1374 ///
1375 /// \pre MI.isRegSequenceLike().
1376 ///
1377 /// \see TargetInstrInfo::getRegSequenceInputs.
1379 const MachineInstr &MI, unsigned DefIdx,
1380 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1381 return false;
1382 }
1383
1384 /// Target-dependent implementation of getExtractSubregInputs.
1385 ///
1386 /// \returns true if it is possible to build the equivalent
1387 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1388 ///
1389 /// \pre MI.isExtractSubregLike().
1390 ///
1391 /// \see TargetInstrInfo::getExtractSubregInputs.
1393 unsigned DefIdx,
1394 RegSubRegPairAndIdx &InputReg) const {
1395 return false;
1396 }
1397
1398 /// Target-dependent implementation of getInsertSubregInputs.
1399 ///
1400 /// \returns true if it is possible to build the equivalent
1401 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1402 ///
1403 /// \pre MI.isInsertSubregLike().
1404 ///
1405 /// \see TargetInstrInfo::getInsertSubregInputs.
1406 virtual bool
1408 RegSubRegPair &BaseReg,
1409 RegSubRegPairAndIdx &InsertedReg) const {
1410 return false;
1411 }
1412
1413public:
1414 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1415 /// a store or a load and a store into two or more instruction. If this is
1416 /// possible, returns true as well as the new instructions by reference.
1417 virtual bool
1419 bool UnfoldLoad, bool UnfoldStore,
1420 SmallVectorImpl<MachineInstr *> &NewMIs) const {
1421 return false;
1422 }
1423
1425 SmallVectorImpl<SDNode *> &NewNodes) const {
1426 return false;
1427 }
1428
1429 /// Returns the opcode of the would be new
1430 /// instruction after load / store are unfolded from an instruction of the
1431 /// specified opcode. It returns zero if the specified unfolding is not
1432 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1433 /// index of the operand which will hold the register holding the loaded
1434 /// value.
1435 virtual unsigned
1436 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1437 unsigned *LoadRegIndex = nullptr) const {
1438 return 0;
1439 }
1440
1441 /// This is used by the pre-regalloc scheduler to determine if two loads are
1442 /// loading from the same base address. It should only return true if the base
1443 /// pointers are the same and the only differences between the two addresses
1444 /// are the offset. It also returns the offsets by reference.
1445 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1446 int64_t &Offset1,
1447 int64_t &Offset2) const {
1448 return false;
1449 }
1450
1451 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1452 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1453 /// On some targets if two loads are loading from
1454 /// addresses in the same cache line, it's better if they are scheduled
1455 /// together. This function takes two integers that represent the load offsets
1456 /// from the common base address. It returns true if it decides it's desirable
1457 /// to schedule the two loads together. "NumLoads" is the number of loads that
1458 /// have already been scheduled after Load1.
1459 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1460 int64_t Offset1, int64_t Offset2,
1461 unsigned NumLoads) const {
1462 return false;
1463 }
1464
1465 /// Get the base operand and byte offset of an instruction that reads/writes
1466 /// memory. This is a convenience function for callers that are only prepared
1467 /// to handle a single base operand.
1468 /// FIXME: Move Offset and OffsetIsScalable to some ElementCount-style
1469 /// abstraction that supports negative offsets.
1471 const MachineOperand *&BaseOp, int64_t &Offset,
1472 bool &OffsetIsScalable,
1473 const TargetRegisterInfo *TRI) const;
1474
1475 /// Get zero or more base operands and the byte offset of an instruction that
1476 /// reads/writes memory. Note that there may be zero base operands if the
1477 /// instruction accesses a constant address.
1478 /// It returns false if MI does not read/write memory.
1479 /// It returns false if base operands and offset could not be determined.
1480 /// It is not guaranteed to always recognize base operands and offsets in all
1481 /// cases.
1482 /// FIXME: Move Offset and OffsetIsScalable to some ElementCount-style
1483 /// abstraction that supports negative offsets.
1486 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
1487 const TargetRegisterInfo *TRI) const {
1488 return false;
1489 }
1490
1491 /// Return true if the instruction contains a base register and offset. If
1492 /// true, the function also sets the operand position in the instruction
1493 /// for the base register and offset.
1495 unsigned &BasePos,
1496 unsigned &OffsetPos) const {
1497 return false;
1498 }
1499
1500 /// Target dependent implementation to get the values constituting the address
1501 /// MachineInstr that is accessing memory. These values are returned as a
1502 /// struct ExtAddrMode which contains all relevant information to make up the
1503 /// address.
1504 virtual std::optional<ExtAddrMode>
1506 const TargetRegisterInfo *TRI) const {
1507 return std::nullopt;
1508 }
1509
1510 /// Check if it's possible and beneficial to fold the addressing computation
1511 /// `AddrI` into the addressing mode of the load/store instruction `MemI`. The
1512 /// memory instruction is a user of the virtual register `Reg`, which in turn
1513 /// is the ultimate destination of zero or more COPY instructions from the
1514 /// output register of `AddrI`.
1515 /// Return the adddressing mode after folding in `AM`.
1517 const MachineInstr &AddrI,
1518 ExtAddrMode &AM) const {
1519 return false;
1520 }
1521
1522 /// Emit a load/store instruction with the same value register as `MemI`, but
1523 /// using the address from `AM`. The addressing mode must have been obtained
1524 /// from `canFoldIntoAddr` for the same memory instruction.
1526 const ExtAddrMode &AM) const {
1527 llvm_unreachable("target did not implement emitLdStWithAddr()");
1528 }
1529
1530 /// Returns true if MI's Def is NullValueReg, and the MI
1531 /// does not change the Zero value. i.e. cases such as rax = shr rax, X where
1532 /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this
1533 /// function can return true even if becomes zero. Specifically cases such as
1534 /// NullValueReg = shl NullValueReg, 63.
1536 const Register NullValueReg,
1537 const TargetRegisterInfo *TRI) const {
1538 return false;
1539 }
1540
1541 /// If the instruction is an increment of a constant value, return the amount.
1542 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1543 return false;
1544 }
1545
1546 /// Returns true if the two given memory operations should be scheduled
1547 /// adjacent. Note that you have to add:
1548 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1549 /// or
1550 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1551 /// to TargetPassConfig::createMachineScheduler() to have an effect.
1552 ///
1553 /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.
1554 /// \p Offset1 and \p Offset2 are the byte offsets for the memory
1555 /// operations.
1556 /// \p OffsetIsScalable1 and \p OffsetIsScalable2 indicate if the offset is
1557 /// scaled by a runtime quantity.
1558 /// \p ClusterSize is the number of operations in the resulting load/store
1559 /// cluster if this hook returns true.
1560 /// \p NumBytes is the number of bytes that will be loaded from all the
1561 /// clustered loads if this hook returns true.
1563 int64_t Offset1, bool OffsetIsScalable1,
1565 int64_t Offset2, bool OffsetIsScalable2,
1566 unsigned ClusterSize,
1567 unsigned NumBytes) const {
1568 llvm_unreachable("target did not implement shouldClusterMemOps()");
1569 }
1570
1571 /// Reverses the branch condition of the specified condition list,
1572 /// returning false on success and true if it cannot be reversed.
1573 virtual bool
1575 return true;
1576 }
1577
1578 /// Insert a noop into the instruction stream at the specified point.
1579 virtual void insertNoop(MachineBasicBlock &MBB,
1581
1582 /// Insert noops into the instruction stream at the specified point.
1583 virtual void insertNoops(MachineBasicBlock &MBB,
1585 unsigned Quantity) const;
1586
1587 /// Return the noop instruction to use for a noop.
1588 virtual MCInst getNop() const;
1589
1590 /// Return true for post-incremented instructions.
1591 virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1592
1593 /// Returns true if the instruction is already predicated.
1594 virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1595
1596 /// Assumes the instruction is already predicated and returns true if the
1597 /// instruction can be predicated again.
1598 virtual bool canPredicatePredicatedInstr(const MachineInstr &MI) const {
1599 assert(isPredicated(MI) && "Instruction is not predicated");
1600 return false;
1601 }
1602
1603 // Returns a MIRPrinter comment for this machine operand.
1604 virtual std::string
1606 unsigned OpIdx, const TargetRegisterInfo *TRI) const;
1607
1608 /// Returns true if the instruction is a
1609 /// terminator instruction that has not been predicated.
1610 bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1611
1612 /// Returns true if MI is an unconditional tail call.
1613 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1614 return false;
1615 }
1616
1617 /// Returns true if the tail call can be made conditional on BranchCond.
1619 const MachineInstr &TailCall) const {
1620 return false;
1621 }
1622
1623 /// Replace the conditional branch in MBB with a conditional tail call.
1626 const MachineInstr &TailCall) const {
1627 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1628 }
1629
1630 /// Convert the instruction into a predicated instruction.
1631 /// It returns true if the operation was successful.
1632 virtual bool PredicateInstruction(MachineInstr &MI,
1633 ArrayRef<MachineOperand> Pred) const;
1634
1635 /// Returns true if the first specified predicate
1636 /// subsumes the second, e.g. GE subsumes GT.
1638 ArrayRef<MachineOperand> Pred2) const {
1639 return false;
1640 }
1641
1642 /// If the specified instruction defines any predicate
1643 /// or condition code register(s) used for predication, returns true as well
1644 /// as the definition predicate(s) by reference.
1645 /// SkipDead should be set to false at any point that dead
1646 /// predicate instructions should be considered as being defined.
1647 /// A dead predicate instruction is one that is guaranteed to be removed
1648 /// after a call to PredicateInstruction.
1650 std::vector<MachineOperand> &Pred,
1651 bool SkipDead) const {
1652 return false;
1653 }
1654
1655 /// Return true if the specified instruction can be predicated.
1656 /// By default, this returns true for every instruction with a
1657 /// PredicateOperand.
1658 virtual bool isPredicable(const MachineInstr &MI) const {
1659 return MI.getDesc().isPredicable();
1660 }
1661
1662 /// Return true if it's safe to move a machine
1663 /// instruction that defines the specified register class.
1664 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1665 return true;
1666 }
1667
1668 /// Test if the given instruction should be considered a scheduling boundary.
1669 /// This primarily includes labels and terminators.
1670 virtual bool isSchedulingBoundary(const MachineInstr &MI,
1671 const MachineBasicBlock *MBB,
1672 const MachineFunction &MF) const;
1673
1674 /// Measure the specified inline asm to determine an approximation of its
1675 /// length.
1676 virtual unsigned getInlineAsmLength(
1677 const char *Str, const MCAsmInfo &MAI,
1678 const TargetSubtargetInfo *STI = nullptr) const;
1679
1680 /// Allocate and return a hazard recognizer to use for this target when
1681 /// scheduling the machine instructions before register allocation.
1682 virtual ScheduleHazardRecognizer *
1684 const ScheduleDAG *DAG) const;
1685
1686 /// Allocate and return a hazard recognizer to use for this target when
1687 /// scheduling the machine instructions before register allocation.
1688 virtual ScheduleHazardRecognizer *
1690 const ScheduleDAGMI *DAG) const;
1691
1692 /// Allocate and return a hazard recognizer to use for this target when
1693 /// scheduling the machine instructions after register allocation.
1694 virtual ScheduleHazardRecognizer *
1696 const ScheduleDAG *DAG) const;
1697
1698 /// Allocate and return a hazard recognizer to use for by non-scheduling
1699 /// passes.
1700 virtual ScheduleHazardRecognizer *
1702 return nullptr;
1703 }
1704
1705 /// Provide a global flag for disabling the PreRA hazard recognizer that
1706 /// targets may choose to honor.
1707 bool usePreRAHazardRecognizer() const;
1708
1709 /// For a comparison instruction, return the source registers
1710 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1711 /// compares against in CmpValue. Return true if the comparison instruction
1712 /// can be analyzed.
1713 virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1714 Register &SrcReg2, int64_t &Mask,
1715 int64_t &Value) const {
1716 return false;
1717 }
1718
1719 /// See if the comparison instruction can be converted
1720 /// into something more efficient. E.g., on ARM most instructions can set the
1721 /// flags register, obviating the need for a separate CMP.
1722 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1723 Register SrcReg2, int64_t Mask,
1724 int64_t Value,
1725 const MachineRegisterInfo *MRI) const {
1726 return false;
1727 }
1728 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1729
1730 /// Try to remove the load by folding it to a register operand at the use.
1731 /// We fold the load instructions if and only if the
1732 /// def and use are in the same BB. We only look at one load and see
1733 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1734 /// defined by the load we are trying to fold. DefMI returns the machine
1735 /// instruction that defines FoldAsLoadDefReg, and the function returns
1736 /// the machine instruction generated due to folding.
1738 const MachineRegisterInfo *MRI,
1739 Register &FoldAsLoadDefReg,
1740 MachineInstr *&DefMI) const {
1741 return nullptr;
1742 }
1743
1744 /// 'Reg' is known to be defined by a move immediate instruction,
1745 /// try to fold the immediate into the use instruction.
1746 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1747 /// then the caller may assume that DefMI has been erased from its parent
1748 /// block. The caller may assume that it will not be erased by this
1749 /// function otherwise.
1752 return false;
1753 }
1754
1755 /// Return the number of u-operations the given machine
1756 /// instruction will be decoded to on the target cpu. The itinerary's
1757 /// IssueWidth is the number of microops that can be dispatched each
1758 /// cycle. An instruction with zero microops takes no dispatch resources.
1759 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1760 const MachineInstr &MI) const;
1761
1762 /// Return true for pseudo instructions that don't consume any
1763 /// machine resources in their current form. These are common cases that the
1764 /// scheduler should consider free, rather than conservatively handling them
1765 /// as instructions with no itinerary.
1766 bool isZeroCost(unsigned Opcode) const {
1767 return Opcode <= TargetOpcode::COPY;
1768 }
1769
1770 virtual std::optional<unsigned>
1771 getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode,
1772 unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const;
1773
1774 /// Compute and return the use operand latency of a given pair of def and use.
1775 /// In most cases, the static scheduling itinerary was enough to determine the
1776 /// operand latency. But it may not be possible for instructions with variable
1777 /// number of defs / uses.
1778 ///
1779 /// This is a raw interface to the itinerary that may be directly overridden
1780 /// by a target. Use computeOperandLatency to get the best estimate of
1781 /// latency.
1782 virtual std::optional<unsigned>
1783 getOperandLatency(const InstrItineraryData *ItinData,
1784 const MachineInstr &DefMI, unsigned DefIdx,
1785 const MachineInstr &UseMI, unsigned UseIdx) const;
1786
1787 /// Compute the instruction latency of a given instruction.
1788 /// If the instruction has higher cost when predicated, it's returned via
1789 /// PredCost.
1790 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1791 const MachineInstr &MI,
1792 unsigned *PredCost = nullptr) const;
1793
1794 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1795
1796 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1797 SDNode *Node) const;
1798
1799 /// Return the default expected latency for a def based on its opcode.
1800 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1801 const MachineInstr &DefMI) const;
1802
1803 /// Return true if this opcode has high latency to its result.
1804 virtual bool isHighLatencyDef(int opc) const { return false; }
1805
1806 /// Compute operand latency between a def of 'Reg'
1807 /// and a use in the current loop. Return true if the target considered
1808 /// it 'high'. This is used by optimization passes such as machine LICM to
1809 /// determine whether it makes sense to hoist an instruction out even in a
1810 /// high register pressure situation.
1811 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1812 const MachineRegisterInfo *MRI,
1813 const MachineInstr &DefMI, unsigned DefIdx,
1814 const MachineInstr &UseMI,
1815 unsigned UseIdx) const {
1816 return false;
1817 }
1818
1819 /// Compute operand latency of a def of 'Reg'. Return true
1820 /// if the target considered it 'low'.
1821 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1822 const MachineInstr &DefMI,
1823 unsigned DefIdx) const;
1824
1825 /// Perform target-specific instruction verification.
1826 virtual bool verifyInstruction(const MachineInstr &MI,
1827 StringRef &ErrInfo) const {
1828 return true;
1829 }
1830
1831 /// Return the current execution domain and bit mask of
1832 /// possible domains for instruction.
1833 ///
1834 /// Some micro-architectures have multiple execution domains, and multiple
1835 /// opcodes that perform the same operation in different domains. For
1836 /// example, the x86 architecture provides the por, orps, and orpd
1837 /// instructions that all do the same thing. There is a latency penalty if a
1838 /// register is written in one domain and read in another.
1839 ///
1840 /// This function returns a pair (domain, mask) containing the execution
1841 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1842 /// function can be used to change the opcode to one of the domains in the
1843 /// bit mask. Instructions whose execution domain can't be changed should
1844 /// return a 0 mask.
1845 ///
1846 /// The execution domain numbers don't have any special meaning except domain
1847 /// 0 is used for instructions that are not associated with any interesting
1848 /// execution domain.
1849 ///
1850 virtual std::pair<uint16_t, uint16_t>
1852 return std::make_pair(0, 0);
1853 }
1854
1855 /// Change the opcode of MI to execute in Domain.
1856 ///
1857 /// The bit (1 << Domain) must be set in the mask returned from
1858 /// getExecutionDomain(MI).
1859 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1860
1861 /// Returns the preferred minimum clearance
1862 /// before an instruction with an unwanted partial register update.
1863 ///
1864 /// Some instructions only write part of a register, and implicitly need to
1865 /// read the other parts of the register. This may cause unwanted stalls
1866 /// preventing otherwise unrelated instructions from executing in parallel in
1867 /// an out-of-order CPU.
1868 ///
1869 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1870 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1871 /// the instruction needs to wait for the old value of the register to become
1872 /// available:
1873 ///
1874 /// addps %xmm1, %xmm0
1875 /// movaps %xmm0, (%rax)
1876 /// cvtsi2ss %rbx, %xmm0
1877 ///
1878 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1879 /// instruction before it can issue, even though the high bits of %xmm0
1880 /// probably aren't needed.
1881 ///
1882 /// This hook returns the preferred clearance before MI, measured in
1883 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1884 /// instructions before MI. It should only return a positive value for
1885 /// unwanted dependencies. If the old bits of the defined register have
1886 /// useful values, or if MI is determined to otherwise read the dependency,
1887 /// the hook should return 0.
1888 ///
1889 /// The unwanted dependency may be handled by:
1890 ///
1891 /// 1. Allocating the same register for an MI def and use. That makes the
1892 /// unwanted dependency identical to a required dependency.
1893 ///
1894 /// 2. Allocating a register for the def that has no defs in the previous N
1895 /// instructions.
1896 ///
1897 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1898 /// allows the target to insert a dependency breaking instruction.
1899 ///
1900 virtual unsigned
1902 const TargetRegisterInfo *TRI) const {
1903 // The default implementation returns 0 for no partial register dependency.
1904 return 0;
1905 }
1906
1907 /// Return the minimum clearance before an instruction that reads an
1908 /// unused register.
1909 ///
1910 /// For example, AVX instructions may copy part of a register operand into
1911 /// the unused high bits of the destination register.
1912 ///
1913 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1914 ///
1915 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1916 /// false dependence on any previous write to %xmm0.
1917 ///
1918 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1919 /// does not take an operand index. Instead sets \p OpNum to the index of the
1920 /// unused register.
1921 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
1922 const TargetRegisterInfo *TRI) const {
1923 // The default implementation returns 0 for no undef register dependency.
1924 return 0;
1925 }
1926
1927 /// Insert a dependency-breaking instruction
1928 /// before MI to eliminate an unwanted dependency on OpNum.
1929 ///
1930 /// If it wasn't possible to avoid a def in the last N instructions before MI
1931 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1932 /// unwanted dependency.
1933 ///
1934 /// On x86, an xorps instruction can be used as a dependency breaker:
1935 ///
1936 /// addps %xmm1, %xmm0
1937 /// movaps %xmm0, (%rax)
1938 /// xorps %xmm0, %xmm0
1939 /// cvtsi2ss %rbx, %xmm0
1940 ///
1941 /// An <imp-kill> operand should be added to MI if an instruction was
1942 /// inserted. This ties the instructions together in the post-ra scheduler.
1943 ///
1944 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1945 const TargetRegisterInfo *TRI) const {}
1946
1947 /// Create machine specific model for scheduling.
1948 virtual DFAPacketizer *
1950 return nullptr;
1951 }
1952
1953 /// Sometimes, it is possible for the target
1954 /// to tell, even without aliasing information, that two MIs access different
1955 /// memory addresses. This function returns true if two MIs access different
1956 /// memory addresses and false otherwise.
1957 ///
1958 /// Assumes any physical registers used to compute addresses have the same
1959 /// value for both instructions. (This is the most useful assumption for
1960 /// post-RA scheduling.)
1961 ///
1962 /// See also MachineInstr::mayAlias, which is implemented on top of this
1963 /// function.
1964 virtual bool
1966 const MachineInstr &MIb) const {
1967 assert(MIa.mayLoadOrStore() &&
1968 "MIa must load from or modify a memory location");
1969 assert(MIb.mayLoadOrStore() &&
1970 "MIb must load from or modify a memory location");
1971 return false;
1972 }
1973
1974 /// Return the value to use for the MachineCSE's LookAheadLimit,
1975 /// which is a heuristic used for CSE'ing phys reg defs.
1976 virtual unsigned getMachineCSELookAheadLimit() const {
1977 // The default lookahead is small to prevent unprofitable quadratic
1978 // behavior.
1979 return 5;
1980 }
1981
1982 /// Return the maximal number of alias checks on memory operands. For
1983 /// instructions with more than one memory operands, the alias check on a
1984 /// single MachineInstr pair has quadratic overhead and results in
1985 /// unacceptable performance in the worst case. The limit here is to clamp
1986 /// that maximal checks performed. Usually, that's the product of memory
1987 /// operand numbers from that pair of MachineInstr to be checked. For
1988 /// instance, with two MachineInstrs with 4 and 5 memory operands
1989 /// correspondingly, a total of 20 checks are required. With this limit set to
1990 /// 16, their alias check is skipped. We choose to limit the product instead
1991 /// of the individual instruction as targets may have special MachineInstrs
1992 /// with a considerably high number of memory operands, such as `ldm` in ARM.
1993 /// Setting this limit per MachineInstr would result in either too high
1994 /// overhead or too rigid restriction.
1995 virtual unsigned getMemOperandAACheckLimit() const { return 16; }
1996
1997 /// Return an array that contains the ids of the target indices (used for the
1998 /// TargetIndex machine operand) and their names.
1999 ///
2000 /// MIR Serialization is able to serialize only the target indices that are
2001 /// defined by this method.
2004 return std::nullopt;
2005 }
2006
2007 /// Decompose the machine operand's target flags into two values - the direct
2008 /// target flag value and any of bit flags that are applied.
2009 virtual std::pair<unsigned, unsigned>
2011 return std::make_pair(0u, 0u);
2012 }
2013
2014 /// Return an array that contains the direct target flag values and their
2015 /// names.
2016 ///
2017 /// MIR Serialization is able to serialize only the target flags that are
2018 /// defined by this method.
2021 return std::nullopt;
2022 }
2023
2024 /// Return an array that contains the bitmask target flag values and their
2025 /// names.
2026 ///
2027 /// MIR Serialization is able to serialize only the target flags that are
2028 /// defined by this method.
2031 return std::nullopt;
2032 }
2033
2034 /// Return an array that contains the MMO target flag values and their
2035 /// names.
2036 ///
2037 /// MIR Serialization is able to serialize only the MMO target flags that are
2038 /// defined by this method.
2041 return std::nullopt;
2042 }
2043
2044 /// Determines whether \p Inst is a tail call instruction. Override this
2045 /// method on targets that do not properly set MCID::Return and MCID::Call on
2046 /// tail call instructions."
2047 virtual bool isTailCall(const MachineInstr &Inst) const {
2048 return Inst.isReturn() && Inst.isCall();
2049 }
2050
2051 /// True if the instruction is bound to the top of its basic block and no
2052 /// other instructions shall be inserted before it. This can be implemented
2053 /// to prevent register allocator to insert spills for \p Reg before such
2054 /// instructions.
2056 Register Reg = Register()) const {
2057 return false;
2058 }
2059
2060 /// Allows targets to use appropriate copy instruction while spilitting live
2061 /// range of a register in register allocation.
2063 const MachineFunction &MF) const {
2064 return TargetOpcode::COPY;
2065 }
2066
2067 /// During PHI eleimination lets target to make necessary checks and
2068 /// insert the copy to the PHI destination register in a target specific
2069 /// manner.
2072 const DebugLoc &DL, Register Src, Register Dst) const {
2073 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
2074 .addReg(Src);
2075 }
2076
2077 /// During PHI eleimination lets target to make necessary checks and
2078 /// insert the copy to the PHI destination register in a target specific
2079 /// manner.
2082 const DebugLoc &DL, Register Src,
2083 unsigned SrcSubReg,
2084 Register Dst) const {
2085 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
2086 .addReg(Src, 0, SrcSubReg);
2087 }
2088
2089 /// Returns a \p outliner::OutlinedFunction struct containing target-specific
2090 /// information for a set of outlining candidates. Returns std::nullopt if the
2091 /// candidates are not suitable for outlining.
2092 virtual std::optional<outliner::OutlinedFunction> getOutliningCandidateInfo(
2093 const MachineModuleInfo &MMI,
2094 std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
2096 "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
2097 }
2098
2099 /// Optional target hook to create the LLVM IR attributes for the outlined
2100 /// function. If overridden, the overriding function must call the default
2101 /// implementation.
2103 Function &F, std::vector<outliner::Candidate> &Candidates) const;
2104
2105protected:
2106 /// Target-dependent implementation for getOutliningTypeImpl.
2107 virtual outliner::InstrType
2109 MachineBasicBlock::iterator &MIT, unsigned Flags) const {
2111 "Target didn't implement TargetInstrInfo::getOutliningTypeImpl!");
2112 }
2113
2114public:
2115 /// Returns how or if \p MIT should be outlined. \p Flags is the
2116 /// target-specific information returned by isMBBSafeToOutlineFrom.
2119 unsigned Flags) const;
2120
2121 /// Optional target hook that returns true if \p MBB is safe to outline from,
2122 /// and returns any target-specific information in \p Flags.
2124 unsigned &Flags) const;
2125
2126 /// Optional target hook which partitions \p MBB into outlinable ranges for
2127 /// instruction mapping purposes. Each range is defined by two iterators:
2128 /// [start, end).
2129 ///
2130 /// Ranges are expected to be ordered top-down. That is, ranges closer to the
2131 /// top of the block should come before ranges closer to the end of the block.
2132 ///
2133 /// Ranges cannot overlap.
2134 ///
2135 /// If an entire block is mappable, then its range is [MBB.begin(), MBB.end())
2136 ///
2137 /// All instructions not present in an outlinable range are considered
2138 /// illegal.
2139 virtual SmallVector<
2140 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
2141 getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const {
2142 return {std::make_pair(MBB.begin(), MBB.end())};
2143 }
2144
2145 /// Insert a custom frame for outlined functions.
2147 const outliner::OutlinedFunction &OF) const {
2149 "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
2150 }
2151
2152 /// Insert a call to an outlined function into the program.
2153 /// Returns an iterator to the spot where we inserted the call. This must be
2154 /// implemented by the target.
2158 outliner::Candidate &C) const {
2160 "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
2161 }
2162
2163 /// Insert an architecture-specific instruction to clear a register. If you
2164 /// need to avoid sideeffects (e.g. avoid XOR on x86, which sets EFLAGS), set
2165 /// \p AllowSideEffects to \p false.
2168 DebugLoc &DL,
2169 bool AllowSideEffects = true) const {
2170#if 0
2171 // FIXME: This should exist once all platforms that use stack protectors
2172 // implements it.
2174 "Target didn't implement TargetInstrInfo::buildClearRegister!");
2175#endif
2176 }
2177
2178 /// Return true if the function can safely be outlined from.
2179 /// A function \p MF is considered safe for outlining if an outlined function
2180 /// produced from instructions in F will produce a program which produces the
2181 /// same output for any set of given inputs.
2183 bool OutlineFromLinkOnceODRs) const {
2184 llvm_unreachable("Target didn't implement "
2185 "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
2186 }
2187
2188 /// Return true if the function should be outlined from by default.
2190 return false;
2191 }
2192
2193 /// Return true if the function is a viable candidate for machine function
2194 /// splitting. The criteria for if a function can be split may vary by target.
2195 virtual bool isFunctionSafeToSplit(const MachineFunction &MF) const;
2196
2197 /// Return true if the MachineBasicBlock can safely be split to the cold
2198 /// section. On AArch64, certain instructions may cause a block to be unsafe
2199 /// to split to the cold section.
2200 virtual bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const {
2201 return true;
2202 }
2203
2204 /// Produce the expression describing the \p MI loading a value into
2205 /// the physical register \p Reg. This hook should only be used with
2206 /// \p MIs belonging to VReg-less functions.
2207 virtual std::optional<ParamLoadedValue>
2209
2210 /// Given the generic extension instruction \p ExtMI, returns true if this
2211 /// extension is a likely candidate for being folded into an another
2212 /// instruction.
2214 MachineRegisterInfo &MRI) const {
2215 return false;
2216 }
2217
2218 /// Return MIR formatter to format/parse MIR operands. Target can override
2219 /// this virtual function and return target specific MIR formatter.
2220 virtual const MIRFormatter *getMIRFormatter() const {
2221 if (!Formatter)
2222 Formatter = std::make_unique<MIRFormatter>();
2223 return Formatter.get();
2224 }
2225
2226 /// Returns the target-specific default value for tail duplication.
2227 /// This value will be used if the tail-dup-placement-threshold argument is
2228 /// not provided.
2229 virtual unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const {
2230 return OptLevel >= CodeGenOptLevel::Aggressive ? 4 : 2;
2231 }
2232
2233 /// Returns the target-specific default value for tail merging.
2234 /// This value will be used if the tail-merge-size argument is not provided.
2235 virtual unsigned getTailMergeSize(const MachineFunction &MF) const {
2236 return 3;
2237 }
2238
2239 /// Returns the callee operand from the given \p MI.
2240 virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const {
2241 return MI.getOperand(0);
2242 }
2243
2244 /// Return the uniformity behavior of the given instruction.
2245 virtual InstructionUniformity
2248 }
2249
2250 /// Returns true if the given \p MI defines a TargetIndex operand that can be
2251 /// tracked by their offset, can have values, and can have debug info
2252 /// associated with it. If so, sets \p Index and \p Offset of the target index
2253 /// operand.
2255 int64_t &Offset) const {
2256 return false;
2257 }
2258
2259 // Get the call frame size just before MI.
2260 unsigned getCallFrameSizeAt(MachineInstr &MI) const;
2261
2262 /// Fills in the necessary MachineOperands to refer to a frame index.
2263 /// The best way to understand this is to print `asm(""::"m"(x));` after
2264 /// finalize-isel. Example:
2265 /// INLINEASM ... 262190 /* mem:m */, %stack.0.x.addr, 1, $noreg, 0, $noreg
2266 /// we would add placeholders for: ^ ^ ^ ^
2268 int FI) const {
2269 llvm_unreachable("unknown number of operands necessary");
2270 }
2271
2272 /// Gets the opcode for the Pseudo Instruction used to initialize
2273 /// the undef value. If no Instruction is available, this will
2274 /// fail compilation.
2275 virtual unsigned getUndefInitOpcode(unsigned RegClassID) const {
2276 (void)RegClassID;
2277
2278 llvm_unreachable("Unexpected register class.");
2279 }
2280
2281private:
2282 mutable std::unique_ptr<MIRFormatter> Formatter;
2283 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
2284 unsigned CatchRetOpcode;
2285 unsigned ReturnOpcode;
2286};
2287
2288/// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
2291
2293 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
2294 RegInfo::getEmptyKey());
2295 }
2296
2298 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
2299 RegInfo::getTombstoneKey());
2300 }
2301
2302 /// Reuse getHashValue implementation from
2303 /// std::pair<unsigned, unsigned>.
2304 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
2305 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2306 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
2307 }
2308
2311 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
2312 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
2313 }
2314};
2315
2316} // end namespace llvm
2317
2318#endif // LLVM_CODEGEN_TARGETINSTRINFO_H
unsigned const MachineRegisterInfo * MRI
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
SmallVector< int16_t, MAX_SRC_OPERANDS_NUM > OperandIndices
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file defines DenseMapInfo traits for DenseMap.
This file defines the DenseMap class.
uint64_t Size
IRTranslator LLVM IR MI
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Machine Check Debug Module
Contains all data structures shared between the outliner implemented in MachineOutliner....
unsigned const TargetRegisterInfo * TRI
unsigned Reg
#define P(N)
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Value * RHS
Value * LHS
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:747
This class represents an Operation in the Expression.
A debug info location.
Definition: DebugLoc.h:33
Itinerary data supplied by a subtarget to be used by a target.
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:32
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:940
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:950
This class contains meta information specific to a module.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
static MachineOperand CreateImm(int64_t Val)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
Represents one node in the SelectionDAG.
This class represents the scheduled code.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:226
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:347
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:587
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1210
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
This class builds the dependence graph for the instructions in a loop, and attempts to schedule the i...
Object returned by analyzeLoopForPipelining.
virtual bool isMVEExpanderSupported()
Return true if the target can expand pipelined schedule with modulo variable expansion.
virtual void disposed()=0
Called when the loop is being removed.
virtual void createRemainingIterationsGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, DenseMap< MachineInstr *, MachineInstr * > &LastStage0Insts)
Create a condition to determine if the remaining trip count for a phase is greater than TC.
virtual void adjustTripCount(int TripCountAdjust)=0
Modify the loop such that the trip count is OriginalTC + TripCountAdjust.
virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const =0
Return true if the given instruction should not be pipelined and should be ignored.
virtual void setPreheader(MachineBasicBlock *NewPreheader)=0
Called when the loop's preheader has been modified to NewPreheader.
virtual bool shouldUseSchedule(SwingSchedulerDAG &SSD, SMSchedule &SMS)
Return true if the proposed schedule should used.
virtual std::optional< bool > createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond)=0
Create a condition to determine if the trip count of the loop is greater than TC, where TC is always ...
TargetInstrInfo - Interface to description of machine instruction set.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual SmallVector< std::pair< MachineBasicBlock::iterator, MachineBasicBlock::iterator > > getOutlinableRanges(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook which partitions MBB into outlinable ranges for instruction mapping purposes.
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
virtual bool isBasicBlockPrologue(const MachineInstr &MI, Register Reg=Register()) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
virtual std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
virtual bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
virtual bool canPredicatePredicatedInstr(const MachineInstr &MI) const
Assumes the instruction is already predicated and returns true if the instruction can be predicated a...
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don't consume any machine resources in their current form.
virtual void buildClearRegister(Register Reg, MachineBasicBlock &MBB, MachineBasicBlock::iterator Iter, DebugLoc &DL, bool AllowSideEffects=true) const
Insert an architecture-specific instruction to clear a register.
virtual void getFrameIndexOperands(SmallVectorImpl< MachineOperand > &Ops, int FI) const
Fills in the necessary MachineOperands to refer to a frame index.
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const
Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate f...
virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, MachineCycleInfo *CI) const
virtual std::optional< DestSourcePair > isCopyLikeInstrImpl(const MachineInstr &MI) const
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
bool isTriviallyReMaterializable(const MachineInstr &MI) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects and requ...
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const
Load the specified register of the given register class from the specified stack frame index.
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
virtual void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const
Return true when \P Opcode1 or its inversion is equal to \P Opcode2.
virtual outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const
Target-dependent implementation for getOutliningTypeImpl.
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
outliner::InstrType getOutliningType(const MachineModuleInfo &MMI, MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MIT should be outlined.
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true,...
virtual bool isThroughputPattern(unsigned Pattern) const
Return true when a code sequence can improve throughput.
virtual bool canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg, const MachineInstr &AddrI, ExtAddrMode &AM) const
Check if it's possible and beneficial to fold the addressing computation AddrI into the addressing mo...
virtual const MIRFormatter * getMIRFormatter() const
Return MIR formatter to format/parse MIR operands.
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...
virtual bool shouldReduceRegisterPressure(const MachineBasicBlock *MBB, const RegisterClassInfo *RegClassInfo) const
Return true if target supports reassociation of instructions in machine combiner pass to reduce regis...
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
bool isFullCopyInstr(const MachineInstr &MI) const
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const
Store the specified register of the given register class to the specified stack frame index.
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
virtual void mergeOutliningCandidateAttributes(Function &F, std::vector< outliner::Candidate > &Candidates) const
Optional target hook to create the LLVM IR attributes for the outlined function.
virtual bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const
Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value.
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
virtual void finalizeInsInstrs(MachineInstr &Root, unsigned &Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs) const
Fix up the placeholder we may add in genAlternativeCodeSequence().
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of 'Reg' and a use in the current loop.
bool isUnspillableTerminator(const MachineInstr *MI) const
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTer...
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
virtual int getExtendResourceLenLimit() const
The limit on resource length extension we accept in MachineCombiner Pass.
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true,...
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const
Sometimes, it is possible for the target to tell, even without aliasing information,...
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
unsigned getReturnOpcode() const
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
virtual void genAlternativeCodeSequence(MachineInstr &Root, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
virtual std::optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
void lowerCopy(MachineInstr *MI, const TargetRegisterInfo *TRI) const
This function defines the logic to lower COPY instruction to target specific instruction(s).
virtual Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
virtual bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, int64_t Offset1, bool OffsetIsScalable1, ArrayRef< const MachineOperand * > BaseOps2, int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize, unsigned NumBytes) const
Returns true if the two given memory operations should be scheduled adjacent.
virtual unsigned getLiveRangeSplitOpcode(Register Reg, const MachineFunction &MF) const
Allows targets to use appropriate copy instruction while spilitting live range of a register in regis...
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient.
virtual unsigned getMemOperandAACheckLimit() const
Return the maximal number of alias checks on memory operands.
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
virtual bool isMBBSafeToSplitToCold(const MachineBasicBlock &MBB) const
Return true if the MachineBasicBlock can safely be split to the cold section.
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
virtual std::optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const
Target dependent implementation to get the values constituting the address MachineInstr that is acces...
virtual std::optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const
Target-dependent implementation for IsCopyInstr.
virtual MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
virtual bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const
Returns true if MI is an instruction that defines Reg to have a constant value and the value is recor...
static bool isGenericOpcode(unsigned Opc)
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
std::optional< DestSourcePair > isCopyLikeInstr(const MachineInstr &MI) const
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< unsigned > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
virtual MCInst getNop() const
Return the noop instruction to use for a noop.
unsigned getCallFrameSizeAt(MachineInstr &MI) const
virtual Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
virtual Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
std::pair< unsigned, unsigned > getReassociationOpcodes(unsigned Pattern, const MachineInstr &Root, const MachineInstr &Prev) const
Reassociation of some instructions requires inverse operations (e.g.
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
virtual bool optimizeCondBranch(MachineInstr &MI) const
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understood.
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
unsigned getCatchReturnOpcode() const
virtual void getReassociateOperandIndices(const MachineInstr &Root, unsigned Pattern, std::array< unsigned, 5 > &OperandIndices) const
The returned array encodes the operand index for each parameter because the operands may be commuted;...
virtual unsigned getTailMergeSize(const MachineFunction &MF) const
Returns the target-specific default value for tail merging.
virtual InstructionUniformity getInstructionUniformity(const MachineInstr &MI) const
Return the uniformity behavior of the given instruction.
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
virtual const MachineOperand & getCalleeOperand(const MachineInstr &MI) const
Returns the callee operand from the given MI.
virtual Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
virtual bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
virtual std::optional< unsigned > getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual int getJumpTableIndex(const MachineInstr &MI) const
Return an index for MachineJumpTableInfo if insn is an indirect jump using a jump table,...
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst, bool Invert=false) const
Return true when \P Inst is both associative and commutative.
virtual bool isExplicitTargetIndexDef(const MachineInstr &MI, int &Index, int64_t &Offset) const
Returns true if the given MI defines a TargetIndex operand that can be tracked by their offset,...
virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part ...
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
virtual MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, outliner::Candidate &C) const
Insert a call to an outlined function into the program.
virtual std::optional< unsigned > getInverseOpcode(unsigned Opcode) const
Return the inverse operation opcode if it exists for \P Opcode (e.g.
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
Insert noops into the instruction stream at the specified point.
unsigned getCallFrameDestroyOpcode() const
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
TargetInstrInfo(const TargetInstrInfo &)=delete
virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const
Return an estimate for the code size reduction (in bytes) which will be caused by removing the given ...
virtual ~TargetInstrInfo()
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const
Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.
virtual bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const
When calculate the latency of the root instruction, accumulate the latency of the sequence to the roo...
std::optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
virtual unsigned getPredicationCost(const MachineInstr &MI) const
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
virtual MachineInstr * convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, LiveIntervals *LIS) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
virtual CombinerObjective getCombinerObjective(unsigned Pattern) const
Return the objective of a combiner pattern.
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it's safe to move a machine instruction that defines the specified register class.
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
virtual bool isFunctionSafeToSplit(const MachineFunction &MF) const
Return true if the function is a viable candidate for machine function splitting.
virtual MachineTraceStrategy getMachineCombinerTraceStrategy() const
Return a strategy that MachineCombiner must use when creating traces.
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
virtual std::optional< outliner::OutlinedFunction > getOutliningCandidateInfo(const MachineModuleInfo &MMI, std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const
Return true if the given terminator MI is not expected to spill.
virtual std::optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a register,...
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, unsigned Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, ArrayRef< unsigned > OperandIndices, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
static bool isGenericAtomicRMWOpcode(unsigned Opc)
virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const
Returns true if the target has a preference on the operands order of the given machine instruction.
static const unsigned CommuteAnyOperandIndex
virtual bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
virtual MachineInstr * emitLdStWithAddr(MachineInstr &MemI, const ExtAddrMode &AM) const
Emit a load/store instruction with the same value register as MemI, but using the address from AM.
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
virtual bool shouldHoist(const MachineInstr &MI, const MachineLoop *FromLoop) const
Return false if the instruction should not be hoisted by MachineLICM.
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
virtual unsigned getTailDuplicateSize(CodeGenOptLevel OptLevel) const
Returns the target-specific default value for tail duplication.
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
virtual Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
virtual unsigned getUndefInitOpcode(unsigned RegClassID) const
Gets the opcode for the Pseudo Instruction used to initialize the undef value.
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing ph...
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it's legal to split the given basic block at the specified instruction (i....
virtual Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Provide an instruction scheduling machine model to CodeGen passes.
TargetSubtargetInfo - Generic base class for all target subtargets.
LLVM Value Representation.
Definition: Value.h:74
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Tail
Attemps to make calls as fast as possible while guaranteeing that tail call optimization can always b...
Definition: CallingConv.h:76
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
InstrType
Represents how an instruction should be mapped by the outliner.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:480
MachineTraceStrategy
Strategies for selecting traces.
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
CombinerObjective
The combiner's goal may differ based on which pattern it is attempting to optimize.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
InstructionUniformity
Enum describing how instructions behave with respect to uniformity and divergence,...
Definition: Uniformity.h:18
@ Default
The result values are uniform if and only if all operands are uniform.
#define N
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
static TargetInstrInfo::RegSubRegPair getEmptyKey()
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
An information struct used to provide DenseMap with the various necessary components for a given valu...
Definition: DenseMapInfo.h:52
const MachineOperand * Source
DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
const MachineOperand * Destination
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
ExtAddrMode()=default
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:253
Used to describe a register and immediate addition.
RegImmPair(Register Reg, int64_t Imm)
Represents a predicate at the MachineFunction level.
bool SingleUseCondition
SingleUseCondition is true if ConditionDef is dead except for the branch(es) at the end of the basic ...
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
RegSubRegPairAndIdx(Register Reg=Register(), unsigned SubReg=0, unsigned SubIdx=0)
A pair composed of a register and a sub-register index.
bool operator==(const RegSubRegPair &P) const
RegSubRegPair(Register Reg=Register(), unsigned SubReg=0)
bool operator!=(const RegSubRegPair &P) const
An individual sequence of instructions to be replaced with a call to an outlined function.
The information necessary to create an outlined function for some class of candidate.