LLVM  14.0.0git
TargetInstrInfo.h
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1 //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file describes the target machine instruction set to the code generator.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_CODEGEN_TARGETINSTRINFO_H
14 #define LLVM_CODEGEN_TARGETINSTRINFO_H
15 
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/None.h"
30 #include "llvm/MC/MCInstrInfo.h"
33 #include <cassert>
34 #include <cstddef>
35 #include <cstdint>
36 #include <utility>
37 #include <vector>
38 
39 namespace llvm {
40 
41 class AAResults;
42 class DFAPacketizer;
43 class InstrItineraryData;
44 class LiveIntervals;
45 class LiveVariables;
46 class MachineLoop;
47 class MachineMemOperand;
48 class MachineRegisterInfo;
49 class MCAsmInfo;
50 class MCInst;
51 struct MCSchedModel;
52 class Module;
53 class ScheduleDAG;
54 class ScheduleDAGMI;
55 class ScheduleHazardRecognizer;
56 class SDNode;
57 class SelectionDAG;
58 class RegScavenger;
59 class TargetRegisterClass;
60 class TargetRegisterInfo;
61 class TargetSchedModel;
62 class TargetSubtargetInfo;
63 
64 template <class T> class SmallVectorImpl;
65 
66 using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>;
67 
71 
72  DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
73  : Destination(&Dest), Source(&Src) {}
74 };
75 
76 /// Used to describe a register and immediate addition.
77 struct RegImmPair {
79  int64_t Imm;
80 
81  RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {}
82 };
83 
84 /// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
85 /// It holds the register values, the scale value and the displacement.
86 struct ExtAddrMode {
89  int64_t Scale;
90  int64_t Displacement;
91 };
92 
93 //---------------------------------------------------------------------------
94 ///
95 /// TargetInstrInfo - Interface to description of machine instruction set
96 ///
97 class TargetInstrInfo : public MCInstrInfo {
98 public:
99  TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
100  unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
101  : CallFrameSetupOpcode(CFSetupOpcode),
102  CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
103  ReturnOpcode(ReturnOpcode) {}
104  TargetInstrInfo(const TargetInstrInfo &) = delete;
105  TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
106  virtual ~TargetInstrInfo();
107 
108  static bool isGenericOpcode(unsigned Opc) {
109  return Opc <= TargetOpcode::GENERIC_OP_END;
110  }
111 
112  /// Given a machine instruction descriptor, returns the register
113  /// class constraint for OpNum, or NULL.
114  virtual
115  const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
116  const TargetRegisterInfo *TRI,
117  const MachineFunction &MF) const;
118 
119  /// Return true if the instruction is trivially rematerializable, meaning it
120  /// has no side effects. Uses of constants and unallocatable physical
121  /// registers are always trivial to rematerialize so that the instructions
122  /// result is independent of the place in the function. Uses of virtual
123  /// registers are allowed but it is caller's responsility to ensure these
124  /// operands are valid at the point the instruction is beeing moved.
126  AAResults *AA = nullptr) const {
127  return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
128  (MI.getDesc().isRematerializable() &&
130  isReallyTriviallyReMaterializableGeneric(MI, AA)));
131  }
132 
133  /// Given \p MO is a PhysReg use return if it can be ignored for the purpose
134  /// of instruction rematerialization.
135  virtual bool isIgnorableUse(const MachineOperand &MO) const {
136  return false;
137  }
138 
139 protected:
140  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
141  /// set, this hook lets the target specify whether the instruction is actually
142  /// trivially rematerializable, taking into consideration its operands. This
143  /// predicate must return false if the instruction has any side effects other
144  /// than producing a value.
145  /// Requirements must be check as stated in isTriviallyReMaterializable() .
147  AAResults *AA) const {
148  return false;
149  }
150 
151  /// This method commutes the operands of the given machine instruction MI.
152  /// The operands to be commuted are specified by their indices OpIdx1 and
153  /// OpIdx2.
154  ///
155  /// If a target has any instructions that are commutable but require
156  /// converting to different instructions or making non-trivial changes
157  /// to commute them, this method can be overloaded to do that.
158  /// The default implementation simply swaps the commutable operands.
159  ///
160  /// If NewMI is false, MI is modified in place and returned; otherwise, a
161  /// new machine instruction is created and returned.
162  ///
163  /// Do not call this method for a non-commutable instruction.
164  /// Even though the instruction is commutable, the method may still
165  /// fail to commute the operands, null pointer is returned in such cases.
166  virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
167  unsigned OpIdx1,
168  unsigned OpIdx2) const;
169 
170  /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
171  /// operand indices to (ResultIdx1, ResultIdx2).
172  /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
173  /// predefined to some indices or be undefined (designated by the special
174  /// value 'CommuteAnyOperandIndex').
175  /// The predefined result indices cannot be re-defined.
176  /// The function returns true iff after the result pair redefinition
177  /// the fixed result pair is equal to or equivalent to the source pair of
178  /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
179  /// the pairs (x,y) and (y,x) are equivalent.
180  static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
181  unsigned CommutableOpIdx1,
182  unsigned CommutableOpIdx2);
183 
184 private:
185  /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
186  /// set and the target hook isReallyTriviallyReMaterializable returns false,
187  /// this function does target-independent tests to determine if the
188  /// instruction is really trivially rematerializable.
189  bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
190  AAResults *AA) const;
191 
192 public:
193  /// These methods return the opcode of the frame setup/destroy instructions
194  /// if they exist (-1 otherwise). Some targets use pseudo instructions in
195  /// order to abstract away the difference between operating with a frame
196  /// pointer and operating without, through the use of these two instructions.
197  ///
198  unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
199  unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
200 
201  /// Returns true if the argument is a frame pseudo instruction.
202  bool isFrameInstr(const MachineInstr &I) const {
203  return I.getOpcode() == getCallFrameSetupOpcode() ||
204  I.getOpcode() == getCallFrameDestroyOpcode();
205  }
206 
207  /// Returns true if the argument is a frame setup pseudo instruction.
208  bool isFrameSetup(const MachineInstr &I) const {
209  return I.getOpcode() == getCallFrameSetupOpcode();
210  }
211 
212  /// Returns size of the frame associated with the given frame instruction.
213  /// For frame setup instruction this is frame that is set up space set up
214  /// after the instruction. For frame destroy instruction this is the frame
215  /// freed by the caller.
216  /// Note, in some cases a call frame (or a part of it) may be prepared prior
217  /// to the frame setup instruction. It occurs in the calls that involve
218  /// inalloca arguments. This function reports only the size of the frame part
219  /// that is set up between the frame setup and destroy pseudo instructions.
220  int64_t getFrameSize(const MachineInstr &I) const {
221  assert(isFrameInstr(I) && "Not a frame instruction");
222  assert(I.getOperand(0).getImm() >= 0);
223  return I.getOperand(0).getImm();
224  }
225 
226  /// Returns the total frame size, which is made up of the space set up inside
227  /// the pair of frame start-stop instructions and the space that is set up
228  /// prior to the pair.
229  int64_t getFrameTotalSize(const MachineInstr &I) const {
230  if (isFrameSetup(I)) {
231  assert(I.getOperand(1).getImm() >= 0 &&
232  "Frame size must not be negative");
233  return getFrameSize(I) + I.getOperand(1).getImm();
234  }
235  return getFrameSize(I);
236  }
237 
238  unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
239  unsigned getReturnOpcode() const { return ReturnOpcode; }
240 
241  /// Returns the actual stack pointer adjustment made by an instruction
242  /// as part of a call sequence. By default, only call frame setup/destroy
243  /// instructions adjust the stack, but targets may want to override this
244  /// to enable more fine-grained adjustment, or adjust by a different value.
245  virtual int getSPAdjust(const MachineInstr &MI) const;
246 
247  /// Return true if the instruction is a "coalescable" extension instruction.
248  /// That is, it's like a copy where it's legal for the source to overlap the
249  /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
250  /// expected the pre-extension value is available as a subreg of the result
251  /// register. This also returns the sub-register index in SubIdx.
252  virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
253  Register &DstReg, unsigned &SubIdx) const {
254  return false;
255  }
256 
257  /// If the specified machine instruction is a direct
258  /// load from a stack slot, return the virtual or physical register number of
259  /// the destination along with the FrameIndex of the loaded stack slot. If
260  /// not, return 0. This predicate must return 0 if the instruction has
261  /// any side effects other than loading from the stack slot.
262  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
263  int &FrameIndex) const {
264  return 0;
265  }
266 
267  /// Optional extension of isLoadFromStackSlot that returns the number of
268  /// bytes loaded from the stack. This must be implemented if a backend
269  /// supports partial stack slot spills/loads to further disambiguate
270  /// what the load does.
271  virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
272  int &FrameIndex,
273  unsigned &MemBytes) const {
274  MemBytes = 0;
276  }
277 
278  /// Check for post-frame ptr elimination stack locations as well.
279  /// This uses a heuristic so it isn't reliable for correctness.
280  virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
281  int &FrameIndex) const {
282  return 0;
283  }
284 
285  /// If the specified machine instruction has a load from a stack slot,
286  /// return true along with the FrameIndices of the loaded stack slot and the
287  /// machine mem operands containing the reference.
288  /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
289  /// any instructions that loads from the stack. This is just a hint, as some
290  /// cases may be missed.
291  virtual bool hasLoadFromStackSlot(
292  const MachineInstr &MI,
294 
295  /// If the specified machine instruction is a direct
296  /// store to a stack slot, return the virtual or physical register number of
297  /// the source reg along with the FrameIndex of the loaded stack slot. If
298  /// not, return 0. This predicate must return 0 if the instruction has
299  /// any side effects other than storing to the stack slot.
300  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
301  int &FrameIndex) const {
302  return 0;
303  }
304 
305  /// Optional extension of isStoreToStackSlot that returns the number of
306  /// bytes stored to the stack. This must be implemented if a backend
307  /// supports partial stack slot spills/loads to further disambiguate
308  /// what the store does.
309  virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
310  int &FrameIndex,
311  unsigned &MemBytes) const {
312  MemBytes = 0;
314  }
315 
316  /// Check for post-frame ptr elimination stack locations as well.
317  /// This uses a heuristic, so it isn't reliable for correctness.
318  virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
319  int &FrameIndex) const {
320  return 0;
321  }
322 
323  /// If the specified machine instruction has a store to a stack slot,
324  /// return true along with the FrameIndices of the loaded stack slot and the
325  /// machine mem operands containing the reference.
326  /// If not, return false. Unlike isStoreToStackSlot,
327  /// this returns true for any instructions that stores to the
328  /// stack. This is just a hint, as some cases may be missed.
329  virtual bool hasStoreToStackSlot(
330  const MachineInstr &MI,
332 
333  /// Return true if the specified machine instruction
334  /// is a copy of one stack slot to another and has no other effect.
335  /// Provide the identity of the two frame indices.
336  virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
337  int &SrcFrameIndex) const {
338  return false;
339  }
340 
341  /// Compute the size in bytes and offset within a stack slot of a spilled
342  /// register or subregister.
343  ///
344  /// \param [out] Size in bytes of the spilled value.
345  /// \param [out] Offset in bytes within the stack slot.
346  /// \returns true if both Size and Offset are successfully computed.
347  ///
348  /// Not all subregisters have computable spill slots. For example,
349  /// subregisters registers may not be byte-sized, and a pair of discontiguous
350  /// subregisters has no single offset.
351  ///
352  /// Targets with nontrivial bigendian implementations may need to override
353  /// this, particularly to support spilled vector registers.
354  virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
355  unsigned &Size, unsigned &Offset,
356  const MachineFunction &MF) const;
357 
358  /// Return true if the given instruction is terminator that is unspillable,
359  /// according to isUnspillableTerminatorImpl.
361  return MI->isTerminator() && isUnspillableTerminatorImpl(MI);
362  }
363 
364  /// Returns the size in bytes of the specified MachineInstr, or ~0U
365  /// when this function is not implemented by a target.
366  virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
367  return ~0U;
368  }
369 
370  /// Return true if the instruction is as cheap as a move instruction.
371  ///
372  /// Targets for different archs need to override this, and different
373  /// micro-architectures can also be finely tuned inside.
374  virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
375  return MI.isAsCheapAsAMove();
376  }
377 
378  /// Return true if the instruction should be sunk by MachineSink.
379  ///
380  /// MachineSink determines on its own whether the instruction is safe to sink;
381  /// this gives the target a hook to override the default behavior with regards
382  /// to which instructions should be sunk.
383  virtual bool shouldSink(const MachineInstr &MI) const { return true; }
384 
385  /// Re-issue the specified 'original' instruction at the
386  /// specific location targeting a new destination register.
387  /// The register in Orig->getOperand(0).getReg() will be substituted by
388  /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
389  /// SubIdx.
390  virtual void reMaterialize(MachineBasicBlock &MBB,
392  unsigned SubIdx, const MachineInstr &Orig,
393  const TargetRegisterInfo &TRI) const;
394 
395  /// Clones instruction or the whole instruction bundle \p Orig and
396  /// insert into \p MBB before \p InsertBefore. The target may update operands
397  /// that are required to be unique.
398  ///
399  /// \p Orig must not return true for MachineInstr::isNotDuplicable().
401  MachineBasicBlock::iterator InsertBefore,
402  const MachineInstr &Orig) const;
403 
404  /// This method must be implemented by targets that
405  /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
406  /// may be able to convert a two-address instruction into one or more true
407  /// three-address instructions on demand. This allows the X86 target (for
408  /// example) to convert ADD and SHL instructions into LEA instructions if they
409  /// would require register copies due to two-addressness.
410  ///
411  /// This method returns a null pointer if the transformation cannot be
412  /// performed, otherwise it returns the last new instruction.
413  ///
415  MachineInstr &MI,
416  LiveVariables *LV) const {
417  return nullptr;
418  }
419 
420  // This constant can be used as an input value of operand index passed to
421  // the method findCommutedOpIndices() to tell the method that the
422  // corresponding operand index is not pre-defined and that the method
423  // can pick any commutable operand.
424  static const unsigned CommuteAnyOperandIndex = ~0U;
425 
426  /// This method commutes the operands of the given machine instruction MI.
427  ///
428  /// The operands to be commuted are specified by their indices OpIdx1 and
429  /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
430  /// 'CommuteAnyOperandIndex', which means that the method is free to choose
431  /// any arbitrarily chosen commutable operand. If both arguments are set to
432  /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
433  /// operands; then commutes them if such operands could be found.
434  ///
435  /// If NewMI is false, MI is modified in place and returned; otherwise, a
436  /// new machine instruction is created and returned.
437  ///
438  /// Do not call this method for a non-commutable instruction or
439  /// for non-commuable operands.
440  /// Even though the instruction is commutable, the method may still
441  /// fail to commute the operands, null pointer is returned in such cases.
442  MachineInstr *
443  commuteInstruction(MachineInstr &MI, bool NewMI = false,
444  unsigned OpIdx1 = CommuteAnyOperandIndex,
445  unsigned OpIdx2 = CommuteAnyOperandIndex) const;
446 
447  /// Returns true iff the routine could find two commutable operands in the
448  /// given machine instruction.
449  /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
450  /// If any of the INPUT values is set to the special value
451  /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
452  /// operand, then returns its index in the corresponding argument.
453  /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
454  /// looks for 2 commutable operands.
455  /// If INPUT values refer to some operands of MI, then the method simply
456  /// returns true if the corresponding operands are commutable and returns
457  /// false otherwise.
458  ///
459  /// For example, calling this method this way:
460  /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
461  /// findCommutedOpIndices(MI, Op1, Op2);
462  /// can be interpreted as a query asking to find an operand that would be
463  /// commutable with the operand#1.
464  virtual bool findCommutedOpIndices(const MachineInstr &MI,
465  unsigned &SrcOpIdx1,
466  unsigned &SrcOpIdx2) const;
467 
468  /// Returns true if the target has a preference on the operands order of
469  /// the given machine instruction. And specify if \p Commute is required to
470  /// get the desired operands order.
471  virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const {
472  return false;
473  }
474 
475  /// A pair composed of a register and a sub-register index.
476  /// Used to give some type checking when modeling Reg:SubReg.
477  struct RegSubRegPair {
479  unsigned SubReg;
480 
482  : Reg(Reg), SubReg(SubReg) {}
483 
484  bool operator==(const RegSubRegPair& P) const {
485  return Reg == P.Reg && SubReg == P.SubReg;
486  }
487  bool operator!=(const RegSubRegPair& P) const {
488  return !(*this == P);
489  }
490  };
491 
492  /// A pair composed of a pair of a register and a sub-register index,
493  /// and another sub-register index.
494  /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
496  unsigned SubIdx;
497 
499  unsigned SubIdx = 0)
501  };
502 
503  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
504  /// and \p DefIdx.
505  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
506  /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
507  /// flag are not added to this list.
508  /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
509  /// two elements:
510  /// - %1:sub1, sub0
511  /// - %2<:0>, sub1
512  ///
513  /// \returns true if it is possible to build such an input sequence
514  /// with the pair \p MI, \p DefIdx. False otherwise.
515  ///
516  /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
517  ///
518  /// \note The generic implementation does not provide any support for
519  /// MI.isRegSequenceLike(). In other words, one has to override
520  /// getRegSequenceLikeInputs for target specific instructions.
521  bool
522  getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
523  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
524 
525  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
526  /// and \p DefIdx.
527  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
528  /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
529  /// - %1:sub1, sub0
530  ///
531  /// \returns true if it is possible to build such an input sequence
532  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
533  /// False otherwise.
534  ///
535  /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
536  ///
537  /// \note The generic implementation does not provide any support for
538  /// MI.isExtractSubregLike(). In other words, one has to override
539  /// getExtractSubregLikeInputs for target specific instructions.
540  bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
541  RegSubRegPairAndIdx &InputReg) const;
542 
543  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
544  /// and \p DefIdx.
545  /// \p [out] BaseReg and \p [out] InsertedReg contain
546  /// the equivalent inputs of INSERT_SUBREG.
547  /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
548  /// - BaseReg: %0:sub0
549  /// - InsertedReg: %1:sub1, sub3
550  ///
551  /// \returns true if it is possible to build such an input sequence
552  /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
553  /// False otherwise.
554  ///
555  /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
556  ///
557  /// \note The generic implementation does not provide any support for
558  /// MI.isInsertSubregLike(). In other words, one has to override
559  /// getInsertSubregLikeInputs for target specific instructions.
560  bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
561  RegSubRegPair &BaseReg,
562  RegSubRegPairAndIdx &InsertedReg) const;
563 
564  /// Return true if two machine instructions would produce identical values.
565  /// By default, this is only true when the two instructions
566  /// are deemed identical except for defs. If this function is called when the
567  /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
568  /// aggressive checks.
569  virtual bool produceSameValue(const MachineInstr &MI0,
570  const MachineInstr &MI1,
571  const MachineRegisterInfo *MRI = nullptr) const;
572 
573  /// \returns true if a branch from an instruction with opcode \p BranchOpc
574  /// bytes is capable of jumping to a position \p BrOffset bytes away.
575  virtual bool isBranchOffsetInRange(unsigned BranchOpc,
576  int64_t BrOffset) const {
577  llvm_unreachable("target did not implement");
578  }
579 
580  /// \returns The block that branch instruction \p MI jumps to.
582  llvm_unreachable("target did not implement");
583  }
584 
585  /// Insert an unconditional indirect branch at the end of \p MBB to \p
586  /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
587  /// the offset of the position to insert the new branch.
588  ///
589  /// \returns The number of bytes added to the block.
591  MachineBasicBlock &NewDestBB,
592  const DebugLoc &DL,
593  int64_t BrOffset = 0,
594  RegScavenger *RS = nullptr) const {
595  llvm_unreachable("target did not implement");
596  }
597 
598  /// Analyze the branching code at the end of MBB, returning
599  /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
600  /// implemented for a target). Upon success, this returns false and returns
601  /// with the following information in various cases:
602  ///
603  /// 1. If this block ends with no branches (it just falls through to its succ)
604  /// just return false, leaving TBB/FBB null.
605  /// 2. If this block ends with only an unconditional branch, it sets TBB to be
606  /// the destination block.
607  /// 3. If this block ends with a conditional branch and it falls through to a
608  /// successor block, it sets TBB to be the branch destination block and a
609  /// list of operands that evaluate the condition. These operands can be
610  /// passed to other TargetInstrInfo methods to create new branches.
611  /// 4. If this block ends with a conditional branch followed by an
612  /// unconditional branch, it returns the 'true' destination in TBB, the
613  /// 'false' destination in FBB, and a list of operands that evaluate the
614  /// condition. These operands can be passed to other TargetInstrInfo
615  /// methods to create new branches.
616  ///
617  /// Note that removeBranch and insertBranch must be implemented to support
618  /// cases where this method returns success.
619  ///
620  /// If AllowModify is true, then this routine is allowed to modify the basic
621  /// block (e.g. delete instructions after the unconditional branch).
622  ///
623  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
624  /// before calling this function.
626  MachineBasicBlock *&FBB,
628  bool AllowModify = false) const {
629  return true;
630  }
631 
632  /// Represents a predicate at the MachineFunction level. The control flow a
633  /// MachineBranchPredicate represents is:
634  ///
635  /// Reg = LHS `Predicate` RHS == ConditionDef
636  /// if Reg then goto TrueDest else goto FalseDest
637  ///
640  PRED_EQ, // True if two values are equal
641  PRED_NE, // True if two values are not equal
642  PRED_INVALID // Sentinel value
643  };
644 
651 
652  /// SingleUseCondition is true if ConditionDef is dead except for the
653  /// branch(es) at the end of the basic block.
654  ///
655  bool SingleUseCondition = false;
656 
657  explicit MachineBranchPredicate() = default;
658  };
659 
660  /// Analyze the branching code at the end of MBB and parse it into the
661  /// MachineBranchPredicate structure if possible. Returns false on success
662  /// and true on failure.
663  ///
664  /// If AllowModify is true, then this routine is allowed to modify the basic
665  /// block (e.g. delete instructions after the unconditional branch).
666  ///
669  bool AllowModify = false) const {
670  return true;
671  }
672 
673  /// Remove the branching code at the end of the specific MBB.
674  /// This is only invoked in cases where analyzeBranch returns success. It
675  /// returns the number of instructions that were removed.
676  /// If \p BytesRemoved is non-null, report the change in code size from the
677  /// removed instructions.
678  virtual unsigned removeBranch(MachineBasicBlock &MBB,
679  int *BytesRemoved = nullptr) const {
680  llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!");
681  }
682 
683  /// Insert branch code into the end of the specified MachineBasicBlock. The
684  /// operands to this method are the same as those returned by analyzeBranch.
685  /// This is only invoked in cases where analyzeBranch returns success. It
686  /// returns the number of instructions inserted. If \p BytesAdded is non-null,
687  /// report the change in code size from the added instructions.
688  ///
689  /// It is also invoked by tail merging to add unconditional branches in
690  /// cases where analyzeBranch doesn't apply because there was no original
691  /// branch to analyze. At least this much must be implemented, else tail
692  /// merging needs to be disabled.
693  ///
694  /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
695  /// before calling this function.
697  MachineBasicBlock *FBB,
699  const DebugLoc &DL,
700  int *BytesAdded = nullptr) const {
701  llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!");
702  }
703 
705  MachineBasicBlock *DestBB,
706  const DebugLoc &DL,
707  int *BytesAdded = nullptr) const {
708  return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
709  BytesAdded);
710  }
711 
712  /// Object returned by analyzeLoopForPipelining. Allows software pipelining
713  /// implementations to query attributes of the loop being pipelined and to
714  /// apply target-specific updates to the loop once pipelining is complete.
716  public:
717  virtual ~PipelinerLoopInfo();
718  /// Return true if the given instruction should not be pipelined and should
719  /// be ignored. An example could be a loop comparison, or induction variable
720  /// update with no users being pipelined.
721  virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;
722 
723  /// Create a condition to determine if the trip count of the loop is greater
724  /// than TC.
725  ///
726  /// If the trip count is statically known to be greater than TC, return
727  /// true. If the trip count is statically known to be not greater than TC,
728  /// return false. Otherwise return nullopt and fill out Cond with the test
729  /// condition.
730  virtual Optional<bool>
733 
734  /// Modify the loop such that the trip count is
735  /// OriginalTC + TripCountAdjust.
736  virtual void adjustTripCount(int TripCountAdjust) = 0;
737 
738  /// Called when the loop's preheader has been modified to NewPreheader.
739  virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;
740 
741  /// Called when the loop is being removed. Any instructions in the preheader
742  /// should be removed.
743  ///
744  /// Once this function is called, no other functions on this object are
745  /// valid; the loop has been removed.
746  virtual void disposed() = 0;
747  };
748 
749  /// Analyze loop L, which must be a single-basic-block loop, and if the
750  /// conditions can be understood enough produce a PipelinerLoopInfo object.
751  virtual std::unique_ptr<PipelinerLoopInfo>
753  return nullptr;
754  }
755 
756  /// Analyze the loop code, return true if it cannot be understood. Upon
757  /// success, this function returns false and returns information about the
758  /// induction variable and compare instruction used at the end.
759  virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
760  MachineInstr *&CmpInst) const {
761  return true;
762  }
763 
764  /// Generate code to reduce the loop iteration by one and check if the loop
765  /// is finished. Return the value/register of the new loop count. We need
766  /// this function when peeling off one or more iterations of a loop. This
767  /// function assumes the nth iteration is peeled first.
769  MachineBasicBlock &PreHeader,
770  MachineInstr *IndVar, MachineInstr &Cmp,
773  unsigned Iter, unsigned MaxIter) const {
774  llvm_unreachable("Target didn't implement ReduceLoopCount");
775  }
776 
777  /// Delete the instruction OldInst and everything after it, replacing it with
778  /// an unconditional branch to NewDest. This is used by the tail merging pass.
780  MachineBasicBlock *NewDest) const;
781 
782  /// Return true if it's legal to split the given basic
783  /// block at the specified instruction (i.e. instruction would be the start
784  /// of a new basic block).
787  return true;
788  }
789 
790  /// Return true if it's profitable to predicate
791  /// instructions with accumulated instruction latency of "NumCycles"
792  /// of the specified basic block, where the probability of the instructions
793  /// being executed is given by Probability, and Confidence is a measure
794  /// of our confidence that it will be properly predicted.
795  virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
796  unsigned ExtraPredCycles,
797  BranchProbability Probability) const {
798  return false;
799  }
800 
801  /// Second variant of isProfitableToIfCvt. This one
802  /// checks for the case where two basic blocks from true and false path
803  /// of a if-then-else (diamond) are predicated on mutually exclusive
804  /// predicates, where the probability of the true path being taken is given
805  /// by Probability, and Confidence is a measure of our confidence that it
806  /// will be properly predicted.
807  virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
808  unsigned ExtraTCycles,
809  MachineBasicBlock &FMBB, unsigned NumFCycles,
810  unsigned ExtraFCycles,
811  BranchProbability Probability) const {
812  return false;
813  }
814 
815  /// Return true if it's profitable for if-converter to duplicate instructions
816  /// of specified accumulated instruction latencies in the specified MBB to
817  /// enable if-conversion.
818  /// The probability of the instructions being executed is given by
819  /// Probability, and Confidence is a measure of our confidence that it
820  /// will be properly predicted.
822  unsigned NumCycles,
823  BranchProbability Probability) const {
824  return false;
825  }
826 
827  /// Return the increase in code size needed to predicate a contiguous run of
828  /// NumInsts instructions.
830  unsigned NumInsts) const {
831  return 0;
832  }
833 
834  /// Return an estimate for the code size reduction (in bytes) which will be
835  /// caused by removing the given branch instruction during if-conversion.
836  virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const {
837  return getInstSizeInBytes(MI);
838  }
839 
840  /// Return true if it's profitable to unpredicate
841  /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
842  /// exclusive predicates.
843  /// e.g.
844  /// subeq r0, r1, #1
845  /// addne r0, r1, #1
846  /// =>
847  /// sub r0, r1, #1
848  /// addne r0, r1, #1
849  ///
850  /// This may be profitable is conditional instructions are always executed.
852  MachineBasicBlock &FMBB) const {
853  return false;
854  }
855 
856  /// Return true if it is possible to insert a select
857  /// instruction that chooses between TrueReg and FalseReg based on the
858  /// condition code in Cond.
859  ///
860  /// When successful, also return the latency in cycles from TrueReg,
861  /// FalseReg, and Cond to the destination register. In most cases, a select
862  /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
863  ///
864  /// Some x86 implementations have 2-cycle cmov instructions.
865  ///
866  /// @param MBB Block where select instruction would be inserted.
867  /// @param Cond Condition returned by analyzeBranch.
868  /// @param DstReg Virtual dest register that the result should write to.
869  /// @param TrueReg Virtual register to select when Cond is true.
870  /// @param FalseReg Virtual register to select when Cond is false.
871  /// @param CondCycles Latency from Cond+Branch to select output.
872  /// @param TrueCycles Latency from TrueReg to select output.
873  /// @param FalseCycles Latency from FalseReg to select output.
874  virtual bool canInsertSelect(const MachineBasicBlock &MBB,
876  Register TrueReg, Register FalseReg,
877  int &CondCycles, int &TrueCycles,
878  int &FalseCycles) const {
879  return false;
880  }
881 
882  /// Insert a select instruction into MBB before I that will copy TrueReg to
883  /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
884  ///
885  /// This function can only be called after canInsertSelect() returned true.
886  /// The condition in Cond comes from analyzeBranch, and it can be assumed
887  /// that the same flags or registers required by Cond are available at the
888  /// insertion point.
889  ///
890  /// @param MBB Block where select instruction should be inserted.
891  /// @param I Insertion point.
892  /// @param DL Source location for debugging.
893  /// @param DstReg Virtual register to be defined by select instruction.
894  /// @param Cond Condition as computed by analyzeBranch.
895  /// @param TrueReg Virtual register to copy when Cond is true.
896  /// @param FalseReg Virtual register to copy when Cons is false.
900  Register TrueReg, Register FalseReg) const {
901  llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
902  }
903 
904  /// Analyze the given select instruction, returning true if
905  /// it cannot be understood. It is assumed that MI->isSelect() is true.
906  ///
907  /// When successful, return the controlling condition and the operands that
908  /// determine the true and false result values.
909  ///
910  /// Result = SELECT Cond, TrueOp, FalseOp
911  ///
912  /// Some targets can optimize select instructions, for example by predicating
913  /// the instruction defining one of the operands. Such targets should set
914  /// Optimizable.
915  ///
916  /// @param MI Select instruction to analyze.
917  /// @param Cond Condition controlling the select.
918  /// @param TrueOp Operand number of the value selected when Cond is true.
919  /// @param FalseOp Operand number of the value selected when Cond is false.
920  /// @param Optimizable Returned as true if MI is optimizable.
921  /// @returns False on success.
922  virtual bool analyzeSelect(const MachineInstr &MI,
924  unsigned &TrueOp, unsigned &FalseOp,
925  bool &Optimizable) const {
926  assert(MI.getDesc().isSelect() && "MI must be a select instruction");
927  return true;
928  }
929 
930  /// Given a select instruction that was understood by
931  /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
932  /// merging it with one of its operands. Returns NULL on failure.
933  ///
934  /// When successful, returns the new select instruction. The client is
935  /// responsible for deleting MI.
936  ///
937  /// If both sides of the select can be optimized, PreferFalse is used to pick
938  /// a side.
939  ///
940  /// @param MI Optimizable select instruction.
941  /// @param NewMIs Set that record all MIs in the basic block up to \p
942  /// MI. Has to be updated with any newly created MI or deleted ones.
943  /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
944  /// @returns Optimized instruction or NULL.
947  bool PreferFalse = false) const {
948  // This function must be implemented if Optimizable is ever set.
949  llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!");
950  }
951 
952  /// Emit instructions to copy a pair of physical registers.
953  ///
954  /// This function should support copies within any legal register class as
955  /// well as any cross-class copies created during instruction selection.
956  ///
957  /// The source and destination registers may overlap, which may require a
958  /// careful implementation when multiple copy instructions are required for
959  /// large registers. See for example the ARM target.
962  MCRegister DestReg, MCRegister SrcReg,
963  bool KillSrc) const {
964  llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
965  }
966 
967  /// Allow targets to tell MachineVerifier whether a specific register
968  /// MachineOperand can be used as part of PC-relative addressing.
969  /// PC-relative addressing modes in many CISC architectures contain
970  /// (non-PC) registers as offsets or scaling values, which inherently
971  /// tags the corresponding MachineOperand with OPERAND_PCREL.
972  ///
973  /// @param MO The MachineOperand in question. MO.isReg() should always
974  /// be true.
975  /// @return Whether this operand is allowed to be used PC-relatively.
976  virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const {
977  return false;
978  }
979 
980 protected:
981  /// Target-dependent implementation for IsCopyInstr.
982  /// If the specific machine instruction is a instruction that moves/copies
983  /// value from one register to another register return destination and source
984  /// registers as machine operands.
987  return None;
988  }
989 
990  /// Return true if the given terminator MI is not expected to spill. This
991  /// sets the live interval as not spillable and adjusts phi node lowering to
992  /// not introduce copies after the terminator. Use with care, these are
993  /// currently used for hardware loop intrinsics in very controlled situations,
994  /// created prior to registry allocation in loops that only have single phi
995  /// users for the terminators value. They may run out of registers if not used
996  /// carefully.
997  virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const {
998  return false;
999  }
1000 
1001 public:
1002  /// If the specific machine instruction is a instruction that moves/copies
1003  /// value from one register to another register return destination and source
1004  /// registers as machine operands.
1005  /// For COPY-instruction the method naturally returns destination and source
1006  /// registers as machine operands, for all other instructions the method calls
1007  /// target-dependent implementation.
1009  if (MI.isCopy()) {
1010  return DestSourcePair{MI.getOperand(0), MI.getOperand(1)};
1011  }
1012  return isCopyInstrImpl(MI);
1013  }
1014 
1015  /// If the specific machine instruction is an instruction that adds an
1016  /// immediate value and a physical register, and stores the result in
1017  /// the given physical register \c Reg, return a pair of the source
1018  /// register and the offset which has been added.
1020  Register Reg) const {
1021  return None;
1022  }
1023 
1024  /// Returns true if MI is an instruction that defines Reg to have a constant
1025  /// value and the value is recorded in ImmVal. The ImmVal is a result that
1026  /// should be interpreted as modulo size of Reg.
1028  const Register Reg,
1029  int64_t &ImmVal) const {
1030  return false;
1031  }
1032 
1033  /// Store the specified register of the given register class to the specified
1034  /// stack frame index. The store instruction is to be added to the given
1035  /// machine basic block before the specified machine instruction. If isKill
1036  /// is true, the register operand is the last use and must be marked kill.
1039  Register SrcReg, bool isKill, int FrameIndex,
1040  const TargetRegisterClass *RC,
1041  const TargetRegisterInfo *TRI) const {
1042  llvm_unreachable("Target didn't implement "
1043  "TargetInstrInfo::storeRegToStackSlot!");
1044  }
1045 
1046  /// Load the specified register of the given register class from the specified
1047  /// stack frame index. The load instruction is to be added to the given
1048  /// machine basic block before the specified machine instruction.
1051  Register DestReg, int FrameIndex,
1052  const TargetRegisterClass *RC,
1053  const TargetRegisterInfo *TRI) const {
1054  llvm_unreachable("Target didn't implement "
1055  "TargetInstrInfo::loadRegFromStackSlot!");
1056  }
1057 
1058  /// This function is called for all pseudo instructions
1059  /// that remain after register allocation. Many pseudo instructions are
1060  /// created to help register allocation. This is the place to convert them
1061  /// into real instructions. The target can edit MI in place, or it can insert
1062  /// new instructions and erase MI. The function should return true if
1063  /// anything was changed.
1064  virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
1065 
1066  /// Check whether the target can fold a load that feeds a subreg operand
1067  /// (or a subreg operand that feeds a store).
1068  /// For example, X86 may want to return true if it can fold
1069  /// movl (%esp), %eax
1070  /// subb, %al, ...
1071  /// Into:
1072  /// subb (%esp), ...
1073  ///
1074  /// Ideally, we'd like the target implementation of foldMemoryOperand() to
1075  /// reject subregs - but since this behavior used to be enforced in the
1076  /// target-independent code, moving this responsibility to the targets
1077  /// has the potential of causing nasty silent breakage in out-of-tree targets.
1078  virtual bool isSubregFoldable() const { return false; }
1079 
1080  /// For a patchpoint, stackmap, or statepoint intrinsic, return the range of
1081  /// operands which can't be folded into stack references. Operands outside
1082  /// of the range are most likely foldable but it is not guaranteed.
1083  /// These instructions are unique in that stack references for some operands
1084  /// have the same execution cost (e.g. none) as the unfolded register forms.
1085  /// The ranged return is guaranteed to include all operands which can't be
1086  /// folded at zero cost.
1087  virtual std::pair<unsigned, unsigned>
1089 
1090  /// Attempt to fold a load or store of the specified stack
1091  /// slot into the specified machine instruction for the specified operand(s).
1092  /// If this is possible, a new instruction is returned with the specified
1093  /// operand folded, otherwise NULL is returned.
1094  /// The new instruction is inserted before MI, and the client is responsible
1095  /// for removing the old instruction.
1096  /// If VRM is passed, the assigned physregs can be inspected by target to
1097  /// decide on using an opcode (note that those assignments can still change).
1099  int FI,
1100  LiveIntervals *LIS = nullptr,
1101  VirtRegMap *VRM = nullptr) const;
1102 
1103  /// Same as the previous version except it allows folding of any load and
1104  /// store from / to any address, not just from a specific stack slot.
1106  MachineInstr &LoadMI,
1107  LiveIntervals *LIS = nullptr) const;
1108 
1109  /// Return true when there is potentially a faster code sequence
1110  /// for an instruction chain ending in \p Root. All potential patterns are
1111  /// returned in the \p Pattern vector. Pattern should be sorted in priority
1112  /// order since the pattern evaluator stops checking as soon as it finds a
1113  /// faster sequence.
1114  /// \param Root - Instruction that could be combined with one of its operands
1115  /// \param Patterns - Vector of possible combination patterns
1116  virtual bool
1119  bool DoRegPressureReduce) const;
1120 
1121  /// Return true if target supports reassociation of instructions in machine
1122  /// combiner pass to reduce register pressure for a given BB.
1123  virtual bool
1125  RegisterClassInfo *RegClassInfo) const {
1126  return false;
1127  }
1128 
1129  /// Fix up the placeholder we may add in genAlternativeCodeSequence().
1130  virtual void
1132  SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
1133 
1134  /// Return true when a code sequence can improve throughput. It
1135  /// should be called only for instructions in loops.
1136  /// \param Pattern - combiner pattern
1138 
1139  /// Return true if the input \P Inst is part of a chain of dependent ops
1140  /// that are suitable for reassociation, otherwise return false.
1141  /// If the instruction's operands must be commuted to have a previous
1142  /// instruction of the same type define the first source operand, \P Commuted
1143  /// will be set to true.
1144  bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
1145 
1146  /// Return true when \P Inst is both associative and commutative.
1147  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
1148  return false;
1149  }
1150 
1151  /// Return true when \P Inst has reassociable operands in the same \P MBB.
1152  virtual bool hasReassociableOperands(const MachineInstr &Inst,
1153  const MachineBasicBlock *MBB) const;
1154 
1155  /// Return true when \P Inst has reassociable sibling.
1156  bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
1157 
1158  /// When getMachineCombinerPatterns() finds patterns, this function generates
1159  /// the instructions that could replace the original code sequence. The client
1160  /// has to decide whether the actual replacement is beneficial or not.
1161  /// \param Root - Instruction that could be combined with one of its operands
1162  /// \param Pattern - Combination pattern for Root
1163  /// \param InsInstrs - Vector of new instructions that implement P
1164  /// \param DelInstrs - Old instructions, including Root, that could be
1165  /// replaced by InsInstr
1166  /// \param InstIdxForVirtReg - map of virtual register to instruction in
1167  /// InsInstr that defines it
1168  virtual void genAlternativeCodeSequence(
1172  DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const;
1173 
1174  /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
1175  /// reduce critical path length.
1176  void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
1180  DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
1181 
1182  /// The limit on resource length extension we accept in MachineCombiner Pass.
1183  virtual int getExtendResourceLenLimit() const { return 0; }
1184 
1185  /// This is an architecture-specific helper function of reassociateOps.
1186  /// Set special operand attributes for new instructions after reassociation.
1187  virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
1188  MachineInstr &NewMI1,
1189  MachineInstr &NewMI2) const {}
1190 
1191  virtual void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const {}
1192 
1193  /// Return true when a target supports MachineCombiner.
1194  virtual bool useMachineCombiner() const { return false; }
1195 
1196  /// Return true if the given SDNode can be copied during scheduling
1197  /// even if it has glue.
1198  virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
1199 
1200 protected:
1201  /// Target-dependent implementation for foldMemoryOperand.
1202  /// Target-independent code in foldMemoryOperand will
1203  /// take care of adding a MachineMemOperand to the newly created instruction.
1204  /// The instruction and any auxiliary instructions necessary will be inserted
1205  /// at InsertPt.
1206  virtual MachineInstr *
1208  ArrayRef<unsigned> Ops,
1210  LiveIntervals *LIS = nullptr,
1211  VirtRegMap *VRM = nullptr) const {
1212  return nullptr;
1213  }
1214 
1215  /// Target-dependent implementation for foldMemoryOperand.
1216  /// Target-independent code in foldMemoryOperand will
1217  /// take care of adding a MachineMemOperand to the newly created instruction.
1218  /// The instruction and any auxiliary instructions necessary will be inserted
1219  /// at InsertPt.
1222  MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1223  LiveIntervals *LIS = nullptr) const {
1224  return nullptr;
1225  }
1226 
1227  /// Target-dependent implementation of getRegSequenceInputs.
1228  ///
1229  /// \returns true if it is possible to build the equivalent
1230  /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
1231  ///
1232  /// \pre MI.isRegSequenceLike().
1233  ///
1234  /// \see TargetInstrInfo::getRegSequenceInputs.
1236  const MachineInstr &MI, unsigned DefIdx,
1237  SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1238  return false;
1239  }
1240 
1241  /// Target-dependent implementation of getExtractSubregInputs.
1242  ///
1243  /// \returns true if it is possible to build the equivalent
1244  /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1245  ///
1246  /// \pre MI.isExtractSubregLike().
1247  ///
1248  /// \see TargetInstrInfo::getExtractSubregInputs.
1250  unsigned DefIdx,
1251  RegSubRegPairAndIdx &InputReg) const {
1252  return false;
1253  }
1254 
1255  /// Target-dependent implementation of getInsertSubregInputs.
1256  ///
1257  /// \returns true if it is possible to build the equivalent
1258  /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1259  ///
1260  /// \pre MI.isInsertSubregLike().
1261  ///
1262  /// \see TargetInstrInfo::getInsertSubregInputs.
1263  virtual bool
1264  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1265  RegSubRegPair &BaseReg,
1266  RegSubRegPairAndIdx &InsertedReg) const {
1267  return false;
1268  }
1269 
1270 public:
1271  /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1272  /// (e.g. stack) the target returns the corresponding address space.
1273  virtual unsigned
1275  return 0;
1276  }
1277 
1278  /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1279  /// a store or a load and a store into two or more instruction. If this is
1280  /// possible, returns true as well as the new instructions by reference.
1281  virtual bool
1283  bool UnfoldLoad, bool UnfoldStore,
1284  SmallVectorImpl<MachineInstr *> &NewMIs) const {
1285  return false;
1286  }
1287 
1289  SmallVectorImpl<SDNode *> &NewNodes) const {
1290  return false;
1291  }
1292 
1293  /// Returns the opcode of the would be new
1294  /// instruction after load / store are unfolded from an instruction of the
1295  /// specified opcode. It returns zero if the specified unfolding is not
1296  /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1297  /// index of the operand which will hold the register holding the loaded
1298  /// value.
1299  virtual unsigned
1300  getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1301  unsigned *LoadRegIndex = nullptr) const {
1302  return 0;
1303  }
1304 
1305  /// This is used by the pre-regalloc scheduler to determine if two loads are
1306  /// loading from the same base address. It should only return true if the base
1307  /// pointers are the same and the only differences between the two addresses
1308  /// are the offset. It also returns the offsets by reference.
1309  virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1310  int64_t &Offset1,
1311  int64_t &Offset2) const {
1312  return false;
1313  }
1314 
1315  /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1316  /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1317  /// On some targets if two loads are loading from
1318  /// addresses in the same cache line, it's better if they are scheduled
1319  /// together. This function takes two integers that represent the load offsets
1320  /// from the common base address. It returns true if it decides it's desirable
1321  /// to schedule the two loads together. "NumLoads" is the number of loads that
1322  /// have already been scheduled after Load1.
1323  virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1324  int64_t Offset1, int64_t Offset2,
1325  unsigned NumLoads) const {
1326  return false;
1327  }
1328 
1329  /// Get the base operand and byte offset of an instruction that reads/writes
1330  /// memory. This is a convenience function for callers that are only prepared
1331  /// to handle a single base operand.
1333  const MachineOperand *&BaseOp, int64_t &Offset,
1334  bool &OffsetIsScalable,
1335  const TargetRegisterInfo *TRI) const;
1336 
1337  /// Get zero or more base operands and the byte offset of an instruction that
1338  /// reads/writes memory. Note that there may be zero base operands if the
1339  /// instruction accesses a constant address.
1340  /// It returns false if MI does not read/write memory.
1341  /// It returns false if base operands and offset could not be determined.
1342  /// It is not guaranteed to always recognize base operands and offsets in all
1343  /// cases.
1346  int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
1347  const TargetRegisterInfo *TRI) const {
1348  return false;
1349  }
1350 
1351  /// Return true if the instruction contains a base register and offset. If
1352  /// true, the function also sets the operand position in the instruction
1353  /// for the base register and offset.
1355  unsigned &BasePos,
1356  unsigned &OffsetPos) const {
1357  return false;
1358  }
1359 
1360  /// Target dependent implementation to get the values constituting the address
1361  /// MachineInstr that is accessing memory. These values are returned as a
1362  /// struct ExtAddrMode which contains all relevant information to make up the
1363  /// address.
1364  virtual Optional<ExtAddrMode>
1366  const TargetRegisterInfo *TRI) const {
1367  return None;
1368  }
1369 
1370  /// Returns true if MI's Def is NullValueReg, and the MI
1371  /// does not change the Zero value. i.e. cases such as rax = shr rax, X where
1372  /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this
1373  /// function can return true even if becomes zero. Specifically cases such as
1374  /// NullValueReg = shl NullValueReg, 63.
1376  const Register NullValueReg,
1377  const TargetRegisterInfo *TRI) const {
1378  return false;
1379  }
1380 
1381  /// If the instruction is an increment of a constant value, return the amount.
1382  virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1383  return false;
1384  }
1385 
1386  /// Returns true if the two given memory operations should be scheduled
1387  /// adjacent. Note that you have to add:
1388  /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1389  /// or
1390  /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1391  /// to TargetPassConfig::createMachineScheduler() to have an effect.
1392  ///
1393  /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations.
1394  /// \p NumLoads is the number of loads that will be in the cluster if this
1395  /// hook returns true.
1396  /// \p NumBytes is the number of bytes that will be loaded from all the
1397  /// clustered loads if this hook returns true.
1400  unsigned NumLoads, unsigned NumBytes) const {
1401  llvm_unreachable("target did not implement shouldClusterMemOps()");
1402  }
1403 
1404  /// Reverses the branch condition of the specified condition list,
1405  /// returning false on success and true if it cannot be reversed.
1406  virtual bool
1408  return true;
1409  }
1410 
1411  /// Insert a noop into the instruction stream at the specified point.
1412  virtual void insertNoop(MachineBasicBlock &MBB,
1414 
1415  /// Insert noops into the instruction stream at the specified point.
1416  virtual void insertNoops(MachineBasicBlock &MBB,
1418  unsigned Quantity) const;
1419 
1420  /// Return the noop instruction to use for a noop.
1421  virtual MCInst getNop() const;
1422 
1423  /// Return true for post-incremented instructions.
1424  virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1425 
1426  /// Returns true if the instruction is already predicated.
1427  virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1428 
1429  // Returns a MIRPrinter comment for this machine operand.
1430  virtual std::string
1432  unsigned OpIdx, const TargetRegisterInfo *TRI) const;
1433 
1434  /// Returns true if the instruction is a
1435  /// terminator instruction that has not been predicated.
1436  bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1437 
1438  /// Returns true if MI is an unconditional tail call.
1439  virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1440  return false;
1441  }
1442 
1443  /// Returns true if the tail call can be made conditional on BranchCond.
1445  const MachineInstr &TailCall) const {
1446  return false;
1447  }
1448 
1449  /// Replace the conditional branch in MBB with a conditional tail call.
1452  const MachineInstr &TailCall) const {
1453  llvm_unreachable("Target didn't implement replaceBranchWithTailCall!");
1454  }
1455 
1456  /// Convert the instruction into a predicated instruction.
1457  /// It returns true if the operation was successful.
1458  virtual bool PredicateInstruction(MachineInstr &MI,
1459  ArrayRef<MachineOperand> Pred) const;
1460 
1461  /// Returns true if the first specified predicate
1462  /// subsumes the second, e.g. GE subsumes GT.
1464  ArrayRef<MachineOperand> Pred2) const {
1465  return false;
1466  }
1467 
1468  /// If the specified instruction defines any predicate
1469  /// or condition code register(s) used for predication, returns true as well
1470  /// as the definition predicate(s) by reference.
1471  /// SkipDead should be set to false at any point that dead
1472  /// predicate instructions should be considered as being defined.
1473  /// A dead predicate instruction is one that is guaranteed to be removed
1474  /// after a call to PredicateInstruction.
1476  std::vector<MachineOperand> &Pred,
1477  bool SkipDead) const {
1478  return false;
1479  }
1480 
1481  /// Return true if the specified instruction can be predicated.
1482  /// By default, this returns true for every instruction with a
1483  /// PredicateOperand.
1484  virtual bool isPredicable(const MachineInstr &MI) const {
1485  return MI.getDesc().isPredicable();
1486  }
1487 
1488  /// Return true if it's safe to move a machine
1489  /// instruction that defines the specified register class.
1490  virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1491  return true;
1492  }
1493 
1494  /// Test if the given instruction should be considered a scheduling boundary.
1495  /// This primarily includes labels and terminators.
1496  virtual bool isSchedulingBoundary(const MachineInstr &MI,
1497  const MachineBasicBlock *MBB,
1498  const MachineFunction &MF) const;
1499 
1500  /// Measure the specified inline asm to determine an approximation of its
1501  /// length.
1502  virtual unsigned getInlineAsmLength(
1503  const char *Str, const MCAsmInfo &MAI,
1504  const TargetSubtargetInfo *STI = nullptr) const;
1505 
1506  /// Allocate and return a hazard recognizer to use for this target when
1507  /// scheduling the machine instructions before register allocation.
1508  virtual ScheduleHazardRecognizer *
1510  const ScheduleDAG *DAG) const;
1511 
1512  /// Allocate and return a hazard recognizer to use for this target when
1513  /// scheduling the machine instructions before register allocation.
1514  virtual ScheduleHazardRecognizer *
1516  const ScheduleDAGMI *DAG) const;
1517 
1518  /// Allocate and return a hazard recognizer to use for this target when
1519  /// scheduling the machine instructions after register allocation.
1520  virtual ScheduleHazardRecognizer *
1522  const ScheduleDAG *DAG) const;
1523 
1524  /// Allocate and return a hazard recognizer to use for by non-scheduling
1525  /// passes.
1526  virtual ScheduleHazardRecognizer *
1528  return nullptr;
1529  }
1530 
1531  /// Provide a global flag for disabling the PreRA hazard recognizer that
1532  /// targets may choose to honor.
1533  bool usePreRAHazardRecognizer() const;
1534 
1535  /// For a comparison instruction, return the source registers
1536  /// in SrcReg and SrcReg2 if having two register operands, and the value it
1537  /// compares against in CmpValue. Return true if the comparison instruction
1538  /// can be analyzed.
1539  virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1540  Register &SrcReg2, int64_t &Mask,
1541  int64_t &Value) const {
1542  return false;
1543  }
1544 
1545  /// See if the comparison instruction can be converted
1546  /// into something more efficient. E.g., on ARM most instructions can set the
1547  /// flags register, obviating the need for a separate CMP.
1548  virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
1549  Register SrcReg2, int64_t Mask,
1550  int64_t Value,
1551  const MachineRegisterInfo *MRI) const {
1552  return false;
1553  }
1554  virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1555 
1556  /// Try to remove the load by folding it to a register operand at the use.
1557  /// We fold the load instructions if and only if the
1558  /// def and use are in the same BB. We only look at one load and see
1559  /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1560  /// defined by the load we are trying to fold. DefMI returns the machine
1561  /// instruction that defines FoldAsLoadDefReg, and the function returns
1562  /// the machine instruction generated due to folding.
1564  const MachineRegisterInfo *MRI,
1565  Register &FoldAsLoadDefReg,
1566  MachineInstr *&DefMI) const {
1567  return nullptr;
1568  }
1569 
1570  /// 'Reg' is known to be defined by a move immediate instruction,
1571  /// try to fold the immediate into the use instruction.
1572  /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1573  /// then the caller may assume that DefMI has been erased from its parent
1574  /// block. The caller may assume that it will not be erased by this
1575  /// function otherwise.
1577  Register Reg, MachineRegisterInfo *MRI) const {
1578  return false;
1579  }
1580 
1581  /// Return the number of u-operations the given machine
1582  /// instruction will be decoded to on the target cpu. The itinerary's
1583  /// IssueWidth is the number of microops that can be dispatched each
1584  /// cycle. An instruction with zero microops takes no dispatch resources.
1585  virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1586  const MachineInstr &MI) const;
1587 
1588  /// Return true for pseudo instructions that don't consume any
1589  /// machine resources in their current form. These are common cases that the
1590  /// scheduler should consider free, rather than conservatively handling them
1591  /// as instructions with no itinerary.
1592  bool isZeroCost(unsigned Opcode) const {
1593  return Opcode <= TargetOpcode::COPY;
1594  }
1595 
1596  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1597  SDNode *DefNode, unsigned DefIdx,
1598  SDNode *UseNode, unsigned UseIdx) const;
1599 
1600  /// Compute and return the use operand latency of a given pair of def and use.
1601  /// In most cases, the static scheduling itinerary was enough to determine the
1602  /// operand latency. But it may not be possible for instructions with variable
1603  /// number of defs / uses.
1604  ///
1605  /// This is a raw interface to the itinerary that may be directly overridden
1606  /// by a target. Use computeOperandLatency to get the best estimate of
1607  /// latency.
1608  virtual int getOperandLatency(const InstrItineraryData *ItinData,
1609  const MachineInstr &DefMI, unsigned DefIdx,
1610  const MachineInstr &UseMI,
1611  unsigned UseIdx) const;
1612 
1613  /// Compute the instruction latency of a given instruction.
1614  /// If the instruction has higher cost when predicated, it's returned via
1615  /// PredCost.
1616  virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1617  const MachineInstr &MI,
1618  unsigned *PredCost = nullptr) const;
1619 
1620  virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1621 
1622  virtual int getInstrLatency(const InstrItineraryData *ItinData,
1623  SDNode *Node) const;
1624 
1625  /// Return the default expected latency for a def based on its opcode.
1626  unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1627  const MachineInstr &DefMI) const;
1628 
1629  /// Return true if this opcode has high latency to its result.
1630  virtual bool isHighLatencyDef(int opc) const { return false; }
1631 
1632  /// Compute operand latency between a def of 'Reg'
1633  /// and a use in the current loop. Return true if the target considered
1634  /// it 'high'. This is used by optimization passes such as machine LICM to
1635  /// determine whether it makes sense to hoist an instruction out even in a
1636  /// high register pressure situation.
1637  virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1638  const MachineRegisterInfo *MRI,
1639  const MachineInstr &DefMI, unsigned DefIdx,
1640  const MachineInstr &UseMI,
1641  unsigned UseIdx) const {
1642  return false;
1643  }
1644 
1645  /// Compute operand latency of a def of 'Reg'. Return true
1646  /// if the target considered it 'low'.
1647  virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1648  const MachineInstr &DefMI,
1649  unsigned DefIdx) const;
1650 
1651  /// Perform target-specific instruction verification.
1652  virtual bool verifyInstruction(const MachineInstr &MI,
1653  StringRef &ErrInfo) const {
1654  return true;
1655  }
1656 
1657  /// Return the current execution domain and bit mask of
1658  /// possible domains for instruction.
1659  ///
1660  /// Some micro-architectures have multiple execution domains, and multiple
1661  /// opcodes that perform the same operation in different domains. For
1662  /// example, the x86 architecture provides the por, orps, and orpd
1663  /// instructions that all do the same thing. There is a latency penalty if a
1664  /// register is written in one domain and read in another.
1665  ///
1666  /// This function returns a pair (domain, mask) containing the execution
1667  /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1668  /// function can be used to change the opcode to one of the domains in the
1669  /// bit mask. Instructions whose execution domain can't be changed should
1670  /// return a 0 mask.
1671  ///
1672  /// The execution domain numbers don't have any special meaning except domain
1673  /// 0 is used for instructions that are not associated with any interesting
1674  /// execution domain.
1675  ///
1676  virtual std::pair<uint16_t, uint16_t>
1678  return std::make_pair(0, 0);
1679  }
1680 
1681  /// Change the opcode of MI to execute in Domain.
1682  ///
1683  /// The bit (1 << Domain) must be set in the mask returned from
1684  /// getExecutionDomain(MI).
1685  virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1686 
1687  /// Returns the preferred minimum clearance
1688  /// before an instruction with an unwanted partial register update.
1689  ///
1690  /// Some instructions only write part of a register, and implicitly need to
1691  /// read the other parts of the register. This may cause unwanted stalls
1692  /// preventing otherwise unrelated instructions from executing in parallel in
1693  /// an out-of-order CPU.
1694  ///
1695  /// For example, the x86 instruction cvtsi2ss writes its result to bits
1696  /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1697  /// the instruction needs to wait for the old value of the register to become
1698  /// available:
1699  ///
1700  /// addps %xmm1, %xmm0
1701  /// movaps %xmm0, (%rax)
1702  /// cvtsi2ss %rbx, %xmm0
1703  ///
1704  /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1705  /// instruction before it can issue, even though the high bits of %xmm0
1706  /// probably aren't needed.
1707  ///
1708  /// This hook returns the preferred clearance before MI, measured in
1709  /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1710  /// instructions before MI. It should only return a positive value for
1711  /// unwanted dependencies. If the old bits of the defined register have
1712  /// useful values, or if MI is determined to otherwise read the dependency,
1713  /// the hook should return 0.
1714  ///
1715  /// The unwanted dependency may be handled by:
1716  ///
1717  /// 1. Allocating the same register for an MI def and use. That makes the
1718  /// unwanted dependency identical to a required dependency.
1719  ///
1720  /// 2. Allocating a register for the def that has no defs in the previous N
1721  /// instructions.
1722  ///
1723  /// 3. Calling breakPartialRegDependency() with the same arguments. This
1724  /// allows the target to insert a dependency breaking instruction.
1725  ///
1726  virtual unsigned
1728  const TargetRegisterInfo *TRI) const {
1729  // The default implementation returns 0 for no partial register dependency.
1730  return 0;
1731  }
1732 
1733  /// Return the minimum clearance before an instruction that reads an
1734  /// unused register.
1735  ///
1736  /// For example, AVX instructions may copy part of a register operand into
1737  /// the unused high bits of the destination register.
1738  ///
1739  /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1740  ///
1741  /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1742  /// false dependence on any previous write to %xmm0.
1743  ///
1744  /// This hook works similarly to getPartialRegUpdateClearance, except that it
1745  /// does not take an operand index. Instead sets \p OpNum to the index of the
1746  /// unused register.
1747  virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
1748  const TargetRegisterInfo *TRI) const {
1749  // The default implementation returns 0 for no undef register dependency.
1750  return 0;
1751  }
1752 
1753  /// Insert a dependency-breaking instruction
1754  /// before MI to eliminate an unwanted dependency on OpNum.
1755  ///
1756  /// If it wasn't possible to avoid a def in the last N instructions before MI
1757  /// (see getPartialRegUpdateClearance), this hook will be called to break the
1758  /// unwanted dependency.
1759  ///
1760  /// On x86, an xorps instruction can be used as a dependency breaker:
1761  ///
1762  /// addps %xmm1, %xmm0
1763  /// movaps %xmm0, (%rax)
1764  /// xorps %xmm0, %xmm0
1765  /// cvtsi2ss %rbx, %xmm0
1766  ///
1767  /// An <imp-kill> operand should be added to MI if an instruction was
1768  /// inserted. This ties the instructions together in the post-ra scheduler.
1769  ///
1770  virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1771  const TargetRegisterInfo *TRI) const {}
1772 
1773  /// Create machine specific model for scheduling.
1774  virtual DFAPacketizer *
1776  return nullptr;
1777  }
1778 
1779  /// Sometimes, it is possible for the target
1780  /// to tell, even without aliasing information, that two MIs access different
1781  /// memory addresses. This function returns true if two MIs access different
1782  /// memory addresses and false otherwise.
1783  ///
1784  /// Assumes any physical registers used to compute addresses have the same
1785  /// value for both instructions. (This is the most useful assumption for
1786  /// post-RA scheduling.)
1787  ///
1788  /// See also MachineInstr::mayAlias, which is implemented on top of this
1789  /// function.
1790  virtual bool
1792  const MachineInstr &MIb) const {
1793  assert(MIa.mayLoadOrStore() &&
1794  "MIa must load from or modify a memory location");
1795  assert(MIb.mayLoadOrStore() &&
1796  "MIb must load from or modify a memory location");
1797  return false;
1798  }
1799 
1800  /// Return the value to use for the MachineCSE's LookAheadLimit,
1801  /// which is a heuristic used for CSE'ing phys reg defs.
1802  virtual unsigned getMachineCSELookAheadLimit() const {
1803  // The default lookahead is small to prevent unprofitable quadratic
1804  // behavior.
1805  return 5;
1806  }
1807 
1808  /// Return the maximal number of alias checks on memory operands. For
1809  /// instructions with more than one memory operands, the alias check on a
1810  /// single MachineInstr pair has quadratic overhead and results in
1811  /// unacceptable performance in the worst case. The limit here is to clamp
1812  /// that maximal checks performed. Usually, that's the product of memory
1813  /// operand numbers from that pair of MachineInstr to be checked. For
1814  /// instance, with two MachineInstrs with 4 and 5 memory operands
1815  /// correspondingly, a total of 20 checks are required. With this limit set to
1816  /// 16, their alias check is skipped. We choose to limit the product instead
1817  /// of the individual instruction as targets may have special MachineInstrs
1818  /// with a considerably high number of memory operands, such as `ldm` in ARM.
1819  /// Setting this limit per MachineInstr would result in either too high
1820  /// overhead or too rigid restriction.
1821  virtual unsigned getMemOperandAACheckLimit() const { return 16; }
1822 
1823  /// Return an array that contains the ids of the target indices (used for the
1824  /// TargetIndex machine operand) and their names.
1825  ///
1826  /// MIR Serialization is able to serialize only the target indices that are
1827  /// defined by this method.
1830  return None;
1831  }
1832 
1833  /// Decompose the machine operand's target flags into two values - the direct
1834  /// target flag value and any of bit flags that are applied.
1835  virtual std::pair<unsigned, unsigned>
1836  decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1837  return std::make_pair(0u, 0u);
1838  }
1839 
1840  /// Return an array that contains the direct target flag values and their
1841  /// names.
1842  ///
1843  /// MIR Serialization is able to serialize only the target flags that are
1844  /// defined by this method.
1847  return None;
1848  }
1849 
1850  /// Return an array that contains the bitmask target flag values and their
1851  /// names.
1852  ///
1853  /// MIR Serialization is able to serialize only the target flags that are
1854  /// defined by this method.
1857  return None;
1858  }
1859 
1860  /// Return an array that contains the MMO target flag values and their
1861  /// names.
1862  ///
1863  /// MIR Serialization is able to serialize only the MMO target flags that are
1864  /// defined by this method.
1867  return None;
1868  }
1869 
1870  /// Determines whether \p Inst is a tail call instruction. Override this
1871  /// method on targets that do not properly set MCID::Return and MCID::Call on
1872  /// tail call instructions."
1873  virtual bool isTailCall(const MachineInstr &Inst) const {
1874  return Inst.isReturn() && Inst.isCall();
1875  }
1876 
1877  /// True if the instruction is bound to the top of its basic block and no
1878  /// other instructions shall be inserted before it. This can be implemented
1879  /// to prevent register allocator to insert spills before such instructions.
1880  virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1881  return false;
1882  }
1883 
1884  /// During PHI eleimination lets target to make necessary checks and
1885  /// insert the copy to the PHI destination register in a target specific
1886  /// manner.
1889  const DebugLoc &DL, Register Src, Register Dst) const {
1890  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1891  .addReg(Src);
1892  }
1893 
1894  /// During PHI eleimination lets target to make necessary checks and
1895  /// insert the copy to the PHI destination register in a target specific
1896  /// manner.
1899  const DebugLoc &DL, Register Src,
1900  unsigned SrcSubReg,
1901  Register Dst) const {
1902  return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1903  .addReg(Src, 0, SrcSubReg);
1904  }
1905 
1906  /// Returns a \p outliner::OutlinedFunction struct containing target-specific
1907  /// information for a set of outlining candidates.
1909  std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
1911  "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!");
1912  }
1913 
1914  /// Returns how or if \p MI should be outlined.
1915  virtual outliner::InstrType
1916  getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1918  "Target didn't implement TargetInstrInfo::getOutliningType!");
1919  }
1920 
1921  /// Optional target hook that returns true if \p MBB is safe to outline from,
1922  /// and returns any target-specific information in \p Flags.
1924  unsigned &Flags) const {
1925  return true;
1926  }
1927 
1928  /// Insert a custom frame for outlined functions.
1930  const outliner::OutlinedFunction &OF) const {
1932  "Target didn't implement TargetInstrInfo::buildOutlinedFrame!");
1933  }
1934 
1935  /// Insert a call to an outlined function into the program.
1936  /// Returns an iterator to the spot where we inserted the call. This must be
1937  /// implemented by the target.
1941  const outliner::Candidate &C) const {
1943  "Target didn't implement TargetInstrInfo::insertOutlinedCall!");
1944  }
1945 
1946  /// Return true if the function can safely be outlined from.
1947  /// A function \p MF is considered safe for outlining if an outlined function
1948  /// produced from instructions in F will produce a program which produces the
1949  /// same output for any set of given inputs.
1951  bool OutlineFromLinkOnceODRs) const {
1952  llvm_unreachable("Target didn't implement "
1953  "TargetInstrInfo::isFunctionSafeToOutlineFrom!");
1954  }
1955 
1956  /// Return true if the function should be outlined from by default.
1958  return false;
1959  }
1960 
1961  /// Produce the expression describing the \p MI loading a value into
1962  /// the physical register \p Reg. This hook should only be used with
1963  /// \p MIs belonging to VReg-less functions.
1965  Register Reg) const;
1966 
1967  /// Given the generic extension instruction \p ExtMI, returns true if this
1968  /// extension is a likely candidate for being folded into an another
1969  /// instruction.
1971  MachineRegisterInfo &MRI) const {
1972  return false;
1973  }
1974 
1975  /// Return MIR formatter to format/parse MIR operands. Target can override
1976  /// this virtual function and return target specific MIR formatter.
1977  virtual const MIRFormatter *getMIRFormatter() const {
1978  if (!Formatter.get())
1979  Formatter = std::make_unique<MIRFormatter>();
1980  return Formatter.get();
1981  }
1982 
1983  /// Returns the target-specific default value for tail duplication.
1984  /// This value will be used if the tail-dup-placement-threshold argument is
1985  /// not provided.
1986  virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const {
1987  return OptLevel >= CodeGenOpt::Aggressive ? 4 : 2;
1988  }
1989 
1990  /// Returns the callee operand from the given \p MI.
1991  virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const {
1992  return MI.getOperand(0);
1993  }
1994 
1995 private:
1996  mutable std::unique_ptr<MIRFormatter> Formatter;
1997  unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1998  unsigned CatchRetOpcode;
1999  unsigned ReturnOpcode;
2000 };
2001 
2002 /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
2005 
2007  return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
2008  RegInfo::getEmptyKey());
2009  }
2010 
2012  return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
2013  RegInfo::getTombstoneKey());
2014  }
2015 
2016  /// Reuse getHashValue implementation from
2017  /// std::pair<unsigned, unsigned>.
2018  static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
2019  std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
2020  return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
2021  }
2022 
2023  static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
2024  const TargetInstrInfo::RegSubRegPair &RHS) {
2025  return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
2026  RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
2027  }
2028 };
2029 
2030 } // end namespace llvm
2031 
2032 #endif // LLVM_CODEGEN_TARGETINSTRINFO_H
llvm::Check::Size
@ Size
Definition: FileCheck.h:73
llvm::TargetInstrInfo::getConstValDefinedInReg
virtual bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg, int64_t &ImmVal) const
Returns true if MI is an instruction that defines Reg to have a constant value and the value is recor...
Definition: TargetInstrInfo.h:1027
llvm::TargetInstrInfo::hasReassociableSibling
bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const
Return true when \P Inst has reassociable sibling.
Definition: TargetInstrInfo.cpp:719
llvm::TargetInstrInfo::getMemOperandWithOffset
bool getMemOperandWithOffset(const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset, bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const
Get the base operand and byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.cpp:1066
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:103
MachineInstr.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::TargetInstrInfo::isSafeToMoveRegClassDefs
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const
Return true if it's safe to move a machine instruction that defines the specified register class.
Definition: TargetInstrInfo.h:1490
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::TargetInstrInfo::analyzeCompare
virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &Mask, int64_t &Value) const
For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two registe...
Definition: TargetInstrInfo.h:1539
llvm::TargetInstrInfo::insertSelect
virtual void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const
Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true,...
Definition: TargetInstrInfo.h:897
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::TargetInstrInfo::isSubregFoldable
virtual bool isSubregFoldable() const
Check whether the target can fold a load that feeds a subreg operand (or a subreg operand that feeds ...
Definition: TargetInstrInfo.h:1078
llvm::TargetInstrInfo::duplicate
virtual MachineInstr & duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, const MachineInstr &Orig) const
Clones instruction or the whole instruction bundle Orig and insert into MBB before InsertBefore.
Definition: TargetInstrInfo.cpp:435
llvm::TargetInstrInfo::areLoadsFromSameBasePtr
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const
This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base a...
Definition: TargetInstrInfo.h:1309
llvm::TargetInstrInfo::CreateTargetHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1046
llvm::DenseMapInfo< unsigned >
Definition: DenseMapInfo.h:117
llvm::TargetInstrInfo::replaceBranchWithTailCall
virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Replace the conditional branch in MBB with a conditional tail call.
Definition: TargetInstrInfo.h:1450
llvm::TargetInstrInfo::getCatchReturnOpcode
unsigned getCatchReturnOpcode() const
Definition: TargetInstrInfo.h:238
llvm::TargetInstrInfo::unfoldMemoryOperand
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a st...
Definition: TargetInstrInfo.h:1282
llvm::TargetInstrInfo::useMachineCombiner
virtual bool useMachineCombiner() const
Return true when a target supports MachineCombiner.
Definition: TargetInstrInfo.h:1194
llvm::TargetInstrInfo::analyzeBranchPredicate
virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify=false) const
Analyze the branching code at the end of MBB and parse it into the MachineBranchPredicate structure i...
Definition: TargetInstrInfo.h:667
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::TargetInstrInfo::MachineBranchPredicate
Represents a predicate at the MachineFunction level.
Definition: TargetInstrInfo.h:638
llvm::MachineInstr::mayLoadOrStore
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
Definition: MachineInstr.h:1028
llvm::RegImmPair::Imm
int64_t Imm
Definition: TargetInstrInfo.h:79
llvm::TargetInstrInfo::getReturnOpcode
unsigned getReturnOpcode() const
Definition: TargetInstrInfo.h:239
llvm::TargetInstrInfo::isThroughputPattern
virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const
Return true when a code sequence can improve throughput.
Definition: TargetInstrInfo.cpp:801
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::TargetInstrInfo::canInsertSelect
virtual bool canInsertSelect(const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const
Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseRe...
Definition: TargetInstrInfo.h:874
llvm::TargetInstrInfo::getExtractSubregInputs
bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1289
llvm::TargetInstrInfo::createPHIDestinationCopy
virtual MachineInstr * createPHIDestinationCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition: TargetInstrInfo.h:1887
llvm::TargetInstrInfo::RegSubRegPairAndIdx
A pair composed of a pair of a register and a sub-register index, and another sub-register index.
Definition: TargetInstrInfo.h:495
llvm::TargetInstrInfo::getMachineCombinerPatterns
virtual bool getMachineCombinerPatterns(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns, bool DoRegPressureReduce) const
Return true when there is potentially a faster code sequence for an instruction chain ending in Root.
Definition: TargetInstrInfo.cpp:777
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isLoadFromStackSlot that returns the number of bytes loaded from the stack.
Definition: TargetInstrInfo.h:271
llvm::TargetInstrInfo::getUndefRegClearance
virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Return the minimum clearance before an instruction that reads an unused register.
Definition: TargetInstrInfo.h:1747
ErrorHandling.h
llvm::VirtRegMap
Definition: VirtRegMap.h:33
llvm::TargetInstrInfo::isCopyInstrImpl
virtual Optional< DestSourcePair > isCopyInstrImpl(const MachineInstr &MI) const
Target-dependent implementation for IsCopyInstr.
Definition: TargetInstrInfo.h:986
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::isEqual
static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, const TargetInstrInfo::RegSubRegPair &RHS)
Definition: TargetInstrInfo.h:2023
llvm::TargetInstrInfo::copyPhysReg
virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const
Emit instructions to copy a pair of physical registers.
Definition: TargetInstrInfo.h:960
llvm::TargetInstrInfo::isGenericOpcode
static bool isGenericOpcode(unsigned Opc)
Definition: TargetInstrInfo.h:108
llvm::SDNode
Represents one node in the SelectionDAG.
Definition: SelectionDAGNodes.h:455
RegisterClassInfo.h
llvm::TargetInstrInfo::optimizeCondBranch
virtual bool optimizeCondBranch(MachineInstr &MI) const
Definition: TargetInstrInfo.h:1554
MachineBasicBlock.h
llvm::TargetInstrInfo::getAddressSpaceForPseudoSourceKind
virtual unsigned getAddressSpaceForPseudoSourceKind(unsigned Kind) const
getAddressSpaceForPseudoSourceKind - Given the kind of memory (e.g.
Definition: TargetInstrInfo.h:1274
llvm::TargetInstrInfo::MachineBranchPredicate::RHS
MachineOperand RHS
Definition: TargetInstrInfo.h:647
llvm::TargetInstrInfo::getCalleeOperand
virtual const MachineOperand & getCalleeOperand(const MachineInstr &MI) const
Returns the callee operand from the given MI.
Definition: TargetInstrInfo.h:1991
llvm::TargetInstrInfo::isUnspillableTerminator
bool isUnspillableTerminator(const MachineInstr *MI) const
Return true if the given instruction is terminator that is unspillable, according to isUnspillableTer...
Definition: TargetInstrInfo.h:360
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:233
llvm::TargetInstrInfo::insertNoops
virtual void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const
Insert noops into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:74
llvm::TargetInstrInfo::getIncrementValue
virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const
If the instruction is an increment of a constant value, return the amount.
Definition: TargetInstrInfo.h:1382
llvm::outliner::InstrType
InstrType
Represents how an instruction should be mapped by the outliner.
Definition: MachineOutliner.h:34
llvm::TargetInstrInfo::ReplaceTailWithBranchTo
virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const
Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to ...
Definition: TargetInstrInfo.cpp:141
DenseMap.h
llvm::TargetInstrInfo::MachineBranchPredicate::FalseDest
MachineBasicBlock * FalseDest
Definition: TargetInstrInfo.h:649
llvm::TargetInstrInfo::getOutliningCandidateInfo
virtual outliner::OutlinedFunction getOutliningCandidateInfo(std::vector< outliner::Candidate > &RepeatedSequenceLocs) const
Returns a outliner::OutlinedFunction struct containing target-specific information for a set of outli...
Definition: TargetInstrInfo.h:1908
llvm::TargetInstrInfo::CreateTargetScheduleState
virtual DFAPacketizer * CreateTargetScheduleState(const TargetSubtargetInfo &) const
Create machine specific model for scheduling.
Definition: TargetInstrInfo.h:1775
llvm::Optional< bool >
llvm::DestSourcePair::Destination
const MachineOperand * Destination
Definition: TargetInstrInfo.h:69
llvm::TargetInstrInfo::isCopyInstr
Optional< DestSourcePair > isCopyInstr(const MachineInstr &MI) const
If the specific machine instruction is a instruction that moves/copies value from one register to ano...
Definition: TargetInstrInfo.h:1008
llvm::TargetInstrInfo::getNop
virtual MCInst getNop() const
Return the noop instruction to use for a noop.
Definition: TargetInstrInfo.cpp:475
llvm::ExtAddrMode::ScaledReg
Register ScaledReg
Definition: TargetInstrInfo.h:88
Offset
uint64_t Offset
Definition: ELFObjHandler.cpp:81
llvm::TargetInstrInfo::isBranchOffsetInRange
virtual bool isBranchOffsetInRange(unsigned BranchOpc, int64_t BrOffset) const
Definition: TargetInstrInfo.h:575
llvm::TargetInstrInfo::hasHighOperandLatency
virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, const MachineRegisterInfo *MRI, const MachineInstr &DefMI, unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const
Compute operand latency between a def of 'Reg' and a use in the current loop.
Definition: TargetInstrInfo.h:1637
llvm::TargetInstrInfo::isPredicable
virtual bool isPredicable(const MachineInstr &MI) const
Return true if the specified instruction can be predicated.
Definition: TargetInstrInfo.h:1484
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::outliner::OutlinedFunction
The information necessary to create an outlined function for some class of candidate.
Definition: MachineOutliner.h:164
llvm::TargetInstrInfo::getInsertSubregInputs
bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1314
llvm::TargetInstrInfo::hasCommutePreference
virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const
Returns true if the target has a preference on the operands order of the given machine instruction.
Definition: TargetInstrInfo.h:471
llvm::TargetInstrInfo::decomposeMachineOperandsTargetFlags
virtual std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags(unsigned) const
Decompose the machine operand's target flags into two values - the direct target flag value and any o...
Definition: TargetInstrInfo.h:1836
llvm::TargetInstrInfo::RegSubRegPair::operator!=
bool operator!=(const RegSubRegPair &P) const
Definition: TargetInstrInfo.h:487
llvm::TargetInstrInfo::unfoldMemoryOperand
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const
Definition: TargetInstrInfo.h:1288
llvm::TargetInstrInfo::shouldClusterMemOps
virtual bool shouldClusterMemOps(ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const
Returns true if the two given memory operations should be scheduled adjacent.
Definition: TargetInstrInfo.h:1398
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::TargetInstrInfo::convertToThreeAddress
virtual MachineInstr * convertToThreeAddress(MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const
This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag.
Definition: TargetInstrInfo.h:414
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, LiveIntervals *LIS=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1220
llvm::TargetInstrInfo::getPartialRegUpdateClearance
virtual unsigned getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Returns the preferred minimum clearance before an instruction with an unwanted partial register updat...
Definition: TargetInstrInfo.h:1727
llvm::TargetInstrInfo::isHighLatencyDef
virtual bool isHighLatencyDef(int opc) const
Return true if this opcode has high latency to its result.
Definition: TargetInstrInfo.h:1630
llvm::MachineFunction::iterator
BasicBlockListType::iterator iterator
Definition: MachineFunction.h:790
llvm::TargetInstrInfo::RegSubRegPair
A pair composed of a register and a sub-register index.
Definition: TargetInstrInfo.h:477
llvm::ExtAddrMode
Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare.
Definition: TargetInstrInfo.h:86
llvm::RegImmPair::Reg
Register Reg
Definition: TargetInstrInfo.h:78
llvm::TargetInstrInfo::insertBranch
virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const
Insert branch code into the end of the specified MachineBasicBlock.
Definition: TargetInstrInfo.h:696
llvm::TargetInstrInfo::getMachineCSELookAheadLimit
virtual unsigned getMachineCSELookAheadLimit() const
Return the value to use for the MachineCSE's LookAheadLimit, which is a heuristic used for CSE'ing ph...
Definition: TargetInstrInfo.h:1802
llvm::TargetInstrInfo::RegSubRegPair::operator==
bool operator==(const RegSubRegPair &P) const
Definition: TargetInstrInfo.h:484
llvm::TargetInstrInfo::isZeroCost
bool isZeroCost(unsigned Opcode) const
Return true for pseudo instructions that don't consume any machine resources in their current form.
Definition: TargetInstrInfo.h:1592
llvm::TargetInstrInfo::getFrameSize
int64_t getFrameSize(const MachineInstr &I) const
Returns size of the frame associated with the given frame instruction.
Definition: TargetInstrInfo.h:220
llvm::TargetInstrInfo::PipelinerLoopInfo
Object returned by analyzeLoopForPipelining.
Definition: TargetInstrInfo.h:715
llvm::TargetInstrInfo::getRegClass
virtual const TargetRegisterClass * getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const
Given a machine instruction descriptor, returns the register class constraint for OpNum,...
Definition: TargetInstrInfo.cpp:47
llvm::DenseMapInfo
Definition: APInt.h:34
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_NE
@ PRED_NE
Definition: TargetInstrInfo.h:641
llvm::TargetInstrInfo::usePreRAHazardRecognizer
bool usePreRAHazardRecognizer() const
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition: TargetInstrInfo.cpp:1040
llvm::TargetInstrInfo::getFrameTotalSize
int64_t getFrameTotalSize(const MachineInstr &I) const
Returns the total frame size, which is made up of the space set up inside the pair of frame start-sto...
Definition: TargetInstrInfo.h:229
llvm::MachineInstr::isCall
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:823
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::TargetInstrInfo::removeBranch
virtual unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const
Remove the branching code at the end of the specific MBB.
Definition: TargetInstrInfo.h:678
llvm::TargetInstrInfo::commuteInstructionImpl
virtual MachineInstr * commuteInstructionImpl(MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:167
llvm::SelectionDAG
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:216
llvm::TargetInstrInfo::loadRegFromStackSlot
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Load the specified register of the given register class from the specified stack frame index.
Definition: TargetInstrInfo.h:1049
llvm::AAResults
Definition: AliasAnalysis.h:456
llvm::MachineOperand::CreateImm
static MachineOperand CreateImm(int64_t Val)
Definition: MachineOperand.h:773
llvm::TargetInstrInfo::MachineBranchPredicate::ConditionDef
MachineInstr * ConditionDef
Definition: TargetInstrInfo.h:650
llvm::TargetInstrInfo::canCopyGluedNodeDuringSchedule
virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const
Return true if the given SDNode can be copied during scheduling even if it has glue.
Definition: TargetInstrInfo.h:1198
llvm::TargetInstrInfo::verifyInstruction
virtual bool verifyInstruction(const MachineInstr &MI, StringRef &ErrInfo) const
Perform target-specific instruction verification.
Definition: TargetInstrInfo.h:1652
llvm::TargetInstrInfo::getInsertSubregLikeInputs
virtual bool getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const
Target-dependent implementation of getInsertSubregInputs.
Definition: TargetInstrInfo.h:1264
llvm::TargetInstrInfo::PipelinerLoopInfo::adjustTripCount
virtual void adjustTripCount(int TripCountAdjust)=0
Modify the loop such that the trip count is OriginalTC + TripCountAdjust.
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetInstrInfo::optimizeLoadInstr
virtual MachineInstr * optimizeLoadInstr(MachineInstr &MI, const MachineRegisterInfo *MRI, Register &FoldAsLoadDefReg, MachineInstr *&DefMI) const
Try to remove the load by folding it to a register operand at the use.
Definition: TargetInstrInfo.h:1563
llvm::TargetInstrInfo::setSpecialOperandAttr
virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, MachineInstr &NewMI1, MachineInstr &NewMI2) const
This is an architecture-specific helper function of reassociateOps.
Definition: TargetInstrInfo.h:1187
llvm::TargetInstrInfo::FoldImmediate
virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const
'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use ...
Definition: TargetInstrInfo.h:1576
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetInstrInfo::buildOutlinedFrame
virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, const outliner::OutlinedFunction &OF) const
Insert a custom frame for outlined functions.
Definition: TargetInstrInfo.h:1929
llvm::TargetInstrInfo::getExtendResourceLenLimit
virtual int getExtendResourceLenLimit() const
The limit on resource length extension we accept in MachineCombiner Pass.
Definition: TargetInstrInfo.h:1183
MCInstrInfo.h
llvm::DFAPacketizer
Definition: DFAPacketizer.h:49
llvm::TargetInstrInfo::RegSubRegPairAndIdx::RegSubRegPairAndIdx
RegSubRegPairAndIdx(Register Reg=Register(), unsigned SubReg=0, unsigned SubIdx=0)
Definition: TargetInstrInfo.h:498
llvm::TargetInstrInfo::getRegSequenceLikeInputs
virtual bool getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Target-dependent implementation of getRegSequenceInputs.
Definition: TargetInstrInfo.h:1235
llvm::TargetInstrInfo::isReassociationCandidate
bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const
Return true if the input \P Inst is part of a chain of dependent ops that are suitable for reassociat...
Definition: TargetInstrInfo.cpp:749
llvm::TargetInstrInfo::shouldOutlineFromFunctionByDefault
virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const
Return true if the function should be outlined from by default.
Definition: TargetInstrInfo.h:1957
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:685
llvm::TargetInstrInfo::expandPostRAPseudo
virtual bool expandPostRAPseudo(MachineInstr &MI) const
This function is called for all pseudo instructions that remain after register allocation.
Definition: TargetInstrInfo.h:1064
llvm::TargetInstrInfo::insertNoop
virtual void insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
Insert a noop into the instruction stream at the specified point.
Definition: TargetInstrInfo.cpp:67
llvm::TargetInstrInfo::getNumMicroOps
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
Definition: TargetInstrInfo.cpp:1115
llvm::MCInstrDesc
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:195
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::TargetInstrInfo::isTailCall
virtual bool isTailCall(const MachineInstr &Inst) const
Determines whether Inst is a tail call instruction.
Definition: TargetInstrInfo.h:1873
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_INVALID
@ PRED_INVALID
Definition: TargetInstrInfo.h:642
llvm::TargetInstrInfo::~TargetInstrInfo
virtual ~TargetInstrInfo()
Definition: TargetInstrInfo.cpp:43
llvm::TargetInstrInfo::analyzeSelect
virtual bool analyzeSelect(const MachineInstr &MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const
Analyze the given select instruction, returning true if it cannot be understood.
Definition: TargetInstrInfo.h:922
llvm::TargetInstrInfo::isProfitableToDupForIfCvt
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, BranchProbability Probability) const
Return true if it's profitable for if-converter to duplicate instructions of specified accumulated in...
Definition: TargetInstrInfo.h:821
llvm::TargetInstrInfo::shouldScheduleLoadsNear
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const
This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePt...
Definition: TargetInstrInfo.h:1323
MachineCombinerPattern.h
llvm::TargetInstrInfo::isStackSlotCopy
virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const
Return true if the specified machine instruction is a copy of one stack slot to another and has no ot...
Definition: TargetInstrInfo.h:336
llvm::TargetInstrInfo::reverseBranchCondition
virtual bool reverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const
Reverses the branch condition of the specified condition list, returning false on success and true if...
Definition: TargetInstrInfo.h:1407
llvm::TargetInstrInfo::defaultDefLatency
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
Definition: TargetInstrInfo.cpp:1131
llvm::TargetInstrInfo::PipelinerLoopInfo::disposed
virtual void disposed()=0
Called when the loop is being removed.
llvm::TargetInstrInfo::shouldSink
virtual bool shouldSink(const MachineInstr &MI) const
Return true if the instruction should be sunk by MachineSink.
Definition: TargetInstrInfo.h:383
llvm::None
const NoneType None
Definition: None.h:23
llvm::lltok::Kind
Kind
Definition: LLToken.h:18
llvm::TargetInstrInfo::optimizeSelect
virtual MachineInstr * optimizeSelect(MachineInstr &MI, SmallPtrSetImpl< MachineInstr * > &NewMIs, bool PreferFalse=false) const
Given a select instruction that was understood by analyzeSelect and returned Optimizable = true,...
Definition: TargetInstrInfo.h:945
BranchProbability.h
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::TargetInstrInfo::isExtendLikelyToBeFolded
virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, MachineRegisterInfo &MRI) const
Given the generic extension instruction ExtMI, returns true if this extension is a likely candidate f...
Definition: TargetInstrInfo.h:1970
llvm::TargetInstrInfo::MachineBranchPredicate::PRED_EQ
@ PRED_EQ
Definition: TargetInstrInfo.h:640
llvm::TargetInstrInfo::hasReassociableOperands
virtual bool hasReassociableOperands(const MachineInstr &Inst, const MachineBasicBlock *MBB) const
Return true when \P Inst has reassociable operands in the same \P MBB.
Definition: TargetInstrInfo.cpp:700
llvm::TargetInstrInfo::isCoalescableExtInstr
virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const
Return true if the instruction is a "coalescable" extension instruction.
Definition: TargetInstrInfo.h:252
llvm::TargetInstrInfo::getBranchDestBlock
virtual MachineBasicBlock * getBranchDestBlock(const MachineInstr &MI) const
Definition: TargetInstrInfo.h:581
llvm::TargetInstrInfo::analyzeLoopForPipelining
virtual std::unique_ptr< PipelinerLoopInfo > analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const
Analyze loop L, which must be a single-basic-block loop, and if the conditions can be understood enou...
Definition: TargetInstrInfo.h:752
llvm::TargetInstrInfo::MachineBranchPredicate::SingleUseCondition
bool SingleUseCondition
SingleUseCondition is true if ConditionDef is dead except for the branch(es) at the end of the basic ...
Definition: TargetInstrInfo.h:655
llvm::TargetInstrInfo::RegSubRegPair::RegSubRegPair
RegSubRegPair(Register Reg=Register(), unsigned SubReg=0)
Definition: TargetInstrInfo.h:481
llvm::TargetInstrInfo::getBaseAndOffsetPosition
virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos, unsigned &OffsetPos) const
Return true if the instruction contains a base register and offset.
Definition: TargetInstrInfo.h:1354
llvm::CmpInst
This class is the base class for the comparison instructions.
Definition: InstrTypes.h:710
llvm::TargetInstrInfo::createMIROperandComment
virtual std::string createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx, const TargetRegisterInfo *TRI) const
Definition: TargetInstrInfo.cpp:1343
llvm::TargetInstrInfo::isStoreToStackSlot
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const
Optional extension of isStoreToStackSlot that returns the number of bytes stored to the stack.
Definition: TargetInstrInfo.h:309
llvm::TargetInstrInfo::isStoreToStackSlot
virtual unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct store to a stack slot, return the virtual or physica...
Definition: TargetInstrInfo.h:300
llvm::TargetInstrInfo::getOutliningType
virtual outliner::InstrType getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const
Returns how or if MI should be outlined.
Definition: TargetInstrInfo.h:1916
llvm::TargetInstrInfo::isAssociativeAndCommutative
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const
Return true when \P Inst is both associative and commutative.
Definition: TargetInstrInfo.h:1147
llvm::TargetInstrInfo::PredicateInstruction
virtual bool PredicateInstruction(MachineInstr &MI, ArrayRef< MachineOperand > Pred) const
Convert the instruction into a predicated instruction.
Definition: TargetInstrInfo.cpp:331
llvm::TargetInstrInfo::canMakeTailCallConditional
virtual bool canMakeTailCallConditional(SmallVectorImpl< MachineOperand > &Cond, const MachineInstr &TailCall) const
Returns true if the tail call can be made conditional on BranchCond.
Definition: TargetInstrInfo.h:1444
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getHashValue
static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val)
Reuse getHashValue implementation from std::pair<unsigned, unsigned>.
Definition: TargetInstrInfo.h:2018
llvm::TargetInstrInfo::getStackSlotRange
virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const MachineFunction &MF) const
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
Definition: TargetInstrInfo.cpp:389
llvm::TargetInstrInfo::getSerializableBitmaskMachineOperandTargetFlags
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableBitmaskMachineOperandTargetFlags() const
Return an array that contains the bitmask target flag values and their names.
Definition: TargetInstrInfo.h:1856
llvm::MachineLoop
Definition: MachineLoopInfo.h:45
llvm::TargetInstrInfo::RegSubRegPair::Reg
Register Reg
Definition: TargetInstrInfo.h:478
llvm::TargetSchedModel
Provide an instruction scheduling machine model to CodeGen passes.
Definition: TargetSchedule.h:31
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
VirtRegMap.h
llvm::ExtAddrMode::BaseReg
Register BaseReg
Definition: TargetInstrInfo.h:87
llvm::TargetInstrInfo::isPredicated
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Definition: TargetInstrInfo.h:1427
llvm::TargetInstrInfo::getAddrModeFromMemoryOp
virtual Optional< ExtAddrMode > getAddrModeFromMemoryOp(const MachineInstr &MemI, const TargetRegisterInfo *TRI) const
Target dependent implementation to get the values constituting the address MachineInstr that is acces...
Definition: TargetInstrInfo.h:1365
llvm::TargetInstrInfo::TargetInstrInfo
TargetInstrInfo(unsigned CFSetupOpcode=~0u, unsigned CFDestroyOpcode=~0u, unsigned CatchRetOpcode=~0u, unsigned ReturnOpcode=~0u)
Definition: TargetInstrInfo.h:99
llvm::outliner::Candidate
An individual sequence of instructions to be replaced with a call to an outlined function.
Definition: MachineOutliner.h:38
llvm::TargetInstrInfo::breakPartialRegDependency
virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const
Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
Definition: TargetInstrInfo.h:1770
llvm::TargetInstrInfo::insertOutlinedCall
virtual MachineBasicBlock::iterator insertOutlinedCall(Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It, MachineFunction &MF, const outliner::Candidate &C) const
Insert a call to an outlined function into the program.
Definition: TargetInstrInfo.h:1939
llvm::DenseMap< unsigned, unsigned >
llvm::TargetInstrInfo::isMBBSafeToOutlineFrom
virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, unsigned &Flags) const
Optional target hook that returns true if MBB is safe to outline from, and returns any target-specifi...
Definition: TargetInstrInfo.h:1923
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::RegScavenger
Definition: RegisterScavenging.h:34
llvm::TargetInstrInfo::hasStoreToStackSlot
virtual bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a store to a stack slot, return true along with the FrameInd...
Definition: TargetInstrInfo.cpp:375
ArrayRef.h
llvm::TargetInstrInfo::isStoreToStackSlotPostFE
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition: TargetInstrInfo.h:318
llvm::ParamLoadedValue
std::pair< MachineOperand, DIExpression * > ParamLoadedValue
Definition: TargetInstrInfo.h:66
llvm::TargetInstrInfo::commuteInstruction
MachineInstr * commuteInstruction(MachineInstr &MI, bool NewMI=false, unsigned OpIdx1=CommuteAnyOperandIndex, unsigned OpIdx2=CommuteAnyOperandIndex) const
This method commutes the operands of the given machine instruction MI.
Definition: TargetInstrInfo.cpp:250
llvm::TargetInstrInfo::isAsCheapAsAMove
virtual bool isAsCheapAsAMove(const MachineInstr &MI) const
Return true if the instruction is as cheap as a move instruction.
Definition: TargetInstrInfo.h:374
RegSubRegPair
TargetInstrInfo::RegSubRegPair RegSubRegPair
Definition: PeepholeOptimizer.cpp:101
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::TargetInstrInfo::getInstSizeInBytes
virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const
Returns the size in bytes of the specified MachineInstr, or ~0U when this function is not implemented...
Definition: TargetInstrInfo.h:366
llvm::TargetInstrInfo::insertUnconditionalBranch
unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, MachineBasicBlock *DestBB, const DebugLoc &DL, int *BytesAdded=nullptr) const
Definition: TargetInstrInfo.h:704
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:30
llvm::TargetInstrInfo::describeLoadedValue
virtual Optional< ParamLoadedValue > describeLoadedValue(const MachineInstr &MI, Register Reg) const
Produce the expression describing the MI loading a value into the physical register Reg.
Definition: TargetInstrInfo.cpp:1170
llvm::TargetInstrInfo::MachineBranchPredicate::ComparePredicate
ComparePredicate
Definition: TargetInstrInfo.h:639
llvm::TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo
virtual ~PipelinerLoopInfo()
Definition: TargetInstrInfo.cpp:1398
llvm::TargetInstrInfo::isLoadFromStackSlotPostFE
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const
Check for post-frame ptr elimination stack locations as well.
Definition: TargetInstrInfo.h:280
MIRFormatter.h
llvm::TargetInstrInfo::getSerializableMachineMemOperandTargetFlags
virtual ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > getSerializableMachineMemOperandTargetFlags() const
Return an array that contains the MMO target flag values and their names.
Definition: TargetInstrInfo.h:1866
llvm::TargetInstrInfo::isPCRelRegisterOperandLegal
virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const
Allow targets to tell MachineVerifier whether a specific register MachineOperand can be used as part ...
Definition: TargetInstrInfo.h:976
llvm::TargetInstrInfo::produceSameValue
virtual bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1, const MachineRegisterInfo *MRI=nullptr) const
Return true if two machine instructions would produce identical values.
Definition: TargetInstrInfo.cpp:429
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::TargetInstrInfo::createPHISourceCopy
virtual MachineInstr * createPHISourceCopy(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const
During PHI eleimination lets target to make necessary checks and insert the copy to the PHI destinati...
Definition: TargetInstrInfo.h:1897
llvm::RegImmPair
Used to describe a register and immediate addition.
Definition: TargetInstrInfo.h:77
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::MachineInstr::isReturn
bool isReturn(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:813
llvm::TargetInstrInfo::getPatchpointUnfoldableRange
virtual std::pair< unsigned, unsigned > getPatchpointUnfoldableRange(const MachineInstr &MI) const
For a patchpoint, stackmap, or statepoint intrinsic, return the range of operands which can't be fold...
Definition: TargetInstrInfo.cpp:478
llvm::TargetInstrInfo::MachineBranchPredicate::Predicate
ComparePredicate Predicate
Definition: TargetInstrInfo.h:645
llvm::MachineFunction
Definition: MachineFunction.h:230
llvm::TargetInstrInfo::isLegalToSplitMBBAt
virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const
Return true if it's legal to split the given basic block at the specified instruction (i....
Definition: TargetInstrInfo.h:785
llvm::TargetInstrInfo::analyzeLoop
virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, MachineInstr *&CmpInst) const
Analyze the loop code, return true if it cannot be understood.
Definition: TargetInstrInfo.h:759
llvm::TargetInstrInfo::getSPAdjust
virtual int getSPAdjust(const MachineInstr &MI) const
Returns the actual stack pointer adjustment made by an instruction as part of a call sequence.
Definition: TargetInstrInfo.cpp:993
llvm::ScheduleDAG
Definition: ScheduleDAG.h:555
llvm::TargetInstrInfo::getPredicationCost
virtual unsigned getPredicationCost(const MachineInstr &MI) const
Definition: TargetInstrInfo.cpp:1142
llvm::TargetInstrInfo::hasLoadFromStackSlot
virtual bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const
If the specified machine instruction has a load from a stack slot, return true along with the FrameIn...
Definition: TargetInstrInfo.cpp:361
llvm::TargetInstrInfo::ClobbersPredicate
virtual bool ClobbersPredicate(MachineInstr &MI, std::vector< MachineOperand > &Pred, bool SkipDead) const
If the specified instruction defines any predicate or condition code register(s) used for predication...
Definition: TargetInstrInfo.h:1475
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
None.h
llvm::TargetInstrInfo::RegSubRegPair::SubReg
unsigned SubReg
Definition: TargetInstrInfo.h:479
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition: AArch64SLSHardening.cpp:75
llvm::CallingConv::Tail
@ Tail
Tail - This calling convention attemps to make calls as fast as possible while guaranteeing that tail...
Definition: CallingConv.h:81
llvm::TargetInstrInfo::getTailDuplicateSize
virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const
Returns the target-specific default value for tail duplication.
Definition: TargetInstrInfo.h:1986
llvm::TargetInstrInfo::reMaterialize
virtual void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, unsigned SubIdx, const MachineInstr &Orig, const TargetRegisterInfo &TRI) const
Re-issue the specified 'original' instruction at the specific location targeting a new destination re...
Definition: TargetInstrInfo.cpp:419
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:136
llvm::TargetInstrInfo::storeRegToStackSlot
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const
Store the specified register of the given register class to the specified stack frame index.
Definition: TargetInstrInfo.h:1037
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetInstrInfo::extraSizeToPredicateInstructions
virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, unsigned NumInsts) const
Return the increase in code size needed to predicate a contiguous run of NumInsts instructions.
Definition: TargetInstrInfo.h:829
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
Module
Machine Check Debug Module
Definition: MachineCheckDebugify.cpp:122
Node
Definition: ItaniumDemangle.h:234
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::TargetInstrInfo::isUnpredicatedTerminator
bool isUnpredicatedTerminator(const MachineInstr &MI) const
Returns true if the instruction is a terminator instruction that has not been predicated.
Definition: TargetInstrInfo.cpp:320
llvm::MipsISD::TailCall
@ TailCall
Definition: MipsISelLowering.h:65
llvm::TargetInstrInfo::isFrameInstr
bool isFrameInstr(const MachineInstr &I) const
Returns true if the argument is a frame pseudo instruction.
Definition: TargetInstrInfo.h:202
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:59
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getEmptyKey
static TargetInstrInfo::RegSubRegPair getEmptyKey()
Definition: TargetInstrInfo.h:2006
llvm::TargetInstrInfo::predictBranchSizeForIfCvt
virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const
Return an estimate for the code size reduction (in bytes) which will be caused by removing the given ...
Definition: TargetInstrInfo.h:836
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::TargetInstrInfo::fixCommutedOpIndices
static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, unsigned CommutableOpIdx1, unsigned CommutableOpIdx2)
Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable operand indices to (ResultIdx1,...
Definition: TargetInstrInfo.cpp:265
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::TargetInstrInfo::isTriviallyReMaterializable
bool isTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA=nullptr) const
Return true if the instruction is trivially rematerializable, meaning it has no side effects.
Definition: TargetInstrInfo.h:125
llvm::TargetInstrInfo::isProfitableToUnpredicate
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const
Return true if it's profitable to unpredicate one side of a 'diamond', i.e.
Definition: TargetInstrInfo.h:851
llvm::TargetInstrInfo::isSchedulingBoundary
virtual bool isSchedulingBoundary(const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const
Test if the given instruction should be considered a scheduling boundary.
Definition: TargetInstrInfo.cpp:1017
llvm::TargetInstrInfo::isFunctionSafeToOutlineFrom
virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, bool OutlineFromLinkOnceODRs) const
Return true if the function can safely be outlined from.
Definition: TargetInstrInfo.h:1950
llvm::ISD::FrameIndex
@ FrameIndex
Definition: ISDOpcodes.h:80
llvm::TargetInstrInfo::reduceLoopCount
virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineBasicBlock &PreHeader, MachineInstr *IndVar, MachineInstr &Cmp, SmallVectorImpl< MachineOperand > &Cond, SmallVectorImpl< MachineInstr * > &PrevInsts, unsigned Iter, unsigned MaxIter) const
Generate code to reduce the loop iteration by one and check if the loop is finished.
Definition: TargetInstrInfo.h:768
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MCInstrInfo
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:25
llvm::TargetInstrInfo::getCallFrameDestroyOpcode
unsigned getCallFrameDestroyOpcode() const
Definition: TargetInstrInfo.h:199
llvm::TargetInstrInfo::getExecutionDomain
virtual std::pair< uint16_t, uint16_t > getExecutionDomain(const MachineInstr &MI) const
Return the current execution domain and bit mask of possible domains for instruction.
Definition: TargetInstrInfo.h:1677
llvm::TargetInstrInfo::isIgnorableUse
virtual bool isIgnorableUse(const MachineOperand &MO) const
Given MO is a PhysReg use return if it can be ignored for the purpose of instruction rematerializatio...
Definition: TargetInstrInfo.h:135
llvm::TargetInstrInfo::isUnconditionalTailCall
virtual bool isUnconditionalTailCall(const MachineInstr &MI) const
Returns true if MI is an unconditional tail call.
Definition: TargetInstrInfo.h:1439
llvm::TargetInstrInfo::isProfitableToIfCvt
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, BranchProbability Probability) const
Return true if it's profitable to predicate instructions with accumulated instruction latency of "Num...
Definition: TargetInstrInfo.h:795
llvm::TargetInstrInfo::isPostIncrement
virtual bool isPostIncrement(const MachineInstr &MI) const
Return true for post-incremented instructions.
Definition: TargetInstrInfo.h:1424
uint16_t
llvm::DestSourcePair
Definition: TargetInstrInfo.h:68
llvm::TargetInstrInfo::preservesZeroValueInReg
virtual bool preservesZeroValueInReg(const MachineInstr *MI, const Register NullValueReg, const TargetRegisterInfo *TRI) const
Returns true if MI's Def is NullValueReg, and the MI does not change the Zero value.
Definition: TargetInstrInfo.h:1375
llvm::TargetInstrInfo::operator=
TargetInstrInfo & operator=(const TargetInstrInfo &)=delete
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:321
llvm::TargetInstrInfo::getMemOperandsWithOffsetWidth
virtual bool getMemOperandsWithOffsetWidth(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const
Get zero or more base operands and the byte offset of an instruction that reads/writes memory.
Definition: TargetInstrInfo.h:1344
llvm::TargetInstrInfo::setSpecialOperandAttr
virtual void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const
Definition: TargetInstrInfo.h:1191
llvm::TargetInstrInfo::analyzeBranch
virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
Definition: TargetInstrInfo.h:625
llvm::TargetInstrInfo::reassociateOps
void reassociateOps(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const
Attempt to reassociate \P Root and \P Prev according to \P Pattern to reduce critical path length.
Definition: TargetInstrInfo.cpp:807
llvm::TargetInstrInfo::getRegSequenceInputs
bool getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx.
Definition: TargetInstrInfo.cpp:1262
llvm::TargetInstrInfo::PipelinerLoopInfo::createTripCountGreaterCondition
virtual Optional< bool > createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, SmallVectorImpl< MachineOperand > &Cond)=0
Create a condition to determine if the trip count of the loop is greater than TC.
llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAGMI *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1053
llvm::ExtAddrMode::Displacement
int64_t Displacement
Definition: TargetInstrInfo.h:90
llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint
virtual bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const
Sometimes, it is possible for the target to tell, even without aliasing information,...
Definition: TargetInstrInfo.h:1791
llvm::ExtAddrMode::Scale
int64_t Scale
Definition: TargetInstrInfo.h:89
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:245
llvm::TargetInstrInfo::getInstrLatency
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Definition: TargetInstrInfo.cpp:1146
llvm::LiveIntervals
Definition: LiveIntervals.h:54
isEqual
static bool isEqual(const Function &Caller, const Function &Callee)
Definition: Attributes.cpp:1935
llvm::TargetInstrInfo::isBasicBlockPrologue
virtual bool isBasicBlockPrologue(const MachineInstr &MI) const
True if the instruction is bound to the top of its basic block and no other instructions shall be ins...
Definition: TargetInstrInfo.h:1880
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:410
llvm::TargetInstrInfo::optimizeCompareInstr
virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t Mask, int64_t Value, const MachineRegisterInfo *MRI) const
See if the comparison instruction can be converted into something more efficient.
Definition: TargetInstrInfo.h:1548
llvm::TargetInstrInfo::hasLowDefLatency
virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, const MachineInstr &DefMI, unsigned DefIdx) const
Compute operand latency of a def of 'Reg'.
Definition: TargetInstrInfo.cpp:1157
llvm::TargetInstrInfo::MachineBranchPredicate::LHS
MachineOperand LHS
Definition: TargetInstrInfo.h:646
llvm::TargetInstrInfo::getCallFrameSetupOpcode
unsigned getCallFrameSetupOpcode() const
These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise).
Definition: TargetInstrInfo.h:198
llvm::TargetInstrInfo::isUnspillableTerminatorImpl
virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const
Return true if the given terminator MI is not expected to spill.
Definition: TargetInstrInfo.h:997
llvm::TargetInstrInfo::getMIRFormatter
virtual const MIRFormatter * getMIRFormatter() const
Return MIR formatter to format/parse MIR operands.
Definition: TargetInstrInfo.h:1977
llvm::MIRFormatter
MIRFormater - Interface to format MIR operand based on target.
Definition: MIRFormatter.h:29
llvm::TargetInstrInfo::shouldReduceRegisterPressure
virtual bool shouldReduceRegisterPressure(MachineBasicBlock *MBB, RegisterClassInfo *RegClassInfo) const
Return true if target supports reassociation of instructions in machine combiner pass to reduce regis...
Definition: TargetInstrInfo.h:1124
llvm::TargetInstrInfo::PipelinerLoopInfo::setPreheader
virtual void setPreheader(MachineBasicBlock *NewPreheader)=0
Called when the loop's preheader has been modified to NewPreheader.
llvm::Pattern
Definition: FileCheckImpl.h:614
llvm::TargetInstrInfo::foldMemoryOperandImpl
virtual MachineInstr * foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Target-dependent implementation for foldMemoryOperand.
Definition: TargetInstrInfo.h:1207
llvm::DestSourcePair::Source
const MachineOperand * Source
Definition: TargetInstrInfo.h:70
llvm::TargetInstrInfo::getMemOperandAACheckLimit
virtual unsigned getMemOperandAACheckLimit() const
Return the maximal number of alias checks on memory operands.
Definition: TargetInstrInfo.h:1821
llvm::TargetInstrInfo::foldMemoryOperand
MachineInstr * foldMemoryOperand(MachineInstr &MI, ArrayRef< unsigned > Ops, int FI, LiveIntervals *LIS=nullptr, VirtRegMap *VRM=nullptr) const
Attempt to fold a load or store of the specified stack slot into the specified machine instruction fo...
Definition: TargetInstrInfo.cpp:560
MachineInstrBuilder.h
llvm::TargetInstrInfo::findCommutedOpIndices
virtual bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const
Returns true iff the routine could find two commutable operands in the given machine instruction.
Definition: TargetInstrInfo.cpp:296
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
N
#define N
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::TargetInstrInfo::genAlternativeCodeSequence
virtual void genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstIdxForVirtReg) const
When getMachineCombinerPatterns() finds patterns, this function generates the instructions that could...
Definition: TargetInstrInfo.cpp:891
llvm::TargetInstrInfo::getOperandLatency
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Definition: TargetInstrInfo.cpp:1084
llvm::DenseMapInfo< TargetInstrInfo::RegSubRegPair >::getTombstoneKey
static TargetInstrInfo::RegSubRegPair getTombstoneKey()
Definition: TargetInstrInfo.h:2011
llvm::TargetInstrInfo::isFrameSetup
bool isFrameSetup(const MachineInstr &I) const
Returns true if the argument is a frame setup pseudo instruction.
Definition: TargetInstrInfo.h:208
llvm::TargetInstrInfo::PipelinerLoopInfo::shouldIgnoreForPipelining
virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const =0
Return true if the given instruction should not be pipelined and should be ignored.
llvm::TargetInstrInfo::insertIndirectBranch
virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset=0, RegScavenger *RS=nullptr) const
Insert an unconditional indirect branch at the end of MBB to NewDestBB.
Definition: TargetInstrInfo.h:590
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const
Allocate and return a hazard recognizer to use for by non-scheduling passes.
Definition: TargetInstrInfo.h:1527
llvm::RegImmPair::RegImmPair
RegImmPair(Register Reg, int64_t Imm)
Definition: TargetInstrInfo.h:81
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::TargetInstrInfo::CreateTargetPostRAHazardRecognizer
virtual ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const
Allocate and return a hazard recognizer to use for this target when scheduling the machine instructio...
Definition: TargetInstrInfo.cpp:1060
llvm::TargetInstrInfo::setExecutionDomain
virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const
Change the opcode of MI to execute in Domain.
Definition: TargetInstrInfo.h:1685
MachineOperand.h
DenseMapInfo.h
llvm::SmallPtrSetImpl
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
llvm::TargetInstrInfo::MachineBranchPredicate::TrueDest
MachineBasicBlock * TrueDest
Definition: TargetInstrInfo.h:648
llvm::LiveVariables
Definition: LiveVariables.h:46
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:62
llvm::DestSourcePair::DestSourcePair
DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src)
Definition: TargetInstrInfo.h:72
llvm::TargetInstrInfo::getSerializableDirectMachineOperandTargetFlags
virtual ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags() const
Return an array that contains the direct target flag values and their names.
Definition: TargetInstrInfo.h:1846
llvm::TargetInstrInfo::getOpcodeAfterMemoryUnfold
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const
Returns the opcode of the would be new instruction after load / store are unfolded from an instructio...
Definition: TargetInstrInfo.h:1300
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::TargetInstrInfo::CommuteAnyOperandIndex
static const unsigned CommuteAnyOperandIndex
Definition: TargetInstrInfo.h:424
llvm::TargetInstrInfo::isReallyTriviallyReMaterializable
virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, AAResults *AA) const
For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target...
Definition: TargetInstrInfo.h:146
MachineFunction.h
llvm::ScheduleHazardRecognizer
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
Definition: ScheduleHazardRecognizer.h:25
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::TargetInstrInfo::isAddImmediate
virtual Optional< RegImmPair > isAddImmediate(const MachineInstr &MI, Register Reg) const
If the specific machine instruction is an instruction that adds an immediate value and a physical reg...
Definition: TargetInstrInfo.h:1019
llvm::TargetInstrInfo::finalizeInsInstrs
virtual void finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, SmallVectorImpl< MachineInstr * > &InsInstrs) const
Fix up the placeholder we may add in genAlternativeCodeSequence().
Definition: TargetInstrInfo.h:1131
llvm::TargetInstrInfo::MachineBranchPredicate::MachineBranchPredicate
MachineBranchPredicate()=default
llvm::Value
LLVM Value Representation.
Definition: Value.h:75
llvm::TargetInstrInfo::SubsumesPredicate
virtual bool SubsumesPredicate(ArrayRef< MachineOperand > Pred1, ArrayRef< MachineOperand > Pred2) const
Returns true if the first specified predicate subsumes the second, e.g.
Definition: TargetInstrInfo.h:1463
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::TargetInstrInfo::isProfitableToIfCvt
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) const
Second variant of isProfitableToIfCvt.
Definition: TargetInstrInfo.h:807
llvm::TargetInstrInfo::getExtractSubregLikeInputs
virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const
Target-dependent implementation of getExtractSubregInputs.
Definition: TargetInstrInfo.h:1249
llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx
unsigned SubIdx
Definition: TargetInstrInfo.h:496
llvm::TargetInstrInfo::getInlineAsmLength
virtual unsigned getInlineAsmLength(const char *Str, const MCAsmInfo &MAI, const TargetSubtargetInfo *STI=nullptr) const
Measure the specified inline asm to determine an approximation of its length.
Definition: TargetInstrInfo.cpp:100
llvm::TargetInstrInfo::isLoadFromStackSlot
virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const
If the specified machine instruction is a direct load from a stack slot, return the virtual or physic...
Definition: TargetInstrInfo.h:262
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:23
llvm::TargetInstrInfo::getSerializableTargetIndices
virtual ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices() const
Return an array that contains the ids of the target indices (used for the TargetIndex machine operand...
Definition: TargetInstrInfo.h:1829
llvm::MachineCombinerPattern
MachineCombinerPattern
These are instruction patterns matched by the machine combiner pass.
Definition: MachineCombinerPattern.h:20
MachineOutliner.h