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74 #ifndef LLVM_CODEGEN_MACHINESCHEDULER_H
75 #define LLVM_CODEGEN_MACHINESCHEDULER_H
114 class MachineDominatorTree;
115 class MachineFunction;
117 class MachineLoopInfo;
118 class RegisterClassInfo;
119 class SchedDFSResult;
120 class ScheduleHazardRecognizer;
121 class TargetInstrInfo;
122 class TargetPassConfig;
123 class TargetRegisterInfo;
145 ScheduleDAGInstrs *(*)(MachineSchedContext *)> {
209 virtual void anchor();
217 unsigned NumRegionInstrs) {}
280 std::vector<std::unique_ptr<ScheduleDAGMutation>>
Mutations;
292 #if LLVM_ENABLE_ABI_BREAKING_CHECKS
295 unsigned NumInstrsScheduled = 0;
311 return SchedImpl->doMBBSchedRegionsTopDown();
339 unsigned regioninstrs)
override;
435 std::unique_ptr<MachineSchedStrategy>
S)
485 unsigned regioninstrs)
override;
494 void dump()
const override;
519 const std::vector<unsigned> &NewMaxPressure);
540 std::vector<SUnit*> Queue;
552 bool empty()
const {
return Queue.empty(); }
556 unsigned size()
const {
return Queue.size(); }
574 (*I)->NodeQueueId &= ~
ID;
576 unsigned idx =
I - Queue.begin();
578 return Queue.begin() + idx;
646 unsigned MinReadyCycle;
649 unsigned ExpectedLatency;
654 unsigned DependentLatency;
658 unsigned RetiredMOps;
668 unsigned MaxExecutedResCount;
671 unsigned ZoneCritResIdx;
674 bool IsResourceLimited;
712 #if LLVM_ENABLE_ABI_BREAKING_CHECKS
715 unsigned MaxObservedStall;
750 return std::max(ExpectedLatency, CurrCycle);
758 return ExecutedResCounts[ResIdx];
774 MaxExecutedResCount);
820 unsigned Cycles,
unsigned ReadyCycle);
868 return !(*
this ==
RHS);
956 bool shouldReduceLatency(
const CandPolicy &Policy,
SchedBoundary &CurrZone,
957 bool ComputeRemLatency,
unsigned &RemLatency)
const;
961 bool tryLess(
int TryVal,
int CandVal,
962 GenericSchedulerBase::SchedCandidate &TryCand,
963 GenericSchedulerBase::SchedCandidate &Cand,
966 GenericSchedulerBase::SchedCandidate &TryCand,
967 GenericSchedulerBase::SchedCandidate &Cand,
969 bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
970 GenericSchedulerBase::SchedCandidate &Cand,
971 SchedBoundary &Zone);
973 const PressureChange &CandP,
974 GenericSchedulerBase::SchedCandidate &TryCand,
975 GenericSchedulerBase::SchedCandidate &Cand,
977 const TargetRegisterInfo *
TRI,
978 const MachineFunction &MF);
992 unsigned NumRegionInstrs)
override;
1048 virtual bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand,
1056 SchedCandidate &Candidate);
1080 unsigned NumRegionInstrs)
override {
1111 virtual bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand);
1124 std::unique_ptr<ScheduleDAGMutation>
1126 const TargetRegisterInfo *
TRI);
1128 std::unique_ptr<ScheduleDAGMutation>
1130 const TargetRegisterInfo *
TRI);
1132 std::unique_ptr<ScheduleDAGMutation>
1134 const TargetRegisterInfo *
TRI);
1138 #endif // LLVM_CODEGEN_MACHINESCHEDULER_H
void updateScheduledPressure(const SUnit *SU, const std::vector< unsigned > &NewMaxPressure)
void updateQueues(SUnit *SU, bool IsTopNode)
Update scheduler DAG and queues after scheduling an instruction.
IntervalPressure RegPressure
unsigned DemandedResources
CandReason
Represent the type of SchedCandidate found within a single queue.
virtual ~MachineSchedStrategy()=default
const TargetRegisterInfo * TRI
Base class for GenericScheduler.
virtual ~MachineSchedContext()
const IntervalPressure & getRegPressure() const
Get register pressure for the entire scheduling region before scheduling.
~ScheduleDAGMILive() override
void setBest(SchedCandidate &Best)
void viewGraph() override
Out-of-line implementation with no arguments is handy for gdb.
This is an optimization pass for GlobalISel generic memory operations.
ScheduleHazardRecognizer * HazardRec
void scheduleMI(SUnit *SU, bool IsTopNode)
Move an instruction and update register pressure.
bool isInQueue(SUnit *SU) const
const MachineLoopInfo * MLI
RegisterClassInfo * RegClassInfo
unsigned getCriticalCount() const
Get the scaled count of scheduled micro-ops and resources, including executed resources.
virtual void initialize(ScheduleDAGMI *DAG)=0
Initialize the strategy after building the DAG for a new region.
MachineBasicBlock::iterator begin() const
Returns an iterator to the top of the current scheduling region.
bool shouldTrackPressure() const override
PostRA scheduling does not track pressure.
List of PressureChanges in order of increasing, unique PSetID.
void reset(const CandPolicy &NewPolicy)
void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel)
std::pair< unsigned, unsigned > getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx, unsigned Cycles)
Compute the next cycle at which the given processor resource can be scheduled.
MachineSchedRegistry provides a selection of available machine instruction schedulers.
bool operator!=(const CandPolicy &RHS) const
SmallVector< SUnit *, 8 > BotRoots
const TargetSchedModel * SchedModel
cl::opt< bool > ForceTopDown
bool tryGreater(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
virtual bool hasVRegLiveness() const
Return true if this DAG supports VReg liveness and RegPressure.
void initialize(ScheduleDAGMI *Dag) override
Initialize the strategy after building the DAG for a new region.
virtual bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand, SchedBoundary *Zone) const
Apply a set of heuristics to a new candidate.
RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.
PressureDiffs SUPressureDiffs
void releasePredecessors(SUnit *SU)
releasePredecessors - Call releasePred on each of SU's predecessors.
void postprocessDAG()
Apply each ScheduleDAGMutation step in order.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Track the current register pressure at some position in the instruction stream, and remember the high...
void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone, SchedBoundary *OtherZone)
Set the CandPolicy given a scheduling zone given the current resources and latencies inside and outsi...
void registerRoots() override
Notify this strategy that all roots have been released (including those that depend on EntrySU or Exi...
void initialize(ScheduleDAGMI *dag) override
Initialize the strategy after building the DAG for a new region.
void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos)
Change the position of an instruction within the basic block and update live ranges and region bounda...
static MachinePassRegistry< ScheduleDAGCtor > Registry
SchedResourceDelta()=default
unsigned countResource(const MCSchedClassDesc *SC, unsigned PIdx, unsigned Cycles, unsigned ReadyCycle)
Add the given processor resource to this scheduled zone.
PressureDiff & getPressureDiff(const SUnit *SU)
unsigned getDepth() const
Returns the depth of this node, which is the length of the maximum path up to any node which has no p...
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
void computeDFSResult()
Compute a DFSResult after DAG building is complete, and before any queue comparisons.
MachineBasicBlock::iterator CurrentBottom
The bottom of the unscheduled zone.
static MachineSchedRegistry * getList()
void initCandidate(SchedCandidate &Cand, SUnit *SU, bool AtTop, const RegPressureTracker &RPTracker, RegPressureTracker &TempTracker)
RegPressureTracker TopRPTracker
virtual void releaseTopNode(SUnit *SU)=0
When all predecessor dependencies have been resolved, free this node for top-down scheduling.
void releaseSucc(SUnit *SU, SDep *SuccEdge)
ReleaseSucc - Decrement the NumPredsLeft count of a successor.
virtual void schedNode(SUnit *SU, bool IsTopNode)=0
Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an instruction and updated scheduled/rem...
unsigned const TargetRegisterInfo * TRI
void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override
Implement the ScheduleDAGInstrs interface for handling the next scheduling region.
MachineBasicBlock::iterator end() const
Returns an iterator to the bottom of the current scheduling region.
void releaseSuccessors(SUnit *SU)
releaseSuccessors - Call releaseSucc on each of SU's successors.
void initQueues(ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)
Release ExitSU predecessors and setup scheduler queues.
const MCProcResourceDesc * getProcResource(unsigned PIdx) const
Get a processor resource by ID for convenience.
iterator remove(iterator I)
std::vector< std::unique_ptr< ScheduleDAGMutation > > Mutations
Ordered list of DAG postprocessing steps.
static void setListener(MachinePassRegistryListener< FunctionPassCtor > *L)
std::vector< PressureChange > RegionCriticalPSets
List of pressure sets that exceed the target's pressure limit before scheduling, listed in increasing...
void dumpPolicy() const override
SchedCandidate TopCand
Candidate last picked from Top boundary.
void dump() const override
void reschedulePhysReg(SUnit *SU, bool isTop)
< i1 > br i1 label label bb bb
unsigned BotReadyCycle
Cycle relative to end when node is ready.
MachineSchedStrategy - Interface to the scheduling algorithm used by ScheduleDAGMI.
const IntervalPressure & getBotPressure() const
Get current register pressure for the bottom scheduled instructions.
const IntervalPressure & getTopPressure() const
Get current register pressure for the top scheduled instructions.
PostGenericScheduler(const MachineSchedContext *C)
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
cl::opt< bool > PrintDAGs
unsigned getExecutedCount() const
Get a scaled count for the minimum execution time of the scheduled micro-ops that are ready to execut...
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling.
(vector float) vec_cmpeq(*A, *B) C
const SUnit * NextClusterPred
Record the next node in a scheduled cluster.
bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, SchedBoundary &Zone)
bool IsAcyclicLatencyLimited
unsigned NodeNum
Entry # of node in the node vector.
virtual void initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs)
Optionally override the per-region scheduling policy.
Summarize the scheduling resources required for an instruction of a particular scheduling class.
virtual void releaseBottomNode(SUnit *SU)=0
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
void findRootsAndBiasEdges(SmallVectorImpl< SUnit * > &TopRoots, SmallVectorImpl< SUnit * > &BotRoots)
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
const HexagonInstrInfo * TII
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void updatePressureDiffs(ArrayRef< RegisterMaskPair > LiveUses)
Update the PressureDiff array for liveness after scheduling this instruction.
BitVector & getScheduledTrees()
bool DisableLatencyHeuristic
Policy for scheduling the next instruction in the candidate's zone.
bool shouldTrackPressure() const override
Check if pressure tracking is needed before building the DAG and initializing this strategy.
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
unsigned getCurrCycle() const
Number of cycles to issue the instructions scheduled in this zone.
void dumpScheduleTraceTopDown() const
Print execution trace of the schedule top-down or bottom-up.
bool hasVRegLiveness() const override
Return true if this DAG supports VReg liveness and RegPressure.
void startBlock(MachineBasicBlock *bb) override
Prepares to perform scheduling in the given block.
void initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) override
Optionally override the per-region scheduling policy.
virtual bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand)
Apply a set of heuristics to a new candidate for PostRA scheduling.
~PostGenericScheduler() override=default
void dumpScheduledState() const
void initQueues(ArrayRef< SUnit * > TopRoots, ArrayRef< SUnit * > BotRoots)
Release ExitSU predecessors and setup scheduler queues.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
void releasePending()
Release pending ready nodes in to the available queue.
MachinePassRegistryNode - Machine pass node stored in registration list.
RegPressureTracker RPTracker
MachineSchedPolicy RegionPolicy
void initPolicy(MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, unsigned NumRegionInstrs) override
Initialize the per-region scheduling policy.
SchedCandidate(const CandPolicy &Policy)
unsigned getHeight() const
Returns the height of this node, which is the length of the maximum path down to any node which has n...
unsigned TopReadyCycle
Cycle relative to start when node is ready.
RegisterClassInfo * RegClassInfo
unsigned getZoneCritResIdx() const
Target-Independent Code Generator Pass Configuration Options.
bool tryLess(int TryVal, int CandVal, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason)
Return true if this heuristic determines order.
virtual void dumpPolicy() const
Store the state used by GenericScheduler heuristics, required for the lifetime of one invocation of p...
ReadyQueue(unsigned id, const Twine &name)
virtual void enterMBB(MachineBasicBlock *MBB)
Tell the strategy that MBB is about to be processed.
bool shouldTrackLaneMasks() const override
Returns true if lanemasks should be tracked.
Provide an instruction scheduling machine model to CodeGen passes.
GenericScheduler(const MachineSchedContext *C)
Representation of each machine instruction.
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
auto find(R &&Range, const T &Val)
Provide wrappers to std::find which take ranges instead of having to pass begin/end explicitly.
GenericSchedulerBase(const MachineSchedContext *C)
const TargetSchedModel * SchedModel
virtual void registerRoots()
Notify this strategy that all roots have been released (including those that depend on EntrySU or Exi...
virtual void scheduleTree(unsigned SubtreeID)
Scheduler callback to notify that a new subtree is scheduled.
void init(ScheduleDAGMI *dag, const TargetSchedModel *smodel, SchedRemainder *rem)
const MachineSchedContext * Context
bool tryPressure(const PressureChange &TryP, const PressureChange &CandP, GenericSchedulerBase::SchedCandidate &TryCand, GenericSchedulerBase::SchedCandidate &Cand, GenericSchedulerBase::CandReason Reason, const TargetRegisterInfo *TRI, const MachineFunction &MF)
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
PostGenericScheduler - Interface to the scheduling algorithm used by ScheduleDAGMI.
void registerRoots() override
Notify this strategy that all roots have been released (including those that depend on EntrySU or Exi...
void releaseTopNode(SUnit *SU) override
When all predecessor dependencies have been resolved, free this node for top-down scheduling.
unsigned getLatencyStallCycles(SUnit *SU)
Get the difference between the given SUnit's ready time and the current cycle.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
bool isScheduled
True once scheduled.
unsigned getCurrMOps() const
Micro-ops issued in the current cycle.
void incExecutedResources(unsigned PIdx, unsigned Count)
LiveIntervals * getLIS() const
Summarize the unscheduled region.
SchedDFSResult * DFSResult
Information about DAG subtrees.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
const std::vector< PressureChange > & getRegionCriticalPSets() const
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
void dumpSchedule() const
dump the scheduled Sequence.
std::unique_ptr< MachineSchedStrategy > SchedImpl
SchedCandidate BotCand
Candidate last picked from Bot boundary.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
StringRef getName() const
void placeDebugValues()
Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S, bool RemoveKillFlags)
void schedNode(SUnit *SU, bool IsTopNode) override
Called after ScheduleDAGMI has scheduled an instruction and updated scheduled/remaining flags in the ...
bool doMBBSchedRegionsTopDown() const override
If this method returns true, handling of the scheduling regions themselves (in case of a scheduling b...
void pickNodeFromQueue(SchedCandidate &Cand)
const MachineDominatorTree * MDT
void releasePred(SUnit *SU, SDep *PredEdge)
ReleasePred - Decrement the NumSuccsLeft count of a predecessor.
virtual SUnit * pickNode(bool &IsTopNode)=0
Pick the next node to schedule, or return NULL.
bool operator!=(const SchedResourceDelta &RHS) const
cl::opt< bool > ForceBottomUp
void dumpReservedCycles() const
Dump the state of the information that tracks resource usage.
void releaseBottomNode(SUnit *SU) override
When all successor dependencies have been resolved, free this node for bottom-up scheduling.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
SUnit * pickNode(bool &IsTopNode) override
Pick the best node to balance the schedule. Implements MachineSchedStrategy.
unsigned getMicroOpFactor() const
Multiply number of micro-ops by this factor to normalize it relative to other resources.
void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs) override
Implement the ScheduleDAGInstrs interface for handling the next scheduling region.
StringRef - Represent a constant reference to a string, i.e.
const RegPressureTracker & getBotRPTracker() const
unsigned getLatencyFactor() const
Multiply cycle count by this factor to normalize it relative to other resources.
MachineFunction & MF
Machine function.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
bool checkHazard(SUnit *SU)
Does this SU have a hazard within the current instruction group.
void bumpCycle(unsigned NextCycle)
Move the boundary of scheduled code by one cycle.
bool ShouldTrackLaneMasks
int biasPhysReg(const SUnit *SU, bool isTop)
Minimize physical register live ranges.
const unsigned * SubUnitsIdxBegin
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
void dumpScheduleTraceBottomUp() const
void traceCandidate(const SchedCandidate &Cand)
MachineBasicBlock::iterator CurrentTop
The top of the unscheduled zone.
SchedResourceDelta ResDelta
const SUnit * NextClusterSucc
SchedBoundary(unsigned ID, const Twine &Name)
Pending queues extend the ready queues with the same ID and the PendingFlag set.
cl::opt< bool > VerifyScheduling
SUnit * pickOnlyChoice()
Call this before applying any other heuristics to the Available queue.
ScheduleDAGMILive(MachineSchedContext *C, std::unique_ptr< MachineSchedStrategy > S)
void pickNodeFromQueue(SchedBoundary &Zone, const CandPolicy &ZonePolicy, const RegPressureTracker &RPTracker, SchedCandidate &Candidate)
Pick the best candidate from the queue.
unsigned getNextResourceCycleByInstance(unsigned InstanceIndex, unsigned Cycles)
Compute the next cycle at which the given processor resource unit can be scheduled.
bool RemoveKillFlags
True if the DAG builder should remove kill flags (in preparation for rescheduling).
std::vector< SUnit * >::iterator iterator
Store the effects of a change in pressure on things that MI scheduler cares about.
const MachineLoopInfo * MLI
void initResourceDelta(const ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel)
void bumpNode(SUnit *SU)
Move the boundary of scheduled code by one SUnit.
virtual void leaveMBB()
Tell the strategy that current MBB is done.
virtual bool shouldTrackPressure() const
Check if pressure tracking is needed before building the DAG and initializing this strategy.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
bool isResourceLimited() const
SmallVector< unsigned, 16 > RemainingCounts
MachineBasicBlock::iterator bottom() const
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
const SUnit * getNextClusterPred() const
MachineBasicBlock::iterator LiveRegionEnd
void finishBlock() override
Cleans up after scheduling in the given block.
void collectVRegUses(SUnit &SU)
const SUnit * getNextClusterSucc() const
bool isTrackingPressure() const
Return true if register pressure tracking is enabled.
Compute the values of each DAG node for various metrics during DFS.
void scheduleTree(unsigned SubtreeID) override
Scheduler callback to notify that a new subtree is scheduled.
ArrayRef< SUnit * > elements()
Each Scheduling boundary is associated with ready queues.
ScheduleDAGInstrs *(*)(MachineSchedContext *) ScheduleDAGCtor
IntervalPressure TopPressure
The top of the unscheduled zone.
unsigned getResourceCount(unsigned ResIdx) const
bool operator==(const SchedResourceDelta &RHS) const
Status of an instruction's critical resource consumption.
IntervalPressure BotPressure
The bottom of the unscheduled zone.
SUnit * pickNode(bool &IsTopNode) override
Pick the next node to schedule.
unsigned NodeQueueId
Queue id of node.
void schedule() override
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
MachineSchedPolicy()=default
bool operator==(const CandPolicy &RHS) const
RegPressureTracker BotRPTracker
A global registry used in conjunction with static constructors to make pluggable components (like tar...
bool ShouldTrackPressure
Register pressure in this region computed by initRegPressure.
const SchedDFSResult * getDFSResult() const
Return a non-null DFS result if the scheduling strategy initialized it.
ScheduleDAGCtor FunctionPassCtor
unsigned getDependentLatency() const
const RegPressureTracker & getTopRPTracker() const
bool ShouldTrackLaneMasks
Track LaneMasks to allow reordering of independent subregister writes of the same vreg.
unsigned findMaxLatency(ArrayRef< SUnit * > ReadySUs)
MachineBasicBlock::iterator top() const
void schedule() override
Implement ScheduleDAGInstrs interface for scheduling a sequence of reorderable instructions.
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
const TargetPassConfig * PassConfig
A static registration template.
MachinePassRegistryNode * getNext() const
static const char * getReasonStr(GenericSchedulerBase::CandReason Reason)
unsigned computeCyclicCriticalPath()
Compute the cyclic critical path through the DAG.
bool isUnbufferedGroup(unsigned PIdx) const
MachineSchedRegistry * getNext() const
Scheduling unit. This is a node in the scheduling DAG.
unsigned getScheduledLatency() const
Get the number of latency cycles "covered" by the scheduled instructions.
unsigned getWeakLeft(const SUnit *SU, bool isTop)
unsigned getOtherResourceCount(unsigned &OtherCritIdx)
Define a generic scheduling policy for targets that don't provide their own MachineSchedStrategy.
VReg2SUnitMultiMap VRegUses
Maps vregs to the SUnits of their uses in the current scheduling region.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
A ScheduleDAG for scheduling lists of MachineInstr.
void schedNode(SUnit *SU, bool IsTopNode) override
Update the scheduler's state after scheduling a node.
cl::opt< bool > ViewMISchedDAGs
void buildDAGWithRegPressure()
Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking enabled.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Helpers for implementing custom MachineSchedStrategy classes.
unsigned getUnscheduledLatency(SUnit *SU) const
GenericScheduler shrinks the unscheduled zone using heuristics to balance the schedule.
HazardRecognizer - This determines whether or not an instruction can be issued this cycle,...
const PressureDiff & getPressureDiff(const SUnit *SU) const
void releaseNode(SUnit *SU, unsigned ReadyCycle, bool InPQueue, unsigned Idx=0)
Release SU to make it ready.
virtual bool doMBBSchedRegionsTopDown() const
~ScheduleDAGMI() override
virtual bool shouldTrackLaneMasks() const
Returns true if lanemasks should be tracked.
void removeReady(SUnit *SU)
Remove SU from the ready set for this boundary.
void checkAcyclicLatency()
Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic critical path by more cycle...
MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
SUnit * pickNodeBidirectional(bool &IsTopNode)
Pick the best candidate node from either the top or bottom queue.