LLVM  15.0.0git
RegisterClassInfo.h
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1 //===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RegisterClassInfo class which provides dynamic
10 // information about target register classes. Callee saved and reserved
11 // registers depends on calling conventions and other dynamic information, so
12 // some things cannot be determined statically.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
17 #define LLVM_CODEGEN_REGISTERCLASSINFO_H
18 
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/MC/MCRegister.h"
24 #include <cstdint>
25 #include <memory>
26 
27 namespace llvm {
28 
30  struct RCInfo {
31  unsigned Tag = 0;
32  unsigned NumRegs = 0;
33  bool ProperSubClass = false;
34  uint8_t MinCost = 0;
35  uint16_t LastCostChange = 0;
36  std::unique_ptr<MCPhysReg[]> Order;
37 
38  RCInfo() = default;
39 
40  operator ArrayRef<MCPhysReg>() const {
41  return makeArrayRef(Order.get(), NumRegs);
42  }
43  };
44 
45  // Brief cached information for each register class.
46  std::unique_ptr<RCInfo[]> RegClass;
47 
48  // Tag changes whenever cached information needs to be recomputed. An RCInfo
49  // entry is valid when its tag matches.
50  unsigned Tag = 0;
51 
52  const MachineFunction *MF = nullptr;
53  const TargetRegisterInfo *TRI = nullptr;
54 
55  // Callee saved registers of last MF. Assumed to be valid until the next
56  // runOnFunction() call.
57  // Used only to determine if an update was made to CalleeSavedAliases.
58  const MCPhysReg *CalleeSavedRegs = nullptr;
59 
60  // Map register alias to the callee saved Register.
61  SmallVector<MCPhysReg, 4> CalleeSavedAliases;
62 
63  // Indicate if a specified callee saved register be in the allocation order
64  // exactly as written in the tablegen descriptions or listed later.
65  BitVector IgnoreCSRForAllocOrder;
66 
67  // Reserved registers in the current MF.
68  BitVector Reserved;
69 
70  std::unique_ptr<unsigned[]> PSetLimits;
71 
72  // The register cost values.
73  ArrayRef<uint8_t> RegCosts;
74 
75  // Compute all information about RC.
76  void compute(const TargetRegisterClass *RC) const;
77 
78  // Return an up-to-date RCInfo for RC.
79  const RCInfo &get(const TargetRegisterClass *RC) const {
80  const RCInfo &RCI = RegClass[RC->getID()];
81  if (Tag != RCI.Tag)
82  compute(RC);
83  return RCI;
84  }
85 
86 public:
88 
89  /// runOnFunction - Prepare to answer questions about MF. This must be called
90  /// before any other methods are used.
91  void runOnMachineFunction(const MachineFunction &MF);
92 
93  /// getNumAllocatableRegs - Returns the number of actually allocatable
94  /// registers in RC in the current function.
95  unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
96  return get(RC).NumRegs;
97  }
98 
99  /// getOrder - Returns the preferred allocation order for RC. The order
100  /// contains no reserved registers, and registers that alias callee saved
101  /// registers come last.
103  return get(RC);
104  }
105 
106  /// isProperSubClass - Returns true if RC has a legal super-class with more
107  /// allocatable registers.
108  ///
109  /// Register classes like GR32_NOSP are not proper sub-classes because %esp
110  /// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb
111  /// mode because the GPR super-class is not legal.
112  bool isProperSubClass(const TargetRegisterClass *RC) const {
113  return get(RC).ProperSubClass;
114  }
115 
116  /// getLastCalleeSavedAlias - Returns the last callee saved register that
117  /// overlaps PhysReg, or NoRegister if Reg doesn't overlap a
118  /// CalleeSavedAliases.
120  if (PhysReg.id() < CalleeSavedAliases.size())
121  return CalleeSavedAliases[PhysReg];
122  return MCRegister::NoRegister;
123  }
124 
125  /// Get the minimum register cost in RC's allocation order.
126  /// This is the smallest value in RegCosts[Reg] for all
127  /// the registers in getOrder(RC).
128  uint8_t getMinCost(const TargetRegisterClass *RC) const {
129  return get(RC).MinCost;
130  }
131 
132  /// Get the position of the last cost change in getOrder(RC).
133  ///
134  /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
135  /// same cost according to RegCosts[Reg].
136  unsigned getLastCostChange(const TargetRegisterClass *RC) const {
137  return get(RC).LastCostChange;
138  }
139 
140  /// Get the register unit limit for the given pressure set index.
141  ///
142  /// RegisterClassInfo adjusts this limit for reserved registers.
143  unsigned getRegPressureSetLimit(unsigned Idx) const {
144  if (!PSetLimits[Idx])
145  PSetLimits[Idx] = computePSetLimit(Idx);
146  return PSetLimits[Idx];
147  }
148 
149 protected:
150  unsigned computePSetLimit(unsigned Idx) const;
151 };
152 
153 } // end namespace llvm
154 
155 #endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:72
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::RegisterClassInfo::getOrder
ArrayRef< MCPhysReg > getOrder(const TargetRegisterClass *RC) const
getOrder - Returns the preferred allocation order for RC.
Definition: RegisterClassInfo.h:102
llvm::RegisterClassInfo::getLastCostChange
unsigned getLastCostChange(const TargetRegisterClass *RC) const
Get the position of the last cost change in getOrder(RC).
Definition: RegisterClassInfo.h:136
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1185
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::MCRegister::NoRegister
static constexpr unsigned NoRegister
Definition: MCRegister.h:43
llvm::dwarf::Tag
Tag
Definition: Dwarf.h:105
llvm::RegisterClassInfo::RegisterClassInfo
RegisterClassInfo()
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:45
BitVector.h
llvm::BitVector
Definition: BitVector.h:75
llvm::RegisterClassInfo::getMinCost
uint8_t getMinCost(const TargetRegisterClass *RC) const
Get the minimum register cost in RC's allocation order.
Definition: RegisterClassInfo.h:128
MCRegister.h
llvm::RegisterClassInfo::isProperSubClass
bool isProperSubClass(const TargetRegisterClass *RC) const
isProperSubClass - Returns true if RC has a legal super-class with more allocatable registers.
Definition: RegisterClassInfo.h:112
llvm::RegisterClassInfo::getNumAllocatableRegs
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
Definition: RegisterClassInfo.h:95
llvm::RegisterClassInfo::runOnMachineFunction
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
Definition: RegisterClassInfo.cpp:42
ArrayRef.h
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MCRegister::id
unsigned id() const
Definition: MCRegister.h:72
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::RegisterClassInfo::getRegPressureSetLimit
unsigned getRegPressureSetLimit(unsigned Idx) const
Get the register unit limit for the given pressure set index.
Definition: RegisterClassInfo.h:143
uint16_t
llvm::makeArrayRef
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
Definition: ArrayRef.h:475
llvm::RegisterClassInfo::getLastCalleeSavedAlias
MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const
getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg,...
Definition: RegisterClassInfo.h:119
llvm::RegisterClassInfo::computePSetLimit
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
Definition: RegisterClassInfo.cpp:183
SmallVector.h
TargetRegisterInfo.h
llvm::MCRegister
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:24