34#define DEBUG_TYPE "regalloc"
38 cl::desc(
"Limit all regclasses to N registers"));
49 if (STI.getRegisterInfo() != TRI) {
50 TRI = STI.getRegisterInfo();
58 bool CSRChanged =
true;
61 size_t LastSize = LastCalleeSavedRegs.size();
62 for (
unsigned I = 0;; ++
I) {
64 CSRChanged =
I != LastSize;
71 if (CSR[
I] != LastCalleeSavedRegs[
I]) {
80 LastCalleeSavedRegs.clear();
86 CalleeSavedAliases[U] = *
I;
87 LastCalleeSavedRegs.push_back(*
I);
98 CSRHintsForAllocOrder[(*AI).id()] =
99 STI.ignoreCSRForAllocationOrder(mf, *AI);
100 if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) {
102 IgnoreCSRForAllocOrder = CSRHintsForAllocOrder;
109 if (RR != Reserved) {
117 PSetLimits.reset(
new unsigned[NumPSets]);
118 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
127 assert(RC &&
"no register class given");
128 RCInfo &RCI = RegClass[RC->
getID()];
141 unsigned LastCostChange = 0;
146 for (
unsigned PhysReg : RawOrder) {
148 if (Reserved.
test(PhysReg))
151 MinCost = std::min(MinCost,
Cost);
154 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
158 if (
Cost != LastCost)
160 RCI.Order[
N++] = PhysReg;
164 RCI.NumRegs =
N + CSRAlias.
size();
165 assert(RCI.NumRegs <= NumRegs &&
"Allocation order larger than regclass");
168 for (
unsigned PhysReg : CSRAlias) {
170 if (
Cost != LastCost)
172 RCI.Order[
N++] = PhysReg;
184 RCI.ProperSubClass =
true;
186 RCI.MinCost = MinCost;
187 RCI.LastCostChange = LastCostChange;
191 for (
unsigned I = 0;
I != RCI.NumRegs; ++
I)
193 dbgs() << (RCI.ProperSubClass ?
" ] (sub-class)\n" :
" ]\n");
205 unsigned NumRCUnits = 0;
208 for (; *PSetID != -1; ++PSetID) {
209 if ((
unsigned)*PSetID ==
Idx)
218 if (!RC || NUnits > NumRCUnits) {
223 assert(RC &&
"Failed to find register class");
231 if (NAllocatableRegs == 0)
232 return RegPressureSetLimit;
233 unsigned NReserved = RC->
getNumRegs() - NAllocatableRegs;
unsigned const MachineRegisterInfo * MRI
This file implements the BitVector class.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static cl::opt< unsigned > StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), cl::desc("Limit all regclasses to N registers"))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool test(unsigned Idx) const
MCRegAliasIterator enumerates all registers aliasing Reg.
unsigned getNumRegUnits() const
Return the number of (native) register units in the target.
iterator_range< MCRegUnitIterator > regunits(MCRegister Reg) const
Returns an iterator range over all regunits for Reg.
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const
getLastCalleeSavedAlias - Returns the last callee saved register that overlaps PhysReg,...
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
unsigned getNumRegs() const
Return the number of registers in this class.
unsigned getID() const
Return the register class ID number.
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
iterator_range< regclass_iterator > regclasses() const
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
unsigned getNumRegClasses() const
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
@ C
The default llvm calling convention, compatible with C.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.