LLVM  14.0.0git
RegisterClassInfo.cpp
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1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RegisterClassInfo class which provides dynamic
10 // information about target register classes. Callee-saved vs. caller-saved and
11 // reserved registers depend on calling conventions and other dynamic
12 // information, so some things cannot be determined statically.
13 //
14 //===----------------------------------------------------------------------===//
15 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/Support/Debug.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstdint>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "regalloc"
36 
37 static cl::opt<unsigned>
38 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
39  cl::desc("Limit all regclasses to N registers"));
40 
42 
44  bool Update = false;
45  MF = &mf;
46 
47  // Allocate new array the first time we see a new target.
48  if (MF->getSubtarget().getRegisterInfo() != TRI) {
49  TRI = MF->getSubtarget().getRegisterInfo();
50  RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
51  Update = true;
52  }
53 
54  // Does this MF have different CSRs?
55  assert(TRI && "no register info set");
56 
57  // Get the callee saved registers.
58  const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
59  if (Update || CSR != CalleeSavedRegs) {
60  // Build a CSRAlias map. Every CSR alias saves the last
61  // overlapping CSR.
62  CalleeSavedAliases.assign(TRI->getNumRegs(), 0);
63  for (const MCPhysReg *I = CSR; *I; ++I)
64  for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
65  CalleeSavedAliases[*AI] = *I;
66 
67  Update = true;
68  }
69  CalleeSavedRegs = CSR;
70 
71  RegCosts = TRI->getRegisterCosts(*MF);
72 
73  // Different reserved registers?
74  const BitVector &RR = MF->getRegInfo().getReservedRegs();
75  if (Reserved.size() != RR.size() || RR != Reserved) {
76  Update = true;
77  Reserved = RR;
78  }
79 
80  // Invalidate cached information from previous function.
81  if (Update) {
82  unsigned NumPSets = TRI->getNumRegPressureSets();
83  PSetLimits.reset(new unsigned[NumPSets]);
84  std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
85  ++Tag;
86  }
87 }
88 
89 /// compute - Compute the preferred allocation order for RC with reserved
90 /// registers filtered out. Volatile registers come first followed by CSR
91 /// aliases ordered according to the CSR order specified by the target.
92 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
93  assert(RC && "no register class given");
94  RCInfo &RCI = RegClass[RC->getID()];
95  auto &STI = MF->getSubtarget();
96 
97  // Raw register count, including all reserved regs.
98  unsigned NumRegs = RC->getNumRegs();
99 
100  if (!RCI.Order)
101  RCI.Order.reset(new MCPhysReg[NumRegs]);
102 
103  unsigned N = 0;
105  uint8_t MinCost = uint8_t(~0u);
106  uint8_t LastCost = uint8_t(~0u);
107  unsigned LastCostChange = 0;
108 
109  // FIXME: Once targets reserve registers instead of removing them from the
110  // allocation order, we can simply use begin/end here.
111  ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
112  for (unsigned PhysReg : RawOrder) {
113  // Remove reserved registers from the allocation order.
114  if (Reserved.test(PhysReg))
115  continue;
116  uint8_t Cost = RegCosts[PhysReg];
117  MinCost = std::min(MinCost, Cost);
118 
119  if (CalleeSavedAliases[PhysReg] &&
120  !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
121  // PhysReg aliases a CSR, save it for later.
122  CSRAlias.push_back(PhysReg);
123  else {
124  if (Cost != LastCost)
125  LastCostChange = N;
126  RCI.Order[N++] = PhysReg;
127  LastCost = Cost;
128  }
129  }
130  RCI.NumRegs = N + CSRAlias.size();
131  assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
132 
133  // CSR aliases go after the volatile registers, preserve the target's order.
134  for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
135  unsigned PhysReg = CSRAlias[i];
136  uint8_t Cost = RegCosts[PhysReg];
137  if (Cost != LastCost)
138  LastCostChange = N;
139  RCI.Order[N++] = PhysReg;
140  LastCost = Cost;
141  }
142 
143  // Register allocator stress test. Clip register class to N registers.
144  if (StressRA && RCI.NumRegs > StressRA)
145  RCI.NumRegs = StressRA;
146 
147  // Check if RC is a proper sub-class.
148  if (const TargetRegisterClass *Super =
149  TRI->getLargestLegalSuperClass(RC, *MF))
150  if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
151  RCI.ProperSubClass = true;
152 
153  RCI.MinCost = MinCost;
154  RCI.LastCostChange = LastCostChange;
155 
156  LLVM_DEBUG({
157  dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
158  for (unsigned I = 0; I != RCI.NumRegs; ++I)
159  dbgs() << ' ' << printReg(RCI.Order[I], TRI);
160  dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
161  });
162 
163  // RCI is now up-to-date.
164  RCI.Tag = Tag;
165 }
166 
167 /// This is not accurate because two overlapping register sets may have some
168 /// nonoverlapping reserved registers. However, computing the allocation order
169 /// for all register classes would be too expensive.
170 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
171  const TargetRegisterClass *RC = nullptr;
172  unsigned NumRCUnits = 0;
173  for (const TargetRegisterClass *C : TRI->regclasses()) {
174  const int *PSetID = TRI->getRegClassPressureSets(C);
175  for (; *PSetID != -1; ++PSetID) {
176  if ((unsigned)*PSetID == Idx)
177  break;
178  }
179  if (*PSetID == -1)
180  continue;
181 
182  // Found a register class that counts against this pressure set.
183  // For efficiency, only compute the set order for the largest set.
184  unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
185  if (!RC || NUnits > NumRCUnits) {
186  RC = C;
187  NumRCUnits = NUnits;
188  }
189  }
190  assert(RC && "Failed to find register class");
191  compute(RC);
192  unsigned NAllocatableRegs = getNumAllocatableRegs(RC);
193  unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx);
194  // If all the regs are reserved, return raw RegPressureSetLimit.
195  // One example is VRSAVERC in PowerPC.
196  // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit
197  // return non-zero value.
198  if (NAllocatableRegs == 0)
199  return RegPressureSetLimit;
200  unsigned NReserved = RC->getNumRegs() - NAllocatableRegs;
201  return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved;
202 }
i
i
Definition: README.txt:29
llvm::TargetRegisterInfo::getLargestLegalSuperClass
virtual const TargetRegisterClass * getLargestLegalSuperClass(const TargetRegisterClass *RC, const MachineFunction &) const
Returns the largest super class of RC that is legal to use in the current sub-target and has the same...
Definition: TargetRegisterInfo.h:777
llvm::TargetRegisterClass::getID
unsigned getID() const
Return the register class ID number.
Definition: TargetRegisterInfo.h:71
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
TargetFrameLowering.h
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1176
llvm::TargetRegisterInfo::getRegisterCosts
ArrayRef< uint8_t > getRegisterCosts(const MachineFunction &MF) const
Get a list of cost values for all registers that correspond to the index returned by RegisterCostTabl...
Definition: TargetRegisterInfo.h:352
llvm::MCRegisterInfo::getNumRegs
unsigned getNumRegs() const
Return the number of registers this target has (useful for sizing arrays holding per register informa...
Definition: MCRegisterInfo.h:491
RegisterClassInfo.h
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:124
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::TargetRegisterInfo::getRegPressureSetLimit
virtual unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const =0
Get the register unit pressure limit for this dimension.
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
MachineRegisterInfo.h
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
CommandLine.h
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MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:651
llvm::RegisterClassInfo::RegisterClassInfo
RegisterClassInfo()
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::BitVector::size
size_type size() const
size - Returns the number of bits in this bitvector.
Definition: BitVector.h:151
llvm::TargetRegisterClass::getRawAllocationOrder
ArrayRef< MCPhysReg > getRawAllocationOrder(const MachineFunction &MF) const
Returns the preferred order for allocating registers from this register class in MF.
Definition: TargetRegisterInfo.h:199
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::TargetRegisterInfo::getRegClassPressureSets
virtual const int * getRegClassPressureSets(const TargetRegisterClass *RC) const =0
Get the dimensions of register pressure impacted by this register class.
BitVector.h
llvm::BitVector
Definition: BitVector.h:74
llvm::RegisterClassInfo::getNumAllocatableRegs
unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const
getNumAllocatableRegs - Returns the number of actually allocatable registers in RC in the current fun...
Definition: RegisterClassInfo.h:92
llvm::TargetRegisterInfo::regclasses
iterator_range< regclass_iterator > regclasses() const
Definition: TargetRegisterInfo.h:729
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const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:641
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Definition: CommandLine.h:1432
llvm::RegisterClassInfo::runOnMachineFunction
void runOnMachineFunction(const MachineFunction &MF)
runOnFunction - Prepare to answer questions about MF.
Definition: RegisterClassInfo.cpp:43
llvm::TargetRegisterInfo::getRegClassName
const char * getRegClassName(const TargetRegisterClass *Class) const
Returns the name of the register class.
Definition: TargetRegisterInfo.h:745
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constexpr double e
Definition: MathExtras.h:57
llvm::MachineRegisterInfo::getCalleeSavedRegs
const MCPhysReg * getCalleeSavedRegs() const
Returns list of callee saved registers.
Definition: MachineRegisterInfo.cpp:619
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetRegisterInfo::getNumRegPressureSets
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
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initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
MCRegisterInfo.h
ArrayRef.h
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Definition: MachineFunction.h:241
llvm::RegClassWeight::RegWeight
unsigned RegWeight
Definition: TargetRegisterInfo.h:223
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ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
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Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:357
TargetSubtargetInfo.h
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unsigned WeightLimit
Definition: TargetRegisterInfo.h:224
llvm::MachineRegisterInfo::getReservedRegs
const BitVector & getReservedRegs() const
getReservedRegs - Returns a reference to the frozen set of reserved registers.
Definition: MachineRegisterInfo.h:917
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bool test(unsigned Idx) const
Definition: BitVector.h:453
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unsigned getNumRegs() const
Return the number of registers in this class.
Definition: TargetRegisterInfo.h:79
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Definition: CommandLine.h:422
llvm::TargetRegisterInfo::getNumRegClasses
unsigned getNumRegClasses() const
Definition: TargetRegisterInfo.h:733
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bool isValid() const
Definition: MCRegisterInfo.h:805
llvm::RegisterClassInfo::computePSetLimit
unsigned computePSetLimit(unsigned Idx) const
This is not accurate because two overlapping register sets may have some nonoverlapping reserved regi...
Definition: RegisterClassInfo.cpp:170
SmallVector.h
N
#define N
llvm::TargetRegisterInfo::getRegClassWeight
virtual const RegClassWeight & getRegClassWeight(const TargetRegisterClass *RC) const =0
Get the weight in units of pressure for this register class.
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static cl::opt< unsigned > StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), cl::desc("Limit all regclasses to N registers"))
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Definition: CommandLine.h:412
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Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Definition: TargetRegisterInfo.cpp:110
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MCRegAliasIterator enumerates all registers aliasing Reg.
Definition: MCRegisterInfo.h:780