LLVM 20.0.0git
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This class represents the scheduled code. More...
#include "llvm/CodeGen/MachinePipeliner.h"
Public Types | |
using | sched_iterator = DenseMap< int, std::deque< SUnit * > >::iterator |
Iterators for the cycle to instruction map. | |
using | const_sched_iterator = DenseMap< int, std::deque< SUnit * > >::const_iterator |
Public Member Functions | |
SMSchedule (MachineFunction *mf, SwingSchedulerDAG *DAG) | |
void | reset () |
void | setInitiationInterval (int ii) |
Set the initiation interval for this schedule. | |
int | getInitiationInterval () const |
Return the initiation interval for this schedule. | |
int | getFirstCycle () const |
Return the first cycle in the completed schedule. | |
int | getFinalCycle () const |
Return the last cycle in the finalized schedule. | |
int | earliestCycleInChain (const SwingSchedulerDDGEdge &Dep, const SwingSchedulerDDG *DDG) |
Return the cycle of the earliest scheduled instruction in the dependence chain. | |
int | latestCycleInChain (const SwingSchedulerDDGEdge &Dep, const SwingSchedulerDDG *DDG) |
Return the cycle of the latest scheduled instruction in the dependence chain. | |
void | computeStart (SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int II, SwingSchedulerDAG *DAG) |
Compute the scheduling start slot for the instruction. | |
bool | insert (SUnit *SU, int StartCycle, int EndCycle, int II) |
Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached. | |
bool | isScheduledAtStage (SUnit *SU, unsigned StageNum) |
Return true if the instruction is scheduled at the specified stage. | |
int | stageScheduled (SUnit *SU) const |
Return the stage for a scheduled instruction. | |
unsigned | cycleScheduled (SUnit *SU) const |
Return the cycle for a scheduled instruction. | |
unsigned | getMaxStageCount () |
Return the maximum stage count needed for this schedule. | |
std::deque< SUnit * > & | getInstructions (int cycle) |
Return the instructions that are scheduled at the specified cycle. | |
SmallSet< SUnit *, 8 > | computeUnpipelineableNodes (SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) |
Determine transitive dependences of unpipelineable instructions. | |
std::deque< SUnit * > | reorderInstructions (const SwingSchedulerDAG *SSD, const std::deque< SUnit * > &Instrs) const |
bool | normalizeNonPipelinedInstructions (SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) |
bool | isValidSchedule (SwingSchedulerDAG *SSD) |
void | finalizeSchedule (SwingSchedulerDAG *SSD) |
After the schedule has been formed, call this function to combine the instructions from the different stages/cycles. | |
void | orderDependence (const SwingSchedulerDAG *SSD, SUnit *SU, std::deque< SUnit * > &Insts) const |
Order the instructions within a cycle so that the definitions occur before the uses. | |
bool | isLoopCarried (const SwingSchedulerDAG *SSD, MachineInstr &Phi) const |
Return true if the scheduled Phi has a loop carried operand. | |
bool | isLoopCarriedDefOfUse (const SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO) const |
Return true if the instruction is a definition that is loop carried and defines the use on the next iteration. | |
bool | onlyHasLoopCarriedOutputOrOrderPreds (SUnit *SU, const SwingSchedulerDDG *DDG) const |
Return true if all scheduled predecessors are loop-carried output/order dependencies. | |
void | print (raw_ostream &os) const |
Print the schedule information to the given output. | |
void | dump () const |
Utility function used for debugging to print the schedule. | |
This class represents the scheduled code.
The main data structure is a map from scheduled cycle to instructions. During scheduling, the data structure explicitly represents all stages/iterations. When the algorithm finshes, the schedule is collapsed into a single stage, which represents instructions from different loop iterations.
The SMS algorithm allows negative values for cycles, so the first cycle in the schedule is the smallest cycle value.
Definition at line 670 of file MachinePipeliner.h.
using llvm::SMSchedule::const_sched_iterator = DenseMap<int, std::deque<SUnit *> >::const_iterator |
Definition at line 741 of file MachinePipeliner.h.
using llvm::SMSchedule::sched_iterator = DenseMap<int, std::deque<SUnit *> >::iterator |
Iterators for the cycle to instruction map.
Definition at line 740 of file MachinePipeliner.h.
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Definition at line 697 of file MachinePipeliner.h.
References MRI.
void SMSchedule::computeStart | ( | SUnit * | SU, |
int * | MaxEarlyStart, | ||
int * | MinLateStart, | ||
int | II, | ||
SwingSchedulerDAG * | DAG | ||
) |
Compute the scheduling start slot for the instruction.
The start slot depends on any predecessor or successor nodes scheduled already.
Definition at line 2877 of file MachinePipeliner.cpp.
References earliestCycleInChain(), End, llvm::SwingSchedulerDAG::getDDG(), getFirstCycle(), llvm::SwingSchedulerDDG::getInEdges(), llvm::SUnit::getInstr(), getInstructions(), llvm::SwingSchedulerDDG::getOutEdges(), I, II, llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::MachineInstr::isPHI(), llvm::SUnit::isPred(), latestCycleInChain(), multipleIterations(), and llvm::SUnit::Preds.
SmallSet< SUnit *, 8 > SMSchedule::computeUnpipelineableNodes | ( | SwingSchedulerDAG * | SSD, |
TargetInstrInfo::PipelinerLoopInfo * | PLI | ||
) |
Determine transitive dependences of unpipelineable instructions.
Definition at line 3118 of file MachinePipeliner.cpp.
References llvm::SmallSet< T, N, C >::count(), llvm::dbgs(), llvm::SmallVectorBase< Size_T >::empty(), llvm::SwingSchedulerDAG::getDDG(), llvm::SwingSchedulerDDG::getInEdges(), llvm::SUnit::getInstr(), llvm::SwingSchedulerDDG::getOutEdges(), llvm::SmallSet< T, N, C >::insert(), llvm::SUnit::isInstr(), LLVM_DEBUG, llvm::SUnit::NodeNum, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::TargetInstrInfo::PipelinerLoopInfo::shouldIgnoreForPipelining(), and llvm::ScheduleDAG::SUnits.
Referenced by normalizeNonPipelinedInstructions().
Return the cycle for a scheduled instruction.
This function normalizes the first cycle to be 0.
Definition at line 760 of file MachinePipeliner.h.
References assert().
Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), isLoopCarried(), and orderDependence().
LLVM_DUMP_METHOD void SMSchedule::dump | ( | ) | const |
Utility function used for debugging to print the schedule.
Definition at line 3444 of file MachinePipeliner.cpp.
References llvm::dbgs(), and print().
Referenced by finalizeSchedule().
int SMSchedule::earliestCycleInChain | ( | const SwingSchedulerDDGEdge & | Dep, |
const SwingSchedulerDDG * | DDG | ||
) |
Return the cycle of the earliest scheduled instruction in the dependence chain.
Definition at line 2816 of file MachinePipeliner.cpp.
References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorBase< Size_T >::empty(), llvm::SwingSchedulerDDG::getInEdges(), llvm::SwingSchedulerDDGEdge::getSrc(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by computeStart().
void SMSchedule::finalizeSchedule | ( | SwingSchedulerDAG * | SSD | ) |
After the schedule has been formed, call this function to combine the instructions from the different stages/cycles.
That is, this function creates a schedule that represents a single iteration.
Definition at line 3386 of file MachinePipeliner.cpp.
References llvm::SwingSchedulerDAG::applyInstrChange(), dump(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), getMaxStageCount(), LLVM_DEBUG, reorderInstructions(), llvm::reverse(), and llvm::ScheduleDAG::SUnits.
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Return the last cycle in the finalized schedule.
Definition at line 723 of file MachinePipeliner.h.
Referenced by computeScheduledInsts(), finalizeSchedule(), print(), and llvm::SwingSchedulerDAG::schedule().
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Return the first cycle in the completed schedule.
This can be a negative value.
Definition at line 720 of file MachinePipeliner.h.
Referenced by computeScheduledInsts(), computeStart(), finalizeSchedule(), normalizeNonPipelinedInstructions(), print(), and llvm::SwingSchedulerDAG::schedule().
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Return the initiation interval for this schedule.
Definition at line 716 of file MachinePipeliner.h.
Referenced by computeScheduledInsts().
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Return the instructions that are scheduled at the specified cycle.
Definition at line 772 of file MachinePipeliner.h.
Referenced by computeScheduledInsts(), computeStart(), normalizeNonPipelinedInstructions(), and llvm::SwingSchedulerDAG::schedule().
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Return the maximum stage count needed for this schedule.
Definition at line 767 of file MachinePipeliner.h.
Referenced by computeScheduledInsts(), finalizeSchedule(), and llvm::SwingSchedulerDAG::schedule().
Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached.
This function returns true if the node is scheduled. This routine may search either forward or backward for a place to insert the instruction based upon the relative values of StartCycle and EndCycle.
Definition at line 2776 of file MachinePipeliner.cpp.
References llvm::ResourceManager::canReserveResources(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOpcode(), II, and LLVM_DEBUG.
bool SMSchedule::isLoopCarried | ( | const SwingSchedulerDAG * | SSD, |
MachineInstr & | Phi | ||
) | const |
Return true if the scheduled Phi has a loop carried operand.
Definition at line 3058 of file MachinePipeliner.cpp.
References assert(), cycleScheduled(), llvm::SUnit::getInstr(), getPhiRegs(), llvm::ScheduleDAGInstrs::getSUnit(), llvm::MachineInstr::isPHI(), MRI, and stageScheduled().
Referenced by isLoopCarriedDefOfUse().
bool SMSchedule::isLoopCarriedDefOfUse | ( | const SwingSchedulerDAG * | SSD, |
MachineInstr * | Def, | ||
MachineOperand & | MO | ||
) | const |
Return true if the instruction is a definition that is loop carried and defines the use on the next iteration.
v1 = phi(v2, v3) (Def) v3 = op v1 (MO) = v1 If MO appears before Def, then v1 and v3 may get assigned to the same register.
Definition at line 3087 of file MachinePipeliner.cpp.
References getLoopPhiReg(), llvm::MachineOperand::getReg(), isLoopCarried(), llvm::MachineOperand::isReg(), and MRI.
Referenced by orderDependence().
Return true if the instruction is scheduled at the specified stage.
Definition at line 745 of file MachinePipeliner.h.
References stageScheduled().
bool SMSchedule::isValidSchedule | ( | SwingSchedulerDAG * | SSD | ) |
Definition at line 3197 of file MachinePipeliner.cpp.
References assert(), llvm::SwingSchedulerDAG::getDDG(), llvm::SwingSchedulerDDG::getOutEdges(), llvm::SUnit::hasPhysRegDefs, llvm::Register::isPhysicalRegister(), stageScheduled(), and llvm::ScheduleDAG::SUnits.
int SMSchedule::latestCycleInChain | ( | const SwingSchedulerDDGEdge & | Dep, |
const SwingSchedulerDDG * | DDG | ||
) |
Return the cycle of the latest scheduled instruction in the dependence chain.
Definition at line 2840 of file MachinePipeliner.cpp.
References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorBase< Size_T >::empty(), llvm::SwingSchedulerDDGEdge::getDst(), llvm::SwingSchedulerDDG::getOutEdges(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SUnit::isBoundaryNode(), llvm::SmallVectorImpl< T >::pop_back_val(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by computeStart().
bool SMSchedule::normalizeNonPipelinedInstructions | ( | SwingSchedulerDAG * | SSD, |
TargetInstrInfo::PipelinerLoopInfo * | PLI | ||
) |
Definition at line 3148 of file MachinePipeliner.cpp.
References computeUnpipelineableNodes(), llvm::SmallSet< T, N, C >::contains(), llvm::dbgs(), llvm::erase(), llvm::SwingSchedulerDAG::getDDG(), getFirstCycle(), llvm::SwingSchedulerDDG::getInEdges(), llvm::SUnit::getInstr(), getInstructions(), llvm::SwingSchedulerDDG::getOutEdges(), llvm::SUnit::isInstr(), LLVM_DEBUG, llvm::SUnit::NodeNum, stageScheduled(), and llvm::ScheduleDAG::SUnits.
bool SMSchedule::onlyHasLoopCarriedOutputOrOrderPreds | ( | SUnit * | SU, |
const SwingSchedulerDDG * | DDG | ||
) | const |
Return true if all scheduled predecessors are loop-carried output/order dependencies.
Definition at line 3109 of file MachinePipeliner.cpp.
References llvm::SwingSchedulerDDG::getInEdges().
void SMSchedule::orderDependence | ( | const SwingSchedulerDAG * | SSD, |
SUnit * | SU, | ||
std::deque< SUnit * > & | Insts | ||
) | const |
Order the instructions within a cycle so that the definitions occur before the uses.
Returns true if the instruction is added to the start of the list, or false if added to the end.
Definition at line 2927 of file MachinePipeliner.cpp.
References cycleScheduled(), llvm::SwingSchedulerDAG::getDDG(), llvm::SwingSchedulerDDG::getInEdges(), llvm::SUnit::getInstr(), llvm::SwingSchedulerDAG::getInstrBaseReg(), llvm::SwingSchedulerDDG::getOutEdges(), I, isLoopCarriedDefOfUse(), MI, orderDependence(), stageScheduled(), and Writes.
Referenced by orderDependence(), and reorderInstructions().
void SMSchedule::print | ( | raw_ostream & | os | ) | const |
Print the schedule information to the given output.
Definition at line 3429 of file MachinePipeliner.cpp.
References getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), llvm::SUnit::NodeNum, llvm::MachineInstr::print(), and stageScheduled().
Referenced by dump().
std::deque< SUnit * > SMSchedule::reorderInstructions | ( | const SwingSchedulerDAG * | SSD, |
const std::deque< SUnit * > & | Instrs | ||
) | const |
Definition at line 3367 of file MachinePipeliner.cpp.
References llvm::append_range(), llvm::SUnit::getInstr(), llvm::MachineInstr::isPHI(), and orderDependence().
Referenced by computeScheduledInsts(), and finalizeSchedule().
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Definition at line 701 of file MachinePipeliner.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::clear().
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Set the initiation interval for this schedule.
Definition at line 710 of file MachinePipeliner.h.
References llvm::ResourceManager::init().
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Return the stage for a scheduled instruction.
Return -1 if the instruction has not been scheduled.
Definition at line 751 of file MachinePipeliner.h.
Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), computeScheduledInsts(), isLoopCarried(), isScheduledAtStage(), isValidSchedule(), normalizeNonPipelinedInstructions(), orderDependence(), print(), and llvm::SwingSchedulerDAG::schedule().