LLVM 22.0.0git
llvm::SMSchedule Class Reference

This class represents the scheduled code. More...

#include "llvm/CodeGen/MachinePipeliner.h"

Public Types

using sched_iterator = DenseMap<int, std::deque<SUnit *>>::iterator
 Iterators for the cycle to instruction map.
using const_sched_iterator

Public Member Functions

 SMSchedule (MachineFunction *mf, SwingSchedulerDAG *DAG)
void reset ()
void setInitiationInterval (int ii)
 Set the initiation interval for this schedule.
int getInitiationInterval () const
 Return the initiation interval for this schedule.
int getFirstCycle () const
 Return the first cycle in the completed schedule.
int getFinalCycle () const
 Return the last cycle in the finalized schedule.
int earliestCycleInChain (const SwingSchedulerDDGEdge &Dep, const SwingSchedulerDDG *DDG)
 Return the cycle of the earliest scheduled instruction in the dependence chain.
int latestCycleInChain (const SwingSchedulerDDGEdge &Dep, const SwingSchedulerDDG *DDG)
 Return the cycle of the latest scheduled instruction in the dependence chain.
void computeStart (SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int II, SwingSchedulerDAG *DAG)
 Compute the scheduling start slot for the instruction.
bool insert (SUnit *SU, int StartCycle, int EndCycle, int II)
 Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached.
bool isScheduledAtStage (SUnit *SU, unsigned StageNum)
 Return true if the instruction is scheduled at the specified stage.
int stageScheduled (SUnit *SU) const
 Return the stage for a scheduled instruction.
unsigned cycleScheduled (SUnit *SU) const
 Return the cycle for a scheduled instruction.
unsigned getMaxStageCount ()
 Return the maximum stage count needed for this schedule.
std::deque< SUnit * > & getInstructions (int cycle)
 Return the instructions that are scheduled at the specified cycle.
SmallPtrSet< SUnit *, 8 > computeUnpipelineableNodes (SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
 Determine transitive dependences of unpipelineable instructions.
std::deque< SUnit * > reorderInstructions (const SwingSchedulerDAG *SSD, const std::deque< SUnit * > &Instrs) const
bool normalizeNonPipelinedInstructions (SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
bool isValidSchedule (SwingSchedulerDAG *SSD)
void finalizeSchedule (SwingSchedulerDAG *SSD)
 After the schedule has been formed, call this function to combine the instructions from the different stages/cycles.
void orderDependence (const SwingSchedulerDAG *SSD, SUnit *SU, std::deque< SUnit * > &Insts) const
 Order the instructions within a cycle so that the definitions occur before the uses.
bool isLoopCarried (const SwingSchedulerDAG *SSD, MachineInstr &Phi) const
 Return true if the scheduled Phi has a loop carried operand.
bool isLoopCarriedDefOfUse (const SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO) const
 Return true if the instruction is a definition that is loop carried and defines the use on the next iteration.
bool onlyHasLoopCarriedOutputOrOrderPreds (SUnit *SU, const SwingSchedulerDDG *DDG) const
 Return true if all scheduled predecessors are loop-carried output/order dependencies.
void print (raw_ostream &os) const
 Print the schedule information to the given output.
void dump () const
 Utility function used for debugging to print the schedule.

Detailed Description

This class represents the scheduled code.

The main data structure is a map from scheduled cycle to instructions. During scheduling, the data structure explicitly represents all stages/iterations. When the algorithm finshes, the schedule is collapsed into a single stage, which represents instructions from different loop iterations.

The SMS algorithm allows negative values for cycles, so the first cycle in the schedule is the smallest cycle value.

Definition at line 727 of file MachinePipeliner.h.

Member Typedef Documentation

◆ const_sched_iterator

◆ sched_iterator

using llvm::SMSchedule::sched_iterator = DenseMap<int, std::deque<SUnit *>>::iterator

Iterators for the cycle to instruction map.

Definition at line 797 of file MachinePipeliner.h.

Constructor & Destructor Documentation

◆ SMSchedule()

llvm::SMSchedule::SMSchedule ( MachineFunction * mf,
SwingSchedulerDAG * DAG )
inline

Definition at line 754 of file MachinePipeliner.h.

Member Function Documentation

◆ computeStart()

void SMSchedule::computeStart ( SUnit * SU,
int * MaxEarlyStart,
int * MinLateStart,
int II,
SwingSchedulerDAG * DAG )

◆ computeUnpipelineableNodes()

◆ cycleScheduled()

unsigned llvm::SMSchedule::cycleScheduled ( SUnit * SU) const
inline

Return the cycle for a scheduled instruction.

This function normalizes the first cycle to be 0.

Definition at line 817 of file MachinePipeliner.h.

References assert().

Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), isLoopCarried(), llvm::SwingSchedulerDDG::isValidSchedule(), and orderDependence().

◆ dump()

LLVM_DUMP_METHOD void SMSchedule::dump ( ) const

Utility function used for debugging to print the schedule.

Definition at line 3821 of file MachinePipeliner.cpp.

References llvm::dbgs(), LLVM_DUMP_METHOD, and print().

◆ earliestCycleInChain()

◆ finalizeSchedule()

void SMSchedule::finalizeSchedule ( SwingSchedulerDAG * SSD)

After the schedule has been formed, call this function to combine the instructions from the different stages/cycles.

That is, this function creates a schedule that represents a single iteration.

Definition at line 3763 of file MachinePipeliner.cpp.

References llvm::SwingSchedulerDAG::applyInstrChange(), llvm::dump(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), getMaxStageCount(), LLVM_DEBUG, reorderInstructions(), llvm::reverse(), and llvm::ScheduleDAG::SUnits.

◆ getFinalCycle()

int llvm::SMSchedule::getFinalCycle ( ) const
inline

Return the last cycle in the finalized schedule.

Definition at line 780 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), finalizeSchedule(), print(), and llvm::SwingSchedulerDAG::schedule().

◆ getFirstCycle()

int llvm::SMSchedule::getFirstCycle ( ) const
inline

Return the first cycle in the completed schedule.

This can be a negative value.

Definition at line 777 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), computeStart(), finalizeSchedule(), normalizeNonPipelinedInstructions(), print(), and llvm::SwingSchedulerDAG::schedule().

◆ getInitiationInterval()

int llvm::SMSchedule::getInitiationInterval ( ) const
inline

Return the initiation interval for this schedule.

Definition at line 773 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), and llvm::SwingSchedulerDDG::isValidSchedule().

◆ getInstructions()

std::deque< SUnit * > & llvm::SMSchedule::getInstructions ( int cycle)
inline

Return the instructions that are scheduled at the specified cycle.

Definition at line 829 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), computeStart(), normalizeNonPipelinedInstructions(), and llvm::SwingSchedulerDAG::schedule().

◆ getMaxStageCount()

unsigned llvm::SMSchedule::getMaxStageCount ( )
inline

Return the maximum stage count needed for this schedule.

Definition at line 824 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), finalizeSchedule(), and llvm::SwingSchedulerDAG::schedule().

◆ insert()

bool SMSchedule::insert ( SUnit * SU,
int StartCycle,
int EndCycle,
int II )

Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached.

This function returns true if the node is scheduled. This routine may search either forward or backward for a place to insert the instruction based upon the relative values of StartCycle and EndCycle.

Definition at line 3127 of file MachinePipeliner.cpp.

References llvm::dbgs(), llvm::MachineInstr::dump(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOpcode(), II, and LLVM_DEBUG.

◆ isLoopCarried()

bool SMSchedule::isLoopCarried ( const SwingSchedulerDAG * SSD,
MachineInstr & Phi ) const

Return true if the scheduled Phi has a loop carried operand.

Definition at line 3409 of file MachinePipeliner.cpp.

References assert(), cycleScheduled(), llvm::SUnit::getInstr(), getPhiRegs(), llvm::ScheduleDAGInstrs::getSUnit(), llvm::MachineInstr::isPHI(), and stageScheduled().

Referenced by isLoopCarriedDefOfUse().

◆ isLoopCarriedDefOfUse()

bool SMSchedule::isLoopCarriedDefOfUse ( const SwingSchedulerDAG * SSD,
MachineInstr * Def,
MachineOperand & MO ) const

Return true if the instruction is a definition that is loop carried and defines the use on the next iteration.

v1 = phi(v2, v3) (Def) v3 = op v1 (MO) = v1 If MO appears before Def, then v1 and v3 may get assigned to the same register.

Definition at line 3438 of file MachinePipeliner.cpp.

References getLoopPhiReg(), llvm::MachineOperand::getReg(), isLoopCarried(), and llvm::MachineOperand::isReg().

Referenced by orderDependence().

◆ isScheduledAtStage()

bool llvm::SMSchedule::isScheduledAtStage ( SUnit * SU,
unsigned StageNum )
inline

Return true if the instruction is scheduled at the specified stage.

Definition at line 802 of file MachinePipeliner.h.

References stageScheduled().

◆ isValidSchedule()

◆ latestCycleInChain()

◆ normalizeNonPipelinedInstructions()

◆ onlyHasLoopCarriedOutputOrOrderPreds()

bool SMSchedule::onlyHasLoopCarriedOutputOrOrderPreds ( SUnit * SU,
const SwingSchedulerDDG * DDG ) const

Return true if all scheduled predecessors are loop-carried output/order dependencies.

Definition at line 3460 of file MachinePipeliner.cpp.

References llvm::SwingSchedulerDDG::getInEdges().

◆ orderDependence()

void SMSchedule::orderDependence ( const SwingSchedulerDAG * SSD,
SUnit * SU,
std::deque< SUnit * > & Insts ) const

Order the instructions within a cycle so that the definitions occur before the uses.

Returns true if the instruction is added to the start of the list, or false if added to the end.

Definition at line 3278 of file MachinePipeliner.cpp.

References cycleScheduled(), llvm::SwingSchedulerDAG::getDDG(), llvm::SwingSchedulerDDG::getInEdges(), llvm::SUnit::getInstr(), llvm::SwingSchedulerDAG::getInstrBaseReg(), llvm::SwingSchedulerDDG::getOutEdges(), I, isLoopCarriedDefOfUse(), MI, orderDependence(), and stageScheduled().

Referenced by orderDependence(), and reorderInstructions().

◆ print()

void SMSchedule::print ( raw_ostream & os) const

Print the schedule information to the given output.

Definition at line 3806 of file MachinePipeliner.cpp.

References getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), llvm::SUnit::NodeNum, llvm::MachineInstr::print(), and stageScheduled().

◆ reorderInstructions()

std::deque< SUnit * > SMSchedule::reorderInstructions ( const SwingSchedulerDAG * SSD,
const std::deque< SUnit * > & Instrs ) const

◆ reset()

void llvm::SMSchedule::reset ( )
inline

Definition at line 758 of file MachinePipeliner.h.

◆ setInitiationInterval()

void llvm::SMSchedule::setInitiationInterval ( int ii)
inline

Set the initiation interval for this schedule.

Definition at line 767 of file MachinePipeliner.h.

◆ stageScheduled()

int llvm::SMSchedule::stageScheduled ( SUnit * SU) const
inline

The documentation for this class was generated from the following files: