This class represents the scheduled code. More...

#include "llvm/CodeGen/MachinePipeliner.h"

Public Types
using	sched_iterator = DenseMap< int, std::deque< SUnit * > >::iterator
	Iterators for the cycle to instruction map.

using	const_sched_iterator = DenseMap< int, std::deque< SUnit * > >::const_iterator

Public Member Functions
	SMSchedule (MachineFunction mf, SwingSchedulerDAG DAG)

void	reset ()

void	setInitiationInterval (int ii)
	Set the initiation interval for this schedule.

int	getInitiationInterval () const
	Return the initiation interval for this schedule.

int	getFirstCycle () const
	Return the first cycle in the completed schedule.

int	getFinalCycle () const
	Return the last cycle in the finalized schedule.

int	earliestCycleInChain (const SDep &Dep)
	Return the cycle of the earliest scheduled instruction in the dependence chain.

int	latestCycleInChain (const SDep &Dep)
	Return the cycle of the latest scheduled instruction in the dependence chain.

void	computeStart (SUnit SU, int MaxEarlyStart, int MinLateStart, int II, SwingSchedulerDAG DAG)
	Compute the scheduling start slot for the instruction.

bool	insert (SUnit *SU, int StartCycle, int EndCycle, int II)
	Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached.

bool	isScheduledAtStage (SUnit *SU, unsigned StageNum)
	Return true if the instruction is scheduled at the specified stage.

int	stageScheduled (SUnit *SU) const
	Return the stage for a scheduled instruction.

unsigned	cycleScheduled (SUnit *SU) const
	Return the cycle for a scheduled instruction.

unsigned	getMaxStageCount ()
	Return the maximum stage count needed for this schedule.

std::deque< SUnit * > &	getInstructions (int cycle)
	Return the instructions that are scheduled at the specified cycle.

SmallSet< SUnit *, 8 >	computeUnpipelineableNodes (SwingSchedulerDAG SSD, TargetInstrInfo::PipelinerLoopInfo PLI)
	Determine transitive dependences of unpipelineable instructions.

std::deque< SUnit * >	reorderInstructions (const SwingSchedulerDAG SSD, const std::deque< SUnit > &Instrs) const

bool	normalizeNonPipelinedInstructions (SwingSchedulerDAG SSD, TargetInstrInfo::PipelinerLoopInfo PLI)

bool	isValidSchedule (SwingSchedulerDAG *SSD)

void	finalizeSchedule (SwingSchedulerDAG *SSD)
	After the schedule has been formed, call this function to combine the instructions from the different stages/cycles.

void	orderDependence (const SwingSchedulerDAG SSD, SUnit SU, std::deque< SUnit * > &Insts) const
	Order the instructions within a cycle so that the definitions occur before the uses.

bool	isLoopCarried (const SwingSchedulerDAG *SSD, MachineInstr &Phi) const
	Return true if the scheduled Phi has a loop carried operand.

bool	isLoopCarriedDefOfUse (const SwingSchedulerDAG SSD, MachineInstr Def, MachineOperand &MO) const
	Return true if the instruction is a definition that is loop carried and defines the use on the next iteration.

bool	onlyHasLoopCarriedOutputOrOrderPreds (SUnit SU, SwingSchedulerDAG DAG) const
	Return true if all scheduled predecessors are loop-carried output/order dependencies.

void	print (raw_ostream &os) const
	Print the schedule information to the given output.

void	dump () const
	Utility function used for debugging to print the schedule.

Detailed Description

This class represents the scheduled code.

The main data structure is a map from scheduled cycle to instructions. During scheduling, the data structure explicitly represents all stages/iterations. When the algorithm finshes, the schedule is collapsed into a single stage, which represents instructions from different loop iterations.

The SMS algorithm allows negative values for cycles, so the first cycle in the schedule is the smallest cycle value.

Definition at line 573 of file MachinePipeliner.h.

Member Typedef Documentation

◆ const_sched_iterator

using llvm::SMSchedule::const_sched_iterator = DenseMap<int, std::deque<SUnit *> >::const_iterator

Definition at line 642 of file MachinePipeliner.h.

◆ sched_iterator

using llvm::SMSchedule::sched_iterator = DenseMap<int, std::deque<SUnit *> >::iterator

Iterators for the cycle to instruction map.

Definition at line 641 of file MachinePipeliner.h.

Constructor & Destructor Documentation

◆ SMSchedule()

llvm::SMSchedule::SMSchedule	(	MachineFunction *	mf,
		SwingSchedulerDAG *	DAG
	)

inline

Definition at line 600 of file MachinePipeliner.h.

References MRI.

Member Function Documentation

◆ computeStart()

void SMSchedule::computeStart	(	SUnit *	SU,
		int *	MaxEarlyStart,
		int *	MinLateStart,
		int	II,
		SwingSchedulerDAG *	DAG
	)

Compute the scheduling start slot for the instruction.

The start slot depends on any predecessor or successor nodes scheduled already.

Definition at line 2878 of file MachinePipeliner.cpp.

References earliestCycleInChain(), End, llvm::SwingSchedulerDAG::getDistance(), getFirstCycle(), llvm::SUnit::getInstr(), getInstructions(), llvm::SDep::getLatency(), llvm::SDep::getSUnit(), I, II, llvm::SwingSchedulerDAG::isBackedge(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::MachineInstr::isPHI(), llvm::SUnit::isPred(), latestCycleInChain(), multipleIterations(), llvm::SUnit::Preds, and llvm::SUnit::Succs.

◆ computeUnpipelineableNodes()

SmallSet< SUnit *, 8 > SMSchedule::computeUnpipelineableNodes	(	SwingSchedulerDAG *	SSD,
		TargetInstrInfo::PipelinerLoopInfo *	PLI
	)

Determine transitive dependences of unpipelineable instructions.

Definition at line 3132 of file MachinePipeliner.cpp.

References llvm::SDep::Anti, llvm::SmallSet< T, N, C >::count(), llvm::dbgs(), llvm::SmallVectorBase< Size_T >::empty(), llvm::SUnit::getInstr(), llvm::SmallSet< T, N, C >::insert(), llvm::SUnit::isInstr(), llvm::MachineInstr::isPHI(), LLVM_DEBUG, llvm::SUnit::NodeNum, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SUnit::Preds, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::TargetInstrInfo::PipelinerLoopInfo::shouldIgnoreForPipelining(), llvm::SUnit::Succs, and llvm::ScheduleDAG::SUnits.

Referenced by normalizeNonPipelinedInstructions().

◆ cycleScheduled()

unsigned llvm::SMSchedule::cycleScheduled ( SUnit * SU ) const

inline

Return the cycle for a scheduled instruction.

This function normalizes the first cycle to be 0.

Definition at line 661 of file MachinePipeliner.h.

References assert().

Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), isLoopCarried(), and orderDependence().

◆ dump()

LLVM_DUMP_METHOD void SMSchedule::dump ( ) const

Utility function used for debugging to print the schedule.

Definition at line 3446 of file MachinePipeliner.cpp.

References llvm::dbgs(), and print().

Referenced by finalizeSchedule().

◆ earliestCycleInChain()

int SMSchedule::earliestCycleInChain ( const SDep & Dep )

Return the cycle of the earliest scheduled instruction in the dependence chain.

Definition at line 2819 of file MachinePipeliner.cpp.

References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorBase< Size_T >::empty(), llvm::SDep::getSUnit(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SDep::Order, llvm::SDep::Output, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SUnit::Preds, and llvm::SmallVectorTemplateBase< T, bool >::push_back().

Referenced by computeStart().

◆ finalizeSchedule()

void SMSchedule::finalizeSchedule ( SwingSchedulerDAG * SSD )

After the schedule has been formed, call this function to combine the instructions from the different stages/cycles.

That is, this function creates a schedule that represents a single iteration.

Definition at line 3388 of file MachinePipeliner.cpp.

References llvm::SwingSchedulerDAG::applyInstrChange(), dump(), llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), getMaxStageCount(), LLVM_DEBUG, reorderInstructions(), llvm::reverse(), and llvm::ScheduleDAG::SUnits.

◆ getFinalCycle()

int llvm::SMSchedule::getFinalCycle ( ) const

inline

Return the last cycle in the finalized schedule.

Definition at line 626 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), finalizeSchedule(), print(), and llvm::SwingSchedulerDAG::schedule().

◆ getFirstCycle()

int llvm::SMSchedule::getFirstCycle ( ) const

inline

Return the first cycle in the completed schedule.

This can be a negative value.

Definition at line 623 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), computeStart(), finalizeSchedule(), normalizeNonPipelinedInstructions(), print(), and llvm::SwingSchedulerDAG::schedule().

◆ getInitiationInterval()

int llvm::SMSchedule::getInitiationInterval ( ) const

inline

Return the initiation interval for this schedule.

Definition at line 619 of file MachinePipeliner.h.

Referenced by computeScheduledInsts().

◆ getInstructions()

std::deque< SUnit * > & llvm::SMSchedule::getInstructions ( int cycle )

inline

Return the instructions that are scheduled at the specified cycle.

Definition at line 673 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), computeStart(), normalizeNonPipelinedInstructions(), and llvm::SwingSchedulerDAG::schedule().

◆ getMaxStageCount()

unsigned llvm::SMSchedule::getMaxStageCount ( )

inline

Return the maximum stage count needed for this schedule.

Definition at line 668 of file MachinePipeliner.h.

Referenced by computeScheduledInsts(), finalizeSchedule(), and llvm::SwingSchedulerDAG::schedule().

◆ insert()

bool SMSchedule::insert	(	SUnit *	SU,
		int	StartCycle,
		int	EndCycle,
		int	II
	)

Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached.

This function returns true if the node is scheduled. This routine may search either forward or backward for a place to insert the instruction based upon the relative values of StartCycle and EndCycle.

Definition at line 2779 of file MachinePipeliner.cpp.

References llvm::ResourceManager::canReserveResources(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOpcode(), II, and LLVM_DEBUG.