LLVM  16.0.0git
Public Types | Public Member Functions | List of all members
llvm::SMSchedule Class Reference

This class represents the scheduled code. More...

#include "llvm/CodeGen/MachinePipeliner.h"

Public Types

using sched_iterator = DenseMap< int, std::deque< SUnit * > >::iterator
 Iterators for the cycle to instruction map. More...
 
using const_sched_iterator = DenseMap< int, std::deque< SUnit * > >::const_iterator
 

Public Member Functions

 SMSchedule (MachineFunction *mf, SwingSchedulerDAG *DAG)
 
void reset ()
 
void setInitiationInterval (int ii)
 Set the initiation interval for this schedule. More...
 
int getInitiationInterval () const
 Return the initiation interval for this schedule. More...
 
int getFirstCycle () const
 Return the first cycle in the completed schedule. More...
 
int getFinalCycle () const
 Return the last cycle in the finalized schedule. More...
 
int earliestCycleInChain (const SDep &Dep)
 Return the cycle of the earliest scheduled instruction in the dependence chain. More...
 
int latestCycleInChain (const SDep &Dep)
 Return the cycle of the latest scheduled instruction in the dependence chain. More...
 
void computeStart (SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG)
 Compute the scheduling start slot for the instruction. More...
 
bool insert (SUnit *SU, int StartCycle, int EndCycle, int II)
 Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached. More...
 
bool isScheduledAtStage (SUnit *SU, unsigned StageNum)
 Return true if the instruction is scheduled at the specified stage. More...
 
int stageScheduled (SUnit *SU) const
 Return the stage for a scheduled instruction. More...
 
unsigned cycleScheduled (SUnit *SU) const
 Return the cycle for a scheduled instruction. More...
 
unsigned getMaxStageCount ()
 Return the maximum stage count needed for this schedule. More...
 
std::deque< SUnit * > & getInstructions (int cycle)
 Return the instructions that are scheduled at the specified cycle. More...
 
SmallSet< SUnit *, 8 > computeUnpipelineableNodes (SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
 Determine transitive dependences of unpipelineable instructions. More...
 
bool normalizeNonPipelinedInstructions (SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
 
bool isValidSchedule (SwingSchedulerDAG *SSD)
 
void finalizeSchedule (SwingSchedulerDAG *SSD)
 After the schedule has been formed, call this function to combine the instructions from the different stages/cycles. More...
 
void orderDependence (SwingSchedulerDAG *SSD, SUnit *SU, std::deque< SUnit * > &Insts)
 Order the instructions within a cycle so that the definitions occur before the uses. More...
 
bool isLoopCarried (SwingSchedulerDAG *SSD, MachineInstr &Phi)
 Return true if the scheduled Phi has a loop carried operand. More...
 
bool isLoopCarriedDefOfUse (SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO)
 Return true if the instruction is a definition that is loop carried and defines the use on the next iteration. More...
 
void print (raw_ostream &os) const
 Print the schedule information to the given output. More...
 
void dump () const
 Utility function used for debugging to print the schedule. More...
 

Detailed Description

This class represents the scheduled code.

The main data structure is a map from scheduled cycle to instructions. During scheduling, the data structure explicitly represents all stages/iterations. When the algorithm finshes, the schedule is collapsed into a single stage, which represents instructions from different loop iterations.

The SMS algorithm allows negative values for cycles, so the first cycle in the schedule is the smallest cycle value.

Definition at line 532 of file MachinePipeliner.h.

Member Typedef Documentation

◆ const_sched_iterator

Definition at line 602 of file MachinePipeliner.h.

◆ sched_iterator

using llvm::SMSchedule::sched_iterator = DenseMap<int, std::deque<SUnit *> >::iterator

Iterators for the cycle to instruction map.

Definition at line 600 of file MachinePipeliner.h.

Constructor & Destructor Documentation

◆ SMSchedule()

llvm::SMSchedule::SMSchedule ( MachineFunction mf,
SwingSchedulerDAG DAG 
)
inline

Definition at line 559 of file MachinePipeliner.h.

References MRI.

Member Function Documentation

◆ computeStart()

void SMSchedule::computeStart ( SUnit SU,
int MaxEarlyStart,
int MinLateStart,
int MinEnd,
int MaxStart,
int  II,
SwingSchedulerDAG DAG 
)

Compute the scheduling start slot for the instruction.

The start slot depends on any predecessor or successor nodes scheduled already.

Definition at line 2428 of file MachinePipeliner.cpp.

References llvm::numbers::e, llvm::SwingSchedulerDAG::getDistance(), getFirstCycle(), getInstructions(), llvm::SDep::getLatency(), llvm::SDep::getSUnit(), i, I, llvm::SwingSchedulerDAG::isBackedge(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::max(), and llvm::SUnit::Preds.

◆ computeUnpipelineableNodes()

SmallSet< SUnit *, 8 > SMSchedule::computeUnpipelineableNodes ( SwingSchedulerDAG SSD,
TargetInstrInfo::PipelinerLoopInfo PLI 
)

◆ cycleScheduled()

unsigned llvm::SMSchedule::cycleScheduled ( SUnit SU) const
inline

Return the cycle for a scheduled instruction.

This function normalizes the first cycle to be 0.

Definition at line 620 of file MachinePipeliner.h.

References assert(), and it.

Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), isLoopCarried(), and orderDependence().

◆ dump()

LLVM_DUMP_METHOD void SMSchedule::dump ( ) const

Utility function used for debugging to print the schedule.

Definition at line 2977 of file MachinePipeliner.cpp.

References llvm::dbgs(), and print().

Referenced by finalizeSchedule().

◆ earliestCycleInChain()

int SMSchedule::earliestCycleInChain ( const SDep Dep)

◆ finalizeSchedule()

void SMSchedule::finalizeSchedule ( SwingSchedulerDAG SSD)

After the schedule has been formed, call this function to combine the instructions from the different stages/cycles.

That is, this function creates a schedule that represents a single iteration.

Definition at line 2907 of file MachinePipeliner.cpp.

References llvm::append_range(), llvm::SwingSchedulerDAG::applyInstrChange(), dump(), E, llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), getMaxStageCount(), llvm::MachineInstr::isPHI(), LLVM_DEBUG, orderDependence(), llvm::reverse(), and llvm::ScheduleDAG::SUnits.

◆ getFinalCycle()

int llvm::SMSchedule::getFinalCycle ( ) const
inline

Return the last cycle in the finalized schedule.

Definition at line 585 of file MachinePipeliner.h.

Referenced by finalizeSchedule(), print(), and llvm::SwingSchedulerDAG::schedule().

◆ getFirstCycle()

int llvm::SMSchedule::getFirstCycle ( ) const
inline

Return the first cycle in the completed schedule.

This can be a negative value.

Definition at line 582 of file MachinePipeliner.h.

Referenced by computeStart(), finalizeSchedule(), normalizeNonPipelinedInstructions(), print(), and llvm::SwingSchedulerDAG::schedule().

◆ getInitiationInterval()

int llvm::SMSchedule::getInitiationInterval ( ) const
inline

Return the initiation interval for this schedule.

Definition at line 578 of file MachinePipeliner.h.

◆ getInstructions()

std::deque<SUnit *>& llvm::SMSchedule::getInstructions ( int  cycle)
inline

Return the instructions that are scheduled at the specified cycle.

Definition at line 632 of file MachinePipeliner.h.

Referenced by computeStart(), normalizeNonPipelinedInstructions(), and llvm::SwingSchedulerDAG::schedule().

◆ getMaxStageCount()

unsigned llvm::SMSchedule::getMaxStageCount ( )
inline

Return the maximum stage count needed for this schedule.

Definition at line 627 of file MachinePipeliner.h.

Referenced by finalizeSchedule(), and llvm::SwingSchedulerDAG::schedule().

◆ insert()

bool SMSchedule::insert ( SUnit SU,
int  StartCycle,
int  EndCycle,
int  II 
)

Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached.

This function returns true if the node is scheduled. This routine may search either forward or backward for a place to insert the instruction based upon the relative values of StartCycle and EndCycle.

Definition at line 2329 of file MachinePipeliner.cpp.

References llvm::ResourceManager::canReserveResources(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOpcode(), and LLVM_DEBUG.

◆ isLoopCarried()

bool SMSchedule::isLoopCarried ( SwingSchedulerDAG SSD,
MachineInstr Phi 
)

◆ isLoopCarriedDefOfUse()

bool SMSchedule::isLoopCarriedDefOfUse ( SwingSchedulerDAG SSD,
MachineInstr Def,
MachineOperand MO 
)

Return true if the instruction is a definition that is loop carried and defines the use on the next iteration.

v1 = phi(v2, v3) (Def) v3 = op v1 (MO) = v1 If MO appears before Def, then then v1 and v3 may get assigned to the same register.

Definition at line 2645 of file MachinePipeliner.cpp.

References llvm::tgtok::Def, llvm::numbers::e, getLoopPhiReg(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getVRegDef(), i, llvm::MachineOperand::isDef(), isLoopCarried(), llvm::MachineInstr::isPHI(), llvm::MachineOperand::isReg(), and MRI.

Referenced by orderDependence().

◆ isScheduledAtStage()

bool llvm::SMSchedule::isScheduledAtStage ( SUnit SU,
unsigned  StageNum 
)
inline

Return true if the instruction is scheduled at the specified stage.

Definition at line 605 of file MachinePipeliner.h.

References stageScheduled().

◆ isValidSchedule()

bool SMSchedule::isValidSchedule ( SwingSchedulerDAG SSD)

◆ latestCycleInChain()

int SMSchedule::latestCycleInChain ( const SDep Dep)

◆ normalizeNonPipelinedInstructions()

bool SMSchedule::normalizeNonPipelinedInstructions ( SwingSchedulerDAG SSD,
TargetInstrInfo::PipelinerLoopInfo PLI 
)

◆ orderDependence()

void SMSchedule::orderDependence ( SwingSchedulerDAG SSD,
SUnit SU,
std::deque< SUnit * > &  Insts 
)

Order the instructions within a cycle so that the definitions occur before the uses.

Returns true if the instruction is added to the start of the list, or false if added to the end.

Definition at line 2489 of file MachinePipeliner.cpp.

References llvm::SDep::Anti, cycleScheduled(), E, llvm::SUnit::getInstr(), llvm::SwingSchedulerDAG::getInstrBaseReg(), I, isLoopCarriedDefOfUse(), llvm::Register::isVirtualRegister(), MI, llvm::SDep::Order, P, llvm::SUnit::Preds, S, stageScheduled(), and llvm::SUnit::Succs.

Referenced by finalizeSchedule().

◆ print()

void SMSchedule::print ( raw_ostream os) const

Print the schedule information to the given output.

Definition at line 2962 of file MachinePipeliner.cpp.

References getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), llvm::SUnit::NodeNum, llvm::MachineInstr::print(), and stageScheduled().

Referenced by dump().

◆ reset()

void llvm::SMSchedule::reset ( )
inline

◆ setInitiationInterval()

void llvm::SMSchedule::setInitiationInterval ( int  ii)
inline

Set the initiation interval for this schedule.

Definition at line 572 of file MachinePipeliner.h.

References llvm::ResourceManager::init().

◆ stageScheduled()

int llvm::SMSchedule::stageScheduled ( SUnit SU) const
inline

Return the stage for a scheduled instruction.

Return -1 if the instruction has not been scheduled.

Definition at line 611 of file MachinePipeliner.h.

References it.

Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), isLoopCarried(), isScheduledAtStage(), isValidSchedule(), normalizeNonPipelinedInstructions(), orderDependence(), print(), and llvm::SwingSchedulerDAG::schedule().


The documentation for this class was generated from the following files: