LLVM 18.0.0git
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This class represents the scheduled code. More...
#include "llvm/CodeGen/MachinePipeliner.h"
Public Types | |
using | sched_iterator = DenseMap< int, std::deque< SUnit * > >::iterator |
Iterators for the cycle to instruction map. | |
using | const_sched_iterator = DenseMap< int, std::deque< SUnit * > >::const_iterator |
Public Member Functions | |
SMSchedule (MachineFunction *mf, SwingSchedulerDAG *DAG) | |
void | reset () |
void | setInitiationInterval (int ii) |
Set the initiation interval for this schedule. | |
int | getInitiationInterval () const |
Return the initiation interval for this schedule. | |
int | getFirstCycle () const |
Return the first cycle in the completed schedule. | |
int | getFinalCycle () const |
Return the last cycle in the finalized schedule. | |
int | earliestCycleInChain (const SDep &Dep) |
Return the cycle of the earliest scheduled instruction in the dependence chain. | |
int | latestCycleInChain (const SDep &Dep) |
Return the cycle of the latest scheduled instruction in the dependence chain. | |
void | computeStart (SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG) |
Compute the scheduling start slot for the instruction. | |
bool | insert (SUnit *SU, int StartCycle, int EndCycle, int II) |
Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached. | |
bool | isScheduledAtStage (SUnit *SU, unsigned StageNum) |
Return true if the instruction is scheduled at the specified stage. | |
int | stageScheduled (SUnit *SU) const |
Return the stage for a scheduled instruction. | |
unsigned | cycleScheduled (SUnit *SU) const |
Return the cycle for a scheduled instruction. | |
unsigned | getMaxStageCount () |
Return the maximum stage count needed for this schedule. | |
std::deque< SUnit * > & | getInstructions (int cycle) |
Return the instructions that are scheduled at the specified cycle. | |
SmallSet< SUnit *, 8 > | computeUnpipelineableNodes (SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) |
Determine transitive dependences of unpipelineable instructions. | |
bool | normalizeNonPipelinedInstructions (SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) |
bool | isValidSchedule (SwingSchedulerDAG *SSD) |
void | finalizeSchedule (SwingSchedulerDAG *SSD) |
After the schedule has been formed, call this function to combine the instructions from the different stages/cycles. | |
void | orderDependence (SwingSchedulerDAG *SSD, SUnit *SU, std::deque< SUnit * > &Insts) |
Order the instructions within a cycle so that the definitions occur before the uses. | |
bool | isLoopCarried (SwingSchedulerDAG *SSD, MachineInstr &Phi) |
Return true if the scheduled Phi has a loop carried operand. | |
bool | isLoopCarriedDefOfUse (SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO) |
Return true if the instruction is a definition that is loop carried and defines the use on the next iteration. | |
void | print (raw_ostream &os) const |
Print the schedule information to the given output. | |
void | dump () const |
Utility function used for debugging to print the schedule. | |
This class represents the scheduled code.
The main data structure is a map from scheduled cycle to instructions. During scheduling, the data structure explicitly represents all stages/iterations. When the algorithm finshes, the schedule is collapsed into a single stage, which represents instructions from different loop iterations.
The SMS algorithm allows negative values for cycles, so the first cycle in the schedule is the smallest cycle value.
Definition at line 534 of file MachinePipeliner.h.
using llvm::SMSchedule::const_sched_iterator = DenseMap<int, std::deque<SUnit *> >::const_iterator |
Definition at line 603 of file MachinePipeliner.h.
using llvm::SMSchedule::sched_iterator = DenseMap<int, std::deque<SUnit *> >::iterator |
Iterators for the cycle to instruction map.
Definition at line 602 of file MachinePipeliner.h.
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Definition at line 561 of file MachinePipeliner.h.
References MRI.
void SMSchedule::computeStart | ( | SUnit * | SU, |
int * | MaxEarlyStart, | ||
int * | MinLateStart, | ||
int * | MinEnd, | ||
int * | MaxStart, | ||
int | II, | ||
SwingSchedulerDAG * | DAG | ||
) |
Compute the scheduling start slot for the instruction.
The start slot depends on any predecessor or successor nodes scheduled already.
Definition at line 2423 of file MachinePipeliner.cpp.
References earliestCycleInChain(), End, llvm::SwingSchedulerDAG::getDistance(), getFirstCycle(), llvm::SUnit::getInstr(), getInstructions(), llvm::SDep::getLatency(), llvm::SDep::getSUnit(), I, llvm::SwingSchedulerDAG::isBackedge(), llvm::SwingSchedulerDAG::isLoopCarriedDep(), llvm::MachineInstr::isPHI(), llvm::SUnit::isPred(), latestCycleInChain(), multipleIterations(), llvm::SUnit::Preds, and llvm::SUnit::Succs.
SmallSet< SUnit *, 8 > SMSchedule::computeUnpipelineableNodes | ( | SwingSchedulerDAG * | SSD, |
TargetInstrInfo::PipelinerLoopInfo * | PLI | ||
) |
Determine transitive dependences of unpipelineable instructions.
Definition at line 2660 of file MachinePipeliner.cpp.
References llvm::SDep::Anti, llvm::SmallSet< T, N, C >::count(), llvm::dbgs(), llvm::SmallVectorBase< Size_T >::empty(), llvm::SUnit::getInstr(), llvm::SmallSet< T, N, C >::insert(), llvm::SUnit::isInstr(), llvm::MachineInstr::isPHI(), LLVM_DEBUG, llvm::SUnit::NodeNum, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SUnit::Preds, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::TargetInstrInfo::PipelinerLoopInfo::shouldIgnoreForPipelining(), llvm::SUnit::Succs, and llvm::ScheduleDAG::SUnits.
Referenced by normalizeNonPipelinedInstructions().
Return the cycle for a scheduled instruction.
This function normalizes the first cycle to be 0.
Definition at line 622 of file MachinePipeliner.h.
References assert().
Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), isLoopCarried(), and orderDependence().
LLVM_DUMP_METHOD void SMSchedule::dump | ( | ) | const |
Utility function used for debugging to print the schedule.
Definition at line 2969 of file MachinePipeliner.cpp.
References llvm::dbgs(), and print().
Referenced by finalizeSchedule().
Return the cycle of the earliest scheduled instruction in the dependence chain.
Definition at line 2364 of file MachinePipeliner.cpp.
References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorBase< Size_T >::empty(), llvm::SDep::getSUnit(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SDep::Order, llvm::SDep::Output, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SUnit::Preds, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by computeStart().
void SMSchedule::finalizeSchedule | ( | SwingSchedulerDAG * | SSD | ) |
After the schedule has been formed, call this function to combine the instructions from the different stages/cycles.
That is, this function creates a schedule that represents a single iteration.
Definition at line 2899 of file MachinePipeliner.cpp.
References llvm::append_range(), llvm::SwingSchedulerDAG::applyInstrChange(), dump(), E, llvm::SwingSchedulerDAG::fixupRegisterOverlaps(), getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), getMaxStageCount(), llvm::MachineInstr::isPHI(), LLVM_DEBUG, orderDependence(), llvm::reverse(), and llvm::ScheduleDAG::SUnits.
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Return the last cycle in the finalized schedule.
Definition at line 587 of file MachinePipeliner.h.
Referenced by finalizeSchedule(), print(), and llvm::SwingSchedulerDAG::schedule().
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Return the first cycle in the completed schedule.
This can be a negative value.
Definition at line 584 of file MachinePipeliner.h.
Referenced by computeStart(), finalizeSchedule(), normalizeNonPipelinedInstructions(), print(), and llvm::SwingSchedulerDAG::schedule().
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Return the initiation interval for this schedule.
Definition at line 580 of file MachinePipeliner.h.
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Return the instructions that are scheduled at the specified cycle.
Definition at line 634 of file MachinePipeliner.h.
Referenced by computeStart(), normalizeNonPipelinedInstructions(), and llvm::SwingSchedulerDAG::schedule().
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Return the maximum stage count needed for this schedule.
Definition at line 629 of file MachinePipeliner.h.
Referenced by finalizeSchedule(), and llvm::SwingSchedulerDAG::schedule().
Try to schedule the node at the specified StartCycle and continue until the node is schedule or the EndCycle is reached.
This function returns true if the node is scheduled. This routine may search either forward or backward for a place to insert the instruction based upon the relative values of StartCycle and EndCycle.
Definition at line 2324 of file MachinePipeliner.cpp.
References llvm::ResourceManager::canReserveResources(), llvm::dbgs(), llvm::MachineInstr::dump(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOpcode(), and LLVM_DEBUG.
bool SMSchedule::isLoopCarried | ( | SwingSchedulerDAG * | SSD, |
MachineInstr & | Phi | ||
) |
Return true if the scheduled Phi has a loop carried operand.
Definition at line 2612 of file MachinePipeliner.cpp.
References assert(), cycleScheduled(), llvm::SUnit::getInstr(), getPhiRegs(), llvm::ScheduleDAGInstrs::getSUnit(), llvm::MachineInstr::isPHI(), MRI, and stageScheduled().
Referenced by isLoopCarriedDefOfUse().
bool SMSchedule::isLoopCarriedDefOfUse | ( | SwingSchedulerDAG * | SSD, |
MachineInstr * | Def, | ||
MachineOperand & | MO | ||
) |
Return true if the instruction is a definition that is loop carried and defines the use on the next iteration.
v1 = phi(v2, v3) (Def) v3 = op v1 (MO) = v1 If MO appears before Def, then v1 and v3 may get assigned to the same register.
Definition at line 2640 of file MachinePipeliner.cpp.
References getLoopPhiReg(), llvm::MachineOperand::getReg(), isLoopCarried(), llvm::MachineOperand::isReg(), and MRI.
Referenced by orderDependence().
Return true if the instruction is scheduled at the specified stage.
Definition at line 607 of file MachinePipeliner.h.
References stageScheduled().
bool SMSchedule::isValidSchedule | ( | SwingSchedulerDAG * | SSD | ) |
Definition at line 2729 of file MachinePipeliner.cpp.
References assert(), llvm::SUnit::hasPhysRegDefs, llvm::Register::isPhysicalRegister(), stageScheduled(), llvm::SUnit::Succs, and llvm::ScheduleDAG::SUnits.
Return the cycle of the latest scheduled instruction in the dependence chain.
Definition at line 2387 of file MachinePipeliner.cpp.
References llvm::SmallPtrSetImpl< PtrType >::count(), llvm::SmallVectorBase< Size_T >::empty(), llvm::SDep::getSUnit(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::SUnit::isBoundaryNode(), llvm::SDep::Order, llvm::SDep::Output, llvm::SmallVectorImpl< T >::pop_back_val(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::SUnit::Succs.
Referenced by computeStart().
bool SMSchedule::normalizeNonPipelinedInstructions | ( | SwingSchedulerDAG * | SSD, |
TargetInstrInfo::PipelinerLoopInfo * | PLI | ||
) |
Definition at line 2687 of file MachinePipeliner.cpp.
References computeUnpipelineableNodes(), llvm::SmallSet< T, N, C >::contains(), llvm::dbgs(), llvm::erase(), getFirstCycle(), llvm::SUnit::getInstr(), getInstructions(), llvm::SUnit::isInstr(), LLVM_DEBUG, llvm::SUnit::NodeNum, llvm::SUnit::Preds, stageScheduled(), and llvm::ScheduleDAG::SUnits.
void SMSchedule::orderDependence | ( | SwingSchedulerDAG * | SSD, |
SUnit * | SU, | ||
std::deque< SUnit * > & | Insts | ||
) |
Order the instructions within a cycle so that the definitions occur before the uses.
Returns true if the instruction is added to the start of the list, or false if added to the end.
Definition at line 2484 of file MachinePipeliner.cpp.
References llvm::SDep::Anti, cycleScheduled(), E, llvm::SUnit::getInstr(), llvm::SwingSchedulerDAG::getInstrBaseReg(), llvm::SDep::getKind(), llvm::SDep::getSUnit(), I, isLoopCarriedDefOfUse(), MI, llvm::SDep::Order, orderDependence(), P, llvm::SUnit::Preds, stageScheduled(), llvm::SUnit::Succs, and Writes.
Referenced by finalizeSchedule(), and orderDependence().
void SMSchedule::print | ( | raw_ostream & | os | ) | const |
Print the schedule information to the given output.
Definition at line 2954 of file MachinePipeliner.cpp.
References getFinalCycle(), getFirstCycle(), llvm::SUnit::getInstr(), llvm::SUnit::NodeNum, llvm::MachineInstr::print(), and stageScheduled().
Referenced by dump().
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Definition at line 565 of file MachinePipeliner.h.
References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::clear().
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Set the initiation interval for this schedule.
Definition at line 574 of file MachinePipeliner.h.
References llvm::ResourceManager::init().
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Return the stage for a scheduled instruction.
Return -1 if the instruction has not been scheduled.
Definition at line 613 of file MachinePipeliner.h.
Referenced by llvm::SwingSchedulerDAG::applyInstrChange(), isLoopCarried(), isScheduledAtStage(), isValidSchedule(), normalizeNonPipelinedInstructions(), orderDependence(), print(), and llvm::SwingSchedulerDAG::schedule().