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MachinePipeliner.h
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1 //===- MachinePipeliner.h - Machine Software Pipeliner Pass -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // An implementation of the Swing Modulo Scheduling (SMS) software pipeliner.
10 //
11 // Software pipelining (SWP) is an instruction scheduling technique for loops
12 // that overlap loop iterations and exploits ILP via a compiler transformation.
13 //
14 // Swing Modulo Scheduling is an implementation of software pipelining
15 // that generates schedules that are near optimal in terms of initiation
16 // interval, register requirements, and stage count. See the papers:
17 //
18 // "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa,
19 // A. Gonzalez, E. Ayguade, and M. Valero. In PACT '96 Proceedings of the 1996
20 // Conference on Parallel Architectures and Compilation Techiniques.
21 //
22 // "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J.
23 // Llosa, E. Ayguade, A. Gonzalez, M. Valero, and J. Eckhardt. In IEEE
24 // Transactions on Computers, Vol. 50, No. 3, 2001.
25 //
26 // "An Implementation of Swing Modulo Scheduling With Extensions for
27 // Superblocks", by T. Lattner, Master's Thesis, University of Illinois at
28 // Urbana-Champaign, 2005.
29 //
30 //
31 // The SMS algorithm consists of three main steps after computing the minimal
32 // initiation interval (MII).
33 // 1) Analyze the dependence graph and compute information about each
34 // instruction in the graph.
35 // 2) Order the nodes (instructions) by priority based upon the heuristics
36 // described in the algorithm.
37 // 3) Attempt to schedule the nodes in the specified order using the MII.
38 //
39 //===----------------------------------------------------------------------===//
40 #ifndef LLVM_CODEGEN_MACHINEPIPELINER_H
41 #define LLVM_CODEGEN_MACHINEPIPELINER_H
42 
43 #include "llvm/ADT/SetVector.h"
50 #include "llvm/InitializePasses.h"
51 
52 #include <deque>
53 
54 namespace llvm {
55 
56 class AAResults;
57 class NodeSet;
58 class SMSchedule;
59 
60 extern cl::opt<bool> SwpEnableCopyToPhi;
61 extern cl::opt<int> SwpForceIssueWidth;
62 
63 /// The main class in the implementation of the target independent
64 /// software pipeliner pass.
66 public:
67  MachineFunction *MF = nullptr;
69  const MachineLoopInfo *MLI = nullptr;
70  const MachineDominatorTree *MDT = nullptr;
72  const TargetInstrInfo *TII = nullptr;
74  bool disabledByPragma = false;
75  unsigned II_setByPragma = 0;
76 
77 #ifndef NDEBUG
78  static int NumTries;
79 #endif
80 
81  /// Cache the target analysis information about the loop.
82  struct LoopInfo {
83  MachineBasicBlock *TBB = nullptr;
84  MachineBasicBlock *FBB = nullptr;
88  std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> LoopPipelinerInfo =
89  nullptr;
90  };
92 
93  static char ID;
94 
97  }
98 
99  bool runOnMachineFunction(MachineFunction &MF) override;
100 
101  void getAnalysisUsage(AnalysisUsage &AU) const override;
102 
103 private:
104  void preprocessPhiNodes(MachineBasicBlock &B);
105  bool canPipelineLoop(MachineLoop &L);
106  bool scheduleLoop(MachineLoop &L);
107  bool swingModuloScheduler(MachineLoop &L);
108  void setPragmaPipelineOptions(MachineLoop &L);
109 };
110 
111 /// This class builds the dependence graph for the instructions in a loop,
112 /// and attempts to schedule the instructions using the SMS algorithm.
115  /// The minimum initiation interval between iterations for this schedule.
116  unsigned MII = 0;
117  /// The maximum initiation interval between iterations for this schedule.
118  unsigned MAX_II = 0;
119  /// Set to true if a valid pipelined schedule is found for the loop.
120  bool Scheduled = false;
121  MachineLoop &Loop;
122  LiveIntervals &LIS;
123  const RegisterClassInfo &RegClassInfo;
124  unsigned II_setByPragma = 0;
125  TargetInstrInfo::PipelinerLoopInfo *LoopPipelinerInfo = nullptr;
126 
127  /// A toplogical ordering of the SUnits, which is needed for changing
128  /// dependences and iterating over the SUnits.
130 
131  struct NodeInfo {
132  int ASAP = 0;
133  int ALAP = 0;
134  int ZeroLatencyDepth = 0;
135  int ZeroLatencyHeight = 0;
136 
137  NodeInfo() = default;
138  };
139  /// Computed properties for each node in the graph.
140  std::vector<NodeInfo> ScheduleInfo;
141 
142  enum OrderKind { BottomUp = 0, TopDown = 1 };
143  /// Computed node ordering for scheduling.
144  SetVector<SUnit *> NodeOrder;
145 
150 
151  /// Instructions to change when emitting the final schedule.
153 
154  /// We may create a new instruction, so remember it because it
155  /// must be deleted when the pass is finished.
157 
158  /// Ordered list of DAG postprocessing steps.
159  std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
160 
161  /// Helper class to implement Johnson's circuit finding algorithm.
162  class Circuits {
163  std::vector<SUnit> &SUnits;
164  SetVector<SUnit *> Stack;
165  BitVector Blocked;
168  // Node to Index from ScheduleDAGTopologicalSort
169  std::vector<int> *Node2Idx;
170  unsigned NumPaths;
171  static unsigned MaxPaths;
172 
173  public:
174  Circuits(std::vector<SUnit> &SUs, ScheduleDAGTopologicalSort &Topo)
175  : SUnits(SUs), Blocked(SUs.size()), B(SUs.size()), AdjK(SUs.size()) {
176  Node2Idx = new std::vector<int>(SUs.size());
177  unsigned Idx = 0;
178  for (const auto &NodeNum : Topo)
179  Node2Idx->at(NodeNum) = Idx++;
180  }
181 
182  ~Circuits() { delete Node2Idx; }
183 
184  /// Reset the data structures used in the circuit algorithm.
185  void reset() {
186  Stack.clear();
187  Blocked.reset();
188  B.assign(SUnits.size(), SmallPtrSet<SUnit *, 4>());
189  NumPaths = 0;
190  }
191 
192  void createAdjacencyStructure(SwingSchedulerDAG *DAG);
193  bool circuit(int V, int S, NodeSetType &NodeSets, bool HasBackedge = false);
194  void unblock(int U);
195  };
196 
197  struct CopyToPhiMutation : public ScheduleDAGMutation {
198  void apply(ScheduleDAGInstrs *DAG) override;
199  };
200 
201 public:
203  const RegisterClassInfo &rci, unsigned II,
205  : ScheduleDAGInstrs(*P.MF, P.MLI, false), Pass(P), Loop(L), LIS(lis),
206  RegClassInfo(rci), II_setByPragma(II), LoopPipelinerInfo(PLI),
207  Topo(SUnits, &ExitSU) {
208  P.MF->getSubtarget().getSMSMutations(Mutations);
209  if (SwpEnableCopyToPhi)
210  Mutations.push_back(std::make_unique<CopyToPhiMutation>());
211  }
212 
213  void schedule() override;
214  void finishBlock() override;
215 
216  /// Return true if the loop kernel has been scheduled.
217  bool hasNewSchedule() { return Scheduled; }
218 
219  /// Return the earliest time an instruction may be scheduled.
220  int getASAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ASAP; }
221 
222  /// Return the latest time an instruction my be scheduled.
223  int getALAP(SUnit *Node) { return ScheduleInfo[Node->NodeNum].ALAP; }
224 
225  /// The mobility function, which the number of slots in which
226  /// an instruction may be scheduled.
227  int getMOV(SUnit *Node) { return getALAP(Node) - getASAP(Node); }
228 
229  /// The depth, in the dependence graph, for a node.
230  unsigned getDepth(SUnit *Node) { return Node->getDepth(); }
231 
232  /// The maximum unweighted length of a path from an arbitrary node to the
233  /// given node in which each edge has latency 0
235  return ScheduleInfo[Node->NodeNum].ZeroLatencyDepth;
236  }
237 
238  /// The height, in the dependence graph, for a node.
239  unsigned getHeight(SUnit *Node) { return Node->getHeight(); }
240 
241  /// The maximum unweighted length of a path from the given node to an
242  /// arbitrary node in which each edge has latency 0
244  return ScheduleInfo[Node->NodeNum].ZeroLatencyHeight;
245  }
246 
247  /// Return true if the dependence is a back-edge in the data dependence graph.
248  /// Since the DAG doesn't contain cycles, we represent a cycle in the graph
249  /// using an anti dependence from a Phi to an instruction.
250  bool isBackedge(SUnit *Source, const SDep &Dep) {
251  if (Dep.getKind() != SDep::Anti)
252  return false;
253  return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI();
254  }
255 
256  bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc = true);
257 
258  /// The distance function, which indicates that operation V of iteration I
259  /// depends on operations U of iteration I-distance.
260  unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep) {
261  // Instructions that feed a Phi have a distance of 1. Computing larger
262  // values for arrays requires data dependence information.
263  if (V->getInstr()->isPHI() && Dep.getKind() == SDep::Anti)
264  return 1;
265  return 0;
266  }
267 
268  void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule);
269 
270  void fixupRegisterOverlaps(std::deque<SUnit *> &Instrs);
271 
272  /// Return the new base register that was stored away for the changed
273  /// instruction.
274  unsigned getInstrBaseReg(SUnit *SU) {
276  InstrChanges.find(SU);
277  if (It != InstrChanges.end())
278  return It->second.first;
279  return 0;
280  }
281 
282  void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
283  Mutations.push_back(std::move(Mutation));
284  }
285 
286  static bool classof(const ScheduleDAGInstrs *DAG) { return true; }
287 
288 private:
289  void addLoopCarriedDependences(AAResults *AA);
290  void updatePhiDependences();
291  void changeDependences();
292  unsigned calculateResMII();
293  unsigned calculateRecMII(NodeSetType &RecNodeSets);
294  void findCircuits(NodeSetType &NodeSets);
295  void fuseRecs(NodeSetType &NodeSets);
296  void removeDuplicateNodes(NodeSetType &NodeSets);
297  void computeNodeFunctions(NodeSetType &NodeSets);
298  void registerPressureFilter(NodeSetType &NodeSets);
299  void colocateNodeSets(NodeSetType &NodeSets);
300  void checkNodeSets(NodeSetType &NodeSets);
301  void groupRemainingNodes(NodeSetType &NodeSets);
302  void addConnectedNodes(SUnit *SU, NodeSet &NewSet,
303  SetVector<SUnit *> &NodesAdded);
304  void computeNodeOrder(NodeSetType &NodeSets);
305  void checkValidNodeOrder(const NodeSetType &Circuits) const;
306  bool schedulePipeline(SMSchedule &Schedule);
307  bool computeDelta(MachineInstr &MI, unsigned &Delta);
308  MachineInstr *findDefInLoop(Register Reg);
309  bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos,
310  unsigned &OffsetPos, unsigned &NewBase,
311  int64_t &NewOffset);
312  void postprocessDAG();
313  /// Set the Minimum Initiation Interval for this schedule attempt.
314  void setMII(unsigned ResMII, unsigned RecMII);
315  /// Set the Maximum Initiation Interval for this schedule attempt.
316  void setMAX_II();
317 };
318 
319 /// A NodeSet contains a set of SUnit DAG nodes with additional information
320 /// that assigns a priority to the set.
321 class NodeSet {
322  SetVector<SUnit *> Nodes;
323  bool HasRecurrence = false;
324  unsigned RecMII = 0;
325  int MaxMOV = 0;
326  unsigned MaxDepth = 0;
327  unsigned Colocate = 0;
328  SUnit *ExceedPressure = nullptr;
329  unsigned Latency = 0;
330 
331 public:
333 
334  NodeSet() = default;
335  NodeSet(iterator S, iterator E) : Nodes(S, E), HasRecurrence(true) {
336  Latency = 0;
337  for (const SUnit *Node : Nodes) {
338  DenseMap<SUnit *, unsigned> SuccSUnitLatency;
339  for (const SDep &Succ : Node->Succs) {
340  auto SuccSUnit = Succ.getSUnit();
341  if (!Nodes.count(SuccSUnit))
342  continue;
343  unsigned CurLatency = Succ.getLatency();
344  unsigned MaxLatency = 0;
345  if (SuccSUnitLatency.count(SuccSUnit))
346  MaxLatency = SuccSUnitLatency[SuccSUnit];
347  if (CurLatency > MaxLatency)
348  SuccSUnitLatency[SuccSUnit] = CurLatency;
349  }
350  for (auto SUnitLatency : SuccSUnitLatency)
351  Latency += SUnitLatency.second;
352  }
353  }
354 
355  bool insert(SUnit *SU) { return Nodes.insert(SU); }
356 
357  void insert(iterator S, iterator E) { Nodes.insert(S, E); }
358 
359  template <typename UnaryPredicate> bool remove_if(UnaryPredicate P) {
360  return Nodes.remove_if(P);
361  }
362 
363  unsigned count(SUnit *SU) const { return Nodes.count(SU); }
364 
365  bool hasRecurrence() { return HasRecurrence; };
366 
367  unsigned size() const { return Nodes.size(); }
368 
369  bool empty() const { return Nodes.empty(); }
370 
371  SUnit *getNode(unsigned i) const { return Nodes[i]; };
372 
373  void setRecMII(unsigned mii) { RecMII = mii; };
374 
375  void setColocate(unsigned c) { Colocate = c; };
376 
377  void setExceedPressure(SUnit *SU) { ExceedPressure = SU; }
378 
379  bool isExceedSU(SUnit *SU) { return ExceedPressure == SU; }
380 
381  int compareRecMII(NodeSet &RHS) { return RecMII - RHS.RecMII; }
382 
383  int getRecMII() { return RecMII; }
384 
385  /// Summarize node functions for the entire node set.
387  for (SUnit *SU : *this) {
388  MaxMOV = std::max(MaxMOV, SSD->getMOV(SU));
389  MaxDepth = std::max(MaxDepth, SSD->getDepth(SU));
390  }
391  }
392 
393  unsigned getLatency() { return Latency; }
394 
395  unsigned getMaxDepth() { return MaxDepth; }
396 
397  void clear() {
398  Nodes.clear();
399  RecMII = 0;
400  HasRecurrence = false;
401  MaxMOV = 0;
402  MaxDepth = 0;
403  Colocate = 0;
404  ExceedPressure = nullptr;
405  }
406 
407  operator SetVector<SUnit *> &() { return Nodes; }
408 
409  /// Sort the node sets by importance. First, rank them by recurrence MII,
410  /// then by mobility (least mobile done first), and finally by depth.
411  /// Each node set may contain a colocate value which is used as the first
412  /// tie breaker, if it's set.
413  bool operator>(const NodeSet &RHS) const {
414  if (RecMII == RHS.RecMII) {
415  if (Colocate != 0 && RHS.Colocate != 0 && Colocate != RHS.Colocate)
416  return Colocate < RHS.Colocate;
417  if (MaxMOV == RHS.MaxMOV)
418  return MaxDepth > RHS.MaxDepth;
419  return MaxMOV < RHS.MaxMOV;
420  }
421  return RecMII > RHS.RecMII;
422  }
423 
424  bool operator==(const NodeSet &RHS) const {
425  return RecMII == RHS.RecMII && MaxMOV == RHS.MaxMOV &&
426  MaxDepth == RHS.MaxDepth;
427  }
428 
429  bool operator!=(const NodeSet &RHS) const { return !operator==(RHS); }
430 
431  iterator begin() { return Nodes.begin(); }
432  iterator end() { return Nodes.end(); }
433  void print(raw_ostream &os) const;
434 
435 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
436  LLVM_DUMP_METHOD void dump() const;
437 #endif
438 };
439 
440 // 16 was selected based on the number of ProcResource kinds for all
441 // existing Subtargets, so that SmallVector don't need to resize too often.
442 static const int DefaultProcResSize = 16;
443 
445 private:
446  const MCSubtargetInfo *STI;
447  const MCSchedModel &SM;
448  const TargetSubtargetInfo *ST;
449  const TargetInstrInfo *TII;
450  SwingSchedulerDAG *DAG;
451  const bool UseDFA;
452  /// DFA resources for each slot
454  /// Modulo Reservation Table. When a resource with ID R is consumed in cycle
455  /// C, it is counted in MRT[C mod II][R]. (Used when UseDFA == F)
457  /// The number of scheduled micro operations for each slot. Micro operations
458  /// are assumed to be scheduled one per cycle, starting with the cycle in
459  /// which the instruction is scheduled.
460  llvm::SmallVector<int> NumScheduledMops;
461  /// Each processor resource is associated with a so-called processor resource
462  /// mask. This vector allows to correlate processor resource IDs with
463  /// processor resource masks. There is exactly one element per each processor
464  /// resource declared by the scheduling model.
466  int InitiationInterval;
467  /// The number of micro operations that can be scheduled at a cycle.
468  int IssueWidth;
469 
470  int calculateResMIIDFA() const;
471  /// Check if MRT is overbooked
472  bool isOverbooked() const;
473  /// Reserve resources on MRT
474  void reserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
475  /// Unreserve resources on MRT
476  void unreserveResources(const MCSchedClassDesc *SCDesc, int Cycle);
477 
478  /// Return M satisfying Dividend = Divisor * X + M, 0 < M < Divisor.
479  /// The slot on MRT to reserve a resource for the cycle C is positiveModulo(C,
480  /// II).
481  int positiveModulo(int Dividend, int Divisor) const {
482  assert(Divisor > 0);
483  int R = Dividend % Divisor;
484  if (R < 0)
485  R += Divisor;
486  return R;
487  }
488 
489 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
490  LLVM_DUMP_METHOD void dumpMRT() const;
491 #endif
492 
493 public:
495  : STI(ST), SM(ST->getSchedModel()), ST(ST), TII(ST->getInstrInfo()),
496  DAG(DAG), UseDFA(ST->useDFAforSMS()),
497  ProcResourceMasks(SM.getNumProcResourceKinds(), 0),
498  IssueWidth(SM.IssueWidth) {
499  initProcResourceVectors(SM, ProcResourceMasks);
500  if (IssueWidth <= 0)
501  // If IssueWidth is not specified, set a sufficiently large value
502  IssueWidth = 100;
503  if (SwpForceIssueWidth > 0)
504  IssueWidth = SwpForceIssueWidth;
505  }
506 
507  void initProcResourceVectors(const MCSchedModel &SM,
509 
510  /// Check if the resources occupied by a machine instruction are available
511  /// in the current state.
512  bool canReserveResources(SUnit &SU, int Cycle);
513 
514  /// Reserve the resources occupied by a machine instruction and change the
515  /// current state to reflect that change.
516  void reserveResources(SUnit &SU, int Cycle);
517 
518  int calculateResMII() const;
519 
520  /// Initialize resources with the initiation interval II.
521  void init(int II);
522 };
523 
524 /// This class represents the scheduled code. The main data structure is a
525 /// map from scheduled cycle to instructions. During scheduling, the
526 /// data structure explicitly represents all stages/iterations. When
527 /// the algorithm finshes, the schedule is collapsed into a single stage,
528 /// which represents instructions from different loop iterations.
529 ///
530 /// The SMS algorithm allows negative values for cycles, so the first cycle
531 /// in the schedule is the smallest cycle value.
532 class SMSchedule {
533 private:
534  /// Map from execution cycle to instructions.
535  DenseMap<int, std::deque<SUnit *>> ScheduledInstrs;
536 
537  /// Map from instruction to execution cycle.
538  std::map<SUnit *, int> InstrToCycle;
539 
540  /// Keep track of the first cycle value in the schedule. It starts
541  /// as zero, but the algorithm allows negative values.
542  int FirstCycle = 0;
543 
544  /// Keep track of the last cycle value in the schedule.
545  int LastCycle = 0;
546 
547  /// The initiation interval (II) for the schedule.
548  int InitiationInterval = 0;
549 
550  /// Target machine information.
551  const TargetSubtargetInfo &ST;
552 
553  /// Virtual register information.
554  MachineRegisterInfo &MRI;
555 
556  ResourceManager ProcItinResources;
557 
558 public:
560  : ST(mf->getSubtarget()), MRI(mf->getRegInfo()),
561  ProcItinResources(&ST, DAG) {}
562 
563  void reset() {
564  ScheduledInstrs.clear();
565  InstrToCycle.clear();
566  FirstCycle = 0;
567  LastCycle = 0;
568  InitiationInterval = 0;
569  }
570 
571  /// Set the initiation interval for this schedule.
572  void setInitiationInterval(int ii) {
573  InitiationInterval = ii;
574  ProcItinResources.init(ii);
575  }
576 
577  /// Return the initiation interval for this schedule.
578  int getInitiationInterval() const { return InitiationInterval; }
579 
580  /// Return the first cycle in the completed schedule. This
581  /// can be a negative value.
582  int getFirstCycle() const { return FirstCycle; }
583 
584  /// Return the last cycle in the finalized schedule.
585  int getFinalCycle() const { return FirstCycle + InitiationInterval - 1; }
586 
587  /// Return the cycle of the earliest scheduled instruction in the dependence
588  /// chain.
589  int earliestCycleInChain(const SDep &Dep);
590 
591  /// Return the cycle of the latest scheduled instruction in the dependence
592  /// chain.
593  int latestCycleInChain(const SDep &Dep);
594 
595  void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart,
596  int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG);
597  bool insert(SUnit *SU, int StartCycle, int EndCycle, int II);
598 
599  /// Iterators for the cycle to instruction map.
601  using const_sched_iterator =
603 
604  /// Return true if the instruction is scheduled at the specified stage.
605  bool isScheduledAtStage(SUnit *SU, unsigned StageNum) {
606  return (stageScheduled(SU) == (int)StageNum);
607  }
608 
609  /// Return the stage for a scheduled instruction. Return -1 if
610  /// the instruction has not been scheduled.
611  int stageScheduled(SUnit *SU) const {
612  std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);
613  if (it == InstrToCycle.end())
614  return -1;
615  return (it->second - FirstCycle) / InitiationInterval;
616  }
617 
618  /// Return the cycle for a scheduled instruction. This function normalizes
619  /// the first cycle to be 0.
620  unsigned cycleScheduled(SUnit *SU) const {
621  std::map<SUnit *, int>::const_iterator it = InstrToCycle.find(SU);
622  assert(it != InstrToCycle.end() && "Instruction hasn't been scheduled.");
623  return (it->second - FirstCycle) % InitiationInterval;
624  }
625 
626  /// Return the maximum stage count needed for this schedule.
627  unsigned getMaxStageCount() {
628  return (LastCycle - FirstCycle) / InitiationInterval;
629  }
630 
631  /// Return the instructions that are scheduled at the specified cycle.
632  std::deque<SUnit *> &getInstructions(int cycle) {
633  return ScheduledInstrs[cycle];
634  }
635 
639 
640  bool
645  void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
646  std::deque<SUnit *> &Insts);
649  MachineOperand &MO);
650  void print(raw_ostream &os) const;
651  void dump() const;
652 };
653 
654 } // end namespace llvm
655 
656 #endif // LLVM_CODEGEN_MACHINEPIPELINER_H
i
i
Definition: README.txt:29
llvm::SwingSchedulerDAG
This class builds the dependence graph for the instructions in a loop, and attempts to schedule the i...
Definition: MachinePipeliner.h:113
const_iterator
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Definition: IRTranslator.cpp:108
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#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
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Definition: README-SSE.txt:81
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Definition: MachinePipeliner.h:84
llvm::SwingSchedulerDAG::getHeight
unsigned getHeight(SUnit *Node)
The height, in the dependence graph, for a node.
Definition: MachinePipeliner.h:239
llvm::SwingSchedulerDAG::finishBlock
void finishBlock() override
Clean up after the software pipeliner runs.
Definition: MachinePipeliner.cpp:671
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void print(raw_ostream &os) const
Definition: MachinePipeliner.cpp:2952
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Definition: MachinePipeliner.h:432
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A command line argument to force pipeliner to use specified issue width.
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@ Latency
Definition: SIMachineScheduler.h:34
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Definition: MachinePipeliner.h:67
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MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::ResourceManager::init
void init(int II)
Initialize resources with the initiation interval II.
Definition: MachinePipeliner.cpp:3274
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::SwingSchedulerDAG::SwingSchedulerDAG
SwingSchedulerDAG(MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis, const RegisterClassInfo &rci, unsigned II, TargetInstrInfo::PipelinerLoopInfo *PLI)
Definition: MachinePipeliner.h:202
ScheduleDAGInstrs.h
llvm::SetVector::size
size_type size() const
Determine the number of elements in the SetVector.
Definition: SetVector.h:77
llvm::NodeSet::compareRecMII
int compareRecMII(NodeSet &RHS)
Definition: MachinePipeliner.h:381
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::NodeSet::iterator
SetVector< SUnit * >::const_iterator iterator
Definition: MachinePipeliner.h:332
llvm::SMSchedule::normalizeNonPipelinedInstructions
bool normalizeNonPipelinedInstructions(SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
Definition: MachinePipeliner.cpp:2695
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineOptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: MachineOptimizationRemarkEmitter.h:151
llvm::SDep::Anti
@ Anti
A register anti-dependence (aka WAR).
Definition: ScheduleDAG.h:54
llvm::SwingSchedulerDAG::schedule
void schedule() override
We override the schedule function in ScheduleDAGInstrs to implement the scheduling part of the Swing ...
Definition: MachinePipeliner.cpp:492
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
RegisterClassInfo.h
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1793
llvm::SetVector::const_iterator
typename vector_type::const_iterator const_iterator
Definition: SetVector.h:49
llvm::DenseMapIterator
Definition: DenseMap.h:57
TargetInstrInfo.h
llvm::SwingSchedulerDAG::isLoopCarriedDep
bool isLoopCarriedDep(SUnit *Source, const SDep &Dep, bool isSucc=true)
Return true for an order or output dependence that is loop carried potentially.
Definition: MachinePipeliner.cpp:2235
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:136
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::count
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
Definition: DenseMap.h:145
llvm::SmallPtrSet
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:450
llvm::SwingSchedulerDAG::getZeroLatencyHeight
int getZeroLatencyHeight(SUnit *Node)
The maximum unweighted length of a path from the given node to an arbitrary node in which each edge h...
Definition: MachinePipeliner.h:243
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::NodeSet::empty
bool empty() const
Definition: MachinePipeliner.h:369
llvm::SMSchedule::insert
bool insert(SUnit *SU, int StartCycle, int EndCycle, int II)
Try to schedule the node at the specified StartCycle and continue until the node is schedule or the E...
Definition: MachinePipeliner.cpp:2329
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MachinePipeliner::LoopInfo::BrCond
SmallVector< MachineOperand, 4 > BrCond
Definition: MachinePipeliner.h:85
llvm::SetVector::remove_if
bool remove_if(UnaryPredicate P)
Remove items from the set vector based on a predicate function.
Definition: SetVector.h:199
llvm::MachineLoopInfo
Definition: MachineLoopInfo.h:89
llvm::SwpEnableCopyToPhi
cl::opt< bool > SwpEnableCopyToPhi
llvm::MachinePipeliner::LI
LoopInfo LI
Definition: MachinePipeliner.h:91
llvm::ScheduleDAGTopologicalSort
This class can compute a topological ordering for SUnits and provides methods for dynamically updatin...
Definition: ScheduleDAG.h:693
llvm::TargetInstrInfo::PipelinerLoopInfo
Object returned by analyzeLoopForPipelining.
Definition: TargetInstrInfo.h:731
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::cl::apply
void apply(Opt *O, const Mod &M, const Mods &... Ms)
Definition: CommandLine.h:1300
llvm::SetVector::begin
iterator begin()
Get an iterator to the beginning of the SetVector.
Definition: SetVector.h:82
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::SMSchedule::dump
void dump() const
Utility function used for debugging to print the schedule.
Definition: MachinePipeliner.cpp:2977
llvm::AAResults
Definition: AliasAnalysis.h:294
llvm::SwingSchedulerDAG::getDistance
unsigned getDistance(SUnit *U, SUnit *V, const SDep &Dep)
The distance function, which indicates that operation V of iteration I depends on operations U of ite...
Definition: MachinePipeliner.h:260
llvm::SwingSchedulerDAG::isBackedge
bool isBackedge(SUnit *Source, const SDep &Dep)
Return true if the dependence is a back-edge in the data dependence graph.
Definition: MachinePipeliner.h:250
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::SwingSchedulerDAG::getMOV
int getMOV(SUnit *Node)
The mobility function, which the number of slots in which an instruction may be scheduled.
Definition: MachinePipeliner.h:227
llvm::MCSchedClassDesc
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:109
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::SMSchedule::getFinalCycle
int getFinalCycle() const
Return the last cycle in the finalized schedule.
Definition: MachinePipeliner.h:585
llvm::SMSchedule::getFirstCycle
int getFirstCycle() const
Return the first cycle in the completed schedule.
Definition: MachinePipeliner.h:582
false
Definition: StackSlotColoring.cpp:141
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::GenericCycle
A possibly irreducible generalization of a Loop.
Definition: GenericCycleInfo.h:48
llvm::SMSchedule::setInitiationInterval
void setInitiationInterval(int ii)
Set the initiation interval for this schedule.
Definition: MachinePipeliner.h:572
llvm::SMSchedule::isValidSchedule
bool isValidSchedule(SwingSchedulerDAG *SSD)
Definition: MachinePipeliner.cpp:2737
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
llvm::SMSchedule::orderDependence
void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU, std::deque< SUnit * > &Insts)
Order the instructions within a cycle so that the definitions occur before the uses.
Definition: MachinePipeliner.cpp:2489
llvm::SMSchedule::reset
void reset()
Definition: MachinePipeliner.h:563
llvm::BitVector
Definition: BitVector.h:75
llvm::initializeMachinePipelinerPass
void initializeMachinePipelinerPass(PassRegistry &)
c
the resulting code requires compare and branches when and if the revised code is with conditional branches instead of More there is a byte word extend before each where there should be only and the condition codes are not remembered when the same two values are compared twice More LSR enhancements i8 and i32 load store addressing modes are identical int int c
Definition: README.txt:418
llvm::NodeSet
A NodeSet contains a set of SUnit DAG nodes with additional information that assigns a priority to th...
Definition: MachinePipeliner.h:321
llvm::SetVector::empty
bool empty() const
Determine if the SetVector is empty or not.
Definition: SetVector.h:72
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::NodeSet::setColocate
void setColocate(unsigned c)
Definition: MachinePipeliner.h:375
llvm::SMSchedule::isLoopCarried
bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi)
Return true if the scheduled Phi has a loop carried operand.
Definition: MachinePipeliner.cpp:2617
llvm::NodeSet::operator!=
bool operator!=(const NodeSet &RHS) const
Definition: MachinePipeliner.h:429
llvm::NodeSet::setExceedPressure
void setExceedPressure(SUnit *SU)
Definition: MachinePipeliner.h:377
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachinePipeliner
The main class in the implementation of the target independent software pipeliner pass.
Definition: MachinePipeliner.h:65
MachineOptimizationRemarkEmitter.h
===- MachineOptimizationRemarkEmitter.h - Opt Diagnostics -*- C++ -*-—===//
llvm::NodeSet::begin
iterator begin()
Definition: MachinePipeliner.h:431
llvm::SMSchedule::computeStart
void computeStart(SUnit *SU, int *MaxEarlyStart, int *MinLateStart, int *MinEnd, int *MaxStart, int II, SwingSchedulerDAG *DAG)
Compute the scheduling start slot for the instruction.
Definition: MachinePipeliner.cpp:2428
llvm::SwingSchedulerDAG::classof
static bool classof(const ScheduleDAGInstrs *DAG)
Definition: MachinePipeliner.h:286
llvm::DefaultProcResSize
static const int DefaultProcResSize
Definition: MachinePipeliner.h:442
llvm::MachineLoop
Definition: MachineLoopInfo.h:44
llvm::MachinePipeliner::LoopInfo::LoopPipelinerInfo
std::unique_ptr< TargetInstrInfo::PipelinerLoopInfo > LoopPipelinerInfo
Definition: MachinePipeliner.h:88
llvm::MachinePipeliner::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachinePipeliner.cpp:462
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::clear
void clear()
Definition: DenseMap.h:110
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::SMSchedule::getInitiationInterval
int getInitiationInterval() const
Return the initiation interval for this schedule.
Definition: MachinePipeliner.h:578
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::NodeSet::getRecMII
int getRecMII()
Definition: MachinePipeliner.h:383
llvm::DenseMap< unsigned, unsigned >
llvm::NodeSet::getMaxDepth
unsigned getMaxDepth()
Definition: MachinePipeliner.h:395
llvm::MachinePipeliner::ORE
MachineOptimizationRemarkEmitter * ORE
Definition: MachinePipeliner.h:68
llvm::MachinePipeliner::InstrItins
const InstrItineraryData * InstrItins
Definition: MachinePipeliner.h:71
llvm::SUnit::getInstr
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
Definition: ScheduleDAG.h:373
llvm::SwingSchedulerDAG::getALAP
int getALAP(SUnit *Node)
Return the latest time an instruction my be scheduled.
Definition: MachinePipeliner.h:223
llvm::NodeSet::size
unsigned size() const
Definition: MachinePipeliner.h:367
llvm::SMSchedule::SMSchedule
SMSchedule(MachineFunction *mf, SwingSchedulerDAG *DAG)
Definition: MachinePipeliner.h:559
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::find
iterator find(const_arg_type_t< KeyT > Val)
Definition: DenseMap.h:150
llvm::MachinePipeliner::LoopInfo::LoopCompare
MachineInstr * LoopCompare
Definition: MachinePipeliner.h:87
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachinePipeliner::MachinePipeliner
MachinePipeliner()
Definition: MachinePipeliner.h:95
llvm::MachinePipeliner::LoopInfo::LoopInductionVar
MachineInstr * LoopInductionVar
Definition: MachinePipeliner.h:86
llvm::RegisterClassInfo
Definition: RegisterClassInfo.h:29
llvm::SMSchedule::isLoopCarriedDefOfUse
bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def, MachineOperand &MO)
Return true if the instruction is a definition that is loop carried and defines the use on the next i...
Definition: MachinePipeliner.cpp:2645
llvm::NodeSet::setRecMII
void setRecMII(unsigned mii)
Definition: MachinePipeliner.h:373
llvm::MachineInstr::isPHI
bool isPHI() const
Definition: MachineInstr.h:1300
llvm::SMSchedule::getInstructions
std::deque< SUnit * > & getInstructions(int cycle)
Return the instructions that are scheduled at the specified cycle.
Definition: MachinePipeliner.h:632
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
ScheduleDAGMutation.h
llvm::SwingSchedulerDAG::getZeroLatencyDepth
int getZeroLatencyDepth(SUnit *Node)
The maximum unweighted length of a path from an arbitrary node to the given node in which each edge h...
Definition: MachinePipeliner.h:234
llvm::Sched::Source
@ Source
Definition: TargetLowering.h:99
llvm::SDep::getSUnit
SUnit * getSUnit() const
Definition: ScheduleDAG.h:480
llvm::NodeSet::operator==
bool operator==(const NodeSet &RHS) const
Definition: MachinePipeliner.h:424
llvm::MachinePipeliner::RegClassInfo
RegisterClassInfo RegClassInfo
Definition: MachinePipeliner.h:73
llvm::ResourceManager::calculateResMII
int calculateResMII() const
Definition: MachinePipeliner.cpp:3199
llvm::MachinePipeliner::ID
static char ID
Definition: MachinePipeliner.h:93
llvm::ScheduleDAG::MF
MachineFunction & MF
Machine function.
Definition: ScheduleDAG.h:559
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
Mutation
PowerPC VSX FMA Mutation
Definition: PPCVSXFMAMutate.cpp:387
llvm::NodeSet::hasRecurrence
bool hasRecurrence()
Definition: MachinePipeliner.h:365
Node
Definition: ItaniumDemangle.h:156
llvm::SMSchedule::isScheduledAtStage
bool isScheduledAtStage(SUnit *SU, unsigned StageNum)
Return true if the instruction is scheduled at the specified stage.
Definition: MachinePipeliner.h:605
llvm::NodeSet::count
unsigned count(SUnit *SU) const
Definition: MachinePipeliner.h:363
llvm::SMSchedule::finalizeSchedule
void finalizeSchedule(SwingSchedulerDAG *SSD)
After the schedule has been formed, call this function to combine the instructions from the different...
Definition: MachinePipeliner.cpp:2907
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::SDep
Scheduling dependency.
Definition: ScheduleDAG.h:49
llvm::SetVector::clear
void clear()
Completely clear the SetVector.
Definition: SetVector.h:220
llvm::ScheduleDAGInstrs::MLI
const MachineLoopInfo * MLI
Definition: ScheduleDAGInstrs.h:122
llvm::NodeSet::remove_if
bool remove_if(UnaryPredicate P)
Definition: MachinePipeliner.h:359
llvm::ScheduleDAG::SUnits
std::vector< SUnit > SUnits
The scheduling units.
Definition: ScheduleDAG.h:561
llvm::ResourceManager::initProcResourceVectors
void initProcResourceVectors(const MCSchedModel &SM, SmallVectorImpl< uint64_t > &Masks)
Definition: MachinePipeliner.cpp:3002
llvm::SwingSchedulerDAG::getDepth
unsigned getDepth(SUnit *Node)
The depth, in the dependence graph, for a node.
Definition: MachinePipeliner.h:230
llvm::DenseMapBase< DenseMap< KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >, KeyT, ValueT, DenseMapInfo< KeyT >, llvm::detail::DenseMapPair< KeyT, ValueT > >::end
iterator end()
Definition: DenseMap.h:84
llvm::NodeSet::clear
void clear()
Definition: MachinePipeliner.h:397
llvm::MachinePipeliner::TII
const TargetInstrInfo * TII
Definition: MachinePipeliner.h:72
llvm::ResourceManager::ResourceManager
ResourceManager(const TargetSubtargetInfo *ST, SwingSchedulerDAG *DAG)
Definition: MachinePipeliner.h:494
llvm::SMSchedule::computeUnpipelineableNodes
SmallSet< SUnit *, 8 > computeUnpipelineableNodes(SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI)
Determine transitive dependences of unpipelineable instructions.
Definition: MachinePipeliner.cpp:2668
llvm::SwingSchedulerDAG::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Definition: MachinePipeliner.h:282
llvm::SetVector::count
size_type count(const key_type &key) const
Count the number of elements of a given key in the SetVector.
Definition: SetVector.h:215
llvm::NodeSet::computeNodeSetInfo
void computeNodeSetInfo(SwingSchedulerDAG *SSD)
Summarize node functions for the entire node set.
Definition: MachinePipeliner.h:386
llvm::MCSchedModel
Machine model for scheduling, bundling, and heuristics.
Definition: MCSchedule.h:244
llvm::LiveIntervals
Definition: LiveIntervals.h:53
llvm::SMSchedule::print
void print(raw_ostream &os) const
Print the schedule information to the given output.
Definition: MachinePipeliner.cpp:2962
llvm::SwingSchedulerDAG::applyInstrChange
void applyInstrChange(MachineInstr *MI, SMSchedule &Schedule)
Apply changes to the instruction if needed.
Definition: MachinePipeliner.cpp:2180
llvm::BitVector::reset
BitVector & reset()
Definition: BitVector.h:385
llvm::SDep::getKind
Kind getKind() const
Returns an enum value representing the kind of the dependence.
Definition: ScheduleDAG.h:486
llvm::NodeSet::isExceedSU
bool isExceedSU(SUnit *SU)
Definition: MachinePipeliner.h:379
llvm::MachinePipeliner::disabledByPragma
bool disabledByPragma
Definition: MachinePipeliner.h:74
llvm::SMSchedule::earliestCycleInChain
int earliestCycleInChain(const SDep &Dep)
Return the cycle of the earliest scheduled instruction in the dependence chain.
Definition: MachinePipeliner.cpp:2369
llvm::SetVector::end
iterator end()
Get an iterator to the end of the SetVector.
Definition: SetVector.h:92
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::MachinePipeliner::LoopInfo
Cache the target analysis information about the loop.
Definition: MachinePipeliner.h:82
llvm::MachinePipeliner::NumTries
static int NumTries
Definition: MachinePipeliner.h:78
llvm::rdf::NodeSet
std::set< NodeId > NodeSet
Definition: RDFGraph.h:514
llvm::ResourceManager::canReserveResources
bool canReserveResources(SUnit &SU, int Cycle)
Check if the resources occupied by a machine instruction are available in the current state.
Definition: MachinePipeliner.cpp:3044
llvm::MachinePipeliner::LoopInfo::TBB
MachineBasicBlock * TBB
Definition: MachinePipeliner.h:83
llvm::NodeSet::getNode
SUnit * getNode(unsigned i) const
Definition: MachinePipeliner.h:371
llvm::MachinePipeliner::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &MF) override
The "main" function for implementing Swing Modulo Scheduling.
Definition: MachinePipeliner.cpp:210
llvm::ScheduleDAGMutation
Mutate the DAG as a postpass after normal DAG building.
Definition: ScheduleDAGMutation.h:22
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
llvm::NodeSet::insert
bool insert(SUnit *SU)
Definition: MachinePipeliner.h:355
llvm::NodeSet::insert
void insert(iterator S, iterator E)
Definition: MachinePipeliner.h:357
llvm::SUnit
Scheduling unit. This is a node in the scheduling DAG.
Definition: ScheduleDAG.h:242
llvm::MachinePipeliner::II_setByPragma
unsigned II_setByPragma
Definition: MachinePipeliner.h:75
llvm::SMSchedule::getMaxStageCount
unsigned getMaxStageCount()
Return the maximum stage count needed for this schedule.
Definition: MachinePipeliner.h:627
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:120
llvm::NodeSet::getLatency
unsigned getLatency()
Definition: MachinePipeliner.h:393
llvm::NodeSet::NodeSet
NodeSet()=default
llvm::SMSchedule::cycleScheduled
unsigned cycleScheduled(SUnit *SU) const
Return the cycle for a scheduled instruction.
Definition: MachinePipeliner.h:620
llvm::SMSchedule::latestCycleInChain
int latestCycleInChain(const SDep &Dep)
Return the cycle of the latest scheduled instruction in the dependence chain.
Definition: MachinePipeliner.cpp:2392
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:51
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
llvm::MachinePipeliner::MLI
const MachineLoopInfo * MLI
Definition: MachinePipeliner.h:69
llvm::SwingSchedulerDAG::fixupRegisterOverlaps
void fixupRegisterOverlaps(std::deque< SUnit * > &Instrs)
Attempt to fix the degenerate cases when the instruction serialization causes the register lifetimes ...
Definition: MachinePipeliner.cpp:2858
llvm::NodeSet::operator>
bool operator>(const NodeSet &RHS) const
Sort the node sets by importance.
Definition: MachinePipeliner.h:413
llvm::MCSubtargetInfo
Generic base class for all target subtargets.
Definition: MCSubtargetInfo.h:76
InitializePasses.h
llvm::ResourceManager
Definition: MachinePipeliner.h:444
llvm::SwingSchedulerDAG::getASAP
int getASAP(SUnit *Node)
Return the earliest time an instruction may be scheduled.
Definition: MachinePipeliner.h:220
llvm::NodeSet::NodeSet
NodeSet(iterator S, iterator E)
Definition: MachinePipeliner.h:335
llvm::ScheduleDAG::ExitSU
SUnit ExitSU
Special node for the region exit.
Definition: ScheduleDAG.h:563
llvm::InstrItineraryData
Itinerary data supplied by a subtarget to be used by a target.
Definition: MCInstrItineraries.h:109
llvm::SDep::getLatency
unsigned getLatency() const
Returns the latency value for this edge, which roughly means the minimum number of cycles that must e...
Definition: ScheduleDAG.h:142
llvm::SwingSchedulerDAG::hasNewSchedule
bool hasNewSchedule()
Return true if the loop kernel has been scheduled.
Definition: MachinePipeliner.h:217
llvm::SMSchedule::stageScheduled
int stageScheduled(SUnit *SU) const
Return the stage for a scheduled instruction.
Definition: MachinePipeliner.h:611
SetVector.h
llvm::SMSchedule
This class represents the scheduled code.
Definition: MachinePipeliner.h:532
MachineDominators.h
llvm::SwingSchedulerDAG::getInstrBaseReg
unsigned getInstrBaseReg(SUnit *SU)
Return the new base register that was stored away for the changed instruction.
Definition: MachinePipeliner.h:274
llvm::MachinePipeliner::MDT
const MachineDominatorTree * MDT
Definition: MachinePipeliner.h:70