This class builds the dependence graph for the instructions in a loop, and attempts to schedule the instructions using the SMS algorithm. More...

#include "llvm/CodeGen/MachinePipeliner.h"

Inheritance diagram for llvm::SwingSchedulerDAG:

[legend]

Public Member Functions
	SwingSchedulerDAG (MachinePipeliner &P, MachineLoop &L, LiveIntervals &lis, const RegisterClassInfo &rci, unsigned II, TargetInstrInfo::PipelinerLoopInfo PLI, AliasAnalysis AA)
void	schedule () override
	We override the schedule function in ScheduleDAGInstrs to implement the scheduling part of the Swing Modulo Scheduling algorithm.
void	finishBlock () override
	Clean up after the software pipeliner runs.
bool	hasNewSchedule ()
	Return true if the loop kernel has been scheduled.
int	getASAP (SUnit *Node)
	Return the earliest time an instruction may be scheduled.
int	getALAP (SUnit *Node)
	Return the latest time an instruction my be scheduled.
int	getMOV (SUnit *Node)
	The mobility function, which the number of slots in which an instruction may be scheduled.
unsigned	getDepth (SUnit *Node)
	The depth, in the dependence graph, for a node.
int	getZeroLatencyDepth (SUnit *Node)
	The maximum unweighted length of a path from an arbitrary node to the given node in which each edge has latency 0.
unsigned	getHeight (SUnit *Node)
	The height, in the dependence graph, for a node.
int	getZeroLatencyHeight (SUnit *Node)
	The maximum unweighted length of a path from the given node to an arbitrary node in which each edge has latency 0.
bool	isLoopCarriedDep (const SwingSchedulerDDGEdge &Edge) const
	Return true for an order or output dependence that is loop carried potentially.
void	applyInstrChange (MachineInstr *MI, SMSchedule &Schedule)
	Apply changes to the instruction if needed.
void	fixupRegisterOverlaps (std::deque< SUnit * > &Instrs)
	Attempt to fix the degenerate cases when the instruction serialization causes the register lifetimes to overlap.
Register	getInstrBaseReg (SUnit *SU) const
	Return the new base register that was stored away for the changed instruction.
void	addMutation (std::unique_ptr< ScheduleDAGMutation > Mutation)
const SwingSchedulerDDG *	getDDG () const
bool	mayOverlapInLaterIter (const MachineInstr BaseMI, const MachineInstr OtherMI) const
	Return false if there is no overlap between the region accessed by BaseMI in an iteration and the region accessed by OtherMI in subsequent iterations.
Public Member Functions inherited from llvm::ScheduleDAGInstrs
void	setDumpDirection (DumpDirection D)
	ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo *mli, bool RemoveKillFlags=false)
	~ScheduleDAGInstrs () override=default
const TargetSchedModel *	getSchedModel () const
	Gets the machine model for instruction scheduling.
const MCSchedClassDesc *	getSchedClass (SUnit *SU) const
	Resolves and cache a resolved scheduling class for an SUnit.
bool	IsReachable (SUnit SU, SUnit TargetSU)
	IsReachable - Checks if SU is reachable from TargetSU.
bool	shouldScheduleSingleMIRegions () const
	Whether regions with a single MI should be scheduled.
MachineBasicBlock::iterator	begin () const
	Returns an iterator to the top of the current scheduling region.
MachineBasicBlock::iterator	end () const
	Returns an iterator to the bottom of the current scheduling region.
SUnit *	newSUnit (MachineInstr *MI)
	Creates a new SUnit and return a ptr to it.
SUnit *	getSUnit (MachineInstr *MI) const
	Returns an existing SUnit for this MI, or nullptr.
virtual bool	doMBBSchedRegionsTopDown () const
	If this method returns true, handling of the scheduling regions themselves (in case of a scheduling boundary in MBB) will be done beginning with the topmost region of MBB.
virtual void	startBlock (MachineBasicBlock *BB)
	Prepares to perform scheduling in the given block.
virtual void	enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned regioninstrs)
	Initialize the DAG and common scheduler state for a new scheduling region.
virtual void	exitRegion ()
	Called when the scheduler has finished scheduling the current region.
void	buildSchedGraph (AAResults AA, RegPressureTracker RPTracker=nullptr, PressureDiffs PDiffs=nullptr, LiveIntervals LIS=nullptr, bool TrackLaneMasks=false)
	Builds SUnits for the current region.
void	addSchedBarrierDeps ()
	Adds dependencies from instructions in the current list of instructions being scheduled to scheduling barrier.
virtual void	finalizeSchedule ()
	Allow targets to perform final scheduling actions at the level of the whole MachineFunction.
void	dumpNode (const SUnit &SU) const override
void	dump () const override
std::string	getGraphNodeLabel (const SUnit *SU) const override
	Returns a label for a DAG node that points to an instruction.
std::string	getDAGName () const override
	Returns a label for the region of code covered by the DAG.
void	fixupKills (MachineBasicBlock &MBB)
	Fixes register kill flags that scheduling has made invalid.
bool	canAddEdge (SUnit SuccSU, SUnit PredSU)
	True if an edge can be added from PredSU to SuccSU without creating a cycle.
bool	addEdge (SUnit *SuccSU, const SDep &PredDep)
	Add a DAG edge to the given SU with the given predecessor dependence data.
SmallVector< ClusterInfo > &	getClusters ()
	Returns the array of the clusters.
ClusterInfo *	getCluster (unsigned Idx)
	Get the specific cluster, return nullptr for InvalidClusterId.
Public Member Functions inherited from llvm::ScheduleDAG
	ScheduleDAG (const ScheduleDAG &)=delete
ScheduleDAG &	operator= (const ScheduleDAG &)=delete
	ScheduleDAG (MachineFunction &mf)
virtual	~ScheduleDAG ()
void	clearDAG ()
	Clears the DAG state (between regions).
const MCInstrDesc *	getInstrDesc (const SUnit *SU) const
	Returns the MCInstrDesc of this SUnit.
virtual void	viewGraph (const Twine &Name, const Twine &Title)
	Pops up a GraphViz/gv window with the ScheduleDAG rendered using 'dot'.
virtual void	viewGraph ()
	Out-of-line implementation with no arguments is handy for gdb.
void	dumpNodeName (const SUnit &SU) const
virtual void	addCustomGraphFeatures (GraphWriter< ScheduleDAG * > &) const
	Adds custom features for a visualization of the ScheduleDAG.
unsigned	VerifyScheduledDAG (bool isBottomUp)
	Verifies that all SUnits were scheduled and that their state is consistent.

Static Public Member Functions
static bool	classof (const ScheduleDAGInstrs *DAG)

Additional Inherited Members
Public Types inherited from llvm::ScheduleDAGInstrs
enum	DumpDirection { TopDown , BottomUp , Bidirectional , NotSet }
	The direction that should be used to dump the scheduled Sequence. More...
using	SUList = std::list<SUnit *>
	A list of SUnits, used in Value2SUsMap, during DAG construction.
Public Attributes inherited from llvm::ScheduleDAG
const TargetMachine &	TM
	Target processor.
const TargetInstrInfo *	TII
	Target instruction information.
const TargetRegisterInfo *	TRI
	Target processor register info.
MachineFunction &	MF
	Machine function.
MachineRegisterInfo &	MRI
	Virtual/real register map.
std::vector< SUnit >	SUnits
	The scheduling units.
SUnit	EntrySU
	Special node for the region entry.
SUnit	ExitSU
	Special node for the region exit.
bool	StressSched
Protected Types inherited from llvm::ScheduleDAGInstrs
using	DbgValueVector
Protected Member Functions inherited from llvm::ScheduleDAGInstrs
BatchAAResults *	getAAForDep () const
	Returns a (possibly null) pointer to the current BatchAAResults.
void	reduceHugeMemNodeMaps (Value2SUsMap &stores, Value2SUsMap &loads, unsigned N)
	Reduces maps in FIFO order, by N SUs.
void	addChainDependency (SUnit SUa, SUnit SUb, unsigned Latency=0)
	Adds a chain edge between SUa and SUb, but only if both AAResults and Target fail to deny the dependency.
void	addChainDependencies (SUnit *SU, SUList &SUs, unsigned Latency)
	Adds dependencies as needed from all SUs in list to SU.
void	addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap)
	Adds dependencies as needed from all SUs in map, to SU.
void	addChainDependencies (SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V)
	Adds dependencies as needed to SU, from all SUs mapped to V.
void	addBarrierChain (Value2SUsMap &map)
	Adds barrier chain edges from all SUs in map, and then clear the map.
void	insertBarrierChain (Value2SUsMap &map)
	Inserts a barrier chain in a huge region, far below current SU.
void	initSUnits ()
	Creates an SUnit for each real instruction, numbered in top-down topological order.
void	addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
	MO is an operand of SU's instruction that defines a physical register.
void	addPhysRegDeps (SUnit *SU, unsigned OperIdx)
	Adds register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx.
void	addVRegDefDeps (SUnit *SU, unsigned OperIdx)
	Adds register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx.
void	addVRegUseDeps (SUnit *SU, unsigned OperIdx)
	Adds a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit.
LaneBitmask	getLaneMaskForMO (const MachineOperand &MO) const
	Returns a mask for which lanes get read/written by the given (register) machine operand.
bool	deadDefHasNoUse (const MachineOperand &MO)
	Returns true if the def register in `MO` has no uses.
Protected Member Functions inherited from llvm::ScheduleDAG
void	dumpNodeAll (const SUnit &SU) const
Protected Attributes inherited from llvm::ScheduleDAGInstrs
const MachineLoopInfo *	MLI = nullptr
const MachineFrameInfo &	MFI
TargetSchedModel	SchedModel
	TargetSchedModel provides an interface to the machine model.
bool	RemoveKillFlags
	True if the DAG builder should remove kill flags (in preparation for rescheduling).
bool	ScheduleSingleMIRegions = false
	True if regions with a single MI should be scheduled.
bool	CanHandleTerminators = false
	The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering.
bool	TrackLaneMasks = false
	Whether lane masks should get tracked.
MachineBasicBlock *	BB = nullptr
	The block in which to insert instructions.
MachineBasicBlock::iterator	RegionBegin
	The beginning of the range to be scheduled.
MachineBasicBlock::iterator	RegionEnd
	The end of the range to be scheduled.
unsigned	NumRegionInstrs = 0
	Instructions in this region (distance(RegionBegin, RegionEnd)).
DenseMap< MachineInstr , SUnit >	MISUnitMap
	After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.
RegUnit2SUnitsMap	Defs
	Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions.
RegUnit2SUnitsMap	Uses
VReg2SUnitMultiMap	CurrentVRegDefs
	Tracks the last instruction(s) in this region defining each virtual register.
VReg2SUnitOperIdxMultiMap	CurrentVRegUses
	Tracks the last instructions in this region using each virtual register.
std::optional< BatchAAResults >	AAForDep
SUnit *	BarrierChain = nullptr
	Remember a generic side-effecting instruction as we proceed.
SmallVector< ClusterInfo >	Clusters
DumpDirection	DumpDir = NotSet
UndefValue *	UnknownValue
	For an unanalyzable memory access, this Value is used in maps.
ScheduleDAGTopologicalSort	Topo
	Topo - A topological ordering for SUnits which permits fast IsReachable and similar queries.
DbgValueVector	DbgValues
	Remember instruction that precedes DBG_VALUE.
MachineInstr *	FirstDbgValue = nullptr
LiveRegUnits	LiveRegs
	Set of live physical registers for updating kill flags.

Detailed Description

This class builds the dependence graph for the instructions in a loop, and attempts to schedule the instructions using the SMS algorithm.

Definition at line 274 of file MachinePipeliner.h.

Constructor & Destructor Documentation

◆ SwingSchedulerDAG()

llvm::SwingSchedulerDAG::SwingSchedulerDAG	(	MachinePipeliner &	P,
		MachineLoop &	L,
		LiveIntervals &	lis,
		const RegisterClassInfo &	rci,
		unsigned	II,
		TargetInstrInfo::PipelinerLoopInfo *	PLI,
		AliasAnalysis *	AA )

inline

Definition at line 375 of file MachinePipeliner.h.

References llvm::ScheduleDAG::ExitSU, II, llvm::ScheduleDAG::MF, llvm::ScheduleDAGInstrs::MLI, P, llvm::ScheduleDAGInstrs::ScheduleDAGInstrs(), llvm::ScheduleDAG::SUnits, and llvm::SwpEnableCopyToPhi.

Member Function Documentation

◆ addMutation()

void llvm::SwingSchedulerDAG::addMutation ( std::unique_ptr< ScheduleDAGMutation > Mutation )

inline

Definition at line 437 of file MachinePipeliner.h.

References Mutation.

◆ applyInstrChange()

void SwingSchedulerDAG::applyInstrChange	(	MachineInstr *	MI,
		SMSchedule &	Schedule )

Apply changes to the instruction if needed.

The changes are need to improve the scheduling and depend up on the final schedule.

Definition at line 2937 of file MachinePipeliner.cpp.

References llvm::SMSchedule::cycleScheduled(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::MachineInstr::getOperand(), llvm::ScheduleDAGInstrs::getSUnit(), llvm::ScheduleDAG::MF, MI, llvm::ScheduleDAGInstrs::MISUnitMap, llvm::MachineOperand::setImm(), llvm::SUnit::setInstr(), llvm::MachineOperand::setReg(), llvm::SMSchedule::stageScheduled(), and llvm::ScheduleDAG::TII.

Referenced by llvm::SMSchedule::finalizeSchedule().

◆ classof()

bool llvm::SwingSchedulerDAG::classof ( const ScheduleDAGInstrs * DAG )

inlinestatic

Definition at line 441 of file MachinePipeliner.h.

References llvm::ScheduleDAGInstrs::ScheduleDAGInstrs().

◆ finishBlock()

void SwingSchedulerDAG::finishBlock ( )

overridevirtual

Clean up after the software pipeliner runs.

Reimplemented from llvm::ScheduleDAGInstrs.

Definition at line 870 of file MachinePipeliner.cpp.

References llvm::ScheduleDAGInstrs::finishBlock(), and llvm::ScheduleDAG::MF.

◆ fixupRegisterOverlaps()

void SwingSchedulerDAG::fixupRegisterOverlaps ( std::deque< SUnit * > & Instrs )

Attempt to fix the degenerate cases when the instruction serialization causes the register lifetimes to overlap.

For example, p' = store_pi(p, b) = load p, offset In this case p and p' overlap, which means that two registers are needed. Instead, this function changes the load to use p' and updates the offset.

Definition at line 3697 of file MachinePipeliner.cpp.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUse(), llvm::ScheduleDAG::MF, MI, llvm::ScheduleDAGInstrs::MISUnitMap, Register, llvm::MachineOperand::setImm(), llvm::SUnit::setInstr(), llvm::MachineOperand::setReg(), and llvm::ScheduleDAG::TII.

Referenced by llvm::SMSchedule::finalizeSchedule().

◆ getALAP()

int llvm::SwingSchedulerDAG::getALAP ( SUnit * Node )

inline

Return the latest time an instruction my be scheduled.

Definition at line 397 of file MachinePipeliner.h.

Referenced by getMOV().

◆ getASAP()

int llvm::SwingSchedulerDAG::getASAP ( SUnit * Node )

inline

Return the earliest time an instruction may be scheduled.

Definition at line 394 of file MachinePipeliner.h.

Referenced by getMOV().

◆ getDDG()

const SwingSchedulerDDG * llvm::SwingSchedulerDAG::getDDG ( ) const

inline

Definition at line 443 of file MachinePipeliner.h.

Referenced by llvm::SMSchedule::computeStart(), llvm::SMSchedule::computeUnpipelineableNodes(), llvm::SMSchedule::isValidSchedule(), llvm::NodeSet::NodeSet(), llvm::SMSchedule::normalizeNonPipelinedInstructions(), and llvm::SMSchedule::orderDependence().

◆ getDepth()

unsigned llvm::SwingSchedulerDAG::getDepth ( SUnit * Node )

inline

The depth, in the dependence graph, for a node.

Definition at line 404 of file MachinePipeliner.h.

Referenced by llvm::NodeSet::computeNodeSetInfo().

◆ getHeight()

unsigned llvm::SwingSchedulerDAG::getHeight ( SUnit * Node )

inline

The height, in the dependence graph, for a node.

Definition at line 413 of file MachinePipeliner.h.

◆ getInstrBaseReg()

Register llvm::SwingSchedulerDAG::getInstrBaseReg ( SUnit * SU ) const

inline

Return the new base register that was stored away for the changed instruction.

Definition at line 429 of file MachinePipeliner.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::end(), and Register.

Referenced by llvm::SMSchedule::orderDependence().

◆ getMOV()

int llvm::SwingSchedulerDAG::getMOV ( SUnit * Node )

inline

The mobility function, which the number of slots in which an instruction may be scheduled.

Definition at line 401 of file MachinePipeliner.h.

References getALAP(), and getASAP().

Referenced by llvm::NodeSet::computeNodeSetInfo().

◆ getZeroLatencyDepth()

int llvm::SwingSchedulerDAG::getZeroLatencyDepth ( SUnit * Node )

inline

The maximum unweighted length of a path from an arbitrary node to the given node in which each edge has latency 0.

Definition at line 408 of file MachinePipeliner.h.

◆ getZeroLatencyHeight()

int llvm::SwingSchedulerDAG::getZeroLatencyHeight ( SUnit * Node )

inline

The maximum unweighted length of a path from the given node to an arbitrary node in which each edge has latency 0.

Definition at line 417 of file MachinePipeliner.h.

◆ hasNewSchedule()

bool llvm::SwingSchedulerDAG::hasNewSchedule ( )

inline

Return true if the loop kernel has been scheduled.

Definition at line 391 of file MachinePipeliner.h.

◆ isLoopCarriedDep()

bool SwingSchedulerDAG::isLoopCarriedDep ( const SwingSchedulerDDGEdge & Edge ) const

Return true for an order or output dependence that is loop carried potentially.

A dependence is loop carried if the destination defines a value that may be used or defined by the source in a subsequent iteration.

Definition at line 3086 of file MachinePipeliner.cpp.

References assert(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), llvm::MachineInstr::mayLoadOrStore(), mayOverlapInLaterIter(), llvm::MachineInstr::mayRaiseFPException(), and SwpPruneLoopCarried.

Referenced by llvm::SMSchedule::computeStart().

◆ mayOverlapInLaterIter()

bool SwingSchedulerDAG::mayOverlapInLaterIter	(	const MachineInstr *	BaseMI,
		const MachineInstr *	OtherMI ) const

Return false if there is no overlap between the region accessed by BaseMI in an iteration and the region accessed by OtherMI in subsequent iterations.

Definition at line 2991 of file MachinePipeliner.cpp.

References llvm::ScheduleDAGInstrs::BB, llvm::computeDelta(), llvm::dbgs(), llvm::MachineInstr::dump(), getPhiRegs(), llvm::MachineOperand::getReg(), llvm::LocationSize::getValue(), llvm::LocationSize::hasValue(), llvm::MachineInstr::isIdenticalTo(), llvm::MachineOperand::isIdenticalTo(), llvm::MachineInstr::isPHI(), llvm::MachineOperand::isReg(), llvm::Register::isVirtual(), LLVM_DEBUG, llvm::MachineInstr::memoperands_begin(), llvm::ScheduleDAG::MF, llvm::ScheduleDAG::MRI, llvm::ScheduleDAG::TII, and llvm::ScheduleDAG::TRI.

Referenced by hasLoopCarriedMemDep(), and isLoopCarriedDep().

◆ schedule()

void SwingSchedulerDAG::schedule ( )

overridevirtual

We override the schedule function in ScheduleDAGInstrs to implement the scheduling part of the Swing Modulo Scheduling algorithm.

Implements llvm::ScheduleDAGInstrs.

Definition at line 680 of file MachinePipeliner.cpp.

References llvm::ModuloScheduleTestAnnotater::annotate(), assert(), llvm::ScheduleDAGInstrs::buildSchedGraph(), llvm::ModuloScheduleExpanderMVE::canApply(), llvm::ModuloScheduleExpander::cleanup(), llvm::dbgs(), DEBUG_TYPE, llvm::LoopCarriedEdges::dump(), llvm::ScheduleDAGInstrs::dump(), EmitTestAnnotations, llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT, BucketT >::empty(), llvm::ScheduleDAG::EntrySU, llvm::ScheduleDAG::ExitSU, llvm::ModuloScheduleExpander::expand(), llvm::ModuloScheduleExpanderMVE::expand(), llvm::PeelingModuloScheduleExpander::expand(), ExperimentalCodeGen, llvm::SMSchedule::getFinalCycle(), llvm::SMSchedule::getFirstCycle(), llvm::SMSchedule::getInstructions(), llvm::SMSchedule::getMaxStageCount(), llvm::ScheduleDAGInstrs::getSUnit(), I, LLVM_DEBUG, llvm::ScheduleDAG::MF, llvm::ScheduleDAG::MRI, MVECodeGen, llvm::stable_sort(), llvm::SMSchedule::stageScheduled(), llvm::ScheduleDAG::SUnits, SwpIgnoreRecMII, SwpMaxMii, SwpMaxStages, and llvm::ScheduleDAG::TRI.

The documentation for this class was generated from the following files:

include/llvm/CodeGen/MachinePipeliner.h
lib/CodeGen/MachinePipeliner.cpp

Public Member Functions

Static Public Member Functions

Additional Inherited Members

Detailed Description

Constructor & Destructor Documentation

◆ SwingSchedulerDAG()

Member Function Documentation

◆ addMutation()

◆ applyInstrChange()

◆ classof()

◆ finishBlock()

◆ fixupRegisterOverlaps()

◆ getALAP()

◆ getASAP()

◆ getDDG()

◆ getDepth()

◆ getHeight()

◆ getInstrBaseReg()

◆ getMOV()

◆ getZeroLatencyDepth()

◆ getZeroLatencyHeight()

◆ hasNewSchedule()

◆ isLoopCarriedDep()

◆ mayOverlapInLaterIter()

◆ schedule()