80 TRI = MF->getSubtarget().getRegisterInfo();
81 MRI = &MF->getRegInfo();
82 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
83 TII = MF->getSubtarget().getInstrInfo();
99 : MCID(&TID), DbgLoc(
std::
move(
DL)), DebugInstrNum(0) {
105 CapOperands = OperandCapacity::get(NumOps);
121 CapOperands = OperandCapacity::get(
MI.getNumOperands());
133 NewMO.TiedTo = OrigMO.TiedTo;
162 MRI.removeRegOperandFromUseList(&MO);
168 MRI.addRegOperandToUseList(&MO);
173 assert(
MBB &&
"Use MachineInstrBuilder to add operands to dangling instrs");
175 assert(MF &&
"Use MachineInstrBuilder to add operands to dangling instrs");
184 return MRI->moveOperands(Dst, Src, NumOps);
186 assert(Dst && Src &&
"Unknown operands");
195 assert(NumOperands < USHRT_MAX &&
"Cannot add more operands.");
196 assert(MCID &&
"Cannot add operands before providing an instr descriptor");
199 if (&Op >= Operands && &Op < Operands + NumOperands) {
215 bool isImpReg = Op.isReg() && Op.isImplicit();
217 while (OpNo && Operands[OpNo-1].
isReg() && Operands[OpNo-1].isImplicit()) {
219 assert(!Operands[OpNo].isTied() &&
"Cannot move tied operands");
227 Op.isValidExcessOperand()) &&
228 "Trying to add an operand to a machine instr that is already done!");
234 OperandCapacity OldCap = CapOperands;
237 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
245 if (OpNo != NumOperands)
246 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
251 if (OldOperands != Operands && OldOperands)
256 NewMO->ParentMI =
this;
259 if (NewMO->
isReg()) {
261 NewMO->Contents.Reg.Prev =
nullptr;
266 MRI->addRegOperandToUseList(NewMO);
272 if (NewMO->
isUse()) {
294 if (Operands[i].
isReg())
295 assert(!Operands[i].isTied() &&
"Cannot move tied operands");
300 MRI->removeRegOperandFromUseList(Operands + OpNo);
306 if (
unsigned N = NumOperands - 1 - OpNo)
317 bool HasPreInstrSymbol = PreInstrSymbol !=
nullptr;
318 bool HasPostInstrSymbol = PostInstrSymbol !=
nullptr;
319 bool HasHeapAllocMarker = HeapAllocMarker !=
nullptr;
320 bool HasPCSections = PCSections !=
nullptr;
321 bool HasCFIType = CFIType != 0;
322 int NumPointers = MMOs.
size() + HasPreInstrSymbol + HasPostInstrSymbol +
323 HasHeapAllocMarker + HasPCSections + HasCFIType;
326 if (NumPointers <= 0) {
335 else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections ||
337 Info.set<EIIK_OutOfLine>(
339 HeapAllocMarker, PCSections, CFIType));
344 if (HasPreInstrSymbol)
345 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
346 else if (HasPostInstrSymbol)
347 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
349 Info.set<EIIK_MMO>(MMOs[0]);
385 "Invalid machine functions when cloning memory refrences!");
405 if (
LHS.size() !=
RHS.size())
410 return std::equal(LHSPointees.begin(), LHSPointees.end(),
411 RHSPointees.begin());
421 if (MIs.
size() == 1) {
437 "Invalid machine functions when cloning memory references!");
442 "Invalid machine functions when cloning memory references!");
453 if (
MI.memoperands_empty()) {
459 MergedMMOs.
append(
MI.memoperands_begin(),
MI.memoperands_end());
471 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
486 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
529 "Invalid machine functions when cloning instruction symbols!");
547 dyn_cast<OverflowingBinaryOperator>(&
I)) {
548 if (OB->hasNoSignedWrap())
550 if (OB->hasNoUnsignedWrap())
566 if (
Flags.noSignedZeros())
568 if (
Flags.allowReciprocal())
570 if (
Flags.allowContract())
572 if (
Flags.approxFunc())
574 if (
Flags.allowReassoc())
585bool MachineInstr::hasPropertyInBundle(
uint64_t Mask, QueryType
Type)
const {
588 if (MII->getDesc().getFlags() & Mask) {
596 if (!MII->isBundledWithSucc())
613 assert(
Other.isBundle() &&
"Expected that both instructions are bundles.");
618 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
621 if (!I1->isIdenticalTo(*I2,
Check))
626 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
694 Other.getDebugExpression(),
Other.isIndirectDebugValue()))
727 case TargetOpcode::PATCHPOINT:
728 case TargetOpcode::STACKMAP:
729 case TargetOpcode::STATEPOINT:
730 case TargetOpcode::FENTRY_CALL:
780 assert(!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
789 assert(!Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
798 assert(Pred->isBundledWithSucc() &&
"Inconsistent bundle flags");
807 assert(Succ->isBundledWithPred() &&
"Inconsistent bundle flags");
827 unsigned *GroupNo)
const {
844 if (i + NumOps > OpIdx) {
856 return cast<DILabel>(
getOperand(0).getMetadata());
900 assert(
getMF() &&
"Can't have an MF reference here!");
926 return TRI->getRegClass(RCID);
930 return TRI->getPointerRegClass(MF);
943 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
944 OpndIt.getOperandNo(), Reg, CurRC,
TII,
TRI);
947 for (
unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
948 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC,
TII,
TRI);
955 assert(CurRC &&
"Invalid initial register class");
970 "Cannot get register constraints for non-register operand");
971 assert(CurRC &&
"Invalid initial register class");
974 CurRC =
TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
976 CurRC =
TRI->getSubClassWithSubReg(CurRC, SubIdx);
978 CurRC =
TRI->getCommonSubClass(CurRC, OpRC);
987 while (
I->isBundledWithSucc()) {
1017 if (MOReg == Reg || (
TRI && Reg && MOReg &&
TRI->regsOverlap(MOReg, Reg)))
1030 bool PartDef =
false;
1031 bool FullDef =
false;
1049 return std::make_pair(
Use || (PartDef && !FullDef), PartDef || FullDef);
1059 bool isPhys = Reg.isPhysical();
1069 bool Found = (MOReg == Reg);
1072 Found =
TRI->regsOverlap(MOReg, Reg);
1074 Found =
TRI->isSubRegister(MOReg, Reg);
1076 if (Found && (!isDead || MO.
isDead()))
1093 if (MCID.
operands()[i].isPredicate())
1118 assert(DefMO.
isDef() &&
"DefIdx must be a def operand");
1119 assert(UseMO.
isUse() &&
"UseIdx must be a use operand");
1120 assert(!DefMO.
isTied() &&
"Def is already tied to another use");
1121 assert(!UseMO.
isTied() &&
"Use is already tied to another def");
1124 UseMO.TiedTo = DefIdx + 1;
1131 "DefIdx out of range");
1136 DefMO.TiedTo = std::min(UseIdx + 1,
TiedMax);
1148 return MO.TiedTo - 1;
1158 if (UseMO.
isReg() && UseMO.
isUse() && UseMO.TiedTo == OpIdx + 1)
1164 if (
getOpcode() == TargetOpcode::STATEPOINT) {
1169 assert(CurUseIdx != -1U &&
"only gc pointer statepoint operands can be tied");
1171 for (
unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1174 if (OpIdx == CurDefIdx)
1176 if (OpIdx == CurUseIdx)
1186 unsigned OpIdxGroup = ~0u;
1191 assert(FlagMO.
isImm() &&
"Invalid tied operand on inline asm");
1192 unsigned CurGroup = GroupIdx.
size();
1196 if (OpIdx > i && OpIdx < i + NumOps)
1197 OpIdxGroup = CurGroup;
1203 unsigned Delta = i - GroupIdx[TiedGroup];
1206 if (OpIdxGroup == CurGroup)
1207 return OpIdx - Delta;
1210 if (OpIdxGroup == TiedGroup)
1211 return OpIdx + Delta;
1230 ToReg = RegInfo.
getSubReg(ToReg, SubIdx);
1295 int64_t MinOffset = std::min(OffsetA, OffsetB);
1304 bool SameVal = (ValA && ValB && (ValA == ValB));
1308 if (PSVa && ValB && !PSVa->
mayAlias(&MFI))
1310 if (PSVb && ValA && !PSVb->
mayAlias(&MFI))
1312 if (PSVa && PSVb && (PSVa == PSVb))
1317 if (!KnownWidthA || !KnownWidthB)
1319 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1320 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1321 return (MinOffset + LowWidth > MaxOffset);
1330 assert((OffsetA >= 0) &&
"Negative MachineMemOperand offset");
1331 assert((OffsetB >= 0) &&
"Negative MachineMemOperand offset");
1375 if (NumChecks >
TII->getMemOperandAACheckLimit())
1381 for (
auto *MMOb :
Other.memoperands())
1427 if (!MMO->isUnordered())
1432 if (MMO->isStore())
return false;
1433 if (MMO->isInvariant() && MMO->isDereferenceable())
1438 if (PSV->isConstant(&MFI))
1457 "It's illegal to have a PHI without source operands");
1507 if (MCID.
Opcode == TargetOpcode::STATEPOINT)
1511 if (!Operand.isReg() || Operand.isDef())
1516 if (ExpectedTiedIdx != TiedIdx)
1529 return MRI.getType(Op.getReg());
1532 if (!OpInfo.isGenericType())
1533 return MRI.getType(Op.getReg());
1535 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1538 LLT TypeToPrint =
MRI.getType(Op.getReg());
1542 PrintedTypes.
set(OpInfo.getGenericTypeIndex());
1546#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1557 if (!AlreadySeenInstrs.
insert(
this).second)
1568 if (Reg.isPhysical())
1571 if (NewMI ==
nullptr)
1585 bool SkipDebugLoc,
bool AddNewLine,
1587 const Module *M =
nullptr;
1599 print(
OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine,
TII);
1603 bool IsStandalone,
bool SkipOpers,
bool SkipDebugLoc,
1616 auto getTiedOperandIdx = [&](
unsigned OpIdx) {
1617 if (!ShouldPrintRegisterTies)
1624 unsigned StartOp = 0;
1628 while (StartOp < e) {
1637 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1638 MO.
print(
OS, MST, TypeToPrint, StartOp,
false, IsStandalone,
1639 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1647 OS <<
"frame-setup ";
1649 OS <<
"frame-destroy ";
1671 OS <<
"nofpexcept ";
1685 bool FirstOp =
true;
1686 unsigned AsmDescOp = ~0u;
1687 unsigned AsmOpCount = 0;
1694 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1696 ShouldPrintRegisterTies, TiedOperandIdx,
TRI,
1702 OS <<
" [sideeffect]";
1706 OS <<
" [maystore]";
1708 OS <<
" [isconvergent]";
1710 OS <<
" [alignstack]";
1712 OS <<
" [attdialect]";
1714 OS <<
" [inteldialect]";
1723 if (FirstOp) FirstOp =
false;
else OS <<
",";
1728 auto *DIV = dyn_cast<DILocalVariable>(MO.
getMetadata());
1729 if (DIV && !DIV->getName().empty())
1730 OS <<
"!\"" << DIV->getName() <<
'\"';
1733 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1734 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1735 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1740 if (DIL && !DIL->getName().empty())
1741 OS <<
"\"" << DIL->getName() <<
'\"';
1744 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1745 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1746 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1748 }
else if (i == AsmDescOp && MO.
isImm()) {
1750 OS <<
'$' << AsmOpCount++;
1751 unsigned Flag = MO.
getImm();
1759 OS <<
':' <<
TRI->getRegClassName(
TRI->getRegClass(RCID));
1761 OS <<
":RC" << RCID;
1769 unsigned TiedTo = 0;
1771 OS <<
" tiedto:$" << TiedTo;
1779 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1783 MO.
print(
OS, MST, TypeToPrint, i,
true, IsStandalone,
1784 ShouldPrintRegisterTies, TiedOperandIdx,
TRI, IntrinsicInfo);
1795 OS <<
" pre-instr-symbol ";
1803 OS <<
" post-instr-symbol ";
1811 OS <<
" heap-alloc-marker ";
1819 OS <<
" pcsections ";
1825 OS <<
" cfi-type " << CFIType;
1828 if (DebugInstrNum) {
1831 OS <<
" debug-instr-number " << DebugInstrNum;
1834 if (!SkipDebugLoc) {
1838 OS <<
" debug-location ";
1846 std::unique_ptr<LLVMContext> CtxPtr;
1852 CtxPtr = std::make_unique<LLVMContext>();
1857 bool NeedComma =
false;
1869 bool HaveSemi =
false;
1888 OS <<
" line no:" << DV->getLine();
1900 bool AddIfNotFound) {
1902 bool hasAliases = isPhysReg &&
1921 if (Reg == IncomingReg) {
1932 }
else if (hasAliases && MO.
isKill() && Reg.isPhysical()) {
1942 while (!DeadOps.
empty()) {
1943 unsigned OpIdx = DeadOps.
back();
1954 if (!Found && AddIfNotFound) {
1966 if (!Reg.isPhysical())
1972 if ((RegInfo && RegInfo->
regsOverlap(Reg, OpReg)) || Reg == OpReg)
1979 bool AddIfNotFound) {
1980 bool isPhysReg = Reg.isPhysical();
1981 bool hasAliases = isPhysReg &&
2006 while (!DeadOps.
empty()) {
2007 unsigned OpIdx = DeadOps.
back();
2018 if (Found || !AddIfNotFound)
2047 if (Reg.isPhysical()) {
2065 bool HasRegMask =
false;
2073 if (!Reg.isPhysical())
2084 for (
const Register &UsedReg : UsedRegs)
2092 HashComponents.
reserve(
MI->getNumOperands() + 1);
2106 const MDNode *LocMD =
nullptr;
2112 mdconst::dyn_extract<ConstantInt>(LocMD->
getOperand(0))) {
2113 LocCookie = CI->getZExtValue();
2129 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2130 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2131 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
2132 "Expected inlined-at fields to agree");
2145 assert(isa<DILocalVariable>(Variable) &&
"not a variable");
2146 assert(cast<DIExpression>(Expr)->
isValid() &&
"not an expression");
2147 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(
DL) &&
2148 "Expected inlined-at fields to agree");
2149 if (MCID.
Opcode == TargetOpcode::DBG_VALUE) {
2151 "DBG_VALUE must contain exactly one debug operand");
2153 if (DebugOp.
isReg())
2166 MIB.addMetadata(Variable).addMetadata(Expr);
2168 if (DebugOp.isReg())
2169 MIB.addReg(DebugOp.getReg());
2194 BuildMI(MF,
DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2204 assert(
MI.getDebugVariable()->isValidLocationForIntrinsic(
MI.getDebugLoc()) &&
2205 "Expected inlined-at fields to agree");
2208 if (
MI.isIndirectDebugValue()) {
2209 assert(
MI.getDebugOffset().getImm() == 0 &&
2210 "DBG_VALUE with nonzero offset");
2212 }
else if (
MI.isDebugValueList()) {
2215 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2217 unsigned OpIdx =
MI.getDebugOperandIndex(Op);
2225 assert(
MI.hasDebugOperandForReg(SpillReg) &&
"Spill Reg is not used in MI.");
2235 int FrameIndex,
Register SpillReg) {
2237 "DBG_INSTR_REF should not reference a virtual register.");
2248 if (Op.isReg() && Op.getReg() == SpillReg)
2283 Op.ChangeToFrameIndex(FrameIndex);
2290 if (!
MI.getOperand(0).isReg())
2296 if (!DI->isDebugValue())
2298 if (DI->hasDebugOperandForReg(
MI.getOperand(0).getReg()))
2311 auto *
MRI = getRegInfo();
2312 for (
auto &MO :
MRI->use_operands(DefReg)) {
2314 if (!DI->isDebugValue())
2316 if (DI->hasDebugOperandForReg(DefReg)) {
2322 for (
auto *DBI : DbgValues)
2332 for (
const auto *
A : Accesses)
2334 cast<FixedStackPseudoSourceValue>(
A->getPseudoValue())
2336 Size +=
A->getSize();
2340std::optional<unsigned>
2343 if (
TII->isStoreToStackSlotPostFE(*
this, FI)) {
2348 return std::nullopt;
2351std::optional<unsigned>
2356 return std::nullopt;
2359std::optional<unsigned>
2362 if (
TII->isLoadFromStackSlotPostFE(*
this, FI)) {
2367 return std::nullopt;
2370std::optional<unsigned>
2375 return std::nullopt;
2379 if (DebugInstrNum == 0)
2381 return DebugInstrNum;
2385 if (DebugInstrNum == 0)
2387 return DebugInstrNum;
2416std::tuple<Register, LLT, Register, LLT>
2420 return std::tuple(Reg0, getRegInfo()->
getType(Reg0), Reg1,
2424std::tuple<Register, LLT, Register, LLT, Register, LLT>
2429 return std::tuple(Reg0, getRegInfo()->
getType(Reg0), Reg1,
2430 getRegInfo()->
getType(Reg1), Reg2,
2434std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2441 Reg0, getRegInfo()->
getType(Reg0), Reg1, getRegInfo()->
getType(Reg1),
2442 Reg2, getRegInfo()->
getType(Reg2), Reg3, getRegInfo()->
getType(Reg3));
2454 Reg0, getRegInfo()->
getType(Reg0), Reg1, getRegInfo()->
getType(Reg1),
2455 Reg2, getRegInfo()->
getType(Reg2), Reg3, getRegInfo()->
getType(Reg3),
2456 Reg4, getRegInfo()->
getType(Reg4));
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
const HexagonInstrInfo * TII
static const unsigned MaxDepth
Implement a low-level type suitable for MachineInstr level instruction selection.
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
static unsigned getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
Module.h This file contains the declarations for the Module class.
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This file implements the SmallBitVector class.
This file defines the SmallVector class.
static SymbolRef::Type getType(const Symbol *Sym)
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)
Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Utility class for floating point operations which can have information about relaxed accuracy require...
Convenience struct for specifying and reasoning about fast-math flags.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
static bool isMemKind(unsigned Flag)
static StringRef getKindName(unsigned Kind)
static unsigned getNumOperandRegisters(unsigned Flag)
getNumOperandRegisters - Extract the number of registers field from the inline asm operand flag.
static StringRef getMemConstraintName(unsigned Constraint)
static unsigned getMemoryConstraintID(unsigned Flag)
@ Kind_RegDefEarlyClobber
static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx)
isUseOperandTiedToDef - Return true if the flag of the inline asm operand indicates it is an use oper...
static bool isImmKind(unsigned Flag)
static bool hasRegClassConstraint(unsigned Flag, unsigned &RC)
hasRegClassConstraint - Returns true if the flag contains a register class constraint.
static unsigned getKind(unsigned Flags)
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Wrapper class representing physical registers. Should be passed by value.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
const MDOperand & getOperand(unsigned I) const
unsigned getNumOperands() const
Return number of MDNode operands.
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
unsigned getNewDebugInstrNum()
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0)
Allocate and construct an extra info structure for a MachineInstr.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
uint16_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
bool isDebugValueList() const
void bundleWithPred()
Bundle this instruction with its predecessor.
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
const MachineBasicBlock * getParent() const
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
QueryType
API for querying MachineInstr properties.
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
bool isCall(QueryType Type=AnyInBundle) const
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
unsigned getNumOperands() const
Retuns the total number of operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
std::optional< unsigned > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
std::tuple< LLT, LLT > getFirst2LLTs() const
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool isStackAligningInlineAsm() const
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
static uint16_t copyFlagsFromInstruction(const Instruction &I)
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' form its basic block and delete it.
iterator_range< mop_iterator > operands()
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
std::optional< unsigned > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
std::optional< unsigned > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isNonListDebugValue() const
std::optional< unsigned > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isDebugValue() const
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
MachineOperand & getDebugOperand(unsigned Index)
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
uint16_t getFlags() const
Return the MI flags bitvector.
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
void unbundleFromSucc()
Break bundle below this instruction.
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
A description of a memory reference used in the backend.
const PseudoSourceValue * getPseudoValue() const
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
uint64_t getSize() const
Return the size in bytes of the memory reference.
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MDNode * getMetadata() const
void setIsDead(bool Val=true)
void setMetadata(const MDNode *MD)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setIsEarlyClobber(bool Val=true)
void setIsUndef(bool Val=true)
void setIsDebug(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Representation for a specific memory location.
Manage lifetime of a slot tracker for printing IR.
void incorporateFunction(const Function &F)
Incorporate the given function.
A Module instance is used to store all the information related to an LLVM module.
LLVMContext & getContext() const
Get the global data context.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Special value supplied for machine level alias analysis.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Wrapper class representing virtual and physical registers.
bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void reserve(size_type N)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
MI-level Statepoint operands.
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual const TargetInstrInfo * getInstrInfo() const
The instances of the Type class are immutable: once they are created, they are never changed.
A Use represents the edge between a Value definition and its users.
LLVM Value Representation.
Iterator for intrusive lists based on ilist_node.
self_iterator getIterator()
This class implements an extremely fast bulk output stream that can only output to a stream.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
hash_code hash_value(const FixedPointSemantics &Val)
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static unsigned getHashValue(const MachineInstr *const &MI)