LLVM 19.0.0git
MachineInstr.cpp
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1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/Hashing.h"
16#include "llvm/ADT/STLExtras.h"
37#include "llvm/IR/Constants.h"
39#include "llvm/IR/DebugLoc.h"
40#include "llvm/IR/Function.h"
41#include "llvm/IR/InlineAsm.h"
43#include "llvm/IR/LLVMContext.h"
44#include "llvm/IR/Metadata.h"
45#include "llvm/IR/Module.h"
47#include "llvm/IR/Operator.h"
48#include "llvm/MC/MCInstrDesc.h"
52#include "llvm/Support/Debug.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <utility>
62
63using namespace llvm;
64
66 if (const MachineBasicBlock *MBB = MI.getParent())
67 if (const MachineFunction *MF = MBB->getParent())
68 return MF;
69 return nullptr;
70}
71
72// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
73// it.
75 const TargetRegisterInfo *&TRI,
77 const TargetIntrinsicInfo *&IntrinsicInfo,
78 const TargetInstrInfo *&TII) {
79
80 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
81 TRI = MF->getSubtarget().getRegisterInfo();
82 MRI = &MF->getRegInfo();
83 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
84 TII = MF->getSubtarget().getInstrInfo();
85 }
86}
87
89 for (MCPhysReg ImpDef : MCID->implicit_defs())
90 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true));
91 for (MCPhysReg ImpUse : MCID->implicit_uses())
92 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true));
93}
94
95/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
96/// implicit operands. It reserves space for the number of operands specified by
97/// the MCInstrDesc.
98MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
99 DebugLoc DL, bool NoImp)
100 : MCID(&TID), NumOperands(0), Flags(0), AsmPrinterFlags(0),
101 DbgLoc(std::move(DL)), DebugInstrNum(0) {
102 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
103
104 // Reserve space for the expected number of operands.
105 if (unsigned NumOps = MCID->getNumOperands() + MCID->implicit_defs().size() +
106 MCID->implicit_uses().size()) {
107 CapOperands = OperandCapacity::get(NumOps);
108 Operands = MF.allocateOperandArray(CapOperands);
109 }
110
111 if (!NoImp)
113}
114
115/// MachineInstr ctor - Copies MachineInstr arg exactly.
116/// Does not copy the number from debug instruction numbering, to preserve
117/// uniqueness.
118MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
119 : MCID(&MI.getDesc()), NumOperands(0), Flags(0), AsmPrinterFlags(0),
120 Info(MI.Info), DbgLoc(MI.getDebugLoc()), DebugInstrNum(0) {
121 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor");
122
123 CapOperands = OperandCapacity::get(MI.getNumOperands());
124 Operands = MF.allocateOperandArray(CapOperands);
125
126 // Copy operands.
127 for (const MachineOperand &MO : MI.operands())
128 addOperand(MF, MO);
129
130 // Replicate ties between the operands, which addOperand was not
131 // able to do reliably.
132 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
133 MachineOperand &NewMO = getOperand(i);
134 const MachineOperand &OrigMO = MI.getOperand(i);
135 NewMO.TiedTo = OrigMO.TiedTo;
136 }
137
138 // Copy all the sensible flags.
139 setFlags(MI.Flags);
140}
141
143 if (getParent())
144 getMF()->handleChangeDesc(*this, TID);
145 MCID = &TID;
146}
147
149 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
150}
151
152/// getRegInfo - If this instruction is embedded into a MachineFunction,
153/// return the MachineRegisterInfo object for the current function, otherwise
154/// return null.
155MachineRegisterInfo *MachineInstr::getRegInfo() {
157 return &MBB->getParent()->getRegInfo();
158 return nullptr;
159}
160
161const MachineRegisterInfo *MachineInstr::getRegInfo() const {
162 if (const MachineBasicBlock *MBB = getParent())
163 return &MBB->getParent()->getRegInfo();
164 return nullptr;
165}
166
167void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
168 for (MachineOperand &MO : operands())
169 if (MO.isReg())
170 MRI.removeRegOperandFromUseList(&MO);
171}
172
173void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
174 for (MachineOperand &MO : operands())
175 if (MO.isReg())
176 MRI.addRegOperandToUseList(&MO);
177}
178
181 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
183 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
184 addOperand(*MF, Op);
185}
186
187/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
188/// ranges. If MRI is non-null also update use-def chains.
190 unsigned NumOps, MachineRegisterInfo *MRI) {
191 if (MRI)
192 return MRI->moveOperands(Dst, Src, NumOps);
193 // MachineOperand is a trivially copyable type so we can just use memmove.
194 assert(Dst && Src && "Unknown operands");
195 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
196}
197
198/// addOperand - Add the specified operand to the instruction. If it is an
199/// implicit operand, it is added to the end of the operand list. If it is
200/// an explicit operand it is added at the end of the explicit operand list
201/// (before the first implicit operand).
203 assert(isUInt<LLVM_MI_NUMOPERANDS_BITS>(NumOperands + 1) &&
204 "Cannot add more operands.");
205 assert(MCID && "Cannot add operands before providing an instr descriptor");
206
207 // Check if we're adding one of our existing operands.
208 if (&Op >= Operands && &Op < Operands + NumOperands) {
209 // This is unusual: MI->addOperand(MI->getOperand(i)).
210 // If adding Op requires reallocating or moving existing operands around,
211 // the Op reference could go stale. Support it by copying Op.
212 MachineOperand CopyOp(Op);
213 return addOperand(MF, CopyOp);
214 }
215
216 // Find the insert location for the new operand. Implicit registers go at
217 // the end, everything else goes before the implicit regs.
218 //
219 // FIXME: Allow mixed explicit and implicit operands on inline asm.
220 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
221 // implicit-defs, but they must not be moved around. See the FIXME in
222 // InstrEmitter.cpp.
223 unsigned OpNo = getNumOperands();
224 bool isImpReg = Op.isReg() && Op.isImplicit();
225 if (!isImpReg && !isInlineAsm()) {
226 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
227 --OpNo;
228 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
229 }
230 }
231
232 // OpNo now points as the desired insertion point. Unless this is a variadic
233 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
234 // RegMask operands go between the explicit and implicit operands.
235 MachineRegisterInfo *MRI = getRegInfo();
236
237 // Determine if the Operands array needs to be reallocated.
238 // Save the old capacity and operand array.
239 OperandCapacity OldCap = CapOperands;
240 MachineOperand *OldOperands = Operands;
241 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
242 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
243 Operands = MF.allocateOperandArray(CapOperands);
244 // Move the operands before the insertion point.
245 if (OpNo)
246 moveOperands(Operands, OldOperands, OpNo, MRI);
247 }
248
249 // Move the operands following the insertion point.
250 if (OpNo != NumOperands)
251 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
252 MRI);
253 ++NumOperands;
254
255 // Deallocate the old operand array.
256 if (OldOperands != Operands && OldOperands)
257 MF.deallocateOperandArray(OldCap, OldOperands);
258
259 // Copy Op into place. It still needs to be inserted into the MRI use lists.
260 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
261 NewMO->ParentMI = this;
262
263 // When adding a register operand, tell MRI about it.
264 if (NewMO->isReg()) {
265 // Ensure isOnRegUseList() returns false, regardless of Op's status.
266 NewMO->Contents.Reg.Prev = nullptr;
267 // Ignore existing ties. This is not a property that can be copied.
268 NewMO->TiedTo = 0;
269 // Add the new operand to MRI, but only for instructions in an MBB.
270 if (MRI)
271 MRI->addRegOperandToUseList(NewMO);
272 // The MCID operand information isn't accurate until we start adding
273 // explicit operands. The implicit operands are added first, then the
274 // explicits are inserted before them.
275 if (!isImpReg) {
276 // Tie uses to defs as indicated in MCInstrDesc.
277 if (NewMO->isUse()) {
278 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
279 if (DefIdx != -1)
280 tieOperands(DefIdx, OpNo);
281 }
282 // If the register operand is flagged as early, mark the operand as such.
283 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
284 NewMO->setIsEarlyClobber(true);
285 }
286 // Ensure debug instructions set debug flag on register uses.
287 if (NewMO->isUse() && isDebugInstr())
288 NewMO->setIsDebug();
289 }
290}
291
292void MachineInstr::removeOperand(unsigned OpNo) {
293 assert(OpNo < getNumOperands() && "Invalid operand number");
294 untieRegOperand(OpNo);
295
296#ifndef NDEBUG
297 // Moving tied operands would break the ties.
298 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
299 if (Operands[i].isReg())
300 assert(!Operands[i].isTied() && "Cannot move tied operands");
301#endif
302
303 MachineRegisterInfo *MRI = getRegInfo();
304 if (MRI && Operands[OpNo].isReg())
305 MRI->removeRegOperandFromUseList(Operands + OpNo);
306
307 // Don't call the MachineOperand destructor. A lot of this code depends on
308 // MachineOperand having a trivial destructor anyway, and adding a call here
309 // wouldn't make it 'destructor-correct'.
310
311 if (unsigned N = NumOperands - 1 - OpNo)
312 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
313 --NumOperands;
314}
315
316void MachineInstr::setExtraInfo(MachineFunction &MF,
318 MCSymbol *PreInstrSymbol,
319 MCSymbol *PostInstrSymbol,
320 MDNode *HeapAllocMarker, MDNode *PCSections,
321 uint32_t CFIType) {
322 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
323 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
324 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
325 bool HasPCSections = PCSections != nullptr;
326 bool HasCFIType = CFIType != 0;
327 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +
328 HasHeapAllocMarker + HasPCSections + HasCFIType;
329
330 // Drop all extra info if there is none.
331 if (NumPointers <= 0) {
332 Info.clear();
333 return;
334 }
335
336 // If more than one pointer, then store out of line. Store heap alloc markers
337 // out of line because PointerSumType cannot hold more than 4 tag types with
338 // 32-bit pointers.
339 // FIXME: Maybe we should make the symbols in the extra info mutable?
340 else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections ||
341 HasCFIType) {
342 Info.set<EIIK_OutOfLine>(
343 MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,
344 HeapAllocMarker, PCSections, CFIType));
345 return;
346 }
347
348 // Otherwise store the single pointer inline.
349 if (HasPreInstrSymbol)
350 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
351 else if (HasPostInstrSymbol)
352 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
353 else
354 Info.set<EIIK_MMO>(MMOs[0]);
355}
356
358 if (memoperands_empty())
359 return;
360
361 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
363}
364
367 if (MMOs.empty()) {
368 dropMemRefs(MF);
369 return;
370 }
371
372 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
374}
375
377 MachineMemOperand *MO) {
380 MMOs.push_back(MO);
381 setMemRefs(MF, MMOs);
382}
383
385 if (this == &MI)
386 // Nothing to do for a self-clone!
387 return;
388
389 assert(&MF == MI.getMF() &&
390 "Invalid machine functions when cloning memory refrences!");
391 // See if we can just steal the extra info already allocated for the
392 // instruction. We can do this whenever the pre- and post-instruction symbols
393 // are the same (including null).
394 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
395 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
396 getHeapAllocMarker() == MI.getHeapAllocMarker() &&
397 getPCSections() == MI.getPCSections()) {
398 Info = MI.Info;
399 return;
400 }
401
402 // Otherwise, fall back on a copy-based clone.
403 setMemRefs(MF, MI.memoperands());
404}
405
406/// Check to see if the MMOs pointed to by the two MemRefs arrays are
407/// identical.
410 if (LHS.size() != RHS.size())
411 return false;
412
413 auto LHSPointees = make_pointee_range(LHS);
414 auto RHSPointees = make_pointee_range(RHS);
415 return std::equal(LHSPointees.begin(), LHSPointees.end(),
416 RHSPointees.begin());
417}
418
421 // Try handling easy numbers of MIs with simpler mechanisms.
422 if (MIs.empty()) {
423 dropMemRefs(MF);
424 return;
425 }
426 if (MIs.size() == 1) {
427 cloneMemRefs(MF, *MIs[0]);
428 return;
429 }
430 // Because an empty memoperands list provides *no* information and must be
431 // handled conservatively (assuming the instruction can do anything), the only
432 // way to merge with it is to drop all other memoperands.
433 if (MIs[0]->memoperands_empty()) {
434 dropMemRefs(MF);
435 return;
436 }
437
438 // Handle the general case.
440 // Start with the first instruction.
441 assert(&MF == MIs[0]->getMF() &&
442 "Invalid machine functions when cloning memory references!");
443 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
444 // Now walk all the other instructions and accumulate any different MMOs.
445 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
446 assert(&MF == MI.getMF() &&
447 "Invalid machine functions when cloning memory references!");
448
449 // Skip MIs with identical operands to the first. This is a somewhat
450 // arbitrary hack but will catch common cases without being quadratic.
451 // TODO: We could fully implement merge semantics here if needed.
452 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
453 continue;
454
455 // Because an empty memoperands list provides *no* information and must be
456 // handled conservatively (assuming the instruction can do anything), the
457 // only way to merge with it is to drop all other memoperands.
458 if (MI.memoperands_empty()) {
459 dropMemRefs(MF);
460 return;
461 }
462
463 // Otherwise accumulate these into our temporary buffer of the merged state.
464 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
465 }
466
467 setMemRefs(MF, MergedMMOs);
468}
469
471 // Do nothing if old and new symbols are the same.
472 if (Symbol == getPreInstrSymbol())
473 return;
474
475 // If there was only one symbol and we're removing it, just clear info.
476 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
477 Info.clear();
478 return;
479 }
480
481 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
483}
484
486 // Do nothing if old and new symbols are the same.
487 if (Symbol == getPostInstrSymbol())
488 return;
489
490 // If there was only one symbol and we're removing it, just clear info.
491 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
492 Info.clear();
493 return;
494 }
495
496 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
498}
499
501 // Do nothing if old and new symbols are the same.
502 if (Marker == getHeapAllocMarker())
503 return;
504
505 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
506 Marker, getPCSections(), getCFIType());
507}
508
510 // Do nothing if old and new symbols are the same.
511 if (PCSections == getPCSections())
512 return;
513
514 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
515 getHeapAllocMarker(), PCSections, getCFIType());
516}
517
519 // Do nothing if old and new types are the same.
520 if (Type == getCFIType())
521 return;
522
523 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
525}
526
528 const MachineInstr &MI) {
529 if (this == &MI)
530 // Nothing to do for a self-clone!
531 return;
532
533 assert(&MF == MI.getMF() &&
534 "Invalid machine functions when cloning instruction symbols!");
535
536 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
537 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
538 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
539 setPCSections(MF, MI.getPCSections());
540}
541
543 // For now, the just return the union of the flags. If the flags get more
544 // complicated over time, we might need more logic here.
545 return getFlags() | Other.getFlags();
546}
547
549 uint32_t MIFlags = 0;
550 // Copy the wrapping flags.
551 if (const OverflowingBinaryOperator *OB =
552 dyn_cast<OverflowingBinaryOperator>(&I)) {
553 if (OB->hasNoSignedWrap())
555 if (OB->hasNoUnsignedWrap())
557 } else if (const TruncInst *TI = dyn_cast<TruncInst>(&I)) {
558 if (TI->hasNoSignedWrap())
560 if (TI->hasNoUnsignedWrap())
562 }
563
564 // Copy the nonneg flag.
565 if (const PossiblyNonNegInst *PNI = dyn_cast<PossiblyNonNegInst>(&I)) {
566 if (PNI->hasNonNeg())
568 // Copy the disjoint flag.
569 } else if (const PossiblyDisjointInst *PD =
570 dyn_cast<PossiblyDisjointInst>(&I)) {
571 if (PD->isDisjoint())
573 }
574
575 // Copy the exact flag.
576 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
577 if (PE->isExact())
579
580 // Copy the fast-math flags.
581 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
582 const FastMathFlags Flags = FP->getFastMathFlags();
583 if (Flags.noNaNs())
585 if (Flags.noInfs())
587 if (Flags.noSignedZeros())
589 if (Flags.allowReciprocal())
591 if (Flags.allowContract())
593 if (Flags.approxFunc())
595 if (Flags.allowReassoc())
597 }
598
599 if (I.getMetadata(LLVMContext::MD_unpredictable))
601
602 return MIFlags;
603}
604
607}
608
609bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
610 assert(!isBundledWithPred() && "Must be called on bundle header");
612 if (MII->getDesc().getFlags() & Mask) {
613 if (Type == AnyInBundle)
614 return true;
615 } else {
616 if (Type == AllInBundle && !MII->isBundle())
617 return false;
618 }
619 // This was the last instruction in the bundle.
620 if (!MII->isBundledWithSucc())
621 return Type == AllInBundle;
622 }
623}
624
626 MICheckType Check) const {
627 // If opcodes or number of operands are not the same then the two
628 // instructions are obviously not identical.
629 if (Other.getOpcode() != getOpcode() ||
630 Other.getNumOperands() != getNumOperands())
631 return false;
632
633 if (isBundle()) {
634 // We have passed the test above that both instructions have the same
635 // opcode, so we know that both instructions are bundles here. Let's compare
636 // MIs inside the bundle.
637 assert(Other.isBundle() && "Expected that both instructions are bundles.");
640 // Loop until we analysed the last intruction inside at least one of the
641 // bundles.
642 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
643 ++I1;
644 ++I2;
645 if (!I1->isIdenticalTo(*I2, Check))
646 return false;
647 }
648 // If we've reached the end of just one of the two bundles, but not both,
649 // the instructions are not identical.
650 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
651 return false;
652 }
653
654 // Check operands to make sure they match.
655 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
656 const MachineOperand &MO = getOperand(i);
657 const MachineOperand &OMO = Other.getOperand(i);
658 if (!MO.isReg()) {
659 if (!MO.isIdenticalTo(OMO))
660 return false;
661 continue;
662 }
663
664 // Clients may or may not want to ignore defs when testing for equality.
665 // For example, machine CSE pass only cares about finding common
666 // subexpressions, so it's safe to ignore virtual register defs.
667 if (MO.isDef()) {
668 if (Check == IgnoreDefs)
669 continue;
670 else if (Check == IgnoreVRegDefs) {
671 if (!MO.getReg().isVirtual() || !OMO.getReg().isVirtual())
672 if (!MO.isIdenticalTo(OMO))
673 return false;
674 } else {
675 if (!MO.isIdenticalTo(OMO))
676 return false;
677 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
678 return false;
679 }
680 } else {
681 if (!MO.isIdenticalTo(OMO))
682 return false;
683 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
684 return false;
685 }
686 }
687 // If DebugLoc does not match then two debug instructions are not identical.
688 if (isDebugInstr())
689 if (getDebugLoc() && Other.getDebugLoc() &&
690 getDebugLoc() != Other.getDebugLoc())
691 return false;
692 // If pre- or post-instruction symbols do not match then the two instructions
693 // are not identical.
694 if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
695 getPostInstrSymbol() != Other.getPostInstrSymbol())
696 return false;
697 // Call instructions with different CFI types are not identical.
698 if (isCall() && getCFIType() != Other.getCFIType())
699 return false;
700
701 return true;
702}
703
705 if (!isDebugValueLike() || !Other.isDebugValueLike())
706 return false;
707 if (getDebugLoc() != Other.getDebugLoc())
708 return false;
709 if (getDebugVariable() != Other.getDebugVariable())
710 return false;
711 if (getNumDebugOperands() != Other.getNumDebugOperands())
712 return false;
713 for (unsigned OpIdx = 0; OpIdx < getNumDebugOperands(); ++OpIdx)
714 if (!getDebugOperand(OpIdx).isIdenticalTo(Other.getDebugOperand(OpIdx)))
715 return false;
718 Other.getDebugExpression(), Other.isIndirectDebugValue()))
719 return false;
720 return true;
721}
722
724 return getParent()->getParent();
725}
726
728 assert(getParent() && "Not embedded in a basic block!");
729 return getParent()->remove(this);
730}
731
733 assert(getParent() && "Not embedded in a basic block!");
734 return getParent()->remove_instr(this);
735}
736
738 assert(getParent() && "Not embedded in a basic block!");
739 getParent()->erase(this);
740}
741
743 assert(getParent() && "Not embedded in a basic block!");
744 getParent()->erase_instr(this);
745}
746
748 if (!isCall(Type))
749 return false;
750 switch (getOpcode()) {
751 case TargetOpcode::PATCHPOINT:
752 case TargetOpcode::STACKMAP:
753 case TargetOpcode::STATEPOINT:
754 case TargetOpcode::FENTRY_CALL:
755 return false;
756 }
757 return true;
758}
759
761 if (isBundle())
764}
765
767 unsigned NumOperands = MCID->getNumOperands();
768 if (!MCID->isVariadic())
769 return NumOperands;
770
771 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
772 const MachineOperand &MO = getOperand(I);
773 // The operands must always be in the following order:
774 // - explicit reg defs,
775 // - other explicit operands (reg uses, immediates, etc.),
776 // - implicit reg defs
777 // - implicit reg uses
778 if (MO.isReg() && MO.isImplicit())
779 break;
780 ++NumOperands;
781 }
782 return NumOperands;
783}
784
786 unsigned NumDefs = MCID->getNumDefs();
787 if (!MCID->isVariadic())
788 return NumDefs;
789
790 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
791 const MachineOperand &MO = getOperand(I);
792 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
793 break;
794 ++NumDefs;
795 }
796 return NumDefs;
797}
798
800 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
803 --Pred;
804 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
805 Pred->setFlag(BundledSucc);
806}
807
809 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
812 ++Succ;
813 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
814 Succ->setFlag(BundledPred);
815}
816
818 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
821 --Pred;
822 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
823 Pred->clearFlag(BundledSucc);
824}
825
827 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
830 ++Succ;
831 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
832 Succ->clearFlag(BundledPred);
833}
834
836 if (isInlineAsm()) {
837 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
838 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
839 return true;
840 }
841 return false;
842}
843
845 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
846 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
847 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
848}
849
851 unsigned *GroupNo) const {
852 assert(isInlineAsm() && "Expected an inline asm instruction");
853 assert(OpIdx < getNumOperands() && "OpIdx out of range");
854
855 // Ignore queries about the initial operands.
857 return -1;
858
859 unsigned Group = 0;
860 unsigned NumOps;
861 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
862 i += NumOps) {
863 const MachineOperand &FlagMO = getOperand(i);
864 // If we reach the implicit register operands, stop looking.
865 if (!FlagMO.isImm())
866 return -1;
867 const InlineAsm::Flag F(FlagMO.getImm());
868 NumOps = 1 + F.getNumOperandRegisters();
869 if (i + NumOps > OpIdx) {
870 if (GroupNo)
871 *GroupNo = Group;
872 return i;
873 }
874 ++Group;
875 }
876 return -1;
877}
878
880 assert(isDebugLabel() && "not a DBG_LABEL");
881 return cast<DILabel>(getOperand(0).getMetadata());
882}
883
885 assert((isDebugValueLike()) && "not a DBG_VALUE*");
886 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
887 return getOperand(VariableOp);
888}
889
891 assert((isDebugValueLike()) && "not a DBG_VALUE*");
892 unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
893 return getOperand(VariableOp);
894}
895
897 return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
898}
899
901 assert((isDebugValueLike()) && "not a DBG_VALUE*");
902 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
903 return getOperand(ExpressionOp);
904}
905
907 assert((isDebugValueLike()) && "not a DBG_VALUE*");
908 unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
909 return getOperand(ExpressionOp);
910}
911
913 return cast<DIExpression>(getDebugExpressionOp().getMetadata());
914}
915
918}
919
922 const TargetInstrInfo *TII,
923 const TargetRegisterInfo *TRI) const {
924 assert(getParent() && "Can't have an MBB reference here!");
925 assert(getMF() && "Can't have an MF reference here!");
926 const MachineFunction &MF = *getMF();
927
928 // Most opcodes have fixed constraints in their MCInstrDesc.
929 if (!isInlineAsm())
930 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
931
932 if (!getOperand(OpIdx).isReg())
933 return nullptr;
934
935 // For tied uses on inline asm, get the constraint from the def.
936 unsigned DefIdx;
937 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
938 OpIdx = DefIdx;
939
940 // Inline asm stores register class constraints in the flag word.
941 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
942 if (FlagIdx < 0)
943 return nullptr;
944
945 const InlineAsm::Flag F(getOperand(FlagIdx).getImm());
946 unsigned RCID;
947 if ((F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind()) &&
948 F.hasRegClassConstraint(RCID))
949 return TRI->getRegClass(RCID);
950
951 // Assume that all registers in a memory operand are pointers.
952 if (F.isMemKind())
953 return TRI->getPointerRegClass(MF);
954
955 return nullptr;
956}
957
959 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
960 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
961 // Check every operands inside the bundle if we have
962 // been asked to.
963 if (ExploreBundle)
964 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
965 ++OpndIt)
966 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
967 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
968 else
969 // Otherwise, just check the current operands.
970 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
971 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
972 return CurRC;
973}
974
975const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
976 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
977 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
978 assert(CurRC && "Invalid initial register class");
979 // Check if Reg is constrained by some of its use/def from MI.
980 const MachineOperand &MO = getOperand(OpIdx);
981 if (!MO.isReg() || MO.getReg() != Reg)
982 return CurRC;
983 // If yes, accumulate the constraints through the operand.
984 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
985}
986
988 unsigned OpIdx, const TargetRegisterClass *CurRC,
989 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
990 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
991 const MachineOperand &MO = getOperand(OpIdx);
992 assert(MO.isReg() &&
993 "Cannot get register constraints for non-register operand");
994 assert(CurRC && "Invalid initial register class");
995 if (unsigned SubIdx = MO.getSubReg()) {
996 if (OpRC)
997 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
998 else
999 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1000 } else if (OpRC)
1001 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
1002 return CurRC;
1003}
1004
1005/// Return the number of instructions inside the MI bundle, not counting the
1006/// header instruction.
1009 unsigned Size = 0;
1010 while (I->isBundledWithSucc()) {
1011 ++Size;
1012 ++I;
1013 }
1014 return Size;
1015}
1016
1017/// Returns true if the MachineInstr has an implicit-use operand of exactly
1018/// the given register (not considering sub/super-registers).
1020 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1021 const MachineOperand &MO = getOperand(i);
1022 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
1023 return true;
1024 }
1025 return false;
1026}
1027
1028/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1029/// the specific register or -1 if it is not found. It further tightens
1030/// the search criteria to a use that kills the register if isKill is true.
1032 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
1033 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1034 const MachineOperand &MO = getOperand(i);
1035 if (!MO.isReg() || !MO.isUse())
1036 continue;
1037 Register MOReg = MO.getReg();
1038 if (!MOReg)
1039 continue;
1040 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
1041 if (!isKill || MO.isKill())
1042 return i;
1043 }
1044 return -1;
1045}
1046
1047/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1048/// indicating if this instruction reads or writes Reg. This also considers
1049/// partial defines.
1050std::pair<bool,bool>
1052 SmallVectorImpl<unsigned> *Ops) const {
1053 bool PartDef = false; // Partial redefine.
1054 bool FullDef = false; // Full define.
1055 bool Use = false;
1056
1057 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1058 const MachineOperand &MO = getOperand(i);
1059 if (!MO.isReg() || MO.getReg() != Reg)
1060 continue;
1061 if (Ops)
1062 Ops->push_back(i);
1063 if (MO.isUse())
1064 Use |= !MO.isUndef();
1065 else if (MO.getSubReg() && !MO.isUndef())
1066 // A partial def undef doesn't count as reading the register.
1067 PartDef = true;
1068 else
1069 FullDef = true;
1070 }
1071 // A partial redefine uses Reg unless there is also a full define.
1072 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1073}
1074
1075/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1076/// the specified register or -1 if it is not found. If isDead is true, defs
1077/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1078/// also checks if there is a def of a super-register.
1079int
1081 const TargetRegisterInfo *TRI) const {
1082 bool isPhys = Reg.isPhysical();
1083 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1084 const MachineOperand &MO = getOperand(i);
1085 // Accept regmask operands when Overlap is set.
1086 // Ignore them when looking for a specific def operand (Overlap == false).
1087 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1088 return i;
1089 if (!MO.isReg() || !MO.isDef())
1090 continue;
1091 Register MOReg = MO.getReg();
1092 bool Found = (MOReg == Reg);
1093 if (!Found && TRI && isPhys && MOReg.isPhysical()) {
1094 if (Overlap)
1095 Found = TRI->regsOverlap(MOReg, Reg);
1096 else
1097 Found = TRI->isSubRegister(MOReg, Reg);
1098 }
1099 if (Found && (!isDead || MO.isDead()))
1100 return i;
1101 }
1102 return -1;
1103}
1104
1105/// findFirstPredOperandIdx() - Find the index of the first operand in the
1106/// operand list that is used to represent the predicate. It returns -1 if
1107/// none is found.
1109 // Don't call MCID.findFirstPredOperandIdx() because this variant
1110 // is sometimes called on an instruction that's not yet complete, and
1111 // so the number of operands is less than the MCID indicates. In
1112 // particular, the PTX target does this.
1113 const MCInstrDesc &MCID = getDesc();
1114 if (MCID.isPredicable()) {
1115 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1116 if (MCID.operands()[i].isPredicate())
1117 return i;
1118 }
1119
1120 return -1;
1121}
1122
1123// MachineOperand::TiedTo is 4 bits wide.
1124const unsigned TiedMax = 15;
1125
1126/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1127///
1128/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1129/// field. TiedTo can have these values:
1130///
1131/// 0: Operand is not tied to anything.
1132/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1133/// TiedMax: Tied to an operand >= TiedMax-1.
1134///
1135/// The tied def must be one of the first TiedMax operands on a normal
1136/// instruction. INLINEASM instructions allow more tied defs.
1137///
1138void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1139 MachineOperand &DefMO = getOperand(DefIdx);
1140 MachineOperand &UseMO = getOperand(UseIdx);
1141 assert(DefMO.isDef() && "DefIdx must be a def operand");
1142 assert(UseMO.isUse() && "UseIdx must be a use operand");
1143 assert(!DefMO.isTied() && "Def is already tied to another use");
1144 assert(!UseMO.isTied() && "Use is already tied to another def");
1145
1146 if (DefIdx < TiedMax)
1147 UseMO.TiedTo = DefIdx + 1;
1148 else {
1149 // Inline asm can use the group descriptors to find tied operands,
1150 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1151 // but on normal instruction, the tied def must be within the first TiedMax
1152 // operands.
1153 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
1154 "DefIdx out of range");
1155 UseMO.TiedTo = TiedMax;
1156 }
1157
1158 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1159 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1160}
1161
1162/// Given the index of a tied register operand, find the operand it is tied to.
1163/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1164/// which must exist.
1165unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1166 const MachineOperand &MO = getOperand(OpIdx);
1167 assert(MO.isTied() && "Operand isn't tied");
1168
1169 // Normally TiedTo is in range.
1170 if (MO.TiedTo < TiedMax)
1171 return MO.TiedTo - 1;
1172
1173 // Uses on normal instructions can be out of range.
1174 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1175 // Normal tied defs must be in the 0..TiedMax-1 range.
1176 if (MO.isUse())
1177 return TiedMax - 1;
1178 // MO is a def. Search for the tied use.
1179 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1180 const MachineOperand &UseMO = getOperand(i);
1181 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1182 return i;
1183 }
1184 llvm_unreachable("Can't find tied use");
1185 }
1186
1187 if (getOpcode() == TargetOpcode::STATEPOINT) {
1188 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1189 // on registers.
1190 StatepointOpers SO(this);
1191 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1192 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied");
1193 unsigned NumDefs = getNumDefs();
1194 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1195 while (!getOperand(CurUseIdx).isReg())
1196 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1197 if (OpIdx == CurDefIdx)
1198 return CurUseIdx;
1199 if (OpIdx == CurUseIdx)
1200 return CurDefIdx;
1201 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1202 }
1203 llvm_unreachable("Can't find tied use");
1204 }
1205
1206 // Now deal with inline asm by parsing the operand group descriptor flags.
1207 // Find the beginning of each operand group.
1208 SmallVector<unsigned, 8> GroupIdx;
1209 unsigned OpIdxGroup = ~0u;
1210 unsigned NumOps;
1211 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1212 i += NumOps) {
1213 const MachineOperand &FlagMO = getOperand(i);
1214 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1215 unsigned CurGroup = GroupIdx.size();
1216 GroupIdx.push_back(i);
1217 const InlineAsm::Flag F(FlagMO.getImm());
1218 NumOps = 1 + F.getNumOperandRegisters();
1219 // OpIdx belongs to this operand group.
1220 if (OpIdx > i && OpIdx < i + NumOps)
1221 OpIdxGroup = CurGroup;
1222 unsigned TiedGroup;
1223 if (!F.isUseOperandTiedToDef(TiedGroup))
1224 continue;
1225 // Operands in this group are tied to operands in TiedGroup which must be
1226 // earlier. Find the number of operands between the two groups.
1227 unsigned Delta = i - GroupIdx[TiedGroup];
1228
1229 // OpIdx is a use tied to TiedGroup.
1230 if (OpIdxGroup == CurGroup)
1231 return OpIdx - Delta;
1232
1233 // OpIdx is a def tied to this use group.
1234 if (OpIdxGroup == TiedGroup)
1235 return OpIdx + Delta;
1236 }
1237 llvm_unreachable("Invalid tied operand on inline asm");
1238}
1239
1240/// clearKillInfo - Clears kill flags on all operands.
1241///
1243 for (MachineOperand &MO : operands()) {
1244 if (MO.isReg() && MO.isUse())
1245 MO.setIsKill(false);
1246 }
1247}
1248
1250 unsigned SubIdx,
1251 const TargetRegisterInfo &RegInfo) {
1252 if (ToReg.isPhysical()) {
1253 if (SubIdx)
1254 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1255 for (MachineOperand &MO : operands()) {
1256 if (!MO.isReg() || MO.getReg() != FromReg)
1257 continue;
1258 MO.substPhysReg(ToReg, RegInfo);
1259 }
1260 } else {
1261 for (MachineOperand &MO : operands()) {
1262 if (!MO.isReg() || MO.getReg() != FromReg)
1263 continue;
1264 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1265 }
1266 }
1267}
1268
1269/// isSafeToMove - Return true if it is safe to move this instruction. If
1270/// SawStore is set to true, it means that there is a store (or call) between
1271/// the instruction's location and its intended destination.
1272bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1273 // Ignore stuff that we obviously can't move.
1274 //
1275 // Treat volatile loads as stores. This is not strictly necessary for
1276 // volatiles, but it is required for atomic loads. It is not allowed to move
1277 // a load across an atomic load with Ordering > Monotonic.
1278 if (mayStore() || isCall() || isPHI() ||
1279 (mayLoad() && hasOrderedMemoryRef())) {
1280 SawStore = true;
1281 return false;
1282 }
1283
1284 if (isPosition() || isDebugInstr() || isTerminator() ||
1287 return false;
1288
1289 // See if this instruction does a load. If so, we have to guarantee that the
1290 // loaded value doesn't change between the load and the its intended
1291 // destination. The check for isInvariantLoad gives the target the chance to
1292 // classify the load as always returning a constant, e.g. a constant pool
1293 // load.
1295 // Otherwise, this is a real load. If there is a store between the load and
1296 // end of block, we can't move it.
1297 return !SawStore;
1298
1299 return true;
1300}
1301
1303 bool UseTBAA, const MachineMemOperand *MMOa,
1304 const MachineMemOperand *MMOb) {
1305 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1306 // operates with MachineMemOperand offset with some important assumptions:
1307 // - LLVM fundamentally assumes flat address spaces.
1308 // - MachineOperand offset can *only* result from legalization and cannot
1309 // affect queries other than the trivial case of overlap checking.
1310 // - These offsets never wrap and never step outside of allocated objects.
1311 // - There should never be any negative offsets here.
1312 //
1313 // FIXME: Modify API to hide this math from "user"
1314 // Even before we go to AA we can reason locally about some memory objects. It
1315 // can save compile time, and possibly catch some corner cases not currently
1316 // covered.
1317
1318 int64_t OffsetA = MMOa->getOffset();
1319 int64_t OffsetB = MMOb->getOffset();
1320 int64_t MinOffset = std::min(OffsetA, OffsetB);
1321
1322 LocationSize WidthA = MMOa->getSize();
1323 LocationSize WidthB = MMOb->getSize();
1324 bool KnownWidthA = WidthA.hasValue();
1325 bool KnownWidthB = WidthB.hasValue();
1326 bool BothMMONonScalable = !WidthA.isScalable() && !WidthB.isScalable();
1327
1328 const Value *ValA = MMOa->getValue();
1329 const Value *ValB = MMOb->getValue();
1330 bool SameVal = (ValA && ValB && (ValA == ValB));
1331 if (!SameVal) {
1332 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1333 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1334 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1335 return false;
1336 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1337 return false;
1338 if (PSVa && PSVb && (PSVa == PSVb))
1339 SameVal = true;
1340 }
1341
1342 if (SameVal && BothMMONonScalable) {
1343 if (!KnownWidthA || !KnownWidthB)
1344 return true;
1345 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1346 int64_t LowWidth = (MinOffset == OffsetA)
1347 ? WidthA.getValue().getKnownMinValue()
1348 : WidthB.getValue().getKnownMinValue();
1349 return (MinOffset + LowWidth > MaxOffset);
1350 }
1351
1352 if (!AA)
1353 return true;
1354
1355 if (!ValA || !ValB)
1356 return true;
1357
1358 assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
1359 assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
1360
1361 // If Scalable Location Size has non-zero offset, Width + Offset does not work
1362 // at the moment
1363 if ((WidthA.isScalable() && OffsetA > 0) ||
1364 (WidthB.isScalable() && OffsetB > 0))
1365 return true;
1366
1367 int64_t OverlapA =
1368 KnownWidthA ? WidthA.getValue().getKnownMinValue() + OffsetA - MinOffset
1370 int64_t OverlapB =
1371 KnownWidthB ? WidthB.getValue().getKnownMinValue() + OffsetB - MinOffset
1373
1374 LocationSize LocA = (WidthA.isScalable() || !KnownWidthA)
1375 ? WidthA
1376 : LocationSize::precise(OverlapA);
1377 LocationSize LocB = (WidthB.isScalable() || !KnownWidthB)
1378 ? WidthB
1379 : LocationSize::precise(OverlapB);
1380
1381 return !AA->isNoAlias(
1382 MemoryLocation(ValA, LocA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1383 MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1384}
1385
1387 bool UseTBAA) const {
1388 const MachineFunction *MF = getMF();
1390 const MachineFrameInfo &MFI = MF->getFrameInfo();
1391
1392 // Exclude call instruction which may alter the memory but can not be handled
1393 // by this function.
1394 if (isCall() || Other.isCall())
1395 return true;
1396
1397 // If neither instruction stores to memory, they can't alias in any
1398 // meaningful way, even if they read from the same address.
1399 if (!mayStore() && !Other.mayStore())
1400 return false;
1401
1402 // Both instructions must be memory operations to be able to alias.
1403 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1404 return false;
1405
1406 // Let the target decide if memory accesses cannot possibly overlap.
1408 return false;
1409
1410 // Memory operations without memory operands may access anything. Be
1411 // conservative and assume `MayAlias`.
1412 if (memoperands_empty() || Other.memoperands_empty())
1413 return true;
1414
1415 // Skip if there are too many memory operands.
1416 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1417 if (NumChecks > TII->getMemOperandAACheckLimit())
1418 return true;
1419
1420 // Check each pair of memory operands from both instructions, which can't
1421 // alias only if all pairs won't alias.
1422 for (auto *MMOa : memoperands())
1423 for (auto *MMOb : Other.memoperands())
1424 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1425 return true;
1426
1427 return false;
1428}
1429
1430/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1431/// or volatile memory reference, or if the information describing the memory
1432/// reference is not available. Return false if it is known to have no ordered
1433/// memory references.
1435 // An instruction known never to access memory won't have a volatile access.
1436 if (!mayStore() &&
1437 !mayLoad() &&
1438 !isCall() &&
1440 return false;
1441
1442 // Otherwise, if the instruction has no memory reference information,
1443 // conservatively assume it wasn't preserved.
1444 if (memoperands_empty())
1445 return true;
1446
1447 // Check if any of our memory operands are ordered.
1448 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1449 return !MMO->isUnordered();
1450 });
1451}
1452
1453/// isDereferenceableInvariantLoad - Return true if this instruction will never
1454/// trap and is loading from a location whose value is invariant across a run of
1455/// this function.
1457 // If the instruction doesn't load at all, it isn't an invariant load.
1458 if (!mayLoad())
1459 return false;
1460
1461 // If the instruction has lost its memoperands, conservatively assume that
1462 // it may not be an invariant load.
1463 if (memoperands_empty())
1464 return false;
1465
1466 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1467
1468 for (MachineMemOperand *MMO : memoperands()) {
1469 if (!MMO->isUnordered())
1470 // If the memory operand has ordering side effects, we can't move the
1471 // instruction. Such an instruction is technically an invariant load,
1472 // but the caller code would need updated to expect that.
1473 return false;
1474 if (MMO->isStore()) return false;
1475 if (MMO->isInvariant() && MMO->isDereferenceable())
1476 continue;
1477
1478 // A load from a constant PseudoSourceValue is invariant.
1479 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1480 if (PSV->isConstant(&MFI))
1481 continue;
1482 }
1483
1484 // Otherwise assume conservatively.
1485 return false;
1486 }
1487
1488 // Everything checks out.
1489 return true;
1490}
1491
1492/// isConstantValuePHI - If the specified instruction is a PHI that always
1493/// merges together the same virtual register, return the register, otherwise
1494/// return 0.
1496 if (!isPHI())
1497 return 0;
1498 assert(getNumOperands() >= 3 &&
1499 "It's illegal to have a PHI without source operands");
1500
1501 Register Reg = getOperand(1).getReg();
1502 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1503 if (getOperand(i).getReg() != Reg)
1504 return 0;
1505 return Reg;
1506}
1507
1510 return true;
1511 if (isInlineAsm()) {
1512 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1513 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1514 return true;
1515 }
1516
1517 return false;
1518}
1519
1521 return mayStore() || isCall() ||
1523}
1524
1525/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1526///
1528 for (const MachineOperand &MO : operands()) {
1529 if (!MO.isReg() || MO.isUse())
1530 continue;
1531 if (!MO.isDead())
1532 return false;
1533 }
1534 return true;
1535}
1536
1538 for (const MachineOperand &MO : implicit_operands()) {
1539 if (!MO.isReg() || MO.isUse())
1540 continue;
1541 if (!MO.isDead())
1542 return false;
1543 }
1544 return true;
1545}
1546
1547/// copyImplicitOps - Copy implicit register operands from specified
1548/// instruction to this instruction.
1550 const MachineInstr &MI) {
1551 for (const MachineOperand &MO :
1552 llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))
1553 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1554 addOperand(MF, MO);
1555}
1556
1558 const MCInstrDesc &MCID = getDesc();
1559 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1560 return true;
1561 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1562 const auto &Operand = getOperand(I);
1563 if (!Operand.isReg() || Operand.isDef())
1564 // Ignore the defined registers as MCID marks only the uses as tied.
1565 continue;
1566 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1567 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1568 if (ExpectedTiedIdx != TiedIdx)
1569 return true;
1570 }
1571 return false;
1572}
1573
1575 const MachineRegisterInfo &MRI) const {
1576 const MachineOperand &Op = getOperand(OpIdx);
1577 if (!Op.isReg())
1578 return LLT{};
1579
1580 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1581 return MRI.getType(Op.getReg());
1582
1583 auto &OpInfo = getDesc().operands()[OpIdx];
1584 if (!OpInfo.isGenericType())
1585 return MRI.getType(Op.getReg());
1586
1587 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1588 return LLT{};
1589
1590 LLT TypeToPrint = MRI.getType(Op.getReg());
1591 // Don't mark the type index printed if it wasn't actually printed: maybe
1592 // another operand with the same type index has an actual type attached:
1593 if (TypeToPrint.isValid())
1594 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1595 return TypeToPrint;
1596}
1597
1598#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1600 dbgs() << " ";
1601 print(dbgs());
1602}
1603
1604LLVM_DUMP_METHOD void MachineInstr::dumprImpl(
1605 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1606 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1607 if (Depth >= MaxDepth)
1608 return;
1609 if (!AlreadySeenInstrs.insert(this).second)
1610 return;
1611 // PadToColumn always inserts at least one space.
1612 // Don't mess up the alignment if we don't want any space.
1613 if (Depth)
1614 fdbgs().PadToColumn(Depth * 2);
1615 print(fdbgs());
1616 for (const MachineOperand &MO : operands()) {
1617 if (!MO.isReg() || MO.isDef())
1618 continue;
1619 Register Reg = MO.getReg();
1620 if (Reg.isPhysical())
1621 continue;
1622 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1623 if (NewMI == nullptr)
1624 continue;
1625 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1626 }
1627}
1628
1630 unsigned MaxDepth) const {
1631 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1632 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1633}
1634#endif
1635
1636void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1637 bool SkipDebugLoc, bool AddNewLine,
1638 const TargetInstrInfo *TII) const {
1639 const Module *M = nullptr;
1640 const Function *F = nullptr;
1641 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1642 F = &MF->getFunction();
1643 M = F->getParent();
1644 if (!TII)
1645 TII = MF->getSubtarget().getInstrInfo();
1646 }
1647
1648 ModuleSlotTracker MST(M);
1649 if (F)
1650 MST.incorporateFunction(*F);
1651 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1652}
1653
1655 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1656 bool AddNewLine, const TargetInstrInfo *TII) const {
1657 // We can be a bit tidier if we know the MachineFunction.
1658 const TargetRegisterInfo *TRI = nullptr;
1659 const MachineRegisterInfo *MRI = nullptr;
1660 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1661 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1662
1663 if (isCFIInstruction())
1664 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
1665
1666 SmallBitVector PrintedTypes(8);
1667 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1668 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1669 if (!ShouldPrintRegisterTies)
1670 return 0U;
1671 const MachineOperand &MO = getOperand(OpIdx);
1672 if (MO.isReg() && MO.isTied() && !MO.isDef())
1673 return findTiedOperandIdx(OpIdx);
1674 return 0U;
1675 };
1676 unsigned StartOp = 0;
1677 unsigned e = getNumOperands();
1678
1679 // Print explicitly defined operands on the left of an assignment syntax.
1680 while (StartOp < e) {
1681 const MachineOperand &MO = getOperand(StartOp);
1682 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1683 break;
1684
1685 if (StartOp != 0)
1686 OS << ", ";
1687
1688 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1689 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1690 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1691 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1692 ++StartOp;
1693 }
1694
1695 if (StartOp != 0)
1696 OS << " = ";
1697
1699 OS << "frame-setup ";
1701 OS << "frame-destroy ";
1703 OS << "nnan ";
1705 OS << "ninf ";
1707 OS << "nsz ";
1709 OS << "arcp ";
1711 OS << "contract ";
1713 OS << "afn ";
1715 OS << "reassoc ";
1717 OS << "nuw ";
1719 OS << "nsw ";
1721 OS << "exact ";
1723 OS << "nofpexcept ";
1725 OS << "nomerge ";
1727 OS << "nneg ";
1729 OS << "disjoint ";
1730
1731 // Print the opcode name.
1732 if (TII)
1733 OS << TII->getName(getOpcode());
1734 else
1735 OS << "UNKNOWN";
1736
1737 if (SkipOpers)
1738 return;
1739
1740 // Print the rest of the operands.
1741 bool FirstOp = true;
1742 unsigned AsmDescOp = ~0u;
1743 unsigned AsmOpCount = 0;
1744
1746 // Print asm string.
1747 OS << " ";
1748 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1749 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1750 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1751 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1752 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1753 IntrinsicInfo);
1754
1755 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1756 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1757 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1758 OS << " [sideeffect]";
1759 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1760 OS << " [mayload]";
1761 if (ExtraInfo & InlineAsm::Extra_MayStore)
1762 OS << " [maystore]";
1763 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1764 OS << " [isconvergent]";
1765 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1766 OS << " [alignstack]";
1768 OS << " [attdialect]";
1770 OS << " [inteldialect]";
1771
1772 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1773 FirstOp = false;
1774 }
1775
1776 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1777 const MachineOperand &MO = getOperand(i);
1778
1779 if (FirstOp) FirstOp = false; else OS << ",";
1780 OS << " ";
1781
1782 if (isDebugValueLike() && MO.isMetadata()) {
1783 // Pretty print DBG_VALUE* instructions.
1784 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1785 if (DIV && !DIV->getName().empty())
1786 OS << "!\"" << DIV->getName() << '\"';
1787 else {
1788 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1789 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1790 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1791 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1792 }
1793 } else if (isDebugLabel() && MO.isMetadata()) {
1794 // Pretty print DBG_LABEL instructions.
1795 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1796 if (DIL && !DIL->getName().empty())
1797 OS << "\"" << DIL->getName() << '\"';
1798 else {
1799 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1800 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1801 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1802 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1803 }
1804 } else if (i == AsmDescOp && MO.isImm()) {
1805 // Pretty print the inline asm operand descriptor.
1806 OS << '$' << AsmOpCount++;
1807 unsigned Flag = MO.getImm();
1808 const InlineAsm::Flag F(Flag);
1809 OS << ":[";
1810 OS << F.getKindName();
1811
1812 unsigned RCID;
1813 if (!F.isImmKind() && !F.isMemKind() && F.hasRegClassConstraint(RCID)) {
1814 if (TRI) {
1815 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1816 } else
1817 OS << ":RC" << RCID;
1818 }
1819
1820 if (F.isMemKind()) {
1821 const InlineAsm::ConstraintCode MCID = F.getMemoryConstraintID();
1822 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1823 }
1824
1825 unsigned TiedTo;
1826 if (F.isUseOperandTiedToDef(TiedTo))
1827 OS << " tiedto:$" << TiedTo;
1828
1829 if ((F.isRegDefKind() || F.isRegDefEarlyClobberKind() ||
1830 F.isRegUseKind()) &&
1831 F.getRegMayBeFolded()) {
1832 OS << " foldable";
1833 }
1834
1835 OS << ']';
1836
1837 // Compute the index of the next operand descriptor.
1838 AsmDescOp += 1 + F.getNumOperandRegisters();
1839 } else {
1840 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1841 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1842 if (MO.isImm() && isOperandSubregIdx(i))
1844 else
1845 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1846 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1847 }
1848 }
1849
1850 // Print any optional symbols attached to this instruction as-if they were
1851 // operands.
1852 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1853 if (!FirstOp) {
1854 FirstOp = false;
1855 OS << ',';
1856 }
1857 OS << " pre-instr-symbol ";
1858 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1859 }
1860 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1861 if (!FirstOp) {
1862 FirstOp = false;
1863 OS << ',';
1864 }
1865 OS << " post-instr-symbol ";
1866 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1867 }
1868 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1869 if (!FirstOp) {
1870 FirstOp = false;
1871 OS << ',';
1872 }
1873 OS << " heap-alloc-marker ";
1874 HeapAllocMarker->printAsOperand(OS, MST);
1875 }
1876 if (MDNode *PCSections = getPCSections()) {
1877 if (!FirstOp) {
1878 FirstOp = false;
1879 OS << ',';
1880 }
1881 OS << " pcsections ";
1882 PCSections->printAsOperand(OS, MST);
1883 }
1884 if (uint32_t CFIType = getCFIType()) {
1885 if (!FirstOp)
1886 OS << ',';
1887 OS << " cfi-type " << CFIType;
1888 }
1889
1890 if (DebugInstrNum) {
1891 if (!FirstOp)
1892 OS << ",";
1893 OS << " debug-instr-number " << DebugInstrNum;
1894 }
1895
1896 if (!SkipDebugLoc) {
1897 if (const DebugLoc &DL = getDebugLoc()) {
1898 if (!FirstOp)
1899 OS << ',';
1900 OS << " debug-location ";
1901 DL->printAsOperand(OS, MST);
1902 }
1903 }
1904
1905 if (!memoperands_empty()) {
1907 const LLVMContext *Context = nullptr;
1908 std::unique_ptr<LLVMContext> CtxPtr;
1909 const MachineFrameInfo *MFI = nullptr;
1910 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1911 MFI = &MF->getFrameInfo();
1912 Context = &MF->getFunction().getContext();
1913 } else {
1914 CtxPtr = std::make_unique<LLVMContext>();
1915 Context = CtxPtr.get();
1916 }
1917
1918 OS << " :: ";
1919 bool NeedComma = false;
1920 for (const MachineMemOperand *Op : memoperands()) {
1921 if (NeedComma)
1922 OS << ", ";
1923 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1924 NeedComma = true;
1925 }
1926 }
1927
1928 if (SkipDebugLoc)
1929 return;
1930
1931 bool HaveSemi = false;
1932
1933 // Print debug location information.
1934 if (const DebugLoc &DL = getDebugLoc()) {
1935 if (!HaveSemi) {
1936 OS << ';';
1937 HaveSemi = true;
1938 }
1939 OS << ' ';
1940 DL.print(OS);
1941 }
1942
1943 // Print extra comments for DEBUG_VALUE and friends if they are well-formed.
1944 if ((isNonListDebugValue() && getNumOperands() >= 4) ||
1945 (isDebugValueList() && getNumOperands() >= 2) ||
1946 (isDebugRef() && getNumOperands() >= 3)) {
1947 if (getDebugVariableOp().isMetadata()) {
1948 if (!HaveSemi) {
1949 OS << ";";
1950 HaveSemi = true;
1951 }
1952 auto *DV = getDebugVariable();
1953 OS << " line no:" << DV->getLine();
1955 OS << " indirect";
1956 }
1957 }
1958 // TODO: DBG_LABEL
1959
1960 if (AddNewLine)
1961 OS << '\n';
1962}
1963
1965 const TargetRegisterInfo *RegInfo,
1966 bool AddIfNotFound) {
1967 bool isPhysReg = IncomingReg.isPhysical();
1968 bool hasAliases = isPhysReg &&
1969 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1970 bool Found = false;
1972 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1973 MachineOperand &MO = getOperand(i);
1974 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1975 continue;
1976
1977 // DEBUG_VALUE nodes do not contribute to code generation and should
1978 // always be ignored. Failure to do so may result in trying to modify
1979 // KILL flags on DEBUG_VALUE nodes.
1980 if (MO.isDebug())
1981 continue;
1982
1983 Register Reg = MO.getReg();
1984 if (!Reg)
1985 continue;
1986
1987 if (Reg == IncomingReg) {
1988 if (!Found) {
1989 if (MO.isKill())
1990 // The register is already marked kill.
1991 return true;
1992 if (isPhysReg && isRegTiedToDefOperand(i))
1993 // Two-address uses of physregs must not be marked kill.
1994 return true;
1995 MO.setIsKill();
1996 Found = true;
1997 }
1998 } else if (hasAliases && MO.isKill() && Reg.isPhysical()) {
1999 // A super-register kill already exists.
2000 if (RegInfo->isSuperRegister(IncomingReg, Reg))
2001 return true;
2002 if (RegInfo->isSubRegister(IncomingReg, Reg))
2003 DeadOps.push_back(i);
2004 }
2005 }
2006
2007 // Trim unneeded kill operands.
2008 while (!DeadOps.empty()) {
2009 unsigned OpIdx = DeadOps.back();
2010 if (getOperand(OpIdx).isImplicit() &&
2011 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2012 removeOperand(OpIdx);
2013 else
2014 getOperand(OpIdx).setIsKill(false);
2015 DeadOps.pop_back();
2016 }
2017
2018 // If not found, this means an alias of one of the operands is killed. Add a
2019 // new implicit operand if required.
2020 if (!Found && AddIfNotFound) {
2022 false /*IsDef*/,
2023 true /*IsImp*/,
2024 true /*IsKill*/));
2025 return true;
2026 }
2027 return Found;
2028}
2029
2031 const TargetRegisterInfo *RegInfo) {
2032 if (!Reg.isPhysical())
2033 RegInfo = nullptr;
2034 for (MachineOperand &MO : operands()) {
2035 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
2036 continue;
2037 Register OpReg = MO.getReg();
2038 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
2039 MO.setIsKill(false);
2040 }
2041}
2042
2044 const TargetRegisterInfo *RegInfo,
2045 bool AddIfNotFound) {
2046 bool isPhysReg = Reg.isPhysical();
2047 bool hasAliases = isPhysReg &&
2048 MCRegAliasIterator(Reg, RegInfo, false).isValid();
2049 bool Found = false;
2051 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
2052 MachineOperand &MO = getOperand(i);
2053 if (!MO.isReg() || !MO.isDef())
2054 continue;
2055 Register MOReg = MO.getReg();
2056 if (!MOReg)
2057 continue;
2058
2059 if (MOReg == Reg) {
2060 MO.setIsDead();
2061 Found = true;
2062 } else if (hasAliases && MO.isDead() && MOReg.isPhysical()) {
2063 // There exists a super-register that's marked dead.
2064 if (RegInfo->isSuperRegister(Reg, MOReg))
2065 return true;
2066 if (RegInfo->isSubRegister(Reg, MOReg))
2067 DeadOps.push_back(i);
2068 }
2069 }
2070
2071 // Trim unneeded dead operands.
2072 while (!DeadOps.empty()) {
2073 unsigned OpIdx = DeadOps.back();
2074 if (getOperand(OpIdx).isImplicit() &&
2075 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
2076 removeOperand(OpIdx);
2077 else
2078 getOperand(OpIdx).setIsDead(false);
2079 DeadOps.pop_back();
2080 }
2081
2082 // If not found, this means an alias of one of the operands is dead. Add a
2083 // new implicit operand if required.
2084 if (Found || !AddIfNotFound)
2085 return Found;
2086
2088 true /*IsDef*/,
2089 true /*IsImp*/,
2090 false /*IsKill*/,
2091 true /*IsDead*/));
2092 return true;
2093}
2094
2096 for (MachineOperand &MO : operands()) {
2097 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2098 continue;
2099 MO.setIsDead(false);
2100 }
2101}
2102
2104 for (MachineOperand &MO : operands()) {
2105 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2106 continue;
2107 MO.setIsUndef(IsUndef);
2108 }
2109}
2110
2112 const TargetRegisterInfo *RegInfo) {
2113 if (Reg.isPhysical()) {
2114 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2115 if (MO)
2116 return;
2117 } else {
2118 for (const MachineOperand &MO : operands()) {
2119 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2120 MO.getSubReg() == 0)
2121 return;
2122 }
2123 }
2125 true /*IsDef*/,
2126 true /*IsImp*/));
2127}
2128
2130 const TargetRegisterInfo &TRI) {
2131 bool HasRegMask = false;
2132 for (MachineOperand &MO : operands()) {
2133 if (MO.isRegMask()) {
2134 HasRegMask = true;
2135 continue;
2136 }
2137 if (!MO.isReg() || !MO.isDef()) continue;
2138 Register Reg = MO.getReg();
2139 if (!Reg.isPhysical())
2140 continue;
2141 // If there are no uses, including partial uses, the def is dead.
2142 if (llvm::none_of(UsedRegs,
2143 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2144 MO.setIsDead();
2145 }
2146
2147 // This is a call with a register mask operand.
2148 // Mask clobbers are always dead, so add defs for the non-dead defines.
2149 if (HasRegMask)
2150 for (const Register &UsedReg : UsedRegs)
2151 addRegisterDefined(UsedReg, &TRI);
2152}
2153
2154unsigned
2156 // Build up a buffer of hash code components.
2157 SmallVector<size_t, 16> HashComponents;
2158 HashComponents.reserve(MI->getNumOperands() + 1);
2159 HashComponents.push_back(MI->getOpcode());
2160 for (const MachineOperand &MO : MI->operands()) {
2161 if (MO.isReg() && MO.isDef() && MO.getReg().isVirtual())
2162 continue; // Skip virtual register defs.
2163
2164 HashComponents.push_back(hash_value(MO));
2165 }
2166 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2167}
2168
2170 // Find the source location cookie.
2171 uint64_t LocCookie = 0;
2172 const MDNode *LocMD = nullptr;
2173 for (unsigned i = getNumOperands(); i != 0; --i) {
2174 if (getOperand(i-1).isMetadata() &&
2175 (LocMD = getOperand(i-1).getMetadata()) &&
2176 LocMD->getNumOperands() != 0) {
2177 if (const ConstantInt *CI =
2178 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2179 LocCookie = CI->getZExtValue();
2180 break;
2181 }
2182 }
2183 }
2184
2185 if (const MachineBasicBlock *MBB = getParent())
2186 if (const MachineFunction *MF = MBB->getParent())
2187 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2188 report_fatal_error(Msg);
2189}
2190
2192 const MCInstrDesc &MCID, bool IsIndirect,
2193 Register Reg, const MDNode *Variable,
2194 const MDNode *Expr) {
2195 assert(isa<DILocalVariable>(Variable) && "not a variable");
2196 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2197 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2198 "Expected inlined-at fields to agree");
2199 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2200 if (IsIndirect)
2201 MIB.addImm(0U);
2202 else
2203 MIB.addReg(0U);
2204 return MIB.addMetadata(Variable).addMetadata(Expr);
2205}
2206
2208 const MCInstrDesc &MCID, bool IsIndirect,
2209 ArrayRef<MachineOperand> DebugOps,
2210 const MDNode *Variable, const MDNode *Expr) {
2211 assert(isa<DILocalVariable>(Variable) && "not a variable");
2212 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
2213 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
2214 "Expected inlined-at fields to agree");
2215 if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
2216 assert(DebugOps.size() == 1 &&
2217 "DBG_VALUE must contain exactly one debug operand");
2218 MachineOperand DebugOp = DebugOps[0];
2219 if (DebugOp.isReg())
2220 return BuildMI(MF, DL, MCID, IsIndirect, DebugOp.getReg(), Variable,
2221 Expr);
2222
2223 auto MIB = BuildMI(MF, DL, MCID).add(DebugOp);
2224 if (IsIndirect)
2225 MIB.addImm(0U);
2226 else
2227 MIB.addReg(0U);
2228 return MIB.addMetadata(Variable).addMetadata(Expr);
2229 }
2230
2231 auto MIB = BuildMI(MF, DL, MCID);
2232 MIB.addMetadata(Variable).addMetadata(Expr);
2233 for (const MachineOperand &DebugOp : DebugOps)
2234 if (DebugOp.isReg())
2235 MIB.addReg(DebugOp.getReg());
2236 else
2237 MIB.add(DebugOp);
2238 return MIB;
2239}
2240
2243 const DebugLoc &DL, const MCInstrDesc &MCID,
2244 bool IsIndirect, Register Reg,
2245 const MDNode *Variable, const MDNode *Expr) {
2246 MachineFunction &MF = *BB.getParent();
2247 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2248 BB.insert(I, MI);
2249 return MachineInstrBuilder(MF, MI);
2250}
2251
2254 const DebugLoc &DL, const MCInstrDesc &MCID,
2255 bool IsIndirect,
2256 ArrayRef<MachineOperand> DebugOps,
2257 const MDNode *Variable, const MDNode *Expr) {
2258 MachineFunction &MF = *BB.getParent();
2259 MachineInstr *MI =
2260 BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);
2261 BB.insert(I, MI);
2262 return MachineInstrBuilder(MF, *MI);
2263}
2264
2265/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2266/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2267static const DIExpression *
2269 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2270 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&
2271 "Expected inlined-at fields to agree");
2272
2273 const DIExpression *Expr = MI.getDebugExpression();
2274 if (MI.isIndirectDebugValue()) {
2275 assert(MI.getDebugOffset().getImm() == 0 &&
2276 "DBG_VALUE with nonzero offset");
2278 } else if (MI.isDebugValueList()) {
2279 // We will replace the spilled register with a frame index, so
2280 // immediately deref all references to the spilled register.
2281 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2282 for (const MachineOperand *Op : SpilledOperands) {
2283 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2284 Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2285 }
2286 }
2287 return Expr;
2288}
2290 Register SpillReg) {
2291 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.");
2293 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2294 SpillOperands.push_back(&Op);
2295 return computeExprForSpill(MI, SpillOperands);
2296}
2297
2300 const MachineInstr &Orig,
2301 int FrameIndex, Register SpillReg) {
2302 assert(!Orig.isDebugRef() &&
2303 "DBG_INSTR_REF should not reference a virtual register.");
2304 const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2305 MachineInstrBuilder NewMI =
2306 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2307 // Non-Variadic Operands: Location, Offset, Variable, Expression
2308 // Variadic Operands: Variable, Expression, Locations...
2309 if (Orig.isNonListDebugValue())
2310 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2311 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2312 if (Orig.isDebugValueList()) {
2313 for (const MachineOperand &Op : Orig.debug_operands())
2314 if (Op.isReg() && Op.getReg() == SpillReg)
2315 NewMI.addFrameIndex(FrameIndex);
2316 else
2317 NewMI.add(MachineOperand(Op));
2318 }
2319 return NewMI;
2320}
2323 const MachineInstr &Orig, int FrameIndex,
2324 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2325 const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2326 MachineInstrBuilder NewMI =
2327 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2328 // Non-Variadic Operands: Location, Offset, Variable, Expression
2329 // Variadic Operands: Variable, Expression, Locations...
2330 if (Orig.isNonListDebugValue())
2331 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2332 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2333 if (Orig.isDebugValueList()) {
2334 for (const MachineOperand &Op : Orig.debug_operands())
2335 if (is_contained(SpilledOperands, &Op))
2336 NewMI.addFrameIndex(FrameIndex);
2337 else
2338 NewMI.add(MachineOperand(Op));
2339 }
2340 return NewMI;
2341}
2342
2344 Register Reg) {
2345 const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2346 if (Orig.isNonListDebugValue())
2348 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2349 Op.ChangeToFrameIndex(FrameIndex);
2350 Orig.getDebugExpressionOp().setMetadata(Expr);
2351}
2352
2355 MachineInstr &MI = *this;
2356 if (!MI.getOperand(0).isReg())
2357 return;
2358
2360 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2361 DI != DE; ++DI) {
2362 if (!DI->isDebugValue())
2363 return;
2364 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2365 DbgValues.push_back(&*DI);
2366 }
2367}
2368
2370 // Collect matching debug values.
2372
2373 if (!getOperand(0).isReg())
2374 return;
2375
2376 Register DefReg = getOperand(0).getReg();
2377 auto *MRI = getRegInfo();
2378 for (auto &MO : MRI->use_operands(DefReg)) {
2379 auto *DI = MO.getParent();
2380 if (!DI->isDebugValue())
2381 continue;
2382 if (DI->hasDebugOperandForReg(DefReg)) {
2383 DbgValues.push_back(DI);
2384 }
2385 }
2386
2387 // Propagate Reg to debug value instructions.
2388 for (auto *DBI : DbgValues)
2389 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2390 Op.setReg(Reg);
2391}
2392
2394
2396 const MachineFrameInfo &MFI) {
2397 uint64_t Size = 0;
2398 for (const auto *A : Accesses) {
2399 if (MFI.isSpillSlotObjectIndex(
2400 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2401 ->getFrameIndex())) {
2402 LocationSize S = A->getSize();
2403 if (!S.hasValue())
2405 Size += S.getValue();
2406 }
2407 }
2408 return Size;
2409}
2410
2411std::optional<LocationSize>
2413 int FI;
2414 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2415 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2416 if (MFI.isSpillSlotObjectIndex(FI))
2417 return (*memoperands_begin())->getSize();
2418 }
2419 return std::nullopt;
2420}
2421
2422std::optional<LocationSize>
2424 MMOList Accesses;
2425 if (TII->hasStoreToStackSlot(*this, Accesses))
2426 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2427 return std::nullopt;
2428}
2429
2430std::optional<LocationSize>
2432 int FI;
2433 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2434 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2435 if (MFI.isSpillSlotObjectIndex(FI))
2436 return (*memoperands_begin())->getSize();
2437 }
2438 return std::nullopt;
2439}
2440
2441std::optional<LocationSize>
2443 MMOList Accesses;
2444 if (TII->hasLoadFromStackSlot(*this, Accesses))
2445 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2446 return std::nullopt;
2447}
2448
2450 if (DebugInstrNum == 0)
2451 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2452 return DebugInstrNum;
2453}
2454
2456 if (DebugInstrNum == 0)
2457 DebugInstrNum = MF.getNewDebugInstrNum();
2458 return DebugInstrNum;
2459}
2460
2461std::tuple<LLT, LLT> MachineInstr::getFirst2LLTs() const {
2462 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2463 getRegInfo()->getType(getOperand(1).getReg()));
2464}
2465
2466std::tuple<LLT, LLT, LLT> MachineInstr::getFirst3LLTs() const {
2467 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2468 getRegInfo()->getType(getOperand(1).getReg()),
2469 getRegInfo()->getType(getOperand(2).getReg()));
2470}
2471
2472std::tuple<LLT, LLT, LLT, LLT> MachineInstr::getFirst4LLTs() const {
2473 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2474 getRegInfo()->getType(getOperand(1).getReg()),
2475 getRegInfo()->getType(getOperand(2).getReg()),
2476 getRegInfo()->getType(getOperand(3).getReg()));
2477}
2478
2479std::tuple<LLT, LLT, LLT, LLT, LLT> MachineInstr::getFirst5LLTs() const {
2480 return std::tuple(getRegInfo()->getType(getOperand(0).getReg()),
2481 getRegInfo()->getType(getOperand(1).getReg()),
2482 getRegInfo()->getType(getOperand(2).getReg()),
2483 getRegInfo()->getType(getOperand(3).getReg()),
2484 getRegInfo()->getType(getOperand(4).getReg()));
2485}
2486
2487std::tuple<Register, LLT, Register, LLT>
2489 Register Reg0 = getOperand(0).getReg();
2490 Register Reg1 = getOperand(1).getReg();
2491 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
2492 getRegInfo()->getType(Reg1));
2493}
2494
2495std::tuple<Register, LLT, Register, LLT, Register, LLT>
2497 Register Reg0 = getOperand(0).getReg();
2498 Register Reg1 = getOperand(1).getReg();
2499 Register Reg2 = getOperand(2).getReg();
2500 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1,
2501 getRegInfo()->getType(Reg1), Reg2,
2502 getRegInfo()->getType(Reg2));
2503}
2504
2505std::tuple<Register, LLT, Register, LLT, Register, LLT, Register, LLT>
2507 Register Reg0 = getOperand(0).getReg();
2508 Register Reg1 = getOperand(1).getReg();
2509 Register Reg2 = getOperand(2).getReg();
2510 Register Reg3 = getOperand(3).getReg();
2511 return std::tuple(
2512 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
2513 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3));
2514}
2515
2517 LLT>
2519 Register Reg0 = getOperand(0).getReg();
2520 Register Reg1 = getOperand(1).getReg();
2521 Register Reg2 = getOperand(2).getReg();
2522 Register Reg3 = getOperand(3).getReg();
2523 Register Reg4 = getOperand(4).getReg();
2524 return std::tuple(
2525 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1),
2526 Reg2, getRegInfo()->getType(Reg2), Reg3, getRegInfo()->getType(Reg3),
2527 Reg4, getRegInfo()->getType(Reg4));
2528}
2529
2532 assert(InsertBefore != nullptr && "invalid iterator");
2533 assert(InsertBefore->getParent() == this &&
2534 "iterator points to operand of other inst");
2535 if (Ops.empty())
2536 return;
2537
2538 // Do one pass to untie operands.
2540 for (const MachineOperand &MO : operands()) {
2541 if (MO.isReg() && MO.isTied()) {
2542 unsigned OpNo = getOperandNo(&MO);
2543 unsigned TiedTo = findTiedOperandIdx(OpNo);
2544 TiedOpIndices[OpNo] = TiedTo;
2545 untieRegOperand(OpNo);
2546 }
2547 }
2548
2549 unsigned OpIdx = getOperandNo(InsertBefore);
2550 unsigned NumOperands = getNumOperands();
2551 unsigned OpsToMove = NumOperands - OpIdx;
2552
2554 MovingOps.reserve(OpsToMove);
2555
2556 for (unsigned I = 0; I < OpsToMove; ++I) {
2557 MovingOps.emplace_back(getOperand(OpIdx));
2558 removeOperand(OpIdx);
2559 }
2560 for (const MachineOperand &MO : Ops)
2561 addOperand(MO);
2562 for (const MachineOperand &OpMoved : MovingOps)
2563 addOperand(OpMoved);
2564
2565 // Re-tie operands.
2566 for (auto [Tie1, Tie2] : TiedOpIndices) {
2567 if (Tie1 >= OpIdx)
2568 Tie1 += Ops.size();
2569 if (Tie2 >= OpIdx)
2570 Tie2 += Ops.size();
2571 tieOperands(Tie1, Tie2);
2572 }
2573}
2574
2575bool MachineInstr::mayFoldInlineAsmRegOp(unsigned OpId) const {
2576 assert(OpId && "expected non-zero operand id");
2577 assert(isInlineAsm() && "should only be used on inline asm");
2578
2579 if (!getOperand(OpId).isReg())
2580 return false;
2581
2582 const MachineOperand &MD = getOperand(OpId - 1);
2583 if (!MD.isImm())
2584 return false;
2585
2586 InlineAsm::Flag F(MD.getImm());
2587 if (F.isRegUseKind() || F.isRegDefKind() || F.isRegDefEarlyClobberKind())
2588 return F.getRegMayBeFolded();
2589 return false;
2590}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Definition: Compiler.h:529
This file contains the declarations for the subclasses of Constant, which represent the different fla...
uint64_t Size
#define Check(C,...)
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
static const unsigned MaxDepth
Implement a low-level type suitable for MachineInstr level instruction selection.
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
static DebugLoc getDebugLoc(MachineBasicBlock::instr_iterator FirstMI, MachineBasicBlock::instr_iterator LastMI)
Return the first found DebugLoc that has a DILocation, given a range of instructions.
const unsigned TiedMax
static void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps, MachineRegisterInfo *MRI)
Move NumOps MachineOperands from Src to Dst, with support for overlapping ranges.
static LocationSize getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI)
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA, bool UseTBAA, const MachineMemOperand *MMOa, const MachineMemOperand *MMOb)
static void tryToGetTargetInfo(const MachineInstr &MI, const TargetRegisterInfo *&TRI, const MachineRegisterInfo *&MRI, const TargetIntrinsicInfo *&IntrinsicInfo, const TargetInstrInfo *&TII)
static const DIExpression * computeExprForSpill(const MachineInstr &MI, SmallVectorImpl< const MachineOperand * > &SpilledOperands)
Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
static const MachineFunction * getMFIfAvailable(const MachineInstr &MI)
static bool hasIdenticalMMOs(ArrayRef< MachineMemOperand * > LHS, ArrayRef< MachineMemOperand * > RHS)
Check to see if the MMOs pointed to by the two MemRefs arrays are identical.
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
This file contains the declarations for metadata subclasses.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static bool isReg(const MCInst &MI, unsigned OpNo)
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
raw_pwrite_stream & OS
static cl::opt< bool > UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"))
This file implements the SmallBitVector class.
This file defines the SmallVector class.
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
Value * RHS
Value * LHS
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB)
A trivial helper function to check to see if the specified pointers are no-alias.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:165
bool empty() const
empty - Check if the array is empty.
Definition: ArrayRef.h:160
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
Definition: ArrayRef.h:195
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
This is the shared class of boolean and integer constants.
Definition: Constants.h:80
DWARF expression.
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool isEqualExpression(const DIExpression *FirstExpr, bool FirstIndirect, const DIExpression *SecondExpr, bool SecondIndirect)
Determines whether two debug values should produce equivalent DWARF expressions, using their DIExpres...
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
This class represents an Operation in the Expression.
bool print(raw_ostream &OS, DIDumpOptions DumpOpts, const DWARFExpression *Expr, DWARFUnit *U) const
A debug info location.
Definition: DebugLoc.h:33
bool hasTrivialDestructor() const
Check whether this has a trivial destructor.
Definition: DebugLoc.h:69
Utility class for floating point operations which can have information about relaxed accuracy require...
Definition: Operator.h:200
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
Definition: Function.cpp:356
bool hasStoreToStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has store to stack slots.
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override
bool hasLoadFromStackSlot(const MachineInstr &MI, SmallVectorImpl< const MachineMemOperand * > &Accesses) const override
Check if the instruction or the bundle of instructions has load from stack slots.
static StringRef getMemConstraintName(ConstraintCode C)
Definition: InlineAsm.h:467
constexpr bool isValid() const
Definition: LowLevelType.h:145
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
bool hasValue() const
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
bool isScalable() const
TypeSize getValue() const
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:248
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
ArrayRef< MCPhysReg > implicit_defs() const
Return a list of registers that are potentially written by any instance of this machine instruction.
Definition: MCInstrDesc.h:579
bool isPredicable() const
Return true if this instruction has a predicate operand that controls execution.
Definition: MCInstrDesc.h:338
unsigned short Opcode
Definition: MCInstrDesc.h:205
bool isVariadic() const
Return true if this instruction can have a variable number of operands.
Definition: MCInstrDesc.h:261
ArrayRef< MCPhysReg > implicit_uses() const
Return a list of registers that are potentially read by any instance of this machine instruction.
Definition: MCInstrDesc.h:565
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isSubRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA.
bool isSuperRegister(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA.
Wrapper class representing physical registers. Should be passed by value.
Definition: MCRegister.h:33
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
Metadata node.
Definition: Metadata.h:1067
const MDOperand & getOperand(unsigned I) const
Definition: Metadata.h:1428
unsigned getNumOperands() const
Return number of MDNode operands.
Definition: Metadata.h:1434
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstr * remove_instr(MachineInstr *I)
Remove the possibly bundled instruction from the instruction list without deleting it.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
instr_iterator erase_instr(MachineInstr *I)
Remove an instruction from the instruction list and delete it.
void printAsOperand(raw_ostream &OS, bool PrintType=true) const
MachineInstr * remove(MachineInstr *I)
Remove the unbundled instruction from the instruction list without deleting it.
void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
Instructions::iterator instr_iterator
Instructions::const_iterator const_instr_iterator
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isSpillSlotObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a spill slot.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
void deallocateOperandArray(OperandCapacity Cap, MachineOperand *Array)
Dellocate an array of MachineOperands and recycle the memory.
MachineOperand * allocateOperandArray(OperandCapacity Cap)
Allocate an array of MachineOperands.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
void handleChangeDesc(MachineInstr &MI, const MCInstrDesc &TID)
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
MachineInstr::ExtraInfo * createMIExtraInfo(ArrayRef< MachineMemOperand * > MMOs, MCSymbol *PreInstrSymbol=nullptr, MCSymbol *PostInstrSymbol=nullptr, MDNode *HeapAllocMarker=nullptr, MDNode *PCSections=nullptr, uint32_t CFIType=0)
Allocate and construct an extra info structure for a MachineInstr.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addMetadata(const MDNode *MD) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
Definition: MachineInstr.h:69
int findRegisterUseOperandIdx(Register Reg, bool isKill=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a use of the specific register or -1 if it is not found.
bool mayRaiseFPException() const
Return true if this instruction could possibly raise a floating-point exception.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:546
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
static iterator_range< filter_iterator< Operand *, std::function< bool(Operand &Op)> > > getDebugOperandsForReg(Instruction *MI, Register Reg)
Returns a range of all of the operands that correspond to a debug use of Reg.
Definition: MachineInstr.h:587
bool isDebugValueList() const
void bundleWithPred()
Bundle this instruction with its predecessor.
bool isPosition() const
bool isSafeToMove(AAResults *AA, bool &SawStore) const
Return true if it is safe to move this instruction.
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
Definition: MachineInstr.h:942
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst5RegLLTs() const
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
void setCFIType(MachineFunction &MF, uint32_t Type)
Set the CFI type for the instruction.
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
iterator_range< mop_iterator > debug_operands()
Returns a range over all operands that are used to determine the variable location for this DBG_VALUE...
Definition: MachineInstr.h:684
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:329
void bundleWithSucc()
Bundle this instruction with its successor.
uint32_t getCFIType() const
Helper to extract a CFI type hash if one has been added.
Definition: MachineInstr.h:842
int findRegisterDefOperandIdx(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr) const
Returns the operand index that is a def of the specified register or -1 if it is not found.
bool isDebugLabel() const
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just prior to the instruction itself.
bool hasProperty(unsigned MCFlag, QueryType Type=AnyInBundle) const
Return true if the instruction (or in the case of a bundle, the instructions inside the bundle) has t...
Definition: MachineInstr.h:865
bool isDereferenceableInvariantLoad() const
Return true if this load instruction never traps and points to a memory location whose value doesn't ...
void setFlags(unsigned flags)
Definition: MachineInstr.h:392
QueryType
API for querying MachineInstr properties.
Definition: MachineInstr.h:854
void addImplicitDefUseOperands(MachineFunction &MF)
Add all implicit def and use operands to this instruction.
std::tuple< LLT, LLT, LLT, LLT, LLT > getFirst5LLTs() const
bool isCall(QueryType Type=AnyInBundle) const
Definition: MachineInstr.h:918
std::tuple< Register, LLT, Register, LLT, Register, LLT > getFirst3RegLLTs() const
bool getFlag(MIFlag Flag) const
Return whether an MI flag is set.
Definition: MachineInstr.h:379
uint32_t mergeFlagsWith(const MachineInstr &Other) const
Return the MIFlags which represent both MachineInstrs.
const MachineOperand & getDebugExpressionOp() const
Return the operand for the complex address expression referenced by this DBG_VALUE instruction.
std::pair< bool, bool > readsWritesVirtualRegister(Register Reg, SmallVectorImpl< unsigned > *Ops=nullptr) const
Return a pair of bools (reads, writes) indicating if this instruction reads or writes Reg.
bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx=nullptr) const
Return true if the use operand of the specified index is tied to a def operand.
bool allImplicitDefsAreDead() const
Return true if all the implicit defs of this instruction are dead.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's memory reference descriptor list and replace ours with it.
const TargetRegisterClass * getRegClassConstraintEffectForVReg(Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, bool ExploreBundle=false) const
Applies the constraints (def/use) implied by this MI on Reg to the given CurRC.
bool isBundle() const
bool isDebugInstr() const
unsigned getNumDebugOperands() const
Returns the total number of operands which are debug locations.
Definition: MachineInstr.h:552
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:549
void addOperand(MachineFunction &MF, const MachineOperand &Op)
Add the specified operand to the instruction.
MachineInstr * removeFromBundle()
Unlink this instruction from its basic block and return it without deleting it.
void dumpr(const MachineRegisterInfo &MRI, unsigned MaxDepth=UINT_MAX) const
Print on dbgs() the current instruction and the instructions defining its operands and so on until we...
void copyIRFlags(const Instruction &I)
Copy all flags to MachineInst MIFlags.
bool isDebugValueLike() const
bool isInlineAsm() const
bool memoperands_empty() const
Return true if we don't have any memory operands which described the memory access done by this instr...
Definition: MachineInstr.h:789
mmo_iterator memoperands_end() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:784
bool isDebugRef() const
void collectDebugValues(SmallVectorImpl< MachineInstr * > &DbgValues)
Scan instructions immediately following MI and collect any matching DBG_VALUEs.
std::optional< LocationSize > getRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a restore instruction.
unsigned getOperandNo(const_mop_iterator I) const
Returns the number of the operand iterator I points to.
Definition: MachineInstr.h:752
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const
Returns true if this instruction's memory access aliases the memory access of Other.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
void setMemRefs(MachineFunction &MF, ArrayRef< MachineMemOperand * > MemRefs)
Assign this MachineInstr's memory reference descriptor list.
bool isBundledWithPred() const
Return true if this instruction is part of a bundle, and it is not the first instruction in the bundl...
Definition: MachineInstr.h:454
std::tuple< LLT, LLT > getFirst2LLTs() const
std::optional< LocationSize > getFoldedSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded spill instruction.
void unbundleFromPred()
Break bundle above this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool isStackAligningInlineAsm() const
void dropMemRefs(MachineFunction &MF)
Clear this MachineInstr's memory reference descriptor list.
bool shouldUpdateCallSiteInfo() const
Return true if copying, moving, or erasing this instruction requires updating Call Site Info (see cop...
MDNode * getPCSections() const
Helper to extract PCSections metadata target sections.
Definition: MachineInstr.h:832
bool isCFIInstruction() const
int findFirstPredOperandIdx() const
Find the index of the first operand in the operand list that is used to represent the predicate.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:543
unsigned getBundleSize() const
Return the number of instructions inside the MI bundle, excluding the bundle header.
void cloneMergedMemRefs(MachineFunction &MF, ArrayRef< const MachineInstr * > MIs)
Clone the merge of multiple MachineInstrs' memory reference descriptors list and replace ours with it...
std::tuple< Register, LLT, Register, LLT, Register, LLT, Register, LLT > getFirst4RegLLTs() const
std::tuple< Register, LLT, Register, LLT > getFirst2RegLLTs() const
unsigned getNumMemOperands() const
Return the number of memory operands.
Definition: MachineInstr.h:795
void clearFlag(MIFlag Flag)
clearFlag - Clear a MI flag.
Definition: MachineInstr.h:401
std::optional< LocationSize > getFoldedRestoreSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a folded restore instruction.
unsigned isConstantValuePHI() const
If the specified instruction is a PHI that always merges together the same virtual register,...
const TargetRegisterClass * getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Applies the constraints (def/use) implied by the OpIdx operand to the given CurRC.
bool isOperandSubregIdx(unsigned OpIdx) const
Return true if operand OpIdx is a subregister index.
Definition: MachineInstr.h:633
InlineAsm::AsmDialect getInlineAsmDialect() const
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
bool isEquivalentDbgInstr(const MachineInstr &Other) const
Returns true if this instruction is a debug instruction that represents an identical debug value to O...
const DILabel * getDebugLabel() const
Return the debug label referenced by this DBG_LABEL instruction.
void untieRegOperand(unsigned OpIdx)
Break any tie involving OpIdx.
static uint32_t copyFlagsFromInstruction(const Instruction &I)
void insert(mop_iterator InsertBefore, ArrayRef< MachineOperand > Ops)
Inserts Ops BEFORE It. Can untie/retie tied operands.
void setDesc(const MCInstrDesc &TID)
Replace the instruction descriptor (thus opcode) of the current instruction with a new one.
bool isJumpTableDebugInfo() const
unsigned getNumExplicitDefs() const
Returns the number of non-implicit definitions.
void eraseFromBundle()
Unlink 'this' from its basic block and delete it.
iterator_range< mop_iterator > operands()
Definition: MachineInstr.h:662
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD)
Set a marker on instructions that denotes where we should create and emit heap alloc site labels.
const DILocalVariable * getDebugVariable() const
Return the debug variable referenced by this DBG_VALUE instruction.
bool hasComplexRegisterTies() const
Return true when an instruction has tied register that can't be determined by the instruction's descr...
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, const MachineRegisterInfo &MRI) const
Debugging supportDetermine the generic type to be printed (if needed) on uses and defs.
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo)
Replace all occurrences of FromReg with ToReg:SubIdx, properly composing subreg indices where necessa...
unsigned findTiedOperandIdx(unsigned OpIdx) const
Given the index of a tied register operand, find the operand it is tied to.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
mmo_iterator memoperands_begin() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:777
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI)
Clone another MachineInstr's pre- and post- instruction symbols and replace ours with it.
void changeDebugValuesDefReg(Register Reg)
Find all DBG_VALUEs that point to the register def in this instruction and point them to Reg instead.
bool isIdenticalTo(const MachineInstr &Other, MICheckType Check=CheckDefs) const
Return true if this instruction is identical to Other.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
const DIExpression * getDebugExpression() const
Return the complex address expression referenced by this DBG_VALUE instruction.
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:759
void print(raw_ostream &OS, bool IsStandalone=true, bool SkipOpers=false, bool SkipDebugLoc=false, bool AddNewLine=true, const TargetInstrInfo *TII=nullptr) const
Print this MI to OS.
bool isNonListDebugValue() const
bool isLoadFoldBarrier() const
Returns true if it is illegal to fold a load across this instruction.
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
void setFlag(MIFlag Flag)
Set a MI flag.
Definition: MachineInstr.h:386
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:475
std::tuple< LLT, LLT, LLT > getFirst3LLTs() const
const MachineOperand & getDebugVariableOp() const
Return the operand for the debug variable referenced by this DBG_VALUE instruction.
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
void setPhysRegsDeadExcept(ArrayRef< Register > UsedRegs, const TargetRegisterInfo &TRI)
Mark every physreg used by this instruction as dead except those in the UsedRegs list.
bool isCandidateForCallSiteEntry(QueryType Type=IgnoreBundle) const
Return true if this is a call instruction that may have an associated call site entry in the debug in...
void removeOperand(unsigned OpNo)
Erase an operand from an instruction, leaving it with one fewer operand than it started with.
MCSymbol * getPreInstrSymbol() const
Helper to extract a pre-instruction symbol if one has been added.
Definition: MachineInstr.h:798
bool addRegisterKilled(Register IncomingReg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI kills a register.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol)
Set a symbol that will be emitted just after the instruction itself.
bool isDebugValue() const
const MachineOperand & getDebugOffset() const
Return the operand containing the offset to be used if this DBG_VALUE instruction is indirect; will b...
Definition: MachineInstr.h:480
MachineOperand & getDebugOperand(unsigned Index)
Definition: MachineInstr.h:565
std::optional< LocationSize > getSpillSize(const TargetInstrInfo *TII) const
Return a valid size if the instruction is a spill instruction.
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:676
bool isBundledWithSucc() const
Return true if this instruction is part of a bundle, and it is not the last instruction in the bundle...
Definition: MachineInstr.h:458
void addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo=nullptr)
We have determined MI defines a register.
MDNode * getHeapAllocMarker() const
Helper to extract a heap alloc marker if one has been added.
Definition: MachineInstr.h:822
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
std::tuple< LLT, LLT, LLT, LLT > getFirst4LLTs() const
bool isPHI() const
void clearRegisterDeads(Register Reg)
Clear all dead flags on operands defining register Reg.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo)
Clear all kill flags affecting Reg.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:556
uint32_t getFlags() const
Return the MI flags bitvector.
Definition: MachineInstr.h:374
bool isPseudoProbe() const
bool hasRegisterImplicitUseOperand(Register Reg) const
Returns true if the MachineInstr has an implicit-use operand of exactly the given register (not consi...
MCSymbol * getPostInstrSymbol() const
Helper to extract a post-instruction symbol if one has been added.
Definition: MachineInstr.h:810
void unbundleFromSucc()
Break bundle below this instruction.
void clearKillInfo()
Clears kill flags on all operands.
bool isDebugEntryValue() const
A DBG_VALUE is an entry value iff its debug expression contains the DW_OP_LLVM_entry_value operation.
bool isIndirectDebugValue() const
A DBG_VALUE is indirect iff the location operand is a register and the offset operand is an immediate...
unsigned getNumDefs() const
Returns the total number of definitions.
Definition: MachineInstr.h:615
void emitError(StringRef Msg) const
Emit an error referring to the source location of this instruction.
void setPCSections(MachineFunction &MF, MDNode *MD)
bool isKill() const
MachineOperand * findRegisterDefOperand(Register Reg, bool isDead=false, bool Overlap=false, const TargetRegisterInfo *TRI=nullptr)
Wrapper for findRegisterDefOperandIdx, it returns a pointer to the MachineOperand rather than an inde...
bool isVariadic(QueryType Type=IgnoreBundle) const
Return true if this instruction can have a variable number of operands.
Definition: MachineInstr.h:886
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo=nullptr) const
Find the index of the flag word operand that corresponds to operand OpIdx on an inline asm instructio...
bool allDefsAreDead() const
Return true if all the defs of this instruction are dead.
const TargetRegisterClass * getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const
Compute the static register class constraint for operand OpIdx.
void moveBefore(MachineInstr *MovePos)
Move the instruction before MovePos.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound=false)
We have determined MI defined a register without a use.
bool mayFoldInlineAsmRegOp(unsigned OpId) const
Returns true if the register operand can be folded with a load or store into a frame index.
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
const Value * getValue() const
Return the base address of the memory access.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
const Module * getModule() const
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo &)
substVirtReg - Substitute the current register with the virtual subregister Reg:SubReg.
static void printSubRegIdx(raw_ostream &OS, uint64_t Index, const TargetRegisterInfo *TRI)
Print a subreg index operand.
int64_t getImm() const
bool isImplicit() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isRegMask() const
isRegMask - Tests if this is a MO_RegisterMask operand.
const MDNode * getMetadata() const
void setIsDead(bool Val=true)
void setMetadata(const MDNode *MD)
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags=0)
ChangeToImmediate - Replace this operand with a new immediate operand of the specified value.
bool isMetadata() const
isMetadata - Tests if this is a MO_Metadata operand.
void setIsKill(bool Val=true)
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
void substPhysReg(MCRegister Reg, const TargetRegisterInfo &)
substPhysReg - Substitute the current register with the physical register Reg, taking any existing Su...
void setIsEarlyClobber(bool Val=true)
void setIsUndef(bool Val=true)
void setIsDebug(bool Val=true)
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
static void printSymbol(raw_ostream &OS, MCSymbol &Sym)
Print a MCSymbol as an operand.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Representation for a specific memory location.
void printAsOperand(raw_ostream &OS, const Module *M=nullptr) const
Print as operand.
Definition: AsmWriter.cpp:5185
Manage lifetime of a slot tracker for printing IR.
void incorporateFunction(const Function &F)
Incorporate the given function.
Definition: AsmWriter.cpp:899
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:301
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
Definition: Operator.h:75
An or instruction, which can be marked as "disjoint", indicating that the inputs don't have a 1 in th...
Definition: InstrTypes.h:516
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Definition: Operator.h:150
Instruction that can have a nneg flag (zext/uitofp).
Definition: InstrTypes.h:931
Special value supplied for machine level alias analysis.
virtual bool mayAlias(const MachineFrameInfo *) const
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
Definition: Register.h:95
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
SmallBitVector & set()
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:321
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
Definition: SmallPtrSet.h:342
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
Definition: SmallPtrSet.h:427
bool empty() const
Definition: SmallVector.h:94
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
reference emplace_back(ArgTypes &&... Args)
Definition: SmallVector.h:950
void reserve(size_type N)
Definition: SmallVector.h:676
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:696
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
static unsigned getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx)
Get index of next meta operand.
Definition: StackMaps.cpp:171
MI-level Statepoint operands.
Definition: StackMaps.h:158
int getFirstGCPtrIdx()
Get index of first GC pointer operand of -1 if there are none.
Definition: StackMaps.cpp:125
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
MCRegister getSubReg(MCRegister Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo.
bool regsOverlap(Register RegA, Register RegB) const
Returns true if the two registers are equal or alias each other.
virtual const TargetInstrInfo * getInstrInfo() const
This class represents a truncation of integer types.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
A Use represents the edge between a Value definition and its users.
Definition: Use.h:43
LLVM Value Representation.
Definition: Value.h:74
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
formatted_raw_ostream & PadToColumn(unsigned NewCol)
PadToColumn - Align the output to some column number.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
@ UnmodeledSideEffects
Definition: MCInstrDesc.h:173
constexpr double e
Definition: MathExtras.h:31
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
Definition: STLExtras.h:329
hash_code hash_value(const FixedPointSemantics &Val)
Definition: APFixedPoint.h:128
formatted_raw_ostream & fdbgs()
fdbgs() - This returns a reference to a formatted_raw_ostream for debug output.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg)
Update a DBG_VALUE whose value has been spilled to FrameIndex.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
iterator_range< pointee_iterator< WrappedIteratorT > > make_pointee_range(RangeT &&Range)
Definition: iterator.h:336
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1736
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
@ Other
Any other memory.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1849
MachineInstr * buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I, const MachineInstr &Orig, int FrameIndex, Register SpillReg)
Clone a DBG_VALUE whose value has been spilled to FrameIndex.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Definition: STLExtras.h:1879
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
Definition: Hashing.h:491
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
#define N
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:760
static unsigned getHashValue(const MachineInstr *const &MI)