LLVM  15.0.0git
MachineMemOperand.h
Go to the documentation of this file.
1 //==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineMemOperand class, which is a
10 // description of a memory reference. It is used to help track dependencies
11 // in the backend.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
16 #define LLVM_CODEGEN_MACHINEMEMOPERAND_H
17 
18 #include "llvm/ADT/BitmaskEnum.h"
19 #include "llvm/ADT/PointerUnion.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
24 #include "llvm/Support/DataTypes.h"
26 
27 namespace llvm {
28 
29 class FoldingSetNodeID;
30 class MDNode;
31 class raw_ostream;
32 class MachineFunction;
33 class ModuleSlotTracker;
34 
35 /// This class contains a discriminated union of information about pointers in
36 /// memory operands, relating them back to LLVM IR or to virtual locations (such
37 /// as frame indices) that are exposed during codegen.
39  /// This is the IR pointer value for the access, or it is null if unknown.
41 
42  /// Offset - This is an offset from the base Value*.
43  int64_t Offset;
44 
45  unsigned AddrSpace = 0;
46 
47  uint8_t StackID;
48 
49  explicit MachinePointerInfo(const Value *v, int64_t offset = 0,
50  uint8_t ID = 0)
51  : V(v), Offset(offset), StackID(ID) {
52  AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0;
53  }
54 
55  explicit MachinePointerInfo(const PseudoSourceValue *v, int64_t offset = 0,
56  uint8_t ID = 0)
57  : V(v), Offset(offset), StackID(ID) {
58  AddrSpace = v ? v->getAddressSpace() : 0;
59  }
60 
61  explicit MachinePointerInfo(unsigned AddressSpace = 0, int64_t offset = 0)
62  : V((const Value *)nullptr), Offset(offset), AddrSpace(AddressSpace),
63  StackID(0) {}
64 
67  int64_t offset = 0,
68  uint8_t ID = 0)
69  : V(v), Offset(offset), StackID(ID) {
70  if (V) {
71  if (const auto *ValPtr = V.dyn_cast<const Value*>())
72  AddrSpace = ValPtr->getType()->getPointerAddressSpace();
73  else
75  }
76  }
77 
79  if (V.isNull())
81  if (V.is<const Value*>())
82  return MachinePointerInfo(V.get<const Value*>(), Offset + O, StackID);
83  return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset + O,
84  StackID);
85  }
86 
87  /// Return true if memory region [V, V+Offset+Size) is known to be
88  /// dereferenceable.
89  bool isDereferenceable(unsigned Size, LLVMContext &C,
90  const DataLayout &DL) const;
91 
92  /// Return the LLVM IR address space number that this pointer points into.
93  unsigned getAddrSpace() const;
94 
95  /// Return a MachinePointerInfo record that refers to the constant pool.
97 
98  /// Return a MachinePointerInfo record that refers to the specified
99  /// FrameIndex.
101  int64_t Offset = 0);
102 
103  /// Return a MachinePointerInfo record that refers to a jump table entry.
105 
106  /// Return a MachinePointerInfo record that refers to a GOT entry.
108 
109  /// Stack pointer relative access.
111  uint8_t ID = 0);
112 
113  /// Stack memory without other information.
115 };
116 
117 
118 //===----------------------------------------------------------------------===//
119 /// A description of a memory reference used in the backend.
120 /// Instead of holding a StoreInst or LoadInst, this class holds the address
121 /// Value of the reference along with a byte size and offset. This allows it
122 /// to describe lowered loads and stores. Also, the special PseudoSourceValue
123 /// objects can be used to represent loads and stores to memory locations
124 /// that aren't explicit in the regular LLVM IR.
125 ///
127 public:
128  /// Flags values. These may be or'd together.
129  enum Flags : uint16_t {
130  // No flags set.
131  MONone = 0,
132  /// The memory access reads data.
133  MOLoad = 1u << 0,
134  /// The memory access writes data.
135  MOStore = 1u << 1,
136  /// The memory access is volatile.
137  MOVolatile = 1u << 2,
138  /// The memory access is non-temporal.
139  MONonTemporal = 1u << 3,
140  /// The memory access is dereferenceable (i.e., doesn't trap).
141  MODereferenceable = 1u << 4,
142  /// The memory access always returns the same value (or traps).
143  MOInvariant = 1u << 5,
144 
145  // Reserved for use by target-specific passes.
146  // Targets may override getSerializableMachineMemOperandTargetFlags() to
147  // enable MIR serialization/parsing of these flags. If more of these flags
148  // are added, the MIR printing/parsing code will need to be updated as well.
149  MOTargetFlag1 = 1u << 6,
150  MOTargetFlag2 = 1u << 7,
151  MOTargetFlag3 = 1u << 8,
152 
153  LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
154  };
155 
156 private:
157  /// Atomic information for this memory operation.
158  struct MachineAtomicInfo {
159  /// Synchronization scope ID for this memory operation.
160  unsigned SSID : 8; // SyncScope::ID
161  /// Atomic ordering requirements for this memory operation. For cmpxchg
162  /// atomic operations, atomic ordering requirements when store occurs.
163  unsigned Ordering : 4; // enum AtomicOrdering
164  /// For cmpxchg atomic operations, atomic ordering requirements when store
165  /// does not occur.
166  unsigned FailureOrdering : 4; // enum AtomicOrdering
167  };
168 
169  MachinePointerInfo PtrInfo;
170 
171  /// Track the memory type of the access. An access size which is unknown or
172  /// too large to be represented by LLT should use the invalid LLT.
173  LLT MemoryType;
174 
175  Flags FlagVals;
176  Align BaseAlign;
177  MachineAtomicInfo AtomicInfo;
178  AAMDNodes AAInfo;
179  const MDNode *Ranges;
180 
181 public:
182  /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
183  /// size, and base alignment. For atomic operations the synchronization scope
184  /// and atomic ordering requirements must also be specified. For cmpxchg
185  /// atomic operations the atomic ordering requirements when store does not
186  /// occur must also be specified.
187  MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
188  Align a, const AAMDNodes &AAInfo = AAMDNodes(),
189  const MDNode *Ranges = nullptr,
192  AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
193  MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LLT type, Align a,
194  const AAMDNodes &AAInfo = AAMDNodes(),
195  const MDNode *Ranges = nullptr,
198  AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
199 
200  const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
201 
202  /// Return the base address of the memory access. This may either be a normal
203  /// LLVM IR Value, or one of the special values used in CodeGen.
204  /// Special values are those obtained via
205  /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
206  /// other PseudoSourceValue member functions which return objects which stand
207  /// for frame/stack pointer relative references and other special references
208  /// which are not representable in the high-level IR.
209  const Value *getValue() const { return PtrInfo.V.dyn_cast<const Value*>(); }
210 
212  return PtrInfo.V.dyn_cast<const PseudoSourceValue*>();
213  }
214 
215  const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
216 
217  /// Return the raw flags of the source value, \see Flags.
218  Flags getFlags() const { return FlagVals; }
219 
220  /// Bitwise OR the current flags with the given flags.
221  void setFlags(Flags f) { FlagVals |= f; }
222 
223  /// For normal values, this is a byte offset added to the base address.
224  /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
225  int64_t getOffset() const { return PtrInfo.Offset; }
226 
227  unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
228 
229  /// Return the memory type of the memory reference. This should only be relied
230  /// on for GlobalISel G_* operation legalization.
231  LLT getMemoryType() const { return MemoryType; }
232 
233  /// Return the size in bytes of the memory reference.
234  uint64_t getSize() const {
235  return MemoryType.isValid() ? MemoryType.getSizeInBytes() : ~UINT64_C(0);
236  }
237 
238  /// Return the size in bits of the memory reference.
240  return MemoryType.isValid() ? MemoryType.getSizeInBits() : ~UINT64_C(0);
241  }
242 
243  LLT getType() const {
244  return MemoryType;
245  }
246 
247  /// Return the minimum known alignment in bytes of the actual memory
248  /// reference.
249  Align getAlign() const;
250 
251  /// Return the minimum known alignment in bytes of the base address, without
252  /// the offset.
253  Align getBaseAlign() const { return BaseAlign; }
254 
255  /// Return the AA tags for the memory reference.
256  AAMDNodes getAAInfo() const { return AAInfo; }
257 
258  /// Return the range tag for the memory reference.
259  const MDNode *getRanges() const { return Ranges; }
260 
261  /// Returns the synchronization scope ID for this memory operation.
263  return static_cast<SyncScope::ID>(AtomicInfo.SSID);
264  }
265 
266  /// Return the atomic ordering requirements for this memory operation. For
267  /// cmpxchg atomic operations, return the atomic ordering requirements when
268  /// store occurs.
270  return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
271  }
272 
273  /// For cmpxchg atomic operations, return the atomic ordering requirements
274  /// when store does not occur.
276  return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
277  }
278 
279  /// Return a single atomic ordering that is at least as strong as both the
280  /// success and failure orderings for an atomic operation. (For operations
281  /// other than cmpxchg, this is equivalent to getSuccessOrdering().)
284  }
285 
286  bool isLoad() const { return FlagVals & MOLoad; }
287  bool isStore() const { return FlagVals & MOStore; }
288  bool isVolatile() const { return FlagVals & MOVolatile; }
289  bool isNonTemporal() const { return FlagVals & MONonTemporal; }
290  bool isDereferenceable() const { return FlagVals & MODereferenceable; }
291  bool isInvariant() const { return FlagVals & MOInvariant; }
292 
293  /// Returns true if this operation has an atomic ordering requirement of
294  /// unordered or higher, false otherwise.
295  bool isAtomic() const {
297  }
298 
299  /// Returns true if this memory operation doesn't have any ordering
300  /// constraints other than normal aliasing. Volatile and (ordered) atomic
301  /// memory operations can't be reordered.
302  bool isUnordered() const {
305  !isVolatile();
306  }
307 
308  /// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
309  /// greater alignment. This must only be used when the new alignment applies
310  /// to all users of this MachineMemOperand.
311  void refineAlignment(const MachineMemOperand *MMO);
312 
313  /// Change the SourceValue for this MachineMemOperand. This should only be
314  /// used when an object is being relocated and all references to it are being
315  /// updated.
316  void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
317  void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
318  void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
319 
320  /// Reset the tracked memory type.
321  void setType(LLT NewTy) {
322  MemoryType = NewTy;
323  }
324 
325  /// Profile - Gather unique data for the object.
326  ///
327  void Profile(FoldingSetNodeID &ID) const;
328 
329  /// Support for operator<<.
330  /// @{
331  void print(raw_ostream &OS, ModuleSlotTracker &MST,
333  const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const;
334  /// @}
335 
336  friend bool operator==(const MachineMemOperand &LHS,
337  const MachineMemOperand &RHS) {
338  return LHS.getValue() == RHS.getValue() &&
339  LHS.getPseudoValue() == RHS.getPseudoValue() &&
340  LHS.getSize() == RHS.getSize() &&
341  LHS.getOffset() == RHS.getOffset() &&
342  LHS.getFlags() == RHS.getFlags() &&
343  LHS.getAAInfo() == RHS.getAAInfo() &&
344  LHS.getRanges() == RHS.getRanges() &&
345  LHS.getAlign() == RHS.getAlign() &&
346  LHS.getAddrSpace() == RHS.getAddrSpace();
347  }
348 
349  friend bool operator!=(const MachineMemOperand &LHS,
350  const MachineMemOperand &RHS) {
351  return !(LHS == RHS);
352  }
353 };
354 
355 } // End llvm namespace
356 
357 #endif
llvm::MachineMemOperand::setValue
void setValue(const Value *NewSV)
Change the SourceValue for this MachineMemOperand.
Definition: MachineMemOperand.h:316
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition: MachineOperand.cpp:1048
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:287
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1087
llvm::MachinePointerInfo::StackID
uint8_t StackID
Definition: MachineMemOperand.h:47
AtomicOrdering.h
LLVM_MARK_AS_BITMASK_ENUM
#define LLVM_MARK_AS_BITMASK_ENUM(LargestValue)
LLVM_MARK_AS_BITMASK_ENUM lets you opt in an individual enum type so you can perform bitwise operatio...
Definition: BitmaskEnum.h:41
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1091
llvm::getMergedAtomicOrdering
AtomicOrdering getMergedAtomicOrdering(AtomicOrdering AO, AtomicOrdering Other)
Return a single atomic ordering that is at least as strong as both the AO and Other orderings for an ...
Definition: AtomicOrdering.h:138
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:1000
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition: MachineOperand.cpp:1024
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition: MachineMemOperand.h:286
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:225
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:729
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:143
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const PseudoSourceValue *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:55
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:150
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:239
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition: MachineMemOperand.h:215
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:126
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:141
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition: MachineMemOperand.h:291
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:256
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:302
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:155
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition: MachineOperand.cpp:1011
llvm::PointerUnion::is
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:150
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:43
llvm::AVR::getAddressSpace
AddressSpace getAddressSpace(T *V)
Definition: AVR.h:64
llvm::MachineMemOperand::getPointerInfo
const MachinePointerInfo & getPointerInfo() const
Definition: MachineMemOperand.h:200
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:149
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:97
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition: MachineMemOperand.h:253
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:227
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:209
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1015
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:127
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:54
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:49
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition: MachineMemOperand.h:262
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
LowLevelTypeImpl.h
llvm::MachineMemOperand::setFlags
void setFlags(Flags f)
Bitwise OR the current flags with the given flags.
Definition: MachineMemOperand.h:221
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:58
llvm::MachineMemOperand::Profile
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
Definition: MachineOperand.cpp:1060
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(unsigned AddressSpace=0, int64_t offset=0)
Definition: MachineMemOperand.h:61
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:239
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition: MachineOperand.cpp:985
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition: MachineMemOperand.h:290
uint64_t
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:162
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:38
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:68
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:47
llvm::AtomicOrdering::Unordered
@ Unordered
llvm::MachineMemOperand::setOffset
void setOffset(int64_t NewOffset)
Definition: MachineMemOperand.h:318
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:129
llvm::PseudoSourceValue::getAddressSpace
unsigned getAddressSpace() const
Definition: PseudoSourceValue.h:73
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:269
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:139
PointerUnion.h
llvm::MachineMemOperand::getMemoryType
LLT getMemoryType() const
Return the memory type of the memory reference.
Definition: MachineMemOperand.h:231
llvm::MDNode
Metadata node.
Definition: Metadata.h:926
llvm::MachineMemOperand::getType
LLT getType() const
Definition: MachineMemOperand.h:243
llvm::MachinePointerInfo::getWithOffset
MachinePointerInfo getWithOffset(int64_t O) const
Definition: MachineMemOperand.h:78
llvm::MachineFunction
Definition: MachineFunction.h:241
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition: MachineMemOperand.h:151
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:40
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
BitmaskEnum.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition: MachineMemOperand.h:45
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:317
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:137
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:981
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:133
llvm::PointerUnion< const Value *, const PseudoSourceValue * >
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:288
uint16_t
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:234
llvm::MachineMemOperand::operator==
friend bool operator==(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
Definition: MachineMemOperand.h:336
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:295
llvm::MachineMemOperand::getMergedOrdering
AtomicOrdering getMergedOrdering() const
Return a single atomic ordering that is at least as strong as both the success and failure orderings ...
Definition: MachineMemOperand.h:282
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition: MachineOperand.cpp:1068
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:135
llvm::MachineMemOperand::setValue
void setValue(const PseudoSourceValue *NewSV)
Definition: MachineMemOperand.h:317
llvm::MachineMemOperand::operator!=
friend bool operator!=(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
Definition: MachineMemOperand.h:349
llvm::MachineMemOperand::setType
void setType(LLT NewTy)
Reset the tracked memory type.
Definition: MachineMemOperand.h:321
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1006
llvm::SmallVectorImpl< StringRef >
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition: MachineMemOperand.h:275
DataTypes.h
DerivedTypes.h
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition: MachineMemOperand.h:289
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition: MachineMemOperand.h:259
Value.h
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:131
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1019
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(PointerUnion< const Value *, const PseudoSourceValue * > v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:65
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:218
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:211
llvm::LLT
Definition: LowLevelTypeImpl.h:39