LLVM 19.0.0git
MachineMemOperand.h
Go to the documentation of this file.
1//==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineMemOperand class, which is a
10// description of a memory reference. It is used to help track dependencies
11// in the backend.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
16#define LLVM_CODEGEN_MACHINEMEMOPERAND_H
17
23#include "llvm/IR/LLVMContext.h"
24#include "llvm/IR/Metadata.h"
25#include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
28
29namespace llvm {
30
31class MDNode;
32class raw_ostream;
33class MachineFunction;
34class ModuleSlotTracker;
35class TargetInstrInfo;
36
37/// This class contains a discriminated union of information about pointers in
38/// memory operands, relating them back to LLVM IR or to virtual locations (such
39/// as frame indices) that are exposed during codegen.
41 /// This is the IR pointer value for the access, or it is null if unknown.
43
44 /// Offset - This is an offset from the base Value*.
45 int64_t Offset;
46
47 unsigned AddrSpace = 0;
48
49 uint8_t StackID;
50
51 explicit MachinePointerInfo(const Value *v, int64_t offset = 0,
52 uint8_t ID = 0)
53 : V(v), Offset(offset), StackID(ID) {
54 AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0;
55 }
56
57 explicit MachinePointerInfo(const PseudoSourceValue *v, int64_t offset = 0,
58 uint8_t ID = 0)
59 : V(v), Offset(offset), StackID(ID) {
60 AddrSpace = v ? v->getAddressSpace() : 0;
61 }
62
63 explicit MachinePointerInfo(unsigned AddressSpace = 0, int64_t offset = 0)
64 : V((const Value *)nullptr), Offset(offset), AddrSpace(AddressSpace),
65 StackID(0) {}
66
69 int64_t offset = 0,
70 uint8_t ID = 0)
71 : V(v), Offset(offset), StackID(ID) {
72 if (V) {
73 if (const auto *ValPtr = dyn_cast_if_present<const Value *>(V))
74 AddrSpace = ValPtr->getType()->getPointerAddressSpace();
75 else
76 AddrSpace = cast<const PseudoSourceValue *>(V)->getAddressSpace();
77 }
78 }
79
81 if (V.isNull())
83 if (isa<const Value *>(V))
84 return MachinePointerInfo(cast<const Value *>(V), Offset + O, StackID);
85 return MachinePointerInfo(cast<const PseudoSourceValue *>(V), Offset + O,
86 StackID);
87 }
88
89 /// Return true if memory region [V, V+Offset+Size) is known to be
90 /// dereferenceable.
91 bool isDereferenceable(unsigned Size, LLVMContext &C,
92 const DataLayout &DL) const;
93
94 /// Return the LLVM IR address space number that this pointer points into.
95 unsigned getAddrSpace() const;
96
97 /// Return a MachinePointerInfo record that refers to the constant pool.
99
100 /// Return a MachinePointerInfo record that refers to the specified
101 /// FrameIndex.
103 int64_t Offset = 0);
104
105 /// Return a MachinePointerInfo record that refers to a jump table entry.
107
108 /// Return a MachinePointerInfo record that refers to a GOT entry.
110
111 /// Stack pointer relative access.
113 uint8_t ID = 0);
114
115 /// Stack memory without other information.
117};
118
119
120//===----------------------------------------------------------------------===//
121/// A description of a memory reference used in the backend.
122/// Instead of holding a StoreInst or LoadInst, this class holds the address
123/// Value of the reference along with a byte size and offset. This allows it
124/// to describe lowered loads and stores. Also, the special PseudoSourceValue
125/// objects can be used to represent loads and stores to memory locations
126/// that aren't explicit in the regular LLVM IR.
127///
129public:
130 /// Flags values. These may be or'd together.
132 // No flags set.
134 /// The memory access reads data.
135 MOLoad = 1u << 0,
136 /// The memory access writes data.
137 MOStore = 1u << 1,
138 /// The memory access is volatile.
139 MOVolatile = 1u << 2,
140 /// The memory access is non-temporal.
141 MONonTemporal = 1u << 3,
142 /// The memory access is dereferenceable (i.e., doesn't trap).
144 /// The memory access always returns the same value (or traps).
145 MOInvariant = 1u << 5,
146
147 // Reserved for use by target-specific passes.
148 // Targets may override getSerializableMachineMemOperandTargetFlags() to
149 // enable MIR serialization/parsing of these flags. If more of these flags
150 // are added, the MIR printing/parsing code will need to be updated as well.
151 MOTargetFlag1 = 1u << 6,
152 MOTargetFlag2 = 1u << 7,
153 MOTargetFlag3 = 1u << 8,
154
155 LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
156 };
157
158private:
159 /// Atomic information for this memory operation.
160 struct MachineAtomicInfo {
161 /// Synchronization scope ID for this memory operation.
162 unsigned SSID : 8; // SyncScope::ID
163 /// Atomic ordering requirements for this memory operation. For cmpxchg
164 /// atomic operations, atomic ordering requirements when store occurs.
165 unsigned Ordering : 4; // enum AtomicOrdering
166 /// For cmpxchg atomic operations, atomic ordering requirements when store
167 /// does not occur.
168 unsigned FailureOrdering : 4; // enum AtomicOrdering
169 };
170
171 MachinePointerInfo PtrInfo;
172
173 /// Track the memory type of the access. An access size which is unknown or
174 /// too large to be represented by LLT should use the invalid LLT.
175 LLT MemoryType;
176
177 Flags FlagVals;
178 Align BaseAlign;
179 MachineAtomicInfo AtomicInfo;
180 AAMDNodes AAInfo;
181 const MDNode *Ranges;
182
183public:
184 /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
185 /// size, and base alignment. For atomic operations the synchronization scope
186 /// and atomic ordering requirements must also be specified. For cmpxchg
187 /// atomic operations the atomic ordering requirements when store does not
188 /// occur must also be specified.
189 MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
190 Align a, const AAMDNodes &AAInfo = AAMDNodes(),
191 const MDNode *Ranges = nullptr,
194 AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
195 MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LLT type, Align a,
196 const AAMDNodes &AAInfo = AAMDNodes(),
197 const MDNode *Ranges = nullptr,
200 AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
201
202 const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
203
204 /// Return the base address of the memory access. This may either be a normal
205 /// LLVM IR Value, or one of the special values used in CodeGen.
206 /// Special values are those obtained via
207 /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
208 /// other PseudoSourceValue member functions which return objects which stand
209 /// for frame/stack pointer relative references and other special references
210 /// which are not representable in the high-level IR.
211 const Value *getValue() const {
212 return dyn_cast_if_present<const Value *>(PtrInfo.V);
213 }
214
216 return dyn_cast_if_present<const PseudoSourceValue *>(PtrInfo.V);
217 }
218
219 const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
220
221 /// Return the raw flags of the source value, \see Flags.
222 Flags getFlags() const { return FlagVals; }
223
224 /// Bitwise OR the current flags with the given flags.
225 void setFlags(Flags f) { FlagVals |= f; }
226
227 /// For normal values, this is a byte offset added to the base address.
228 /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
229 int64_t getOffset() const { return PtrInfo.Offset; }
230
231 unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
232
233 /// Return the memory type of the memory reference. This should only be relied
234 /// on for GlobalISel G_* operation legalization.
235 LLT getMemoryType() const { return MemoryType; }
236
237 /// Return the size in bytes of the memory reference.
239 return MemoryType.isValid() ? MemoryType.getSizeInBytes() : ~UINT64_C(0);
240 }
241
242 /// Return the size in bits of the memory reference.
244 return MemoryType.isValid() ? MemoryType.getSizeInBits() : ~UINT64_C(0);
245 }
246
247 LLT getType() const {
248 return MemoryType;
249 }
250
251 /// Return the minimum known alignment in bytes of the actual memory
252 /// reference.
253 Align getAlign() const;
254
255 /// Return the minimum known alignment in bytes of the base address, without
256 /// the offset.
257 Align getBaseAlign() const { return BaseAlign; }
258
259 /// Return the AA tags for the memory reference.
260 AAMDNodes getAAInfo() const { return AAInfo; }
261
262 /// Return the range tag for the memory reference.
263 const MDNode *getRanges() const { return Ranges; }
264
265 /// Returns the synchronization scope ID for this memory operation.
267 return static_cast<SyncScope::ID>(AtomicInfo.SSID);
268 }
269
270 /// Return the atomic ordering requirements for this memory operation. For
271 /// cmpxchg atomic operations, return the atomic ordering requirements when
272 /// store occurs.
274 return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
275 }
276
277 /// For cmpxchg atomic operations, return the atomic ordering requirements
278 /// when store does not occur.
280 return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
281 }
282
283 /// Return a single atomic ordering that is at least as strong as both the
284 /// success and failure orderings for an atomic operation. (For operations
285 /// other than cmpxchg, this is equivalent to getSuccessOrdering().)
288 }
289
290 bool isLoad() const { return FlagVals & MOLoad; }
291 bool isStore() const { return FlagVals & MOStore; }
292 bool isVolatile() const { return FlagVals & MOVolatile; }
293 bool isNonTemporal() const { return FlagVals & MONonTemporal; }
294 bool isDereferenceable() const { return FlagVals & MODereferenceable; }
295 bool isInvariant() const { return FlagVals & MOInvariant; }
296
297 /// Returns true if this operation has an atomic ordering requirement of
298 /// unordered or higher, false otherwise.
299 bool isAtomic() const {
301 }
302
303 /// Returns true if this memory operation doesn't have any ordering
304 /// constraints other than normal aliasing. Volatile and (ordered) atomic
305 /// memory operations can't be reordered.
306 bool isUnordered() const {
309 !isVolatile();
310 }
311
312 /// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
313 /// greater alignment. This must only be used when the new alignment applies
314 /// to all users of this MachineMemOperand.
315 void refineAlignment(const MachineMemOperand *MMO);
316
317 /// Change the SourceValue for this MachineMemOperand. This should only be
318 /// used when an object is being relocated and all references to it are being
319 /// updated.
320 void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
321 void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
322 void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
323
324 /// Reset the tracked memory type.
325 void setType(LLT NewTy) {
326 MemoryType = NewTy;
327 }
328
329 /// Support for operator<<.
330 /// @{
332 SmallVectorImpl<StringRef> &SSNs, const LLVMContext &Context,
333 const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const;
334 /// @}
335
336 friend bool operator==(const MachineMemOperand &LHS,
337 const MachineMemOperand &RHS) {
338 return LHS.getValue() == RHS.getValue() &&
339 LHS.getPseudoValue() == RHS.getPseudoValue() &&
340 LHS.getSize() == RHS.getSize() &&
341 LHS.getOffset() == RHS.getOffset() &&
342 LHS.getFlags() == RHS.getFlags() &&
343 LHS.getAAInfo() == RHS.getAAInfo() &&
344 LHS.getRanges() == RHS.getRanges() &&
345 LHS.getAlign() == RHS.getAlign() &&
346 LHS.getAddrSpace() == RHS.getAddrSpace();
347 }
348
349 friend bool operator!=(const MachineMemOperand &LHS,
350 const MachineMemOperand &RHS) {
351 return !(LHS == RHS);
352 }
353};
354
355} // End llvm namespace
356
357#endif
aarch64 promote const
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Atomic ordering constants.
uint64_t Size
const HexagonInstrInfo * TII
Implement a low-level type suitable for MachineInstr level instruction selection.
This file contains the declarations for metadata subclasses.
This file defines the PointerUnion class, which is a discriminated union of pointer types.
raw_pwrite_stream & OS
Value * RHS
Value * LHS
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
Metadata node.
Definition: Metadata.h:1067
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
A description of a memory reference used in the backend.
void setType(LLT NewTy)
Reset the tracked memory type.
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
const PseudoSourceValue * getPseudoValue() const
LLT getMemoryType() const
Return the memory type of the memory reference.
unsigned getAddrSpace() const
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
const MDNode * getRanges() const
Return the range tag for the memory reference.
void setValue(const Value *NewSV)
Change the SourceValue for this MachineMemOperand.
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
uint64_t getSize() const
Return the size in bytes of the memory reference.
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
const void * getOpaqueValue() const
friend bool operator!=(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
AtomicOrdering getMergedOrdering() const
Return a single atomic ordering that is at least as strong as both the success and failure orderings ...
void setOffset(int64_t NewOffset)
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
void setFlags(Flags f)
Bitwise OR the current flags with the given flags.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
friend bool operator==(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
void setValue(const PseudoSourceValue *NewSV)
const Value * getValue() const
Return the base address of the memory access.
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Manage lifetime of a slot tracker for printing IR.
A discriminated union of two or more pointer types, with the discriminator in the low bit of the poin...
Definition: PointerUnion.h:118
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
Special value supplied for machine level alias analysis.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
TargetInstrInfo - Interface to description of machine instruction set.
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:57
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
AddressSpace
Definition: NVPTXBaseInfo.h:21
AtomicOrdering getMergedAtomicOrdering(AtomicOrdering AO, AtomicOrdering Other)
Return a single atomic ordering that is at least as strong as both the AO and Other orderings for an ...
AtomicOrdering
Atomic ordering for LLVM's memory model.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:760
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
MachinePointerInfo(const PseudoSourceValue *v, int64_t offset=0, uint8_t ID=0)
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
MachinePointerInfo(unsigned AddressSpace=0, int64_t offset=0)
int64_t Offset
Offset - This is an offset from the base Value*.
MachinePointerInfo(PointerUnion< const Value *, const PseudoSourceValue * > v, int64_t offset=0, uint8_t ID=0)
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.