LLVM  16.0.0git
MachineMemOperand.h
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1 //==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the declaration of the MachineMemOperand class, which is a
10 // description of a memory reference. It is used to help track dependencies
11 // in the backend.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
16 #define LLVM_CODEGEN_MACHINEMEMOPERAND_H
17 
18 #include "llvm/ADT/BitmaskEnum.h"
19 #include "llvm/ADT/PointerUnion.h"
21 #include "llvm/IR/DerivedTypes.h"
22 #include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
24 #include "llvm/Support/DataTypes.h"
26 
27 namespace llvm {
28 
29 class FoldingSetNodeID;
30 class MDNode;
31 class raw_ostream;
32 class MachineFunction;
33 class ModuleSlotTracker;
34 class TargetInstrInfo;
35 
36 /// This class contains a discriminated union of information about pointers in
37 /// memory operands, relating them back to LLVM IR or to virtual locations (such
38 /// as frame indices) that are exposed during codegen.
40  /// This is the IR pointer value for the access, or it is null if unknown.
42 
43  /// Offset - This is an offset from the base Value*.
44  int64_t Offset;
45 
46  unsigned AddrSpace = 0;
47 
48  uint8_t StackID;
49 
50  explicit MachinePointerInfo(const Value *v, int64_t offset = 0,
51  uint8_t ID = 0)
52  : V(v), Offset(offset), StackID(ID) {
53  AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0;
54  }
55 
56  explicit MachinePointerInfo(const PseudoSourceValue *v, int64_t offset = 0,
57  uint8_t ID = 0)
58  : V(v), Offset(offset), StackID(ID) {
59  AddrSpace = v ? v->getAddressSpace() : 0;
60  }
61 
62  explicit MachinePointerInfo(unsigned AddressSpace = 0, int64_t offset = 0)
63  : V((const Value *)nullptr), Offset(offset), AddrSpace(AddressSpace),
64  StackID(0) {}
65 
68  int64_t offset = 0,
69  uint8_t ID = 0)
70  : V(v), Offset(offset), StackID(ID) {
71  if (V) {
72  if (const auto *ValPtr = V.dyn_cast<const Value*>())
73  AddrSpace = ValPtr->getType()->getPointerAddressSpace();
74  else
76  }
77  }
78 
80  if (V.isNull())
82  if (V.is<const Value*>())
83  return MachinePointerInfo(V.get<const Value*>(), Offset + O, StackID);
84  return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset + O,
85  StackID);
86  }
87 
88  /// Return true if memory region [V, V+Offset+Size) is known to be
89  /// dereferenceable.
90  bool isDereferenceable(unsigned Size, LLVMContext &C,
91  const DataLayout &DL) const;
92 
93  /// Return the LLVM IR address space number that this pointer points into.
94  unsigned getAddrSpace() const;
95 
96  /// Return a MachinePointerInfo record that refers to the constant pool.
98 
99  /// Return a MachinePointerInfo record that refers to the specified
100  /// FrameIndex.
102  int64_t Offset = 0);
103 
104  /// Return a MachinePointerInfo record that refers to a jump table entry.
106 
107  /// Return a MachinePointerInfo record that refers to a GOT entry.
109 
110  /// Stack pointer relative access.
112  uint8_t ID = 0);
113 
114  /// Stack memory without other information.
116 };
117 
118 
119 //===----------------------------------------------------------------------===//
120 /// A description of a memory reference used in the backend.
121 /// Instead of holding a StoreInst or LoadInst, this class holds the address
122 /// Value of the reference along with a byte size and offset. This allows it
123 /// to describe lowered loads and stores. Also, the special PseudoSourceValue
124 /// objects can be used to represent loads and stores to memory locations
125 /// that aren't explicit in the regular LLVM IR.
126 ///
128 public:
129  /// Flags values. These may be or'd together.
130  enum Flags : uint16_t {
131  // No flags set.
132  MONone = 0,
133  /// The memory access reads data.
134  MOLoad = 1u << 0,
135  /// The memory access writes data.
136  MOStore = 1u << 1,
137  /// The memory access is volatile.
138  MOVolatile = 1u << 2,
139  /// The memory access is non-temporal.
140  MONonTemporal = 1u << 3,
141  /// The memory access is dereferenceable (i.e., doesn't trap).
142  MODereferenceable = 1u << 4,
143  /// The memory access always returns the same value (or traps).
144  MOInvariant = 1u << 5,
145 
146  // Reserved for use by target-specific passes.
147  // Targets may override getSerializableMachineMemOperandTargetFlags() to
148  // enable MIR serialization/parsing of these flags. If more of these flags
149  // are added, the MIR printing/parsing code will need to be updated as well.
150  MOTargetFlag1 = 1u << 6,
151  MOTargetFlag2 = 1u << 7,
152  MOTargetFlag3 = 1u << 8,
153 
154  LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
155  };
156 
157 private:
158  /// Atomic information for this memory operation.
159  struct MachineAtomicInfo {
160  /// Synchronization scope ID for this memory operation.
161  unsigned SSID : 8; // SyncScope::ID
162  /// Atomic ordering requirements for this memory operation. For cmpxchg
163  /// atomic operations, atomic ordering requirements when store occurs.
164  unsigned Ordering : 4; // enum AtomicOrdering
165  /// For cmpxchg atomic operations, atomic ordering requirements when store
166  /// does not occur.
167  unsigned FailureOrdering : 4; // enum AtomicOrdering
168  };
169 
170  MachinePointerInfo PtrInfo;
171 
172  /// Track the memory type of the access. An access size which is unknown or
173  /// too large to be represented by LLT should use the invalid LLT.
174  LLT MemoryType;
175 
176  Flags FlagVals;
177  Align BaseAlign;
178  MachineAtomicInfo AtomicInfo;
179  AAMDNodes AAInfo;
180  const MDNode *Ranges;
181 
182 public:
183  /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
184  /// size, and base alignment. For atomic operations the synchronization scope
185  /// and atomic ordering requirements must also be specified. For cmpxchg
186  /// atomic operations the atomic ordering requirements when store does not
187  /// occur must also be specified.
188  MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
189  Align a, const AAMDNodes &AAInfo = AAMDNodes(),
190  const MDNode *Ranges = nullptr,
193  AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
194  MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, LLT type, Align a,
195  const AAMDNodes &AAInfo = AAMDNodes(),
196  const MDNode *Ranges = nullptr,
199  AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
200 
201  const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
202 
203  /// Return the base address of the memory access. This may either be a normal
204  /// LLVM IR Value, or one of the special values used in CodeGen.
205  /// Special values are those obtained via
206  /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
207  /// other PseudoSourceValue member functions which return objects which stand
208  /// for frame/stack pointer relative references and other special references
209  /// which are not representable in the high-level IR.
210  const Value *getValue() const { return PtrInfo.V.dyn_cast<const Value*>(); }
211 
213  return PtrInfo.V.dyn_cast<const PseudoSourceValue*>();
214  }
215 
216  const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
217 
218  /// Return the raw flags of the source value, \see Flags.
219  Flags getFlags() const { return FlagVals; }
220 
221  /// Bitwise OR the current flags with the given flags.
222  void setFlags(Flags f) { FlagVals |= f; }
223 
224  /// For normal values, this is a byte offset added to the base address.
225  /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
226  int64_t getOffset() const { return PtrInfo.Offset; }
227 
228  unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
229 
230  /// Return the memory type of the memory reference. This should only be relied
231  /// on for GlobalISel G_* operation legalization.
232  LLT getMemoryType() const { return MemoryType; }
233 
234  /// Return the size in bytes of the memory reference.
235  uint64_t getSize() const {
236  return MemoryType.isValid() ? MemoryType.getSizeInBytes() : ~UINT64_C(0);
237  }
238 
239  /// Return the size in bits of the memory reference.
241  return MemoryType.isValid() ? MemoryType.getSizeInBits() : ~UINT64_C(0);
242  }
243 
244  LLT getType() const {
245  return MemoryType;
246  }
247 
248  /// Return the minimum known alignment in bytes of the actual memory
249  /// reference.
250  Align getAlign() const;
251 
252  /// Return the minimum known alignment in bytes of the base address, without
253  /// the offset.
254  Align getBaseAlign() const { return BaseAlign; }
255 
256  /// Return the AA tags for the memory reference.
257  AAMDNodes getAAInfo() const { return AAInfo; }
258 
259  /// Return the range tag for the memory reference.
260  const MDNode *getRanges() const { return Ranges; }
261 
262  /// Returns the synchronization scope ID for this memory operation.
264  return static_cast<SyncScope::ID>(AtomicInfo.SSID);
265  }
266 
267  /// Return the atomic ordering requirements for this memory operation. For
268  /// cmpxchg atomic operations, return the atomic ordering requirements when
269  /// store occurs.
271  return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
272  }
273 
274  /// For cmpxchg atomic operations, return the atomic ordering requirements
275  /// when store does not occur.
277  return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
278  }
279 
280  /// Return a single atomic ordering that is at least as strong as both the
281  /// success and failure orderings for an atomic operation. (For operations
282  /// other than cmpxchg, this is equivalent to getSuccessOrdering().)
285  }
286 
287  bool isLoad() const { return FlagVals & MOLoad; }
288  bool isStore() const { return FlagVals & MOStore; }
289  bool isVolatile() const { return FlagVals & MOVolatile; }
290  bool isNonTemporal() const { return FlagVals & MONonTemporal; }
291  bool isDereferenceable() const { return FlagVals & MODereferenceable; }
292  bool isInvariant() const { return FlagVals & MOInvariant; }
293 
294  /// Returns true if this operation has an atomic ordering requirement of
295  /// unordered or higher, false otherwise.
296  bool isAtomic() const {
298  }
299 
300  /// Returns true if this memory operation doesn't have any ordering
301  /// constraints other than normal aliasing. Volatile and (ordered) atomic
302  /// memory operations can't be reordered.
303  bool isUnordered() const {
306  !isVolatile();
307  }
308 
309  /// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
310  /// greater alignment. This must only be used when the new alignment applies
311  /// to all users of this MachineMemOperand.
312  void refineAlignment(const MachineMemOperand *MMO);
313 
314  /// Change the SourceValue for this MachineMemOperand. This should only be
315  /// used when an object is being relocated and all references to it are being
316  /// updated.
317  void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
318  void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
319  void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
320 
321  /// Reset the tracked memory type.
322  void setType(LLT NewTy) {
323  MemoryType = NewTy;
324  }
325 
326  /// Profile - Gather unique data for the object.
327  ///
328  void Profile(FoldingSetNodeID &ID) const;
329 
330  /// Support for operator<<.
331  /// @{
332  void print(raw_ostream &OS, ModuleSlotTracker &MST,
334  const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const;
335  /// @}
336 
337  friend bool operator==(const MachineMemOperand &LHS,
338  const MachineMemOperand &RHS) {
339  return LHS.getValue() == RHS.getValue() &&
340  LHS.getPseudoValue() == RHS.getPseudoValue() &&
341  LHS.getSize() == RHS.getSize() &&
342  LHS.getOffset() == RHS.getOffset() &&
343  LHS.getFlags() == RHS.getFlags() &&
344  LHS.getAAInfo() == RHS.getAAInfo() &&
345  LHS.getRanges() == RHS.getRanges() &&
346  LHS.getAlign() == RHS.getAlign() &&
347  LHS.getAddrSpace() == RHS.getAddrSpace();
348  }
349 
350  friend bool operator!=(const MachineMemOperand &LHS,
351  const MachineMemOperand &RHS) {
352  return !(LHS == RHS);
353  }
354 };
355 
356 } // End llvm namespace
357 
358 #endif
llvm::MachineMemOperand::setValue
void setValue(const Value *NewSV)
Change the SourceValue for this MachineMemOperand.
Definition: MachineMemOperand.h:317
llvm::MachineMemOperand::MachineMemOperand
MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s, Align a, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
Construct a MachineMemOperand object with the specified PtrInfo, flags, size, and base alignment.
Definition: MachineOperand.cpp:1060
llvm::MachineMemOperand::isStore
bool isStore() const
Definition: MachineMemOperand.h:288
llvm::PointerUnion::isNull
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Definition: PointerUnion.h:142
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::MachineMemOperand::getAlign
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
Definition: MachineOperand.cpp:1099
llvm::MachinePointerInfo::StackID
uint8_t StackID
Definition: MachineMemOperand.h:48
AtomicOrdering.h
LLVM_MARK_AS_BITMASK_ENUM
#define LLVM_MARK_AS_BITMASK_ENUM(LargestValue)
LLVM_MARK_AS_BITMASK_ENUM lets you opt in an individual enum type so you can perform bitwise operatio...
Definition: BitmaskEnum.h:41
llvm::MachineMemOperand::print
void print(raw_ostream &OS, ModuleSlotTracker &MST, SmallVectorImpl< StringRef > &SSNs, const LLVMContext &Context, const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const
Support for operator<<.
Definition: MachineOperand.cpp:1103
llvm::getMergedAtomicOrdering
AtomicOrdering getMergedAtomicOrdering(AtomicOrdering AO, AtomicOrdering Other)
Return a single atomic ordering that is at least as strong as both the AO and Other orderings for an ...
Definition: AtomicOrdering.h:138
llvm::MachinePointerInfo::getConstantPool
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
Definition: MachineOperand.cpp:1012
llvm::MachinePointerInfo::getUnknownStack
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
Definition: MachineOperand.cpp:1036
llvm::MachineMemOperand::isLoad
bool isLoad() const
Definition: MachineMemOperand.h:287
llvm::MachineMemOperand::getOffset
int64_t getOffset() const
For normal values, this is a byte offset added to the base address.
Definition: MachineMemOperand.h:226
llvm::Type::getPointerAddressSpace
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
Definition: DerivedTypes.h:729
llvm::MachineMemOperand::MOInvariant
@ MOInvariant
The memory access always returns the same value (or traps).
Definition: MachineMemOperand.h:144
llvm::SyncScope::System
@ System
Synchronized with respect to all concurrently executing threads.
Definition: LLVMContext.h:57
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const PseudoSourceValue *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:56
llvm::MachineMemOperand::MOTargetFlag2
@ MOTargetFlag2
Definition: MachineMemOperand.h:151
llvm::MachineMemOperand::getSizeInBits
uint64_t getSizeInBits() const
Return the size in bits of the memory reference.
Definition: MachineMemOperand.h:240
llvm::AAMDNodes
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
Definition: Metadata.h:652
llvm::MachineMemOperand::getOpaqueValue
const void * getOpaqueValue() const
Definition: MachineMemOperand.h:216
llvm::MachineMemOperand
A description of a memory reference used in the backend.
Definition: MachineMemOperand.h:127
llvm::MachineMemOperand::MODereferenceable
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
Definition: MachineMemOperand.h:142
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
llvm::MachineMemOperand::isInvariant
bool isInvariant() const
Definition: MachineMemOperand.h:292
llvm::MachineMemOperand::getAAInfo
AAMDNodes getAAInfo() const
Return the AA tags for the memory reference.
Definition: MachineMemOperand.h:257
llvm::MachineMemOperand::isUnordered
bool isUnordered() const
Returns true if this memory operation doesn't have any ordering constraints other than normal aliasin...
Definition: MachineMemOperand.h:303
llvm::ModuleSlotTracker
Manage lifetime of a slot tracker for printing IR.
Definition: ModuleSlotTracker.h:44
llvm::PointerUnion::get
T get() const
Returns the value of the specified pointer type.
Definition: PointerUnion.h:155
llvm::MachinePointerInfo::getJumpTable
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Definition: MachineOperand.cpp:1023
llvm::PointerUnion::is
bool is() const
Test if the Union currently holds the type matching T.
Definition: PointerUnion.h:150
a
=0.0 ? 0.0 :(a > 0.0 ? 1.0 :-1.0) a
Definition: README.txt:489
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::MachinePointerInfo::Offset
int64_t Offset
Offset - This is an offset from the base Value*.
Definition: MachineMemOperand.h:44
llvm::AVR::getAddressSpace
AddressSpace getAddressSpace(T *V)
Definition: AVR.h:64
llvm::MachineMemOperand::getPointerInfo
const MachinePointerInfo & getPointerInfo() const
Definition: MachineMemOperand.h:201
LHS
Value * LHS
Definition: X86PartialReduction.cpp:75
llvm::MachineMemOperand::MOTargetFlag1
@ MOTargetFlag1
Definition: MachineMemOperand.h:150
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::MachineMemOperand::getBaseAlign
Align getBaseAlign() const
Return the minimum known alignment in bytes of the base address, without the offset.
Definition: MachineMemOperand.h:254
f
Itanium Name Demangler i e convert the string _Z1fv into f()". You can also use the CRTP base ManglingParser to perform some simple analysis on the mangled name
llvm::MachineMemOperand::getAddrSpace
unsigned getAddrSpace() const
Definition: MachineMemOperand.h:228
llvm::MachineMemOperand::getValue
const Value * getValue() const
Return the base address of the memory access.
Definition: MachineMemOperand.h:210
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::MachinePointerInfo::getGOT
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
Definition: MachineOperand.cpp:1027
PseudoSourceValue.h
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
llvm::PseudoSourceValue
Special value supplied for machine level alias analysis.
Definition: PseudoSourceValue.h:35
Align
uint64_t Align
Definition: ELFObjHandler.cpp:81
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(const Value *v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:50
llvm::MachineMemOperand::getSyncScopeID
SyncScope::ID getSyncScopeID() const
Returns the synchronization scope ID for this memory operation.
Definition: MachineMemOperand.h:263
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
LowLevelTypeImpl.h
llvm::MachineMemOperand::setFlags
void setFlags(Flags f)
Bitwise OR the current flags with the given flags.
Definition: MachineMemOperand.h:222
llvm::MachineMemOperand::Profile
void Profile(FoldingSetNodeID &ID) const
Profile - Gather unique data for the object.
Definition: MachineOperand.cpp:1072
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(unsigned AddressSpace=0, int64_t offset=0)
Definition: MachineMemOperand.h:62
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::RISCVFenceField::O
@ O
Definition: RISCVBaseInfo.h:264
type
AMD64 Optimization Manual has some nice information about optimizing integer multiplication by a constant How much of it applies to Intel s X86 implementation There are definite trade offs to xmm0 cvttss2siq rdx jb L3 subss xmm0 rax cvttss2siq rdx xorq rdx rax ret instead of xmm1 cvttss2siq rcx movaps xmm2 subss xmm2 cvttss2siq rax rdx xorq rax ucomiss xmm0 cmovb rax ret Seems like the jb branch has high likelihood of being taken It would have saved a few instructions It s not possible to reference and DH registers in an instruction requiring REX prefix divb and mulb both produce results in AH If isel emits a CopyFromReg which gets turned into a movb and that can be allocated a r8b r15b To get around isel emits a CopyFromReg from AX and then right shift it down by and truncate it It s not pretty but it works We need some register allocation magic to make the hack go which would often require a callee saved register Callees usually need to keep this value live for most of their body so it doesn t add a significant burden on them We currently implement this in however this is suboptimal because it means that it would be quite awkward to implement the optimization for callers A better implementation would be to relax the LLVM IR rules for sret arguments to allow a function with an sret argument to have a non void return type
Definition: README-X86-64.txt:70
llvm::MachinePointerInfo::isDereferenceable
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
Definition: MachineOperand.cpp:997
llvm::MachineMemOperand::isDereferenceable
bool isDereferenceable() const
Definition: MachineMemOperand.h:291
uint64_t
const
aarch64 promote const
Definition: AArch64PromoteConstant.cpp:232
s
multiplies can be turned into SHL s
Definition: README.txt:370
llvm::PointerUnion::dyn_cast
T dyn_cast() const
Returns the current pointer if it is of the specified pointer type, otherwise returns null.
Definition: PointerUnion.h:162
llvm::MachinePointerInfo
This class contains a discriminated union of information about pointers in memory operands,...
Definition: MachineMemOperand.h:39
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::SyncScope::ID
uint8_t ID
Definition: LLVMContext.h:46
llvm::AtomicOrdering::Unordered
@ Unordered
llvm::MachineMemOperand::setOffset
void setOffset(int64_t NewOffset)
Definition: MachineMemOperand.h:319
llvm::MachineMemOperand::Flags
Flags
Flags values. These may be or'd together.
Definition: MachineMemOperand.h:130
llvm::PseudoSourceValue::getAddressSpace
unsigned getAddressSpace() const
Definition: PseudoSourceValue.h:73
llvm::MachineMemOperand::getSuccessOrdering
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
Definition: MachineMemOperand.h:270
llvm::MachineMemOperand::MONonTemporal
@ MONonTemporal
The memory access is non-temporal.
Definition: MachineMemOperand.h:140
PointerUnion.h
llvm::MachineMemOperand::getMemoryType
LLT getMemoryType() const
Return the memory type of the memory reference.
Definition: MachineMemOperand.h:232
llvm::MDNode
Metadata node.
Definition: Metadata.h:944
llvm::MachineMemOperand::getType
LLT getType() const
Definition: MachineMemOperand.h:244
llvm::MachinePointerInfo::getWithOffset
MachinePointerInfo getWithOffset(int64_t O) const
Definition: MachineMemOperand.h:79
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::MachineMemOperand::MOTargetFlag3
@ MOTargetFlag3
Definition: MachineMemOperand.h:152
llvm::MachinePointerInfo::V
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
Definition: MachineMemOperand.h:41
llvm::Value::getType
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
BitmaskEnum.h
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachinePointerInfo::AddrSpace
unsigned AddrSpace
Definition: MachineMemOperand.h:46
llvm::FoldingSetNodeID
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
Definition: FoldingSet.h:318
llvm::MachineMemOperand::MOVolatile
@ MOVolatile
The memory access is volatile.
Definition: MachineMemOperand.h:138
llvm::MachinePointerInfo::getAddrSpace
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
Definition: MachineOperand.cpp:993
llvm::MachineMemOperand::MOLoad
@ MOLoad
The memory access reads data.
Definition: MachineMemOperand.h:134
llvm::PointerUnion< const Value *, const PseudoSourceValue * >
llvm::MachineMemOperand::isVolatile
bool isVolatile() const
Definition: MachineMemOperand.h:289
uint16_t
llvm::MachineMemOperand::getSize
uint64_t getSize() const
Return the size in bytes of the memory reference.
Definition: MachineMemOperand.h:235
llvm::MachineMemOperand::operator==
friend bool operator==(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
Definition: MachineMemOperand.h:337
llvm::MachineMemOperand::isAtomic
bool isAtomic() const
Returns true if this operation has an atomic ordering requirement of unordered or higher,...
Definition: MachineMemOperand.h:296
llvm::MachineMemOperand::getMergedOrdering
AtomicOrdering getMergedOrdering() const
Return a single atomic ordering that is at least as strong as both the success and failure orderings ...
Definition: MachineMemOperand.h:283
llvm::MachineMemOperand::refineAlignment
void refineAlignment(const MachineMemOperand *MMO)
Update this MachineMemOperand to reflect the alignment of MMO, if it has a greater alignment.
Definition: MachineOperand.cpp:1080
llvm::MachineMemOperand::MOStore
@ MOStore
The memory access writes data.
Definition: MachineMemOperand.h:136
llvm::MachineMemOperand::setValue
void setValue(const PseudoSourceValue *NewSV)
Definition: MachineMemOperand.h:318
llvm::MachineMemOperand::operator!=
friend bool operator!=(const MachineMemOperand &LHS, const MachineMemOperand &RHS)
Definition: MachineMemOperand.h:350
llvm::MachineMemOperand::setType
void setType(LLT NewTy)
Reset the tracked memory type.
Definition: MachineMemOperand.h:322
llvm::MachineFrameInfo
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
Definition: MachineFrameInfo.h:105
llvm::MachinePointerInfo::getFixedStack
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
Definition: MachineOperand.cpp:1018
llvm::SmallVectorImpl< StringRef >
llvm::MachineMemOperand::getFailureOrdering
AtomicOrdering getFailureOrdering() const
For cmpxchg atomic operations, return the atomic ordering requirements when store does not occur.
Definition: MachineMemOperand.h:276
DataTypes.h
DerivedTypes.h
llvm::MachineMemOperand::isNonTemporal
bool isNonTemporal() const
Definition: MachineMemOperand.h:290
llvm::MachineMemOperand::getRanges
const MDNode * getRanges() const
Return the range tag for the memory reference.
Definition: MachineMemOperand.h:260
Value.h
llvm::MachineMemOperand::MONone
@ MONone
Definition: MachineMemOperand.h:132
llvm::MachinePointerInfo::getStack
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
Definition: MachineOperand.cpp:1031
llvm::MachinePointerInfo::MachinePointerInfo
MachinePointerInfo(PointerUnion< const Value *, const PseudoSourceValue * > v, int64_t offset=0, uint8_t ID=0)
Definition: MachineMemOperand.h:66
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::MachineMemOperand::getFlags
Flags getFlags() const
Return the raw flags of the source value,.
Definition: MachineMemOperand.h:219
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::MachineMemOperand::getPseudoValue
const PseudoSourceValue * getPseudoValue() const
Definition: MachineMemOperand.h:212
llvm::LLT
Definition: LowLevelTypeImpl.h:39