LLVM  10.0.0svn
Classes | Macros | Enumerations | Functions | Variables
AMDGPUAsmParser.cpp File Reference
#include "AMDGPU.h"
#include "AMDKernelCodeT.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "MCTargetDesc/AMDGPUTargetStreamer.h"
#include "SIDefines.h"
#include "SIInstrInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUAsmUtils.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "Utils/AMDKernelCodeTUtils.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCAsmParserExtension.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/AMDGPUMetadata.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/SMLoc.h"
#include "llvm/Support/TargetParser.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstring>
#include <iterator>
#include <map>
#include <memory>
#include <string>
#include "AMDGPUGenAsmMatcher.inc"

Go to the source code of this file.

Classes

struct  RegInfo
 

Macros

#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE)
 
#define GET_REGISTER_MATCHER
 
#define GET_MATCHER_IMPLEMENTATION
 
#define GET_MNEMONIC_SPELL_CHECKER
 
Auto-generated Match Functions

{

#define GET_ASSEMBLER_HEADER
 

Enumerations

enum  RegisterKind
 

Functions

static const fltSemantics * getFltSemantics (unsigned Size)
 
static const fltSemantics * getFltSemantics (MVT VT)
 
static const fltSemantics * getOpFltSemantics (uint8_t OperandType)
 
static bool canLosslesslyConvertToFPType (APFloat &FPLiteral, MVT VT)
 
static bool isSafeTruncation (int64_t Val, unsigned Size)
 
static bool isInlineValue (unsigned Reg)
 
static int getRegClass (RegisterKind Is, unsigned RegWidth)
 
static unsigned getSpecialRegForName (StringRef RegName)
 
static bool isRegularReg (RegisterKind Kind)
 
static const RegInfo * getRegularRegInfo (StringRef Str)
 
static bool getRegNum (StringRef Str, unsigned &Num)
 
static bool IsRevOpcode (const unsigned Opcode)
 
static std::string AMDGPUMnemonicSpellCheck (StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)
 
static void addOptionalImmOperand (MCInst &Inst, const OperandVector &Operands, AMDGPUAsmParser::OptionalImmIndexMap &OptionalIdx, AMDGPUOperand::ImmTy ImmT, int64_t Default=0)
 
static bool encodeCnt (const AMDGPU::IsaVersion ISA, int64_t &IntVal, int64_t CntVal, bool Saturate, unsigned(*encode)(const IsaVersion &Version, unsigned, unsigned), unsigned(*decode)(const IsaVersion &Version, unsigned))
 
static LLVM_READNONE unsigned encodeBitmaskPerm (const unsigned AndMask, const unsigned OrMask, const unsigned XorMask)
 
static bool ConvertOmodMul (int64_t &Mul)
 
static bool ConvertOmodDiv (int64_t &Div)
 
static bool ConvertBoundCtrl (int64_t &BoundCtrl)
 
static bool isRegOrImmWithInputMods (const MCInstrDesc &Desc, unsigned OpNum)
 
void LLVMInitializeAMDGPUAsmParser ()
 Force static initialization. More...
 

Variables

static constexpr RegInfo RegularRegisters []
 
static const OptionalOperand AMDGPUOptionalOperandTable []
 

Macro Definition Documentation

◆ GET_ASSEMBLER_HEADER

#define GET_ASSEMBLER_HEADER

Definition at line 1012 of file AMDGPUAsmParser.cpp.

◆ GET_MATCHER_IMPLEMENTATION

#define GET_MATCHER_IMPLEMENTATION

Definition at line 6949 of file AMDGPUAsmParser.cpp.

◆ GET_MNEMONIC_SPELL_CHECKER

#define GET_MNEMONIC_SPELL_CHECKER

Definition at line 6950 of file AMDGPUAsmParser.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 6948 of file AMDGPUAsmParser.cpp.

◆ PARSE_BITS_ENTRY

#define PARSE_BITS_ENTRY (   FIELD,
  ENTRY,
  VALUE,
  RANGE 
)
Value:
if (!isUInt<ENTRY##_WIDTH>(VALUE)) \
return OutOfRangeError(RANGE); \
AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);
FIELD
#define FIELD(name)
Definition: AMDKernelCodeTInfo.h:21
ENTRY
#define ENTRY(ASMNAME, ENUM)

Referenced by IsRevOpcode().

Enumeration Type Documentation

◆ RegisterKind

enum RegisterKind

Definition at line 72 of file AMDGPUAsmParser.cpp.

Function Documentation

◆ addOptionalImmOperand()

static void addOptionalImmOperand ( MCInst &  Inst,
const OperandVector &  Operands,
AMDGPUAsmParser::OptionalImmIndexMap &  OptionalIdx,
AMDGPUOperand::ImmTy  ImmT,
int64_t  Default = 0 
)
static

Definition at line 4639 of file AMDGPUAsmParser.cpp.

References llvm::MCInst::addOperand(), assert(), llvm::AsmToken::Colon, llvm::MCOperand::createImm(), llvm::MCOperand::createReg(), llvm::numbers::e, llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::AsmToken::Identifier, llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MCOperand::setReg(), llvm::SmallVectorBase::size(), and llvm::MCInst::size().

Referenced by encodeBitmaskPerm(), and isRegOrImmWithInputMods().

◆ AMDGPUMnemonicSpellCheck()

static std::string AMDGPUMnemonicSpellCheck ( StringRef  S,
const FeatureBitset &  FBS,
unsigned  VariantID = 0 
)
static

Referenced by IsRevOpcode().

◆ canLosslesslyConvertToFPType()

static bool canLosslesslyConvertToFPType ( APFloat &  FPLiteral,
MVT  VT 
)
static

Definition at line 1504 of file AMDGPUAsmParser.cpp.

◆ ConvertBoundCtrl()

static bool ConvertBoundCtrl ( int64_t &  BoundCtrl)
static

Definition at line 6021 of file AMDGPUAsmParser.cpp.

◆ ConvertOmodDiv()

static bool ConvertOmodDiv ( int64_t &  Div)
static

Definition at line 6007 of file AMDGPUAsmParser.cpp.

◆ ConvertOmodMul()

static bool ConvertOmodMul ( int64_t &  Mul)
static

Definition at line 5999 of file AMDGPUAsmParser.cpp.

◆ encodeBitmaskPerm()

static LLVM_READNONE unsigned encodeBitmaskPerm ( const unsigned  AndMask,
const unsigned  OrMask,
const unsigned  XorMask 
)
static

Definition at line 5418 of file AMDGPUAsmParser.cpp.

References addOptionalImmOperand(), assert(), llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT, llvm::AMDGPU::Swizzle::BITMASK_MAX, llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT, llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC, llvm::AMDGPU::Swizzle::BITMASK_WIDTH, llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT, llvm::AsmToken::Colon, llvm::AsmToken::Comma, llvm::numbers::e, E, llvm::AMDGPU::getMUBUFNoLdsInst(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInst::getOpcode(), I, llvm::AMDGPU::Swizzle::ID_BITMASK_PERM, llvm::AMDGPU::Swizzle::ID_BROADCAST, llvm::AMDGPU::VGPRIndexMode::ID_MAX, llvm::AMDGPU::VGPRIndexMode::ID_MIN, llvm::AMDGPU::Swizzle::ID_QUAD_PERM, llvm::AMDGPU::Swizzle::ID_REVERSE, llvm::AMDGPU::Swizzle::ID_SWAP, llvm::AsmToken::Identifier, llvm::AMDGPU::SendMsg::IdSymbolic, llvm::AMDGPU::isGFX10(), llvm::isPowerOf2_64(), llvm::isUInt< 16 >(), llvm::isUInt< 32 >(), llvm::isUInt< 8 >(), llvm::AMDGPU::Swizzle::LANE_MAX, llvm::AMDGPU::Swizzle::LANE_NUM, llvm::AMDGPU::Swizzle::LANE_SHIFT, llvm_unreachable, llvm::AsmToken::LParen, llvm::BitmaskEnumDetail::Mask(), llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, Mode, llvm::AMDGPU::VGPRIndexMode::OFF, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPU::Swizzle::QUAD_PERM_ENC, llvm::AsmToken::RParen, llvm::MCInst::setOpcode(), llvm::SmallVectorBase::size(), and llvm::StringRef::size().

◆ encodeCnt()

static bool encodeCnt ( const AMDGPU::IsaVersion  ISA,
int64_t &  IntVal,
int64_t  CntVal,
bool  Saturate,
unsigned(*)(const IsaVersion &Version, unsigned, unsigned)  encode,
unsigned(*)(const IsaVersion &Version, unsigned)  decode 
)
static

Definition at line 4854 of file AMDGPUAsmParser.cpp.

References llvm::AsmToken::Amp, llvm::StringSwitch< T, R >::Case(), llvm::AsmToken::Comma, llvm::StringRef::data(), decode(), llvm::AMDGPU::decodeExpcnt(), llvm::AMDGPU::decodeLgkmcnt(), llvm::AMDGPU::decodeVmcnt(), llvm::StringSwitch< T, R >::Default(), llvm::StringRef::drop_back(), llvm::StringRef::drop_front(), llvm::encode(), llvm::AMDGPU::encodeExpcnt(), llvm::AMDGPU::Hwreg::encodeHwreg(), llvm::AMDGPU::encodeLgkmcnt(), llvm::AMDGPU::SendMsg::encodeMsg(), llvm::AMDGPU::encodeVmcnt(), llvm::AsmToken::EndOfStatement, llvm::StringRef::endswith(), llvm::AsmToken::Error, llvm::Failed(), llvm::StringRef::getAsInteger(), llvm::getCPU(), llvm::SMLoc::getFromPointer(), llvm::AMDGPU::Hwreg::getHwregId(), llvm::AMDGPU::getIsaVersion(), llvm::AsmToken::getKind(), llvm::AMDGPU::SendMsg::getMsgId(), llvm::AMDGPU::SendMsg::getMsgOpId(), llvm::AsmToken::getString(), llvm::getToken(), llvm::AMDGPU::getWaitcntBitMask(), llvm::AMDGPU::SendMsg::ID_UNKNOWN_, llvm::AsmToken::Identifier, llvm::tgtok::IntVal, llvm::AsmToken::is(), llvm::AMDGPU::isGFX10(), llvm::isUInt< 16 >(), llvm::AMDGPU::Hwreg::isValidHwreg(), llvm::AMDGPU::Hwreg::isValidHwregOffset(), llvm::AMDGPU::Hwreg::isValidHwregWidth(), llvm::AMDGPU::SendMsg::isValidMsgId(), llvm::AMDGPU::SendMsg::isValidMsgOp(), llvm::AMDGPU::SendMsg::isValidMsgStream(), LLVM_READNONE, llvm::AsmToken::LParen, llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::AMDGPU::SendMsg::msgRequiresOp(), llvm::AMDGPU::SendMsg::msgSupportsStream(), llvm::AMDGPU::Hwreg::OFFSET_DEFAULT_, llvm::AMDGPU::SendMsg::OP_NONE_, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AsmToken::RParen, llvm::ArrayRef< T >::size(), llvm::StringRef::startswith(), llvm::AMDGPU::SendMsg::STREAM_ID_NONE_, llvm::FPOpFusion::Strict, llvm::AsmToken::String, llvm::StringRef::take_back(), and llvm::AMDGPU::Hwreg::WIDTH_DEFAULT_.

◆ getFltSemantics() [1/2]

static const fltSemantics* getFltSemantics ( unsigned  Size)
static

Definition at line 1451 of file AMDGPUAsmParser.cpp.

◆ getFltSemantics() [2/2]

static const fltSemantics* getFltSemantics ( MVT  VT)
static

Definition at line 1464 of file AMDGPUAsmParser.cpp.

◆ getOpFltSemantics()

static const fltSemantics* getOpFltSemantics ( uint8_t  OperandType)
static

Definition at line 1468 of file AMDGPUAsmParser.cpp.

◆ getRegClass()

static int getRegClass ( RegisterKind  Is,
unsigned  RegWidth 
)
static

Definition at line 1894 of file AMDGPUAsmParser.cpp.

Referenced by canTurnIntoCOPY(), countMCSymbolRefExpr(), llvm::AArch64InstrInfo::foldMemoryOperandImpl(), llvm::X86InstrInfo::foldMemoryOperandImpl(), llvm::SIRegisterInfo::getRegClass(), getRegClassFromGRPhysReg(), getRegNum(), llvm::MipsSEInstrInfo::loadImmediate(), MakeM0Inst(), llvm::AVRRegisterInfo::shouldCoalesce(), and llvm::X86InstrInfo::unfoldMemoryOperand().

◆ getRegNum()

static bool getRegNum ( StringRef  Str,
unsigned &  Num 
)
static

Definition at line 2068 of file AMDGPUAsmParser.cpp.

References assert(), llvm::SmallVectorTemplateCommon< T, typename >::back(), llvm::APFloat::bitcastToAPInt(), llvm::APFloat::changeSign(), llvm::AsmToken::Colon, llvm::AsmToken::Comma, llvm::APFloat::convertFromString(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::count(), llvm::countPopulation(), llvm::MCConstantExpr::create(), llvm::AMDGPUAsmVariants::DEFAULT, llvm::SIInstrFlags::DPP, llvm::AMDGPUAsmVariants::DPP, llvm::AMDGPU::SDWA::DWORD, llvm::MCOI::EARLY_CLOBBER, llvm::StringRef::empty(), llvm::SIInstrFlags::Gather4, llvm::StringRef::getAsInteger(), llvm::getCPU(), llvm::MCOperand::getImm(), llvm::AMDGPU::getIsaVersion(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCRegisterClass::getNumRegs(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::AMDGPU::getOperandSize(), llvm::MCOperand::getReg(), llvm::MCRegisterInfo::getRegClass(), getRegClass(), llvm::MCRegisterClass::getRegister(), llvm::AMDGPU::getRegOperandSize(), getRegularRegInfo(), getSpecialRegForName(), llvm::AsmToken::getString(), llvm::getToken(), llvm::MCSymbol::getVariableValue(), llvm::APInt::getZExtValue(), llvm::AMDGPU::IsaInfo::hasCodeObjectV3(), llvm::AMDGPU::hasPackedD16(), llvm::AsmToken::Identifier, llvm::APFloatBase::IEEEdouble(), llvm::MCInstrDesc::ImplicitUses, Info, llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::insert(), llvm::SIInstrFlags::IntClamp, llvm::tgtok::IntVal, llvm::AsmToken::is(), llvm::AMDGPU::isCI(), llvm::AMDGPU::isGFX10(), llvm::MCOperand::isImm(), llvm::AMDGPU::isInlinableLiteral16(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralV216(), llvm::MCOperand::isReg(), llvm::AMDGPU::isRegIntersect(), isRegularReg(), llvm::AMDGPU::isSGPR(), llvm::AMDGPU::isSI(), llvm::AMDGPU::isSISrcOperand(), llvm::isUInt< 32 >(), llvm::MCSymbol::isVariable(), llvm::AsmToken::LBrac, llvm_unreachable, llvm::AsmToken::LParen, llvm::makeArrayRef(), llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::MCInstrDesc::mayLoad(), llvm::MCInstrDesc::mayStore(), llvm::AMDGPU::mc2PseudoReg(), llvm::SIInstrFlags::MIMG, llvm::AsmToken::Minus, llvm::None, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, Operands, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::APFloatBase::opInvalidOp, llvm::AsmToken::Pipe, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AsmToken::RBrac, llvm::AsmToken::Real, Reg, llvm::APFloatBase::rmNearestTiesToEven, llvm::AsmToken::RParen, llvm::SIInstrFlags::SDWA, llvm::AMDGPUAsmVariants::SDWA, llvm::AMDGPUAsmVariants::SDWA9, llvm::MCSymbol::setVariableValue(), Size, llvm::StringRef::size(), llvm::StringRef::substr(), llvm::AMDGPU::HSAMD::Kernel::Key::SymbolName, TRI, llvm::MCInstrDesc::TSFlags, llvm::SIInstrFlags::VOP1, llvm::SIInstrFlags::VOP2, llvm::SIInstrFlags::VOP3, llvm::AMDGPUAsmVariants::VOP3, llvm::SIInstrFlags::VOP3P, llvm::SIInstrFlags::VOPAsmPrefer32Bit, and llvm::SIInstrFlags::VOPC.

◆ getRegularRegInfo()

static const RegInfo* getRegularRegInfo ( StringRef  Str)
static

Definition at line 2061 of file AMDGPUAsmParser.cpp.

References llvm::StringRef::startswith().

Referenced by getRegNum().

◆ getSpecialRegForName()

static unsigned getSpecialRegForName ( StringRef  RegName)
static

Definition at line 1938 of file AMDGPUAsmParser.cpp.

References assert(), llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), llvm_unreachable, and Reg.

Referenced by getRegNum().

◆ isInlineValue()

static bool isInlineValue ( unsigned  Reg)
static

Definition at line 1867 of file AMDGPUAsmParser.cpp.

References getReg().

◆ isRegOrImmWithInputMods()

static bool isRegOrImmWithInputMods ( const MCInstrDesc &  Desc,
unsigned  OpNum 
)
static

Definition at line 6183 of file AMDGPUAsmParser.cpp.

References llvm::MCInst::addOperand(), addOptionalImmOperand(), assert(), llvm::AMDGPU::DPP::BCAST15, llvm::AMDGPU::DPP::BCAST31, llvm::MCInst::begin(), llvm::AMDGPU::SDWA::BYTE_0, llvm::AMDGPU::SDWA::BYTE_1, llvm::AMDGPU::SDWA::BYTE_2, llvm::AMDGPU::SDWA::BYTE_3, llvm::StringSwitch< T, R >::Case(), llvm::AsmToken::Colon, llvm::AsmToken::Comma, llvm::MCOperand::createImm(), llvm::StringSwitch< T, R >::Default(), llvm::SIInstrFlags::DPP, llvm::AMDGPU::DPP::DPP8_FI_0, llvm::AMDGPU::DPP::DPP8_FI_1, llvm::AMDGPU::SDWA::DWORD, E, llvm::MCOperand::getImm(), llvm::AMDGPU::getMIMGDimInfoByAsmSuffix(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumDefs(), llvm::MCInst::getNumOperands(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), I, llvm::AsmToken::Identifier, llvm::MCInst::insert(), llvm::AsmToken::Integer, llvm::AMDGPU::isGFX10(), llvm::AMDGPU::isGFX9(), llvm::isInt< 16 >(), llvm::SIInstrFlags::IsPacked, llvm::isUInt< 16 >(), llvm::AMDGPU::isVI(), llvm::AsmToken::LBrac, llvm_unreachable, llvm::MatchOperand_NoMatch, llvm::MatchOperand_ParseFail, llvm::MatchOperand_Success, llvm::SISrcMods::NEG, llvm::SISrcMods::NEG_HI, llvm::MCInstrDesc::NumOperands, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, llvm::AMDGPU::OPERAND_INPUT_MODS, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::cl::Prefix, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::AMDGPU::DPP::QUAD_PERM_FIRST, llvm::AMDGPU::DPP::QUAD_PERM_LAST, llvm::AsmToken::RBrac, llvm::MCOperandInfo::RegClass, llvm::AMDGPU::DPP::ROW_HALF_MIRROR, llvm::AMDGPU::DPP::ROW_MIRROR, llvm::AMDGPU::DPP::ROW_ROR0, llvm::AMDGPU::DPP::ROW_ROR_FIRST, llvm::AMDGPU::DPP::ROW_ROR_LAST, llvm::AMDGPU::DPP::ROW_SHARE_FIRST, llvm::AMDGPU::DPP::ROW_SHARE_LAST, llvm::AMDGPU::DPP::ROW_SHL0, llvm::AMDGPU::DPP::ROW_SHL_FIRST, llvm::AMDGPU::DPP::ROW_SHL_LAST, llvm::AMDGPU::DPP::ROW_SHR0, llvm::AMDGPU::DPP::ROW_SHR_FIRST, llvm::AMDGPU::DPP::ROW_SHR_LAST, llvm::AMDGPU::DPP::ROW_XMASK_FIRST, llvm::AMDGPU::DPP::ROW_XMASK_LAST, llvm::MCOperand::setImm(), llvm::SmallVectorBase::size(), llvm::StringRef::startswith(), llvm::StringRef::substr(), llvm::MCOI::TIED_TO, llvm::MCInstrDesc::TSFlags, llvm::AMDGPU::SDWA::UNUSED_PAD, llvm::AMDGPU::SDWA::UNUSED_PRESERVE, llvm::AMDGPU::SDWA::UNUSED_SEXT, llvm::SIInstrFlags::VOP1, llvm::SIInstrFlags::VOP2, llvm::SIInstrFlags::VOPC, llvm::AMDGPU::DPP::WAVE_ROL1, llvm::AMDGPU::DPP::WAVE_ROR1, llvm::AMDGPU::DPP::WAVE_SHL1, llvm::AMDGPU::DPP::WAVE_SHR1, llvm::AMDGPU::SDWA::WORD_0, and llvm::AMDGPU::SDWA::WORD_1.

◆ isRegularReg()

static bool isRegularReg ( RegisterKind  Kind)
static

Definition at line 2054 of file AMDGPUAsmParser.cpp.

Referenced by getRegNum().

◆ IsRevOpcode()

static bool IsRevOpcode ( const unsigned  Opcode)
static

Definition at line 3087 of file AMDGPUAsmParser.cpp.

References llvm::Triple::amdgcn, AMDGPUMnemonicSpellCheck(), llvm::Triple::AMDHSA, AMDHSA_BITS_SET, assert(), llvm::AsmToken::Comma, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc1, llvm::amdhsa::kernel_descriptor_t::compute_pgm_rsrc2, llvm::numbers::e, llvm::MCStreamer::EmitInstruction(), llvm::StringMap< NoneType, AllocatorTy >::end(), llvm::AsmToken::EndOfStatement, llvm::StringMap< NoneType, AllocatorTy >::find(), llvm::AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), llvm::getCPU(), llvm::AMDGPU::getDefaultAmdhsaKernelDescriptor(), llvm::MCOperand::getImm(), llvm::AMDGPU::getIsaVersion(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getNumSGPRBlocks(), llvm::AMDGPU::IsaInfo::getNumVGPRBlocks(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::getToken(), llvm::amdhsa::kernel_descriptor_t::group_segment_fixed_size, llvm::AMDGPU::hasXNACK(), llvm::AsmToken::Identifier, llvm::StringSet< AllocatorTy >::insert(), llvm::AsmToken::Integer, llvm::MCOperand::isExpr(), llvm::AMDGPU::isGFX9(), llvm::MCOperand::isImm(), llvm::isIntN(), llvm::SIInstrFlags::IsMAI, llvm::SIInstrFlags::IsNonFlatSeg, llvm::MCOperand::isReg(), llvm::AMDGPU::isSISrcOperand(), llvm::isUInt(), llvm::isUIntN(), llvm::amdhsa::kernel_descriptor_t::kernel_code_properties, llvm_unreachable, llvm::AMDGPU::IsaVersion::Major, llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumSGPRs, llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::NumVGPRs, PARSE_BITS_ENTRY, llvm::amdhsa::kernel_descriptor_t::private_segment_fixed_size, llvm::MipsISD::Ret, llvm::SIInstrFlags::SDWA, llvm::MCInst::setLoc(), llvm::SmallVectorBase::size(), llvm::SIInstrFlags::SOP2, llvm::SIInstrFlags::SOPC, llvm::SMRange::Start, llvm::raw_string_ostream::str(), llvm::AMDGPU::IsaInfo::streamIsaVersion(), llvm::AsmToken::String, llvm::FeatureBitset::test(), llvm::MCInstrDesc::TSFlags, llvm::IndexedInstrProf::Version, llvm::SIInstrFlags::VOP1, llvm::SIInstrFlags::VOP2, llvm::SIInstrFlags::VOP3, llvm::SIInstrFlags::VOP3P, and llvm::SIInstrFlags::VOPC.

◆ isSafeTruncation()

static bool isSafeTruncation ( int64_t  Val,
unsigned  Size 
)
static

Definition at line 1522 of file AMDGPUAsmParser.cpp.

References llvm::Literal, and llvm::Warning.

◆ LLVMInitializeAMDGPUAsmParser()

void LLVMInitializeAMDGPUAsmParser ( )

Force static initialization.

Definition at line 6943 of file AMDGPUAsmParser.cpp.

References B, llvm::getTheAMDGPUTarget(), and llvm::getTheGCNTarget().

Variable Documentation

◆ AMDGPUOptionalOperandTable

const OptionalOperand AMDGPUOptionalOperandTable[]
static

Definition at line 6036 of file AMDGPUAsmParser.cpp.

◆ RegularRegisters

constexpr RegInfo RegularRegisters[]
static
Initial value:
= {
{{"v"}, IS_VGPR},
{{"s"}, IS_SGPR},
{{"ttmp"}, IS_TTMP},
{{"acc"}, IS_AGPR},
{{"a"}, IS_AGPR},
}

Definition at line 2046 of file AMDGPUAsmParser.cpp.

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