LLVM 20.0.0git
Classes | Macros | Typedefs | Functions | Variables
AMDGPUAsmParser.cpp File Reference
#include "AMDKernelCodeT.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCExpr.h"
#include "MCTargetDesc/AMDGPUMCKernelDescriptor.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "MCTargetDesc/AMDGPUTargetStreamer.h"
#include "SIDefines.h"
#include "SIInstrInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUAsmUtils.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "Utils/AMDKernelCodeTUtils.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/Twine.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/AMDGPUMetadata.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/TargetParser/TargetParser.h"
#include <optional>
#include "AMDGPUGenAsmMatcher.inc"

Go to the source code of this file.

Classes

struct  RegInfo
 

Macros

#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE)
 
#define EXPR_RESOLVE_OR_ERROR(RESOLVED)
 
#define GET_REGISTER_MATCHER
 
#define GET_MATCHER_IMPLEMENTATION
 
#define GET_MNEMONIC_SPELL_CHECKER
 
#define GET_MNEMONIC_CHECKER
 
Auto-generated Match Functions

{

#define GET_ASSEMBLER_HEADER
 

Typedefs

using OperandIndices = SmallVector< int16_t, MAX_SRC_OPERANDS_NUM >
 

Functions

static const fltSemantics * getFltSemantics (unsigned Size)
 
static const fltSemantics * getFltSemantics (MVT VT)
 
static const fltSemantics * getOpFltSemantics (uint8_t OperandType)
 
static bool canLosslesslyConvertToFPType (APFloat &FPLiteral, MVT VT)
 
static bool isSafeTruncation (int64_t Val, unsigned Size)
 
static bool isInlineableLiteralOp16 (int64_t Val, MVT VT, bool HasInv2Pi)
 
static int getRegClass (RegisterKind Is, unsigned RegWidth)
 
static MCRegister getSpecialRegForName (StringRef RegName)
 
static bool isRegularReg (RegisterKind Kind)
 
static const RegInfo * getRegularRegInfo (StringRef Str)
 
static bool getRegNum (StringRef Str, unsigned &Num)
 
static ArrayRef< unsigned > getAllVariants ()
 
static OperandIndices getSrcOperandIndices (unsigned Opcode, bool AddMandatoryLiterals=false)
 
static bool checkWriteLane (const MCInst &Inst)
 
static bool IsMovrelsSDWAOpcode (const unsigned Opcode)
 
static bool IsRevOpcode (const unsigned Opcode)
 
static int IsAGPROperand (const MCInst &Inst, uint16_t NameIdx, const MCRegisterInfo *MRI)
 
static std::string AMDGPUMnemonicSpellCheck (StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)
 
static bool AMDGPUCheckMnemonic (StringRef Mnemonic, const FeatureBitset &AvailableFeatures, unsigned VariantID)
 
static bool isInvalidVOPDY (const OperandVector &Operands, uint64_t InvalidOprIdx)
 
static void applyMnemonicAliases (StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID)
 
static void addOptionalImmOperand (MCInst &Inst, const OperandVector &Operands, AMDGPUAsmParser::OptionalImmIndexMap &OptionalIdx, AMDGPUOperand::ImmTy ImmT, int64_t Default=0)
 
static bool encodeCnt (const AMDGPU::IsaVersion ISA, int64_t &IntVal, int64_t CntVal, bool Saturate, unsigned(*encode)(const IsaVersion &Version, unsigned, unsigned), unsigned(*decode)(const IsaVersion &Version, unsigned))
 
static LLVM_READNONE unsigned encodeBitmaskPerm (const unsigned AndMask, const unsigned OrMask, const unsigned XorMask)
 
static bool ConvertOmodMul (int64_t &Mul)
 
static bool ConvertOmodDiv (int64_t &Div)
 
static void cvtVOP3DstOpSelOnly (MCInst &Inst, const MCRegisterInfo &MRI)
 
static bool isRegOrImmWithInputMods (const MCInstrDesc &Desc, unsigned OpNum)
 
static void addSrcModifiersAndSrc (MCInst &Inst, const OperandVector &Operands, unsigned i, unsigned Opc, unsigned OpName)
 
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser ()
 Force static initialization.
 

Variables

static constexpr RegInfo RegularRegisters []
 
constexpr unsigned MAX_SRC_OPERANDS_NUM = 6
 
constexpr uint64_t MIMGFlags
 

Macro Definition Documentation

◆ EXPR_RESOLVE_OR_ERROR

#define EXPR_RESOLVE_OR_ERROR (   RESOLVED)
Value:
if (!(RESOLVED)) \
return Error(IDRange.Start, "directive should have resolvable expression", \
IDRange);
llvm::Error
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160

◆ GET_ASSEMBLER_HEADER

#define GET_ASSEMBLER_HEADER

Definition at line 1328 of file AMDGPUAsmParser.cpp.

◆ GET_MATCHER_IMPLEMENTATION

#define GET_MATCHER_IMPLEMENTATION

Definition at line 9688 of file AMDGPUAsmParser.cpp.

◆ GET_MNEMONIC_CHECKER

#define GET_MNEMONIC_CHECKER

Definition at line 9690 of file AMDGPUAsmParser.cpp.

◆ GET_MNEMONIC_SPELL_CHECKER

#define GET_MNEMONIC_SPELL_CHECKER

Definition at line 9689 of file AMDGPUAsmParser.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 9687 of file AMDGPUAsmParser.cpp.

◆ PARSE_BITS_ENTRY

#define PARSE_BITS_ENTRY (   FIELD,
  ENTRY,
  VALUE,
  RANGE 
)
Value:
if (!isUInt<ENTRY##_WIDTH>(Val)) \
return OutOfRangeError(RANGE); \
AMDGPU::MCKernelDescriptor::bits_set(FIELD, VALUE, ENTRY##_SHIFT, ENTRY, \
getContext());
FIELD
#define FIELD(name)
Definition: AMDKernelCodeTInfo.h:28
ENTRY
#define ENTRY(ASMNAME, ENUM)

Typedef Documentation

◆ OperandIndices

using OperandIndices = SmallVector<int16_t, MAX_SRC_OPERANDS_NUM>

Definition at line 3687 of file AMDGPUAsmParser.cpp.

Function Documentation

◆ addOptionalImmOperand()

static void addOptionalImmOperand ( MCInst &  Inst,
const OperandVector &  Operands,
AMDGPUAsmParser::OptionalImmIndexMap &  OptionalIdx,
AMDGPUOperand::ImmTy  ImmT,
int64_t  Default = 0 
)
static

Definition at line 6768 of file AMDGPUAsmParser.cpp.

References llvm::MCInst::addOperand(), llvm::MCOperand::createImm(), Default, Idx, and Operands.

◆ addSrcModifiersAndSrc()

static void addSrcModifiersAndSrc ( MCInst &  Inst,
const OperandVector &  Operands,
unsigned  i,
unsigned  Opc,
unsigned  OpName 
)
static

Definition at line 8979 of file AMDGPUAsmParser.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), and Operands.

◆ AMDGPUCheckMnemonic()

static bool AMDGPUCheckMnemonic ( StringRef  Mnemonic,
const FeatureBitset &  AvailableFeatures,
unsigned  VariantID 
)
static

◆ AMDGPUMnemonicSpellCheck()

static std::string AMDGPUMnemonicSpellCheck ( StringRef  S,
const FeatureBitset &  FBS,
unsigned  VariantID = 0 
)
static

◆ applyMnemonicAliases()

static void applyMnemonicAliases ( StringRef &  Mnemonic,
const FeatureBitset &  Features,
unsigned  VariantID 
)
static

◆ canLosslesslyConvertToFPType()

static bool canLosslesslyConvertToFPType ( APFloat &  FPLiteral,
MVT  VT 
)
static

Definition at line 2001 of file AMDGPUAsmParser.cpp.

References llvm::APFloat::convert(), and getFltSemantics().

◆ checkWriteLane()

static bool checkWriteLane ( const MCInst &  Inst)
static

Definition at line 3735 of file AMDGPUAsmParser.cpp.

References llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::MCOperand::isReg(), llvm::M0(), and llvm::AMDGPU::mc2PseudoReg().

◆ ConvertOmodDiv()

static bool ConvertOmodDiv ( int64_t &  Div)
static

Definition at line 8527 of file AMDGPUAsmParser.cpp.

◆ ConvertOmodMul()

static bool ConvertOmodMul ( int64_t &  Mul)
static

Definition at line 8519 of file AMDGPUAsmParser.cpp.

References Mul.

◆ cvtVOP3DstOpSelOnly()

static void cvtVOP3DstOpSelOnly ( MCInst &  Inst,
const MCRegisterInfo &  MRI 
)
static

Definition at line 8640 of file AMDGPUAsmParser.cpp.

References assert(), llvm::SISrcMods::DST_OP_SEL, llvm::MCOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::DstOp::getReg(), llvm::AMDGPU::hasNamedOperand(), llvm::AMDGPU::isHi16Reg(), MRI, and llvm::MCOperand::setImm().

◆ encodeBitmaskPerm()

static LLVM_READNONE unsigned encodeBitmaskPerm ( const unsigned  AndMask,
const unsigned  OrMask,
const unsigned  XorMask 
)
static

Definition at line 8031 of file AMDGPUAsmParser.cpp.

◆ encodeCnt()

static bool encodeCnt ( const AMDGPU::IsaVersion  ISA,
int64_t &  IntVal,
int64_t  CntVal,
bool  Saturate,
unsigned(*)(const IsaVersion &Version, unsigned, unsigned)  encode,
unsigned(*)(const IsaVersion &Version, unsigned)  decode 
)
static

Definition at line 7196 of file AMDGPUAsmParser.cpp.

References decode(), llvm::encode(), and llvm::Failed().

◆ getAllVariants()

static ArrayRef< unsigned > getAllVariants ( )
static

Definition at line 3518 of file AMDGPUAsmParser.cpp.

References llvm::AMDGPUAsmVariants::DEFAULT, llvm::AMDGPUAsmVariants::DPP, llvm::AMDGPUAsmVariants::SDWA, llvm::AMDGPUAsmVariants::SDWA9, llvm::AMDGPUAsmVariants::VOP3, and llvm::AMDGPUAsmVariants::VOP3_DPP.

◆ getFltSemantics() [1/2]

static const fltSemantics * getFltSemantics ( MVT  VT)
static

Definition at line 1941 of file AMDGPUAsmParser.cpp.

References getFltSemantics(), and llvm::MVT::getSizeInBits().

◆ getFltSemantics() [2/2]

static const fltSemantics * getFltSemantics ( unsigned  Size)
static

Definition at line 1928 of file AMDGPUAsmParser.cpp.

References llvm_unreachable, and Size.

Referenced by canLosslesslyConvertToFPType(), and getFltSemantics().

◆ getOpFltSemantics()

static const fltSemantics * getOpFltSemantics ( uint8_t  OperandType)
static

Definition at line 1945 of file AMDGPUAsmParser.cpp.

References llvm_unreachable, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_AC_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, and llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT32.

◆ getRegClass()

static int getRegClass ( RegisterKind  Is,
unsigned  RegWidth 
)
static

Definition at line 2533 of file AMDGPUAsmParser.cpp.

◆ getRegNum()

static bool getRegNum ( StringRef  Str,
unsigned &  Num 
)
static

Definition at line 2797 of file AMDGPUAsmParser.cpp.

◆ getRegularRegInfo()

static const RegInfo * getRegularRegInfo ( StringRef  Str)
static

Definition at line 2790 of file AMDGPUAsmParser.cpp.

References RegularRegisters.

◆ getSpecialRegForName()

static MCRegister getSpecialRegForName ( StringRef  RegName)
static

Definition at line 2646 of file AMDGPUAsmParser.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), and RegName.

◆ getSrcOperandIndices()

static OperandIndices getSrcOperandIndices ( unsigned  Opcode,
bool  AddMandatoryLiterals = false 
)
static

Definition at line 3691 of file AMDGPUAsmParser.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), and llvm::AMDGPU::isVOPD().

◆ IsAGPROperand()

static int IsAGPROperand ( const MCInst &  Inst,
uint16_t  NameIdx,
const MCRegisterInfo *  MRI 
)
static

Definition at line 4808 of file AMDGPUAsmParser.cpp.

References llvm::MCRegisterClass::contains(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), and MRI.

Referenced by decodeAVLdSt().

◆ isInlineableLiteralOp16()

static bool isInlineableLiteralOp16 ( int64_t  Val,
MVT  VT,
bool  HasInv2Pi 
)
static

Definition at line 2023 of file AMDGPUAsmParser.cpp.

References assert(), llvm::MVT::getScalarType(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteralBF16(), and llvm::AMDGPU::isInlinableLiteralFP16().

◆ isInvalidVOPDY()

static bool isInvalidVOPDY ( const OperandVector &  Operands,
uint64_t  InvalidOprIdx 
)
static

Definition at line 5324 of file AMDGPUAsmParser.cpp.

References assert(), and Operands.

◆ IsMovrelsSDWAOpcode()

static bool IsMovrelsSDWAOpcode ( const unsigned  Opcode)
static

Definition at line 4097 of file AMDGPUAsmParser.cpp.

◆ isRegOrImmWithInputMods()

static bool isRegOrImmWithInputMods ( const MCInstrDesc &  Desc,
unsigned  OpNum 
)
static

Definition at line 8687 of file AMDGPUAsmParser.cpp.

References llvm::AMDGPU::OPERAND_INPUT_MODS.

◆ isRegularReg()

static bool isRegularReg ( RegisterKind  Kind)
static

Definition at line 2783 of file AMDGPUAsmParser.cpp.

◆ IsRevOpcode()

static bool IsRevOpcode ( const unsigned  Opcode)
static

Definition at line 4299 of file AMDGPUAsmParser.cpp.

◆ isSafeTruncation()

static bool isSafeTruncation ( int64_t  Val,
unsigned  Size 
)
static

Definition at line 2019 of file AMDGPUAsmParser.cpp.

References llvm::isIntN(), llvm::isUIntN(), and Size.

◆ LLVMInitializeAMDGPUAsmParser()

LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser ( )

Force static initialization.

Definition at line 9682 of file AMDGPUAsmParser.cpp.

References A, B, llvm::getTheGCNTarget(), and llvm::getTheR600Target().

Variable Documentation

◆ MAX_SRC_OPERANDS_NUM

constexpr unsigned MAX_SRC_OPERANDS_NUM = 6
constexpr

Definition at line 3686 of file AMDGPUAsmParser.cpp.

◆ MIMGFlags

constexpr uint64_t MIMGFlags
constexpr
Initial value:
=
SIInstrFlags::MIMG | SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE

Definition at line 3892 of file AMDGPUAsmParser.cpp.

◆ RegularRegisters

constexpr RegInfo RegularRegisters[]
staticconstexpr
Initial value:
= {
{{"v"}, IS_VGPR},
{{"s"}, IS_SGPR},
{{"ttmp"}, IS_TTMP},
{{"acc"}, IS_AGPR},
{{"a"}, IS_AGPR},
}

Definition at line 2775 of file AMDGPUAsmParser.cpp.

Referenced by getRegularRegInfo().

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