LLVM 24.0.0git
Classes | Macros | Typedefs | Functions | Variables
AMDGPUAsmParser.cpp File Reference
#include "AMDKernelCodeT.h"
#include "MCTargetDesc/AMDGPUInstPrinter.h"
#include "MCTargetDesc/AMDGPUMCAsmInfo.h"
#include "MCTargetDesc/AMDGPUMCExpr.h"
#include "MCTargetDesc/AMDGPUMCKernelDescriptor.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "MCTargetDesc/AMDGPUTargetStreamer.h"
#include "SIDefines.h"
#include "SIInstrInfo.h"
#include "TargetInfo/AMDGPUTargetInfo.h"
#include "Utils/AMDGPUAsmUtils.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "Utils/AMDKernelCodeTUtils.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/SmallBitVector.h"
#include "llvm/ADT/Twine.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCParser/AsmLexer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/AMDGPUMetadata.h"
#include "llvm/Support/AMDGPUObjLinkingInfo.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/TargetParser/AMDGPUTargetParser.h"
#include <optional>
#include "AMDGPUGenAsmMatcher.inc"

Go to the source code of this file.

Classes

struct  RegInfo

Macros

#define GET_REGISTER_MATCHER
#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE)
#define EXPR_RESOLVE_OR_ERROR(RESOLVED)
#define GET_MATCHER_IMPLEMENTATION
#define GET_MNEMONIC_SPELL_CHECKER
#define GET_MNEMONIC_CHECKER
Auto-generated Match Functions

{

#define GET_ASSEMBLER_HEADER

Typedefs

using OperandIndices = SmallVector<int16_t, MAX_SRC_OPERANDS_NUM>

Functions

static const fltSemantics * getFltSemantics (unsigned Size)
static const fltSemantics * getFltSemantics (MVT VT)
static const fltSemantics * getOpFltSemantics (uint8_t OperandType)
static bool canLosslesslyConvertToFPType (APFloat &FPLiteral, MVT VT)
static bool isSafeTruncation (int64_t Val, unsigned Size)
static bool isInlineableLiteralOp16 (int64_t Val, MVT VT, bool HasInv2Pi)
static int getRegClass (RegisterKind Is, unsigned RegWidth)
static MCRegister getSpecialRegForName (StringRef RegName)
static bool isRegularReg (RegisterKind Kind)
static const RegInfo * getRegularRegInfo (StringRef Str)
static bool getRegNum (StringRef Str, unsigned &Num)
static ArrayRef< unsigned > getAllVariants ()
static OperandIndices getSrcOperandIndices (unsigned Opcode, bool AddMandatoryLiterals=false)
static bool checkWriteLane (const MCInst &Inst)
static bool IsMovrelsSDWAOpcode (const unsigned Opcode)
static bool IsRevOpcode (const unsigned Opcode)
static int IsAGPROperand (const MCInst &Inst, AMDGPU::OpName Name, const MCRegisterInfo *MRI)
static std::string AMDGPUMnemonicSpellCheck (StringRef S, const FeatureBitset &FBS, unsigned VariantID=0)
static bool AMDGPUCheckMnemonic (StringRef Mnemonic, const FeatureBitset &AvailableFeatures, unsigned VariantID)
static bool isInvalidVOPDY (const OperandVector &Operands, uint64_t InvalidOprIdx)
static void applyMnemonicAliases (StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID)
static void addOptionalImmOperand (MCInst &Inst, const OperandVector &Operands, AMDGPUAsmParser::OptionalImmIndexMap &OptionalIdx, AMDGPUOperand::ImmTy ImmT, int64_t Default=0, std::optional< unsigned > InsertAt=std::nullopt)
static bool encodeCnt (const AMDGPU::IsaVersion ISA, int64_t &IntVal, int64_t CntVal, bool Saturate, unsigned(*encode)(const IsaVersion &Version, unsigned, unsigned), unsigned(*decode)(const IsaVersion &Version, unsigned))
static LLVM_READNONE unsigned encodeBitmaskPerm (const unsigned AndMask, const unsigned OrMask, const unsigned XorMask)
static bool ConvertOmodMul (int64_t &Mul)
static bool ConvertOmodDiv (int64_t &Div)
static void cvtVOP3DstOpSelOnly (MCInst &Inst, const MCRegisterInfo &MRI)
static bool isRegOrImmWithInputMods (const MCInstrDesc &Desc, unsigned OpNum)
static void addSrcModifiersAndSrc (MCInst &Inst, const OperandVector &Operands, unsigned i, unsigned Opc, AMDGPU::OpName OpName)
LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser ()
 Force static initialization.

Variables

static constexpr RegInfo RegularRegisters []
constexpr unsigned MAX_SRC_OPERANDS_NUM = 6

Macro Definition Documentation

◆ EXPR_RESOLVE_OR_ERROR

#define EXPR_RESOLVE_OR_ERROR ( RESOLVED)
Value:
if (!(RESOLVED)) \
return Error(IDRange.Start, "directive should have resolvable expression", \
IDRange);

◆ GET_ASSEMBLER_HEADER

#define GET_ASSEMBLER_HEADER

Definition at line 1365 of file AMDGPUAsmParser.cpp.

◆ GET_MATCHER_IMPLEMENTATION

#define GET_MATCHER_IMPLEMENTATION

Definition at line 10908 of file AMDGPUAsmParser.cpp.

◆ GET_MNEMONIC_CHECKER

#define GET_MNEMONIC_CHECKER

Definition at line 10910 of file AMDGPUAsmParser.cpp.

◆ GET_MNEMONIC_SPELL_CHECKER

#define GET_MNEMONIC_SPELL_CHECKER

Definition at line 10909 of file AMDGPUAsmParser.cpp.

◆ GET_REGISTER_MATCHER

#define GET_REGISTER_MATCHER

Definition at line 1258 of file AMDGPUAsmParser.cpp.

◆ PARSE_BITS_ENTRY

#define PARSE_BITS_ENTRY ( FIELD,
ENTRY,
VALUE,
RANGE )
Value:
if (!isUInt<ENTRY##_WIDTH>(Val)) \
return OutOfRangeError(RANGE); \
AMDGPU::MCKernelDescriptor::bits_set(FIELD, VALUE, ENTRY##_SHIFT, ENTRY, \
getContext());
FIELD
#define FIELD(name)
Definition AMDKernelCodeTInfo.h:28
ENTRY
#define ENTRY(ASMNAME, ENUM)
getContext
Func getContext().diagnose(DiagnosticInfoUnsupported(Func
llvm::isUInt
constexpr bool isUInt(uint64_t x)
Checks if an unsigned integer fits into the given bit width.
Definition MathExtras.h:190

Typedef Documentation

◆ OperandIndices

using OperandIndices = SmallVector<int16_t, MAX_SRC_OPERANDS_NUM>

Definition at line 3890 of file AMDGPUAsmParser.cpp.

Function Documentation

◆ addOptionalImmOperand()

void addOptionalImmOperand ( MCInst & Inst,
const OperandVector & Operands,
AMDGPUAsmParser::OptionalImmIndexMap & OptionalIdx,
AMDGPUOperand::ImmTy ImmT,
int64_t Default = 0,
std::optional< unsigned > InsertAt = std::nullopt )
static

Definition at line 7760 of file AMDGPUAsmParser.cpp.

References llvm::MCInst::addOperand(), llvm::MCInst::begin(), llvm::MCOperand::createImm(), Default, llvm::MCInst::insert(), and Operands.

◆ addSrcModifiersAndSrc()

void addSrcModifiersAndSrc ( MCInst & Inst,
const OperandVector & Operands,
unsigned i,
unsigned Opc,
AMDGPU::OpName OpName )
static

Definition at line 10165 of file AMDGPUAsmParser.cpp.

References Opc, and Operands.

◆ AMDGPUCheckMnemonic()

bool AMDGPUCheckMnemonic ( StringRef Mnemonic,
const FeatureBitset & AvailableFeatures,
unsigned VariantID )
static

◆ AMDGPUMnemonicSpellCheck()

std::string AMDGPUMnemonicSpellCheck ( StringRef S,
const FeatureBitset & FBS,
unsigned VariantID = 0 )
static

◆ applyMnemonicAliases()

void applyMnemonicAliases ( StringRef & Mnemonic,
const FeatureBitset & Features,
unsigned VariantID )
static

References llvm::AsmToken::EndOfStatement, Mode, Msg, and Operands.

◆ canLosslesslyConvertToFPType()

bool canLosslesslyConvertToFPType ( APFloat & FPLiteral,
MVT VT )
static

Definition at line 2108 of file AMDGPUAsmParser.cpp.

References llvm::APFloat::convert(), getFltSemantics(), llvm::APFloatBase::opOK, llvm::APFloatBase::opOverflow, llvm::APFloatBase::opUnderflow, and llvm::APFloatBase::rmNearestTiesToEven.

◆ checkWriteLane()

bool checkWriteLane ( const MCInst & Inst)
static

Definition at line 3939 of file AMDGPUAsmParser.cpp.

References llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCOperand::getReg(), llvm::MCOperand::isReg(), llvm::M0(), and llvm::AMDGPU::mc2PseudoReg().

◆ ConvertOmodDiv()

bool ConvertOmodDiv ( int64_t & Div)
static

Definition at line 9546 of file AMDGPUAsmParser.cpp.

◆ ConvertOmodMul()

bool ConvertOmodMul ( int64_t & Mul)
static

Definition at line 9538 of file AMDGPUAsmParser.cpp.

References Mul.

◆ cvtVOP3DstOpSelOnly()

void cvtVOP3DstOpSelOnly ( MCInst & Inst,
const MCRegisterInfo & MRI )
static

Definition at line 9677 of file AMDGPUAsmParser.cpp.

References AbstractManglingParser< Derived, Alloc >::Ops, assert(), llvm::MCRegisterClass::contains(), llvm::SISrcMods::DST_OP_SEL, llvm::MCOperand::getImm(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::DstOp::getReg(), llvm::MCRegisterInfo::getRegClass(), llvm::AMDGPU::hasNamedOperand(), llvm::AMDGPU::isHi16Reg(), Opc, and llvm::MCOperand::setImm().

◆ encodeBitmaskPerm()

LLVM_READNONE unsigned encodeBitmaskPerm ( const unsigned AndMask,
const unsigned OrMask,
const unsigned XorMask )
static

Definition at line 9065 of file AMDGPUAsmParser.cpp.

References llvm::AMDGPU::Swizzle::BITMASK_AND_SHIFT, llvm::AMDGPU::Swizzle::BITMASK_OR_SHIFT, llvm::AMDGPU::Swizzle::BITMASK_PERM_ENC, and llvm::AMDGPU::Swizzle::BITMASK_XOR_SHIFT.

◆ encodeCnt()

bool encodeCnt ( const AMDGPU::IsaVersion ISA,
int64_t & IntVal,
int64_t CntVal,
bool Saturate,
unsigned(* encode )(const IsaVersion &Version, unsigned, unsigned),
unsigned(* decode )(const IsaVersion &Version, unsigned) )
static

Definition at line 8249 of file AMDGPUAsmParser.cpp.

References decode(), llvm::encode(), and llvm::Failed().

◆ getAllVariants()

ArrayRef< unsigned > getAllVariants ( )
static

Definition at line 3722 of file AMDGPUAsmParser.cpp.

References llvm::ArrayRef(), llvm::AMDGPUAsmVariants::DEFAULT, llvm::AMDGPUAsmVariants::DPP, llvm::AMDGPUAsmVariants::SDWA, llvm::AMDGPUAsmVariants::SDWA9, llvm::AMDGPUAsmVariants::VOP3, and llvm::AMDGPUAsmVariants::VOP3_DPP.

◆ getFltSemantics() [1/2]

const fltSemantics * getFltSemantics ( MVT VT)
static

Definition at line 2053 of file AMDGPUAsmParser.cpp.

References getFltSemantics(), and llvm::MVT::getScalarSizeInBits().

◆ getFltSemantics() [2/2]

const fltSemantics * getFltSemantics ( unsigned Size)
static

Definition at line 2040 of file AMDGPUAsmParser.cpp.

References llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEsingle(), llvm_unreachable, and Size.

Referenced by canLosslesslyConvertToFPType(), and getFltSemantics().

◆ getOpFltSemantics()

const fltSemantics * getOpFltSemantics ( uint8_t OperandType)
static

Definition at line 2057 of file AMDGPUAsmParser.cpp.

References llvm::APFloatBase::BFloat(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEsingle(), llvm_unreachable, llvm::AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32, llvm::AMDGPU::OPERAND_KIMM16, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_KIMM64, llvm::AMDGPU::OPERAND_REG_IMM_BF16, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_NOINLINE_FP16, llvm::AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2BF16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16_SPLAT, llvm::AMDGPU::OPERAND_REG_IMM_V2FP32, llvm::AMDGPU::OPERAND_REG_IMM_V2FP64, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT32, llvm::AMDGPU::OPERAND_REG_IMM_V2INT64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_AC_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_AC_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2BF16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, and llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16.

◆ getRegClass()

int getRegClass ( RegisterKind Is,
unsigned RegWidth )
static

Definition at line 2648 of file AMDGPUAsmParser.cpp.

◆ getRegNum()

bool getRegNum ( StringRef Str,
unsigned & Num )
static

Definition at line 2930 of file AMDGPUAsmParser.cpp.

◆ getRegularRegInfo()

const RegInfo * getRegularRegInfo ( StringRef Str)
static

Definition at line 2923 of file AMDGPUAsmParser.cpp.

References Reg, and RegularRegisters.

◆ getSpecialRegForName()

MCRegister getSpecialRegForName ( StringRef RegName)
static

Definition at line 2765 of file AMDGPUAsmParser.cpp.

References llvm::StringSwitch< T, R >::Case(), llvm::StringSwitch< T, R >::Default(), and RegName.

◆ getSrcOperandIndices()

OperandIndices getSrcOperandIndices ( unsigned Opcode,
bool AddMandatoryLiterals = false )
static

Definition at line 3894 of file AMDGPUAsmParser.cpp.

References llvm::AMDGPU::isVOPD().

◆ IsAGPROperand()

int IsAGPROperand ( const MCInst & Inst,
AMDGPU::OpName Name,
const MCRegisterInfo * MRI )
static

Definition at line 5302 of file AMDGPUAsmParser.cpp.

References llvm::MCRegisterClass::contains(), llvm::MCInst::getOpcode(), llvm::MCInst::getOperand(), llvm::MCRegisterInfo::getRegClass(), llvm::MCRegisterInfo::getSubReg(), Reg, and llvm::Sub.

◆ isInlineableLiteralOp16()

bool isInlineableLiteralOp16 ( int64_t Val,
MVT VT,
bool HasInv2Pi )
static

Definition at line 2128 of file AMDGPUAsmParser.cpp.

References assert(), llvm::MVT::getScalarType(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteralBF16(), and llvm::AMDGPU::isInlinableLiteralFP16().

◆ isInvalidVOPDY()

bool isInvalidVOPDY ( const OperandVector & Operands,
uint64_t InvalidOprIdx )
static

Definition at line 5964 of file AMDGPUAsmParser.cpp.

References assert(), Operands, and uint64_t.

◆ IsMovrelsSDWAOpcode()

bool IsMovrelsSDWAOpcode ( const unsigned Opcode)
static

Definition at line 4410 of file AMDGPUAsmParser.cpp.

◆ isRegOrImmWithInputMods()

bool isRegOrImmWithInputMods ( const MCInstrDesc & Desc,
unsigned OpNum )
static

Definition at line 9723 of file AMDGPUAsmParser.cpp.

References llvm::AMDGPU::OPERAND_INPUT_MODS, and llvm::MCOI::TIED_TO.

◆ isRegularReg()

bool isRegularReg ( RegisterKind Kind)
static

Definition at line 2918 of file AMDGPUAsmParser.cpp.

◆ IsRevOpcode()

bool IsRevOpcode ( const unsigned Opcode)
static

Definition at line 4614 of file AMDGPUAsmParser.cpp.

◆ isSafeTruncation()

bool isSafeTruncation ( int64_t Val,
unsigned Size )
static

Definition at line 2124 of file AMDGPUAsmParser.cpp.

References llvm::isIntN(), llvm::isUIntN(), and Size.

◆ LLVMInitializeAMDGPUAsmParser()

LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser ( )

Force static initialization.

Definition at line 10902 of file AMDGPUAsmParser.cpp.

References A(), B(), C(), llvm::getTheGCNLegacyTarget(), llvm::getTheGCNTarget(), and llvm::getTheR600Target().

Variable Documentation

◆ MAX_SRC_OPERANDS_NUM

unsigned MAX_SRC_OPERANDS_NUM = 6
constexpr

Definition at line 3889 of file AMDGPUAsmParser.cpp.

◆ RegularRegisters

RegInfo RegularRegisters[]
staticconstexpr
Initial value:
= {
{{"v"}, IS_VGPR}, {{"s"}, IS_SGPR}, {{"ttmp"}, IS_TTMP},
{{"acc"}, IS_AGPR}, {{"a"}, IS_AGPR},
}

Definition at line 2913 of file AMDGPUAsmParser.cpp.

Referenced by getRegularRegInfo().

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