llvm::MVT Class Reference

Machine Value Type. More...

#include "llvm/CodeGenTypes/MachineValueType.h"

Public Types
enum	SimpleValueType : uint16_t { INVALID_SIMPLE_VALUE_TYPE = 0 , VALUETYPE_SIZE = LAST_VALUETYPE + 1 }

Public Member Functions
constexpr	MVT ()=default
constexpr	MVT (SimpleValueType SVT)
bool	operator> (const MVT &S) const
bool	operator< (const MVT &S) const
bool	operator== (const MVT &S) const
bool	operator!= (const MVT &S) const
bool	operator>= (const MVT &S) const
bool	operator<= (const MVT &S) const
void	dump () const
	Support for debugging, callable in GDB: VT.dump()
void	print (raw_ostream &OS) const
	Implement operator<<.
bool	isValid () const
	Return true if this is a valid simple valuetype.
bool	isFloatingPoint () const
	Return true if this is a FP or a vector FP type.
bool	isInteger () const
	Return true if this is an integer or a vector integer type.
bool	isScalarInteger () const
	Return true if this is an integer, not including vectors.
bool	isVector () const
	Return true if this is a vector value type.
bool	isScalableVector () const
	Return true if this is a vector value type where the runtime length is machine dependent.
bool	isRISCVVectorTuple () const
	Return true if this is a RISCV vector tuple type where the runtime length is machine dependent.
bool	isScalableTargetExtVT () const
	Return true if this is a custom target type that has a scalable size.
bool	isScalableVT () const
	Return true if the type is a scalable type.
bool	isFixedLengthVector () const
bool	is16BitVector () const
	Return true if this is a 16-bit vector type.
bool	is32BitVector () const
	Return true if this is a 32-bit vector type.
bool	is64BitVector () const
	Return true if this is a 64-bit vector type.
bool	is128BitVector () const
	Return true if this is a 128-bit vector type.
bool	is256BitVector () const
	Return true if this is a 256-bit vector type.
bool	is512BitVector () const
	Return true if this is a 512-bit vector type.
bool	is1024BitVector () const
	Return true if this is a 1024-bit vector type.
bool	is2048BitVector () const
	Return true if this is a 2048-bit vector type.
bool	isOverloaded () const
	Return true if this is an overloaded type for TableGen.
MVT	changeVectorElementTypeToInteger () const
	Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.
MVT	changeVectorElementType (MVT EltVT) const
	Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
MVT	changeTypeToInteger ()
	Return the type converted to an equivalently sized integer or vector with integer element type.
MVT	getHalfNumVectorElementsVT () const
	Return a VT for a vector type with the same element type but half the number of elements.
MVT	getDoubleNumVectorElementsVT () const
bool	isPow2VectorType () const
	Returns true if the given vector is a power of 2.
MVT	getPow2VectorType () const
	Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
MVT	getScalarType () const
	If this is a vector, return the element type, otherwise return this.
MVT	getVectorElementType () const
unsigned	getVectorMinNumElements () const
	Given a vector type, return the minimum number of elements it contains.
ElementCount	getVectorElementCount () const
unsigned	getVectorNumElements () const
TypeSize	getSizeInBits () const
	Returns the size of the specified MVT in bits.
uint64_t	getFixedSizeInBits () const
	Return the size of the specified fixed width value type in bits.
uint64_t	getScalarSizeInBits () const
TypeSize	getStoreSize () const
	Return the number of bytes overwritten by a store of the specified value type.
uint64_t	getScalarStoreSize () const
TypeSize	getStoreSizeInBits () const
	Return the number of bits overwritten by a store of the specified value type.
bool	isByteSized () const
	Returns true if the number of bits for the type is a multiple of an 8-bit byte.
bool	knownBitsGT (MVT VT) const
	Return true if we know at compile time this has more bits than VT.
bool	knownBitsGE (MVT VT) const
	Return true if we know at compile time this has more than or the same bits as VT.
bool	knownBitsLT (MVT VT) const
	Return true if we know at compile time this has fewer bits than VT.
bool	knownBitsLE (MVT VT) const
	Return true if we know at compile time this has fewer than or the same bits as VT.
bool	bitsGT (MVT VT) const
	Return true if this has more bits than VT.
bool	bitsGE (MVT VT) const
	Return true if this has no less bits than VT.
bool	bitsLT (MVT VT) const
	Return true if this has less bits than VT.
bool	bitsLE (MVT VT) const
	Return true if this has no more bits than VT.
unsigned	getRISCVVectorTupleNumFields () const
	Given a RISC-V vector tuple type, return the num_fields.
const fltSemantics &	getFltSemantics () const
	Returns an APFloat semantics tag appropriate for the value type.

Static Public Member Functions
static MVT	getFloatingPointVT (unsigned BitWidth)
static MVT	getIntegerVT (unsigned BitWidth)
static MVT	getVectorVT (MVT VT, unsigned NumElements)
static MVT	getScalableVectorVT (MVT VT, unsigned NumElements)
static MVT	getRISCVVectorTupleVT (unsigned Sz, unsigned NFields)
static MVT	getVectorVT (MVT VT, unsigned NumElements, bool IsScalable)
static MVT	getVectorVT (MVT VT, ElementCount EC)
static MVT	getVT (Type *Ty, bool HandleUnknown=false)
	Return the value type corresponding to the specified type.
static auto	all_valuetypes ()
	SimpleValueType Iteration.
static auto	integer_valuetypes ()
static auto	fp_valuetypes ()
static auto	vector_valuetypes ()
static auto	fixedlen_vector_valuetypes ()
static auto	scalable_vector_valuetypes ()
static auto	integer_fixedlen_vector_valuetypes ()
static auto	fp_fixedlen_vector_valuetypes ()
static auto	integer_scalable_vector_valuetypes ()
static auto	fp_scalable_vector_valuetypes ()

Public Attributes
SimpleValueType	SimpleTy = INVALID_SIMPLE_VALUE_TYPE

Detailed Description

Machine Value Type.

Every type that is supported natively by some processor targeted by LLVM occurs here. This means that any legal value type can be represented by an MVT.

Definition at line 35 of file MachineValueType.h.

Member Enumeration Documentation

SimpleValueType

enum llvm::MVT::SimpleValueType : uint16_t

Enumerator
INVALID_SIMPLE_VALUE_TYPE
VALUETYPE_SIZE

Definition at line 37 of file MachineValueType.h.

Constructor & Destructor Documentation

MVT() [1/2]

constexpr llvm::MVT::MVT ( )

constexprdefault

Referenced by getVT().

MVT() [2/2]

constexpr llvm::MVT::MVT ( SimpleValueType  SVT )

inlineconstexpr

Definition at line 58 of file MachineValueType.h.

Member Function Documentation

all_valuetypes()

static auto llvm::MVT::all_valuetypes ( )

inlinestatic

SimpleValueType Iteration.

Definition at line 520 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::TargetLoweringBase::initActions().

bitsGE()

bool llvm::MVT::bitsGE ( MVT  VT ) const

inline

Return true if this has no less bits than VT.

Definition at line 411 of file MachineValueType.h.

References assert(), isScalableVector(), and knownBitsGE().

Referenced by LowerABD(), and llvm::RISCVTargetLowering::LowerOperation().

bitsGT()

bool llvm::MVT::bitsGT ( MVT  VT ) const

inline

Return true if this has more bits than VT.

Definition at line 404 of file MachineValueType.h.

References assert(), isScalableVector(), and knownBitsGT().

Referenced by getSmallestVTForIndex(), getVRGatherIndexType(), LowerFCOPYSIGN(), and lowerVECTOR_SHUFFLE().

bitsLE()

bool llvm::MVT::bitsLE ( MVT  VT ) const

inline

Return true if this has no more bits than VT.

Definition at line 425 of file MachineValueType.h.

References assert(), isScalableVector(), and knownBitsLE().

Referenced by getMaskNode(), llvm::SITargetLowering::getPreferredVectorAction(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerReductionSeq(), lowerScalarInsert(), and llvm::RISCVTargetLowering::PerformDAGCombine().

bitsLT()

bool llvm::MVT::bitsLT ( MVT  VT ) const

inline

Return true if this has less bits than VT.

Definition at line 418 of file MachineValueType.h.

References assert(), isScalableVector(), and knownBitsLT().

Referenced by LowerFCOPYSIGN(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::PerformDAGCombine(), and promoteVCIXScalar().

changeTypeToInteger()

MVT llvm::MVT::changeTypeToInteger ( )

inline

Return the type converted to an equivalently sized integer or vector with integer element type.

Similar to changeVectorElementTypeToInteger, but also handles scalars.

Definition at line 217 of file MachineValueType.h.

References changeVectorElementTypeToInteger(), getIntegerVT(), getSizeInBits(), and isVector().

Referenced by llvm::EVT::changeTypeToInteger(), combineStore(), getVRGatherIndexType(), getWideningInterleave(), getWideningSpread(), lowerShuffleWithPERMV(), lowerVECTOR_SHUFFLE(), and matchBinaryShuffle().

changeVectorElementType()

MVT llvm::MVT::changeVectorElementType ( MVT  EltVT ) const

inline

Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.

Definition at line 207 of file MachineValueType.h.

References assert(), getVectorElementCount(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.

Referenced by llvm::EVT::changeVectorElementType(), combineTruncToVnclip(), llvm::RISCVTTIImpl::getCastInstrCost(), getVRGatherIndexType(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXbf16(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerDisjointIndicesShuffle(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarSplat(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVSETCC(), matchUnaryShuffle(), performCONCAT_VECTORSCombine(), promoteXINT_TO_FP(), and widenVectorOpsToi8().

changeVectorElementTypeToInteger()

MVT llvm::MVT::changeVectorElementTypeToInteger ( ) const

inline

Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.

Definition at line 196 of file MachineValueType.h.

References assert(), getIntegerVT(), getSizeInBits(), getVectorElementCount(), getVectorElementType(), getVectorVT(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.

Referenced by changeTypeToInteger(), llvm::EVT::changeVectorElementTypeToInteger(), combineSetCCMOVMSK(), getDeinterleaveShiftAndTrunc(), lowerBuildVectorOfConstants(), lowerVECTOR_SHUFFLE_VSHUF(), lowerVECTOR_SHUFFLE_XVSHUF(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), and lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND().

dump()

void MVT::dump

(

)

const

Support for debugging, callable in GDB: VT.dump()

Definition at line 325 of file ValueTypes.cpp.

References llvm::dbgs(), and print().

fixedlen_vector_valuetypes()

static auto llvm::MVT::fixedlen_vector_valuetypes ( )

inlinestatic

Definition at line 542 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LoongArchTargetLowering::LoongArchTargetLowering(), llvm::MipsSETargetLowering::MipsSETargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), and llvm::X86TargetLowering::X86TargetLowering().

fp_fixedlen_vector_valuetypes()

static auto llvm::MVT::fp_fixedlen_vector_valuetypes ( )

inlinestatic

Definition at line 560 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), and llvm::RISCVTargetLowering::RISCVTargetLowering().

fp_scalable_vector_valuetypes()

static auto llvm::MVT::fp_scalable_vector_valuetypes ( )

inlinestatic

Definition at line 572 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

fp_valuetypes()

static auto llvm::MVT::fp_valuetypes ( )

inlinestatic

Definition at line 531 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::TargetLoweringBase::initActions(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), and llvm::SystemZTargetLowering::SystemZTargetLowering().

getDoubleNumVectorElementsVT()

MVT llvm::MVT::getDoubleNumVectorElementsVT ( ) const

inline

Definition at line 234 of file MachineValueType.h.

References getVectorElementCount(), getVectorElementType(), and getVectorVT().

Referenced by combinePTESTCC(), and getSmallestVTForIndex().

getFixedSizeInBits()

uint64_t llvm::MVT::getFixedSizeInBits ( ) const

inline

Return the size of the specified fixed width value type in bits.

The function will assert if the type is scalable.

Definition at line 342 of file MachineValueType.h.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), and getSizeInBits().

Referenced by CC_AIX(), combineINSERT_SUBVECTOR(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), getCopyToPartsVector(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32BitVector(), is512BitVector(), is64BitVector(), lowerBUILD_VECTOR(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), lowerShuffleViaVRegSplitting(), LowerVSETCC(), MatchingStackOffset(), truncateScalarIntegerArg(), useRVVForFixedLengthVectorVT(), and widenSubVector().

getFloatingPointVT()

static MVT llvm::MVT::getFloatingPointVT ( unsigned  BitWidth )

inlinestatic

Definition at line 431 of file MachineValueType.h.

References llvm_unreachable.

Referenced by combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combinePredicateReduction(), combinePTESTCC(), combineSetCCMOVMSK(), combineX86ShuffleChain(), combineX86ShufflesConstants(), EltsFromConsecutiveLoads(), llvm::RISCVTTIImpl::getCastInstrCost(), llvm::EVT::getFloatingPointVT(), lower256BitShuffle(), lowerVECTOR_SHUFFLE(), and tryWidenMaskForShuffle().

getFltSemantics()

const fltSemantics & MVT::getFltSemantics

(

)

const

Returns an APFloat semantics tag appropriate for the value type.

If this is a vector type, the element semantics are returned.

Definition at line 307 of file ValueTypes.cpp.

References llvm::APFloatBase::BFloat(), getScalarType(), llvm::APFloatBase::IEEEdouble(), llvm::APFloatBase::IEEEhalf(), llvm::APFloatBase::IEEEquad(), llvm::APFloatBase::IEEEsingle(), llvm_unreachable, llvm::APFloatBase::PPCDoubleDouble(), SimpleTy, and llvm::APFloatBase::x87DoubleExtended().

Referenced by CastIntSETCCtoFP(), llvm::EVT::getFltSemantics(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFROUND(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), lowerShuffleAsBitMask(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), and lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND().

getHalfNumVectorElementsVT()

MVT llvm::MVT::getHalfNumVectorElementsVT ( ) const

inline

Return a VT for a vector type with the same element type but half the number of elements.

Definition at line 225 of file MachineValueType.h.

References assert(), getVectorElementCount(), getVectorElementType(), and getVectorVT().

Referenced by canonicalizeShuffleMaskWithHorizOp(), combineSetCCMOVMSK(), combineTargetShuffle(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getHopForBuildVector(), getShuffleHalfVectors(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), llvm::RISCVTargetLowering::LowerOperation(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), lowerV2X128Shuffle(), and lowerVECTOR_SHUFFLE().

getIntegerVT()

static MVT llvm::MVT::getIntegerVT ( unsigned  BitWidth )

inlinestatic

Definition at line 441 of file MachineValueType.h.

References INVALID_SIMPLE_VALUE_TYPE.

Referenced by changeTypeToInteger(), changeVectorElementTypeToInteger(), combineBitcast(), combineConcatVectorOps(), combineTruncToVnclip(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), llvm::computeSignatureVTs(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::SelectionDAG::getBitcastedSExtOrTrunc(), llvm::SelectionDAG::getBitcastedZExtOrTrunc(), llvm::RISCVTTIImpl::getCastInstrCost(), getDeinterleaveShiftAndTrunc(), getDWordFromOffset(), llvm::EVT::getIntegerVT(), llvm::getMVTForLLT(), llvm::RISCVTargetLowering::getOptimalMemOpType(), getPermuteNode(), llvm::TargetLoweringBase::getPointerMemTy(), llvm::TargetLoweringBase::getPointerTy(), llvm::AArch64TargetLowering::getPointerTy(), getRegistersForValue(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::M68kTargetLowering::getScalarShiftAmountTy(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::SelectionDAGBuilder::getValueImpl(), getVCIXISDNodeWCHAIN(), getVectorBitwiseReduce(), llvm::SPIRVTargetLowering::getVectorIdxTy(), getVT(), getWideningInterleave(), getWideningSpread(), llvm::TargetLoweringBase::hasFastEqualityCompare(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::TargetLoweringBase::initActions(), insert1BitVector(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), isLegalBitRotate(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), LowerABD(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), LowerCTPOP(), lowerFCOPYSIGN64(), lowerFP_TO_INT_SAT(), LowerFunnelShift(), lowerLaneOp(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleWithEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_COMPRESS(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), LowerVectorMatch(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerX86FPLogicOp(), matchPERM(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), memsetStore(), performBitcastCombine(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformEXTRACTCombine(), performSETCCCombine(), PerformVECREDUCE_ADDCombine(), PerformVQDMULHCombine(), processVCIXOperands(), llvm::X86TargetLowering::ReplaceNodeResults(), scaleVectorType(), llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(), llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(), ShrinkLoadReplaceStoreWithStore(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), SkipExtensionForVMULL(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TryCombineBaseUpdate(), tryWidenMaskForShuffle(), unpackFromMemLoc(), vectorToScalarBitmask(), and llvm::X86TargetLowering::X86TargetLowering().

getPow2VectorType()

MVT llvm::MVT::getPow2VectorType ( ) const

inline

Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.

Definition at line 248 of file MachineValueType.h.

References llvm::ElementCount::get(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getVectorElementCount(), getVectorElementType(), getVectorVT(), isPow2VectorType(), llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable(), and llvm::Log2_32_Ceil().

Referenced by llvm::TargetLoweringBase::computeRegisterProperties().

getRISCVVectorTupleNumFields()

unsigned llvm::MVT::getRISCVVectorTupleNumFields ( ) const

inline

Given a RISC-V vector tuple type, return the num_fields.

Definition at line 482 of file MachineValueType.h.

References assert(), isRISCVVectorTuple(), and SimpleTy.

Referenced by llvm::RISCVTargetLowering::getRegClassIDForVecVT(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().

getRISCVVectorTupleVT()

static MVT llvm::MVT::getRISCVVectorTupleVT ( unsigned  Sz, unsigned  NFields  )

inlinestatic

Definition at line 471 of file MachineValueType.h.

References llvm_unreachable.

Referenced by getVT().

getScalableVectorVT()

static MVT llvm::MVT::getScalableVectorVT ( MVT  VT, unsigned  NumElements  )

inlinestatic

Definition at line 461 of file MachineValueType.h.

References INVALID_SIMPLE_VALUE_TYPE.

Referenced by getContainerForFixedLengthVector(), getLMUL1VT(), getVectorVT(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::RISCVTargetLowering::PerformDAGCombine().

getScalarSizeInBits()

uint64_t llvm::MVT::getScalarSizeInBits ( ) const

inline

Definition at line 346 of file MachineValueType.h.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getSizeInBits().

Referenced by canonicalizeBitSelect(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), checkSignTestSetCCCombine(), combineAddOfPMADDWD(), combineAndnp(), combineBitOpWithPACK(), combineBlendOfPermutes(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineMOVMSK(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineTESTP(), combineTruncToVnclip(), combineVectorCompare(), combineVEXTRACT_STORE(), combineVPMADD(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMAXBounds(), createPackShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), expandFP_TO_UINT_SSE(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TTIImpl::getCmpSelInstrCost(), getConstantVector(), getConstVector(), llvm::RegsForValue::getCopyFromRegs(), getDeinterleaveShiftAndTrunc(), getFauxShuffleMask(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::RTLIB::getOUTLINE_ATOMIC(), getPack(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), getPSHUFShuffleMask(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarValueForVectorElement(), llvm::RISCVTTIImpl::getShuffleCost(), getSmallestVTForIndex(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeToPromoteTo(), getVectorTypeBreakdownMVT(), getVRGatherIndexType(), getWideningInterleave(), getWideningSpread(), is128BitLaneCrossingShuffleMask(), isHorizontalBinOp(), isInterleaveShuffle(), isRepeatedShuffleMask(), isRepeatedTargetShuffleMask(), lower256BitShuffle(), LowerABD(), LowerADDSAT_SUBSAT(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), lowerVectorIntrinsicScalars(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::X86::mayFoldLoadIntoBroadcastFromMem(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INTCombine(), PerformVQDMULHCombine(), processPSInputArgs(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and vectorizeExtractedCast().

getScalarStoreSize()

uint64_t llvm::MVT::getScalarStoreSize ( ) const

inline

Definition at line 363 of file MachineValueType.h.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getStoreSize().

getScalarType()

MVT llvm::MVT::getScalarType ( ) const

inline

If this is a vector, return the element type, otherwise return this.

Definition at line 259 of file MachineValueType.h.

References getVectorElementType(), and isVector().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), CastIntSETCCtoFP(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineMOVMSK(), combineStore(), combineTargetShuffle(), constructDup(), createVariablePermute(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), getConstantVector(), getFauxShuffleMask(), getFltSemantics(), getIEEEProperties(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarSizeInBits(), getScalarStoreSize(), getTargetShuffleMask(), getTargetVShiftNode(), getVRGatherIndexType(), isInlineableLiteralOp16(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerMLOAD(), LowerMSTORE(), LowerRotate(), LowerShift(), lowerShuffleAsBroadcast(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsRotate(), LowerVectorCTPOP(), matchUnaryShuffle(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), vectorizeExtractedCast(), and widenSubVector().

getSizeInBits()

TypeSize llvm::MVT::getSizeInBits ( ) const

inline

Returns the size of the specified MVT in bits.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 308 of file MachineValueType.h.

References assert(), INVALID_SIMPLE_VALUE_TYPE, llvm_unreachable, llvm::Other, SimpleTy, and VALUETYPE_SIZE.

Referenced by Analyze_CC_Sparc64_Full(), Analyze_CC_Sparc64_Half(), llvm::MachineIRBuilder::buildExtractVectorElementConstant(), canonicalizeBitSelect(), CC_ARM_AAPCS_Custom_Aggregate(), llvm::CC_RISCV_FastCC(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), changeVectorElementTypeToInteger(), combineAndLoadToBZHI(), combineEXTRACT_SUBVECTOR(), combinePredicateReduction(), combinePTESTCC(), combineSetCCMOVMSK(), combineShiftRightArithmetic(), combineTargetShuffle(), combineVectorHADDSUB(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), llvm::RISCVTargetLowering::computeVLMAXBounds(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), createVariablePermute(), createVPDPBUSD(), DecodePALIGNRMask(), emitRepstos(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::FastISel::fastEmit_ri_(), finishStackBlock(), genShuffleBland(), getAVX512Node(), getAVX512TruncNode(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getFauxShuffleMask(), getFixedSizeInBits(), getFltSemantics(), getGFNICtrlMask(), getHopForBuildVector(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), llvm::RISCVTargetLowering::getLMULCost(), llvm::TargetLoweringBase::getNumRegisters(), getPack(), llvm::HvxSelector::getPairVT(), llvm::PPCTargetLowering::getPreferredVectorAction(), getPromotedVectorElementType(), getPSHUFShuffleMask(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getRegistersForValue(), llvm::RegsForValue::getRegsAndSizes(), getScalarSizeInBits(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), llvm::HvxSelector::getSingleVT(), getStoreSize(), getTargetShuffleAndZeroables(), getTargetVShiftNode(), llvm::HexagonSubtarget::getTypeAlignment(), llvm::TargetLoweringBase::getVaListSizeInBits(), llvm::AArch64TargetLowering::getVaListSizeInBits(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getZeroVector(), group2Shuffle(), insert1BitVector(), isByteSized(), IsElementEquivalent(), isHorizontalBinOp(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), isTargetShuffleEquivalent(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), llvm::LLT::LLT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCTLZ(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::HexagonTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), LowerHorizontalByteSum(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), llvm::RISCVTargetLowering::LowerOperation(), LowerPARITY(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSplitOrBlend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleViaVRegSplitting(), lowerShuffleWithPACK(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), MatchingStackOffset(), matchShuffleAsBlend(), matchSplatAsGather(), matchUnaryPermuteShuffle(), narrowExtractedVectorSelect(), llvm::TargetLowering::ParseConstraints(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFpToIntCombine(), performScatterStoreCombine(), PerformTruncatingStoreCombine(), PerformVCVTCombine(), PerformVMulVCTPCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::LoongArchDAGToDAGISel::selectSExti32(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::RISCVDAGToDAGISel::selectZExtBits(), llvm::LoongArchDAGToDAGISel::selectZExti32(), setGroupSize(), shouldTransformMulToShiftsAddsSubs(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), TryCombineBaseUpdate(), tryCombineShiftImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), UnpackFromArgumentSlot(), and useRVVForFixedLengthVectorVT().

getStoreSize()

TypeSize llvm::MVT::getStoreSize ( ) const

inline

Return the number of bytes overwritten by a store of the specified value type.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 356 of file MachineValueType.h.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getKnownMinValue(), getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isScalable().

Referenced by llvm::analyzeArguments(), llvm::analyzeReturnValues(), CC_AIX(), CC_MipsO32(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), CC_Xtensa_Custom(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::SystemZTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::SystemZTargetLowering::emitEHSjLjSetJmp(), llvm::BasicTTIImplBase< T >::getInterleavedMemoryOpCost(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::MSP430TargetLowering::getReturnAddressFrameIndex(), getScalarStoreSize(), llvm::X86TTIImpl::getShuffleCost(), getStoreSizeInBits(), llvm::SITargetLowering::LowerCall(), lowerShuffleAsBroadcast(), lowerV2X128Shuffle(), lowerVECTOR_SHUFFLE(), scalarizeVectorStore(), and llvm::RISCVDAGToDAGISel::Select().

getStoreSizeInBits()

TypeSize llvm::MVT::getStoreSizeInBits ( ) const

inline

Return the number of bits overwritten by a store of the specified value type.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 373 of file MachineValueType.h.

References getStoreSize().

Referenced by llvm::HexagonTargetLowering::LowerCall(), and llvm::HexagonTargetLowering::LowerFormalArguments().

getVectorElementCount()

ElementCount llvm::MVT::getVectorElementCount ( ) const

inline

Definition at line 290 of file MachineValueType.h.

References llvm::ElementCount::get(), getVectorMinNumElements(), and isScalableVector().

Referenced by changeVectorElementType(), changeVectorElementTypeToInteger(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMax(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), getCopyToPartsVector(), getDoubleNumVectorElementsVT(), getHalfNumVectorElementsVT(), llvm::getLLTForMVT(), getMaskTypeFor(), getPow2VectorType(), llvm::TargetLoweringBase::getPreferredVectorAction(), getVCIXISDNodeWCHAIN(), getVectorTypeBreakdownMVT(), getWideningInterleave(), getWideningSpread(), llvm::LLT::LLT(), lowerCttzElts(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerVECTOR_SHUFFLE(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::RISCVDAGToDAGISel::Select(), and splatPartsI64WithVL().

getVectorElementType()

MVT llvm::MVT::getVectorElementType ( ) const

inline

Definition at line 263 of file MachineValueType.h.

References assert(), INVALID_SIMPLE_VALUE_TYPE, and SimpleTy.

Referenced by allocateRVVReg(), llvm::RISCVCallLowering::canLowerReturn(), changeVectorElementTypeToInteger(), combineBitcast(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineScalarCTPOPToVCPOP(), combineShuffleToAddSubOrFMAddSub(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), convertShiftLeftToScale(), ExtendToType(), getConstVector(), getContainerForFixedLengthVector(), getDoubleNumVectorElementsVT(), getGFNICtrlMask(), getHalfNumVectorElementsVT(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), getPow2VectorType(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getUnderlyingExtractedFromVec(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getVectorTypeBreakdownMVT(), getWideningInterleave(), getWideningSpread(), getZeroVector(), incDecVectorConstant(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), llvm::HexagonSubtarget::isHVXElementType(), llvm::HexagonSubtarget::isHVXVectorType(), isLegalT2AddressImmediate(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LLT::LLT(), LowerANY_EXTEND(), LowerAVXExtend(), LowerBITCAST(), lowerBitreverseShuffle(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorv4x32(), lowerBuildVectorViaPacking(), LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(), lowerFP_TO_INT_SAT(), LowerHorizontalByteSum(), LowerIntVSETCC_AVX512(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), lowerScalarInsert(), lowerScalarSplat(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsTruncBroadcast(), lowerShuffleViaVRegSplitting(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerZERO_EXTEND(), LowerZERO_EXTEND_Mask(), matchSplatAsGather(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::splitVectorType(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), widenMaskVectorType(), and llvm::X86TargetLowering::X86TargetLowering().

getVectorMinNumElements()

unsigned llvm::MVT::getVectorMinNumElements ( ) const

inline

Given a vector type, return the minimum number of elements it contains.

Definition at line 277 of file MachineValueType.h.

References assert(), and SimpleTy.

Referenced by llvm::HexagonTargetLowering::getPreferredVectorAction(), getVectorElementCount(), getVectorNumElements(), isPow2VectorType(), llvm::LLT::LLT(), lowerBUILD_VECTOR(), lowerShuffleViaVRegSplitting(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), and llvm::RISCVDAGToDAGISel::selectVSXSEG().

getVectorNumElements()

unsigned llvm::MVT::getVectorNumElements ( ) const

inline

Definition at line 294 of file MachineValueType.h.

References getVectorMinNumElements(), isScalableVector(), and llvm::reportInvalidSizeRequest().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeShuffleMaskWithHorizOp(), combineAndnp(), combineBitcast(), combineBlendOfPermutes(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combinePredicateReduction(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVectorCompare(), combineVEXTRACT_STORE(), combineVPMADD(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), llvm::createSplat2ShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), genShuffleBland(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512TruncNode(), getConstVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), getExtractedDemandedElts(), getFauxShuffleMask(), getGatherNode(), getHopForBuildVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::X86TTIImpl::getMaskedMemoryOpCost(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), getPack(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), llvm::X86TTIImpl::getShuffleCost(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getSingleShuffleSrc(), getTargetShuffleAndZeroables(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getUnderlyingExtractedFromVec(), getVectorMaskingNode(), getVRGatherIndexType(), getZeroVector(), group2Shuffle(), incDecVectorConstant(), insert1BitVector(), InsertBitToMaskVector(), isAddSubOrSubAdd(), IsElementEquivalent(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), isHopBuildVector(), isHorizontalBinOp(), isInterleaveShuffle(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), LowerAsSplatVectorLoad(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), llvm::VETargetLowering::lowerBUILD_VECTOR(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), lowerBuildVectorViaPacking(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerLoad(), LowerMGATHER(), LowerMSCATTER(), LowerMUL(), LowerMULH(), LowerMULO(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleViaVRegSplitting(), lowerShuffleWithEXPAND(), lowerShuffleWithPERMV(), lowerShuffleWithUndefHalf(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), LowerToHorizontalOp(), LowerTruncateVecI1(), LowerTruncateVecPack(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlideup(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowervXi8MulWithUNPCK(), LowerZERO_EXTEND_Mask(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchShuffleWithUNPCK(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), performLOADCombine(), PerformVECREDUCE_ADDCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), scaleVectorType(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), setGroupSize(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), vectorizeExtractedCast(), and widenMaskVectorType().

getVectorVT() [1/3]

static MVT llvm::MVT::getVectorVT ( MVT  VT, ElementCount  EC  )

inlinestatic

Definition at line 500 of file MachineValueType.h.

References getScalableVectorVT(), and getVectorVT().

getVectorVT() [2/3]

static MVT llvm::MVT::getVectorVT ( MVT  VT, unsigned  NumElements  )

inlinestatic

Definition at line 451 of file MachineValueType.h.

References INVALID_SIMPLE_VALUE_TYPE.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), AddCombineBUILD_VECTORToVPADDL(), canonicalizeBitSelect(), canonicalizeShuffleMaskWithHorizOp(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineArithReduction(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineMOVMSK(), combineMulToPMADDWD(), combinePredicateReduction(), combinePTESTCC(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVectorHADDSUB(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), ConstantBuildVector(), constructDup(), constructRetValue(), createPSADBW(), createVariablePermute(), createVPDPBUSD(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::X86TTIImpl::getArithmeticInstrCost(), getAVX512Node(), getAVX512TruncNode(), llvm::HvxSelector::getBoolVT(), getBuildDwordsVector(), getConstVector(), getDeinterleaveShiftAndTrunc(), getDoubleNumVectorElementsVT(), getDWordFromOffset(), getGatherNode(), getHalfNumVectorElementsVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::getLegalVectorType(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMaskTypeFor(), llvm::getMVTForLLT(), getOnesVector(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::HvxSelector::getPairVT(), getPermuteNode(), getPow2VectorType(), getPrefetchNode(), getPromotedVectorElementType(), getScatterNode(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::HvxSelector::getSingleVT(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getVCIXISDNodeWCHAIN(), getVectorLoweringShape(), getVectorMaskingNode(), getVectorTypeBreakdownMVT(), llvm::EVT::getVectorVT(), getVectorVT(), getVT(), getWideningInterleave(), getWideningSpread(), getZeroVector(), llvm::HexagonTargetLowering::HexagonTargetLowering(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), isLegalBitRotate(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lower1BitShuffle(), lower256BitShuffle(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), LowerCONCAT_VECTORS_i1(), LowerCTPOP(), LowerEXTRACT_SUBVECTOR(), LowerFMINIMUM_FMAXIMUM(), lowerFPToIntToFP(), LowerFunnelShift(), LowerHorizontalByteSum(), LowerI64IntToFP_AVX512DQ(), LowerINTRINSIC_W_CHAIN(), lowerLaneOp(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleViaVRegSplitting(), lowerShuffleWithEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND_Mask(), LowerStore(), LowerTruncateVecI1(), LowerTruncateVecPack(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), lowerVECTOR_COMPRESS(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), LowerVectorMatch(), llvm::HexagonTargetLowering::LowerVSELECT(), LowervXi8MulWithUNPCK(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::MipsTargetLowering::MipsTargetLowering(), narrowExtractedVectorSelect(), NarrowVector(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), performLOADCombine(), PerformVQDMULHCombine(), processVCIXOperands(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), SkipExtensionForVMULL(), splatPartsI64WithVL(), splitAndLowerShuffle(), llvm::splitVectorType(), TryCombineBaseUpdate(), tryExtendDUPToExtractHigh(), tryWidenMaskForShuffle(), vectorizeExtractedCast(), vectorToScalarBitmask(), widenSubVector(), and WidenVector().

getVectorVT() [3/3]

static MVT llvm::MVT::getVectorVT ( MVT  VT, unsigned  NumElements, bool  IsScalable  )

inlinestatic

Definition at line 494 of file MachineValueType.h.

References getScalableVectorVT(), and getVectorVT().

getVT()

MVT MVT::getVT ( Type *  Ty, bool  HandleUnknown = false  )

static

Return the value type corresponding to the specified type.

If HandleUnknown is true, unknown types are returned as Other, otherwise they are invalid. NB: This includes pointer types, which require a DataLayout to convert to a concrete value type.

Definition at line 237 of file ValueTypes.cpp.

References assert(), llvm::Type::BFloatTyID, llvm::Type::DoubleTyID, llvm::Type::FixedVectorTyID, llvm::Type::FloatTyID, llvm::Type::FP128TyID, getBitWidth(), llvm::VectorType::getElementCount(), llvm::VectorType::getElementType(), getIntegerVT(), llvm::TargetExtType::getIntParameter(), llvm::TargetExtType::getName(), getRISCVVectorTupleVT(), llvm::Type::getTypeID(), llvm::TargetExtType::getTypeParameter(), getVectorVT(), getVT(), llvm::Type::HalfTyID, llvm::Type::IntegerTyID, llvm_unreachable, MVT(), llvm::Type::PPC_FP128TyID, llvm::Type::ScalableVectorTyID, llvm::StringRef::starts_with(), llvm::Type::TargetExtTyID, llvm::Type::VoidTyID, llvm::Type::X86_AMXTyID, and llvm::Type::X86_FP80TyID.

Referenced by llvm::RISCVCallLowering::canLowerReturn(), llvm::CallLowering::checkReturn(), getConvRTLibDesc(), llvm::EVT::getEVT(), llvm::SITargetLowering::getTgtMemIntrinsic(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::HexagonTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getVT(), llvm::GCNTTIImpl::isReadRegisterSourceOfDivergence(), and performSIGN_EXTEND_INREGCombine().

integer_fixedlen_vector_valuetypes()

static auto llvm::MVT::integer_fixedlen_vector_valuetypes ( )

inlinestatic

Definition at line 554 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::RISCVTargetLowering::RISCVTargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), and llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering().

integer_scalable_vector_valuetypes()

static auto llvm::MVT::integer_scalable_vector_valuetypes ( )

inlinestatic

Definition at line 566 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::RISCVTargetLowering::RISCVTargetLowering().

integer_valuetypes()

static auto llvm::MVT::integer_valuetypes ( )

inlinestatic

Definition at line 525 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), llvm::AMDGPUTargetLowering::AMDGPUTargetLowering(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::AVRTargetLowering::AVRTargetLowering(), llvm::BPFTargetLowering::BPFTargetLowering(), findMemType(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::LanaiTargetLowering::LanaiTargetLowering(), llvm::M68kTargetLowering::M68kTargetLowering(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::MSP430TargetLowering::MSP430TargetLowering(), llvm::NVPTXTargetLowering::NVPTXTargetLowering(), PerformTruncatingStoreCombine(), llvm::PPCTargetLowering::PPCTargetLowering(), llvm::R600TargetLowering::R600TargetLowering(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::SystemZTargetLowering::SystemZTargetLowering(), llvm::WebAssemblyTargetLowering::WebAssemblyTargetLowering(), llvm::X86TargetLowering::X86TargetLowering(), llvm::XCoreTargetLowering::XCoreTargetLowering(), and llvm::XtensaTargetLowering::XtensaTargetLowering().

is1024BitVector()

bool llvm::MVT::is1024BitVector ( ) const

inline

Return true if this is a 1024-bit vector type.

Definition at line 171 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

is128BitVector()

bool llvm::MVT::is128BitVector ( ) const

inline

Return true if this is a 128-bit vector type.

Definition at line 156 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

Referenced by CC_AArch64_Custom_Block(), CC_LoongArch(), CC_PPC64_ELF_Shadow_GPR_Regs(), llvm::CC_XPLINK64_Shadow_Reg(), combineAndNotIntoANDNP(), combineCVTP2I_CVTTP2I(), combinePTESTCC(), combineSetCCMOVMSK(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TTIImpl::getCmpSelInstrCost(), getZeroVector(), INITIALIZE_PASS(), isHorizontalBinOp(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), LowerBuildVectorv4x32(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), LowerRotate(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitRotate(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsInsertPS(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performAddSubLongCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), and llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode().

is16BitVector()

bool llvm::MVT::is16BitVector ( ) const

inline

Return true if this is a 16-bit vector type.

Definition at line 141 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

is2048BitVector()

bool llvm::MVT::is2048BitVector ( ) const

inline

Return true if this is a 2048-bit vector type.

Definition at line 176 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

is256BitVector()

bool llvm::MVT::is256BitVector ( ) const

inline

Return true if this is a 256-bit vector type.

Definition at line 161 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

Referenced by CC_LoongArch(), CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineBlendOfPermutes(), combineConcatVectorOps(), combineSetCCMOVMSK(), combineX86ShuffleChain(), ExpandHorizontalBinOp(), getHopForBuildVector(), getZeroVector(), INITIALIZE_PASS(), isHopBuildVector(), isHorizontalBinOp(), LowerABD(), LowerABS(), LowerADDSAT_SUBSAT(), LowerAVG(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMINMAX(), LowerMUL(), LowerMULH(), LowerRotate(), LowerShift(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerStore(), LowerToHorizontalOp(), LowerTruncateVecI1(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), and llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode().

is32BitVector()

bool llvm::MVT::is32BitVector ( ) const

inline

Return true if this is a 32-bit vector type.

Definition at line 146 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

Referenced by CC_AArch64_Custom_Block(), and LowerStore().

is512BitVector()

bool llvm::MVT::is512BitVector ( ) const

inline

Return true if this is a 512-bit vector type.

Definition at line 166 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

Referenced by CC_X86_VectorCallGetSSEs(), combineAndNotIntoANDNP(), combineConcatVectorOps(), combineShuffleToAddSubOrFMAddSub(), combineTargetShuffle(), combineX86ShuffleChain(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TargetLowering::getSetCCResultType(), getZeroVector(), LowerAVXCONCAT_VECTORS(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVSETCC(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsVTRUNC(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), narrowExtractedVectorSelect(), and useVPTERNLOG().

is64BitVector()

bool llvm::MVT::is64BitVector ( ) const

inline

Return true if this is a 64-bit vector type.

Definition at line 151 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

Referenced by CC_AArch64_Custom_Block(), LowerStore(), and tryExtendDUPToExtractHigh().

isByteSized()

bool llvm::MVT::isByteSized ( ) const

inline

Returns true if the number of bits for the type is a multiple of an 8-bit byte.

Definition at line 379 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf().

isFixedLengthVector()

bool llvm::MVT::isFixedLengthVector ( ) const

inline

Definition at line 135 of file MachineValueType.h.

References SimpleTy.

Referenced by llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), convertLocVTToValVT(), convertValVTToLocVT(), getContainerForFixedLengthVector(), getDefaultVLOps(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getWideningInterleave(), is1024BitVector(), is128BitVector(), is16BitVector(), is2048BitVector(), is256BitVector(), is32BitVector(), is512BitVector(), is64BitVector(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), lowerBuildVectorViaPacking(), lowerCttzElts(), lowerFMAXIMUM_FMINIMUM(), lowerFP_TO_INT_SAT(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarInsert(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT(), matchSplatAsGather(), performFP_TO_INTCombine(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), and useRVVForFixedLengthVectorVT().

isFloatingPoint()

bool llvm::MVT::isFloatingPoint ( ) const

inline

Return true if this is a FP or a vector FP type.

Definition at line 80 of file MachineValueType.h.

References SimpleTy.

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), CC_LoongArch(), CC_MipsO32(), llvm::CC_RISCV(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), combineConcatVectorOps(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShufflesConstants(), getConstantVector(), getCopyFromParts(), getCopyToParts(), getCopyToPartsVector(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), getTargetShuffleAndZeroables(), llvm::TargetLoweringBase::getTypeToPromoteTo(), getVCmpInst(), getZeroVector(), isAddSubOrSubAdd(), isHorizontalBinOp(), lowerBUILD_VECTOR(), lowerBuildVectorOfConstants(), lowerBuildVectorViaDominantValues(), LowerFABSorFNEG(), LowerFCOPYSIGN(), llvm::RISCVTargetLowering::LowerOperation(), lowerScalarInsert(), lowerScalarSplat(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndShuffle(), lowerShuffleAsPermuteAndUnpack(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), LowerVSETCC(), llvm::TargetLowering::ParseConstraints(), and performScatterStoreCombine().

isInteger()

bool llvm::MVT::isInteger ( ) const

inline

Return true if this is an integer or a vector integer type.

Definition at line 90 of file MachineValueType.h.

References SimpleTy.

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), convertLocVTToValVT(), llvm::TargetLowering::findOptimalMemOpLowering(), getCopyFromParts(), llvm::RegsForValue::getCopyFromRegs(), getCopyToParts(), getCopyToPartsVector(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), getRegistersForValue(), llvm::X86TTIImpl::getScalarizationOverhead(), getShuffleScalarElt(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::X86TTIImpl::getVectorInstrCost(), isValueTypeInRegForCC(), llvm::TargetLowering::LegalizeSetCCCondCode(), lower256BitShuffle(), LowerABS(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), lowerBuildVectorOfConstants(), lowerBuildVectorViaPacking(), LowerLoad(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), lowerShuffleAsBitBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsTruncBroadcast(), LowerStore(), lowerVECTOR_SHUFFLE(), matchUnaryShuffle(), llvm::TargetLowering::ParseConstraints(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), and llvm::X86TargetLowering::ReplaceNodeResults().

isOverloaded()

bool llvm::MVT::isOverloaded ( ) const

inline

Return true if this is an overloaded type for TableGen.

Definition at line 181 of file MachineValueType.h.

References SimpleTy.

isPow2VectorType()

bool llvm::MVT::isPow2VectorType ( ) const

inline

Returns true if the given vector is a power of 2.

Definition at line 241 of file MachineValueType.h.

References getVectorMinNumElements().

Referenced by getPow2VectorType(), llvm::TargetLoweringBase::getPreferredVectorAction(), llvm::SITargetLowering::getPreferredVectorAction(), and useRVVForFixedLengthVectorVT().

isRISCVVectorTuple()

bool llvm::MVT::isRISCVVectorTuple ( ) const

inline

Return true if this is a RISCV vector tuple type where the runtime length is machine dependent.

Definition at line 120 of file MachineValueType.h.

References SimpleTy.

Referenced by llvm::CC_RISCV(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), getRISCVVectorTupleNumFields(), isScalableTargetExtVT(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().

isScalableTargetExtVT()

bool llvm::MVT::isScalableTargetExtVT ( ) const

inline

Return true if this is a custom target type that has a scalable size.

Definition at line 126 of file MachineValueType.h.

References isRISCVVectorTuple(), and SimpleTy.

Referenced by isScalableVT(), and llvm::LLT::LLT().

isScalableVector()

bool llvm::MVT::isScalableVector ( ) const

inline

Return true if this is a vector value type where the runtime length is machine dependent.

Definition at line 113 of file MachineValueType.h.

References SimpleTy.

Referenced by bitsGE(), bitsGT(), bitsLE(), bitsLT(), CC_AArch64_Custom_Block(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMax(), llvm::RISCVTargetLowering::computeVLMAXBounds(), convertLocVTToValVT(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), finishStackBlock(), getDefaultScalableVLOps(), getDefaultVLOps(), llvm::RISCVTargetLowering::getLMUL(), llvm::RISCVTargetLowering::getLMULCost(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), getSmallestVTForIndex(), getVectorElementCount(), getVectorNumElements(), getVectorTypeBreakdownMVT(), isScalableVT(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LLT::LLT(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerScalarInsert(), llvm::RISCVTargetLowering::PerformDAGCombine(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVDAGToDAGISel::Select(), and llvm::RISCVTargetLowering::splitValueIntoRegisterParts().

isScalableVT()

bool llvm::MVT::isScalableVT ( ) const

inline

Return true if the type is a scalable type.

Definition at line 131 of file MachineValueType.h.

References isScalableTargetExtVT(), and isScalableVector().

isScalarInteger()

bool llvm::MVT::isScalarInteger ( ) const

inline

Return true if this is an integer, not including vectors.

Definition at line 100 of file MachineValueType.h.

References SimpleTy.

Referenced by CC_LoongArch(), llvm::CC_RISCV(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::RTLIB::getOUTLINE_ATOMIC(), LowerABD(), LowerBITCAST(), LowerCTPOP(), llvm::RISCVTargetLowering::LowerOperation(), llvm::HexagonTargetLowering::LowerSETCC(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), promoteVCIXScalar(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), and truncateScalarIntegerArg().

isValid()

bool llvm::MVT::isValid ( ) const

inline

Return true if this is a valid simple valuetype.

Definition at line 74 of file MachineValueType.h.

References SimpleTy.

Referenced by getSmallestVTForIndex(), llvm::TargetLoweringBase::initActions(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::LLT::LLT(), llvm::MipsTargetLowering::MipsTargetLowering(), llvm::TargetLoweringBase::setAtomicLoadExtAction(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), and llvm::TargetLoweringBase::setTruncStoreAction().

isVector()

bool llvm::MVT::isVector ( ) const

inline

Return true if this is a vector value type.

Definition at line 106 of file MachineValueType.h.

References SimpleTy.

Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), llvm::RISCVCallLowering::canLowerReturn(), canonicalizeBitSelect(), llvm::CC_RISCV(), llvm::CC_RISCV_FastCC(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), combineAndnp(), combineScalarCTPOPToVCPOP(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), constructRetValue(), convertLocVTToValVT(), convertValVTToLocVT(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), llvm::X86TTIImpl::getCmpSelInstrCost(), getCopyFromParts(), getCopyToPartsVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMULCost(), getMaskTypeFor(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), llvm::CallLowering::ValueHandler::getStackValueStoreType(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeConversion(), llvm::HexagonSubtarget::isHVXElementType(), isValueTypeInRegForCC(), llvm::LLT::LLT(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::RISCVTargetLowering::LowerCall(), LowerCTLZ(), LowerCTPOP(), LowerCTTZ(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerFMAXIMUM_FMINIMUM(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), LowerLoad(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::AArch64CallLowering::lowerReturn(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerShuffleAsTruncBroadcast(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT(), lowerX86FPLogicOp(), performConcatVectorsCombine(), processPSInputArgs(), promoteXINT_TO_FP(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and llvm::splitVectorType().

knownBitsGE()

bool llvm::MVT::knownBitsGE ( MVT  VT ) const

inline

Return true if we know at compile time this has more than or the same bits as VT.

Definition at line 388 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGE().

Referenced by bitsGE().

knownBitsGT()

bool llvm::MVT::knownBitsGT ( MVT  VT ) const

inline

Return true if we know at compile time this has more bits than VT.

Definition at line 382 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGT().

Referenced by bitsGT().

knownBitsLE()

bool llvm::MVT::knownBitsLE ( MVT  VT ) const

inline

Return true if we know at compile time this has fewer than or the same bits as VT.

Definition at line 399 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE().

Referenced by bitsLE().

knownBitsLT()

bool llvm::MVT::knownBitsLT ( MVT  VT ) const

inline

Return true if we know at compile time this has fewer bits than VT.

Definition at line 393 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLT().

Referenced by bitsLT().

operator!=()

bool llvm::MVT::operator!= ( const MVT &  S ) const

inline

Definition at line 63 of file MachineValueType.h.

References SimpleTy.

operator<()

bool llvm::MVT::operator< ( const MVT &  S ) const

inline

Definition at line 61 of file MachineValueType.h.

References SimpleTy.

operator<=()

bool llvm::MVT::operator<= ( const MVT &  S ) const

inline

Definition at line 65 of file MachineValueType.h.

References SimpleTy.

operator==()

bool llvm::MVT::operator== ( const MVT &  S ) const

inline

Definition at line 62 of file MachineValueType.h.

References SimpleTy.

operator>()

bool llvm::MVT::operator> ( const MVT &  S ) const

inline

Definition at line 60 of file MachineValueType.h.

References SimpleTy.

operator>=()

bool llvm::MVT::operator>= ( const MVT &  S ) const

inline

Definition at line 64 of file MachineValueType.h.

References SimpleTy.

print()

void MVT::print

(

raw_ostream &

OS

)

const

Implement operator<<.

Definition at line 331 of file ValueTypes.cpp.

References llvm::EVT::getEVTString(), INVALID_SIMPLE_VALUE_TYPE, OS, and SimpleTy.

Referenced by dump(), and llvm::operator<<().

scalable_vector_valuetypes()

static auto llvm::MVT::scalable_vector_valuetypes ( )

inlinestatic

Definition at line 548 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering().

vector_valuetypes()

static auto llvm::MVT::vector_valuetypes ( )

inlinestatic

Definition at line 536 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by findMemType().

Member Data Documentation

SimpleTy

SimpleValueType llvm::MVT::SimpleTy = INVALID_SIMPLE_VALUE_TYPE

Definition at line 55 of file MachineValueType.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(), AVRDAGToDAGISel::select< ISD::LOAD >(), CC_AArch64_Custom_Block(), CC_AIX(), CC_ARM_AAPCS_Custom_Aggregate(), changeVectorElementType(), changeVectorElementTypeToInteger(), llvm::SITargetLowering::checkAsmConstraintValA(), combineBitcastvxi1(), llvm::VETargetLowering::combineSelectCC(), ComputePTXValueVTs(), convertFPToInt(), createVariablePermute(), llvm::SITargetLowering::denormalsEnabledForType(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::ARMTargetLowering::findRepresentativeClass(), llvm::X86TargetLowering::findRepresentativeClass(), foldVectorXorShiftIntoCmp(), llvm::TargetLoweringBase::getAtomicLoadExtAction(), llvm::R600RegisterInfo::getCFGStructurizerRegClass(), llvm::TargetLoweringBase::getCondCodeAction(), getContainerForFixedLengthVector(), llvm::EVT::getEVTString(), getExtensionTo64Bits(), getFltSemantics(), getIEEEProperties(), getImplicitScaleFactor(), getLdStRegType(), llvm::RISCVTargetLowering::getLMUL(), llvm::TargetLoweringBase::getLoadExtAction(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLoweringBase::getOperationAction(), getPackedSVEVectorVT(), getPredicateForFixedLengthVector(), llvm::TargetLoweringBase::getRegClassFor(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetLoweringBase::getRegisterType(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), getRISCVVectorTupleNumFields(), llvm::TargetLoweringBase::getSetCCResultType(), getSizeInBits(), getSVEContainerType(), llvm::TargetLoweringBase::getTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), llvm::TargetLoweringBase::getTypeConversion(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::SelectionDAG::getValueType(), getVectorElementType(), getVectorLoweringShape(), getVectorMinNumElements(), getVectorTyFromPredicateVector(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getVPTESTMOpc(), Is16bitsType(), is32Bit(), isConstantSplatVectorMaskForType(), isFixedLengthVector(), isFloatingPoint(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), isInteger(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(), isOverloaded(), IsPTXVectorType(), isRISCVVectorTuple(), isScalableTargetExtVT(), isScalableVector(), isScalarInteger(), llvm::TargetLoweringBase::isTypeLegal(), isValid(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidIndexedLoad(), isVector(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerADDSUBSAT(), llvm::SystemZTargetLowering::LowerFormalArguments(), lowerLaneOp(), lowerRegToMasks(), lowerShuffleAsBlend(), lowerUINT_TO_FP_vec(), operator!=(), llvm::EVT::operator!=(), operator<(), operator<=(), operator==(), operator>(), operator>=(), performUADDVZextCombine(), performUzpCombine(), performVSelectCombine(), print(), ReplaceINTRINSIC_W_CHAIN(), llvm::RISCVDAGToDAGISel::Select(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::TargetLoweringBase::setAtomicLoadExtAction(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), unpackFromRegLoc(), usePartialVectorLoads(), useRVVForFixedLengthVectorVT(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), X86ChooseCmpImmediateOpcode(), and X86ChooseCmpOpcode().

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The documentation for this class was generated from the following files:

• include/llvm/CodeGenTypes/MachineValueType.h
• lib/CodeGen/ValueTypes.cpp