LLVM 19.0.0git
Public Types | Public Member Functions | Static Public Member Functions | Public Attributes | List of all members
llvm::MVT Class Reference

Machine Value Type. More...

#include "llvm/CodeGenTypes/MachineValueType.h"

Public Types

enum  SimpleValueType : uint8_t { INVALID_SIMPLE_VALUE_TYPE = 0 , VALUETYPE_SIZE = LAST_VALUETYPE + 1 , MAX_ALLOWED_VALUETYPE = 224 }
 

Public Member Functions

constexpr MVT ()=default
 
constexpr MVT (SimpleValueType SVT)
 
bool operator> (const MVT &S) const
 
bool operator< (const MVT &S) const
 
bool operator== (const MVT &S) const
 
bool operator!= (const MVT &S) const
 
bool operator>= (const MVT &S) const
 
bool operator<= (const MVT &S) const
 
void dump () const
 Support for debugging, callable in GDB: VT.dump()
 
void print (raw_ostream &OS) const
 Implement operator<<.
 
bool isValid () const
 Return true if this is a valid simple valuetype.
 
bool isFloatingPoint () const
 Return true if this is a FP or a vector FP type.
 
bool isInteger () const
 Return true if this is an integer or a vector integer type.
 
bool isScalarInteger () const
 Return true if this is an integer, not including vectors.
 
bool isVector () const
 Return true if this is a vector value type.
 
bool isScalableVector () const
 Return true if this is a vector value type where the runtime length is machine dependent.
 
bool isScalableTargetExtVT () const
 Return true if this is a custom target type that has a scalable size.
 
bool isScalableVT () const
 Return true if the type is a scalable type.
 
bool isFixedLengthVector () const
 
bool is16BitVector () const
 Return true if this is a 16-bit vector type.
 
bool is32BitVector () const
 Return true if this is a 32-bit vector type.
 
bool is64BitVector () const
 Return true if this is a 64-bit vector type.
 
bool is128BitVector () const
 Return true if this is a 128-bit vector type.
 
bool is256BitVector () const
 Return true if this is a 256-bit vector type.
 
bool is512BitVector () const
 Return true if this is a 512-bit vector type.
 
bool is1024BitVector () const
 Return true if this is a 1024-bit vector type.
 
bool is2048BitVector () const
 Return true if this is a 2048-bit vector type.
 
bool isOverloaded () const
 Return true if this is an overloaded type for TableGen.
 
MVT changeVectorElementTypeToInteger () const
 Return a vector with the same number of elements as this vector, but with the element type converted to an integer type with the same bitwidth.
 
MVT changeVectorElementType (MVT EltVT) const
 Return a VT for a vector type whose attributes match ourselves with the exception of the element type that is chosen by the caller.
 
MVT changeTypeToInteger ()
 Return the type converted to an equivalently sized integer or vector with integer element type.
 
MVT getHalfNumVectorElementsVT () const
 Return a VT for a vector type with the same element type but half the number of elements.
 
MVT getDoubleNumVectorElementsVT () const
 
bool isPow2VectorType () const
 Returns true if the given vector is a power of 2.
 
MVT getPow2VectorType () const
 Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
 
MVT getScalarType () const
 If this is a vector, return the element type, otherwise return this.
 
MVT getVectorElementType () const
 
unsigned getVectorMinNumElements () const
 Given a vector type, return the minimum number of elements it contains.
 
ElementCount getVectorElementCount () const
 
unsigned getVectorNumElements () const
 
TypeSize getSizeInBits () const
 Returns the size of the specified MVT in bits.
 
uint64_t getFixedSizeInBits () const
 Return the size of the specified fixed width value type in bits.
 
uint64_t getScalarSizeInBits () const
 
TypeSize getStoreSize () const
 Return the number of bytes overwritten by a store of the specified value type.
 
uint64_t getScalarStoreSize () const
 
TypeSize getStoreSizeInBits () const
 Return the number of bits overwritten by a store of the specified value type.
 
bool isByteSized () const
 Returns true if the number of bits for the type is a multiple of an 8-bit byte.
 
bool knownBitsGT (MVT VT) const
 Return true if we know at compile time this has more bits than VT.
 
bool knownBitsGE (MVT VT) const
 Return true if we know at compile time this has more than or the same bits as VT.
 
bool knownBitsLT (MVT VT) const
 Return true if we know at compile time this has fewer bits than VT.
 
bool knownBitsLE (MVT VT) const
 Return true if we know at compile time this has fewer than or the same bits as VT.
 
bool bitsGT (MVT VT) const
 Return true if this has more bits than VT.
 
bool bitsGE (MVT VT) const
 Return true if this has no less bits than VT.
 
bool bitsLT (MVT VT) const
 Return true if this has less bits than VT.
 
bool bitsLE (MVT VT) const
 Return true if this has no more bits than VT.
 

Static Public Member Functions

static MVT getFloatingPointVT (unsigned BitWidth)
 
static MVT getIntegerVT (unsigned BitWidth)
 
static MVT getVectorVT (MVT VT, unsigned NumElements)
 
static MVT getScalableVectorVT (MVT VT, unsigned NumElements)
 
static MVT getVectorVT (MVT VT, unsigned NumElements, bool IsScalable)
 
static MVT getVectorVT (MVT VT, ElementCount EC)
 
static MVT getVT (Type *Ty, bool HandleUnknown=false)
 Return the value type corresponding to the specified type.
 
static auto all_valuetypes ()
 SimpleValueType Iteration.
 
static auto integer_valuetypes ()
 
static auto fp_valuetypes ()
 
static auto vector_valuetypes ()
 
static auto fixedlen_vector_valuetypes ()
 
static auto scalable_vector_valuetypes ()
 
static auto integer_fixedlen_vector_valuetypes ()
 
static auto fp_fixedlen_vector_valuetypes ()
 
static auto integer_scalable_vector_valuetypes ()
 
static auto fp_scalable_vector_valuetypes ()
 

Public Attributes

SimpleValueType SimpleTy = INVALID_SIMPLE_VALUE_TYPE
 

Detailed Description

Machine Value Type.

Every type that is supported natively by some processor targeted by LLVM occurs here. This means that any legal value type can be represented by an MVT.

Definition at line 34 of file MachineValueType.h.

Member Enumeration Documentation

◆ SimpleValueType

Enumerator
INVALID_SIMPLE_VALUE_TYPE 
VALUETYPE_SIZE 
MAX_ALLOWED_VALUETYPE 

Definition at line 36 of file MachineValueType.h.

Constructor & Destructor Documentation

◆ MVT() [1/2]

constexpr llvm::MVT::MVT ( )
constexprdefault

Referenced by getVT().

◆ MVT() [2/2]

constexpr llvm::MVT::MVT ( SimpleValueType  SVT)
inlineconstexpr

Definition at line 61 of file MachineValueType.h.

Member Function Documentation

◆ all_valuetypes()

static auto llvm::MVT::all_valuetypes ( )
inlinestatic

SimpleValueType Iteration.

Definition at line 489 of file MachineValueType.h.

References llvm::enum_seq_inclusive(), and llvm::force_iteration_on_noniterable_enum.

Referenced by llvm::TargetLoweringBase::initActions().

◆ bitsGE()

bool llvm::MVT::bitsGE ( MVT  VT) const
inline

Return true if this has no less bits than VT.

Definition at line 407 of file MachineValueType.h.

References assert(), isScalableVector(), and knownBitsGE().

Referenced by llvm::RISCVTargetLowering::LowerOperation().

◆ bitsGT()

bool llvm::MVT::bitsGT ( MVT  VT) const
inline

Return true if this has more bits than VT.

Definition at line 400 of file MachineValueType.h.

References assert(), isScalableVector(), and knownBitsGT().

Referenced by getSmallestVTForIndex(), getVRGatherIndexType(), LowerFCOPYSIGN(), and lowerVECTOR_SHUFFLE().

◆ bitsLE()

bool llvm::MVT::bitsLE ( MVT  VT) const
inline

◆ bitsLT()

bool llvm::MVT::bitsLT ( MVT  VT) const
inline

Return true if this has less bits than VT.

Definition at line 414 of file MachineValueType.h.

References assert(), isScalableVector(), and knownBitsLT().

Referenced by LowerFCOPYSIGN(), lowerVectorIntrinsicScalars(), llvm::RISCVTargetLowering::PerformDAGCombine(), and promoteVCIXScalar().

◆ changeTypeToInteger()

MVT llvm::MVT::changeTypeToInteger ( )
inline

Return the type converted to an equivalently sized integer or vector with integer element type.

Similar to changeVectorElementTypeToInteger, but also handles scalars.

Definition at line 213 of file MachineValueType.h.

References changeVectorElementTypeToInteger(), getIntegerVT(), getSizeInBits(), and isVector().

Referenced by llvm::EVT::changeTypeToInteger(), getVRGatherIndexType(), getWideningInterleave(), lowerShuffleWithPERMV(), lowerVECTOR_SHUFFLE(), and matchBinaryShuffle().

◆ changeVectorElementType()

MVT llvm::MVT::changeVectorElementType ( MVT  EltVT) const
inline

◆ changeVectorElementTypeToInteger()

MVT llvm::MVT::changeVectorElementTypeToInteger ( ) const
inline

◆ dump()

void MVT::dump ( ) const

Support for debugging, callable in GDB: VT.dump()

Definition at line 650 of file ValueTypes.cpp.

References llvm::dbgs(), and print().

◆ fixedlen_vector_valuetypes()

static auto llvm::MVT::fixedlen_vector_valuetypes ( )
inlinestatic

◆ fp_fixedlen_vector_valuetypes()

static auto llvm::MVT::fp_fixedlen_vector_valuetypes ( )
inlinestatic

◆ fp_scalable_vector_valuetypes()

static auto llvm::MVT::fp_scalable_vector_valuetypes ( )
inlinestatic

◆ fp_valuetypes()

static auto llvm::MVT::fp_valuetypes ( )
inlinestatic

◆ getDoubleNumVectorElementsVT()

MVT llvm::MVT::getDoubleNumVectorElementsVT ( ) const
inline

◆ getFixedSizeInBits()

uint64_t llvm::MVT::getFixedSizeInBits ( ) const
inline

◆ getFloatingPointVT()

static MVT llvm::MVT::getFloatingPointVT ( unsigned  BitWidth)
inlinestatic

◆ getHalfNumVectorElementsVT()

MVT llvm::MVT::getHalfNumVectorElementsVT ( ) const
inline

◆ getIntegerVT()

static MVT llvm::MVT::getIntegerVT ( unsigned  BitWidth)
inlinestatic

Definition at line 437 of file MachineValueType.h.

References INVALID_SIMPLE_VALUE_TYPE.

Referenced by changeTypeToInteger(), changeVectorElementTypeToInteger(), combineBitcast(), combineConcatVectorOps(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), llvm::computeSignatureVTs(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::SelectionDAG::getBitcastedAnyExtOrTrunc(), llvm::SelectionDAG::getBitcastedSExtOrTrunc(), llvm::SelectionDAG::getBitcastedZExtOrTrunc(), llvm::RISCVTTIImpl::getCastInstrCost(), getDeinterleaveViaVNSRL(), getDWordFromOffset(), llvm::EVT::getIntegerVT(), llvm::getMVTForLLT(), llvm::RISCVTargetLowering::getOptimalMemOpType(), getPermuteNode(), llvm::TargetLoweringBase::getPointerMemTy(), llvm::TargetLoweringBase::getPointerTy(), llvm::AArch64TargetLowering::getPointerTy(), getRegistersForValue(), llvm::TargetLoweringBase::getScalarShiftAmountTy(), llvm::M68kTargetLowering::getScalarShiftAmountTy(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), getVCIXISDNodeWCHAIN(), getVectorBitwiseReduce(), llvm::SPIRVTargetLowering::getVectorIdxTy(), getVT(), getWideningInterleave(), llvm::TargetLoweringBase::hasFastEqualityCompare(), llvm::X86TargetLowering::hasFastEqualityCompare(), llvm::TargetLoweringBase::initActions(), insert1BitVector(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), isLegalBitRotate(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), LowerABD(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), LowerCTPOP(), lowerFCOPYSIGN64(), LowerFunnelShift(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBlend(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleToEXPAND(), lowerShuffleWithPACK(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerVECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), lowerX86FPLogicOp(), matchPERM(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), memsetStore(), performBitcastCombine(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), PerformEXTRACTCombine(), performSETCCCombine(), PerformVECREDUCE_ADDCombine(), PerformVQDMULHCombine(), processVCIXOperands(), llvm::X86TargetLowering::ReplaceNodeResults(), scaleVectorType(), llvm::AArch64TargetLowering::shouldTransformSignedTruncationCheck(), llvm::X86TargetLowering::shouldTransformSignedTruncationCheck(), ShrinkLoadReplaceStoreWithStore(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), llvm::SparcTargetLowering::SparcTargetLowering(), llvm::HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(), llvm::SystemZTargetLowering::SystemZTargetLowering(), TryCombineBaseUpdate(), tryWidenMaskForShuffle(), unpackFromMemLoc(), vectorToScalarBitmask(), and llvm::X86TargetLowering::X86TargetLowering().

◆ getPow2VectorType()

MVT llvm::MVT::getPow2VectorType ( ) const
inline

◆ getScalableVectorVT()

static MVT llvm::MVT::getScalableVectorVT ( MVT  VT,
unsigned  NumElements 
)
inlinestatic

◆ getScalarSizeInBits()

uint64_t llvm::MVT::getScalarSizeInBits ( ) const
inline

Definition at line 342 of file MachineValueType.h.

References llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::getFixedValue(), getScalarType(), and getSizeInBits().

Referenced by canonicalizeBitSelect(), llvm::RISCV::CC_RISCV(), llvm::RISCV::CC_RISCV_FastCC(), combineAddOfPMADDWD(), combineAndnp(), combineBitOpWithPACK(), combineBlendOfPermutes(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineMOVMSK(), combineOrXorWithSETCC(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineTESTP(), combineVEXTRACT_STORE(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), llvm::TargetLoweringBase::computeRegisterProperties(), llvm::RISCVTargetLowering::computeVLMAXBounds(), createPackShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), expandFP_TO_UINT_SSE(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), llvm::X86TTIImpl::getCmpSelInstrCost(), getConstantVector(), getConstVector(), llvm::RegsForValue::getCopyFromRegs(), getDeinterleaveViaVNSRL(), getFauxShuffleMask(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::RTLIB::getOUTLINE_ATOMIC(), getPack(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::SystemZTargetLowering::getPreferredVectorAction(), getPSHUFShuffleMask(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarValueForVectorElement(), llvm::RISCVTTIImpl::getShuffleCost(), getSmallestVTForIndex(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeToPromoteTo(), getVectorTypeBreakdownMVT(), getVRGatherIndexType(), getWideningInterleave(), is128BitLaneCrossingShuffleMask(), isDeinterleaveShuffle(), isHorizontalBinOp(), isInterleaveShuffle(), isRepeatedShuffleMask(), isRepeatedTargetShuffleMask(), lower256BitShuffle(), LowerABD(), LowerADDSAT_SUBSAT(), LowerBITREVERSE_XOP(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), LowerCTTZ(), LowerEXTEND_VECTOR_INREG(), LowerFABSorFNEG(), LowerFCOPYSIGN(), LowerFunnelShift(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerRotate(), LowerShift(), LowerShiftByScalarImmediate(), lowerShuffleAsBitRotate(), lowerShuffleAsBlend(), lowerShuffleAsBlendAndPermute(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsByteShiftMask(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerTruncateVecI1(), lowerV4X128Shuffle(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZInRegLUT(), lowerVectorIntrinsicScalars(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), matchShuffleAsBlend(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::X86::mayFoldLoadIntoBroadcastFromMem(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFP_TO_INTCombine(), PerformVQDMULHCombine(), processPSInputArgs(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::RISCVDAGToDAGISel::selectVLSEG(), llvm::RISCVDAGToDAGISel::selectVLSEGFF(), llvm::RISCVDAGToDAGISel::selectVLXSEG(), llvm::RISCVDAGToDAGISel::selectVSSEG(), llvm::RISCVDAGToDAGISel::selectVSXSEG(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and vectorizeExtractedCast().

◆ getScalarStoreSize()

uint64_t llvm::MVT::getScalarStoreSize ( ) const
inline

◆ getScalarType()

MVT llvm::MVT::getScalarType ( ) const
inline

If this is a vector, return the element type, otherwise return this.

Definition at line 255 of file MachineValueType.h.

References getVectorElementType(), and isVector().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineMOVMSK(), combineStore(), combineTargetShuffle(), constructDup(), createVariablePermute(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), getAVX512TruncNode(), getConstantVector(), getFauxShuffleMask(), getIEEEProperties(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarSizeInBits(), getScalarStoreSize(), getTargetShuffleMask(), getTargetVShiftNode(), getVRGatherIndexType(), isInlineableLiteralOp16(), llvm::RISCVTargetLowering::isShuffleMaskLegal(), llvm::X86TargetLowering::isShuffleMaskLegal(), LowerBITREVERSE(), lowerBuildVectorAsBroadcast(), lowerBuildVectorToBitOp(), LowerMLOAD(), LowerMSTORE(), LowerRotate(), lowerShuffleAsBroadcast(), lowerShuffleAsVALIGN(), lowerShuffleAsVTRUNC(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsRotate(), LowerVectorCTPOP(), matchUnaryShuffle(), scalarizeVectorStore(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), vectorizeExtractedCast(), and widenSubVector().

◆ getSizeInBits()

TypeSize llvm::MVT::getSizeInBits ( ) const
inline

Returns the size of the specified MVT in bits.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 304 of file MachineValueType.h.

References assert(), INVALID_SIMPLE_VALUE_TYPE, llvm_unreachable, llvm::Other, SimpleTy, and VALUETYPE_SIZE.

Referenced by Analyze_CC_Sparc64_Full(), Analyze_CC_Sparc64_Half(), llvm::MachineIRBuilder::buildExtractVectorElementConstant(), canonicalizeBitSelect(), CC_ARM_AAPCS_Custom_Aggregate(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), changeVectorElementTypeToInteger(), combineAndLoadToBZHI(), combineEXTRACT_SUBVECTOR(), combinePredicateReduction(), combinePTESTCC(), combineSetCCMOVMSK(), combineShiftRightArithmetic(), combineTargetShuffle(), combineVectorHADDSUB(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), llvm::RISCVTargetLowering::computeVLMAXBounds(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), createVariablePermute(), createVPDPBUSD(), DecodePALIGNRMask(), llvm::TargetLowering::expandUnalignedLoad(), llvm::TargetLowering::expandUnalignedStore(), llvm::FastISel::fastEmit_ri_(), finishStackBlock(), genShuffleBland(), getAVX512Node(), getAVX512TruncNode(), getCopyFromParts(), getCopyFromPartsVector(), getCopyToParts(), getCopyToPartsVector(), getFauxShuffleMask(), getFixedSizeInBits(), getFltSemantics(), getHopForBuildVector(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), llvm::RISCVTargetLowering::getLMULCost(), llvm::TargetLoweringBase::getNumRegisters(), getPack(), llvm::HvxSelector::getPairVT(), llvm::PPCTargetLowering::getPreferredVectorAction(), getPromotedVectorElementType(), getPSHUFShuffleMask(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::ARMTargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::SystemZTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), getRegistersForValue(), llvm::RegsForValue::getRegsAndSizes(), getScalarSizeInBits(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::TargetLoweringBase::getShiftAmountTy(), llvm::X86TTIImpl::getShuffleCost(), llvm::HvxSelector::getSingleVT(), getStoreSize(), getTargetShuffleAndZeroables(), getTargetVShiftNode(), llvm::HexagonSubtarget::getTypeAlignment(), llvm::TargetLoweringBase::getVaListSizeInBits(), llvm::AArch64TargetLowering::getVaListSizeInBits(), llvm::TargetLoweringBase::getVectorTypeBreakdown(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getZeroVector(), group2Shuffle(), insert1BitVector(), isByteSized(), IsElementEquivalent(), isHorizontalBinOp(), llvm::X86TargetLowering::isShuffleMaskLegal(), isSupportedType(), isTargetShuffleEquivalent(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), knownBitsGE(), knownBitsGT(), knownBitsLE(), knownBitsLT(), llvm::LLT::LLT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAsSplatVectorLoad(), llvm::HexagonTargetLowering::LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), llvm::SystemZTargetLowering::LowerCall(), llvm::TargetLowering::LowerCallTo(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCTLZ(), LowerEXTEND_VECTOR_INREG(), LowerEXTRACT_VECTOR_ELT_SSE4(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::VETargetLowering::LowerFormalArguments(), llvm::SparcTargetLowering::LowerFormalArguments_64(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), LowerHorizontalByteSum(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), llvm::RISCVTargetLowering::LowerOperation(), LowerPARITY(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsDecomposedShuffleMerge(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsLanePermuteAndRepeatedMask(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsSplitOrBlend(), lowerShuffleAsTruncBroadcast(), lowerShuffleAsUNPCKAndPermute(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleViaVRegSplitting(), lowerShuffleWithPACK(), lowerShuffleWithPERMV(), lowerShuffleWithPSHUFB(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND_Mask(), llvm::LanaiTargetLowering::LowerSRL_PARTS(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchBinaryShuffle(), MatchingStackOffset(), matchShuffleAsBlend(), matchUnaryPermuteShuffle(), narrowExtractedVectorSelect(), llvm::TargetLowering::ParseConstraints(), performCONCAT_VECTORSCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), performFpToIntCombine(), performScatterStoreCombine(), PerformTruncatingStoreCombine(), PerformVCVTCombine(), PerformVDIVCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HexagonDAGToDAGISel::SelectQ2V(), llvm::RISCVDAGToDAGISel::selectSExtBits(), llvm::LoongArchDAGToDAGISel::selectSExti32(), llvm::HexagonDAGToDAGISel::SelectV2Q(), llvm::HexagonDAGToDAGISel::SelectVAlign(), llvm::RISCVDAGToDAGISel::selectZExtBits(), llvm::LoongArchDAGToDAGISel::selectZExti32(), setGroupSize(), shouldTransformMulToShiftsAddsSubs(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), TryCombineBaseUpdate(), tryCombineShiftImm(), llvm::RISCVDAGToDAGISel::trySignedBitfieldExtract(), UnpackFromArgumentSlot(), and useRVVForFixedLengthVectorVT().

◆ getStoreSize()

TypeSize llvm::MVT::getStoreSize ( ) const
inline

◆ getStoreSizeInBits()

TypeSize llvm::MVT::getStoreSizeInBits ( ) const
inline

Return the number of bits overwritten by a store of the specified value type.

If the value type is a scalable vector type, the scalable property will be set and the runtime size will be a positive integer multiple of the base size.

Definition at line 369 of file MachineValueType.h.

References getStoreSize().

Referenced by llvm::HexagonTargetLowering::LowerCall(), and llvm::HexagonTargetLowering::LowerFormalArguments().

◆ getVectorElementCount()

ElementCount llvm::MVT::getVectorElementCount ( ) const
inline

◆ getVectorElementType()

MVT llvm::MVT::getVectorElementType ( ) const
inline

Definition at line 259 of file MachineValueType.h.

References llvm_unreachable, and SimpleTy.

Referenced by changeVectorElementTypeToInteger(), combineBitcast(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineShuffleToAddSubOrFMAddSub(), combineTargetShuffle(), llvm::TargetLoweringBase::computeRegisterProperties(), convertShiftLeftToScale(), ExtendToType(), getConstVector(), getContainerForFixedLengthVector(), getDeinterleaveViaVNSRL(), getDoubleNumVectorElementsVT(), getHalfNumVectorElementsVT(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMUL(), getLMUL1VT(), getPow2VectorType(), llvm::HexagonTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), getShuffleScalarElt(), getTargetVShiftByConstNode(), getTargetVShiftNode(), llvm::AArch64TargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getUnderlyingExtractedFromVec(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getVectorTypeBreakdownMVT(), getWideningInterleave(), getZeroVector(), incDecVectorConstant(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), llvm::HexagonSubtarget::isHVXElementType(), llvm::HexagonSubtarget::isHVXVectorType(), isLegalT2AddressImmediate(), llvm::RISCVTargetLowering::joinRegisterPartsIntoValue(), llvm::LLT::LLT(), LowerANY_EXTEND(), LowerAVXExtend(), LowerBITCAST(), lowerBitreverseShuffle(), lowerBUILD_VECTOR(), LowerBUILD_VECTORvXi1(), lowerBuildVectorOfConstants(), LowerBuildVectorv4x32(), LowerCONCAT_VECTORS(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerEXTEND_VECTOR_INREG(), llvm::HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(), lowerFP_TO_INT_SAT(), LowerHorizontalByteSum(), LowerIntVSETCC_AVX512(), LowerLoad(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), llvm::RISCVTargetLowering::LowerOperation(), LowerSCALAR_TO_VECTOR(), lowerScalarInsert(), llvm::HexagonTargetLowering::LowerSETCC(), lowerShuffleAsBitBlend(), lowerShuffleAsBitMask(), lowerShuffleAsBroadcast(), lowerShuffleAsElementInsertion(), lowerShuffleAsTruncBroadcast(), lowerShuffleViaVRegSplitting(), lowerShuffleWithUndefHalf(), LowerSIGN_EXTEND(), LowerSIGN_EXTEND_Mask(), LowerTruncateVecI1(), LowerTruncateVecPack(), LowerTruncateVecPackWithSignBits(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), llvm::HexagonTargetLowering::LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorCTLZ(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowerVSETCCWithSUBUS(), LowerZERO_EXTEND(), LowerZERO_EXTEND_Mask(), matchSplatAsGather(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), llvm::RISCVTargetLowering::PerformDAGCombine(), preAssignMask(), llvm::RISCVDAGToDAGISel::PreprocessISelDAG(), llvm::RISCVTargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), splitAndLowerShuffle(), llvm::RISCVTargetLowering::splitValueIntoRegisterParts(), llvm::splitVectorType(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), widenMaskVectorType(), and llvm::X86TargetLowering::X86TargetLowering().

◆ getVectorMinNumElements()

unsigned llvm::MVT::getVectorMinNumElements ( ) const
inline

Given a vector type, return the minimum number of elements it contains.

Definition at line 273 of file MachineValueType.h.

References llvm_unreachable, and SimpleTy.

Referenced by llvm::HexagonTargetLowering::getPreferredVectorAction(), getVectorElementCount(), getVectorNumElements(), isPow2VectorType(), llvm::LLT::LLT(), lowerBUILD_VECTOR(), and lowerShuffleViaVRegSplitting().

◆ getVectorNumElements()

unsigned llvm::MVT::getVectorNumElements ( ) const
inline

Definition at line 290 of file MachineValueType.h.

References getVectorMinNumElements(), isScalableVector(), and llvm::reportInvalidSizeRequest().

Referenced by llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeShuffleMaskWithHorizOp(), combineAndnp(), combineBitcast(), combineBlendOfPermutes(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineMOVMSK(), combinePredicateReduction(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVEXTRACT_STORE(), combineX86INT_TO_FP(), combineX86ShuffleChain(), llvm::X86TargetLowering::ComputeNumSignBitsForTargetNode(), convertShiftLeftToScale(), createPackShuffleMask(), createShuffleStride(), llvm::createSplat2ShuffleMask(), createVariablePermute(), DecodePALIGNRMask(), ExpandHorizontalBinOp(), ExtendToType(), ExtractBitFromMaskVector(), genShuffleBland(), llvm::AArch64TTIImpl::getArithmeticReductionCost(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512TruncNode(), getConstVector(), getContainerForFixedLengthVector(), getDefaultVLOps(), getExtractedDemandedElts(), getFauxShuffleMask(), getGatherNode(), getHopForBuildVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), getPack(), llvm::SITargetLowering::getPreferredVectorAction(), llvm::NVPTXTargetLowering::getPreferredVectorAction(), llvm::PPCTargetLowering::getPreferredVectorAction(), llvm::X86TargetLowering::getPreferredVectorAction(), llvm::X86TTIImpl::getReplicationShuffleCost(), llvm::X86TTIImpl::getShuffleCost(), getShuffleHalfVectors(), getShuffleScalarElt(), getShuffleVectorZeroOrUndef(), getTargetShuffleAndZeroables(), getTargetShuffleMask(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), getUnderlyingExtractedFromVec(), getVectorMaskingNode(), getVRGatherIndexType(), getZeroVector(), group2Shuffle(), incDecVectorConstant(), insert1BitVector(), InsertBitToMaskVector(), isAddSubOrSubAdd(), IsElementEquivalent(), llvm::HexagonTargetLowering::isExtractSubvectorCheap(), isHopBuildVector(), isHorizontalBinOp(), isInterleaveShuffle(), lower1BitShuffle(), lower256BitShuffle(), LowerAsSplatVectorLoad(), LowerAVXCONCAT_VECTORS(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBitreverseShuffle(), llvm::HexagonTargetLowering::LowerBUILD_VECTOR(), llvm::VETargetLowering::lowerBUILD_VECTOR(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), LowerBuildVectorAsInsert(), lowerBuildVectorOfConstants(), lowerBuildVectorToBitOp(), llvm::HexagonTargetLowering::LowerCONCAT_VECTORS(), LowerCONCAT_VECTORSvXi1(), LowerEXTEND_VECTOR_INREG(), LowerFunnelShift(), LowerLoad(), LowerMGATHER(), LowerMSCATTER(), LowerMUL(), LowerMULH(), LowerMULO(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBlend(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsLanePermuteAndPermute(), lowerShuffleAsRepeatedMaskAndLanePermute(), lowerShuffleAsShift(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleAsZeroOrAnyExtend(), lowerShuffleOfExtractsAsVperm(), lowerShufflePairAsUNPCKAndPermute(), lowerShuffleToEXPAND(), lowerShuffleViaVRegSplitting(), lowerShuffleWithPERMV(), lowerShuffleWithUndefHalf(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), LowerSIGN_EXTEND_Mask(), lowerToAddSubOrFMAddSub(), LowerToHorizontalOp(), LowerTruncateVecI1(), LowerTruncateVecPack(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), lowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLEAsVSlide1(), lowerVECTOR_SHUFFLEAsVSlideup(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), LowerVectorCTPOPInRegLUT(), llvm::HexagonTargetLowering::LowerVSELECT(), LowerVSETCC(), LowervXi8MulWithUNPCK(), LowerZERO_EXTEND_Mask(), matchShuffleAsEXTRQ(), matchShuffleAsINSERTQ(), matchShuffleWithPACK(), matchShuffleWithSHUFPD(), matchShuffleWithUNPCK(), matchUnaryShuffle(), narrowExtractedVectorSelect(), performConcatVectorsCombine(), performLOADCombine(), PerformVECREDUCE_ADDCombine(), llvm::X86TargetLowering::ReplaceNodeResults(), scalarizeVectorStore(), scaleVectorType(), llvm::HexagonDAGToDAGISel::SelectExtractSubvector(), llvm::HvxSelector::selectExtractSubvector(), setGroupSize(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), splitAndLowerShuffle(), tryExtendDUPToExtractHigh(), useRVVForFixedLengthVectorVT(), vectorizeExtractedCast(), and widenMaskVectorType().

◆ getVectorVT() [1/3]

static MVT llvm::MVT::getVectorVT ( MVT  VT,
ElementCount  EC 
)
inlinestatic

Definition at line 473 of file MachineValueType.h.

References getScalableVectorVT(), and getVectorVT().

◆ getVectorVT() [2/3]

static MVT llvm::MVT::getVectorVT ( MVT  VT,
unsigned  NumElements 
)
inlinestatic

Definition at line 447 of file MachineValueType.h.

References INVALID_SIMPLE_VALUE_TYPE.

Referenced by llvm::AArch64TargetLowering::AArch64TargetLowering(), AddCombineBUILD_VECTORToVPADDL(), canonicalizeBitSelect(), canonicalizeShuffleMaskWithHorizOp(), changeVectorElementType(), changeVectorElementTypeToInteger(), combineArithReduction(), combineBitcast(), combineConcatVectorOps(), combineCVTP2I_CVTTP2I(), combineExtractVectorElt(), combineExtractWithShuffle(), combineFaddCFmul(), combineMOVMSK(), combineMulToPMADDWD(), combinePredicateReduction(), combinePTESTCC(), combineSetCCMOVMSK(), combineStore(), combineTargetShuffle(), combineVectorHADDSUB(), combineX86INT_TO_FP(), combineX86ShuffleChain(), combineX86ShufflesConstants(), ConstantBuildVector(), constructDup(), constructRetValue(), createPSADBW(), createVariablePermute(), createVPDPBUSD(), detectPMADDUBSW(), EltsFromConsecutiveLoads(), ExtractBitFromMaskVector(), llvm::X86TTIImpl::getArithmeticInstrCost(), getAVX512Node(), getAVX512TruncNode(), llvm::HvxSelector::getBoolVT(), getBuildDwordsVector(), getConstVector(), getDeinterleaveViaVNSRL(), getDoubleNumVectorElementsVT(), getDWordFromOffset(), getGatherNode(), getHalfNumVectorElementsVT(), llvm::X86TTIImpl::getInterleavedMemoryOpCostAVX512(), llvm::getLegalVectorType(), llvm::VECustomDAG::getMaskBroadcast(), getMaskNode(), getMaskTypeFor(), llvm::getMVTForLLT(), getOnesVector(), llvm::RISCVTargetLowering::getOptimalMemOpType(), llvm::HvxSelector::getPairVT(), getPermuteNode(), getPow2VectorType(), getPrefetchNode(), getPromotedVectorElementType(), getScatterNode(), llvm::ARMTargetLowering::getSetCCResultType(), llvm::HvxSelector::getSingleVT(), getTargetVShiftNode(), llvm::ARMTargetLowering::getTgtMemIntrinsic(), llvm::X86TargetLowering::getTgtMemIntrinsic(), llvm::TargetLoweringBase::getTypeConversion(), getVCIXISDNodeWCHAIN(), getVectorMaskingNode(), getVectorTypeBreakdownMVT(), llvm::EVT::getVectorVT(), getVectorVT(), getVT(), getWideningInterleave(), getZeroVector(), llvm::HexagonTargetLowering::HexagonTargetLowering(), InsertBitToMaskVector(), is128BitUnpackShuffleMask(), isLegalBitRotate(), llvm::HexagonSubtarget::isTypeForHVX(), llvm::SystemZVectorConstantInfo::isVectorConstantLegal(), lower1BitShuffle(), lower256BitShuffle(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), lowerBUILD_VECTOR(), lowerBuildVectorAsBroadcast(), lowerBuildVectorOfConstants(), LowerCONCAT_VECTORS_i1(), LowerCTPOP(), LowerEXTRACT_SUBVECTOR(), LowerFMINIMUM_FMAXIMUM(), lowerFPToIntToFP(), LowerFunnelShift(), LowerHorizontalByteSum(), LowerI64IntToFP_AVX512DQ(), LowerINTRINSIC_W_CHAIN(), LowerMGATHER(), LowerMLOAD(), LowerMSCATTER(), LowerMSTORE(), LowerMUL(), LowerMULH(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), LowerRotate(), LowerSCALAR_TO_VECTOR(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), LowerShiftByScalarImmediate(), LowerShiftByScalarVariable(), lowerShuffleAsBitMask(), lowerShuffleAsBlend(), lowerShuffleAsBlendOfPSHUFBs(), lowerShuffleAsBroadcast(), lowerShuffleAsByteRotate(), lowerShuffleAsByteRotateAndPermute(), lowerShuffleAsElementInsertion(), lowerShuffleAsPermuteAndUnpack(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVTRUNC(), lowerShuffleToEXPAND(), lowerShuffleViaVRegSplitting(), lowerShuffleWithPACK(), lowerShuffleWithPSHUFB(), lowerShuffleWithVPMOV(), LowerSIGN_EXTEND_Mask(), LowerStore(), LowerTruncateVecI1(), LowerTruncateVecPack(), llvm::HexagonTargetLowering::LowerUnalignedLoad(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16GeneralSingleInputShuffle(), llvm::HexagonTargetLowering::LowerVECTOR_SHIFT(), LowerVECTOR_SHUFFLE(), lowerVECTOR_SHUFFLE(), LowerVectorAllEqual(), LowerVectorCTLZ_AVX512CDI(), LowerVectorCTLZInRegLUT(), LowerVectorCTPOP(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorIntrinsicScalars(), llvm::HexagonTargetLowering::LowerVSELECT(), LowervXi8MulWithUNPCK(), lowerX86FPLogicOp(), LowerZERO_EXTEND_Mask(), matchBinaryPermuteShuffle(), matchShuffleAsBitRotate(), matchShuffleAsShift(), matchShuffleAsVTRUNC(), matchShuffleWithPACK(), matchUnaryPermuteShuffle(), matchUnaryShuffle(), llvm::MipsTargetLowering::MipsTargetLowering(), narrowExtractedVectorSelect(), NarrowVector(), performCONCAT_VECTORSCombine(), performConcatVectorsCombine(), performLOADCombine(), PerformVQDMULHCombine(), processVCIXOperands(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::RISCVTargetLowering::RISCVTargetLowering(), scaleVectorType(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), skipExtensionForVectorMULL(), SkipExtensionForVMULL(), splatPartsI64WithVL(), splitAndLowerShuffle(), llvm::splitVectorType(), TryCombineBaseUpdate(), tryExtendDUPToExtractHigh(), tryWidenMaskForShuffle(), vectorizeExtractedCast(), vectorToScalarBitmask(), widenSubVector(), and WidenVector().

◆ getVectorVT() [3/3]

static MVT llvm::MVT::getVectorVT ( MVT  VT,
unsigned  NumElements,
bool  IsScalable 
)
inlinestatic

Definition at line 467 of file MachineValueType.h.

References getScalableVectorVT(), and getVectorVT().

◆ getVT()

MVT MVT::getVT ( Type Ty,
bool  HandleUnknown = false 
)
static

◆ integer_fixedlen_vector_valuetypes()

static auto llvm::MVT::integer_fixedlen_vector_valuetypes ( )
inlinestatic

◆ integer_scalable_vector_valuetypes()

static auto llvm::MVT::integer_scalable_vector_valuetypes ( )
inlinestatic

◆ integer_valuetypes()

static auto llvm::MVT::integer_valuetypes ( )
inlinestatic

◆ is1024BitVector()

bool llvm::MVT::is1024BitVector ( ) const
inline

Return true if this is a 1024-bit vector type.

Definition at line 167 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

◆ is128BitVector()

bool llvm::MVT::is128BitVector ( ) const
inline

◆ is16BitVector()

bool llvm::MVT::is16BitVector ( ) const
inline

Return true if this is a 16-bit vector type.

Definition at line 137 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

◆ is2048BitVector()

bool llvm::MVT::is2048BitVector ( ) const
inline

Return true if this is a 2048-bit vector type.

Definition at line 172 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

◆ is256BitVector()

bool llvm::MVT::is256BitVector ( ) const
inline

◆ is32BitVector()

bool llvm::MVT::is32BitVector ( ) const
inline

Return true if this is a 32-bit vector type.

Definition at line 142 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

Referenced by CC_AArch64_Custom_Block(), and LowerStore().

◆ is512BitVector()

bool llvm::MVT::is512BitVector ( ) const
inline

◆ is64BitVector()

bool llvm::MVT::is64BitVector ( ) const
inline

Return true if this is a 64-bit vector type.

Definition at line 147 of file MachineValueType.h.

References getFixedSizeInBits(), and isFixedLengthVector().

Referenced by CC_AArch64_Custom_Block(), LowerStore(), and tryExtendDUPToExtractHigh().

◆ isByteSized()

bool llvm::MVT::isByteSized ( ) const
inline

Returns true if the number of bits for the type is a multiple of an 8-bit byte.

Definition at line 375 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< LeafTy, ValueTy >::isKnownMultipleOf().

◆ isFixedLengthVector()

bool llvm::MVT::isFixedLengthVector ( ) const
inline

◆ isFloatingPoint()

bool llvm::MVT::isFloatingPoint ( ) const
inline

◆ isInteger()

bool llvm::MVT::isInteger ( ) const
inline

◆ isOverloaded()

bool llvm::MVT::isOverloaded ( ) const
inline

Return true if this is an overloaded type for TableGen.

Definition at line 177 of file MachineValueType.h.

References SimpleTy.

◆ isPow2VectorType()

bool llvm::MVT::isPow2VectorType ( ) const
inline

◆ isScalableTargetExtVT()

bool llvm::MVT::isScalableTargetExtVT ( ) const
inline

Return true if this is a custom target type that has a scalable size.

Definition at line 122 of file MachineValueType.h.

References SimpleTy.

Referenced by isScalableVT(), and llvm::LLT::LLT().

◆ isScalableVector()

bool llvm::MVT::isScalableVector ( ) const
inline

◆ isScalableVT()

bool llvm::MVT::isScalableVT ( ) const
inline

Return true if the type is a scalable type.

Definition at line 127 of file MachineValueType.h.

References isScalableTargetExtVT(), and isScalableVector().

◆ isScalarInteger()

bool llvm::MVT::isScalarInteger ( ) const
inline

◆ isValid()

bool llvm::MVT::isValid ( ) const
inline

◆ isVector()

bool llvm::MVT::isVector ( ) const
inline

Return true if this is a vector value type.

Definition at line 109 of file MachineValueType.h.

References SimpleTy.

Referenced by llvm::PPCTargetLowering::allowsMisalignedMemoryAccesses(), llvm::AMDGPUTargetLowering::analyzeFormalArgumentsCompute(), canonicalizeBitSelect(), llvm::RISCV::CC_RISCV(), llvm::RISCV::CC_RISCV_FastCC(), CC_X86_32_VectorCall(), CC_X86_64_VectorCall(), changeTypeToInteger(), combineAndnp(), combineX86ShuffleChain(), combineX86ShufflesRecursively(), constructRetValue(), convertLocVTToValVT(), convertValVTToLocVT(), llvm::X86TTIImpl::getArithmeticReductionCost(), getAVX512Node(), llvm::X86TTIImpl::getCmpSelInstrCost(), getCopyFromParts(), getCopyToPartsVector(), llvm::X86TTIImpl::getInterleavedMemoryOpCost(), llvm::AArch64TTIImpl::getIntrinsicInstrCost(), llvm::X86TTIImpl::getIntrinsicInstrCost(), llvm::getLLTForMVT(), llvm::RISCVTargetLowering::getLMULCost(), getMaskTypeFor(), getMemCmpLoad(), llvm::X86TTIImpl::getMinMaxReductionCost(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::SPIRVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::X86TTIImpl::getReplicationShuffleCost(), getScalarType(), getScalarValueForVectorElement(), llvm::X86TargetLowering::getSetCCResultType(), llvm::X86TTIImpl::getShuffleCost(), llvm::CallLowering::ValueHandler::getStackValueStoreType(), getTargetVShiftNode(), llvm::TargetLoweringBase::getTypeConversion(), llvm::HexagonSubtarget::isHVXElementType(), isValueTypeInRegForCC(), llvm::LLT::LLT(), LowerADDSAT_SUBSAT(), llvm::X86TargetLowering::LowerAsmOutputForConstraint(), LowerAVXExtend(), LowerBITCAST(), LowerBITREVERSE(), LowerBITREVERSE_XOP(), llvm::RISCVTargetLowering::LowerCall(), LowerCTLZ(), LowerCTPOP(), LowerCTTZ(), LowerFABSorFNEG(), LowerFCOPYSIGN(), lowerFMAXIMUM_FMINIMUM(), llvm::RISCVTargetLowering::LowerFormalArguments(), lowerFP_TO_INT_SAT(), lowerFPToIntToFP(), lowerFTRUNC_FCEIL_FFLOOR_FROUND(), LowerFunnelShift(), LowerLoad(), LowerMULO(), llvm::RISCVTargetLowering::LowerOperation(), llvm::AArch64CallLowering::lowerReturn(), LowerRotate(), llvm::HexagonTargetLowering::LowerSETCC(), LowerShift(), lowerShuffleAsTruncBroadcast(), LowerSIGN_EXTEND(), llvm::AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(), lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND(), lowerVectorXRINT(), lowerX86FPLogicOp(), performConcatVectorsCombine(), preAssignMask(), processPSInputArgs(), promoteXINT_TO_FP(), llvm::X86TargetLowering::ReplaceNodeResults(), llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), and llvm::splitVectorType().

◆ knownBitsGE()

bool llvm::MVT::knownBitsGE ( MVT  VT) const
inline

Return true if we know at compile time this has more than or the same bits as VT.

Definition at line 384 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGE().

Referenced by bitsGE().

◆ knownBitsGT()

bool llvm::MVT::knownBitsGT ( MVT  VT) const
inline

Return true if we know at compile time this has more bits than VT.

Definition at line 378 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownGT().

Referenced by bitsGT().

◆ knownBitsLE()

bool llvm::MVT::knownBitsLE ( MVT  VT) const
inline

Return true if we know at compile time this has fewer than or the same bits as VT.

Definition at line 395 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLE().

Referenced by bitsLE().

◆ knownBitsLT()

bool llvm::MVT::knownBitsLT ( MVT  VT) const
inline

Return true if we know at compile time this has fewer bits than VT.

Definition at line 389 of file MachineValueType.h.

References getSizeInBits(), and llvm::details::FixedOrScalableQuantity< TypeSize, uint64_t >::isKnownLT().

Referenced by bitsLT().

◆ operator!=()

bool llvm::MVT::operator!= ( const MVT S) const
inline

Definition at line 66 of file MachineValueType.h.

References SimpleTy.

◆ operator<()

bool llvm::MVT::operator< ( const MVT S) const
inline

Definition at line 64 of file MachineValueType.h.

References SimpleTy.

◆ operator<=()

bool llvm::MVT::operator<= ( const MVT S) const
inline

Definition at line 68 of file MachineValueType.h.

References SimpleTy.

◆ operator==()

bool llvm::MVT::operator== ( const MVT S) const
inline

Definition at line 65 of file MachineValueType.h.

References SimpleTy.

◆ operator>()

bool llvm::MVT::operator> ( const MVT S) const
inline

Definition at line 63 of file MachineValueType.h.

References SimpleTy.

◆ operator>=()

bool llvm::MVT::operator>= ( const MVT S) const
inline

Definition at line 67 of file MachineValueType.h.

References SimpleTy.

◆ print()

void MVT::print ( raw_ostream OS) const

Implement operator<<.

Definition at line 656 of file ValueTypes.cpp.

References llvm::EVT::getEVTString(), INVALID_SIMPLE_VALUE_TYPE, OS, and SimpleTy.

Referenced by dump(), and llvm::operator<<().

◆ scalable_vector_valuetypes()

static auto llvm::MVT::scalable_vector_valuetypes ( )
inlinestatic

◆ vector_valuetypes()

static auto llvm::MVT::vector_valuetypes ( )
inlinestatic

Member Data Documentation

◆ SimpleTy

Definition at line 58 of file MachineValueType.h.

Referenced by AddCombineBUILD_VECTORToVPADDL(), llvm::TargetLoweringBase::AddPromotedToType(), llvm::TargetLoweringBase::addRegisterClass(), llvm::ARMTargetLowering::allowsMisalignedMemoryAccesses(), llvm::MipsSETargetLowering::allowsMisalignedMemoryAccesses(), AVRDAGToDAGISel::select< ISD::LOAD >(), CC_AArch64_Custom_Block(), CC_AIX(), CC_ARM_AAPCS_Custom_Aggregate(), changeVectorElementType(), changeVectorElementTypeToInteger(), llvm::SITargetLowering::checkAsmConstraintValA(), combineBitcastvxi1(), llvm::VETargetLowering::combineSelectCC(), ComputePTXValueVTs(), convertFPToInt(), createVariablePermute(), llvm::SITargetLowering::denormalsEnabledForType(), llvm::SelectionDAG::EVTToAPFloatSemantics(), llvm::TargetLowering::expandBSWAP(), llvm::TargetLowering::expandVPBSWAP(), llvm::TargetLowering::findOptimalMemOpLowering(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::ARMTargetLowering::findRepresentativeClass(), llvm::X86TargetLowering::findRepresentativeClass(), foldVectorXorShiftIntoCmp(), llvm::TargetLoweringBase::getAtomicLoadExtAction(), llvm::R600RegisterInfo::getCFGStructurizerRegClass(), llvm::TargetLoweringBase::getCondCodeAction(), getContainerForFixedLengthVector(), llvm::EVT::getEVTString(), getExtensionTo64Bits(), getIEEEProperties(), getImplicitScaleFactor(), getLdStRegType(), llvm::TargetLoweringBase::getLoadExtAction(), llvm::TargetLoweringBase::getNumRegisters(), llvm::TargetLoweringBase::getOperationAction(), getPackedSVEVectorVT(), getPredicateForFixedLengthVector(), llvm::TargetLoweringBase::getRegClassFor(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(), llvm::M68kTargetLowering::getRegForInlineAsmConstraint(), llvm::RISCVTargetLowering::getRegForInlineAsmConstraint(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetLoweringBase::getRegisterType(), llvm::TargetLoweringBase::getRepRegClassCostFor(), llvm::TargetLoweringBase::getRepRegClassFor(), llvm::TargetLoweringBase::getSetCCResultType(), getSizeInBits(), getSVEContainerType(), llvm::TargetLoweringBase::getTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::getTypeAction(), llvm::TargetLoweringBase::getTypeConversion(), llvm::EVT::getTypeForEVT(), llvm::TargetLoweringBase::getTypeToPromoteTo(), llvm::SelectionDAG::getValueType(), getVectorElementType(), getVectorMinNumElements(), getVectorTyFromPredicateVector(), llvm::AArch64TargetLowering::getVectorTypeBreakdownForCallingConv(), getVPTESTMOpc(), Is16bitsType(), is32Bit(), isConstantSplatVectorMaskForType(), isFixedLengthVector(), isFloatingPoint(), llvm::AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SITargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::LoongArchTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::X86TargetLowering::isFMAFasterThanFMulAndFAdd(), llvm::ARMTargetLowering::isFNegFree(), llvm::PPCTargetLowering::isFPImmLegal(), isInteger(), isLegalAddressImmediate(), llvm::ARMTargetLowering::isLegalAddressingMode(), llvm::RISCVTargetLowering::isLegalElementTypeForRVV(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::ARMTargetLowering::isLegalT2ScaledAddressingMode(), isOverloaded(), IsPTXVectorType(), isScalableTargetExtVT(), isScalableVector(), isScalarInteger(), llvm::TargetLoweringBase::isTypeLegal(), isValid(), llvm::HexagonInstrInfo::isValidAutoIncImm(), isValidIndexedLoad(), isVector(), llvm::ARMTargetLowering::isZExtFree(), llvm::X86TargetLowering::isZExtFree(), llvm::XCoreTargetLowering::isZExtFree(), lower128BitShuffle(), lower1BitShuffle(), lower256BitShuffle(), lower512BitShuffle(), LowerADDSUBSAT(), llvm::SystemZTargetLowering::LowerFormalArguments(), lowerRegToMasks(), lowerShuffleAsBlend(), lowerUINT_TO_FP_vec(), operator!=(), llvm::EVT::operator!=(), operator<(), operator<=(), operator==(), operator>(), operator>=(), performUADDVZextCombine(), performUzpCombine(), performVSelectCombine(), print(), ReplaceINTRINSIC_W_CHAIN(), ReplaceLoadVector(), llvm::RISCVDAGToDAGISel::Select(), llvm::HexagonDAGToDAGISel::SelectIndexedLoad(), llvm::HexagonDAGToDAGISel::SelectIndexedStore(), llvm::TargetLoweringBase::setAtomicLoadExtAction(), llvm::TargetLoweringBase::setCondCodeAction(), llvm::TargetLoweringBase::setLoadExtAction(), llvm::TargetLoweringBase::setOperationAction(), llvm::TargetLoweringBase::setTruncStoreAction(), llvm::TargetLoweringBase::ValueTypeActionImpl::setTypeAction(), llvm::ARMTargetLowering::shouldConvertFpToSat(), llvm::RISCVTargetLowering::shouldConvertFpToSat(), llvm::X86InstrInfo::shouldScheduleLoadsNear(), unpackFromRegLoc(), usePartialVectorLoads(), useRVVForFixedLengthVectorVT(), llvm::AArch64TargetLowering::useSVEForFixedLengthVectorVT(), X86ChooseCmpImmediateOpcode(), and X86ChooseCmpOpcode().


The documentation for this class was generated from the following files: