LLVM  10.0.0svn
LegalizeDAG.cpp
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1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAG::Legalize method.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/SetVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Metadata.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/Support/Casting.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/Debug.h"
47 #include <algorithm>
48 #include <cassert>
49 #include <cstdint>
50 #include <tuple>
51 #include <utility>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "legalizedag"
56 
57 namespace {
58 
59 /// Keeps track of state when getting the sign of a floating-point value as an
60 /// integer.
61 struct FloatSignAsInt {
62  EVT FloatVT;
63  SDValue Chain;
64  SDValue FloatPtr;
65  SDValue IntPtr;
66  MachinePointerInfo IntPointerInfo;
67  MachinePointerInfo FloatPointerInfo;
68  SDValue IntValue;
69  APInt SignMask;
70  uint8_t SignBit;
71 };
72 
73 //===----------------------------------------------------------------------===//
74 /// This takes an arbitrary SelectionDAG as input and
75 /// hacks on it until the target machine can handle it. This involves
76 /// eliminating value sizes the machine cannot handle (promoting small sizes to
77 /// large sizes or splitting up large values into small values) as well as
78 /// eliminating operations the machine cannot handle.
79 ///
80 /// This code also does a small amount of optimization and recognition of idioms
81 /// as part of its processing. For example, if a target does not support a
82 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
83 /// will attempt merge setcc and brc instructions into brcc's.
84 class SelectionDAGLegalize {
85  const TargetMachine &TM;
86  const TargetLowering &TLI;
87  SelectionDAG &DAG;
88 
89  /// The set of nodes which have already been legalized. We hold a
90  /// reference to it in order to update as necessary on node deletion.
91  SmallPtrSetImpl<SDNode *> &LegalizedNodes;
92 
93  /// A set of all the nodes updated during legalization.
94  SmallSetVector<SDNode *, 16> *UpdatedNodes;
95 
96  EVT getSetCCResultType(EVT VT) const {
97  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
98  }
99 
100  // Libcall insertion helpers.
101 
102 public:
103  SelectionDAGLegalize(SelectionDAG &DAG,
104  SmallPtrSetImpl<SDNode *> &LegalizedNodes,
105  SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
106  : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
107  LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
108 
109  /// Legalizes the given operation.
110  void LegalizeOp(SDNode *Node);
111 
112 private:
113  SDValue OptimizeFloatStore(StoreSDNode *ST);
114 
115  void LegalizeLoadOps(SDNode *Node);
116  void LegalizeStoreOps(SDNode *Node);
117 
118  /// Some targets cannot handle a variable
119  /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
120  /// is necessary to spill the vector being inserted into to memory, perform
121  /// the insert there, and then read the result back.
122  SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
123  const SDLoc &dl);
124  SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
125  const SDLoc &dl);
126 
127  /// Return a vector shuffle operation which
128  /// performs the same shuffe in terms of order or result bytes, but on a type
129  /// whose vector element type is narrower than the original shuffle type.
130  /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
131  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
132  SDValue N1, SDValue N2,
133  ArrayRef<int> Mask) const;
134 
135  bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
136  bool &NeedInvert, const SDLoc &dl);
137 
138  SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
139 
140  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
141  SDNode *Node, bool isSigned);
142  SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
143  RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
144  RTLIB::Libcall Call_F128,
145  RTLIB::Libcall Call_PPCF128);
146  SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
147  RTLIB::Libcall Call_I8,
148  RTLIB::Libcall Call_I16,
149  RTLIB::Libcall Call_I32,
150  RTLIB::Libcall Call_I64,
151  RTLIB::Libcall Call_I128);
152  SDValue ExpandArgFPLibCall(SDNode *Node,
153  RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
154  RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
155  RTLIB::Libcall Call_PPCF128);
156  void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
157  void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
158 
159  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
160  const SDLoc &dl);
161  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
162  const SDLoc &dl, SDValue ChainIn);
163  SDValue ExpandBUILD_VECTOR(SDNode *Node);
164  SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
165  void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
166  SmallVectorImpl<SDValue> &Results);
167  void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
168  SDValue Value) const;
169  SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
170  SDValue NewIntValue) const;
171  SDValue ExpandFCOPYSIGN(SDNode *Node) const;
172  SDValue ExpandFABS(SDNode *Node) const;
173  SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
174  const SDLoc &dl);
175  SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
176  const SDLoc &dl);
177  SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
178  const SDLoc &dl);
179 
180  SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
181  SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
182 
183  SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
184  SDValue ExpandInsertToVectorThroughStack(SDValue Op);
185  SDValue ExpandVectorBuildThroughStack(SDNode* Node);
186 
187  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
188  SDValue ExpandConstant(ConstantSDNode *CP);
189 
190  // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
191  bool ExpandNode(SDNode *Node);
192  void ConvertNodeToLibcall(SDNode *Node);
193  void PromoteNode(SDNode *Node);
194 
195 public:
196  // Node replacement helpers
197 
198  void ReplacedNode(SDNode *N) {
199  LegalizedNodes.erase(N);
200  if (UpdatedNodes)
201  UpdatedNodes->insert(N);
202  }
203 
204  void ReplaceNode(SDNode *Old, SDNode *New) {
205  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
206  dbgs() << " with: "; New->dump(&DAG));
207 
208  assert(Old->getNumValues() == New->getNumValues() &&
209  "Replacing one node with another that produces a different number "
210  "of values!");
211  DAG.ReplaceAllUsesWith(Old, New);
212  if (UpdatedNodes)
213  UpdatedNodes->insert(New);
214  ReplacedNode(Old);
215  }
216 
217  void ReplaceNode(SDValue Old, SDValue New) {
218  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
219  dbgs() << " with: "; New->dump(&DAG));
220 
221  DAG.ReplaceAllUsesWith(Old, New);
222  if (UpdatedNodes)
223  UpdatedNodes->insert(New.getNode());
224  ReplacedNode(Old.getNode());
225  }
226 
227  void ReplaceNode(SDNode *Old, const SDValue *New) {
228  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
229 
230  DAG.ReplaceAllUsesWith(Old, New);
231  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
232  LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
233  New[i]->dump(&DAG));
234  if (UpdatedNodes)
235  UpdatedNodes->insert(New[i].getNode());
236  }
237  ReplacedNode(Old);
238  }
239 
240  void ReplaceNodeWithValue(SDValue Old, SDValue New) {
241  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
242  dbgs() << " with: "; New->dump(&DAG));
243 
244  DAG.ReplaceAllUsesOfValueWith(Old, New);
245  if (UpdatedNodes)
246  UpdatedNodes->insert(New.getNode());
247  ReplacedNode(Old.getNode());
248  }
249 };
250 
251 } // end anonymous namespace
252 
253 /// Return a vector shuffle operation which
254 /// performs the same shuffle in terms of order or result bytes, but on a type
255 /// whose vector element type is narrower than the original shuffle type.
256 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
257 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
258  EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
259  ArrayRef<int> Mask) const {
260  unsigned NumMaskElts = VT.getVectorNumElements();
261  unsigned NumDestElts = NVT.getVectorNumElements();
262  unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
263 
264  assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
265 
266  if (NumEltsGrowth == 1)
267  return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
268 
269  SmallVector<int, 8> NewMask;
270  for (unsigned i = 0; i != NumMaskElts; ++i) {
271  int Idx = Mask[i];
272  for (unsigned j = 0; j != NumEltsGrowth; ++j) {
273  if (Idx < 0)
274  NewMask.push_back(-1);
275  else
276  NewMask.push_back(Idx * NumEltsGrowth + j);
277  }
278  }
279  assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
280  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
281  return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
282 }
283 
284 /// Expands the ConstantFP node to an integer constant or
285 /// a load from the constant pool.
286 SDValue
287 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
288  bool Extend = false;
289  SDLoc dl(CFP);
290 
291  // If a FP immediate is precise when represented as a float and if the
292  // target can do an extending load from float to double, we put it into
293  // the constant pool as a float, even if it's is statically typed as a
294  // double. This shrinks FP constants and canonicalizes them for targets where
295  // an FP extending load is the same cost as a normal load (such as on the x87
296  // fp stack or PPC FP unit).
297  EVT VT = CFP->getValueType(0);
298  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
299  if (!UseCP) {
300  assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
301  return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
302  (VT == MVT::f64) ? MVT::i64 : MVT::i32);
303  }
304 
305  APFloat APF = CFP->getValueAPF();
306  EVT OrigVT = VT;
307  EVT SVT = VT;
308 
309  // We don't want to shrink SNaNs. Converting the SNaN back to its real type
310  // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
311  if (!APF.isSignaling()) {
312  while (SVT != MVT::f32 && SVT != MVT::f16) {
313  SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
315  // Only do this if the target has a native EXTLOAD instruction from
316  // smaller type.
317  TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
318  TLI.ShouldShrinkFPConstant(OrigVT)) {
319  Type *SType = SVT.getTypeForEVT(*DAG.getContext());
320  LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
321  VT = SVT;
322  Extend = true;
323  }
324  }
325  }
326 
327  SDValue CPIdx =
328  DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
329  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
330  if (Extend) {
331  SDValue Result = DAG.getExtLoad(
332  ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
333  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
334  Alignment);
335  return Result;
336  }
337  SDValue Result = DAG.getLoad(
338  OrigVT, dl, DAG.getEntryNode(), CPIdx,
339  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
340  return Result;
341 }
342 
343 /// Expands the Constant node to a load from the constant pool.
344 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
345  SDLoc dl(CP);
346  EVT VT = CP->getValueType(0);
347  SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
348  TLI.getPointerTy(DAG.getDataLayout()));
349  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
350  SDValue Result = DAG.getLoad(
351  VT, dl, DAG.getEntryNode(), CPIdx,
352  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
353  return Result;
354 }
355 
356 /// Some target cannot handle a variable insertion index for the
357 /// INSERT_VECTOR_ELT instruction. In this case, it
358 /// is necessary to spill the vector being inserted into to memory, perform
359 /// the insert there, and then read the result back.
360 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
361  SDValue Val,
362  SDValue Idx,
363  const SDLoc &dl) {
364  SDValue Tmp1 = Vec;
365  SDValue Tmp2 = Val;
366  SDValue Tmp3 = Idx;
367 
368  // If the target doesn't support this, we have to spill the input vector
369  // to a temporary stack slot, update the element, then reload it. This is
370  // badness. We could also load the value into a vector register (either
371  // with a "move to register" or "extload into register" instruction, then
372  // permute it into place, if the idx is a constant and if the idx is
373  // supported by the target.
374  EVT VT = Tmp1.getValueType();
375  EVT EltVT = VT.getVectorElementType();
376  SDValue StackPtr = DAG.CreateStackTemporary(VT);
377 
378  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
379 
380  // Store the vector.
381  SDValue Ch = DAG.getStore(
382  DAG.getEntryNode(), dl, Tmp1, StackPtr,
383  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
384 
385  SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
386 
387  // Store the scalar value.
388  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT);
389  // Load the updated vector.
390  return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
391  DAG.getMachineFunction(), SPFI));
392 }
393 
394 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
395  SDValue Idx,
396  const SDLoc &dl) {
397  if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
398  // SCALAR_TO_VECTOR requires that the type of the value being inserted
399  // match the element type of the vector being created, except for
400  // integers in which case the inserted value can be over width.
401  EVT EltVT = Vec.getValueType().getVectorElementType();
402  if (Val.getValueType() == EltVT ||
403  (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
404  SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
405  Vec.getValueType(), Val);
406 
407  unsigned NumElts = Vec.getValueType().getVectorNumElements();
408  // We generate a shuffle of InVec and ScVec, so the shuffle mask
409  // should be 0,1,2,3,4,5... with the appropriate element replaced with
410  // elt 0 of the RHS.
411  SmallVector<int, 8> ShufOps;
412  for (unsigned i = 0; i != NumElts; ++i)
413  ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
414 
415  return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
416  }
417  }
418  return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
419 }
420 
421 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
422  LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
423  // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
424  // FIXME: We shouldn't do this for TargetConstantFP's.
425  // FIXME: move this to the DAG Combiner! Note that we can't regress due
426  // to phase ordering between legalized code and the dag combiner. This
427  // probably means that we need to integrate dag combiner and legalizer
428  // together.
429  // We generally can't do this one for long doubles.
430  SDValue Chain = ST->getChain();
431  SDValue Ptr = ST->getBasePtr();
432  unsigned Alignment = ST->getAlignment();
433  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
434  AAMDNodes AAInfo = ST->getAAInfo();
435  SDLoc dl(ST);
436  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
437  if (CFP->getValueType(0) == MVT::f32 &&
438  TLI.isTypeLegal(MVT::i32)) {
439  SDValue Con = DAG.getConstant(CFP->getValueAPF().
440  bitcastToAPInt().zextOrTrunc(32),
441  SDLoc(CFP), MVT::i32);
442  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), Alignment,
443  MMOFlags, AAInfo);
444  }
445 
446  if (CFP->getValueType(0) == MVT::f64) {
447  // If this target supports 64-bit registers, do a single 64-bit store.
448  if (TLI.isTypeLegal(MVT::i64)) {
449  SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
450  zextOrTrunc(64), SDLoc(CFP), MVT::i64);
451  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
452  Alignment, MMOFlags, AAInfo);
453  }
454 
455  if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
456  // Otherwise, if the target supports 32-bit registers, use 2 32-bit
457  // stores. If the target supports neither 32- nor 64-bits, this
458  // xform is certainly not worth it.
459  const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
460  SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
461  SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
462  if (DAG.getDataLayout().isBigEndian())
463  std::swap(Lo, Hi);
464 
465  Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
466  MMOFlags, AAInfo);
467  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
468  DAG.getConstant(4, dl, Ptr.getValueType()));
469  Hi = DAG.getStore(Chain, dl, Hi, Ptr,
470  ST->getPointerInfo().getWithOffset(4),
471  MinAlign(Alignment, 4U), MMOFlags, AAInfo);
472 
473  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
474  }
475  }
476  }
477  return SDValue(nullptr, 0);
478 }
479 
480 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
481  StoreSDNode *ST = cast<StoreSDNode>(Node);
482  SDValue Chain = ST->getChain();
483  SDValue Ptr = ST->getBasePtr();
484  SDLoc dl(Node);
485 
486  unsigned Alignment = ST->getAlignment();
487  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
488  AAMDNodes AAInfo = ST->getAAInfo();
489 
490  if (!ST->isTruncatingStore()) {
491  LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
492  if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
493  ReplaceNode(ST, OptStore);
494  return;
495  }
496 
497  SDValue Value = ST->getValue();
498  MVT VT = Value.getSimpleValueType();
499  switch (TLI.getOperationAction(ISD::STORE, VT)) {
500  default: llvm_unreachable("This action is not supported yet!");
501  case TargetLowering::Legal: {
502  // If this is an unaligned store and the target doesn't support it,
503  // expand it.
504  EVT MemVT = ST->getMemoryVT();
505  const DataLayout &DL = DAG.getDataLayout();
506  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT,
507  *ST->getMemOperand())) {
508  LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
509  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
510  ReplaceNode(SDValue(ST, 0), Result);
511  } else
512  LLVM_DEBUG(dbgs() << "Legal store\n");
513  break;
514  }
515  case TargetLowering::Custom: {
516  LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
517  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
518  if (Res && Res != SDValue(Node, 0))
519  ReplaceNode(SDValue(Node, 0), Res);
520  return;
521  }
523  MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
524  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
525  "Can only promote stores to same size type");
526  Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
527  SDValue Result =
528  DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
529  Alignment, MMOFlags, AAInfo);
530  ReplaceNode(SDValue(Node, 0), Result);
531  break;
532  }
533  }
534  return;
535  }
536 
537  LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
538  SDValue Value = ST->getValue();
539  EVT StVT = ST->getMemoryVT();
540  unsigned StWidth = StVT.getSizeInBits();
541  auto &DL = DAG.getDataLayout();
542 
543  if (StWidth != StVT.getStoreSizeInBits()) {
544  // Promote to a byte-sized store with upper bits zero if not
545  // storing an integral number of bytes. For example, promote
546  // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
547  EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
548  StVT.getStoreSizeInBits());
549  Value = DAG.getZeroExtendInReg(Value, dl, StVT);
550  SDValue Result =
551  DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
552  Alignment, MMOFlags, AAInfo);
553  ReplaceNode(SDValue(Node, 0), Result);
554  } else if (StWidth & (StWidth - 1)) {
555  // If not storing a power-of-2 number of bits, expand as two stores.
556  assert(!StVT.isVector() && "Unsupported truncstore!");
557  unsigned LogStWidth = Log2_32(StWidth);
558  assert(LogStWidth < 32);
559  unsigned RoundWidth = 1 << LogStWidth;
560  assert(RoundWidth < StWidth);
561  unsigned ExtraWidth = StWidth - RoundWidth;
562  assert(ExtraWidth < RoundWidth);
563  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
564  "Store size not an integral number of bytes!");
565  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
566  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
567  SDValue Lo, Hi;
568  unsigned IncrementSize;
569 
570  if (DL.isLittleEndian()) {
571  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
572  // Store the bottom RoundWidth bits.
573  Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
574  RoundVT, Alignment, MMOFlags, AAInfo);
575 
576  // Store the remaining ExtraWidth bits.
577  IncrementSize = RoundWidth / 8;
578  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
579  DAG.getConstant(IncrementSize, dl,
580  Ptr.getValueType()));
581  Hi = DAG.getNode(
582  ISD::SRL, dl, Value.getValueType(), Value,
583  DAG.getConstant(RoundWidth, dl,
584  TLI.getShiftAmountTy(Value.getValueType(), DL)));
585  Hi = DAG.getTruncStore(
586  Chain, dl, Hi, Ptr,
587  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
588  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
589  } else {
590  // Big endian - avoid unaligned stores.
591  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
592  // Store the top RoundWidth bits.
593  Hi = DAG.getNode(
594  ISD::SRL, dl, Value.getValueType(), Value,
595  DAG.getConstant(ExtraWidth, dl,
596  TLI.getShiftAmountTy(Value.getValueType(), DL)));
597  Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
598  RoundVT, Alignment, MMOFlags, AAInfo);
599 
600  // Store the remaining ExtraWidth bits.
601  IncrementSize = RoundWidth / 8;
602  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
603  DAG.getConstant(IncrementSize, dl,
604  Ptr.getValueType()));
605  Lo = DAG.getTruncStore(
606  Chain, dl, Value, Ptr,
607  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
608  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
609  }
610 
611  // The order of the stores doesn't matter.
612  SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
613  ReplaceNode(SDValue(Node, 0), Result);
614  } else {
615  switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
616  default: llvm_unreachable("This action is not supported yet!");
617  case TargetLowering::Legal: {
618  EVT MemVT = ST->getMemoryVT();
619  // If this is an unaligned store and the target doesn't support it,
620  // expand it.
621  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT,
622  *ST->getMemOperand())) {
623  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
624  ReplaceNode(SDValue(ST, 0), Result);
625  }
626  break;
627  }
628  case TargetLowering::Custom: {
629  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
630  if (Res && Res != SDValue(Node, 0))
631  ReplaceNode(SDValue(Node, 0), Res);
632  return;
633  }
635  assert(!StVT.isVector() &&
636  "Vector Stores are handled in LegalizeVectorOps");
637 
638  SDValue Result;
639 
640  // TRUNCSTORE:i16 i32 -> STORE i16
641  if (TLI.isTypeLegal(StVT)) {
642  Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
643  Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
644  Alignment, MMOFlags, AAInfo);
645  } else {
646  // The in-memory type isn't legal. Truncate to the type it would promote
647  // to, and then do a truncstore.
648  Value = DAG.getNode(ISD::TRUNCATE, dl,
649  TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
650  Value);
651  Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
652  StVT, Alignment, MMOFlags, AAInfo);
653  }
654 
655  ReplaceNode(SDValue(Node, 0), Result);
656  break;
657  }
658  }
659 }
660 
661 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
662  LoadSDNode *LD = cast<LoadSDNode>(Node);
663  SDValue Chain = LD->getChain(); // The chain.
664  SDValue Ptr = LD->getBasePtr(); // The base pointer.
665  SDValue Value; // The value returned by the load op.
666  SDLoc dl(Node);
667 
669  if (ExtType == ISD::NON_EXTLOAD) {
670  LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
671  MVT VT = Node->getSimpleValueType(0);
672  SDValue RVal = SDValue(Node, 0);
673  SDValue RChain = SDValue(Node, 1);
674 
675  switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
676  default: llvm_unreachable("This action is not supported yet!");
677  case TargetLowering::Legal: {
678  EVT MemVT = LD->getMemoryVT();
679  const DataLayout &DL = DAG.getDataLayout();
680  // If this is an unaligned load and the target doesn't support it,
681  // expand it.
682  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT,
683  *LD->getMemOperand())) {
684  std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
685  }
686  break;
687  }
689  if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
690  RVal = Res;
691  RChain = Res.getValue(1);
692  }
693  break;
694 
696  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
697  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
698  "Can only promote loads to same size type");
699 
700  SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
701  RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
702  RChain = Res.getValue(1);
703  break;
704  }
705  }
706  if (RChain.getNode() != Node) {
707  assert(RVal.getNode() != Node && "Load must be completely replaced");
708  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
709  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
710  if (UpdatedNodes) {
711  UpdatedNodes->insert(RVal.getNode());
712  UpdatedNodes->insert(RChain.getNode());
713  }
714  ReplacedNode(Node);
715  }
716  return;
717  }
718 
719  LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
720  EVT SrcVT = LD->getMemoryVT();
721  unsigned SrcWidth = SrcVT.getSizeInBits();
722  unsigned Alignment = LD->getAlignment();
723  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
724  AAMDNodes AAInfo = LD->getAAInfo();
725 
726  if (SrcWidth != SrcVT.getStoreSizeInBits() &&
727  // Some targets pretend to have an i1 loading operation, and actually
728  // load an i8. This trick is correct for ZEXTLOAD because the top 7
729  // bits are guaranteed to be zero; it helps the optimizers understand
730  // that these bits are zero. It is also useful for EXTLOAD, since it
731  // tells the optimizers that those bits are undefined. It would be
732  // nice to have an effective generic way of getting these benefits...
733  // Until such a way is found, don't insist on promoting i1 here.
734  (SrcVT != MVT::i1 ||
735  TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
737  // Promote to a byte-sized load if not loading an integral number of
738  // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
739  unsigned NewWidth = SrcVT.getStoreSizeInBits();
740  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
741  SDValue Ch;
742 
743  // The extra bits are guaranteed to be zero, since we stored them that
744  // way. A zext load from NVT thus automatically gives zext from SrcVT.
745 
746  ISD::LoadExtType NewExtType =
748 
749  SDValue Result =
750  DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Chain, Ptr,
751  LD->getPointerInfo(), NVT, Alignment, MMOFlags, AAInfo);
752 
753  Ch = Result.getValue(1); // The chain.
754 
755  if (ExtType == ISD::SEXTLOAD)
756  // Having the top bits zero doesn't help when sign extending.
757  Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
758  Result.getValueType(),
759  Result, DAG.getValueType(SrcVT));
760  else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
761  // All the top bits are guaranteed to be zero - inform the optimizers.
762  Result = DAG.getNode(ISD::AssertZext, dl,
763  Result.getValueType(), Result,
764  DAG.getValueType(SrcVT));
765 
766  Value = Result;
767  Chain = Ch;
768  } else if (SrcWidth & (SrcWidth - 1)) {
769  // If not loading a power-of-2 number of bits, expand as two loads.
770  assert(!SrcVT.isVector() && "Unsupported extload!");
771  unsigned LogSrcWidth = Log2_32(SrcWidth);
772  assert(LogSrcWidth < 32);
773  unsigned RoundWidth = 1 << LogSrcWidth;
774  assert(RoundWidth < SrcWidth);
775  unsigned ExtraWidth = SrcWidth - RoundWidth;
776  assert(ExtraWidth < RoundWidth);
777  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
778  "Load size not an integral number of bytes!");
779  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
780  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
781  SDValue Lo, Hi, Ch;
782  unsigned IncrementSize;
783  auto &DL = DAG.getDataLayout();
784 
785  if (DL.isLittleEndian()) {
786  // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
787  // Load the bottom RoundWidth bits.
788  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
789  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
790  AAInfo);
791 
792  // Load the remaining ExtraWidth bits.
793  IncrementSize = RoundWidth / 8;
794  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
795  DAG.getConstant(IncrementSize, dl,
796  Ptr.getValueType()));
797  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
798  LD->getPointerInfo().getWithOffset(IncrementSize),
799  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
800  AAInfo);
801 
802  // Build a factor node to remember that this load is independent of
803  // the other one.
804  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
805  Hi.getValue(1));
806 
807  // Move the top bits to the right place.
808  Hi = DAG.getNode(
809  ISD::SHL, dl, Hi.getValueType(), Hi,
810  DAG.getConstant(RoundWidth, dl,
811  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
812 
813  // Join the hi and lo parts.
814  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
815  } else {
816  // Big endian - avoid unaligned loads.
817  // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
818  // Load the top RoundWidth bits.
819  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
820  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
821  AAInfo);
822 
823  // Load the remaining ExtraWidth bits.
824  IncrementSize = RoundWidth / 8;
825  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
826  DAG.getConstant(IncrementSize, dl,
827  Ptr.getValueType()));
828  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
829  LD->getPointerInfo().getWithOffset(IncrementSize),
830  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
831  AAInfo);
832 
833  // Build a factor node to remember that this load is independent of
834  // the other one.
835  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
836  Hi.getValue(1));
837 
838  // Move the top bits to the right place.
839  Hi = DAG.getNode(
840  ISD::SHL, dl, Hi.getValueType(), Hi,
841  DAG.getConstant(ExtraWidth, dl,
842  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
843 
844  // Join the hi and lo parts.
845  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
846  }
847 
848  Chain = Ch;
849  } else {
850  bool isCustom = false;
851  switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
852  SrcVT.getSimpleVT())) {
853  default: llvm_unreachable("This action is not supported yet!");
855  isCustom = true;
858  Value = SDValue(Node, 0);
859  Chain = SDValue(Node, 1);
860 
861  if (isCustom) {
862  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
863  Value = Res;
864  Chain = Res.getValue(1);
865  }
866  } else {
867  // If this is an unaligned load and the target doesn't support it,
868  // expand it.
869  EVT MemVT = LD->getMemoryVT();
870  const DataLayout &DL = DAG.getDataLayout();
871  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT,
872  *LD->getMemOperand())) {
873  std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
874  }
875  }
876  break;
877 
878  case TargetLowering::Expand: {
879  EVT DestVT = Node->getValueType(0);
880  if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
881  // If the source type is not legal, see if there is a legal extload to
882  // an intermediate type that we can then extend further.
883  EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
884  if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
885  TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
886  // If we are loading a legal type, this is a non-extload followed by a
887  // full extend.
888  ISD::LoadExtType MidExtType =
889  (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
890 
891  SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
892  SrcVT, LD->getMemOperand());
893  unsigned ExtendOp =
895  Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
896  Chain = Load.getValue(1);
897  break;
898  }
899 
900  // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
901  // normal undefined upper bits behavior to allow using an in-reg extend
902  // with the illegal FP type, so load as an integer and do the
903  // from-integer conversion.
904  if (SrcVT.getScalarType() == MVT::f16) {
905  EVT ISrcVT = SrcVT.changeTypeToInteger();
906  EVT IDestVT = DestVT.changeTypeToInteger();
907  EVT ILoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
908 
909  SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, ILoadVT, Chain,
910  Ptr, ISrcVT, LD->getMemOperand());
911  Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
912  Chain = Result.getValue(1);
913  break;
914  }
915  }
916 
917  assert(!SrcVT.isVector() &&
918  "Vector Loads are handled in LegalizeVectorOps");
919 
920  // FIXME: This does not work for vectors on most targets. Sign-
921  // and zero-extend operations are currently folded into extending
922  // loads, whether they are legal or not, and then we end up here
923  // without any support for legalizing them.
924  assert(ExtType != ISD::EXTLOAD &&
925  "EXTLOAD should always be supported!");
926  // Turn the unsupported load into an EXTLOAD followed by an
927  // explicit zero/sign extend inreg.
928  SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
929  Node->getValueType(0),
930  Chain, Ptr, SrcVT,
931  LD->getMemOperand());
932  SDValue ValRes;
933  if (ExtType == ISD::SEXTLOAD)
934  ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
935  Result.getValueType(),
936  Result, DAG.getValueType(SrcVT));
937  else
938  ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
939  Value = ValRes;
940  Chain = Result.getValue(1);
941  break;
942  }
943  }
944  }
945 
946  // Since loads produce two values, make sure to remember that we legalized
947  // both of them.
948  if (Chain.getNode() != Node) {
949  assert(Value.getNode() != Node && "Load must be completely replaced");
950  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
951  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
952  if (UpdatedNodes) {
953  UpdatedNodes->insert(Value.getNode());
954  UpdatedNodes->insert(Chain.getNode());
955  }
956  ReplacedNode(Node);
957  }
958 }
959 
960 /// Return a legal replacement for the given operation, with all legal operands.
961 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
962  LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
963 
964  // Allow illegal target nodes and illegal registers.
965  if (Node->getOpcode() == ISD::TargetConstant ||
966  Node->getOpcode() == ISD::Register)
967  return;
968 
969 #ifndef NDEBUG
970  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
971  assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
973  "Unexpected illegal type!");
974 
975  for (const SDValue &Op : Node->op_values())
976  assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
978  Op.getOpcode() == ISD::TargetConstant ||
979  Op.getOpcode() == ISD::Register) &&
980  "Unexpected illegal type!");
981 #endif
982 
983  // Figure out the correct action; the way to query this varies by opcode
985  bool SimpleFinishLegalizing = true;
986  switch (Node->getOpcode()) {
989  case ISD::INTRINSIC_VOID:
990  case ISD::STACKSAVE:
991  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
992  break;
994  Action = TLI.getOperationAction(Node->getOpcode(),
995  Node->getValueType(0));
996  break;
997  case ISD::VAARG:
998  Action = TLI.getOperationAction(Node->getOpcode(),
999  Node->getValueType(0));
1000  if (Action != TargetLowering::Promote)
1001  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1002  break;
1003  case ISD::FP_TO_FP16:
1004  case ISD::SINT_TO_FP:
1005  case ISD::UINT_TO_FP:
1007  case ISD::LROUND:
1008  case ISD::LLROUND:
1009  case ISD::LRINT:
1010  case ISD::LLRINT:
1011  Action = TLI.getOperationAction(Node->getOpcode(),
1012  Node->getOperand(0).getValueType());
1013  break;
1014  case ISD::SIGN_EXTEND_INREG: {
1015  EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1016  Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1017  break;
1018  }
1019  case ISD::ATOMIC_STORE:
1020  Action = TLI.getOperationAction(Node->getOpcode(),
1021  Node->getOperand(2).getValueType());
1022  break;
1023  case ISD::SELECT_CC:
1024  case ISD::SETCC:
1025  case ISD::BR_CC: {
1026  unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1027  Node->getOpcode() == ISD::SETCC ? 2 : 1;
1028  unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1029  MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1030  ISD::CondCode CCCode =
1031  cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1032  Action = TLI.getCondCodeAction(CCCode, OpVT);
1033  if (Action == TargetLowering::Legal) {
1034  if (Node->getOpcode() == ISD::SELECT_CC)
1035  Action = TLI.getOperationAction(Node->getOpcode(),
1036  Node->getValueType(0));
1037  else
1038  Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1039  }
1040  break;
1041  }
1042  case ISD::LOAD:
1043  case ISD::STORE:
1044  // FIXME: Model these properly. LOAD and STORE are complicated, and
1045  // STORE expects the unlegalized operand in some cases.
1046  SimpleFinishLegalizing = false;
1047  break;
1048  case ISD::CALLSEQ_START:
1049  case ISD::CALLSEQ_END:
1050  // FIXME: This shouldn't be necessary. These nodes have special properties
1051  // dealing with the recursive nature of legalization. Removing this
1052  // special case should be done as part of making LegalizeDAG non-recursive.
1053  SimpleFinishLegalizing = false;
1054  break;
1055  case ISD::EXTRACT_ELEMENT:
1056  case ISD::FLT_ROUNDS_:
1057  case ISD::MERGE_VALUES:
1058  case ISD::EH_RETURN:
1060  case ISD::EH_DWARF_CFA:
1061  case ISD::EH_SJLJ_SETJMP:
1062  case ISD::EH_SJLJ_LONGJMP:
1064  // These operations lie about being legal: when they claim to be legal,
1065  // they should actually be expanded.
1066  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1067  if (Action == TargetLowering::Legal)
1068  Action = TargetLowering::Expand;
1069  break;
1070  case ISD::INIT_TRAMPOLINE:
1072  case ISD::FRAMEADDR:
1073  case ISD::RETURNADDR:
1074  case ISD::ADDROFRETURNADDR:
1075  case ISD::SPONENTRY:
1076  // These operations lie about being legal: when they claim to be legal,
1077  // they should actually be custom-lowered.
1078  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1079  if (Action == TargetLowering::Legal)
1080  Action = TargetLowering::Custom;
1081  break;
1082  case ISD::READCYCLECOUNTER:
1083  // READCYCLECOUNTER returns an i64, even if type legalization might have
1084  // expanded that to several smaller types.
1085  Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1086  break;
1087  case ISD::READ_REGISTER:
1088  case ISD::WRITE_REGISTER:
1089  // Named register is legal in the DAG, but blocked by register name
1090  // selection if not implemented by target (to chose the correct register)
1091  // They'll be converted to Copy(To/From)Reg.
1092  Action = TargetLowering::Legal;
1093  break;
1094  case ISD::DEBUGTRAP:
1095  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1096  if (Action == TargetLowering::Expand) {
1097  // replace ISD::DEBUGTRAP with ISD::TRAP
1098  SDValue NewVal;
1099  NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1100  Node->getOperand(0));
1101  ReplaceNode(Node, NewVal.getNode());
1102  LegalizeOp(NewVal.getNode());
1103  return;
1104  }
1105  break;
1106  case ISD::SADDSAT:
1107  case ISD::UADDSAT:
1108  case ISD::SSUBSAT:
1109  case ISD::USUBSAT: {
1110  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1111  break;
1112  }
1113  case ISD::SMULFIX:
1114  case ISD::SMULFIXSAT:
1115  case ISD::UMULFIX:
1116  case ISD::UMULFIXSAT: {
1117  unsigned Scale = Node->getConstantOperandVal(2);
1118  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
1119  Node->getValueType(0), Scale);
1120  break;
1121  }
1122  case ISD::MSCATTER:
1123  Action = TLI.getOperationAction(Node->getOpcode(),
1124  cast<MaskedScatterSDNode>(Node)->getValue().getValueType());
1125  break;
1126  case ISD::MSTORE:
1127  Action = TLI.getOperationAction(Node->getOpcode(),
1128  cast<MaskedStoreSDNode>(Node)->getValue().getValueType());
1129  break;
1130  case ISD::VECREDUCE_FADD:
1131  case ISD::VECREDUCE_FMUL:
1132  case ISD::VECREDUCE_ADD:
1133  case ISD::VECREDUCE_MUL:
1134  case ISD::VECREDUCE_AND:
1135  case ISD::VECREDUCE_OR:
1136  case ISD::VECREDUCE_XOR:
1137  case ISD::VECREDUCE_SMAX:
1138  case ISD::VECREDUCE_SMIN:
1139  case ISD::VECREDUCE_UMAX:
1140  case ISD::VECREDUCE_UMIN:
1141  case ISD::VECREDUCE_FMAX:
1142  case ISD::VECREDUCE_FMIN:
1143  Action = TLI.getOperationAction(
1144  Node->getOpcode(), Node->getOperand(0).getValueType());
1145  break;
1146  default:
1147  if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1148  Action = TargetLowering::Legal;
1149  } else {
1150  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1151  }
1152  break;
1153  }
1154 
1155  if (SimpleFinishLegalizing) {
1156  SDNode *NewNode = Node;
1157  switch (Node->getOpcode()) {
1158  default: break;
1159  case ISD::SHL:
1160  case ISD::SRL:
1161  case ISD::SRA:
1162  case ISD::ROTL:
1163  case ISD::ROTR: {
1164  // Legalizing shifts/rotates requires adjusting the shift amount
1165  // to the appropriate width.
1166  SDValue Op0 = Node->getOperand(0);
1167  SDValue Op1 = Node->getOperand(1);
1168  if (!Op1.getValueType().isVector()) {
1169  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1170  // The getShiftAmountOperand() may create a new operand node or
1171  // return the existing one. If new operand is created we need
1172  // to update the parent node.
1173  // Do not try to legalize SAO here! It will be automatically legalized
1174  // in the next round.
1175  if (SAO != Op1)
1176  NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1177  }
1178  }
1179  break;
1180  case ISD::FSHL:
1181  case ISD::FSHR:
1182  case ISD::SRL_PARTS:
1183  case ISD::SRA_PARTS:
1184  case ISD::SHL_PARTS: {
1185  // Legalizing shifts/rotates requires adjusting the shift amount
1186  // to the appropriate width.
1187  SDValue Op0 = Node->getOperand(0);
1188  SDValue Op1 = Node->getOperand(1);
1189  SDValue Op2 = Node->getOperand(2);
1190  if (!Op2.getValueType().isVector()) {
1191  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1192  // The getShiftAmountOperand() may create a new operand node or
1193  // return the existing one. If new operand is created we need
1194  // to update the parent node.
1195  if (SAO != Op2)
1196  NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1197  }
1198  break;
1199  }
1200  }
1201 
1202  if (NewNode != Node) {
1203  ReplaceNode(Node, NewNode);
1204  Node = NewNode;
1205  }
1206  switch (Action) {
1207  case TargetLowering::Legal:
1208  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1209  return;
1211  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1212  // FIXME: The handling for custom lowering with multiple results is
1213  // a complete mess.
1214  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1215  if (!(Res.getNode() != Node || Res.getResNo() != 0))
1216  return;
1217 
1218  if (Node->getNumValues() == 1) {
1219  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1220  // We can just directly replace this node with the lowered value.
1221  ReplaceNode(SDValue(Node, 0), Res);
1222  return;
1223  }
1224 
1225  SmallVector<SDValue, 8> ResultVals;
1226  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1227  ResultVals.push_back(Res.getValue(i));
1228  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1229  ReplaceNode(Node, ResultVals.data());
1230  return;
1231  }
1232  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1235  if (ExpandNode(Node))
1236  return;
1239  ConvertNodeToLibcall(Node);
1240  return;
1242  PromoteNode(Node);
1243  return;
1244  }
1245  }
1246 
1247  switch (Node->getOpcode()) {
1248  default:
1249 #ifndef NDEBUG
1250  dbgs() << "NODE: ";
1251  Node->dump( &DAG);
1252  dbgs() << "\n";
1253 #endif
1254  llvm_unreachable("Do not know how to legalize this operator!");
1255 
1256  case ISD::CALLSEQ_START:
1257  case ISD::CALLSEQ_END:
1258  break;
1259  case ISD::LOAD:
1260  return LegalizeLoadOps(Node);
1261  case ISD::STORE:
1262  return LegalizeStoreOps(Node);
1263  }
1264 }
1265 
1266 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1267  SDValue Vec = Op.getOperand(0);
1268  SDValue Idx = Op.getOperand(1);
1269  SDLoc dl(Op);
1270 
1271  // Before we generate a new store to a temporary stack slot, see if there is
1272  // already one that we can use. There often is because when we scalarize
1273  // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1274  // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1275  // the vector. If all are expanded here, we don't want one store per vector
1276  // element.
1277 
1278  // Caches for hasPredecessorHelper
1281  Visited.insert(Op.getNode());
1282  Worklist.push_back(Idx.getNode());
1283  SDValue StackPtr, Ch;
1284  for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1285  UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1286  SDNode *User = *UI;
1287  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1288  if (ST->isIndexed() || ST->isTruncatingStore() ||
1289  ST->getValue() != Vec)
1290  continue;
1291 
1292  // Make sure that nothing else could have stored into the destination of
1293  // this store.
1294  if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1295  continue;
1296 
1297  // If the index is dependent on the store we will introduce a cycle when
1298  // creating the load (the load uses the index, and by replacing the chain
1299  // we will make the index dependent on the load). Also, the store might be
1300  // dependent on the extractelement and introduce a cycle when creating
1301  // the load.
1302  if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
1303  ST->hasPredecessor(Op.getNode()))
1304  continue;
1305 
1306  StackPtr = ST->getBasePtr();
1307  Ch = SDValue(ST, 0);
1308  break;
1309  }
1310  }
1311 
1312  EVT VecVT = Vec.getValueType();
1313 
1314  if (!Ch.getNode()) {
1315  // Store the value to a temporary stack slot, then LOAD the returned part.
1316  StackPtr = DAG.CreateStackTemporary(VecVT);
1317  Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1318  MachinePointerInfo());
1319  }
1320 
1321  StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1322 
1323  SDValue NewLoad;
1324 
1325  if (Op.getValueType().isVector())
1326  NewLoad =
1327  DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, MachinePointerInfo());
1328  else
1329  NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1331  VecVT.getVectorElementType());
1332 
1333  // Replace the chain going out of the store, by the one out of the load.
1334  DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1335 
1336  // We introduced a cycle though, so update the loads operands, making sure
1337  // to use the original store's chain as an incoming chain.
1338  SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1339  NewLoad->op_end());
1340  NewLoadOperands[0] = Ch;
1341  NewLoad =
1342  SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1343  return NewLoad;
1344 }
1345 
1346 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1347  assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1348 
1349  SDValue Vec = Op.getOperand(0);
1350  SDValue Part = Op.getOperand(1);
1351  SDValue Idx = Op.getOperand(2);
1352  SDLoc dl(Op);
1353 
1354  // Store the value to a temporary stack slot, then LOAD the returned part.
1355  EVT VecVT = Vec.getValueType();
1356  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1357  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1358  MachinePointerInfo PtrInfo =
1359  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1360 
1361  // First store the whole vector.
1362  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1363 
1364  // Then store the inserted part.
1365  SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1366 
1367  // Store the subvector.
1368  Ch = DAG.getStore(Ch, dl, Part, SubStackPtr, MachinePointerInfo());
1369 
1370  // Finally, load the updated vector.
1371  return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1372 }
1373 
1374 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1375  // We can't handle this case efficiently. Allocate a sufficiently
1376  // aligned object on the stack, store each element into it, then load
1377  // the result as a vector.
1378  // Create the stack frame object.
1379  EVT VT = Node->getValueType(0);
1380  EVT EltVT = VT.getVectorElementType();
1381  SDLoc dl(Node);
1382  SDValue FIPtr = DAG.CreateStackTemporary(VT);
1383  int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1384  MachinePointerInfo PtrInfo =
1385  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1386 
1387  // Emit a store of each element to the stack slot.
1388  SmallVector<SDValue, 8> Stores;
1389  unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1390  assert(TypeByteSize > 0 && "Vector element type too small for stack store!");
1391  // Store (in the right endianness) the elements to memory.
1392  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1393  // Ignore undef elements.
1394  if (Node->getOperand(i).isUndef()) continue;
1395 
1396  unsigned Offset = TypeByteSize*i;
1397 
1398  SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1399  Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1400 
1401  // If the destination vector element type is narrower than the source
1402  // element type, only store the bits necessary.
1403  if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1404  Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1405  Node->getOperand(i), Idx,
1406  PtrInfo.getWithOffset(Offset), EltVT));
1407  } else
1408  Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1409  Idx, PtrInfo.getWithOffset(Offset)));
1410  }
1411 
1412  SDValue StoreChain;
1413  if (!Stores.empty()) // Not all undef elements?
1414  StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1415  else
1416  StoreChain = DAG.getEntryNode();
1417 
1418  // Result is a load from the stack slot.
1419  return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1420 }
1421 
1422 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1423 /// containing the sign bit if the target has no integer value capable of
1424 /// holding all bits of the floating-point value.
1425 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1426  const SDLoc &DL,
1427  SDValue Value) const {
1428  EVT FloatVT = Value.getValueType();
1429  unsigned NumBits = FloatVT.getSizeInBits();
1430  State.FloatVT = FloatVT;
1431  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1432  // Convert to an integer of the same size.
1433  if (TLI.isTypeLegal(IVT)) {
1434  State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1435  State.SignMask = APInt::getSignMask(NumBits);
1436  State.SignBit = NumBits - 1;
1437  return;
1438  }
1439 
1440  auto &DataLayout = DAG.getDataLayout();
1441  // Store the float to memory, then load the sign part out as an integer.
1442  MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1443  // First create a temporary that is aligned for both the load and store.
1444  SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1445  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1446  // Then store the float to it.
1447  State.FloatPtr = StackPtr;
1448  MachineFunction &MF = DAG.getMachineFunction();
1449  State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1450  State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1451  State.FloatPointerInfo);
1452 
1453  SDValue IntPtr;
1454  if (DataLayout.isBigEndian()) {
1455  assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1456  // Load out a legal integer with the same sign bit as the float.
1457  IntPtr = StackPtr;
1458  State.IntPointerInfo = State.FloatPointerInfo;
1459  } else {
1460  // Advance the pointer so that the loaded byte will contain the sign bit.
1461  unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1462  IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1463  DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1464  State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1465  ByteOffset);
1466  }
1467 
1468  State.IntPtr = IntPtr;
1469  State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1470  State.IntPointerInfo, MVT::i8);
1471  State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1472  State.SignBit = 7;
1473 }
1474 
1475 /// Replace the integer value produced by getSignAsIntValue() with a new value
1476 /// and cast the result back to a floating-point type.
1477 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1478  const SDLoc &DL,
1479  SDValue NewIntValue) const {
1480  if (!State.Chain)
1481  return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1482 
1483  // Override the part containing the sign bit in the value stored on the stack.
1484  SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1485  State.IntPointerInfo, MVT::i8);
1486  return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1487  State.FloatPointerInfo);
1488 }
1489 
1490 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1491  SDLoc DL(Node);
1492  SDValue Mag = Node->getOperand(0);
1493  SDValue Sign = Node->getOperand(1);
1494 
1495  // Get sign bit into an integer value.
1496  FloatSignAsInt SignAsInt;
1497  getSignAsIntValue(SignAsInt, DL, Sign);
1498 
1499  EVT IntVT = SignAsInt.IntValue.getValueType();
1500  SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1501  SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1502  SignMask);
1503 
1504  // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1505  EVT FloatVT = Mag.getValueType();
1506  if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1507  TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1508  SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1509  SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1510  SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1511  DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1512  return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1513  }
1514 
1515  // Transform Mag value to integer, and clear the sign bit.
1516  FloatSignAsInt MagAsInt;
1517  getSignAsIntValue(MagAsInt, DL, Mag);
1518  EVT MagVT = MagAsInt.IntValue.getValueType();
1519  SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1520  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1521  ClearSignMask);
1522 
1523  // Get the signbit at the right position for MagAsInt.
1524  int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1525  EVT ShiftVT = IntVT;
1526  if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1527  SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1528  ShiftVT = MagVT;
1529  }
1530  if (ShiftAmount > 0) {
1531  SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1532  SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst);
1533  } else if (ShiftAmount < 0) {
1534  SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
1535  SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
1536  }
1537  if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1538  SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1539  }
1540 
1541  // Store the part with the modified sign and convert back to float.
1542  SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1543  return modifySignAsInt(MagAsInt, DL, CopiedSign);
1544 }
1545 
1546 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1547  SDLoc DL(Node);
1548  SDValue Value = Node->getOperand(0);
1549 
1550  // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1551  EVT FloatVT = Value.getValueType();
1552  if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1553  SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1554  return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1555  }
1556 
1557  // Transform value to integer, clear the sign bit and transform back.
1558  FloatSignAsInt ValueAsInt;
1559  getSignAsIntValue(ValueAsInt, DL, Value);
1560  EVT IntVT = ValueAsInt.IntValue.getValueType();
1561  SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1562  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1563  ClearSignMask);
1564  return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1565 }
1566 
1567 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1569  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1570  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1571  " not tell us which reg is the stack pointer!");
1572  SDLoc dl(Node);
1573  EVT VT = Node->getValueType(0);
1574  SDValue Tmp1 = SDValue(Node, 0);
1575  SDValue Tmp2 = SDValue(Node, 1);
1576  SDValue Tmp3 = Node->getOperand(2);
1577  SDValue Chain = Tmp1.getOperand(0);
1578 
1579  // Chain the dynamic stack allocation so that it doesn't modify the stack
1580  // pointer when other instructions are using the stack.
1581  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1582 
1583  SDValue Size = Tmp2.getOperand(1);
1584  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1585  Chain = SP.getValue(1);
1586  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1587  unsigned StackAlign =
1588  DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1589  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1590  if (Align > StackAlign)
1591  Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1592  DAG.getConstant(-(uint64_t)Align, dl, VT));
1593  Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1594 
1595  Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1596  DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1597 
1598  Results.push_back(Tmp1);
1599  Results.push_back(Tmp2);
1600 }
1601 
1602 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1603 /// target.
1604 ///
1605 /// If the SETCC has been legalized using AND / OR, then the legalized node
1606 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1607 /// will be set to false.
1608 ///
1609 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1610 /// then the values of LHS and RHS will be swapped, CC will be set to the
1611 /// new condition, and NeedInvert will be set to false.
1612 ///
1613 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1614 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1615 /// will be set to true. The caller must invert the result of the SETCC with
1616 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1617 /// of a true/false result.
1618 ///
1619 /// \returns true if the SetCC has been legalized, false if it hasn't.
1620 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1621  SDValue &RHS, SDValue &CC,
1622  bool &NeedInvert,
1623  const SDLoc &dl) {
1624  MVT OpVT = LHS.getSimpleValueType();
1625  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1626  NeedInvert = false;
1627  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1628  default: llvm_unreachable("Unknown condition code action!");
1629  case TargetLowering::Legal:
1630  // Nothing to do.
1631  break;
1632  case TargetLowering::Expand: {
1634  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1635  std::swap(LHS, RHS);
1636  CC = DAG.getCondCode(InvCC);
1637  return true;
1638  }
1639  // Swapping operands didn't work. Try inverting the condition.
1640  bool NeedSwap = false;
1641  InvCC = getSetCCInverse(CCCode, OpVT.isInteger());
1642  if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1643  // If inverting the condition is not enough, try swapping operands
1644  // on top of it.
1645  InvCC = ISD::getSetCCSwappedOperands(InvCC);
1646  NeedSwap = true;
1647  }
1648  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1649  CC = DAG.getCondCode(InvCC);
1650  NeedInvert = true;
1651  if (NeedSwap)
1652  std::swap(LHS, RHS);
1653  return true;
1654  }
1655 
1657  unsigned Opc = 0;
1658  switch (CCCode) {
1659  default: llvm_unreachable("Don't know how to expand this condition!");
1660  case ISD::SETO:
1661  assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
1662  && "If SETO is expanded, SETOEQ must be legal!");
1663  CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1664  case ISD::SETUO:
1665  assert(TLI.isCondCodeLegal(ISD::SETUNE, OpVT)
1666  && "If SETUO is expanded, SETUNE must be legal!");
1667  CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1668  case ISD::SETOEQ:
1669  case ISD::SETOGT:
1670  case ISD::SETOGE:
1671  case ISD::SETOLT:
1672  case ISD::SETOLE:
1673  case ISD::SETONE:
1674  case ISD::SETUEQ:
1675  case ISD::SETUNE:
1676  case ISD::SETUGT:
1677  case ISD::SETUGE:
1678  case ISD::SETULT:
1679  case ISD::SETULE:
1680  // If we are floating point, assign and break, otherwise fall through.
1681  if (!OpVT.isInteger()) {
1682  // We can use the 4th bit to tell if we are the unordered
1683  // or ordered version of the opcode.
1684  CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1685  Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1686  CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1687  break;
1688  }
1689  // Fallthrough if we are unsigned integer.
1691  case ISD::SETLE:
1692  case ISD::SETGT:
1693  case ISD::SETGE:
1694  case ISD::SETLT:
1695  case ISD::SETNE:
1696  case ISD::SETEQ:
1697  // If all combinations of inverting the condition and swapping operands
1698  // didn't work then we have no means to expand the condition.
1699  llvm_unreachable("Don't know how to expand this condition!");
1700  }
1701 
1702  SDValue SetCC1, SetCC2;
1703  if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1704  // If we aren't the ordered or unorder operation,
1705  // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1706  SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1707  SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1708  } else {
1709  // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1710  SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1711  SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1712  }
1713  LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1714  RHS = SDValue();
1715  CC = SDValue();
1716  return true;
1717  }
1718  }
1719  return false;
1720 }
1721 
1722 /// Emit a store/load combination to the stack. This stores
1723 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1724 /// a load from the stack slot to DestVT, extending it if needed.
1725 /// The resultant code need not be legal.
1726 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1727  EVT DestVT, const SDLoc &dl) {
1728  return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode());
1729 }
1730 
1731 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1732  EVT DestVT, const SDLoc &dl,
1733  SDValue Chain) {
1734  // Create the stack frame object.
1735  unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1736  SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1737  SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1738 
1739  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1740  int SPFI = StackPtrFI->getIndex();
1741  MachinePointerInfo PtrInfo =
1742  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1743 
1744  unsigned SrcSize = SrcOp.getValueSizeInBits();
1745  unsigned SlotSize = SlotVT.getSizeInBits();
1746  unsigned DestSize = DestVT.getSizeInBits();
1747  Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1748  unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1749 
1750  // Emit a store to the stack slot. Use a truncstore if the input value is
1751  // later than DestVT.
1752  SDValue Store;
1753 
1754  if (SrcSize > SlotSize)
1755  Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo,
1756  SlotVT, SrcAlign);
1757  else {
1758  assert(SrcSize == SlotSize && "Invalid store");
1759  Store =
1760  DAG.getStore(Chain, dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1761  }
1762 
1763  // Result is a load from the stack slot.
1764  if (SlotSize == DestSize)
1765  return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1766 
1767  assert(SlotSize < DestSize && "Unknown extension!");
1768  return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1769  DestAlign);
1770 }
1771 
1772 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1773  SDLoc dl(Node);
1774  // Create a vector sized/aligned stack slot, store the value to element #0,
1775  // then load the whole vector back out.
1776  SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1777 
1778  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1779  int SPFI = StackPtrFI->getIndex();
1780 
1781  SDValue Ch = DAG.getTruncStore(
1782  DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1783  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1784  Node->getValueType(0).getVectorElementType());
1785  return DAG.getLoad(
1786  Node->getValueType(0), dl, Ch, StackPtr,
1787  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1788 }
1789 
1790 static bool
1792  const TargetLowering &TLI, SDValue &Res) {
1793  unsigned NumElems = Node->getNumOperands();
1794  SDLoc dl(Node);
1795  EVT VT = Node->getValueType(0);
1796 
1797  // Try to group the scalars into pairs, shuffle the pairs together, then
1798  // shuffle the pairs of pairs together, etc. until the vector has
1799  // been built. This will work only if all of the necessary shuffle masks
1800  // are legal.
1801 
1802  // We do this in two phases; first to check the legality of the shuffles,
1803  // and next, assuming that all shuffles are legal, to create the new nodes.
1804  for (int Phase = 0; Phase < 2; ++Phase) {
1806  NewIntermedVals;
1807  for (unsigned i = 0; i < NumElems; ++i) {
1808  SDValue V = Node->getOperand(i);
1809  if (V.isUndef())
1810  continue;
1811 
1812  SDValue Vec;
1813  if (Phase)
1814  Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1815  IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1816  }
1817 
1818  while (IntermedVals.size() > 2) {
1819  NewIntermedVals.clear();
1820  for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1821  // This vector and the next vector are shuffled together (simply to
1822  // append the one to the other).
1823  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1824 
1825  SmallVector<int, 16> FinalIndices;
1826  FinalIndices.reserve(IntermedVals[i].second.size() +
1827  IntermedVals[i+1].second.size());
1828 
1829  int k = 0;
1830  for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1831  ++j, ++k) {
1832  ShuffleVec[k] = j;
1833  FinalIndices.push_back(IntermedVals[i].second[j]);
1834  }
1835  for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1836  ++j, ++k) {
1837  ShuffleVec[k] = NumElems + j;
1838  FinalIndices.push_back(IntermedVals[i+1].second[j]);
1839  }
1840 
1841  SDValue Shuffle;
1842  if (Phase)
1843  Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1844  IntermedVals[i+1].first,
1845  ShuffleVec);
1846  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1847  return false;
1848  NewIntermedVals.push_back(
1849  std::make_pair(Shuffle, std::move(FinalIndices)));
1850  }
1851 
1852  // If we had an odd number of defined values, then append the last
1853  // element to the array of new vectors.
1854  if ((IntermedVals.size() & 1) != 0)
1855  NewIntermedVals.push_back(IntermedVals.back());
1856 
1857  IntermedVals.swap(NewIntermedVals);
1858  }
1859 
1860  assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1861  "Invalid number of intermediate vectors");
1862  SDValue Vec1 = IntermedVals[0].first;
1863  SDValue Vec2;
1864  if (IntermedVals.size() > 1)
1865  Vec2 = IntermedVals[1].first;
1866  else if (Phase)
1867  Vec2 = DAG.getUNDEF(VT);
1868 
1869  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1870  for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1871  ShuffleVec[IntermedVals[0].second[i]] = i;
1872  for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1873  ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1874 
1875  if (Phase)
1876  Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1877  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1878  return false;
1879  }
1880 
1881  return true;
1882 }
1883 
1884 /// Expand a BUILD_VECTOR node on targets that don't
1885 /// support the operation, but do support the resultant vector type.
1886 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1887  unsigned NumElems = Node->getNumOperands();
1888  SDValue Value1, Value2;
1889  SDLoc dl(Node);
1890  EVT VT = Node->getValueType(0);
1891  EVT OpVT = Node->getOperand(0).getValueType();
1892  EVT EltVT = VT.getVectorElementType();
1893 
1894  // If the only non-undef value is the low element, turn this into a
1895  // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1896  bool isOnlyLowElement = true;
1897  bool MoreThanTwoValues = false;
1898  bool isConstant = true;
1899  for (unsigned i = 0; i < NumElems; ++i) {
1900  SDValue V = Node->getOperand(i);
1901  if (V.isUndef())
1902  continue;
1903  if (i > 0)
1904  isOnlyLowElement = false;
1905  if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1906  isConstant = false;
1907 
1908  if (!Value1.getNode()) {
1909  Value1 = V;
1910  } else if (!Value2.getNode()) {
1911  if (V != Value1)
1912  Value2 = V;
1913  } else if (V != Value1 && V != Value2) {
1914  MoreThanTwoValues = true;
1915  }
1916  }
1917 
1918  if (!Value1.getNode())
1919  return DAG.getUNDEF(VT);
1920 
1921  if (isOnlyLowElement)
1922  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1923 
1924  // If all elements are constants, create a load from the constant pool.
1925  if (isConstant) {
1927  for (unsigned i = 0, e = NumElems; i != e; ++i) {
1928  if (ConstantFPSDNode *V =
1929  dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1930  CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1931  } else if (ConstantSDNode *V =
1932  dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1933  if (OpVT==EltVT)
1934  CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1935  else {
1936  // If OpVT and EltVT don't match, EltVT is not legal and the
1937  // element values have been promoted/truncated earlier. Undo this;
1938  // we don't want a v16i8 to become a v16i32 for example.
1939  const ConstantInt *CI = V->getConstantIntValue();
1940  CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1941  CI->getZExtValue()));
1942  }
1943  } else {
1944  assert(Node->getOperand(i).isUndef());
1945  Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1946  CV.push_back(UndefValue::get(OpNTy));
1947  }
1948  }
1949  Constant *CP = ConstantVector::get(CV);
1950  SDValue CPIdx =
1951  DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1952  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1953  return DAG.getLoad(
1954  VT, dl, DAG.getEntryNode(), CPIdx,
1955  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1956  Alignment);
1957  }
1958 
1959  SmallSet<SDValue, 16> DefinedValues;
1960  for (unsigned i = 0; i < NumElems; ++i) {
1961  if (Node->getOperand(i).isUndef())
1962  continue;
1963  DefinedValues.insert(Node->getOperand(i));
1964  }
1965 
1966  if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1967  if (!MoreThanTwoValues) {
1968  SmallVector<int, 8> ShuffleVec(NumElems, -1);
1969  for (unsigned i = 0; i < NumElems; ++i) {
1970  SDValue V = Node->getOperand(i);
1971  if (V.isUndef())
1972  continue;
1973  ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1974  }
1975  if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1976  // Get the splatted value into the low element of a vector register.
1977  SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1978  SDValue Vec2;
1979  if (Value2.getNode())
1980  Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1981  else
1982  Vec2 = DAG.getUNDEF(VT);
1983 
1984  // Return shuffle(LowValVec, undef, <0,0,0,0>)
1985  return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1986  }
1987  } else {
1988  SDValue Res;
1989  if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
1990  return Res;
1991  }
1992  }
1993 
1994  // Otherwise, we can't handle this case efficiently.
1995  return ExpandVectorBuildThroughStack(Node);
1996 }
1997 
1998 // Expand a node into a call to a libcall. If the result value
1999 // does not fit into a register, return the lo part and set the hi part to the
2000 // by-reg argument. If it does fit into a single register, return the result
2001 // and leave the Hi part unset.
2002 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2003  bool isSigned) {
2005  TargetLowering::ArgListEntry Entry;
2006  for (const SDValue &Op : Node->op_values()) {
2007  EVT ArgVT = Op.getValueType();
2008  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2009  Entry.Node = Op;
2010  Entry.Ty = ArgTy;
2011  Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2012  Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2013  Args.push_back(Entry);
2014  }
2015  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2016  TLI.getPointerTy(DAG.getDataLayout()));
2017 
2018  EVT RetVT = Node->getValueType(0);
2019  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2020 
2021  // By default, the input chain to this libcall is the entry node of the
2022  // function. If the libcall is going to be emitted as a tail call then
2023  // TLI.isUsedByReturnOnly will change it to the right chain if the return
2024  // node which is being folded has a non-entry input chain.
2025  SDValue InChain = DAG.getEntryNode();
2026 
2027  // isTailCall may be true since the callee does not reference caller stack
2028  // frame. Check if it's in the right position and that the return types match.
2029  SDValue TCChain = InChain;
2030  const Function &F = DAG.getMachineFunction().getFunction();
2031  bool isTailCall =
2032  TLI.isInTailCallPosition(DAG, Node, TCChain) &&
2033  (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2034  if (isTailCall)
2035  InChain = TCChain;
2036 
2038  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2039  CLI.setDebugLoc(SDLoc(Node))
2040  .setChain(InChain)
2041  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2042  std::move(Args))
2043  .setTailCall(isTailCall)
2044  .setSExtResult(signExtend)
2045  .setZExtResult(!signExtend)
2047 
2048  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2049 
2050  if (!CallInfo.second.getNode()) {
2051  LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump(&DAG));
2052  // It's a tailcall, return the chain (which is the DAG root).
2053  return DAG.getRoot();
2054  }
2055 
2056  LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump(&DAG));
2057  return CallInfo.first;
2058 }
2059 
2060 // Expand a node into a call to a libcall. Similar to
2061 // ExpandLibCall except that the first operand is the in-chain.
2062 std::pair<SDValue, SDValue>
2063 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2064  SDNode *Node,
2065  bool isSigned) {
2066  SDValue InChain = Node->getOperand(0);
2067 
2069  TargetLowering::ArgListEntry Entry;
2070  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2071  EVT ArgVT = Node->getOperand(i).getValueType();
2072  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2073  Entry.Node = Node->getOperand(i);
2074  Entry.Ty = ArgTy;
2075  Entry.IsSExt = isSigned;
2076  Entry.IsZExt = !isSigned;
2077  Args.push_back(Entry);
2078  }
2079  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2080  TLI.getPointerTy(DAG.getDataLayout()));
2081 
2082  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2083 
2085  CLI.setDebugLoc(SDLoc(Node))
2086  .setChain(InChain)
2087  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2088  std::move(Args))
2089  .setSExtResult(isSigned)
2090  .setZExtResult(!isSigned);
2091 
2092  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2093 
2094  return CallInfo;
2095 }
2096 
2097 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2098  RTLIB::Libcall Call_F32,
2099  RTLIB::Libcall Call_F64,
2100  RTLIB::Libcall Call_F80,
2101  RTLIB::Libcall Call_F128,
2102  RTLIB::Libcall Call_PPCF128) {
2103  if (Node->isStrictFPOpcode())
2104  Node = DAG.mutateStrictFPToFP(Node);
2105 
2106  RTLIB::Libcall LC;
2107  switch (Node->getSimpleValueType(0).SimpleTy) {
2108  default: llvm_unreachable("Unexpected request for libcall!");
2109  case MVT::f32: LC = Call_F32; break;
2110  case MVT::f64: LC = Call_F64; break;
2111  case MVT::f80: LC = Call_F80; break;
2112  case MVT::f128: LC = Call_F128; break;
2113  case MVT::ppcf128: LC = Call_PPCF128; break;
2114  }
2115  return ExpandLibCall(LC, Node, false);
2116 }
2117 
2118 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2119  RTLIB::Libcall Call_I8,
2120  RTLIB::Libcall Call_I16,
2121  RTLIB::Libcall Call_I32,
2122  RTLIB::Libcall Call_I64,
2123  RTLIB::Libcall Call_I128) {
2124  RTLIB::Libcall LC;
2125  switch (Node->getSimpleValueType(0).SimpleTy) {
2126  default: llvm_unreachable("Unexpected request for libcall!");
2127  case MVT::i8: LC = Call_I8; break;
2128  case MVT::i16: LC = Call_I16; break;
2129  case MVT::i32: LC = Call_I32; break;
2130  case MVT::i64: LC = Call_I64; break;
2131  case MVT::i128: LC = Call_I128; break;
2132  }
2133  return ExpandLibCall(LC, Node, isSigned);
2134 }
2135 
2136 /// Expand the node to a libcall based on first argument type (for instance
2137 /// lround and its variant).
2138 SDValue SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
2139  RTLIB::Libcall Call_F32,
2140  RTLIB::Libcall Call_F64,
2141  RTLIB::Libcall Call_F80,
2142  RTLIB::Libcall Call_F128,
2143  RTLIB::Libcall Call_PPCF128) {
2144  RTLIB::Libcall LC;
2145  switch (Node->getOperand(0).getValueType().getSimpleVT().SimpleTy) {
2146  default: llvm_unreachable("Unexpected request for libcall!");
2147  case MVT::f32: LC = Call_F32; break;
2148  case MVT::f64: LC = Call_F64; break;
2149  case MVT::f80: LC = Call_F80; break;
2150  case MVT::f128: LC = Call_F128; break;
2151  case MVT::ppcf128: LC = Call_PPCF128; break;
2152  }
2153 
2154  return ExpandLibCall(LC, Node, false);
2155 }
2156 
2157 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2158 void
2159 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2160  SmallVectorImpl<SDValue> &Results) {
2161  unsigned Opcode = Node->getOpcode();
2162  bool isSigned = Opcode == ISD::SDIVREM;
2163 
2164  RTLIB::Libcall LC;
2165  switch (Node->getSimpleValueType(0).SimpleTy) {
2166  default: llvm_unreachable("Unexpected request for libcall!");
2167  case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2168  case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2169  case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2170  case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2171  case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2172  }
2173 
2174  // The input chain to this libcall is the entry node of the function.
2175  // Legalizing the call will automatically add the previous call to the
2176  // dependence.
2177  SDValue InChain = DAG.getEntryNode();
2178 
2179  EVT RetVT = Node->getValueType(0);
2180  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2181 
2183  TargetLowering::ArgListEntry Entry;
2184  for (const SDValue &Op : Node->op_values()) {
2185  EVT ArgVT = Op.getValueType();
2186  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2187  Entry.Node = Op;
2188  Entry.Ty = ArgTy;
2189  Entry.IsSExt = isSigned;
2190  Entry.IsZExt = !isSigned;
2191  Args.push_back(Entry);
2192  }
2193 
2194  // Also pass the return address of the remainder.
2195  SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2196  Entry.Node = FIPtr;
2197  Entry.Ty = RetTy->getPointerTo();
2198  Entry.IsSExt = isSigned;
2199  Entry.IsZExt = !isSigned;
2200  Args.push_back(Entry);
2201 
2202  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2203  TLI.getPointerTy(DAG.getDataLayout()));
2204 
2205  SDLoc dl(Node);
2207  CLI.setDebugLoc(dl)
2208  .setChain(InChain)
2209  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2210  std::move(Args))
2211  .setSExtResult(isSigned)
2212  .setZExtResult(!isSigned);
2213 
2214  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2215 
2216  // Remainder is loaded back from the stack frame.
2217  SDValue Rem =
2218  DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2219  Results.push_back(CallInfo.first);
2220  Results.push_back(Rem);
2221 }
2222 
2223 /// Return true if sincos libcall is available.
2224 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2225  RTLIB::Libcall LC;
2226  switch (Node->getSimpleValueType(0).SimpleTy) {
2227  default: llvm_unreachable("Unexpected request for libcall!");
2228  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2229  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2230  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2231  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2232  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2233  }
2234  return TLI.getLibcallName(LC) != nullptr;
2235 }
2236 
2237 /// Only issue sincos libcall if both sin and cos are needed.
2238 static bool useSinCos(SDNode *Node) {
2239  unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2240  ? ISD::FCOS : ISD::FSIN;
2241 
2242  SDValue Op0 = Node->getOperand(0);
2243  for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2244  UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2245  SDNode *User = *UI;
2246  if (User == Node)
2247  continue;
2248  // The other user might have been turned into sincos already.
2249  if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2250  return true;
2251  }
2252  return false;
2253 }
2254 
2255 /// Issue libcalls to sincos to compute sin / cos pairs.
2256 void
2257 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2258  SmallVectorImpl<SDValue> &Results) {
2259  RTLIB::Libcall LC;
2260  switch (Node->getSimpleValueType(0).SimpleTy) {
2261  default: llvm_unreachable("Unexpected request for libcall!");
2262  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2263  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2264  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2265  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2266  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2267  }
2268 
2269  // The input chain to this libcall is the entry node of the function.
2270  // Legalizing the call will automatically add the previous call to the
2271  // dependence.
2272  SDValue InChain = DAG.getEntryNode();
2273 
2274  EVT RetVT = Node->getValueType(0);
2275  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2276 
2278  TargetLowering::ArgListEntry Entry;
2279 
2280  // Pass the argument.
2281  Entry.Node = Node->getOperand(0);
2282  Entry.Ty = RetTy;
2283  Entry.IsSExt = false;
2284  Entry.IsZExt = false;
2285  Args.push_back(Entry);
2286 
2287  // Pass the return address of sin.
2288  SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2289  Entry.Node = SinPtr;
2290  Entry.Ty = RetTy->getPointerTo();
2291  Entry.IsSExt = false;
2292  Entry.IsZExt = false;
2293  Args.push_back(Entry);
2294 
2295  // Also pass the return address of the cos.
2296  SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2297  Entry.Node = CosPtr;
2298  Entry.Ty = RetTy->getPointerTo();
2299  Entry.IsSExt = false;
2300  Entry.IsZExt = false;
2301  Args.push_back(Entry);
2302 
2303  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2304  TLI.getPointerTy(DAG.getDataLayout()));
2305 
2306  SDLoc dl(Node);
2308  CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2309  TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee,
2310  std::move(Args));
2311 
2312  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2313 
2314  Results.push_back(
2315  DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2316  Results.push_back(
2317  DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2318 }
2319 
2320 /// This function is responsible for legalizing a
2321 /// INT_TO_FP operation of the specified operand when the target requests that
2322 /// we expand it. At this point, we know that the result and operand types are
2323 /// legal for the target.
2324 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
2325  EVT DestVT,
2326  const SDLoc &dl) {
2327  EVT SrcVT = Op0.getValueType();
2328 
2329  // TODO: Should any fast-math-flags be set for the created nodes?
2330  LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2331  if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2332  LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2333  "expansion\n");
2334 
2335  // Get the stack frame index of a 8 byte buffer.
2336  SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2337 
2338  // word offset constant for Hi/Lo address computation
2339  SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2340  StackSlot.getValueType());
2341  // set up Hi and Lo (into buffer) address based on endian
2342  SDValue Hi = StackSlot;
2343  SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2344  StackSlot, WordOff);
2345  if (DAG.getDataLayout().isLittleEndian())
2346  std::swap(Hi, Lo);
2347 
2348  // if signed map to unsigned space
2349  SDValue Op0Mapped;
2350  if (isSigned) {
2351  // constant used to invert sign bit (signed to unsigned mapping)
2352  SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2353  Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2354  } else {
2355  Op0Mapped = Op0;
2356  }
2357  // store the lo of the constructed double - based on integer input
2358  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo,
2359  MachinePointerInfo());
2360  // initial hi portion of constructed double
2361  SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2362  // store the hi of the constructed double - biased exponent
2363  SDValue Store2 =
2364  DAG.getStore(Store1, dl, InitialHi, Hi, MachinePointerInfo());
2365  // load the constructed double
2366  SDValue Load =
2367  DAG.getLoad(MVT::f64, dl, Store2, StackSlot, MachinePointerInfo());
2368  // FP constant to bias correct the final result
2369  SDValue Bias = DAG.getConstantFP(isSigned ?
2370  BitsToDouble(0x4330000080000000ULL) :
2371  BitsToDouble(0x4330000000000000ULL),
2372  dl, MVT::f64);
2373  // subtract the bias
2374  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2375  // final result
2376  SDValue Result = DAG.getFPExtendOrRound(Sub, dl, DestVT);
2377  return Result;
2378  }
2379  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2380  // Code below here assumes !isSigned without checking again.
2381 
2382  SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2383 
2384  SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
2385  DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2386  SDValue Zero = DAG.getIntPtrConstant(0, dl),
2387  Four = DAG.getIntPtrConstant(4, dl);
2388  SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2389  SignSet, Four, Zero);
2390 
2391  // If the sign bit of the integer is set, the large number will be treated
2392  // as a negative number. To counteract this, the dynamic code adds an
2393  // offset depending on the data type.
2394  uint64_t FF;
2395  switch (SrcVT.getSimpleVT().SimpleTy) {
2396  default: llvm_unreachable("Unsupported integer type!");
2397  case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2398  case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2399  case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2400  case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2401  }
2402  if (DAG.getDataLayout().isLittleEndian())
2403  FF <<= 32;
2404  Constant *FudgeFactor = ConstantInt::get(
2405  Type::getInt64Ty(*DAG.getContext()), FF);
2406 
2407  SDValue CPIdx =
2408  DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2409  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2410  CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2411  Alignment = std::min(Alignment, 4u);
2412  SDValue FudgeInReg;
2413  if (DestVT == MVT::f32)
2414  FudgeInReg = DAG.getLoad(
2415  MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2416  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2417  Alignment);
2418  else {
2419  SDValue Load = DAG.getExtLoad(
2420  ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2421  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2422  Alignment);
2423  HandleSDNode Handle(Load);
2424  LegalizeOp(Load.getNode());
2425  FudgeInReg = Handle.getValue();
2426  }
2427 
2428  return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2429 }
2430 
2431 /// This function is responsible for legalizing a
2432 /// *INT_TO_FP operation of the specified operand when the target requests that
2433 /// we promote it. At this point, we know that the result and operand types are
2434 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2435 /// operation that takes a larger input.
2436 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
2437  bool isSigned,
2438  const SDLoc &dl) {
2439  // First step, figure out the appropriate *INT_TO_FP operation to use.
2440  EVT NewInTy = LegalOp.getValueType();
2441 
2442  unsigned OpToUse = 0;
2443 
2444  // Scan for the appropriate larger type to use.
2445  while (true) {
2446  NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2447  assert(NewInTy.isInteger() && "Ran out of possibilities!");
2448 
2449  // If the target supports SINT_TO_FP of this type, use it.
2450  if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2451  OpToUse = ISD::SINT_TO_FP;
2452  break;
2453  }
2454  if (isSigned) continue;
2455 
2456  // If the target supports UINT_TO_FP of this type, use it.
2457  if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2458  OpToUse = ISD::UINT_TO_FP;
2459  break;
2460  }
2461 
2462  // Otherwise, try a larger type.
2463  }
2464 
2465  // Okay, we found the operation and type to use. Zero extend our input to the
2466  // desired type then run the operation on it.
2467  return DAG.getNode(OpToUse, dl, DestVT,
2468  DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2469  dl, NewInTy, LegalOp));
2470 }
2471 
2472 /// This function is responsible for legalizing a
2473 /// FP_TO_*INT operation of the specified operand when the target requests that
2474 /// we promote it. At this point, we know that the result and operand types are
2475 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2476 /// operation that returns a larger result.
2477 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
2478  bool isSigned,
2479  const SDLoc &dl) {
2480  // First step, figure out the appropriate FP_TO*INT operation to use.
2481  EVT NewOutTy = DestVT;
2482 
2483  unsigned OpToUse = 0;
2484 
2485  // Scan for the appropriate larger type to use.
2486  while (true) {
2487  NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2488  assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2489 
2490  // A larger signed type can hold all unsigned values of the requested type,
2491  // so using FP_TO_SINT is valid
2492  if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2493  OpToUse = ISD::FP_TO_SINT;
2494  break;
2495  }
2496 
2497  // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2498  if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2499  OpToUse = ISD::FP_TO_UINT;
2500  break;
2501  }
2502 
2503  // Otherwise, try a larger type.
2504  }
2505 
2506  // Okay, we found the operation and type to use.
2507  SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2508 
2509  // Truncate the result of the extended FP_TO_*INT operation to the desired
2510  // size.
2511  return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2512 }
2513 
2514 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2515 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
2516  EVT VT = Op.getValueType();
2517  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2518  unsigned Sz = VT.getScalarSizeInBits();
2519 
2520  SDValue Tmp, Tmp2, Tmp3;
2521 
2522  // If we can, perform BSWAP first and then the mask+swap the i4, then i2
2523  // and finally the i1 pairs.
2524  // TODO: We can easily support i4/i2 legal types if any target ever does.
2525  if (Sz >= 8 && isPowerOf2_32(Sz)) {
2526  // Create the masks - repeating the pattern every byte.
2527  APInt MaskHi4 = APInt::getSplat(Sz, APInt(8, 0xF0));
2528  APInt MaskHi2 = APInt::getSplat(Sz, APInt(8, 0xCC));
2529  APInt MaskHi1 = APInt::getSplat(Sz, APInt(8, 0xAA));
2530  APInt MaskLo4 = APInt::getSplat(Sz, APInt(8, 0x0F));
2531  APInt MaskLo2 = APInt::getSplat(Sz, APInt(8, 0x33));
2532  APInt MaskLo1 = APInt::getSplat(Sz, APInt(8, 0x55));
2533 
2534  // BSWAP if the type is wider than a single byte.
2535  Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2536 
2537  // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4)
2538  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2539  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2540  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT));
2541  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT));
2542  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2543 
2544  // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2)
2545  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2546  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2547  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT));
2548  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT));
2549  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2550 
2551  // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
2552  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2553  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2554  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT));
2555  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT));
2556  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2557  return Tmp;
2558  }
2559 
2560  Tmp = DAG.getConstant(0, dl, VT);
2561  for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2562  if (I < J)
2563  Tmp2 =
2564  DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2565  else
2566  Tmp2 =
2567  DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2568 
2569  APInt Shift(Sz, 1);
2570  Shift <<= J;
2571  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2572  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2573  }
2574 
2575  return Tmp;
2576 }
2577 
2578 /// Open code the operations for BSWAP of the specified operation.
2579 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
2580  EVT VT = Op.getValueType();
2581  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2582  SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2583  switch (VT.getSimpleVT().getScalarType().SimpleTy) {
2584  default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2585  case MVT::i16:
2586  // Use a rotate by 8. This can be further expanded if necessary.
2587  return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2588  case MVT::i32:
2589  Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2590  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2591  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2592  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2593  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2594  DAG.getConstant(0xFF0000, dl, VT));
2595  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2596  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2597  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2598  return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2599  case MVT::i64:
2600  Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2601  Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2602  Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2603  Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2604  Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2605  Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2606  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2607  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2608  Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2609  DAG.getConstant(255ULL<<48, dl, VT));
2610  Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2611  DAG.getConstant(255ULL<<40, dl, VT));
2612  Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2613  DAG.getConstant(255ULL<<32, dl, VT));
2614  Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2615  DAG.getConstant(255ULL<<24, dl, VT));
2616  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2617  DAG.getConstant(255ULL<<16, dl, VT));
2618  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2619  DAG.getConstant(255ULL<<8 , dl, VT));
2620  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2621  Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2622  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2623  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2624  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2625  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2626  return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2627  }
2628 }
2629 
2630 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2631  LLVM_DEBUG(dbgs() << "Trying to expand node\n");
2633  SDLoc dl(Node);
2634  SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2635  bool NeedInvert;
2636  switch (Node->getOpcode()) {
2637  case ISD::ABS:
2638  if (TLI.expandABS(Node, Tmp1, DAG))
2639  Results.push_back(Tmp1);
2640  break;
2641  case ISD::CTPOP:
2642  if (TLI.expandCTPOP(Node, Tmp1, DAG))
2643  Results.push_back(Tmp1);
2644  break;
2645  case ISD::CTLZ:
2646  case ISD::CTLZ_ZERO_UNDEF:
2647  if (TLI.expandCTLZ(Node, Tmp1, DAG))
2648  Results.push_back(Tmp1);
2649  break;
2650  case ISD::CTTZ:
2651  case ISD::CTTZ_ZERO_UNDEF:
2652  if (TLI.expandCTTZ(Node, Tmp1, DAG))
2653  Results.push_back(Tmp1);
2654  break;
2655  case ISD::BITREVERSE:
2656  Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
2657  break;
2658  case ISD::BSWAP:
2659  Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2660  break;
2661  case ISD::FRAMEADDR:
2662  case ISD::RETURNADDR:
2664  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2665  break;
2666  case ISD::EH_DWARF_CFA: {
2667  SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2668  TLI.getPointerTy(DAG.getDataLayout()));
2669  SDValue Offset = DAG.getNode(ISD::ADD, dl,
2670  CfaArg.getValueType(),
2671  DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2672  CfaArg.getValueType()),
2673  CfaArg);
2674  SDValue FA = DAG.getNode(
2675  ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2676  DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2677  Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2678  FA, Offset));
2679  break;
2680  }
2681  case ISD::FLT_ROUNDS_:
2682  Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2683  break;
2684  case ISD::EH_RETURN:
2685  case ISD::EH_LABEL:
2686  case ISD::PREFETCH:
2687  case ISD::VAEND:
2688  case ISD::EH_SJLJ_LONGJMP:
2689  // If the target didn't expand these, there's nothing to do, so just
2690  // preserve the chain and be done.
2691  Results.push_back(Node->getOperand(0));
2692  break;
2693  case ISD::READCYCLECOUNTER:
2694  // If the target didn't expand this, just return 'zero' and preserve the
2695  // chain.
2696  Results.append(Node->getNumValues() - 1,
2697  DAG.getConstant(0, dl, Node->getValueType(0)));
2698  Results.push_back(Node->getOperand(0));
2699  break;
2700  case ISD::EH_SJLJ_SETJMP:
2701  // If the target didn't expand this, just return 'zero' and preserve the
2702  // chain.
2703  Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2704  Results.push_back(Node->getOperand(0));
2705  break;
2706  case ISD::ATOMIC_LOAD: {
2707  // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2708  SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2709  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2710  SDValue Swap = DAG.getAtomicCmpSwap(
2711  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2712  Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2713  cast<AtomicSDNode>(Node)->getMemOperand());
2714  Results.push_back(Swap.getValue(0));
2715  Results.push_back(Swap.getValue(1));
2716  break;
2717  }
2718  case ISD::ATOMIC_STORE: {
2719  // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2720  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2721  cast<AtomicSDNode>(Node)->getMemoryVT(),
2722  Node->getOperand(0),
2723  Node->getOperand(1), Node->getOperand(2),
2724  cast<AtomicSDNode>(Node)->getMemOperand());
2725  Results.push_back(Swap.getValue(1));
2726  break;
2727  }
2729  // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2730  // splits out the success value as a comparison. Expanding the resulting
2731  // ATOMIC_CMP_SWAP will produce a libcall.
2732  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2733  SDValue Res = DAG.getAtomicCmpSwap(
2734  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2735  Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2736  Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2737 
2738  SDValue ExtRes = Res;
2739  SDValue LHS = Res;
2740  SDValue RHS = Node->getOperand(1);
2741 
2742  EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2743  EVT OuterType = Node->getValueType(0);
2744  switch (TLI.getExtendForAtomicOps()) {
2745  case ISD::SIGN_EXTEND:
2746  LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2747  DAG.getValueType(AtomicType));
2748  RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2749  Node->getOperand(2), DAG.getValueType(AtomicType));
2750  ExtRes = LHS;
2751  break;
2752  case ISD::ZERO_EXTEND:
2753  LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2754  DAG.getValueType(AtomicType));
2755  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2756  ExtRes = LHS;
2757  break;
2758  case ISD::ANY_EXTEND:
2759  LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2760  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2761  break;
2762  default:
2763  llvm_unreachable("Invalid atomic op extension");
2764  }
2765 
2766  SDValue Success =
2767  DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2768 
2769  Results.push_back(ExtRes.getValue(0));
2770  Results.push_back(Success);
2771  Results.push_back(Res.getValue(1));
2772  break;
2773  }
2775  ExpandDYNAMIC_STACKALLOC(Node, Results);
2776  break;
2777  case ISD::MERGE_VALUES:
2778  for (unsigned i = 0; i < Node->getNumValues(); i++)
2779  Results.push_back(Node->getOperand(i));
2780  break;
2781  case ISD::UNDEF: {
2782  EVT VT = Node->getValueType(0);
2783  if (VT.isInteger())
2784  Results.push_back(DAG.getConstant(0, dl, VT));
2785  else {
2786  assert(VT.isFloatingPoint() && "Unknown value type!");
2787  Results.push_back(DAG.getConstantFP(0, dl, VT));
2788  }
2789  break;
2790  }
2791  case ISD::STRICT_FP_ROUND:
2792  // This expansion does not honor the "strict" properties anyway,
2793  // so prefer falling back to the non-strict operation if legal.
2794  if (TLI.getStrictFPOperationAction(Node->getOpcode(),
2795  Node->getValueType(0))
2797  break;
2798  Tmp1 = EmitStackConvert(Node->getOperand(1),
2799  Node->getValueType(0),
2800  Node->getValueType(0), dl, Node->getOperand(0));
2801  ReplaceNode(Node, Tmp1.getNode());
2802  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_ROUND node\n");
2803  return true;
2804  case ISD::FP_ROUND:
2805  case ISD::BITCAST:
2806  Tmp1 = EmitStackConvert(Node->getOperand(0),
2807  Node->getValueType(0),
2808  Node->getValueType(0), dl);
2809  Results.push_back(Tmp1);
2810  break;
2811  case ISD::STRICT_FP_EXTEND:
2812  // This expansion does not honor the "strict" properties anyway,
2813  // so prefer falling back to the non-strict operation if legal.
2814  if (TLI.getStrictFPOperationAction(Node->getOpcode(),
2815  Node->getValueType(0))
2817  break;
2818  Tmp1 = EmitStackConvert(Node->getOperand(1),
2819  Node->getOperand(1).getValueType(),
2820  Node->getValueType(0), dl, Node->getOperand(0));
2821  ReplaceNode(Node, Tmp1.getNode());
2822  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_EXTEND node\n");
2823  return true;
2824  case ISD::FP_EXTEND:
2825  Tmp1 = EmitStackConvert(Node->getOperand(0),
2826  Node->getOperand(0).getValueType(),
2827  Node->getValueType(0), dl);
2828  Results.push_back(Tmp1);
2829  break;
2830  case ISD::SIGN_EXTEND_INREG: {
2831  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2832  EVT VT = Node->getValueType(0);
2833 
2834  // An in-register sign-extend of a boolean is a negation:
2835  // 'true' (1) sign-extended is -1.
2836  // 'false' (0) sign-extended is 0.
2837  // However, we must mask the high bits of the source operand because the
2838  // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2839 
2840  // TODO: Do this for vectors too?
2841  if (ExtraVT.getSizeInBits() == 1) {
2842  SDValue One = DAG.getConstant(1, dl, VT);
2843  SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2844  SDValue Zero = DAG.getConstant(0, dl, VT);
2845  SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2846  Results.push_back(Neg);
2847  break;
2848  }
2849 
2850  // NOTE: we could fall back on load/store here too for targets without
2851  // SRA. However, it is doubtful that any exist.
2852  EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2853  unsigned BitsDiff = VT.getScalarSizeInBits() -
2854  ExtraVT.getScalarSizeInBits();
2855  SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2856  Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2857  Node->getOperand(0), ShiftCst);
2858  Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2859  Results.push_back(Tmp1);
2860  break;
2861  }
2862  case ISD::UINT_TO_FP:
2863  if (TLI.expandUINT_TO_FP(Node, Tmp1, DAG)) {
2864  Results.push_back(Tmp1);
2865  break;
2866  }
2868  case ISD::SINT_TO_FP:
2869  Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2870  Node->getOperand(0), Node->getValueType(0), dl);
2871  Results.push_back(Tmp1);
2872  break;
2873  case ISD::FP_TO_SINT:
2874  if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
2875  Results.push_back(Tmp1);
2876  break;
2878  if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG)) {
2879  ReplaceNode(Node, Tmp1.getNode());
2880  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_SINT node\n");
2881  return true;
2882  }
2883  break;
2884  case ISD::FP_TO_UINT:
2885  if (TLI.expandFP_TO_UINT(Node, Tmp1, Tmp2, DAG))
2886  Results.push_back(Tmp1);
2887  break;
2889  if (TLI.expandFP_TO_UINT(Node, Tmp1, Tmp2, DAG)) {
2890  // Relink the chain.
2891  DAG.ReplaceAllUsesOfValueWith(SDValue(Node,1), Tmp2);
2892  // Replace the new UINT result.
2893  ReplaceNodeWithValue(SDValue(Node, 0), Tmp1);
2894  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_TO_UINT node\n");
2895  return true;
2896  }
2897  break;
2898  case ISD::LROUND:
2899  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LROUND_F32,
2900  RTLIB::LROUND_F64, RTLIB::LROUND_F80,
2901  RTLIB::LROUND_F128,
2902  RTLIB::LROUND_PPCF128));
2903  break;
2904  case ISD::LLROUND:
2905  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LLROUND_F32,
2906  RTLIB::LLROUND_F64, RTLIB::LLROUND_F80,
2907  RTLIB::LLROUND_F128,
2908  RTLIB::LLROUND_PPCF128));
2909  break;
2910  case ISD::LRINT:
2911  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LRINT_F32,
2912  RTLIB::LRINT_F64, RTLIB::LRINT_F80,
2913  RTLIB::LRINT_F128,
2914  RTLIB::LRINT_PPCF128));
2915  break;
2916  case ISD::LLRINT:
2917  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LLRINT_F32,
2918  RTLIB::LLRINT_F64, RTLIB::LLRINT_F80,
2919  RTLIB::LLRINT_F128,
2920  RTLIB::LLRINT_PPCF128));
2921  break;
2922  case ISD::VAARG:
2923  Results.push_back(DAG.expandVAArg(Node));
2924  Results.push_back(Results[0].getValue(1));
2925  break;
2926  case ISD::VACOPY:
2927  Results.push_back(DAG.expandVACopy(Node));
2928  break;
2930  if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2931  // This must be an access of the only element. Return it.
2932  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2933  Node->getOperand(0));
2934  else
2935  Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2936  Results.push_back(Tmp1);
2937  break;
2939  Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2940  break;
2941  case ISD::INSERT_SUBVECTOR:
2942  Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2943  break;
2944  case ISD::CONCAT_VECTORS:
2945  Results.push_back(ExpandVectorBuildThroughStack(Node));
2946  break;
2947  case ISD::SCALAR_TO_VECTOR:
2948  Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2949  break;
2951  Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2952  Node->getOperand(1),
2953  Node->getOperand(2), dl));
2954  break;
2955  case ISD::VECTOR_SHUFFLE: {
2956  SmallVector<int, 32> NewMask;
2957  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2958 
2959  EVT VT = Node->getValueType(0);
2960  EVT EltVT = VT.getVectorElementType();
2961  SDValue Op0 = Node->getOperand(0);
2962  SDValue Op1 = Node->getOperand(1);
2963  if (!TLI.isTypeLegal(EltVT)) {
2964  EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2965 
2966  // BUILD_VECTOR operands are allowed to be wider than the element type.
2967  // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
2968  // it.
2969  if (NewEltVT.bitsLT(EltVT)) {
2970  // Convert shuffle node.
2971  // If original node was v4i64 and the new EltVT is i32,
2972  // cast operands to v8i32 and re-build the mask.
2973 
2974  // Calculate new VT, the size of the new VT should be equal to original.
2975  EVT NewVT =
2976  EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2977  VT.getSizeInBits() / NewEltVT.getSizeInBits());
2978  assert(NewVT.bitsEq(VT));
2979 
2980  // cast operands to new VT
2981  Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2982  Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2983 
2984  // Convert the shuffle mask
2985  unsigned int factor =
2987 
2988  // EltVT gets smaller
2989  assert(factor > 0);
2990 
2991  for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2992  if (Mask[i] < 0) {
2993  for (unsigned fi = 0; fi < factor; ++fi)
2994  NewMask.push_back(Mask[i]);
2995  }
2996  else {
2997  for (unsigned fi = 0; fi < factor; ++fi)
2998  NewMask.push_back(Mask[i]*factor+fi);
2999  }
3000  }
3001  Mask = NewMask;
3002  VT = NewVT;
3003  }
3004  EltVT = NewEltVT;
3005  }
3006  unsigned NumElems = VT.getVectorNumElements();
3008  for (unsigned i = 0; i != NumElems; ++i) {
3009  if (Mask[i] < 0) {
3010  Ops.push_back(DAG.getUNDEF(EltVT));
3011  continue;
3012  }
3013  unsigned Idx = Mask[i];
3014  if (Idx < NumElems)
3015  Ops.push_back(DAG.getNode(
3016  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3017  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3018  else
3019  Ops.push_back(DAG.getNode(
3020  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3021  DAG.getConstant(Idx - NumElems, dl,
3022  TLI.getVectorIdxTy(DAG.getDataLayout()))));
3023  }
3024 
3025  Tmp1 = DAG.getBuildVector(VT, dl, Ops);
3026  // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3027  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3028  Results.push_back(Tmp1);
3029  break;
3030  }
3031  case ISD::EXTRACT_ELEMENT: {
3032  EVT OpTy = Node->getOperand(0).getValueType();
3033  if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3034  // 1 -> Hi
3035  Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3036  DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3037  TLI.getShiftAmountTy(
3038  Node->getOperand(0).getValueType(),
3039  DAG.getDataLayout())));
3040  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3041  } else {
3042  // 0 -> Lo
3043  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3044  Node->getOperand(0));
3045  }
3046  Results.push_back(Tmp1);
3047  break;
3048  }
3049  case ISD::STACKSAVE:
3050  // Expand to CopyFromReg if the target set
3051  // StackPointerRegisterToSaveRestore.
3052  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3053  Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3054  Node->getValueType(0)));
3055  Results.push_back(Results[0].getValue(1));
3056  } else {
3057  Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3058  Results.push_back(Node->getOperand(0));
3059  }
3060  break;
3061  case ISD::STACKRESTORE:
3062  // Expand to CopyToReg if the target set
3063  // StackPointerRegisterToSaveRestore.
3064  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3065  Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3066  Node->getOperand(1)));
3067  } else {
3068  Results.push_back(Node->getOperand(0));
3069  }
3070  break;
3072  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3073  Results.push_back(Results[0].getValue(0));
3074  break;
3075  case ISD::FCOPYSIGN:
3076  Results.push_back(ExpandFCOPYSIGN(Node));
3077  break;
3078  case ISD::FNEG:
3079  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3080  Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3081  // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3082  Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3083  Node->getOperand(0));
3084  Results.push_back(Tmp1);
3085  break;
3086  case ISD::FABS:
3087  Results.push_back(ExpandFABS(Node));
3088  break;
3089  case ISD::SMIN:
3090  case ISD::SMAX:
3091  case ISD::UMIN:
3092  case ISD::UMAX: {
3093  // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3094  ISD::CondCode Pred;
3095  switch (Node->getOpcode()) {
3096  default: llvm_unreachable("How did we get here?");
3097  case ISD::SMAX: Pred = ISD::SETGT; break;
3098  case ISD::SMIN: Pred = ISD::SETLT; break;
3099  case ISD::UMAX: Pred = ISD::SETUGT; break;
3100  case ISD::UMIN: Pred = ISD::SETULT; break;
3101  }
3102  Tmp1 = Node->getOperand(0);
3103  Tmp2 = Node->getOperand(1);
3104  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3105  Results.push_back(Tmp1);
3106  break;
3107  }
3108  case ISD::FMINNUM:
3109  case ISD::FMAXNUM: {
3110  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Node, DAG))
3111  Results.push_back(Expanded);
3112  break;
3113  }
3114  case ISD::FSIN:
3115  case ISD::FCOS: {
3116  EVT VT = Node->getValueType(0);
3117  // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3118  // fcos which share the same operand and both are used.
3119  if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3120  isSinCosLibcallAvailable(Node, TLI))
3121  && useSinCos(Node)) {
3122  SDVTList VTs = DAG.getVTList(VT, VT);
3123  Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3124  if (Node->getOpcode() == ISD::FCOS)
3125  Tmp1 = Tmp1.getValue(1);
3126  Results.push_back(Tmp1);
3127  }
3128  break;
3129  }
3130  case ISD::FMAD:
3131  llvm_unreachable("Illegal fmad should never be formed");
3132 
3133  case ISD::FP16_TO_FP:
3134  if (Node->getValueType(0) != MVT::f32) {
3135  // We can extend to types bigger than f32 in two steps without changing
3136  // the result. Since "f16 -> f32" is much more commonly available, give
3137  // CodeGen the option of emitting that before resorting to a libcall.
3138  SDValue Res =
3139  DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3140  Results.push_back(
3141  DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3142  }
3143  break;
3144  case ISD::FP_TO_FP16:
3145  LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3146  if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3147  SDValue Op = Node->getOperand(0);
3148  MVT SVT = Op.getSimpleValueType();
3149  if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3150  TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3151  // Under fastmath, we can expand this node into a fround followed by
3152  // a float-half conversion.
3153  SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3154  DAG.getIntPtrConstant(0, dl));
3155  Results.push_back(
3156  DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3157  }
3158  }
3159  break;
3160  case ISD::ConstantFP: {
3161  ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3162  // Check to see if this FP immediate is already legal.
3163  // If this is a legal constant, turn it into a TargetConstantFP node.
3164  if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0),
3165  DAG.getMachineFunction().getFunction().hasOptSize()))
3166  Results.push_back(ExpandConstantFP(CFP, true));
3167  break;
3168  }
3169  case ISD::Constant: {
3170  ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3171  Results.push_back(ExpandConstant(CP));
3172  break;
3173  }
3174  case ISD::FSUB: {
3175  EVT VT = Node->getValueType(0);
3176  if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3177  TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3178  const SDNodeFlags Flags = Node->getFlags();
3179  Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3180  Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3181  Results.push_back(Tmp1);
3182  }
3183  break;
3184  }
3185  case ISD::SUB: {
3186  EVT VT = Node->getValueType(0);
3187  assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3188  TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3189  "Don't know how to expand this subtraction!");
3190  Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3191  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3192  VT));
3193  Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3194  Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3195  break;
3196  }
3197  case ISD::UREM:
3198  case ISD::SREM: {
3199  EVT VT = Node->getValueType(0);
3200  bool isSigned = Node->getOpcode() == ISD::SREM;
3201  unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3202  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3203  Tmp2 = Node->getOperand(0);
3204  Tmp3 = Node->getOperand(1);
3205  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3206  SDVTList VTs = DAG.getVTList(VT, VT);
3207  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3208  Results.push_back(Tmp1);
3209  } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3210  // X % Y -> X-X/Y*Y
3211  Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3212  Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3213  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3214  Results.push_back(Tmp1);
3215  }
3216  break;
3217  }
3218  case ISD::UDIV:
3219  case ISD::SDIV: {
3220  bool isSigned = Node->getOpcode() == ISD::SDIV;
3221  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3222  EVT VT = Node->getValueType(0);
3223  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3224  SDVTList VTs = DAG.getVTList(VT, VT);
3225  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3226  Node->getOperand(1));
3227  Results.push_back(Tmp1);
3228  }
3229  break;
3230  }
3231  case ISD::MULHU:
3232  case ISD::MULHS: {
3233  unsigned ExpandOpcode =
3235  EVT VT = Node->getValueType(0);
3236  SDVTList VTs = DAG.getVTList(VT, VT);
3237 
3238  Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3239  Node->getOperand(1));
3240  Results.push_back(Tmp1.getValue(1));
3241  break;
3242  }
3243  case ISD::UMUL_LOHI:
3244  case ISD::SMUL_LOHI: {
3245  SDValue LHS = Node->getOperand(0);
3246  SDValue RHS = Node->getOperand(1);
3247  MVT VT = LHS.getSimpleValueType();
3248  unsigned MULHOpcode =
3250 
3251  if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3252  Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3253  Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3254  break;
3255  }
3256 
3257  SmallVector<SDValue, 4> Halves;
3258  EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3259  assert(TLI.isTypeLegal(HalfType));
3260  if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3261  HalfType, DAG,
3263  for (unsigned i = 0; i < 2; ++i) {
3264  SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3265  SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3266  SDValue Shift = DAG.getConstant(
3267  HalfType.getScalarSizeInBits(), dl,
3268  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3269  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3270  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3271  }
3272  break;
3273  }
3274  break;
3275  }
3276  case ISD::MUL: {
3277  EVT VT = Node->getValueType(0);
3278  SDVTList VTs = DAG.getVTList(VT, VT);
3279  // See if multiply or divide can be lowered using two-result operations.
3280  // We just need the low half of the multiply; try both the signed
3281  // and unsigned forms. If the target supports both SMUL_LOHI and
3282  // UMUL_LOHI, form a preference by checking which forms of plain
3283  // MULH it supports.
3284  bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3285  bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3286  bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3287  bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3288  unsigned OpToUse = 0;
3289  if (HasSMUL_LOHI && !HasMULHS) {
3290  OpToUse = ISD::SMUL_LOHI;
3291  } else if (HasUMUL_LOHI && !HasMULHU) {
3292  OpToUse = ISD::UMUL_LOHI;
3293  } else if (HasSMUL_LOHI) {
3294  OpToUse = ISD::SMUL_LOHI;
3295  } else if (HasUMUL_LOHI) {
3296  OpToUse = ISD::UMUL_LOHI;
3297  }
3298  if (OpToUse) {
3299  Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3300  Node->getOperand(1)));
3301  break;
3302  }
3303 
3304  SDValue Lo, Hi;
3305  EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3306  if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3307  TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3308  TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3309  TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3310  TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3312  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3313  Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3314  SDValue Shift =
3315  DAG.getConstant(HalfType.getSizeInBits(), dl,
3316  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3317  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3318  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3319  }
3320  break;
3321  }
3322  case ISD::FSHL:
3323  case ISD::FSHR:
3324  if (TLI.expandFunnelShift(Node, Tmp1, DAG))
3325  Results.push_back(Tmp1);
3326  break;
3327  case ISD::ROTL:
3328  case ISD::ROTR:
3329  if (TLI.expandROT(Node, Tmp1, DAG))
3330  Results.push_back(Tmp1);
3331  break;
3332  case ISD::SADDSAT:
3333  case ISD::UADDSAT:
3334  case ISD::SSUBSAT:
3335  case ISD::USUBSAT:
3336  Results.push_back(TLI.expandAddSubSat(Node, DAG));
3337  break;
3338  case ISD::SMULFIX:
3339  case ISD::SMULFIXSAT:
3340  case ISD::UMULFIX:
3341  case ISD::UMULFIXSAT:
3342  Results.push_back(TLI.expandFixedPointMul(Node, DAG));
3343  break;
3344  case ISD::ADDCARRY:
3345  case ISD::SUBCARRY: {
3346  SDValue LHS = Node->getOperand(0);
3347  SDValue RHS = Node->getOperand(1);
3348  SDValue Carry = Node->getOperand(2);
3349 
3350  bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;
3351 
3352  // Initial add of the 2 operands.
3353  unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
3354  EVT VT = LHS.getValueType();
3355  SDValue Sum = DAG.getNode(Op, dl, VT, LHS, RHS);
3356 
3357  // Initial check for overflow.
3358  EVT CarryType = Node->getValueType(1);
3359  EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3360  ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3361  SDValue Overflow = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3362 
3363  // Add of the sum and the carry.
3364  SDValue CarryExt =
3365  DAG.getZeroExtendInReg(DAG.getZExtOrTrunc(Carry, dl, VT), dl, MVT::i1);
3366  SDValue Sum2 = DAG.getNode(Op, dl, VT, Sum, CarryExt);
3367 
3368  // Second check for overflow. If we are adding, we can only overflow if the
3369  // initial sum is all 1s ang the carry is set, resulting in a new sum of 0.
3370  // If we are subtracting, we can only overflow if the initial sum is 0 and
3371  // the carry is set, resulting in a new sum of all 1s.
3372  SDValue Zero = DAG.getConstant(0, dl, VT);
3373  SDValue Overflow2 =
3374  IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ)
3375  : DAG.getSetCC(dl, SetCCType, Sum, Zero, ISD::SETEQ);
3376  Overflow2 = DAG.getNode(ISD::AND, dl, SetCCType, Overflow2,
3377  DAG.getZExtOrTrunc(Carry, dl, SetCCType));
3378 
3379  SDValue ResultCarry =
3380  DAG.getNode(ISD::OR, dl, SetCCType, Overflow, Overflow2);
3381 
3382  Results.push_back(Sum2);
3383  Results.push_back(DAG.getBoolExtOrTrunc(ResultCarry, dl, CarryType, VT));
3384  break;
3385  }
3386  case ISD::SADDO:
3387  case ISD::SSUBO: {
3388  SDValue Result, Overflow;
3389  TLI.expandSADDSUBO(Node, Result, Overflow, DAG);
3390  Results.push_back(Result);
3391  Results.push_back(Overflow);
3392  break;
3393  }
3394  case ISD::UADDO:
3395  case ISD::USUBO: {
3396  SDValue Result, Overflow;
3397  TLI.expandUADDSUBO(Node, Result, Overflow, DAG);
3398  Results.push_back(Result);
3399  Results.push_back(Overflow);
3400  break;
3401  }
3402  case ISD::UMULO:
3403  case ISD::SMULO: {
3404  SDValue Result, Overflow;
3405  if (TLI.expandMULO(Node, Result, Overflow, DAG)) {
3406  Results.push_back(Result);
3407  Results.push_back(Overflow);
3408  }
3409  break;
3410  }
3411  case ISD::BUILD_PAIR: {
3412  EVT PairTy = Node->getValueType(0);
3413  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3414  Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3415  Tmp2 = DAG.getNode(
3416  ISD::SHL, dl, PairTy, Tmp2,
3417  DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3418  TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3419  Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3420  break;
3421  }
3422  case ISD::SELECT:
3423  Tmp1 = Node->getOperand(0);
3424  Tmp2 = Node->getOperand(1);
3425  Tmp3 = Node->getOperand(2);
3426  if (Tmp1.getOpcode() == ISD::SETCC) {
3427  Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3428  Tmp2, Tmp3,
3429  cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3430  } else {
3431  Tmp1 = DAG.getSelectCC(dl, Tmp1,
3432  DAG.getConstant(0, dl, Tmp1.getValueType()),
3433  Tmp2, Tmp3, ISD::SETNE);
3434  }
3435  Tmp1->setFlags(Node->getFlags());
3436  Results.push_back(Tmp1);
3437  break;
3438  case ISD::BR_JT: {
3439  SDValue Chain = Node->getOperand(0);
3440  SDValue Table = Node->getOperand(1);
3441  SDValue Index = Node->getOperand(2);
3442 
3443  const DataLayout &TD = DAG.getDataLayout();
3444  EVT PTy = TLI.getPointerTy(TD);
3445 
3446  unsigned EntrySize =
3447  DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3448 
3449  // For power-of-two jumptable entry sizes convert multiplication to a shift.
3450  // This transformation needs to be done here since otherwise the MIPS
3451  // backend will end up emitting a three instruction multiply sequence
3452  // instead of a single shift and MSP430 will call a runtime function.
3453  if (llvm::isPowerOf2_32(EntrySize))
3454  Index = DAG.getNode(
3455  ISD::SHL, dl, Index.getValueType(), Index,
3456  DAG.getConstant(llvm::Log2_32(EntrySize), dl, Index.getValueType()));
3457  else
3458  Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3459  DAG.getConstant(EntrySize, dl, Index.getValueType()));
3460  SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3461  Index, Table);
3462 
3463  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3464  SDValue LD = DAG.getExtLoad(
3465  ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3466  MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3467  Addr = LD;
3468  if (TLI.isJumpTableRelative()) {
3469  // For PIC, the sequence is:
3470  // BRIND(load(Jumptable + index) + RelocBase)
3471  // RelocBase can be JumpTable, GOT or some sort of global base.
3472  Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3473  TLI.getPICJumpTableRelocBase(Table, DAG));
3474  }
3475 
3476  Tmp1 = TLI.expandIndirectJTBranch(dl, LD.getValue(1), Addr, DAG);
3477  Results.push_back(Tmp1);
3478  break;
3479  }
3480  case ISD::BRCOND:
3481  // Expand brcond's setcc into its constituent parts and create a BR_CC
3482  // Node.
3483  Tmp1 = Node->getOperand(0);
3484  Tmp2 = Node->getOperand(1);
3485  if (Tmp2.getOpcode() == ISD::SETCC) {
3486  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3487  Tmp1, Tmp2.getOperand(2),
3488  Tmp2.getOperand(0), Tmp2.getOperand(1),
3489  Node->getOperand(2));
3490  } else {
3491  // We test only the i1 bit. Skip the AND if UNDEF or another AND.
3492  if (Tmp2.isUndef() ||
3493  (Tmp2.getOpcode() == ISD::AND &&
3494  isa<ConstantSDNode>(Tmp2.getOperand(1)) &&
3495  cast<ConstantSDNode>(Tmp2.getOperand(1))->getZExtValue() == 1))
3496  Tmp3 = Tmp2;
3497  else
3498  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3499  DAG.getConstant(1, dl, Tmp2.getValueType()));
3500  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3501  DAG.getCondCode(ISD::SETNE), Tmp3,
3502  DAG.getConstant(0, dl, Tmp3.getValueType()),
3503  Node->getOperand(2));
3504  }
3505  Results.push_back(Tmp1);
3506  break;
3507  case ISD::SETCC: {
3508  Tmp1 = Node->getOperand(0);
3509  Tmp2 = Node->getOperand(1);
3510  Tmp3 = Node->getOperand(2);
3511  bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3512  Tmp3, NeedInvert, dl);
3513 
3514  if (Legalized) {
3515  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3516  // condition code, create a new SETCC node.
3517  if (Tmp3.getNode())
3518  Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3519  Tmp1, Tmp2, Tmp3, Node->getFlags());
3520 
3521  // If we expanded the SETCC by inverting the condition code, then wrap
3522  // the existing SETCC in a NOT to restore the intended condition.
3523  if (NeedInvert)
3524  Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3525 
3526  Results.push_back(Tmp1);
3527  break;
3528  }
3529 
3530  // Otherwise, SETCC for the given comparison type must be completely
3531  // illegal; expand it into a SELECT_CC.
3532  EVT VT = Node->getValueType(0);
3533  int TrueValue;
3534  switch (TLI.getBooleanContents(Tmp1.getValueType())) {
3537  TrueValue = 1;
3538  break;
3540  TrueValue = -1;
3541  break;
3542  }
3543  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3544  DAG.getConstant(TrueValue, dl, VT),
3545  DAG.getConstant(0, dl, VT),
3546  Tmp3);
3547  Tmp1->setFlags(Node->getFlags());
3548  Results.push_back(Tmp1);
3549  break;
3550  }
3551  case ISD::SELECT_CC: {
3552  Tmp1 = Node->getOperand(0); // LHS
3553  Tmp2 = Node->getOperand(1); // RHS
3554  Tmp3 = Node->getOperand(2); // True
3555  Tmp4 = Node->getOperand(3); // False
3556  EVT VT = Node->getValueType(0);
3557  SDValue CC = Node->getOperand(4);
3558  ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3559 
3560  if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) {
3561  // If the condition code is legal, then we need to expand this
3562  // node using SETCC and SELECT.
3563  EVT CmpVT = Tmp1.getValueType();
3564  assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3565  "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3566  "expanded.");
3567  EVT CCVT = getSetCCResultType(CmpVT);
3568  SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags());
3569  Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3570  break;
3571  }
3572 
3573  // SELECT_CC is legal, so the condition code must not be.
3574  bool Legalized = false;
3575  // Try to legalize by inverting the condition. This is for targets that
3576  // might support an ordered version of a condition, but not the unordered
3577  // version (or vice versa).
3578  ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3579  Tmp1.getValueType().isInteger());
3580  if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
3581  // Use the new condition code and swap true and false
3582  Legalized = true;
3583  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3584  Tmp1->setFlags(Node->getFlags());
3585  } else {
3586  // If The inverse is not legal, then try to swap the arguments using
3587  // the inverse condition code.
3588  ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3589  if (TLI.isCondCodeLegalOrCustom(SwapInvCC, Tmp1.getSimpleValueType())) {
3590  // The swapped inverse condition is legal, so swap true and false,
3591  // lhs and rhs.
3592  Legalized = true;
3593  Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3594  Tmp1->setFlags(Node->getFlags());
3595  }
3596  }
3597 
3598  if (!Legalized) {
3599  Legalized = LegalizeSetCCCondCode(
3600  getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3601  dl);
3602 
3603  assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3604 
3605  // If we expanded the SETCC by inverting the condition code, then swap
3606  // the True/False operands to match.
3607  if (NeedInvert)
3608  std::swap(Tmp3, Tmp4);
3609 
3610  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3611  // condition code, create a new SELECT_CC node.
3612  if (CC.getNode()) {
3613  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3614  Tmp1, Tmp2, Tmp3, Tmp4, CC);
3615  } else {
3616  Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3617  CC = DAG.getCondCode(ISD::SETNE);
3618  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3619  Tmp2, Tmp3, Tmp4, CC);
3620  }
3621  Tmp1->setFlags(Node->getFlags());
3622  }
3623  Results.push_back(Tmp1);
3624  break;
3625  }
3626  case ISD::BR_CC: {
3627  Tmp1 = Node->getOperand(0); // Chain
3628  Tmp2 = Node->getOperand(2); // LHS
3629  Tmp3 = Node->getOperand(3); // RHS
3630  Tmp4 = Node->getOperand(1); // CC
3631 
3632  bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3633  Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3634  (void)Legalized;
3635  assert(Legalized && "Can't legalize BR_CC with legal condition!");
3636 
3637  assert(!NeedInvert && "Don't know how to invert BR_CC!");
3638 
3639  // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3640  // node.
3641  if (Tmp4.getNode()) {
3642  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3643  Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3644  } else {
3645  Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3646  Tmp4 = DAG.getCondCode(ISD::SETNE);
3647  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3648  Tmp2, Tmp3, Node->getOperand(4));
3649  }
3650  Results.push_back(Tmp1);
3651  break;
3652  }
3653  case ISD::BUILD_VECTOR:
3654  Results.push_back(ExpandBUILD_VECTOR(Node));
3655  break;
3656  case ISD::SRA:
3657  case ISD::SRL:
3658  case ISD::SHL: {
3659  // Scalarize vector SRA/SRL/SHL.
3660  EVT VT = Node->getValueType(0);
3661  assert(VT.isVector() && "Unable to legalize non-vector shift");
3662  assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3663  unsigned NumElem = VT.getVectorNumElements();
3664 
3665  SmallVector<SDValue, 8> Scalars;
3666  for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3667  SDValue Ex = DAG.getNode(
3668  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3669  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3670  SDValue Sh = DAG.getNode(
3671  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3672  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3673  Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3674  VT.getScalarType(), Ex, Sh));
3675  }
3676 
3677  SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
3678  ReplaceNode(SDValue(Node, 0), Result);
3679  break;
3680  }
3681  case ISD::VECREDUCE_FADD:
3682  case ISD::VECREDUCE_FMUL:
3683  case ISD::VECREDUCE_ADD:
3684  case ISD::VECREDUCE_MUL:
3685  case ISD::VECREDUCE_AND:
3686  case ISD::VECREDUCE_OR:
3687  case ISD::VECREDUCE_XOR:
3688  case ISD::VECREDUCE_SMAX:
3689  case ISD::VECREDUCE_SMIN:
3690  case ISD::VECREDUCE_UMAX:
3691  case ISD::VECREDUCE_UMIN:
3692  case ISD::VECREDUCE_FMAX:
3693  case ISD::VECREDUCE_FMIN:
3694  Results.push_back(TLI.expandVecReduce(Node, DAG));
3695  break;
3697  case ISD::GlobalAddress:
3698  case ISD::GlobalTLSAddress:
3699  case ISD::ExternalSymbol:
3700  case ISD::ConstantPool:
3701  case ISD::JumpTable:
3704  case ISD::INTRINSIC_VOID:
3705  // FIXME: Custom lowering for these operations shouldn't return null!
3706  break;
3707  }
3708 
3709  if (Results.empty() && Node->isStrictFPOpcode()) {
3710  // FIXME: We were asked to expand a strict floating-point operation,
3711  // but there is currently no expansion implemented that would preserve
3712  // the "strict" properties. For now, we just fall back to the non-strict
3713  // version if that is legal on the target. The actual mutation of the
3714  // operation will happen in SelectionDAGISel::DoInstructionSelection.
3715  if (TLI.getStrictFPOperationAction(Node->getOpcode(),
3716  Node->getValueType(0))
3718  return true;
3719  }
3720 
3721  // Replace the original node with the legalized result.
3722  if (Results.empty()) {
3723  LLVM_DEBUG(dbgs() << "Cannot expand node\n");
3724  return false;
3725  }
3726 
3727  LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
3728  ReplaceNode(Node, Results.data());
3729  return true;
3730 }
3731 
3732 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3733  LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
3735  SDLoc dl(Node);
3736  // FIXME: Check flags on the node to see if we can use a finite call.
3737  bool CanUseFiniteLibCall = TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath;
3738  unsigned Opc = Node->getOpcode();
3739  switch (Opc) {
3740  case ISD::ATOMIC_FENCE: {
3741  // If the target didn't lower this, lower it to '__sync_synchronize()' call
3742  // FIXME: handle "fence singlethread" more efficiently.
3744 
3746  CLI.setDebugLoc(dl)
3747  .setChain(Node->getOperand(0))
3748  .setLibCallee(
3749  CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3750  DAG.getExternalSymbol("__sync_synchronize",
3751  TLI.getPointerTy(DAG.getDataLayout())),
3752  std::move(Args));
3753 
3754  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3755 
3756  Results.push_back(CallResult.second);
3757  break;
3758  }
3759  // By default, atomic intrinsics are marked Legal and lowered. Targets
3760  // which don't support them directly, however, may want libcalls, in which
3761  // case they mark them Expand, and we get here.
3762  case ISD::ATOMIC_SWAP:
3763  case ISD::ATOMIC_LOAD_ADD:
3764  case ISD::ATOMIC_LOAD_SUB:
3765  case ISD::ATOMIC_LOAD_AND:
3766  case ISD::ATOMIC_LOAD_CLR:
3767  case ISD::ATOMIC_LOAD_OR:
3768  case ISD::ATOMIC_LOAD_XOR:
3769  case ISD::ATOMIC_LOAD_NAND:
3770  case ISD::ATOMIC_LOAD_MIN:
3771  case ISD::ATOMIC_LOAD_MAX:
3772  case ISD::ATOMIC_LOAD_UMIN:
3773  case ISD::ATOMIC_LOAD_UMAX:
3774  case ISD::ATOMIC_CMP_SWAP: {
3775  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3776  RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
3777  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3778 
3779  std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3780  Results.push_back(Tmp.first);
3781  Results.push_back(Tmp.second);
3782  break;
3783  }
3784  case ISD::TRAP: {
3785  // If this operation is not supported, lower it to 'abort()' call
3788  CLI.setDebugLoc(dl)
3789  .setChain(Node->getOperand(0))
3790  .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3791  DAG.getExternalSymbol(
3792  "abort", TLI.getPointerTy(DAG.getDataLayout())),
3793  std::move(Args));
3794  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3795 
3796  Results.push_back(CallResult.second);
3797  break;
3798  }
3799  case ISD::FMINNUM:
3800  case ISD::STRICT_FMINNUM:
3801  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3802  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3803  RTLIB::FMIN_PPCF128));
3804  break;
3805  case ISD::FMAXNUM:
3806  case ISD::STRICT_FMAXNUM:
3807  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3808  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3809  RTLIB::FMAX_PPCF128));
3810  break;
3811  case ISD::FSQRT:
3812  case ISD::STRICT_FSQRT:
3813  Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3814  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3815  RTLIB::SQRT_PPCF128));
3816  break;
3817  case ISD::FCBRT:
3818  Results.push_back(ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
3819  RTLIB::CBRT_F80, RTLIB::CBRT_F128,
3820  RTLIB::CBRT_PPCF128));
3821  break;
3822  case ISD::FSIN:
3823  case ISD::STRICT_FSIN:
3824  Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3825  RTLIB::SIN_F80, RTLIB::SIN_F128,
3826  RTLIB::SIN_PPCF128));
3827  break;
3828  case ISD::FCOS:
3829  case ISD::STRICT_FCOS:
3830  Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3831  RTLIB::COS_F80, RTLIB::COS_F128,
3832  RTLIB::COS_PPCF128));
3833  break;
3834  case ISD::FSINCOS:
3835  // Expand into sincos libcall.
3836  ExpandSinCosLibCall(Node, Results);
3837  break;
3838  case ISD::FLOG:
3839  case ISD::STRICT_FLOG:
3840  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log_finite))
3841  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_FINITE_F32,
3842  RTLIB::LOG_FINITE_F64,
3843  RTLIB::LOG_FINITE_F80,
3844  RTLIB::LOG_FINITE_F128,
3845  RTLIB::LOG_FINITE_PPCF128));
3846  else
3847  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3848  RTLIB::LOG_F80, RTLIB::LOG_F128,
3849  RTLIB::LOG_PPCF128));
3850  break;
3851  case ISD::FLOG2:
3852  case ISD::STRICT_FLOG2:
3853  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log2_finite))
3854  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_FINITE_F32,
3855  RTLIB::LOG2_FINITE_F64,
3856  RTLIB::LOG2_FINITE_F80,
3857  RTLIB::LOG2_FINITE_F128,
3858  RTLIB::LOG2_FINITE_PPCF128));
3859  else
3860  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3861  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3862  RTLIB::LOG2_PPCF128));
3863  break;
3864  case ISD::FLOG10:
3865  case ISD::STRICT_FLOG10:
3866  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log10_finite))
3867  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_FINITE_F32,
3868  RTLIB::LOG10_FINITE_F64,
3869  RTLIB::LOG10_FINITE_F80,
3870  RTLIB::LOG10_FINITE_F128,
3871  RTLIB::LOG10_FINITE_PPCF128));
3872  else
3873  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3874  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3875  RTLIB::LOG10_PPCF128));
3876  break;
3877  case ISD::FEXP:
3878  case ISD::STRICT_FEXP:
3879  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp_finite))
3880  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_FINITE_F32,
3881  RTLIB::EXP_FINITE_F64,
3882  RTLIB::EXP_FINITE_F80,
3883  RTLIB::EXP_FINITE_F128,
3884  RTLIB::EXP_FINITE_PPCF128));
3885  else
3886  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3887  RTLIB::EXP_F80, RTLIB::EXP_F128,
3888  RTLIB::EXP_PPCF128));
3889  break;
3890  case ISD::FEXP2:
3891  case ISD::STRICT_FEXP2:
3892  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp2_finite))
3893  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_FINITE_F32,
3894  RTLIB::EXP2_FINITE_F64,
3895  RTLIB::EXP2_FINITE_F80,
3896  RTLIB::EXP2_FINITE_F128,
3897  RTLIB::EXP2_FINITE_PPCF128));
3898  else
3899  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3900  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3901  RTLIB::EXP2_PPCF128));
3902  break;
3903  case ISD::FTRUNC:
3904  case ISD::STRICT_FTRUNC:
3905  Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3906  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3907  RTLIB::TRUNC_PPCF128));
3908  break;
3909  case ISD::FFLOOR:
3910  case ISD::STRICT_FFLOOR:
3911  Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3912  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3913  RTLIB::FLOOR_PPCF128));
3914  break;
3915  case ISD::FCEIL:
3916  case ISD::STRICT_FCEIL:
3917  Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3918  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3919  RTLIB::CEIL_PPCF128));
3920  break;
3921  case ISD::FRINT:
3922  case ISD::STRICT_FRINT:
3923  Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3924  RTLIB::RINT_F80, RTLIB::RINT_F128,
3925  RTLIB::RINT_PPCF128));
3926  break;
3927  case ISD::FNEARBYINT:
3929  Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3930  RTLIB::NEARBYINT_F64,
3931  RTLIB::NEARBYINT_F80,
3932  RTLIB::NEARBYINT_F128,
3933  RTLIB::NEARBYINT_PPCF128));
3934  break;
3935  case ISD::FROUND:
3936  case ISD::STRICT_FROUND:
3937  Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3938  RTLIB::ROUND_F64,
3939  RTLIB::ROUND_F80,
3940  RTLIB::ROUND_F128,
3941  RTLIB::ROUND_PPCF128));
3942  break;
3943  case ISD::FPOWI:
3944  case ISD::STRICT_FPOWI:
3945  Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3946  RTLIB::POWI_F80, RTLIB::POWI_F128,
3947  RTLIB::POWI_PPCF128));
3948  break;
3949  case ISD::FPOW:
3950  case ISD::STRICT_FPOW:
3951  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_pow_finite))
3952  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_FINITE_F32,
3953  RTLIB::POW_FINITE_F64,
3954  RTLIB::POW_FINITE_F80,
3955  RTLIB::POW_FINITE_F128,
3956  RTLIB::POW_FINITE_PPCF128));
3957  else
3958  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3959  RTLIB::POW_F80, RTLIB::POW_F128,
3960  RTLIB::POW_PPCF128));
3961  break;
3962  case ISD::FDIV:
3963  Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3964  RTLIB::DIV_F80, RTLIB::DIV_F128,
3965  RTLIB::DIV_PPCF128));
3966  break;
3967  case ISD::FREM:
3968  case ISD::STRICT_FREM:
3969  Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3970  RTLIB::REM_F80, RTLIB::REM_F128,
3971  RTLIB::REM_PPCF128));
3972  break;
3973  case ISD::FMA:
3974  case ISD::STRICT_FMA:
3975  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3976  RTLIB::FMA_F80, RTLIB::FMA_F128,
3977  RTLIB::FMA_PPCF128));
3978  break;
3979  case ISD::FADD:
3980  Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3981  RTLIB::ADD_F80, RTLIB::ADD_F128,
3982  RTLIB::ADD_PPCF128));
3983  break;
3984  case ISD::FMUL:
3985  Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3986  RTLIB::MUL_F80, RTLIB::MUL_F128,
3987  RTLIB::MUL_PPCF128));
3988  break;
3989  case ISD::FP16_TO_FP:
3990  if (Node->getValueType(0) == MVT::f32) {
3991  Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3992  }
3993  break;
3994  case ISD::FP_TO_FP16: {
3995  RTLIB::Libcall LC =
3997  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3998  Results.push_back(ExpandLibCall(LC, Node, false));
3999  break;
4000  }
4001  case ISD::FSUB:
4002  Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4003  RTLIB::SUB_F80, RTLIB::SUB_F128,
4004  RTLIB::SUB_PPCF128));
4005  break;
4006  case ISD::SREM:
4007  Results.push_back(ExpandIntLibCall(Node, true,
4008  RTLIB::SREM_I8,
4009  RTLIB::SREM_I16, RTLIB::SREM_I32,
4010  RTLIB::SREM_I64, RTLIB::SREM_I128));
4011  break;
4012  case ISD::UREM:
4013  Results.push_back(ExpandIntLibCall(Node, false,
4014  RTLIB::UREM_I8,
4015  RTLIB::UREM_I16, RTLIB::UREM_I32,
4016  RTLIB::UREM_I64, RTLIB::UREM_I128));
4017  break;
4018  case ISD::SDIV:
4019  Results.push_back(ExpandIntLibCall(Node, true,
4020  RTLIB::SDIV_I8,
4021  RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4022  RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4023  break;
4024  case ISD::UDIV:
4025  Results.push_back(ExpandIntLibCall(Node, false,
4026  RTLIB::UDIV_I8,
4027  RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4028  RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4029  break;
4030  case ISD::SDIVREM:
4031  case ISD::UDIVREM:
4032  // Expand into divrem libcall
4033  ExpandDivRemLibCall(Node, Results);
4034  break;
4035  case ISD::MUL:
4036  Results.push_back(ExpandIntLibCall(Node, false,
4037  RTLIB::MUL_I8,
4038  RTLIB::MUL_I16, RTLIB::MUL_I32,
4039  RTLIB::MUL_I64, RTLIB::MUL_I128));
4040  break;
4041  case ISD::CTLZ_ZERO_UNDEF:
4042  switch (Node->getSimpleValueType(0).SimpleTy) {
4043  default:
4044  llvm_unreachable("LibCall explicitly requested, but not available");
4045  case MVT::i32:
4046  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false));
4047  break;
4048  case MVT::i64:
4049  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false));
4050  break;
4051  case MVT::i128:
4052  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false));
4053  break;
4054  }
4055  break;
4056  }
4057 
4058  // Replace the original node with the legalized result.
4059  if (!Results.empty()) {
4060  LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
4061  ReplaceNode(Node, Results.data());
4062  } else
4063  LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
4064 }
4065 
4066 // Determine the vector type to use in place of an original scalar element when
4067 // promoting equally sized vectors.
4069  MVT EltVT, MVT NewEltVT) {
4070  unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4071  MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4072  assert(TLI.isTypeLegal(MidVT) && "unexpected");
4073  return MidVT;
4074 }
4075 
4076 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4077  LLVM_DEBUG(dbgs() << "Trying to promote node\n");
4079  MVT OVT = Node->getSimpleValueType(0);
4080  if (Node->getOpcode() == ISD::UINT_TO_FP ||
4081  Node->getOpcode() == ISD::SINT_TO_FP ||
4082  Node->getOpcode() == ISD::SETCC ||
4083  Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4084  Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4085  OVT = Node->getOperand(0).getSimpleValueType();
4086  }
4087  if (Node->getOpcode() == ISD::BR_CC)
4088  OVT = Node->getOperand(2).getSimpleValueType();
4089  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4090  SDLoc dl(Node);
4091  SDValue Tmp1, Tmp2, Tmp3;
4092  switch (Node->getOpcode()) {
4093  case ISD::CTTZ:
4094  case ISD::CTTZ_ZERO_UNDEF:
4095  case ISD::CTLZ:
4096  case ISD::CTLZ_ZERO_UNDEF:
4097  case ISD::CTPOP:
4098  // Zero extend the argument.
4099  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4100  if (Node->getOpcode() == ISD::CTTZ) {
4101  // The count is the same in the promoted type except if the original
4102  // value was zero. This can be handled by setting the bit just off
4103  // the top of the original type.
4104  auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
4105  OVT.getSizeInBits());
4106  Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4107  DAG.getConstant(TopBit, dl, NVT));
4108  }
4109  // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4110  // already the correct result.
4111  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4112  if (Node->getOpcode() == ISD::CTLZ ||
4113  Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4114  // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4115  Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4116  DAG.getConstant(NVT.getSizeInBits() -
4117  OVT.getSizeInBits(), dl, NVT));
4118  }
4119  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4120  break;
4121  case ISD::BITREVERSE:
4122  case ISD::BSWAP: {
4123  unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4124  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4125  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4126  Tmp1 = DAG.getNode(
4127  ISD::SRL, dl, NVT, Tmp1,
4128  DAG.getConstant(DiffBits, dl,
4129  TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4130 
4131  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4132  break;
4133  }
4134  case ISD::FP_TO_UINT:
4135  case ISD::FP_TO_SINT:
4136  Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4137  Node->getOpcode() == ISD::FP_TO_SINT, dl);
4138  Results.push_back(Tmp1);
4139  break;
4140  case ISD::UINT_TO_FP:
4141  case ISD::SINT_TO_FP:
4142  Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4143  Node->getOpcode() == ISD::SINT_TO_FP, dl);
4144  Results.push_back(Tmp1);
4145  break;
4146  case ISD::VAARG: {
4147  SDValue Chain = Node->getOperand(0); // Get the chain.
4148  SDValue Ptr = Node->getOperand(1); // Get the pointer.
4149 
4150  unsigned TruncOp;
4151  if (OVT.isVector()) {
4152  TruncOp = ISD::BITCAST;
4153  } else {
4154  assert(OVT.isInteger()
4155  && "VAARG promotion is supported only for vectors or integer types");
4156  TruncOp = ISD::TRUNCATE;
4157  }
4158 
4159  // Perform the larger operation, then convert back
4160  Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4161  Node->getConstantOperandVal(3));
4162  Chain = Tmp1.getValue(1);
4163 
4164  Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4165 
4166  // Modified the chain result - switch anything that used the old chain to
4167  // use the new one.
4168  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4169  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4170  if (UpdatedNodes) {
4171  UpdatedNodes->insert(Tmp2.getNode());
4172  UpdatedNodes->insert(Chain.getNode());
4173  }
4174  ReplacedNode(Node);
4175  break;
4176  }
4177  case ISD::MUL:
4178  case ISD::SDIV:
4179  case ISD::SREM:
4180  case ISD::UDIV:
4181  case ISD::UREM:
4182  case ISD::AND:
4183  case ISD::OR:
4184  case ISD::XOR: {
4185  unsigned ExtOp, TruncOp;
4186  if (OVT.isVector()) {
4187  ExtOp = ISD::BITCAST;
4188  TruncOp = ISD::BITCAST;
4189  } else {
4190  assert(OVT.isInteger() && "Cannot promote logic operation");
4191 
4192  switch (Node->getOpcode()) {
4193  default:
4194  ExtOp = ISD::ANY_EXTEND;
4195  break;
4196  case ISD::SDIV:
4197  case ISD::SREM:
4198  ExtOp = ISD::SIGN_EXTEND;
4199  break;
4200  case ISD::UDIV:
4201  case ISD::UREM:
4202  ExtOp = ISD::ZERO_EXTEND;
4203  break;
4204  }
4205  TruncOp = ISD::TRUNCATE;
4206  }
4207  // Promote each of the values to the new type.
4208  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4209  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4210  // Perform the larger operation, then convert back
4211  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4212  Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4213  break;
4214  }
4215  case ISD::UMUL_LOHI:
4216  case ISD::SMUL_LOHI: {
4217  // Promote to a multiply in a wider integer type.
4218  unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4219  : ISD::SIGN_EXTEND;
4220  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4221  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4222  Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4223 
4224  auto &DL = DAG.getDataLayout();
4225  unsigned OriginalSize = OVT.getScalarSizeInBits();
4226  Tmp2 = DAG.getNode(
4227  ISD::SRL, dl, NVT, Tmp1,
4228  DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4229  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4230  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4231  break;
4232  }
4233  case ISD::SELECT: {
4234  unsigned ExtOp, TruncOp;
4235  if (Node->getValueType(0).isVector() ||
4236  Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4237  ExtOp = ISD::BITCAST;
4238  TruncOp = ISD::BITCAST;
4239  } else if (Node->getValueType(0).isInteger()) {
4240  ExtOp = ISD::ANY_EXTEND;
4241  TruncOp = ISD::TRUNCATE;
4242  } else {
4243  ExtOp = ISD::FP_EXTEND;
4244  TruncOp = ISD::FP_ROUND;
4245  }
4246  Tmp1 = Node->getOperand(0);
4247  // Promote each of the values to the new type.
4248  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4249  Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4250  // Perform the larger operation, then round down.
4251  Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4252  Tmp1->setFlags(Node->getFlags());
4253  if (TruncOp != ISD::FP_ROUND)
4254  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4255  else
4256  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4257  DAG.getIntPtrConstant(0, dl));
4258  Results.push_back(Tmp1);
4259  break;
4260  }
4261  case ISD::VECTOR_SHUFFLE: {
4262  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4263 
4264  // Cast the two input vectors.
4265  Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4266  Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4267 
4268  // Convert the shuffle mask to the right # elements.
4269  Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4270  Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4271  Results.push_back(Tmp1);
4272  break;
4273  }
4274  case ISD::SETCC: {
4275  unsigned ExtOp = ISD::FP_EXTEND;
4276  if (NVT.isInteger()) {
4277  ISD::CondCode CCCode =
4278  cast<CondCodeSDNode>(Node->getOperand(2))->get();
4280  }
4281  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4282  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4283  Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1,
4284  Tmp2, Node->getOperand(2), Node->getFlags()));
4285  break;
4286  }
4287  case ISD::BR_CC: {
4288  unsigned ExtOp = ISD::FP_EXTEND;
4289  if (NVT.isInteger()) {
4290  ISD::CondCode CCCode =
4291  cast<CondCodeSDNode>(Node->getOperand(1))->get();
4293  }
4294  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4295  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4296  Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4297  Node->getOperand(0), Node->getOperand(1),
4298  Tmp1, Tmp2, Node->getOperand(4)));
4299  break;
4300  }
4301  case ISD::FADD:
4302  case ISD::FSUB:
4303  case ISD::FMUL:
4304  case ISD::FDIV:
4305  case ISD::FREM:
4306  case ISD::FMINNUM:
4307  case ISD::FMAXNUM:
4308  case ISD::FPOW:
4309  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4310  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4311  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4312  Node->getFlags());
4313  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4314  Tmp3, DAG.getIntPtrConstant(0, dl)));
4315  break;
4316  case ISD::FMA:
4317  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4318  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4319  Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4320  Results.push_back(
4321  DAG.getNode(ISD::FP_ROUND, dl, OVT,
4322  DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4323  DAG.getIntPtrConstant(0, dl)));
4324  break;
4325  case ISD::FCOPYSIGN:
4326  case ISD::FPOWI: {
4327  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4328  Tmp2 = Node->getOperand(1);
4329  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4330 
4331  // fcopysign doesn't change anything but the sign bit, so
4332  // (fp_round (fcopysign (fpext a), b))
4333  // is as precise as
4334  // (fp_round (fpext a))
4335  // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4336  const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4337  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4338  Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4339  break;
4340  }
4341  case ISD::FFLOOR:
4342  case ISD::FCEIL:
4343  case ISD::FRINT:
4344  case ISD::FNEARBYINT:
4345  case ISD::FROUND:
4346  case ISD::FTRUNC:
4347  case ISD::FNEG:
4348  case ISD::FSQRT:
4349  case ISD::FSIN:
4350  case ISD::FCOS:
4351  case ISD::FLOG:
4352  case ISD::FLOG2:
4353  case ISD::FLOG10:
4354  case ISD::FABS:
4355  case ISD::FEXP:
4356  case ISD::FEXP2:
4357  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4358  Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4359  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4360  Tmp2, DAG.getIntPtrConstant(0, dl)));
4361  break;
4362  case ISD::BUILD_VECTOR: {
4363  MVT EltVT = OVT.getVectorElementType();
4364  MVT NewEltVT = NVT.getVectorElementType();
4365 
4366  // Handle bitcasts to a different vector type with the same total bit size
4367  //
4368  // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4369  // =>
4370  // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4371 
4372  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4373  "Invalid promote type for build_vector");
4374  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4375 
4376  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4377 
4378  SmallVector<SDValue, 8> NewOps;
4379  for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4380  SDValue Op = Node->getOperand(I);
4381  NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4382  }
4383 
4384  SDLoc SL(Node);
4385  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4386  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4387  Results.push_back(CvtVec);
4388  break;
4389  }
4390  case ISD::EXTRACT_VECTOR_ELT: {
4391  MVT EltVT = OVT.getVectorElementType();
4392  MVT NewEltVT = NVT.getVectorElementType();
4393 
4394  // Handle bitcasts to a different vector type with the same total bit size.
4395  //
4396  // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4397  // =>
4398  // v4i32:castx = bitcast x:v2i64
4399  //
4400  // i64 = bitcast
4401  // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4402  // (i32 (extract_vector_elt castx, (2 * y + 1)))
4403  //
4404 
4405  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4406  "Invalid promote type for extract_vector_elt");
4407  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4408 
4409  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4410  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4411 
4412  SDValue Idx = Node->getOperand(1);
4413  EVT IdxVT = Idx.getValueType();
4414  SDLoc SL(Node);
4415  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4416  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4417 
4418  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4419 
4420  SmallVector<SDValue, 8> NewOps;
4421  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4422  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4423  SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4424 
4425  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4426  CastVec, TmpIdx);
4427  NewOps.push_back(Elt);
4428  }
4429 
4430  SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4431  Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4432  break;
4433  }
4434  case ISD::INSERT_VECTOR_ELT: {
4435  MVT EltVT = OVT.getVectorElementType();
4436  MVT NewEltVT = NVT.getVectorElementType();
4437 
4438  // Handle bitcasts to a different vector type with the same total bit size
4439  //
4440  // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4441  // =>
4442  // v4i32:castx = bitcast x:v2i64
4443  // v2i32:casty = bitcast y:i64
4444  //
4445  // v2i64 = bitcast
4446  // (v4i32 insert_vector_elt
4447  // (v4i32 insert_vector_elt v4i32:castx,
4448  // (extract_vector_elt casty, 0), 2 * z),
4449  // (extract_vector_elt casty, 1), (2 * z + 1))
4450 
4451  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4452  "Invalid promote type for insert_vector_elt");
4453  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4454 
4455  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4456  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4457 
4458  SDValue Val = Node->getOperand(1);
4459  SDValue Idx = Node->getOperand(2);
4460  EVT IdxVT = Idx.getValueType();
4461  SDLoc SL(Node);
4462 
4463  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4464  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4465 
4466  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4467  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4468 
4469  SDValue NewVec = CastVec;
4470  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4471  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4472  SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4473 
4474  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4475  CastVal, IdxOffset);
4476 
4477  NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4478  NewVec, Elt, InEltIdx);
4479  }
4480 
4481  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4482  break;
4483  }
4484  case ISD::SCALAR_TO_VECTOR: {
4485  MVT EltVT = OVT.getVectorElementType();
4486  MVT NewEltVT = NVT.getVectorElementType();
4487 
4488  // Handle bitcasts to different vector type with the same total bit size.
4489  //
4490  // e.g. v2i64 = scalar_to_vector x:i64
4491  // =>
4492  // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4493  //
4494 
4495  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4496  SDValue Val = Node->getOperand(0);
4497  SDLoc SL(Node);
4498 
4499  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4500  SDValue Undef = DAG.getUNDEF(MidVT);
4501 
4502  SmallVector<SDValue, 8> NewElts;
4503  NewElts.push_back(CastVal);
4504  for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4505  NewElts.push_back(Undef);
4506 
4507  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4508  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4509  Results.push_back(CvtVec);
4510  break;
4511  }
4512  case ISD::ATOMIC_SWAP: {
4513  AtomicSDNode *AM = cast<AtomicSDNode>(Node);
4514  SDLoc SL(Node);
4515  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
4516  assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
4517  "unexpected promotion type");
4518  assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
4519  "unexpected atomic_swap with illegal type");
4520 
4521  SDValue NewAtomic
4522  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, NVT,
4523  DAG.getVTList(NVT, MVT::Other),
4524  { AM->getChain(), AM->getBasePtr(), CastVal },
4525  AM->getMemOperand());
4526  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
4527  Results.push_back(NewAtomic.getValue(1));
4528  break;
4529  }
4530  }
4531 
4532  // Replace the original node with the legalized result.
4533  if (!Results.empty()) {
4534  LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
4535  ReplaceNode(Node, Results.data());
4536  } else
4537  LLVM_DEBUG(dbgs() << "Could not promote node\n");
4538 }
4539 
4540 /// This is the entry point for the file.
4542  AssignTopologicalOrder();
4543 
4544  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4545  // Use a delete listener to remove nodes which were deleted during
4546  // legalization from LegalizeNodes. This is needed to handle the situation
4547  // where a new node is allocated by the object pool to the same address of a
4548  // previously deleted node.
4549  DAGNodeDeletedListener DeleteListener(
4550  *this,
4551  [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(N); });
4552 
4553  SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4554 
4555  // Visit all the nodes. We start in topological order, so that we see
4556  // nodes with their original operands intact. Legalization can produce
4557  // new nodes which may themselves need to be legalized. Iterate until all
4558  // nodes have been legalized.
4559  while (true) {
4560  bool AnyLegalized = false;
4561  for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4562  --NI;
4563 
4564  SDNode *N = &*NI;
4565  if (N->use_empty() && N != getRoot().getNode()) {
4566  ++NI;
4567  DeleteNode(N);
4568  continue;
4569  }
4570 
4571  if (LegalizedNodes.insert(N).second) {
4572  AnyLegalized = true;
4573  Legalizer.LegalizeOp(N);
4574 
4575  if (N->use_empty() && N != getRoot().getNode()) {
4576  ++NI;
4577  DeleteNode(N);
4578  }
4579  }
4580  }
4581  if (!AnyLegalized)
4582  break;
4583 
4584  }
4585 
4586  // Remove dead nodes now.
4587  RemoveDeadNodes();
4588 }
4589 
4591  SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4592  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4593  SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4594 
4595  // Directly insert the node in question, and legalize it. This will recurse
4596  // as needed through operands.
4597  LegalizedNodes.insert(N);
4598  Legalizer.LegalizeOp(N);
4599 
4600  return LegalizedNodes.count(N);
4601 }
bool LegalizeOp(SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target ...
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:795
static Constant * getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced=false)
Definition: Constants.cpp:1710
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:569
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isInteger() const
Return true if this is an integer or a vector integer type.
void setFlags(SDNodeFlags NewFlags)
static bool isConstant(const MachineInstr &MI)
bool isUndef() const
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:389
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static MVT getVectorVT(MVT VT, unsigned NumElements)
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:398
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
const SDValue & getVal() const
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
bool isVector() const
Return true if this is a vector value type.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void push_back(const T &Elt)
Definition: SmallVector.h:211
const SDValue & getValue() const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:730
SDVTList getVTList() const
This file contains the declarations for metadata subclasses.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
const SDValue & getBasePtr() const
unsigned getVectorNumElements() const
const SDValue & getChain() const
Function Alias Analysis Results
static MVT getPromotedVectorElementType(const TargetLowering &TLI, MVT EltVT, MVT NewEltVT)
unsigned getAlignment() const
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:833
unsigned second
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:865
static uint32_t Concat[]
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:176
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:415
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Same for subtraction.
Definition: ISDOpcodes.h:253
void reserve(size_type N)
Definition: SmallVector.h:369
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:384
The address of the GOT.
Definition: ISDOpcodes.h:65
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:812
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:466
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
const ConstantFP * getConstantFPValue() const
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isTruncatingStore() const
Return true if the op does a truncation before store.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode *> &Visited, SmallVectorImpl< const SDNode *> &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
Definition: ISDOpcodes.h:113
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:487
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Shift and rotation operations.
Definition: ISDOpcodes.h:441
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:263
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:424
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:654
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
op_iterator op_end() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
Definition: ISDOpcodes.h:577
SimpleValueType SimpleTy
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence, and carry arbitrary information that target might want to know.
Definition: ISDOpcodes.h:744
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA)...
Definition: ISDOpcodes.h:95
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:841
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:417
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
This is an SDNode representing atomic operations.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:726
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:90
unsigned getSizeInBits() const
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:509
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here...
Definition: ISDOpcodes.h:117
falkor hwpf fix Falkor HW Prefetch Fix Late Phase
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:418
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool bitsLT(MVT VT) const
Return true if this has less bits than VT.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
CallLoweringInfo & setZExtResult(bool Value=true)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:878
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:1012
op_iterator op_begin() const
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:330
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:124
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:778
static bool useSinCos(SDNode *Node)
Only issue sincos libcall if both sin and cos are needed.
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:1045
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
MVT getVectorElementType() const
UNDEF - An undefined node.
Definition: ISDOpcodes.h:177
This class is used to represent ISD::STORE nodes.
Definition: SelectionDA