LLVM  9.0.0svn
LegalizeDAG.cpp
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1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAG::Legalize method.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/APFloat.h"
14 #include "llvm/ADT/APInt.h"
15 #include "llvm/ADT/ArrayRef.h"
16 #include "llvm/ADT/SetVector.h"
17 #include "llvm/ADT/SmallPtrSet.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DataLayout.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Metadata.h"
37 #include "llvm/IR/Type.h"
38 #include "llvm/Support/Casting.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/Debug.h"
47 #include <algorithm>
48 #include <cassert>
49 #include <cstdint>
50 #include <tuple>
51 #include <utility>
52 
53 using namespace llvm;
54 
55 #define DEBUG_TYPE "legalizedag"
56 
57 namespace {
58 
59 /// Keeps track of state when getting the sign of a floating-point value as an
60 /// integer.
61 struct FloatSignAsInt {
62  EVT FloatVT;
63  SDValue Chain;
64  SDValue FloatPtr;
65  SDValue IntPtr;
66  MachinePointerInfo IntPointerInfo;
67  MachinePointerInfo FloatPointerInfo;
68  SDValue IntValue;
69  APInt SignMask;
70  uint8_t SignBit;
71 };
72 
73 //===----------------------------------------------------------------------===//
74 /// This takes an arbitrary SelectionDAG as input and
75 /// hacks on it until the target machine can handle it. This involves
76 /// eliminating value sizes the machine cannot handle (promoting small sizes to
77 /// large sizes or splitting up large values into small values) as well as
78 /// eliminating operations the machine cannot handle.
79 ///
80 /// This code also does a small amount of optimization and recognition of idioms
81 /// as part of its processing. For example, if a target does not support a
82 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
83 /// will attempt merge setcc and brc instructions into brcc's.
84 class SelectionDAGLegalize {
85  const TargetMachine &TM;
86  const TargetLowering &TLI;
87  SelectionDAG &DAG;
88 
89  /// The set of nodes which have already been legalized. We hold a
90  /// reference to it in order to update as necessary on node deletion.
91  SmallPtrSetImpl<SDNode *> &LegalizedNodes;
92 
93  /// A set of all the nodes updated during legalization.
94  SmallSetVector<SDNode *, 16> *UpdatedNodes;
95 
96  EVT getSetCCResultType(EVT VT) const {
97  return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
98  }
99 
100  // Libcall insertion helpers.
101 
102 public:
103  SelectionDAGLegalize(SelectionDAG &DAG,
104  SmallPtrSetImpl<SDNode *> &LegalizedNodes,
105  SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
106  : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
107  LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
108 
109  /// Legalizes the given operation.
110  void LegalizeOp(SDNode *Node);
111 
112 private:
113  SDValue OptimizeFloatStore(StoreSDNode *ST);
114 
115  void LegalizeLoadOps(SDNode *Node);
116  void LegalizeStoreOps(SDNode *Node);
117 
118  /// Some targets cannot handle a variable
119  /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
120  /// is necessary to spill the vector being inserted into to memory, perform
121  /// the insert there, and then read the result back.
122  SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
123  const SDLoc &dl);
124  SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx,
125  const SDLoc &dl);
126 
127  /// Return a vector shuffle operation which
128  /// performs the same shuffe in terms of order or result bytes, but on a type
129  /// whose vector element type is narrower than the original shuffle type.
130  /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
131  SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, const SDLoc &dl,
132  SDValue N1, SDValue N2,
133  ArrayRef<int> Mask) const;
134 
135  bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
136  bool &NeedInvert, const SDLoc &dl);
137 
138  SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
139 
140  std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
141  SDNode *Node, bool isSigned);
142  SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
143  RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
144  RTLIB::Libcall Call_F128,
145  RTLIB::Libcall Call_PPCF128);
146  SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
147  RTLIB::Libcall Call_I8,
148  RTLIB::Libcall Call_I16,
149  RTLIB::Libcall Call_I32,
150  RTLIB::Libcall Call_I64,
151  RTLIB::Libcall Call_I128);
152  SDValue ExpandArgFPLibCall(SDNode *Node,
153  RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
154  RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
155  RTLIB::Libcall Call_PPCF128);
156  void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
157  void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
158 
159  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
160  const SDLoc &dl);
161  SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
162  const SDLoc &dl, SDValue ChainIn);
163  SDValue ExpandBUILD_VECTOR(SDNode *Node);
164  SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
165  void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
166  SmallVectorImpl<SDValue> &Results);
167  void getSignAsIntValue(FloatSignAsInt &State, const SDLoc &DL,
168  SDValue Value) const;
169  SDValue modifySignAsInt(const FloatSignAsInt &State, const SDLoc &DL,
170  SDValue NewIntValue) const;
171  SDValue ExpandFCOPYSIGN(SDNode *Node) const;
172  SDValue ExpandFABS(SDNode *Node) const;
173  SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
174  const SDLoc &dl);
175  SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
176  const SDLoc &dl);
177  SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
178  const SDLoc &dl);
179 
180  SDValue ExpandBITREVERSE(SDValue Op, const SDLoc &dl);
181  SDValue ExpandBSWAP(SDValue Op, const SDLoc &dl);
182 
183  SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
184  SDValue ExpandInsertToVectorThroughStack(SDValue Op);
185  SDValue ExpandVectorBuildThroughStack(SDNode* Node);
186 
187  SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
188  SDValue ExpandConstant(ConstantSDNode *CP);
189 
190  // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
191  bool ExpandNode(SDNode *Node);
192  void ConvertNodeToLibcall(SDNode *Node);
193  void PromoteNode(SDNode *Node);
194 
195 public:
196  // Node replacement helpers
197 
198  void ReplacedNode(SDNode *N) {
199  LegalizedNodes.erase(N);
200  if (UpdatedNodes)
201  UpdatedNodes->insert(N);
202  }
203 
204  void ReplaceNode(SDNode *Old, SDNode *New) {
205  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
206  dbgs() << " with: "; New->dump(&DAG));
207 
208  assert(Old->getNumValues() == New->getNumValues() &&
209  "Replacing one node with another that produces a different number "
210  "of values!");
211  DAG.ReplaceAllUsesWith(Old, New);
212  if (UpdatedNodes)
213  UpdatedNodes->insert(New);
214  ReplacedNode(Old);
215  }
216 
217  void ReplaceNode(SDValue Old, SDValue New) {
218  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
219  dbgs() << " with: "; New->dump(&DAG));
220 
221  DAG.ReplaceAllUsesWith(Old, New);
222  if (UpdatedNodes)
223  UpdatedNodes->insert(New.getNode());
224  ReplacedNode(Old.getNode());
225  }
226 
227  void ReplaceNode(SDNode *Old, const SDValue *New) {
228  LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
229 
230  DAG.ReplaceAllUsesWith(Old, New);
231  for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
232  LLVM_DEBUG(dbgs() << (i == 0 ? " with: " : " and: ");
233  New[i]->dump(&DAG));
234  if (UpdatedNodes)
235  UpdatedNodes->insert(New[i].getNode());
236  }
237  ReplacedNode(Old);
238  }
239 };
240 
241 } // end anonymous namespace
242 
243 /// Return a vector shuffle operation which
244 /// performs the same shuffle in terms of order or result bytes, but on a type
245 /// whose vector element type is narrower than the original shuffle type.
246 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
247 SDValue SelectionDAGLegalize::ShuffleWithNarrowerEltType(
248  EVT NVT, EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
249  ArrayRef<int> Mask) const {
250  unsigned NumMaskElts = VT.getVectorNumElements();
251  unsigned NumDestElts = NVT.getVectorNumElements();
252  unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
253 
254  assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
255 
256  if (NumEltsGrowth == 1)
257  return DAG.getVectorShuffle(NVT, dl, N1, N2, Mask);
258 
259  SmallVector<int, 8> NewMask;
260  for (unsigned i = 0; i != NumMaskElts; ++i) {
261  int Idx = Mask[i];
262  for (unsigned j = 0; j != NumEltsGrowth; ++j) {
263  if (Idx < 0)
264  NewMask.push_back(-1);
265  else
266  NewMask.push_back(Idx * NumEltsGrowth + j);
267  }
268  }
269  assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
270  assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
271  return DAG.getVectorShuffle(NVT, dl, N1, N2, NewMask);
272 }
273 
274 /// Expands the ConstantFP node to an integer constant or
275 /// a load from the constant pool.
276 SDValue
277 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
278  bool Extend = false;
279  SDLoc dl(CFP);
280 
281  // If a FP immediate is precise when represented as a float and if the
282  // target can do an extending load from float to double, we put it into
283  // the constant pool as a float, even if it's is statically typed as a
284  // double. This shrinks FP constants and canonicalizes them for targets where
285  // an FP extending load is the same cost as a normal load (such as on the x87
286  // fp stack or PPC FP unit).
287  EVT VT = CFP->getValueType(0);
288  ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
289  if (!UseCP) {
290  assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
291  return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
292  (VT == MVT::f64) ? MVT::i64 : MVT::i32);
293  }
294 
295  APFloat APF = CFP->getValueAPF();
296  EVT OrigVT = VT;
297  EVT SVT = VT;
298 
299  // We don't want to shrink SNaNs. Converting the SNaN back to its real type
300  // can cause it to be changed into a QNaN on some platforms (e.g. on SystemZ).
301  if (!APF.isSignaling()) {
302  while (SVT != MVT::f32 && SVT != MVT::f16) {
303  SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
305  // Only do this if the target has a native EXTLOAD instruction from
306  // smaller type.
307  TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
308  TLI.ShouldShrinkFPConstant(OrigVT)) {
309  Type *SType = SVT.getTypeForEVT(*DAG.getContext());
310  LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
311  VT = SVT;
312  Extend = true;
313  }
314  }
315  }
316 
317  SDValue CPIdx =
318  DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
319  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
320  if (Extend) {
321  SDValue Result = DAG.getExtLoad(
322  ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
323  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
324  Alignment);
325  return Result;
326  }
327  SDValue Result = DAG.getLoad(
328  OrigVT, dl, DAG.getEntryNode(), CPIdx,
329  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
330  return Result;
331 }
332 
333 /// Expands the Constant node to a load from the constant pool.
334 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
335  SDLoc dl(CP);
336  EVT VT = CP->getValueType(0);
337  SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
338  TLI.getPointerTy(DAG.getDataLayout()));
339  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
340  SDValue Result = DAG.getLoad(
341  VT, dl, DAG.getEntryNode(), CPIdx,
342  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), Alignment);
343  return Result;
344 }
345 
346 /// Some target cannot handle a variable insertion index for the
347 /// INSERT_VECTOR_ELT instruction. In this case, it
348 /// is necessary to spill the vector being inserted into to memory, perform
349 /// the insert there, and then read the result back.
350 SDValue SelectionDAGLegalize::PerformInsertVectorEltInMemory(SDValue Vec,
351  SDValue Val,
352  SDValue Idx,
353  const SDLoc &dl) {
354  SDValue Tmp1 = Vec;
355  SDValue Tmp2 = Val;
356  SDValue Tmp3 = Idx;
357 
358  // If the target doesn't support this, we have to spill the input vector
359  // to a temporary stack slot, update the element, then reload it. This is
360  // badness. We could also load the value into a vector register (either
361  // with a "move to register" or "extload into register" instruction, then
362  // permute it into place, if the idx is a constant and if the idx is
363  // supported by the target.
364  EVT VT = Tmp1.getValueType();
365  EVT EltVT = VT.getVectorElementType();
366  SDValue StackPtr = DAG.CreateStackTemporary(VT);
367 
368  int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
369 
370  // Store the vector.
371  SDValue Ch = DAG.getStore(
372  DAG.getEntryNode(), dl, Tmp1, StackPtr,
373  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
374 
375  SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
376 
377  // Store the scalar value.
378  Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT);
379  // Load the updated vector.
380  return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
381  DAG.getMachineFunction(), SPFI));
382 }
383 
384 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
385  SDValue Idx,
386  const SDLoc &dl) {
387  if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
388  // SCALAR_TO_VECTOR requires that the type of the value being inserted
389  // match the element type of the vector being created, except for
390  // integers in which case the inserted value can be over width.
391  EVT EltVT = Vec.getValueType().getVectorElementType();
392  if (Val.getValueType() == EltVT ||
393  (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
394  SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
395  Vec.getValueType(), Val);
396 
397  unsigned NumElts = Vec.getValueType().getVectorNumElements();
398  // We generate a shuffle of InVec and ScVec, so the shuffle mask
399  // should be 0,1,2,3,4,5... with the appropriate element replaced with
400  // elt 0 of the RHS.
401  SmallVector<int, 8> ShufOps;
402  for (unsigned i = 0; i != NumElts; ++i)
403  ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
404 
405  return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, ShufOps);
406  }
407  }
408  return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
409 }
410 
411 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
412  LLVM_DEBUG(dbgs() << "Optimizing float store operations\n");
413  // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
414  // FIXME: We shouldn't do this for TargetConstantFP's.
415  // FIXME: move this to the DAG Combiner! Note that we can't regress due
416  // to phase ordering between legalized code and the dag combiner. This
417  // probably means that we need to integrate dag combiner and legalizer
418  // together.
419  // We generally can't do this one for long doubles.
420  SDValue Chain = ST->getChain();
421  SDValue Ptr = ST->getBasePtr();
422  unsigned Alignment = ST->getAlignment();
423  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
424  AAMDNodes AAInfo = ST->getAAInfo();
425  SDLoc dl(ST);
426  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
427  if (CFP->getValueType(0) == MVT::f32 &&
428  TLI.isTypeLegal(MVT::i32)) {
429  SDValue Con = DAG.getConstant(CFP->getValueAPF().
430  bitcastToAPInt().zextOrTrunc(32),
431  SDLoc(CFP), MVT::i32);
432  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), Alignment,
433  MMOFlags, AAInfo);
434  }
435 
436  if (CFP->getValueType(0) == MVT::f64) {
437  // If this target supports 64-bit registers, do a single 64-bit store.
438  if (TLI.isTypeLegal(MVT::i64)) {
439  SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
440  zextOrTrunc(64), SDLoc(CFP), MVT::i64);
441  return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
442  Alignment, MMOFlags, AAInfo);
443  }
444 
445  if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
446  // Otherwise, if the target supports 32-bit registers, use 2 32-bit
447  // stores. If the target supports neither 32- nor 64-bits, this
448  // xform is certainly not worth it.
449  const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
450  SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
451  SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
452  if (DAG.getDataLayout().isBigEndian())
453  std::swap(Lo, Hi);
454 
455  Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), Alignment,
456  MMOFlags, AAInfo);
457  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
458  DAG.getConstant(4, dl, Ptr.getValueType()));
459  Hi = DAG.getStore(Chain, dl, Hi, Ptr,
460  ST->getPointerInfo().getWithOffset(4),
461  MinAlign(Alignment, 4U), MMOFlags, AAInfo);
462 
463  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
464  }
465  }
466  }
467  return SDValue(nullptr, 0);
468 }
469 
470 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
471  StoreSDNode *ST = cast<StoreSDNode>(Node);
472  SDValue Chain = ST->getChain();
473  SDValue Ptr = ST->getBasePtr();
474  SDLoc dl(Node);
475 
476  unsigned Alignment = ST->getAlignment();
477  MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
478  AAMDNodes AAInfo = ST->getAAInfo();
479 
480  if (!ST->isTruncatingStore()) {
481  LLVM_DEBUG(dbgs() << "Legalizing store operation\n");
482  if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
483  ReplaceNode(ST, OptStore);
484  return;
485  }
486 
487  SDValue Value = ST->getValue();
488  MVT VT = Value.getSimpleValueType();
489  switch (TLI.getOperationAction(ISD::STORE, VT)) {
490  default: llvm_unreachable("This action is not supported yet!");
491  case TargetLowering::Legal: {
492  // If this is an unaligned store and the target doesn't support it,
493  // expand it.
494  EVT MemVT = ST->getMemoryVT();
495  unsigned AS = ST->getAddressSpace();
496  unsigned Align = ST->getAlignment();
497  const DataLayout &DL = DAG.getDataLayout();
498  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
499  LLVM_DEBUG(dbgs() << "Expanding unsupported unaligned store\n");
500  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
501  ReplaceNode(SDValue(ST, 0), Result);
502  } else
503  LLVM_DEBUG(dbgs() << "Legal store\n");
504  break;
505  }
506  case TargetLowering::Custom: {
507  LLVM_DEBUG(dbgs() << "Trying custom lowering\n");
508  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
509  if (Res && Res != SDValue(Node, 0))
510  ReplaceNode(SDValue(Node, 0), Res);
511  return;
512  }
514  MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
515  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
516  "Can only promote stores to same size type");
517  Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
518  SDValue Result =
519  DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
520  Alignment, MMOFlags, AAInfo);
521  ReplaceNode(SDValue(Node, 0), Result);
522  break;
523  }
524  }
525  return;
526  }
527 
528  LLVM_DEBUG(dbgs() << "Legalizing truncating store operations\n");
529  SDValue Value = ST->getValue();
530  EVT StVT = ST->getMemoryVT();
531  unsigned StWidth = StVT.getSizeInBits();
532  auto &DL = DAG.getDataLayout();
533 
534  if (StWidth != StVT.getStoreSizeInBits()) {
535  // Promote to a byte-sized store with upper bits zero if not
536  // storing an integral number of bytes. For example, promote
537  // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
538  EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
539  StVT.getStoreSizeInBits());
540  Value = DAG.getZeroExtendInReg(Value, dl, StVT);
541  SDValue Result =
542  DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
543  Alignment, MMOFlags, AAInfo);
544  ReplaceNode(SDValue(Node, 0), Result);
545  } else if (StWidth & (StWidth - 1)) {
546  // If not storing a power-of-2 number of bits, expand as two stores.
547  assert(!StVT.isVector() && "Unsupported truncstore!");
548  unsigned LogStWidth = Log2_32(StWidth);
549  assert(LogStWidth < 32);
550  unsigned RoundWidth = 1 << LogStWidth;
551  assert(RoundWidth < StWidth);
552  unsigned ExtraWidth = StWidth - RoundWidth;
553  assert(ExtraWidth < RoundWidth);
554  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
555  "Store size not an integral number of bytes!");
556  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
557  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
558  SDValue Lo, Hi;
559  unsigned IncrementSize;
560 
561  if (DL.isLittleEndian()) {
562  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
563  // Store the bottom RoundWidth bits.
564  Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
565  RoundVT, Alignment, MMOFlags, AAInfo);
566 
567  // Store the remaining ExtraWidth bits.
568  IncrementSize = RoundWidth / 8;
569  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
570  DAG.getConstant(IncrementSize, dl,
571  Ptr.getValueType()));
572  Hi = DAG.getNode(
573  ISD::SRL, dl, Value.getValueType(), Value,
574  DAG.getConstant(RoundWidth, dl,
575  TLI.getShiftAmountTy(Value.getValueType(), DL)));
576  Hi = DAG.getTruncStore(
577  Chain, dl, Hi, Ptr,
578  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
579  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
580  } else {
581  // Big endian - avoid unaligned stores.
582  // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
583  // Store the top RoundWidth bits.
584  Hi = DAG.getNode(
585  ISD::SRL, dl, Value.getValueType(), Value,
586  DAG.getConstant(ExtraWidth, dl,
587  TLI.getShiftAmountTy(Value.getValueType(), DL)));
588  Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
589  RoundVT, Alignment, MMOFlags, AAInfo);
590 
591  // Store the remaining ExtraWidth bits.
592  IncrementSize = RoundWidth / 8;
593  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
594  DAG.getConstant(IncrementSize, dl,
595  Ptr.getValueType()));
596  Lo = DAG.getTruncStore(
597  Chain, dl, Value, Ptr,
598  ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT,
599  MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
600  }
601 
602  // The order of the stores doesn't matter.
603  SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
604  ReplaceNode(SDValue(Node, 0), Result);
605  } else {
606  switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
607  default: llvm_unreachable("This action is not supported yet!");
608  case TargetLowering::Legal: {
609  EVT MemVT = ST->getMemoryVT();
610  unsigned AS = ST->getAddressSpace();
611  unsigned Align = ST->getAlignment();
612  // If this is an unaligned store and the target doesn't support it,
613  // expand it.
614  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
615  SDValue Result = TLI.expandUnalignedStore(ST, DAG);
616  ReplaceNode(SDValue(ST, 0), Result);
617  }
618  break;
619  }
620  case TargetLowering::Custom: {
621  SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
622  if (Res && Res != SDValue(Node, 0))
623  ReplaceNode(SDValue(Node, 0), Res);
624  return;
625  }
627  assert(!StVT.isVector() &&
628  "Vector Stores are handled in LegalizeVectorOps");
629 
630  SDValue Result;
631 
632  // TRUNCSTORE:i16 i32 -> STORE i16
633  if (TLI.isTypeLegal(StVT)) {
634  Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
635  Result = DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
636  Alignment, MMOFlags, AAInfo);
637  } else {
638  // The in-memory type isn't legal. Truncate to the type it would promote
639  // to, and then do a truncstore.
640  Value = DAG.getNode(ISD::TRUNCATE, dl,
641  TLI.getTypeToTransformTo(*DAG.getContext(), StVT),
642  Value);
643  Result = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
644  StVT, Alignment, MMOFlags, AAInfo);
645  }
646 
647  ReplaceNode(SDValue(Node, 0), Result);
648  break;
649  }
650  }
651 }
652 
653 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
654  LoadSDNode *LD = cast<LoadSDNode>(Node);
655  SDValue Chain = LD->getChain(); // The chain.
656  SDValue Ptr = LD->getBasePtr(); // The base pointer.
657  SDValue Value; // The value returned by the load op.
658  SDLoc dl(Node);
659 
661  if (ExtType == ISD::NON_EXTLOAD) {
662  LLVM_DEBUG(dbgs() << "Legalizing non-extending load operation\n");
663  MVT VT = Node->getSimpleValueType(0);
664  SDValue RVal = SDValue(Node, 0);
665  SDValue RChain = SDValue(Node, 1);
666 
667  switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
668  default: llvm_unreachable("This action is not supported yet!");
669  case TargetLowering::Legal: {
670  EVT MemVT = LD->getMemoryVT();
671  unsigned AS = LD->getAddressSpace();
672  unsigned Align = LD->getAlignment();
673  const DataLayout &DL = DAG.getDataLayout();
674  // If this is an unaligned load and the target doesn't support it,
675  // expand it.
676  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
677  std::tie(RVal, RChain) = TLI.expandUnalignedLoad(LD, DAG);
678  }
679  break;
680  }
682  if (SDValue Res = TLI.LowerOperation(RVal, DAG)) {
683  RVal = Res;
684  RChain = Res.getValue(1);
685  }
686  break;
687 
689  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
690  assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
691  "Can only promote loads to same size type");
692 
693  SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
694  RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
695  RChain = Res.getValue(1);
696  break;
697  }
698  }
699  if (RChain.getNode() != Node) {
700  assert(RVal.getNode() != Node && "Load must be completely replaced");
701  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
702  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
703  if (UpdatedNodes) {
704  UpdatedNodes->insert(RVal.getNode());
705  UpdatedNodes->insert(RChain.getNode());
706  }
707  ReplacedNode(Node);
708  }
709  return;
710  }
711 
712  LLVM_DEBUG(dbgs() << "Legalizing extending load operation\n");
713  EVT SrcVT = LD->getMemoryVT();
714  unsigned SrcWidth = SrcVT.getSizeInBits();
715  unsigned Alignment = LD->getAlignment();
716  MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
717  AAMDNodes AAInfo = LD->getAAInfo();
718 
719  if (SrcWidth != SrcVT.getStoreSizeInBits() &&
720  // Some targets pretend to have an i1 loading operation, and actually
721  // load an i8. This trick is correct for ZEXTLOAD because the top 7
722  // bits are guaranteed to be zero; it helps the optimizers understand
723  // that these bits are zero. It is also useful for EXTLOAD, since it
724  // tells the optimizers that those bits are undefined. It would be
725  // nice to have an effective generic way of getting these benefits...
726  // Until such a way is found, don't insist on promoting i1 here.
727  (SrcVT != MVT::i1 ||
728  TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
730  // Promote to a byte-sized load if not loading an integral number of
731  // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
732  unsigned NewWidth = SrcVT.getStoreSizeInBits();
733  EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
734  SDValue Ch;
735 
736  // The extra bits are guaranteed to be zero, since we stored them that
737  // way. A zext load from NVT thus automatically gives zext from SrcVT.
738 
739  ISD::LoadExtType NewExtType =
741 
742  SDValue Result =
743  DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), Chain, Ptr,
744  LD->getPointerInfo(), NVT, Alignment, MMOFlags, AAInfo);
745 
746  Ch = Result.getValue(1); // The chain.
747 
748  if (ExtType == ISD::SEXTLOAD)
749  // Having the top bits zero doesn't help when sign extending.
750  Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
751  Result.getValueType(),
752  Result, DAG.getValueType(SrcVT));
753  else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
754  // All the top bits are guaranteed to be zero - inform the optimizers.
755  Result = DAG.getNode(ISD::AssertZext, dl,
756  Result.getValueType(), Result,
757  DAG.getValueType(SrcVT));
758 
759  Value = Result;
760  Chain = Ch;
761  } else if (SrcWidth & (SrcWidth - 1)) {
762  // If not loading a power-of-2 number of bits, expand as two loads.
763  assert(!SrcVT.isVector() && "Unsupported extload!");
764  unsigned LogSrcWidth = Log2_32(SrcWidth);
765  assert(LogSrcWidth < 32);
766  unsigned RoundWidth = 1 << LogSrcWidth;
767  assert(RoundWidth < SrcWidth);
768  unsigned ExtraWidth = SrcWidth - RoundWidth;
769  assert(ExtraWidth < RoundWidth);
770  assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
771  "Load size not an integral number of bytes!");
772  EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
773  EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
774  SDValue Lo, Hi, Ch;
775  unsigned IncrementSize;
776  auto &DL = DAG.getDataLayout();
777 
778  if (DL.isLittleEndian()) {
779  // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
780  // Load the bottom RoundWidth bits.
781  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
782  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
783  AAInfo);
784 
785  // Load the remaining ExtraWidth bits.
786  IncrementSize = RoundWidth / 8;
787  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
788  DAG.getConstant(IncrementSize, dl,
789  Ptr.getValueType()));
790  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
791  LD->getPointerInfo().getWithOffset(IncrementSize),
792  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
793  AAInfo);
794 
795  // Build a factor node to remember that this load is independent of
796  // the other one.
797  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
798  Hi.getValue(1));
799 
800  // Move the top bits to the right place.
801  Hi = DAG.getNode(
802  ISD::SHL, dl, Hi.getValueType(), Hi,
803  DAG.getConstant(RoundWidth, dl,
804  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
805 
806  // Join the hi and lo parts.
807  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
808  } else {
809  // Big endian - avoid unaligned loads.
810  // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
811  // Load the top RoundWidth bits.
812  Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
813  LD->getPointerInfo(), RoundVT, Alignment, MMOFlags,
814  AAInfo);
815 
816  // Load the remaining ExtraWidth bits.
817  IncrementSize = RoundWidth / 8;
818  Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
819  DAG.getConstant(IncrementSize, dl,
820  Ptr.getValueType()));
821  Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
822  LD->getPointerInfo().getWithOffset(IncrementSize),
823  ExtraVT, MinAlign(Alignment, IncrementSize), MMOFlags,
824  AAInfo);
825 
826  // Build a factor node to remember that this load is independent of
827  // the other one.
828  Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
829  Hi.getValue(1));
830 
831  // Move the top bits to the right place.
832  Hi = DAG.getNode(
833  ISD::SHL, dl, Hi.getValueType(), Hi,
834  DAG.getConstant(ExtraWidth, dl,
835  TLI.getShiftAmountTy(Hi.getValueType(), DL)));
836 
837  // Join the hi and lo parts.
838  Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
839  }
840 
841  Chain = Ch;
842  } else {
843  bool isCustom = false;
844  switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
845  SrcVT.getSimpleVT())) {
846  default: llvm_unreachable("This action is not supported yet!");
848  isCustom = true;
851  Value = SDValue(Node, 0);
852  Chain = SDValue(Node, 1);
853 
854  if (isCustom) {
855  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
856  Value = Res;
857  Chain = Res.getValue(1);
858  }
859  } else {
860  // If this is an unaligned load and the target doesn't support it,
861  // expand it.
862  EVT MemVT = LD->getMemoryVT();
863  unsigned AS = LD->getAddressSpace();
864  unsigned Align = LD->getAlignment();
865  const DataLayout &DL = DAG.getDataLayout();
866  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) {
867  std::tie(Value, Chain) = TLI.expandUnalignedLoad(LD, DAG);
868  }
869  }
870  break;
871 
872  case TargetLowering::Expand: {
873  EVT DestVT = Node->getValueType(0);
874  if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
875  // If the source type is not legal, see if there is a legal extload to
876  // an intermediate type that we can then extend further.
877  EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
878  if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
879  TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
880  // If we are loading a legal type, this is a non-extload followed by a
881  // full extend.
882  ISD::LoadExtType MidExtType =
883  (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
884 
885  SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
886  SrcVT, LD->getMemOperand());
887  unsigned ExtendOp =
889  Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
890  Chain = Load.getValue(1);
891  break;
892  }
893 
894  // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
895  // normal undefined upper bits behavior to allow using an in-reg extend
896  // with the illegal FP type, so load as an integer and do the
897  // from-integer conversion.
898  if (SrcVT.getScalarType() == MVT::f16) {
899  EVT ISrcVT = SrcVT.changeTypeToInteger();
900  EVT IDestVT = DestVT.changeTypeToInteger();
901  EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
902 
903  SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
904  Chain, Ptr, ISrcVT,
905  LD->getMemOperand());
906  Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
907  Chain = Result.getValue(1);
908  break;
909  }
910  }
911 
912  assert(!SrcVT.isVector() &&
913  "Vector Loads are handled in LegalizeVectorOps");
914 
915  // FIXME: This does not work for vectors on most targets. Sign-
916  // and zero-extend operations are currently folded into extending
917  // loads, whether they are legal or not, and then we end up here
918  // without any support for legalizing them.
919  assert(ExtType != ISD::EXTLOAD &&
920  "EXTLOAD should always be supported!");
921  // Turn the unsupported load into an EXTLOAD followed by an
922  // explicit zero/sign extend inreg.
923  SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
924  Node->getValueType(0),
925  Chain, Ptr, SrcVT,
926  LD->getMemOperand());
927  SDValue ValRes;
928  if (ExtType == ISD::SEXTLOAD)
929  ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
930  Result.getValueType(),
931  Result, DAG.getValueType(SrcVT));
932  else
933  ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
934  Value = ValRes;
935  Chain = Result.getValue(1);
936  break;
937  }
938  }
939  }
940 
941  // Since loads produce two values, make sure to remember that we legalized
942  // both of them.
943  if (Chain.getNode() != Node) {
944  assert(Value.getNode() != Node && "Load must be completely replaced");
945  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
946  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
947  if (UpdatedNodes) {
948  UpdatedNodes->insert(Value.getNode());
949  UpdatedNodes->insert(Chain.getNode());
950  }
951  ReplacedNode(Node);
952  }
953 }
954 
955 /// Return a legal replacement for the given operation, with all legal operands.
956 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
957  LLVM_DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
958 
959  // Allow illegal target nodes and illegal registers.
960  if (Node->getOpcode() == ISD::TargetConstant ||
961  Node->getOpcode() == ISD::Register)
962  return;
963 
964 #ifndef NDEBUG
965  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
966  assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
968  TLI.isTypeLegal(Node->getValueType(i))) &&
969  "Unexpected illegal type!");
970 
971  for (const SDValue &Op : Node->op_values())
972  assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
974  TLI.isTypeLegal(Op.getValueType()) ||
975  Op.getOpcode() == ISD::TargetConstant ||
976  Op.getOpcode() == ISD::Register) &&
977  "Unexpected illegal type!");
978 #endif
979 
980  // Figure out the correct action; the way to query this varies by opcode
982  bool SimpleFinishLegalizing = true;
983  switch (Node->getOpcode()) {
986  case ISD::INTRINSIC_VOID:
987  case ISD::STACKSAVE:
988  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
989  break;
991  Action = TLI.getOperationAction(Node->getOpcode(),
992  Node->getValueType(0));
993  break;
994  case ISD::VAARG:
995  Action = TLI.getOperationAction(Node->getOpcode(),
996  Node->getValueType(0));
997  if (Action != TargetLowering::Promote)
998  Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
999  break;
1000  case ISD::FP_TO_FP16:
1001  case ISD::SINT_TO_FP:
1002  case ISD::UINT_TO_FP:
1004  case ISD::LROUND:
1005  case ISD::LLROUND:
1006  Action = TLI.getOperationAction(Node->getOpcode(),
1007  Node->getOperand(0).getValueType());
1008  break;
1009  case ISD::FP_ROUND_INREG:
1010  case ISD::SIGN_EXTEND_INREG: {
1011  EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1012  Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1013  break;
1014  }
1015  case ISD::ATOMIC_STORE:
1016  Action = TLI.getOperationAction(Node->getOpcode(),
1017  Node->getOperand(2).getValueType());
1018  break;
1019  case ISD::SELECT_CC:
1020  case ISD::SETCC:
1021  case ISD::BR_CC: {
1022  unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1023  Node->getOpcode() == ISD::SETCC ? 2 : 1;
1024  unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1025  MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1026  ISD::CondCode CCCode =
1027  cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1028  Action = TLI.getCondCodeAction(CCCode, OpVT);
1029  if (Action == TargetLowering::Legal) {
1030  if (Node->getOpcode() == ISD::SELECT_CC)
1031  Action = TLI.getOperationAction(Node->getOpcode(),
1032  Node->getValueType(0));
1033  else
1034  Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1035  }
1036  break;
1037  }
1038  case ISD::LOAD:
1039  case ISD::STORE:
1040  // FIXME: Model these properly. LOAD and STORE are complicated, and
1041  // STORE expects the unlegalized operand in some cases.
1042  SimpleFinishLegalizing = false;
1043  break;
1044  case ISD::CALLSEQ_START:
1045  case ISD::CALLSEQ_END:
1046  // FIXME: This shouldn't be necessary. These nodes have special properties
1047  // dealing with the recursive nature of legalization. Removing this
1048  // special case should be done as part of making LegalizeDAG non-recursive.
1049  SimpleFinishLegalizing = false;
1050  break;
1051  case ISD::EXTRACT_ELEMENT:
1052  case ISD::FLT_ROUNDS_:
1053  case ISD::MERGE_VALUES:
1054  case ISD::EH_RETURN:
1056  case ISD::EH_DWARF_CFA:
1057  case ISD::EH_SJLJ_SETJMP:
1058  case ISD::EH_SJLJ_LONGJMP:
1060  // These operations lie about being legal: when they claim to be legal,
1061  // they should actually be expanded.
1062  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1063  if (Action == TargetLowering::Legal)
1064  Action = TargetLowering::Expand;
1065  break;
1066  case ISD::INIT_TRAMPOLINE:
1068  case ISD::FRAMEADDR:
1069  case ISD::RETURNADDR:
1070  case ISD::ADDROFRETURNADDR:
1071  case ISD::SPONENTRY:
1072  // These operations lie about being legal: when they claim to be legal,
1073  // they should actually be custom-lowered.
1074  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1075  if (Action == TargetLowering::Legal)
1076  Action = TargetLowering::Custom;
1077  break;
1078  case ISD::READCYCLECOUNTER:
1079  // READCYCLECOUNTER returns an i64, even if type legalization might have
1080  // expanded that to several smaller types.
1081  Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1082  break;
1083  case ISD::READ_REGISTER:
1084  case ISD::WRITE_REGISTER:
1085  // Named register is legal in the DAG, but blocked by register name
1086  // selection if not implemented by target (to chose the correct register)
1087  // They'll be converted to Copy(To/From)Reg.
1088  Action = TargetLowering::Legal;
1089  break;
1090  case ISD::DEBUGTRAP:
1091  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1092  if (Action == TargetLowering::Expand) {
1093  // replace ISD::DEBUGTRAP with ISD::TRAP
1094  SDValue NewVal;
1095  NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1096  Node->getOperand(0));
1097  ReplaceNode(Node, NewVal.getNode());
1098  LegalizeOp(NewVal.getNode());
1099  return;
1100  }
1101  break;
1102  case ISD::STRICT_FADD:
1103  case ISD::STRICT_FSUB:
1104  case ISD::STRICT_FMUL:
1105  case ISD::STRICT_FDIV:
1106  case ISD::STRICT_FREM:
1107  case ISD::STRICT_FSQRT:
1108  case ISD::STRICT_FMA:
1109  case ISD::STRICT_FPOW:
1110  case ISD::STRICT_FPOWI:
1111  case ISD::STRICT_FSIN:
1112  case ISD::STRICT_FCOS:
1113  case ISD::STRICT_FEXP:
1114  case ISD::STRICT_FEXP2:
1115  case ISD::STRICT_FLOG:
1116  case ISD::STRICT_FLOG10:
1117  case ISD::STRICT_FLOG2:
1118  case ISD::STRICT_FRINT:
1120  case ISD::STRICT_FMAXNUM:
1121  case ISD::STRICT_FMINNUM:
1122  case ISD::STRICT_FCEIL:
1123  case ISD::STRICT_FFLOOR:
1124  case ISD::STRICT_FROUND:
1125  case ISD::STRICT_FTRUNC:
1126  case ISD::STRICT_FP_ROUND:
1127  case ISD::STRICT_FP_EXTEND:
1128  // These pseudo-ops get legalized as if they were their non-strict
1129  // equivalent. For instance, if ISD::FSQRT is legal then ISD::STRICT_FSQRT
1130  // is also legal, but if ISD::FSQRT requires expansion then so does
1131  // ISD::STRICT_FSQRT.
1132  Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
1133  Node->getValueType(0));
1134  break;
1135  case ISD::SADDSAT:
1136  case ISD::UADDSAT:
1137  case ISD::SSUBSAT:
1138  case ISD::USUBSAT: {
1139  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1140  break;
1141  }
1142  case ISD::SMULFIX:
1143  case ISD::SMULFIXSAT:
1144  case ISD::UMULFIX: {
1145  unsigned Scale = Node->getConstantOperandVal(2);
1146  Action = TLI.getFixedPointOperationAction(Node->getOpcode(),
1147  Node->getValueType(0), Scale);
1148  break;
1149  }
1150  case ISD::MSCATTER:
1151  Action = TLI.getOperationAction(Node->getOpcode(),
1152  cast<MaskedScatterSDNode>(Node)->getValue().getValueType());
1153  break;
1154  case ISD::MSTORE:
1155  Action = TLI.getOperationAction(Node->getOpcode(),
1156  cast<MaskedStoreSDNode>(Node)->getValue().getValueType());
1157  break;
1158  case ISD::VECREDUCE_FADD:
1159  case ISD::VECREDUCE_FMUL:
1160  case ISD::VECREDUCE_ADD:
1161  case ISD::VECREDUCE_MUL:
1162  case ISD::VECREDUCE_AND:
1163  case ISD::VECREDUCE_OR:
1164  case ISD::VECREDUCE_XOR:
1165  case ISD::VECREDUCE_SMAX:
1166  case ISD::VECREDUCE_SMIN:
1167  case ISD::VECREDUCE_UMAX:
1168  case ISD::VECREDUCE_UMIN:
1169  case ISD::VECREDUCE_FMAX:
1170  case ISD::VECREDUCE_FMIN:
1171  Action = TLI.getOperationAction(
1172  Node->getOpcode(), Node->getOperand(0).getValueType());
1173  break;
1174  default:
1175  if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1176  Action = TargetLowering::Legal;
1177  } else {
1178  Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1179  }
1180  break;
1181  }
1182 
1183  if (SimpleFinishLegalizing) {
1184  SDNode *NewNode = Node;
1185  switch (Node->getOpcode()) {
1186  default: break;
1187  case ISD::SHL:
1188  case ISD::SRL:
1189  case ISD::SRA:
1190  case ISD::ROTL:
1191  case ISD::ROTR: {
1192  // Legalizing shifts/rotates requires adjusting the shift amount
1193  // to the appropriate width.
1194  SDValue Op0 = Node->getOperand(0);
1195  SDValue Op1 = Node->getOperand(1);
1196  if (!Op1.getValueType().isVector()) {
1197  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1);
1198  // The getShiftAmountOperand() may create a new operand node or
1199  // return the existing one. If new operand is created we need
1200  // to update the parent node.
1201  // Do not try to legalize SAO here! It will be automatically legalized
1202  // in the next round.
1203  if (SAO != Op1)
1204  NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO);
1205  }
1206  }
1207  break;
1208  case ISD::FSHL:
1209  case ISD::FSHR:
1210  case ISD::SRL_PARTS:
1211  case ISD::SRA_PARTS:
1212  case ISD::SHL_PARTS: {
1213  // Legalizing shifts/rotates requires adjusting the shift amount
1214  // to the appropriate width.
1215  SDValue Op0 = Node->getOperand(0);
1216  SDValue Op1 = Node->getOperand(1);
1217  SDValue Op2 = Node->getOperand(2);
1218  if (!Op2.getValueType().isVector()) {
1219  SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2);
1220  // The getShiftAmountOperand() may create a new operand node or
1221  // return the existing one. If new operand is created we need
1222  // to update the parent node.
1223  if (SAO != Op2)
1224  NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO);
1225  }
1226  break;
1227  }
1228  }
1229 
1230  if (NewNode != Node) {
1231  ReplaceNode(Node, NewNode);
1232  Node = NewNode;
1233  }
1234  switch (Action) {
1235  case TargetLowering::Legal:
1236  LLVM_DEBUG(dbgs() << "Legal node: nothing to do\n");
1237  return;
1239  LLVM_DEBUG(dbgs() << "Trying custom legalization\n");
1240  // FIXME: The handling for custom lowering with multiple results is
1241  // a complete mess.
1242  if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) {
1243  if (!(Res.getNode() != Node || Res.getResNo() != 0))
1244  return;
1245 
1246  if (Node->getNumValues() == 1) {
1247  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1248  // We can just directly replace this node with the lowered value.
1249  ReplaceNode(SDValue(Node, 0), Res);
1250  return;
1251  }
1252 
1253  SmallVector<SDValue, 8> ResultVals;
1254  for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1255  ResultVals.push_back(Res.getValue(i));
1256  LLVM_DEBUG(dbgs() << "Successfully custom legalized node\n");
1257  ReplaceNode(Node, ResultVals.data());
1258  return;
1259  }
1260  LLVM_DEBUG(dbgs() << "Could not custom legalize node\n");
1263  if (ExpandNode(Node))
1264  return;
1267  ConvertNodeToLibcall(Node);
1268  return;
1270  PromoteNode(Node);
1271  return;
1272  }
1273  }
1274 
1275  switch (Node->getOpcode()) {
1276  default:
1277 #ifndef NDEBUG
1278  dbgs() << "NODE: ";
1279  Node->dump( &DAG);
1280  dbgs() << "\n";
1281 #endif
1282  llvm_unreachable("Do not know how to legalize this operator!");
1283 
1284  case ISD::CALLSEQ_START:
1285  case ISD::CALLSEQ_END:
1286  break;
1287  case ISD::LOAD:
1288  return LegalizeLoadOps(Node);
1289  case ISD::STORE:
1290  return LegalizeStoreOps(Node);
1291  }
1292 }
1293 
1294 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1295  SDValue Vec = Op.getOperand(0);
1296  SDValue Idx = Op.getOperand(1);
1297  SDLoc dl(Op);
1298 
1299  // Before we generate a new store to a temporary stack slot, see if there is
1300  // already one that we can use. There often is because when we scalarize
1301  // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1302  // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1303  // the vector. If all are expanded here, we don't want one store per vector
1304  // element.
1305 
1306  // Caches for hasPredecessorHelper
1309  Visited.insert(Op.getNode());
1310  Worklist.push_back(Idx.getNode());
1311  SDValue StackPtr, Ch;
1312  for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1313  UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1314  SDNode *User = *UI;
1315  if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1316  if (ST->isIndexed() || ST->isTruncatingStore() ||
1317  ST->getValue() != Vec)
1318  continue;
1319 
1320  // Make sure that nothing else could have stored into the destination of
1321  // this store.
1322  if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1323  continue;
1324 
1325  // If the index is dependent on the store we will introduce a cycle when
1326  // creating the load (the load uses the index, and by replacing the chain
1327  // we will make the index dependent on the load). Also, the store might be
1328  // dependent on the extractelement and introduce a cycle when creating
1329  // the load.
1330  if (SDNode::hasPredecessorHelper(ST, Visited, Worklist) ||
1331  ST->hasPredecessor(Op.getNode()))
1332  continue;
1333 
1334  StackPtr = ST->getBasePtr();
1335  Ch = SDValue(ST, 0);
1336  break;
1337  }
1338  }
1339 
1340  EVT VecVT = Vec.getValueType();
1341 
1342  if (!Ch.getNode()) {
1343  // Store the value to a temporary stack slot, then LOAD the returned part.
1344  StackPtr = DAG.CreateStackTemporary(VecVT);
1345  Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1346  MachinePointerInfo());
1347  }
1348 
1349  StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1350 
1351  SDValue NewLoad;
1352 
1353  if (Op.getValueType().isVector())
1354  NewLoad =
1355  DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, MachinePointerInfo());
1356  else
1357  NewLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1359  VecVT.getVectorElementType());
1360 
1361  // Replace the chain going out of the store, by the one out of the load.
1362  DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1363 
1364  // We introduced a cycle though, so update the loads operands, making sure
1365  // to use the original store's chain as an incoming chain.
1366  SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1367  NewLoad->op_end());
1368  NewLoadOperands[0] = Ch;
1369  NewLoad =
1370  SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1371  return NewLoad;
1372 }
1373 
1374 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1375  assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1376 
1377  SDValue Vec = Op.getOperand(0);
1378  SDValue Part = Op.getOperand(1);
1379  SDValue Idx = Op.getOperand(2);
1380  SDLoc dl(Op);
1381 
1382  // Store the value to a temporary stack slot, then LOAD the returned part.
1383  EVT VecVT = Vec.getValueType();
1384  SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1385  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1386  MachinePointerInfo PtrInfo =
1387  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1388 
1389  // First store the whole vector.
1390  SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1391 
1392  // Then store the inserted part.
1393  SDValue SubStackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1394 
1395  // Store the subvector.
1396  Ch = DAG.getStore(Ch, dl, Part, SubStackPtr, MachinePointerInfo());
1397 
1398  // Finally, load the updated vector.
1399  return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo);
1400 }
1401 
1402 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1403  // We can't handle this case efficiently. Allocate a sufficiently
1404  // aligned object on the stack, store each element into it, then load
1405  // the result as a vector.
1406  // Create the stack frame object.
1407  EVT VT = Node->getValueType(0);
1408  EVT EltVT = VT.getVectorElementType();
1409  SDLoc dl(Node);
1410  SDValue FIPtr = DAG.CreateStackTemporary(VT);
1411  int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1412  MachinePointerInfo PtrInfo =
1413  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1414 
1415  // Emit a store of each element to the stack slot.
1416  SmallVector<SDValue, 8> Stores;
1417  unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1418  // Store (in the right endianness) the elements to memory.
1419  for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1420  // Ignore undef elements.
1421  if (Node->getOperand(i).isUndef()) continue;
1422 
1423  unsigned Offset = TypeByteSize*i;
1424 
1425  SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1426  Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1427 
1428  // If the destination vector element type is narrower than the source
1429  // element type, only store the bits necessary.
1430  if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1431  Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1432  Node->getOperand(i), Idx,
1433  PtrInfo.getWithOffset(Offset), EltVT));
1434  } else
1435  Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1436  Idx, PtrInfo.getWithOffset(Offset)));
1437  }
1438 
1439  SDValue StoreChain;
1440  if (!Stores.empty()) // Not all undef elements?
1441  StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1442  else
1443  StoreChain = DAG.getEntryNode();
1444 
1445  // Result is a load from the stack slot.
1446  return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo);
1447 }
1448 
1449 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1450 /// containing the sign bit if the target has no integer value capable of
1451 /// holding all bits of the floating-point value.
1452 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1453  const SDLoc &DL,
1454  SDValue Value) const {
1455  EVT FloatVT = Value.getValueType();
1456  unsigned NumBits = FloatVT.getSizeInBits();
1457  State.FloatVT = FloatVT;
1458  EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1459  // Convert to an integer of the same size.
1460  if (TLI.isTypeLegal(IVT)) {
1461  State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1462  State.SignMask = APInt::getSignMask(NumBits);
1463  State.SignBit = NumBits - 1;
1464  return;
1465  }
1466 
1467  auto &DataLayout = DAG.getDataLayout();
1468  // Store the float to memory, then load the sign part out as an integer.
1469  MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1470  // First create a temporary that is aligned for both the load and store.
1471  SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1472  int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1473  // Then store the float to it.
1474  State.FloatPtr = StackPtr;
1475  MachineFunction &MF = DAG.getMachineFunction();
1476  State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1477  State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1478  State.FloatPointerInfo);
1479 
1480  SDValue IntPtr;
1481  if (DataLayout.isBigEndian()) {
1482  assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1483  // Load out a legal integer with the same sign bit as the float.
1484  IntPtr = StackPtr;
1485  State.IntPointerInfo = State.FloatPointerInfo;
1486  } else {
1487  // Advance the pointer so that the loaded byte will contain the sign bit.
1488  unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1489  IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1490  DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1491  State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1492  ByteOffset);
1493  }
1494 
1495  State.IntPtr = IntPtr;
1496  State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain, IntPtr,
1497  State.IntPointerInfo, MVT::i8);
1498  State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1499  State.SignBit = 7;
1500 }
1501 
1502 /// Replace the integer value produced by getSignAsIntValue() with a new value
1503 /// and cast the result back to a floating-point type.
1504 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1505  const SDLoc &DL,
1506  SDValue NewIntValue) const {
1507  if (!State.Chain)
1508  return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1509 
1510  // Override the part containing the sign bit in the value stored on the stack.
1511  SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1512  State.IntPointerInfo, MVT::i8);
1513  return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1514  State.FloatPointerInfo);
1515 }
1516 
1517 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1518  SDLoc DL(Node);
1519  SDValue Mag = Node->getOperand(0);
1520  SDValue Sign = Node->getOperand(1);
1521 
1522  // Get sign bit into an integer value.
1523  FloatSignAsInt SignAsInt;
1524  getSignAsIntValue(SignAsInt, DL, Sign);
1525 
1526  EVT IntVT = SignAsInt.IntValue.getValueType();
1527  SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1528  SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1529  SignMask);
1530 
1531  // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1532  EVT FloatVT = Mag.getValueType();
1533  if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1534  TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1535  SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1536  SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1537  SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1538  DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1539  return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1540  }
1541 
1542  // Transform Mag value to integer, and clear the sign bit.
1543  FloatSignAsInt MagAsInt;
1544  getSignAsIntValue(MagAsInt, DL, Mag);
1545  EVT MagVT = MagAsInt.IntValue.getValueType();
1546  SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1547  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1548  ClearSignMask);
1549 
1550  // Get the signbit at the right position for MagAsInt.
1551  int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1552  EVT ShiftVT = IntVT;
1553  if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1554  SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1555  ShiftVT = MagVT;
1556  }
1557  if (ShiftAmount > 0) {
1558  SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT);
1559  SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst);
1560  } else if (ShiftAmount < 0) {
1561  SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT);
1562  SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst);
1563  }
1564  if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1565  SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1566  }
1567 
1568  // Store the part with the modified sign and convert back to float.
1569  SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1570  return modifySignAsInt(MagAsInt, DL, CopiedSign);
1571 }
1572 
1573 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1574  SDLoc DL(Node);
1575  SDValue Value = Node->getOperand(0);
1576 
1577  // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1578  EVT FloatVT = Value.getValueType();
1579  if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1580  SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1581  return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1582  }
1583 
1584  // Transform value to integer, clear the sign bit and transform back.
1585  FloatSignAsInt ValueAsInt;
1586  getSignAsIntValue(ValueAsInt, DL, Value);
1587  EVT IntVT = ValueAsInt.IntValue.getValueType();
1588  SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1589  SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1590  ClearSignMask);
1591  return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1592 }
1593 
1594 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1596  unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1597  assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1598  " not tell us which reg is the stack pointer!");
1599  SDLoc dl(Node);
1600  EVT VT = Node->getValueType(0);
1601  SDValue Tmp1 = SDValue(Node, 0);
1602  SDValue Tmp2 = SDValue(Node, 1);
1603  SDValue Tmp3 = Node->getOperand(2);
1604  SDValue Chain = Tmp1.getOperand(0);
1605 
1606  // Chain the dynamic stack allocation so that it doesn't modify the stack
1607  // pointer when other instructions are using the stack.
1608  Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
1609 
1610  SDValue Size = Tmp2.getOperand(1);
1611  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1612  Chain = SP.getValue(1);
1613  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1614  unsigned StackAlign =
1615  DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1616  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1617  if (Align > StackAlign)
1618  Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1619  DAG.getConstant(-(uint64_t)Align, dl, VT));
1620  Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1621 
1622  Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1623  DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1624 
1625  Results.push_back(Tmp1);
1626  Results.push_back(Tmp2);
1627 }
1628 
1629 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1630 /// target.
1631 ///
1632 /// If the SETCC has been legalized using AND / OR, then the legalized node
1633 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1634 /// will be set to false.
1635 ///
1636 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1637 /// then the values of LHS and RHS will be swapped, CC will be set to the
1638 /// new condition, and NeedInvert will be set to false.
1639 ///
1640 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1641 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1642 /// will be set to true. The caller must invert the result of the SETCC with
1643 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1644 /// of a true/false result.
1645 ///
1646 /// \returns true if the SetCC has been legalized, false if it hasn't.
1647 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS,
1648  SDValue &RHS, SDValue &CC,
1649  bool &NeedInvert,
1650  const SDLoc &dl) {
1651  MVT OpVT = LHS.getSimpleValueType();
1652  ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1653  NeedInvert = false;
1654  bool NeedSwap = false;
1655  switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1656  default: llvm_unreachable("Unknown condition code action!");
1657  case TargetLowering::Legal:
1658  // Nothing to do.
1659  break;
1660  case TargetLowering::Expand: {
1662  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1663  std::swap(LHS, RHS);
1664  CC = DAG.getCondCode(InvCC);
1665  return true;
1666  }
1667  // Swapping operands didn't work. Try inverting the condition.
1668  InvCC = getSetCCInverse(CCCode, OpVT.isInteger());
1669  if (!TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1670  // If inverting the condition is not enough, try swapping operands
1671  // on top of it.
1672  InvCC = ISD::getSetCCSwappedOperands(InvCC);
1673  NeedSwap = true;
1674  }
1675  if (TLI.isCondCodeLegalOrCustom(InvCC, OpVT)) {
1676  CC = DAG.getCondCode(InvCC);
1677  NeedInvert = true;
1678  if (NeedSwap)
1679  std::swap(LHS, RHS);
1680  return true;
1681  }
1682 
1684  unsigned Opc = 0;
1685  switch (CCCode) {
1686  default: llvm_unreachable("Don't know how to expand this condition!");
1687  case ISD::SETO:
1688  assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
1689  && "If SETO is expanded, SETOEQ must be legal!");
1690  CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1691  case ISD::SETUO:
1692  assert(TLI.isCondCodeLegal(ISD::SETUNE, OpVT)
1693  && "If SETUO is expanded, SETUNE must be legal!");
1694  CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1695  case ISD::SETOEQ:
1696  case ISD::SETOGT:
1697  case ISD::SETOGE:
1698  case ISD::SETOLT:
1699  case ISD::SETOLE:
1700  case ISD::SETONE:
1701  case ISD::SETUEQ:
1702  case ISD::SETUNE:
1703  case ISD::SETUGT:
1704  case ISD::SETUGE:
1705  case ISD::SETULT:
1706  case ISD::SETULE:
1707  // If we are floating point, assign and break, otherwise fall through.
1708  if (!OpVT.isInteger()) {
1709  // We can use the 4th bit to tell if we are the unordered
1710  // or ordered version of the opcode.
1711  CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1712  Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1713  CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1714  break;
1715  }
1716  // Fallthrough if we are unsigned integer.
1718  case ISD::SETLE:
1719  case ISD::SETGT:
1720  case ISD::SETGE:
1721  case ISD::SETLT:
1722  case ISD::SETNE:
1723  case ISD::SETEQ:
1724  // If all combinations of inverting the condition and swapping operands
1725  // didn't work then we have no means to expand the condition.
1726  llvm_unreachable("Don't know how to expand this condition!");
1727  }
1728 
1729  SDValue SetCC1, SetCC2;
1730  if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1731  // If we aren't the ordered or unorder operation,
1732  // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1733  SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1734  SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1735  } else {
1736  // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1737  SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1738  SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1739  }
1740  LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1741  RHS = SDValue();
1742  CC = SDValue();
1743  return true;
1744  }
1745  }
1746  return false;
1747 }
1748 
1749 /// Emit a store/load combination to the stack. This stores
1750 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1751 /// a load from the stack slot to DestVT, extending it if needed.
1752 /// The resultant code need not be legal.
1753 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1754  EVT DestVT, const SDLoc &dl) {
1755  return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode());
1756 }
1757 
1758 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1759  EVT DestVT, const SDLoc &dl,
1760  SDValue Chain) {
1761  // Create the stack frame object.
1762  unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1763  SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1764  SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1765 
1766  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1767  int SPFI = StackPtrFI->getIndex();
1768  MachinePointerInfo PtrInfo =
1769  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1770 
1771  unsigned SrcSize = SrcOp.getValueSizeInBits();
1772  unsigned SlotSize = SlotVT.getSizeInBits();
1773  unsigned DestSize = DestVT.getSizeInBits();
1774  Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1775  unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1776 
1777  // Emit a store to the stack slot. Use a truncstore if the input value is
1778  // later than DestVT.
1779  SDValue Store;
1780 
1781  if (SrcSize > SlotSize)
1782  Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo,
1783  SlotVT, SrcAlign);
1784  else {
1785  assert(SrcSize == SlotSize && "Invalid store");
1786  Store =
1787  DAG.getStore(Chain, dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
1788  }
1789 
1790  // Result is a load from the stack slot.
1791  if (SlotSize == DestSize)
1792  return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, DestAlign);
1793 
1794  assert(SlotSize < DestSize && "Unknown extension!");
1795  return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, PtrInfo, SlotVT,
1796  DestAlign);
1797 }
1798 
1799 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1800  SDLoc dl(Node);
1801  // Create a vector sized/aligned stack slot, store the value to element #0,
1802  // then load the whole vector back out.
1803  SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1804 
1805  FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1806  int SPFI = StackPtrFI->getIndex();
1807 
1808  SDValue Ch = DAG.getTruncStore(
1809  DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1810  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1811  Node->getValueType(0).getVectorElementType());
1812  return DAG.getLoad(
1813  Node->getValueType(0), dl, Ch, StackPtr,
1814  MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI));
1815 }
1816 
1817 static bool
1819  const TargetLowering &TLI, SDValue &Res) {
1820  unsigned NumElems = Node->getNumOperands();
1821  SDLoc dl(Node);
1822  EVT VT = Node->getValueType(0);
1823 
1824  // Try to group the scalars into pairs, shuffle the pairs together, then
1825  // shuffle the pairs of pairs together, etc. until the vector has
1826  // been built. This will work only if all of the necessary shuffle masks
1827  // are legal.
1828 
1829  // We do this in two phases; first to check the legality of the shuffles,
1830  // and next, assuming that all shuffles are legal, to create the new nodes.
1831  for (int Phase = 0; Phase < 2; ++Phase) {
1833  NewIntermedVals;
1834  for (unsigned i = 0; i < NumElems; ++i) {
1835  SDValue V = Node->getOperand(i);
1836  if (V.isUndef())
1837  continue;
1838 
1839  SDValue Vec;
1840  if (Phase)
1841  Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1842  IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1843  }
1844 
1845  while (IntermedVals.size() > 2) {
1846  NewIntermedVals.clear();
1847  for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1848  // This vector and the next vector are shuffled together (simply to
1849  // append the one to the other).
1850  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1851 
1852  SmallVector<int, 16> FinalIndices;
1853  FinalIndices.reserve(IntermedVals[i].second.size() +
1854  IntermedVals[i+1].second.size());
1855 
1856  int k = 0;
1857  for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1858  ++j, ++k) {
1859  ShuffleVec[k] = j;
1860  FinalIndices.push_back(IntermedVals[i].second[j]);
1861  }
1862  for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1863  ++j, ++k) {
1864  ShuffleVec[k] = NumElems + j;
1865  FinalIndices.push_back(IntermedVals[i+1].second[j]);
1866  }
1867 
1868  SDValue Shuffle;
1869  if (Phase)
1870  Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1871  IntermedVals[i+1].first,
1872  ShuffleVec);
1873  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1874  return false;
1875  NewIntermedVals.push_back(
1876  std::make_pair(Shuffle, std::move(FinalIndices)));
1877  }
1878 
1879  // If we had an odd number of defined values, then append the last
1880  // element to the array of new vectors.
1881  if ((IntermedVals.size() & 1) != 0)
1882  NewIntermedVals.push_back(IntermedVals.back());
1883 
1884  IntermedVals.swap(NewIntermedVals);
1885  }
1886 
1887  assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1888  "Invalid number of intermediate vectors");
1889  SDValue Vec1 = IntermedVals[0].first;
1890  SDValue Vec2;
1891  if (IntermedVals.size() > 1)
1892  Vec2 = IntermedVals[1].first;
1893  else if (Phase)
1894  Vec2 = DAG.getUNDEF(VT);
1895 
1896  SmallVector<int, 16> ShuffleVec(NumElems, -1);
1897  for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1898  ShuffleVec[IntermedVals[0].second[i]] = i;
1899  for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1900  ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1901 
1902  if (Phase)
1903  Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
1904  else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1905  return false;
1906  }
1907 
1908  return true;
1909 }
1910 
1911 /// Expand a BUILD_VECTOR node on targets that don't
1912 /// support the operation, but do support the resultant vector type.
1913 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1914  unsigned NumElems = Node->getNumOperands();
1915  SDValue Value1, Value2;
1916  SDLoc dl(Node);
1917  EVT VT = Node->getValueType(0);
1918  EVT OpVT = Node->getOperand(0).getValueType();
1919  EVT EltVT = VT.getVectorElementType();
1920 
1921  // If the only non-undef value is the low element, turn this into a
1922  // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1923  bool isOnlyLowElement = true;
1924  bool MoreThanTwoValues = false;
1925  bool isConstant = true;
1926  for (unsigned i = 0; i < NumElems; ++i) {
1927  SDValue V = Node->getOperand(i);
1928  if (V.isUndef())
1929  continue;
1930  if (i > 0)
1931  isOnlyLowElement = false;
1932  if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1933  isConstant = false;
1934 
1935  if (!Value1.getNode()) {
1936  Value1 = V;
1937  } else if (!Value2.getNode()) {
1938  if (V != Value1)
1939  Value2 = V;
1940  } else if (V != Value1 && V != Value2) {
1941  MoreThanTwoValues = true;
1942  }
1943  }
1944 
1945  if (!Value1.getNode())
1946  return DAG.getUNDEF(VT);
1947 
1948  if (isOnlyLowElement)
1949  return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1950 
1951  // If all elements are constants, create a load from the constant pool.
1952  if (isConstant) {
1954  for (unsigned i = 0, e = NumElems; i != e; ++i) {
1955  if (ConstantFPSDNode *V =
1956  dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1957  CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1958  } else if (ConstantSDNode *V =
1959  dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1960  if (OpVT==EltVT)
1961  CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1962  else {
1963  // If OpVT and EltVT don't match, EltVT is not legal and the
1964  // element values have been promoted/truncated earlier. Undo this;
1965  // we don't want a v16i8 to become a v16i32 for example.
1966  const ConstantInt *CI = V->getConstantIntValue();
1967  CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1968  CI->getZExtValue()));
1969  }
1970  } else {
1971  assert(Node->getOperand(i).isUndef());
1972  Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1973  CV.push_back(UndefValue::get(OpNTy));
1974  }
1975  }
1976  Constant *CP = ConstantVector::get(CV);
1977  SDValue CPIdx =
1978  DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
1979  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1980  return DAG.getLoad(
1981  VT, dl, DAG.getEntryNode(), CPIdx,
1982  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
1983  Alignment);
1984  }
1985 
1986  SmallSet<SDValue, 16> DefinedValues;
1987  for (unsigned i = 0; i < NumElems; ++i) {
1988  if (Node->getOperand(i).isUndef())
1989  continue;
1990  DefinedValues.insert(Node->getOperand(i));
1991  }
1992 
1993  if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1994  if (!MoreThanTwoValues) {
1995  SmallVector<int, 8> ShuffleVec(NumElems, -1);
1996  for (unsigned i = 0; i < NumElems; ++i) {
1997  SDValue V = Node->getOperand(i);
1998  if (V.isUndef())
1999  continue;
2000  ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2001  }
2002  if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2003  // Get the splatted value into the low element of a vector register.
2004  SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2005  SDValue Vec2;
2006  if (Value2.getNode())
2007  Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2008  else
2009  Vec2 = DAG.getUNDEF(VT);
2010 
2011  // Return shuffle(LowValVec, undef, <0,0,0,0>)
2012  return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec);
2013  }
2014  } else {
2015  SDValue Res;
2016  if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2017  return Res;
2018  }
2019  }
2020 
2021  // Otherwise, we can't handle this case efficiently.
2022  return ExpandVectorBuildThroughStack(Node);
2023 }
2024 
2025 // Expand a node into a call to a libcall. If the result value
2026 // does not fit into a register, return the lo part and set the hi part to the
2027 // by-reg argument. If it does fit into a single register, return the result
2028 // and leave the Hi part unset.
2029 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2030  bool isSigned) {
2032  TargetLowering::ArgListEntry Entry;
2033  for (const SDValue &Op : Node->op_values()) {
2034  EVT ArgVT = Op.getValueType();
2035  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2036  Entry.Node = Op;
2037  Entry.Ty = ArgTy;
2038  Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2039  Entry.IsZExt = !TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2040  Args.push_back(Entry);
2041  }
2042  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2043  TLI.getPointerTy(DAG.getDataLayout()));
2044 
2045  EVT RetVT = Node->getValueType(0);
2046  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2047 
2048  // By default, the input chain to this libcall is the entry node of the
2049  // function. If the libcall is going to be emitted as a tail call then
2050  // TLI.isUsedByReturnOnly will change it to the right chain if the return
2051  // node which is being folded has a non-entry input chain.
2052  SDValue InChain = DAG.getEntryNode();
2053 
2054  // isTailCall may be true since the callee does not reference caller stack
2055  // frame. Check if it's in the right position and that the return types match.
2056  SDValue TCChain = InChain;
2057  const Function &F = DAG.getMachineFunction().getFunction();
2058  bool isTailCall =
2059  TLI.isInTailCallPosition(DAG, Node, TCChain) &&
2060  (RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
2061  if (isTailCall)
2062  InChain = TCChain;
2063 
2065  bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2066  CLI.setDebugLoc(SDLoc(Node))
2067  .setChain(InChain)
2068  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2069  std::move(Args))
2070  .setTailCall(isTailCall)
2071  .setSExtResult(signExtend)
2072  .setZExtResult(!signExtend)
2074 
2075  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2076 
2077  if (!CallInfo.second.getNode()) {
2078  LLVM_DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump());
2079  // It's a tailcall, return the chain (which is the DAG root).
2080  return DAG.getRoot();
2081  }
2082 
2083  LLVM_DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump());
2084  return CallInfo.first;
2085 }
2086 
2087 // Expand a node into a call to a libcall. Similar to
2088 // ExpandLibCall except that the first operand is the in-chain.
2089 std::pair<SDValue, SDValue>
2090 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2091  SDNode *Node,
2092  bool isSigned) {
2093  SDValue InChain = Node->getOperand(0);
2094 
2096  TargetLowering::ArgListEntry Entry;
2097  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2098  EVT ArgVT = Node->getOperand(i).getValueType();
2099  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2100  Entry.Node = Node->getOperand(i);
2101  Entry.Ty = ArgTy;
2102  Entry.IsSExt = isSigned;
2103  Entry.IsZExt = !isSigned;
2104  Args.push_back(Entry);
2105  }
2106  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2107  TLI.getPointerTy(DAG.getDataLayout()));
2108 
2109  Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2110 
2112  CLI.setDebugLoc(SDLoc(Node))
2113  .setChain(InChain)
2114  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2115  std::move(Args))
2116  .setSExtResult(isSigned)
2117  .setZExtResult(!isSigned);
2118 
2119  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2120 
2121  return CallInfo;
2122 }
2123 
2124 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2125  RTLIB::Libcall Call_F32,
2126  RTLIB::Libcall Call_F64,
2127  RTLIB::Libcall Call_F80,
2128  RTLIB::Libcall Call_F128,
2129  RTLIB::Libcall Call_PPCF128) {
2130  if (Node->isStrictFPOpcode())
2131  Node = DAG.mutateStrictFPToFP(Node);
2132 
2133  RTLIB::Libcall LC;
2134  switch (Node->getSimpleValueType(0).SimpleTy) {
2135  default: llvm_unreachable("Unexpected request for libcall!");
2136  case MVT::f32: LC = Call_F32; break;
2137  case MVT::f64: LC = Call_F64; break;
2138  case MVT::f80: LC = Call_F80; break;
2139  case MVT::f128: LC = Call_F128; break;
2140  case MVT::ppcf128: LC = Call_PPCF128; break;
2141  }
2142  return ExpandLibCall(LC, Node, false);
2143 }
2144 
2145 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2146  RTLIB::Libcall Call_I8,
2147  RTLIB::Libcall Call_I16,
2148  RTLIB::Libcall Call_I32,
2149  RTLIB::Libcall Call_I64,
2150  RTLIB::Libcall Call_I128) {
2151  RTLIB::Libcall LC;
2152  switch (Node->getSimpleValueType(0).SimpleTy) {
2153  default: llvm_unreachable("Unexpected request for libcall!");
2154  case MVT::i8: LC = Call_I8; break;
2155  case MVT::i16: LC = Call_I16; break;
2156  case MVT::i32: LC = Call_I32; break;
2157  case MVT::i64: LC = Call_I64; break;
2158  case MVT::i128: LC = Call_I128; break;
2159  }
2160  return ExpandLibCall(LC, Node, isSigned);
2161 }
2162 
2163 /// Expand the node to a libcall based on first argument type (for instance
2164 /// lround and its variant).
2165 SDValue SelectionDAGLegalize::ExpandArgFPLibCall(SDNode* Node,
2166  RTLIB::Libcall Call_F32,
2167  RTLIB::Libcall Call_F64,
2168  RTLIB::Libcall Call_F80,
2169  RTLIB::Libcall Call_F128,
2170  RTLIB::Libcall Call_PPCF128) {
2171  RTLIB::Libcall LC;
2172  switch (Node->getOperand(0).getValueType().getSimpleVT().SimpleTy) {
2173  default: llvm_unreachable("Unexpected request for libcall!");
2174  case MVT::f32: LC = Call_F32; break;
2175  case MVT::f64: LC = Call_F64; break;
2176  case MVT::f80: LC = Call_F80; break;
2177  case MVT::f128: LC = Call_F128; break;
2178  case MVT::ppcf128: LC = Call_PPCF128; break;
2179  }
2180 
2181  return ExpandLibCall(LC, Node, false);
2182 }
2183 
2184 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2185 void
2186 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2187  SmallVectorImpl<SDValue> &Results) {
2188  unsigned Opcode = Node->getOpcode();
2189  bool isSigned = Opcode == ISD::SDIVREM;
2190 
2191  RTLIB::Libcall LC;
2192  switch (Node->getSimpleValueType(0).SimpleTy) {
2193  default: llvm_unreachable("Unexpected request for libcall!");
2194  case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2195  case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2196  case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2197  case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2198  case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2199  }
2200 
2201  // The input chain to this libcall is the entry node of the function.
2202  // Legalizing the call will automatically add the previous call to the
2203  // dependence.
2204  SDValue InChain = DAG.getEntryNode();
2205 
2206  EVT RetVT = Node->getValueType(0);
2207  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2208 
2210  TargetLowering::ArgListEntry Entry;
2211  for (const SDValue &Op : Node->op_values()) {
2212  EVT ArgVT = Op.getValueType();
2213  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2214  Entry.Node = Op;
2215  Entry.Ty = ArgTy;
2216  Entry.IsSExt = isSigned;
2217  Entry.IsZExt = !isSigned;
2218  Args.push_back(Entry);
2219  }
2220 
2221  // Also pass the return address of the remainder.
2222  SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2223  Entry.Node = FIPtr;
2224  Entry.Ty = RetTy->getPointerTo();
2225  Entry.IsSExt = isSigned;
2226  Entry.IsZExt = !isSigned;
2227  Args.push_back(Entry);
2228 
2229  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2230  TLI.getPointerTy(DAG.getDataLayout()));
2231 
2232  SDLoc dl(Node);
2234  CLI.setDebugLoc(dl)
2235  .setChain(InChain)
2236  .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee,
2237  std::move(Args))
2238  .setSExtResult(isSigned)
2239  .setZExtResult(!isSigned);
2240 
2241  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2242 
2243  // Remainder is loaded back from the stack frame.
2244  SDValue Rem =
2245  DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, MachinePointerInfo());
2246  Results.push_back(CallInfo.first);
2247  Results.push_back(Rem);
2248 }
2249 
2250 /// Return true if sincos libcall is available.
2251 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2252  RTLIB::Libcall LC;
2253  switch (Node->getSimpleValueType(0).SimpleTy) {
2254  default: llvm_unreachable("Unexpected request for libcall!");
2255  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2256  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2257  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2258  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2259  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2260  }
2261  return TLI.getLibcallName(LC) != nullptr;
2262 }
2263 
2264 /// Only issue sincos libcall if both sin and cos are needed.
2265 static bool useSinCos(SDNode *Node) {
2266  unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2267  ? ISD::FCOS : ISD::FSIN;
2268 
2269  SDValue Op0 = Node->getOperand(0);
2270  for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2271  UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2272  SDNode *User = *UI;
2273  if (User == Node)
2274  continue;
2275  // The other user might have been turned into sincos already.
2276  if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2277  return true;
2278  }
2279  return false;
2280 }
2281 
2282 /// Issue libcalls to sincos to compute sin / cos pairs.
2283 void
2284 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2285  SmallVectorImpl<SDValue> &Results) {
2286  RTLIB::Libcall LC;
2287  switch (Node->getSimpleValueType(0).SimpleTy) {
2288  default: llvm_unreachable("Unexpected request for libcall!");
2289  case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2290  case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2291  case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2292  case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2293  case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2294  }
2295 
2296  // The input chain to this libcall is the entry node of the function.
2297  // Legalizing the call will automatically add the previous call to the
2298  // dependence.
2299  SDValue InChain = DAG.getEntryNode();
2300 
2301  EVT RetVT = Node->getValueType(0);
2302  Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2303 
2305  TargetLowering::ArgListEntry Entry;
2306 
2307  // Pass the argument.
2308  Entry.Node = Node->getOperand(0);
2309  Entry.Ty = RetTy;
2310  Entry.IsSExt = false;
2311  Entry.IsZExt = false;
2312  Args.push_back(Entry);
2313 
2314  // Pass the return address of sin.
2315  SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2316  Entry.Node = SinPtr;
2317  Entry.Ty = RetTy->getPointerTo();
2318  Entry.IsSExt = false;
2319  Entry.IsZExt = false;
2320  Args.push_back(Entry);
2321 
2322  // Also pass the return address of the cos.
2323  SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2324  Entry.Node = CosPtr;
2325  Entry.Ty = RetTy->getPointerTo();
2326  Entry.IsSExt = false;
2327  Entry.IsZExt = false;
2328  Args.push_back(Entry);
2329 
2330  SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2331  TLI.getPointerTy(DAG.getDataLayout()));
2332 
2333  SDLoc dl(Node);
2335  CLI.setDebugLoc(dl).setChain(InChain).setLibCallee(
2336  TLI.getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()), Callee,
2337  std::move(Args));
2338 
2339  std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2340 
2341  Results.push_back(
2342  DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr, MachinePointerInfo()));
2343  Results.push_back(
2344  DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr, MachinePointerInfo()));
2345 }
2346 
2347 /// This function is responsible for legalizing a
2348 /// INT_TO_FP operation of the specified operand when the target requests that
2349 /// we expand it. At this point, we know that the result and operand types are
2350 /// legal for the target.
2351 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
2352  EVT DestVT,
2353  const SDLoc &dl) {
2354  EVT SrcVT = Op0.getValueType();
2355 
2356  // TODO: Should any fast-math-flags be set for the created nodes?
2357  LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
2358  if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2359  LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
2360  "expansion\n");
2361 
2362  // Get the stack frame index of a 8 byte buffer.
2363  SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2364 
2365  // word offset constant for Hi/Lo address computation
2366  SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2367  StackSlot.getValueType());
2368  // set up Hi and Lo (into buffer) address based on endian
2369  SDValue Hi = StackSlot;
2370  SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2371  StackSlot, WordOff);
2372  if (DAG.getDataLayout().isLittleEndian())
2373  std::swap(Hi, Lo);
2374 
2375  // if signed map to unsigned space
2376  SDValue Op0Mapped;
2377  if (isSigned) {
2378  // constant used to invert sign bit (signed to unsigned mapping)
2379  SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2380  Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2381  } else {
2382  Op0Mapped = Op0;
2383  }
2384  // store the lo of the constructed double - based on integer input
2385  SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo,
2386  MachinePointerInfo());
2387  // initial hi portion of constructed double
2388  SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2389  // store the hi of the constructed double - biased exponent
2390  SDValue Store2 =
2391  DAG.getStore(Store1, dl, InitialHi, Hi, MachinePointerInfo());
2392  // load the constructed double
2393  SDValue Load =
2394  DAG.getLoad(MVT::f64, dl, Store2, StackSlot, MachinePointerInfo());
2395  // FP constant to bias correct the final result
2396  SDValue Bias = DAG.getConstantFP(isSigned ?
2397  BitsToDouble(0x4330000080000000ULL) :
2398  BitsToDouble(0x4330000000000000ULL),
2399  dl, MVT::f64);
2400  // subtract the bias
2401  SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2402  // final result
2403  SDValue Result = DAG.getFPExtendOrRound(Sub, dl, DestVT);
2404  return Result;
2405  }
2406  assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2407  // Code below here assumes !isSigned without checking again.
2408 
2409  SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2410 
2411  SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
2412  DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
2413  SDValue Zero = DAG.getIntPtrConstant(0, dl),
2414  Four = DAG.getIntPtrConstant(4, dl);
2415  SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2416  SignSet, Four, Zero);
2417 
2418  // If the sign bit of the integer is set, the large number will be treated
2419  // as a negative number. To counteract this, the dynamic code adds an
2420  // offset depending on the data type.
2421  uint64_t FF;
2422  switch (SrcVT.getSimpleVT().SimpleTy) {
2423  default: llvm_unreachable("Unsupported integer type!");
2424  case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2425  case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2426  case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2427  case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2428  }
2429  if (DAG.getDataLayout().isLittleEndian())
2430  FF <<= 32;
2431  Constant *FudgeFactor = ConstantInt::get(
2432  Type::getInt64Ty(*DAG.getContext()), FF);
2433 
2434  SDValue CPIdx =
2435  DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2436  unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2437  CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2438  Alignment = std::min(Alignment, 4u);
2439  SDValue FudgeInReg;
2440  if (DestVT == MVT::f32)
2441  FudgeInReg = DAG.getLoad(
2442  MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2443  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2444  Alignment);
2445  else {
2446  SDValue Load = DAG.getExtLoad(
2447  ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2448  MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2449  Alignment);
2450  HandleSDNode Handle(Load);
2451  LegalizeOp(Load.getNode());
2452  FudgeInReg = Handle.getValue();
2453  }
2454 
2455  return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2456 }
2457 
2458 /// This function is responsible for legalizing a
2459 /// *INT_TO_FP operation of the specified operand when the target requests that
2460 /// we promote it. At this point, we know that the result and operand types are
2461 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2462 /// operation that takes a larger input.
2463 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT,
2464  bool isSigned,
2465  const SDLoc &dl) {
2466  // First step, figure out the appropriate *INT_TO_FP operation to use.
2467  EVT NewInTy = LegalOp.getValueType();
2468 
2469  unsigned OpToUse = 0;
2470 
2471  // Scan for the appropriate larger type to use.
2472  while (true) {
2473  NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2474  assert(NewInTy.isInteger() && "Ran out of possibilities!");
2475 
2476  // If the target supports SINT_TO_FP of this type, use it.
2477  if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2478  OpToUse = ISD::SINT_TO_FP;
2479  break;
2480  }
2481  if (isSigned) continue;
2482 
2483  // If the target supports UINT_TO_FP of this type, use it.
2484  if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2485  OpToUse = ISD::UINT_TO_FP;
2486  break;
2487  }
2488 
2489  // Otherwise, try a larger type.
2490  }
2491 
2492  // Okay, we found the operation and type to use. Zero extend our input to the
2493  // desired type then run the operation on it.
2494  return DAG.getNode(OpToUse, dl, DestVT,
2495  DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2496  dl, NewInTy, LegalOp));
2497 }
2498 
2499 /// This function is responsible for legalizing a
2500 /// FP_TO_*INT operation of the specified operand when the target requests that
2501 /// we promote it. At this point, we know that the result and operand types are
2502 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2503 /// operation that returns a larger result.
2504 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT,
2505  bool isSigned,
2506  const SDLoc &dl) {
2507  // First step, figure out the appropriate FP_TO*INT operation to use.
2508  EVT NewOutTy = DestVT;
2509 
2510  unsigned OpToUse = 0;
2511 
2512  // Scan for the appropriate larger type to use.
2513  while (true) {
2514  NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2515  assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2516 
2517  // A larger signed type can hold all unsigned values of the requested type,
2518  // so using FP_TO_SINT is valid
2519  if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2520  OpToUse = ISD::FP_TO_SINT;
2521  break;
2522  }
2523 
2524  // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2525  if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2526  OpToUse = ISD::FP_TO_UINT;
2527  break;
2528  }
2529 
2530  // Otherwise, try a larger type.
2531  }
2532 
2533  // Okay, we found the operation and type to use.
2534  SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2535 
2536  // Truncate the result of the extended FP_TO_*INT operation to the desired
2537  // size.
2538  return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2539 }
2540 
2541 /// Legalize a BITREVERSE scalar/vector operation as a series of mask + shifts.
2542 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, const SDLoc &dl) {
2543  EVT VT = Op.getValueType();
2544  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2545  unsigned Sz = VT.getScalarSizeInBits();
2546 
2547  SDValue Tmp, Tmp2, Tmp3;
2548 
2549  // If we can, perform BSWAP first and then the mask+swap the i4, then i2
2550  // and finally the i1 pairs.
2551  // TODO: We can easily support i4/i2 legal types if any target ever does.
2552  if (Sz >= 8 && isPowerOf2_32(Sz)) {
2553  // Create the masks - repeating the pattern every byte.
2554  APInt MaskHi4 = APInt::getSplat(Sz, APInt(8, 0xF0));
2555  APInt MaskHi2 = APInt::getSplat(Sz, APInt(8, 0xCC));
2556  APInt MaskHi1 = APInt::getSplat(Sz, APInt(8, 0xAA));
2557  APInt MaskLo4 = APInt::getSplat(Sz, APInt(8, 0x0F));
2558  APInt MaskLo2 = APInt::getSplat(Sz, APInt(8, 0x33));
2559  APInt MaskLo1 = APInt::getSplat(Sz, APInt(8, 0x55));
2560 
2561  // BSWAP if the type is wider than a single byte.
2562  Tmp = (Sz > 8 ? DAG.getNode(ISD::BSWAP, dl, VT, Op) : Op);
2563 
2564  // swap i4: ((V & 0xF0) >> 4) | ((V & 0x0F) << 4)
2565  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi4, dl, VT));
2566  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo4, dl, VT));
2567  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(4, dl, SHVT));
2568  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(4, dl, SHVT));
2569  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2570 
2571  // swap i2: ((V & 0xCC) >> 2) | ((V & 0x33) << 2)
2572  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi2, dl, VT));
2573  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo2, dl, VT));
2574  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(2, dl, SHVT));
2575  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(2, dl, SHVT));
2576  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2577 
2578  // swap i1: ((V & 0xAA) >> 1) | ((V & 0x55) << 1)
2579  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskHi1, dl, VT));
2580  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp, DAG.getConstant(MaskLo1, dl, VT));
2581  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Tmp2, DAG.getConstant(1, dl, SHVT));
2582  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Tmp3, DAG.getConstant(1, dl, SHVT));
2583  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
2584  return Tmp;
2585  }
2586 
2587  Tmp = DAG.getConstant(0, dl, VT);
2588  for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2589  if (I < J)
2590  Tmp2 =
2591  DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2592  else
2593  Tmp2 =
2594  DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2595 
2596  APInt Shift(Sz, 1);
2597  Shift <<= J;
2598  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2599  Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2600  }
2601 
2602  return Tmp;
2603 }
2604 
2605 /// Open code the operations for BSWAP of the specified operation.
2606 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, const SDLoc &dl) {
2607  EVT VT = Op.getValueType();
2608  EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2609  SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2610  switch (VT.getSimpleVT().getScalarType().SimpleTy) {
2611  default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2612  case MVT::i16:
2613  // Use a rotate by 8. This can be further expanded if necessary.
2614  return DAG.getNode(ISD::ROTL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2615  case MVT::i32:
2616  Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2617  Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2618  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2619  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2620  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2621  DAG.getConstant(0xFF0000, dl, VT));
2622  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2623  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2624  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2625  return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2626  case MVT::i64:
2627  Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2628  Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2629  Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2630  Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2631  Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2632  Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2633  Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2634  Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2635  Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2636  DAG.getConstant(255ULL<<48, dl, VT));
2637  Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2638  DAG.getConstant(255ULL<<40, dl, VT));
2639  Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2640  DAG.getConstant(255ULL<<32, dl, VT));
2641  Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2642  DAG.getConstant(255ULL<<24, dl, VT));
2643  Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2644  DAG.getConstant(255ULL<<16, dl, VT));
2645  Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2646  DAG.getConstant(255ULL<<8 , dl, VT));
2647  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2648  Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2649  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2650  Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2651  Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2652  Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2653  return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2654  }
2655 }
2656 
2657 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2658  LLVM_DEBUG(dbgs() << "Trying to expand node\n");
2660  SDLoc dl(Node);
2661  SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2662  bool NeedInvert;
2663  switch (Node->getOpcode()) {
2664  case ISD::ABS:
2665  if (TLI.expandABS(Node, Tmp1, DAG))
2666  Results.push_back(Tmp1);
2667  break;
2668  case ISD::CTPOP:
2669  if (TLI.expandCTPOP(Node, Tmp1, DAG))
2670  Results.push_back(Tmp1);
2671  break;
2672  case ISD::CTLZ:
2673  case ISD::CTLZ_ZERO_UNDEF:
2674  if (TLI.expandCTLZ(Node, Tmp1, DAG))
2675  Results.push_back(Tmp1);
2676  break;
2677  case ISD::CTTZ:
2678  case ISD::CTTZ_ZERO_UNDEF:
2679  if (TLI.expandCTTZ(Node, Tmp1, DAG))
2680  Results.push_back(Tmp1);
2681  break;
2682  case ISD::BITREVERSE:
2683  Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
2684  break;
2685  case ISD::BSWAP:
2686  Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2687  break;
2688  case ISD::FRAMEADDR:
2689  case ISD::RETURNADDR:
2691  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2692  break;
2693  case ISD::EH_DWARF_CFA: {
2694  SDValue CfaArg = DAG.getSExtOrTrunc(Node->getOperand(0), dl,
2695  TLI.getPointerTy(DAG.getDataLayout()));
2696  SDValue Offset = DAG.getNode(ISD::ADD, dl,
2697  CfaArg.getValueType(),
2698  DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
2699  CfaArg.getValueType()),
2700  CfaArg);
2701  SDValue FA = DAG.getNode(
2702  ISD::FRAMEADDR, dl, TLI.getPointerTy(DAG.getDataLayout()),
2703  DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout())));
2704  Results.push_back(DAG.getNode(ISD::ADD, dl, FA.getValueType(),
2705  FA, Offset));
2706  break;
2707  }
2708  case ISD::FLT_ROUNDS_:
2709  Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2710  break;
2711  case ISD::EH_RETURN:
2712  case ISD::EH_LABEL:
2713  case ISD::PREFETCH:
2714  case ISD::VAEND:
2715  case ISD::EH_SJLJ_LONGJMP:
2716  // If the target didn't expand these, there's nothing to do, so just
2717  // preserve the chain and be done.
2718  Results.push_back(Node->getOperand(0));
2719  break;
2720  case ISD::READCYCLECOUNTER:
2721  // If the target didn't expand this, just return 'zero' and preserve the
2722  // chain.
2723  Results.append(Node->getNumValues() - 1,
2724  DAG.getConstant(0, dl, Node->getValueType(0)));
2725  Results.push_back(Node->getOperand(0));
2726  break;
2727  case ISD::EH_SJLJ_SETJMP:
2728  // If the target didn't expand this, just return 'zero' and preserve the
2729  // chain.
2730  Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2731  Results.push_back(Node->getOperand(0));
2732  break;
2733  case ISD::ATOMIC_LOAD: {
2734  // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2735  SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2736  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2737  SDValue Swap = DAG.getAtomicCmpSwap(
2738  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2739  Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2740  cast<AtomicSDNode>(Node)->getMemOperand());
2741  Results.push_back(Swap.getValue(0));
2742  Results.push_back(Swap.getValue(1));
2743  break;
2744  }
2745  case ISD::ATOMIC_STORE: {
2746  // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2747  SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2748  cast<AtomicSDNode>(Node)->getMemoryVT(),
2749  Node->getOperand(0),
2750  Node->getOperand(1), Node->getOperand(2),
2751  cast<AtomicSDNode>(Node)->getMemOperand());
2752  Results.push_back(Swap.getValue(1));
2753  break;
2754  }
2756  // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2757  // splits out the success value as a comparison. Expanding the resulting
2758  // ATOMIC_CMP_SWAP will produce a libcall.
2759  SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2760  SDValue Res = DAG.getAtomicCmpSwap(
2761  ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2762  Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2763  Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand());
2764 
2765  SDValue ExtRes = Res;
2766  SDValue LHS = Res;
2767  SDValue RHS = Node->getOperand(1);
2768 
2769  EVT AtomicType = cast<AtomicSDNode>(Node)->getMemoryVT();
2770  EVT OuterType = Node->getValueType(0);
2771  switch (TLI.getExtendForAtomicOps()) {
2772  case ISD::SIGN_EXTEND:
2773  LHS = DAG.getNode(ISD::AssertSext, dl, OuterType, Res,
2774  DAG.getValueType(AtomicType));
2775  RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, OuterType,
2776  Node->getOperand(2), DAG.getValueType(AtomicType));
2777  ExtRes = LHS;
2778  break;
2779  case ISD::ZERO_EXTEND:
2780  LHS = DAG.getNode(ISD::AssertZext, dl, OuterType, Res,
2781  DAG.getValueType(AtomicType));
2782  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2783  ExtRes = LHS;
2784  break;
2785  case ISD::ANY_EXTEND:
2786  LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType);
2787  RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType);
2788  break;
2789  default:
2790  llvm_unreachable("Invalid atomic op extension");
2791  }
2792 
2793  SDValue Success =
2794  DAG.getSetCC(dl, Node->getValueType(1), LHS, RHS, ISD::SETEQ);
2795 
2796  Results.push_back(ExtRes.getValue(0));
2797  Results.push_back(Success);
2798  Results.push_back(Res.getValue(1));
2799  break;
2800  }
2802  ExpandDYNAMIC_STACKALLOC(Node, Results);
2803  break;
2804  case ISD::MERGE_VALUES:
2805  for (unsigned i = 0; i < Node->getNumValues(); i++)
2806  Results.push_back(Node->getOperand(i));
2807  break;
2808  case ISD::UNDEF: {
2809  EVT VT = Node->getValueType(0);
2810  if (VT.isInteger())
2811  Results.push_back(DAG.getConstant(0, dl, VT));
2812  else {
2813  assert(VT.isFloatingPoint() && "Unknown value type!");
2814  Results.push_back(DAG.getConstantFP(0, dl, VT));
2815  }
2816  break;
2817  }
2818  case ISD::STRICT_FP_ROUND:
2819  Tmp1 = EmitStackConvert(Node->getOperand(1),
2820  Node->getValueType(0),
2821  Node->getValueType(0), dl, Node->getOperand(0));
2822  ReplaceNode(Node, Tmp1.getNode());
2823  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_ROUND node\n");
2824  return true;
2825  case ISD::FP_ROUND:
2826  case ISD::BITCAST:
2827  Tmp1 = EmitStackConvert(Node->getOperand(0),
2828  Node->getValueType(0),
2829  Node->getValueType(0), dl);
2830  Results.push_back(Tmp1);
2831  break;
2832  case ISD::STRICT_FP_EXTEND:
2833  Tmp1 = EmitStackConvert(Node->getOperand(1),
2834  Node->getOperand(1).getValueType(),
2835  Node->getValueType(0), dl, Node->getOperand(0));
2836  ReplaceNode(Node, Tmp1.getNode());
2837  LLVM_DEBUG(dbgs() << "Successfully expanded STRICT_FP_EXTEND node\n");
2838  return true;
2839  case ISD::FP_EXTEND:
2840  Tmp1 = EmitStackConvert(Node->getOperand(0),
2841  Node->getOperand(0).getValueType(),
2842  Node->getValueType(0), dl);
2843  Results.push_back(Tmp1);
2844  break;
2845  case ISD::SIGN_EXTEND_INREG: {
2846  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2847  EVT VT = Node->getValueType(0);
2848 
2849  // An in-register sign-extend of a boolean is a negation:
2850  // 'true' (1) sign-extended is -1.
2851  // 'false' (0) sign-extended is 0.
2852  // However, we must mask the high bits of the source operand because the
2853  // SIGN_EXTEND_INREG does not guarantee that the high bits are already zero.
2854 
2855  // TODO: Do this for vectors too?
2856  if (ExtraVT.getSizeInBits() == 1) {
2857  SDValue One = DAG.getConstant(1, dl, VT);
2858  SDValue And = DAG.getNode(ISD::AND, dl, VT, Node->getOperand(0), One);
2859  SDValue Zero = DAG.getConstant(0, dl, VT);
2860  SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, Zero, And);
2861  Results.push_back(Neg);
2862  break;
2863  }
2864 
2865  // NOTE: we could fall back on load/store here too for targets without
2866  // SRA. However, it is doubtful that any exist.
2867  EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2868  unsigned BitsDiff = VT.getScalarSizeInBits() -
2869  ExtraVT.getScalarSizeInBits();
2870  SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
2871  Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2872  Node->getOperand(0), ShiftCst);
2873  Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2874  Results.push_back(Tmp1);
2875  break;
2876  }
2877  case ISD::FP_ROUND_INREG: {
2878  // The only way we can lower this is to turn it into a TRUNCSTORE,
2879  // EXTLOAD pair, targeting a temporary location (a stack slot).
2880 
2881  // NOTE: there is a choice here between constantly creating new stack
2882  // slots and always reusing the same one. We currently always create
2883  // new ones, as reuse may inhibit scheduling.
2884  EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2885  Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2886  Node->getValueType(0), dl);
2887  Results.push_back(Tmp1);
2888  break;
2889  }
2890  case ISD::UINT_TO_FP:
2891  if (TLI.expandUINT_TO_FP(Node, Tmp1, DAG)) {
2892  Results.push_back(Tmp1);
2893  break;
2894  }
2896  case ISD::SINT_TO_FP:
2897  Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2898  Node->getOperand(0), Node->getValueType(0), dl);
2899  Results.push_back(Tmp1);
2900  break;
2901  case ISD::FP_TO_SINT:
2902  if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
2903  Results.push_back(Tmp1);
2904  break;
2905  case ISD::FP_TO_UINT:
2906  if (TLI.expandFP_TO_UINT(Node, Tmp1, DAG))
2907  Results.push_back(Tmp1);
2908  break;
2909  case ISD::LROUND:
2910  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LROUND_F32,
2911  RTLIB::LROUND_F64, RTLIB::LROUND_F80,
2912  RTLIB::LROUND_F128,
2913  RTLIB::LROUND_PPCF128));
2914  break;
2915  case ISD::LLROUND:
2916  Results.push_back(ExpandArgFPLibCall(Node, RTLIB::LLROUND_F32,
2917  RTLIB::LLROUND_F64, RTLIB::LLROUND_F80,
2918  RTLIB::LLROUND_F128,
2919  RTLIB::LLROUND_PPCF128));
2920  break;
2921  case ISD::VAARG:
2922  Results.push_back(DAG.expandVAArg(Node));
2923  Results.push_back(Results[0].getValue(1));
2924  break;
2925  case ISD::VACOPY:
2926  Results.push_back(DAG.expandVACopy(Node));
2927  break;
2929  if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2930  // This must be an access of the only element. Return it.
2931  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2932  Node->getOperand(0));
2933  else
2934  Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2935  Results.push_back(Tmp1);
2936  break;
2938  Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2939  break;
2940  case ISD::INSERT_SUBVECTOR:
2941  Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2942  break;
2943  case ISD::CONCAT_VECTORS:
2944  Results.push_back(ExpandVectorBuildThroughStack(Node));
2945  break;
2946  case ISD::SCALAR_TO_VECTOR:
2947  Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2948  break;
2950  Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2951  Node->getOperand(1),
2952  Node->getOperand(2), dl));
2953  break;
2954  case ISD::VECTOR_SHUFFLE: {
2955  SmallVector<int, 32> NewMask;
2956  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
2957 
2958  EVT VT = Node->getValueType(0);
2959  EVT EltVT = VT.getVectorElementType();
2960  SDValue Op0 = Node->getOperand(0);
2961  SDValue Op1 = Node->getOperand(1);
2962  if (!TLI.isTypeLegal(EltVT)) {
2963  EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2964 
2965  // BUILD_VECTOR operands are allowed to be wider than the element type.
2966  // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
2967  // it.
2968  if (NewEltVT.bitsLT(EltVT)) {
2969  // Convert shuffle node.
2970  // If original node was v4i64 and the new EltVT is i32,
2971  // cast operands to v8i32 and re-build the mask.
2972 
2973  // Calculate new VT, the size of the new VT should be equal to original.
2974  EVT NewVT =
2975  EVT::getVectorVT(*DAG.getContext(), NewEltVT,
2976  VT.getSizeInBits() / NewEltVT.getSizeInBits());
2977  assert(NewVT.bitsEq(VT));
2978 
2979  // cast operands to new VT
2980  Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
2981  Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
2982 
2983  // Convert the shuffle mask
2984  unsigned int factor =
2986 
2987  // EltVT gets smaller
2988  assert(factor > 0);
2989 
2990  for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
2991  if (Mask[i] < 0) {
2992  for (unsigned fi = 0; fi < factor; ++fi)
2993  NewMask.push_back(Mask[i]);
2994  }
2995  else {
2996  for (unsigned fi = 0; fi < factor; ++fi)
2997  NewMask.push_back(Mask[i]*factor+fi);
2998  }
2999  }
3000  Mask = NewMask;
3001  VT = NewVT;
3002  }
3003  EltVT = NewEltVT;
3004  }
3005  unsigned NumElems = VT.getVectorNumElements();
3007  for (unsigned i = 0; i != NumElems; ++i) {
3008  if (Mask[i] < 0) {
3009  Ops.push_back(DAG.getUNDEF(EltVT));
3010  continue;
3011  }
3012  unsigned Idx = Mask[i];
3013  if (Idx < NumElems)
3014  Ops.push_back(DAG.getNode(
3015  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3016  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3017  else
3018  Ops.push_back(DAG.getNode(
3019  ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3020  DAG.getConstant(Idx - NumElems, dl,
3021  TLI.getVectorIdxTy(DAG.getDataLayout()))));
3022  }
3023 
3024  Tmp1 = DAG.getBuildVector(VT, dl, Ops);
3025  // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3026  Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3027  Results.push_back(Tmp1);
3028  break;
3029  }
3030  case ISD::EXTRACT_ELEMENT: {
3031  EVT OpTy = Node->getOperand(0).getValueType();
3032  if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3033  // 1 -> Hi
3034  Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3035  DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3036  TLI.getShiftAmountTy(
3037  Node->getOperand(0).getValueType(),
3038  DAG.getDataLayout())));
3039  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3040  } else {
3041  // 0 -> Lo
3042  Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3043  Node->getOperand(0));
3044  }
3045  Results.push_back(Tmp1);
3046  break;
3047  }
3048  case ISD::STACKSAVE:
3049  // Expand to CopyFromReg if the target set
3050  // StackPointerRegisterToSaveRestore.
3051  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3052  Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3053  Node->getValueType(0)));
3054  Results.push_back(Results[0].getValue(1));
3055  } else {
3056  Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3057  Results.push_back(Node->getOperand(0));
3058  }
3059  break;
3060  case ISD::STACKRESTORE:
3061  // Expand to CopyToReg if the target set
3062  // StackPointerRegisterToSaveRestore.
3063  if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3064  Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3065  Node->getOperand(1)));
3066  } else {
3067  Results.push_back(Node->getOperand(0));
3068  }
3069  break;
3071  Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3072  Results.push_back(Results[0].getValue(0));
3073  break;
3074  case ISD::FCOPYSIGN:
3075  Results.push_back(ExpandFCOPYSIGN(Node));
3076  break;
3077  case ISD::FNEG:
3078  // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3079  Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3080  // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3081  Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3082  Node->getOperand(0));
3083  Results.push_back(Tmp1);
3084  break;
3085  case ISD::FABS:
3086  Results.push_back(ExpandFABS(Node));
3087  break;
3088  case ISD::SMIN:
3089  case ISD::SMAX:
3090  case ISD::UMIN:
3091  case ISD::UMAX: {
3092  // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3093  ISD::CondCode Pred;
3094  switch (Node->getOpcode()) {
3095  default: llvm_unreachable("How did we get here?");
3096  case ISD::SMAX: Pred = ISD::SETGT; break;
3097  case ISD::SMIN: Pred = ISD::SETLT; break;
3098  case ISD::UMAX: Pred = ISD::SETUGT; break;
3099  case ISD::UMIN: Pred = ISD::SETULT; break;
3100  }
3101  Tmp1 = Node->getOperand(0);
3102  Tmp2 = Node->getOperand(1);
3103  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3104  Results.push_back(Tmp1);
3105  break;
3106  }
3107  case ISD::FMINNUM:
3108  case ISD::FMAXNUM: {
3109  if (SDValue Expanded = TLI.expandFMINNUM_FMAXNUM(Node, DAG))
3110  Results.push_back(Expanded);
3111  break;
3112  }
3113  case ISD::FSIN:
3114  case ISD::FCOS: {
3115  EVT VT = Node->getValueType(0);
3116  // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3117  // fcos which share the same operand and both are used.
3118  if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3119  isSinCosLibcallAvailable(Node, TLI))
3120  && useSinCos(Node)) {
3121  SDVTList VTs = DAG.getVTList(VT, VT);
3122  Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3123  if (Node->getOpcode() == ISD::FCOS)
3124  Tmp1 = Tmp1.getValue(1);
3125  Results.push_back(Tmp1);
3126  }
3127  break;
3128  }
3129  case ISD::FMAD:
3130  llvm_unreachable("Illegal fmad should never be formed");
3131 
3132  case ISD::FP16_TO_FP:
3133  if (Node->getValueType(0) != MVT::f32) {
3134  // We can extend to types bigger than f32 in two steps without changing
3135  // the result. Since "f16 -> f32" is much more commonly available, give
3136  // CodeGen the option of emitting that before resorting to a libcall.
3137  SDValue Res =
3138  DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3139  Results.push_back(
3140  DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3141  }
3142  break;
3143  case ISD::FP_TO_FP16:
3144  LLVM_DEBUG(dbgs() << "Legalizing FP_TO_FP16\n");
3145  if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3146  SDValue Op = Node->getOperand(0);
3147  MVT SVT = Op.getSimpleValueType();
3148  if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3149  TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3150  // Under fastmath, we can expand this node into a fround followed by
3151  // a float-half conversion.
3152  SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3153  DAG.getIntPtrConstant(0, dl));
3154  Results.push_back(
3155  DAG.getNode(ISD::FP_TO_FP16, dl, Node->getValueType(0), FloatVal));
3156  }
3157  }
3158  break;
3159  case ISD::ConstantFP: {
3160  ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3161  // Check to see if this FP immediate is already legal.
3162  // If this is a legal constant, turn it into a TargetConstantFP node.
3163  if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0),
3164  DAG.getMachineFunction().getFunction().hasOptSize()))
3165  Results.push_back(ExpandConstantFP(CFP, true));
3166  break;
3167  }
3168  case ISD::Constant: {
3169  ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3170  Results.push_back(ExpandConstant(CP));
3171  break;
3172  }
3173  case ISD::FSUB: {
3174  EVT VT = Node->getValueType(0);
3175  if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3176  TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3177  const SDNodeFlags Flags = Node->getFlags();
3178  Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3179  Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3180  Results.push_back(Tmp1);
3181  }
3182  break;
3183  }
3184  case ISD::SUB: {
3185  EVT VT = Node->getValueType(0);
3186  assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3187  TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3188  "Don't know how to expand this subtraction!");
3189  Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3190  DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3191  VT));
3192  Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3193  Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3194  break;
3195  }
3196  case ISD::UREM:
3197  case ISD::SREM: {
3198  EVT VT = Node->getValueType(0);
3199  bool isSigned = Node->getOpcode() == ISD::SREM;
3200  unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3201  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3202  Tmp2 = Node->getOperand(0);
3203  Tmp3 = Node->getOperand(1);
3204  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3205  SDVTList VTs = DAG.getVTList(VT, VT);
3206  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3207  Results.push_back(Tmp1);
3208  } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3209  // X % Y -> X-X/Y*Y
3210  Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3211  Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3212  Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3213  Results.push_back(Tmp1);
3214  }
3215  break;
3216  }
3217  case ISD::UDIV:
3218  case ISD::SDIV: {
3219  bool isSigned = Node->getOpcode() == ISD::SDIV;
3220  unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3221  EVT VT = Node->getValueType(0);
3222  if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3223  SDVTList VTs = DAG.getVTList(VT, VT);
3224  Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3225  Node->getOperand(1));
3226  Results.push_back(Tmp1);
3227  }
3228  break;
3229  }
3230  case ISD::MULHU:
3231  case ISD::MULHS: {
3232  unsigned ExpandOpcode =
3234  EVT VT = Node->getValueType(0);
3235  SDVTList VTs = DAG.getVTList(VT, VT);
3236 
3237  Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3238  Node->getOperand(1));
3239  Results.push_back(Tmp1.getValue(1));
3240  break;
3241  }
3242  case ISD::UMUL_LOHI:
3243  case ISD::SMUL_LOHI: {
3244  SDValue LHS = Node->getOperand(0);
3245  SDValue RHS = Node->getOperand(1);
3246  MVT VT = LHS.getSimpleValueType();
3247  unsigned MULHOpcode =
3249 
3250  if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) {
3251  Results.push_back(DAG.getNode(ISD::MUL, dl, VT, LHS, RHS));
3252  Results.push_back(DAG.getNode(MULHOpcode, dl, VT, LHS, RHS));
3253  break;
3254  }
3255 
3256  SmallVector<SDValue, 4> Halves;
3257  EVT HalfType = EVT(VT).getHalfSizedIntegerVT(*DAG.getContext());
3258  assert(TLI.isTypeLegal(HalfType));
3259  if (TLI.expandMUL_LOHI(Node->getOpcode(), VT, Node, LHS, RHS, Halves,
3260  HalfType, DAG,
3262  for (unsigned i = 0; i < 2; ++i) {
3263  SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Halves[2 * i]);
3264  SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]);
3265  SDValue Shift = DAG.getConstant(
3266  HalfType.getScalarSizeInBits(), dl,
3267  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3268  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3269  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3270  }
3271  break;
3272  }
3273  break;
3274  }
3275  case ISD::MUL: {
3276  EVT VT = Node->getValueType(0);
3277  SDVTList VTs = DAG.getVTList(VT, VT);
3278  // See if multiply or divide can be lowered using two-result operations.
3279  // We just need the low half of the multiply; try both the signed
3280  // and unsigned forms. If the target supports both SMUL_LOHI and
3281  // UMUL_LOHI, form a preference by checking which forms of plain
3282  // MULH it supports.
3283  bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3284  bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3285  bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3286  bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3287  unsigned OpToUse = 0;
3288  if (HasSMUL_LOHI && !HasMULHS) {
3289  OpToUse = ISD::SMUL_LOHI;
3290  } else if (HasUMUL_LOHI && !HasMULHU) {
3291  OpToUse = ISD::UMUL_LOHI;
3292  } else if (HasSMUL_LOHI) {
3293  OpToUse = ISD::SMUL_LOHI;
3294  } else if (HasUMUL_LOHI) {
3295  OpToUse = ISD::UMUL_LOHI;
3296  }
3297  if (OpToUse) {
3298  Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3299  Node->getOperand(1)));
3300  break;
3301  }
3302 
3303  SDValue Lo, Hi;
3304  EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3305  if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3306  TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3307  TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3308  TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3309  TLI.expandMUL(Node, Lo, Hi, HalfType, DAG,
3311  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3312  Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3313  SDValue Shift =
3314  DAG.getConstant(HalfType.getSizeInBits(), dl,
3315  TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3316  Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3317  Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3318  }
3319  break;
3320  }
3321  case ISD::FSHL:
3322  case ISD::FSHR:
3323  if (TLI.expandFunnelShift(Node, Tmp1, DAG))
3324  Results.push_back(Tmp1);
3325  break;
3326  case ISD::ROTL:
3327  case ISD::ROTR:
3328  if (TLI.expandROT(Node, Tmp1, DAG))
3329  Results.push_back(Tmp1);
3330  break;
3331  case ISD::SADDSAT:
3332  case ISD::UADDSAT:
3333  case ISD::SSUBSAT:
3334  case ISD::USUBSAT:
3335  Results.push_back(TLI.expandAddSubSat(Node, DAG));
3336  break;
3337  case ISD::SMULFIX:
3338  case ISD::SMULFIXSAT:
3339  case ISD::UMULFIX:
3340  Results.push_back(TLI.expandFixedPointMul(Node, DAG));
3341  break;
3342  case ISD::ADDCARRY:
3343  case ISD::SUBCARRY: {
3344  SDValue LHS = Node->getOperand(0);
3345  SDValue RHS = Node->getOperand(1);
3346  SDValue Carry = Node->getOperand(2);
3347 
3348  bool IsAdd = Node->getOpcode() == ISD::ADDCARRY;
3349 
3350  // Initial add of the 2 operands.
3351  unsigned Op = IsAdd ? ISD::ADD : ISD::SUB;
3352  EVT VT = LHS.getValueType();
3353  SDValue Sum = DAG.getNode(Op, dl, VT, LHS, RHS);
3354 
3355  // Initial check for overflow.
3356  EVT CarryType = Node->getValueType(1);
3357  EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3358  ISD::CondCode CC = IsAdd ? ISD::SETULT : ISD::SETUGT;
3359  SDValue Overflow = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3360 
3361  // Add of the sum and the carry.
3362  SDValue CarryExt =
3363  DAG.getZeroExtendInReg(DAG.getZExtOrTrunc(Carry, dl, VT), dl, MVT::i1);
3364  SDValue Sum2 = DAG.getNode(Op, dl, VT, Sum, CarryExt);
3365 
3366  // Second check for overflow. If we are adding, we can only overflow if the
3367  // initial sum is all 1s ang the carry is set, resulting in a new sum of 0.
3368  // If we are subtracting, we can only overflow if the initial sum is 0 and
3369  // the carry is set, resulting in a new sum of all 1s.
3370  SDValue Zero = DAG.getConstant(0, dl, VT);
3371  SDValue Overflow2 =
3372  IsAdd ? DAG.getSetCC(dl, SetCCType, Sum2, Zero, ISD::SETEQ)
3373  : DAG.getSetCC(dl, SetCCType, Sum, Zero, ISD::SETEQ);
3374  Overflow2 = DAG.getNode(ISD::AND, dl, SetCCType, Overflow2,
3375  DAG.getZExtOrTrunc(Carry, dl, SetCCType));
3376 
3377  SDValue ResultCarry =
3378  DAG.getNode(ISD::OR, dl, SetCCType, Overflow, Overflow2);
3379 
3380  Results.push_back(Sum2);
3381  Results.push_back(DAG.getBoolExtOrTrunc(ResultCarry, dl, CarryType, VT));
3382  break;
3383  }
3384  case ISD::SADDO:
3385  case ISD::SSUBO: {
3386  SDValue Result, Overflow;
3387  TLI.expandSADDSUBO(Node, Result, Overflow, DAG);
3388  Results.push_back(Result);
3389  Results.push_back(Overflow);
3390  break;
3391  }
3392  case ISD::UADDO:
3393  case ISD::USUBO: {
3394  SDValue Result, Overflow;
3395  TLI.expandUADDSUBO(Node, Result, Overflow, DAG);
3396  Results.push_back(Result);
3397  Results.push_back(Overflow);
3398  break;
3399  }
3400  case ISD::UMULO:
3401  case ISD::SMULO: {
3402  SDValue Result, Overflow;
3403  if (TLI.expandMULO(Node, Result, Overflow, DAG)) {
3404  Results.push_back(Result);
3405  Results.push_back(Overflow);
3406  }
3407  break;
3408  }
3409  case ISD::BUILD_PAIR: {
3410  EVT PairTy = Node->getValueType(0);
3411  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3412  Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3413  Tmp2 = DAG.getNode(
3414  ISD::SHL, dl, PairTy, Tmp2,
3415  DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3416  TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3417  Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3418  break;
3419  }
3420  case ISD::SELECT:
3421  Tmp1 = Node->getOperand(0);
3422  Tmp2 = Node->getOperand(1);
3423  Tmp3 = Node->getOperand(2);
3424  if (Tmp1.getOpcode() == ISD::SETCC) {
3425  Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3426  Tmp2, Tmp3,
3427  cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3428  } else {
3429  Tmp1 = DAG.getSelectCC(dl, Tmp1,
3430  DAG.getConstant(0, dl, Tmp1.getValueType()),
3431  Tmp2, Tmp3, ISD::SETNE);
3432  }
3433  Results.push_back(Tmp1);
3434  break;
3435  case ISD::BR_JT: {
3436  SDValue Chain = Node->getOperand(0);
3437  SDValue Table = Node->getOperand(1);
3438  SDValue Index = Node->getOperand(2);
3439 
3440  const DataLayout &TD = DAG.getDataLayout();
3441  EVT PTy = TLI.getPointerTy(TD);
3442 
3443  unsigned EntrySize =
3444  DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3445 
3446  // For power-of-two jumptable entry sizes convert multiplication to a shift.
3447  // This transformation needs to be done here since otherwise the MIPS
3448  // backend will end up emitting a three instruction multiply sequence
3449  // instead of a single shift and MSP430 will call a runtime function.
3450  if (llvm::isPowerOf2_32(EntrySize))
3451  Index = DAG.getNode(
3452  ISD::SHL, dl, Index.getValueType(), Index,
3453  DAG.getConstant(llvm::Log2_32(EntrySize), dl, Index.getValueType()));
3454  else
3455  Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3456  DAG.getConstant(EntrySize, dl, Index.getValueType()));
3457  SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3458  Index, Table);
3459 
3460  EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3461  SDValue LD = DAG.getExtLoad(
3462  ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3463  MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT);
3464  Addr = LD;
3465  if (TLI.isJumpTableRelative()) {
3466  // For PIC, the sequence is:
3467  // BRIND(load(Jumptable + index) + RelocBase)
3468  // RelocBase can be JumpTable, GOT or some sort of global base.
3469  Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3470  TLI.getPICJumpTableRelocBase(Table, DAG));
3471  }
3472 
3473  Tmp1 = TLI.expandIndirectJTBranch(dl, LD.getValue(1), Addr, DAG);
3474  Results.push_back(Tmp1);
3475  break;
3476  }
3477  case ISD::BRCOND:
3478  // Expand brcond's setcc into its constituent parts and create a BR_CC
3479  // Node.
3480  Tmp1 = Node->getOperand(0);
3481  Tmp2 = Node->getOperand(1);
3482  if (Tmp2.getOpcode() == ISD::SETCC) {
3483  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3484  Tmp1, Tmp2.getOperand(2),
3485  Tmp2.getOperand(0), Tmp2.getOperand(1),
3486  Node->getOperand(2));
3487  } else {
3488  // We test only the i1 bit. Skip the AND if UNDEF or another AND.
3489  if (Tmp2.isUndef() ||
3490  (Tmp2.getOpcode() == ISD::AND &&
3491  isa<ConstantSDNode>(Tmp2.getOperand(1)) &&
3492  cast<ConstantSDNode>(Tmp2.getOperand(1))->getZExtValue() == 1))
3493  Tmp3 = Tmp2;
3494  else
3495  Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3496  DAG.getConstant(1, dl, Tmp2.getValueType()));
3497  Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3498  DAG.getCondCode(ISD::SETNE), Tmp3,
3499  DAG.getConstant(0, dl, Tmp3.getValueType()),
3500  Node->getOperand(2));
3501  }
3502  Results.push_back(Tmp1);
3503  break;
3504  case ISD::SETCC: {
3505  Tmp1 = Node->getOperand(0);
3506  Tmp2 = Node->getOperand(1);
3507  Tmp3 = Node->getOperand(2);
3508  bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3509  Tmp3, NeedInvert, dl);
3510 
3511  if (Legalized) {
3512  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3513  // condition code, create a new SETCC node.
3514  if (Tmp3.getNode())
3515  Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3516  Tmp1, Tmp2, Tmp3);
3517 
3518  // If we expanded the SETCC by inverting the condition code, then wrap
3519  // the existing SETCC in a NOT to restore the intended condition.
3520  if (NeedInvert)
3521  Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3522 
3523  Results.push_back(Tmp1);
3524  break;
3525  }
3526 
3527  // Otherwise, SETCC for the given comparison type must be completely
3528  // illegal; expand it into a SELECT_CC.
3529  EVT VT = Node->getValueType(0);
3530  int TrueValue;
3531  switch (TLI.getBooleanContents(Tmp1.getValueType())) {
3534  TrueValue = 1;
3535  break;
3537  TrueValue = -1;
3538  break;
3539  }
3540  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3541  DAG.getConstant(TrueValue, dl, VT),
3542  DAG.getConstant(0, dl, VT),
3543  Tmp3);
3544  Results.push_back(Tmp1);
3545  break;
3546  }
3547  case ISD::SELECT_CC: {
3548  Tmp1 = Node->getOperand(0); // LHS
3549  Tmp2 = Node->getOperand(1); // RHS
3550  Tmp3 = Node->getOperand(2); // True
3551  Tmp4 = Node->getOperand(3); // False
3552  EVT VT = Node->getValueType(0);
3553  SDValue CC = Node->getOperand(4);
3554  ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3555 
3556  if (TLI.isCondCodeLegalOrCustom(CCOp, Tmp1.getSimpleValueType())) {
3557  // If the condition code is legal, then we need to expand this
3558  // node using SETCC and SELECT.
3559  EVT CmpVT = Tmp1.getValueType();
3560  assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3561  "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3562  "expanded.");
3563  EVT CCVT =
3564  TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3565  SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3566  Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3567  break;
3568  }
3569 
3570  // SELECT_CC is legal, so the condition code must not be.
3571  bool Legalized = false;
3572  // Try to legalize by inverting the condition. This is for targets that
3573  // might support an ordered version of a condition, but not the unordered
3574  // version (or vice versa).
3575  ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3576  Tmp1.getValueType().isInteger());
3577  if (TLI.isCondCodeLegalOrCustom(InvCC, Tmp1.getSimpleValueType())) {
3578  // Use the new condition code and swap true and false
3579  Legalized = true;
3580  Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3581  } else {
3582  // If The inverse is not legal, then try to swap the arguments using
3583  // the inverse condition code.
3584  ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3585  if (TLI.isCondCodeLegalOrCustom(SwapInvCC, Tmp1.getSimpleValueType())) {
3586  // The swapped inverse condition is legal, so swap true and false,
3587  // lhs and rhs.
3588  Legalized = true;
3589  Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3590  }
3591  }
3592 
3593  if (!Legalized) {
3594  Legalized = LegalizeSetCCCondCode(
3595  getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3596  dl);
3597 
3598  assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3599 
3600  // If we expanded the SETCC by inverting the condition code, then swap
3601  // the True/False operands to match.
3602  if (NeedInvert)
3603  std::swap(Tmp3, Tmp4);
3604 
3605  // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3606  // condition code, create a new SELECT_CC node.
3607  if (CC.getNode()) {
3608  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3609  Tmp1, Tmp2, Tmp3, Tmp4, CC);
3610  } else {
3611  Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3612  CC = DAG.getCondCode(ISD::SETNE);
3613  Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3614  Tmp2, Tmp3, Tmp4, CC);
3615  }
3616  }
3617  Results.push_back(Tmp1);
3618  break;
3619  }
3620  case ISD::BR_CC: {
3621  Tmp1 = Node->getOperand(0); // Chain
3622  Tmp2 = Node->getOperand(2); // LHS
3623  Tmp3 = Node->getOperand(3); // RHS
3624  Tmp4 = Node->getOperand(1); // CC
3625 
3626  bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3627  Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3628  (void)Legalized;
3629  assert(Legalized && "Can't legalize BR_CC with legal condition!");
3630 
3631  assert(!NeedInvert && "Don't know how to invert BR_CC!");
3632 
3633  // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3634  // node.
3635  if (Tmp4.getNode()) {
3636  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3637  Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3638  } else {
3639  Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3640  Tmp4 = DAG.getCondCode(ISD::SETNE);
3641  Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3642  Tmp2, Tmp3, Node->getOperand(4));
3643  }
3644  Results.push_back(Tmp1);
3645  break;
3646  }
3647  case ISD::BUILD_VECTOR:
3648  Results.push_back(ExpandBUILD_VECTOR(Node));
3649  break;
3650  case ISD::SRA:
3651  case ISD::SRL:
3652  case ISD::SHL: {
3653  // Scalarize vector SRA/SRL/SHL.
3654  EVT VT = Node->getValueType(0);
3655  assert(VT.isVector() && "Unable to legalize non-vector shift");
3656  assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3657  unsigned NumElem = VT.getVectorNumElements();
3658 
3659  SmallVector<SDValue, 8> Scalars;
3660  for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3661  SDValue Ex = DAG.getNode(
3662  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3663  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3664  SDValue Sh = DAG.getNode(
3665  ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3666  DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3667  Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3668  VT.getScalarType(), Ex, Sh));
3669  }
3670 
3671  SDValue Result = DAG.getBuildVector(Node->getValueType(0), dl, Scalars);
3672  ReplaceNode(SDValue(Node, 0), Result);
3673  break;
3674  }
3675  case ISD::VECREDUCE_FADD:
3676  case ISD::VECREDUCE_FMUL:
3677  case ISD::VECREDUCE_ADD:
3678  case ISD::VECREDUCE_MUL:
3679  case ISD::VECREDUCE_AND:
3680  case ISD::VECREDUCE_OR:
3681  case ISD::VECREDUCE_XOR:
3682  case ISD::VECREDUCE_SMAX:
3683  case ISD::VECREDUCE_SMIN:
3684  case ISD::VECREDUCE_UMAX:
3685  case ISD::VECREDUCE_UMIN:
3686  case ISD::VECREDUCE_FMAX:
3687  case ISD::VECREDUCE_FMIN:
3688  Results.push_back(TLI.expandVecReduce(Node, DAG));
3689  break;
3691  case ISD::GlobalAddress:
3692  case ISD::GlobalTLSAddress:
3693  case ISD::ExternalSymbol:
3694  case ISD::ConstantPool:
3695  case ISD::JumpTable:
3698  case ISD::INTRINSIC_VOID:
3699  // FIXME: Custom lowering for these operations shouldn't return null!
3700  break;
3701  }
3702 
3703  // Replace the original node with the legalized result.
3704  if (Results.empty()) {
3705  LLVM_DEBUG(dbgs() << "Cannot expand node\n");
3706  return false;
3707  }
3708 
3709  LLVM_DEBUG(dbgs() << "Successfully expanded node\n");
3710  ReplaceNode(Node, Results.data());
3711  return true;
3712 }
3713 
3714 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3715  LLVM_DEBUG(dbgs() << "Trying to convert node to libcall\n");
3717  SDLoc dl(Node);
3718  // FIXME: Check flags on the node to see if we can use a finite call.
3719  bool CanUseFiniteLibCall = TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath;
3720  unsigned Opc = Node->getOpcode();
3721  switch (Opc) {
3722  case ISD::ATOMIC_FENCE: {
3723  // If the target didn't lower this, lower it to '__sync_synchronize()' call
3724  // FIXME: handle "fence singlethread" more efficiently.
3726 
3728  CLI.setDebugLoc(dl)
3729  .setChain(Node->getOperand(0))
3730  .setLibCallee(
3731  CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3732  DAG.getExternalSymbol("__sync_synchronize",
3733  TLI.getPointerTy(DAG.getDataLayout())),
3734  std::move(Args));
3735 
3736  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3737 
3738  Results.push_back(CallResult.second);
3739  break;
3740  }
3741  // By default, atomic intrinsics are marked Legal and lowered. Targets
3742  // which don't support them directly, however, may want libcalls, in which
3743  // case they mark them Expand, and we get here.
3744  case ISD::ATOMIC_SWAP:
3745  case ISD::ATOMIC_LOAD_ADD:
3746  case ISD::ATOMIC_LOAD_SUB:
3747  case ISD::ATOMIC_LOAD_AND:
3748  case ISD::ATOMIC_LOAD_CLR:
3749  case ISD::ATOMIC_LOAD_OR:
3750  case ISD::ATOMIC_LOAD_XOR:
3751  case ISD::ATOMIC_LOAD_NAND:
3752  case ISD::ATOMIC_LOAD_MIN:
3753  case ISD::ATOMIC_LOAD_MAX:
3754  case ISD::ATOMIC_LOAD_UMIN:
3755  case ISD::ATOMIC_LOAD_UMAX:
3756  case ISD::ATOMIC_CMP_SWAP: {
3757  MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3758  RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
3759  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
3760 
3761  std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
3762  Results.push_back(Tmp.first);
3763  Results.push_back(Tmp.second);
3764  break;
3765  }
3766  case ISD::TRAP: {
3767  // If this operation is not supported, lower it to 'abort()' call
3770  CLI.setDebugLoc(dl)
3771  .setChain(Node->getOperand(0))
3772  .setLibCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3773  DAG.getExternalSymbol(
3774  "abort", TLI.getPointerTy(DAG.getDataLayout())),
3775  std::move(Args));
3776  std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3777 
3778  Results.push_back(CallResult.second);
3779  break;
3780  }
3781  case ISD::FMINNUM:
3782  case ISD::STRICT_FMINNUM:
3783  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3784  RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3785  RTLIB::FMIN_PPCF128));
3786  break;
3787  case ISD::FMAXNUM:
3788  case ISD::STRICT_FMAXNUM:
3789  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3790  RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3791  RTLIB::FMAX_PPCF128));
3792  break;
3793  case ISD::FSQRT:
3794  case ISD::STRICT_FSQRT:
3795  Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3796  RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3797  RTLIB::SQRT_PPCF128));
3798  break;
3799  case ISD::FCBRT:
3800  Results.push_back(ExpandFPLibCall(Node, RTLIB::CBRT_F32, RTLIB::CBRT_F64,
3801  RTLIB::CBRT_F80, RTLIB::CBRT_F128,
3802  RTLIB::CBRT_PPCF128));
3803  break;
3804  case ISD::FSIN:
3805  case ISD::STRICT_FSIN:
3806  Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3807  RTLIB::SIN_F80, RTLIB::SIN_F128,
3808  RTLIB::SIN_PPCF128));
3809  break;
3810  case ISD::FCOS:
3811  case ISD::STRICT_FCOS:
3812  Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3813  RTLIB::COS_F80, RTLIB::COS_F128,
3814  RTLIB::COS_PPCF128));
3815  break;
3816  case ISD::FSINCOS:
3817  // Expand into sincos libcall.
3818  ExpandSinCosLibCall(Node, Results);
3819  break;
3820  case ISD::FLOG:
3821  case ISD::STRICT_FLOG:
3822  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log_finite))
3823  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_FINITE_F32,
3824  RTLIB::LOG_FINITE_F64,
3825  RTLIB::LOG_FINITE_F80,
3826  RTLIB::LOG_FINITE_F128,
3827  RTLIB::LOG_FINITE_PPCF128));
3828  else
3829  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3830  RTLIB::LOG_F80, RTLIB::LOG_F128,
3831  RTLIB::LOG_PPCF128));
3832  break;
3833  case ISD::FLOG2:
3834  case ISD::STRICT_FLOG2:
3835  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log2_finite))
3836  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_FINITE_F32,
3837  RTLIB::LOG2_FINITE_F64,
3838  RTLIB::LOG2_FINITE_F80,
3839  RTLIB::LOG2_FINITE_F128,
3840  RTLIB::LOG2_FINITE_PPCF128));
3841  else
3842  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3843  RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3844  RTLIB::LOG2_PPCF128));
3845  break;
3846  case ISD::FLOG10:
3847  case ISD::STRICT_FLOG10:
3848  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_log10_finite))
3849  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_FINITE_F32,
3850  RTLIB::LOG10_FINITE_F64,
3851  RTLIB::LOG10_FINITE_F80,
3852  RTLIB::LOG10_FINITE_F128,
3853  RTLIB::LOG10_FINITE_PPCF128));
3854  else
3855  Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3856  RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3857  RTLIB::LOG10_PPCF128));
3858  break;
3859  case ISD::FEXP:
3860  case ISD::STRICT_FEXP:
3861  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp_finite))
3862  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_FINITE_F32,
3863  RTLIB::EXP_FINITE_F64,
3864  RTLIB::EXP_FINITE_F80,
3865  RTLIB::EXP_FINITE_F128,
3866  RTLIB::EXP_FINITE_PPCF128));
3867  else
3868  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3869  RTLIB::EXP_F80, RTLIB::EXP_F128,
3870  RTLIB::EXP_PPCF128));
3871  break;
3872  case ISD::FEXP2:
3873  case ISD::STRICT_FEXP2:
3874  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_exp2_finite))
3875  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_FINITE_F32,
3876  RTLIB::EXP2_FINITE_F64,
3877  RTLIB::EXP2_FINITE_F80,
3878  RTLIB::EXP2_FINITE_F128,
3879  RTLIB::EXP2_FINITE_PPCF128));
3880  else
3881  Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3882  RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3883  RTLIB::EXP2_PPCF128));
3884  break;
3885  case ISD::FTRUNC:
3886  case ISD::STRICT_FTRUNC:
3887  Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3888  RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3889  RTLIB::TRUNC_PPCF128));
3890  break;
3891  case ISD::FFLOOR:
3892  case ISD::STRICT_FFLOOR:
3893  Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3894  RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3895  RTLIB::FLOOR_PPCF128));
3896  break;
3897  case ISD::FCEIL:
3898  case ISD::STRICT_FCEIL:
3899  Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3900  RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3901  RTLIB::CEIL_PPCF128));
3902  break;
3903  case ISD::FRINT:
3904  case ISD::STRICT_FRINT:
3905  Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3906  RTLIB::RINT_F80, RTLIB::RINT_F128,
3907  RTLIB::RINT_PPCF128));
3908  break;
3909  case ISD::FNEARBYINT:
3911  Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3912  RTLIB::NEARBYINT_F64,
3913  RTLIB::NEARBYINT_F80,
3914  RTLIB::NEARBYINT_F128,
3915  RTLIB::NEARBYINT_PPCF128));
3916  break;
3917  case ISD::FROUND:
3918  case ISD::STRICT_FROUND:
3919  Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3920  RTLIB::ROUND_F64,
3921  RTLIB::ROUND_F80,
3922  RTLIB::ROUND_F128,
3923  RTLIB::ROUND_PPCF128));
3924  break;
3925  case ISD::FPOWI:
3926  case ISD::STRICT_FPOWI:
3927  Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3928  RTLIB::POWI_F80, RTLIB::POWI_F128,
3929  RTLIB::POWI_PPCF128));
3930  break;
3931  case ISD::FPOW:
3932  case ISD::STRICT_FPOW:
3933  if (CanUseFiniteLibCall && DAG.getLibInfo().has(LibFunc_pow_finite))
3934  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_FINITE_F32,
3935  RTLIB::POW_FINITE_F64,
3936  RTLIB::POW_FINITE_F80,
3937  RTLIB::POW_FINITE_F128,
3938  RTLIB::POW_FINITE_PPCF128));
3939  else
3940  Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3941  RTLIB::POW_F80, RTLIB::POW_F128,
3942  RTLIB::POW_PPCF128));
3943  break;
3944  case ISD::FDIV:
3945  Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3946  RTLIB::DIV_F80, RTLIB::DIV_F128,
3947  RTLIB::DIV_PPCF128));
3948  break;
3949  case ISD::FREM:
3950  case ISD::STRICT_FREM:
3951  Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3952  RTLIB::REM_F80, RTLIB::REM_F128,
3953  RTLIB::REM_PPCF128));
3954  break;
3955  case ISD::FMA:
3956  case ISD::STRICT_FMA:
3957  Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3958  RTLIB::FMA_F80, RTLIB::FMA_F128,
3959  RTLIB::FMA_PPCF128));
3960  break;
3961  case ISD::FADD:
3962  Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3963  RTLIB::ADD_F80, RTLIB::ADD_F128,
3964  RTLIB::ADD_PPCF128));
3965  break;
3966  case ISD::FMUL:
3967  Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3968  RTLIB::MUL_F80, RTLIB::MUL_F128,
3969  RTLIB::MUL_PPCF128));
3970  break;
3971  case ISD::FP16_TO_FP:
3972  if (Node->getValueType(0) == MVT::f32) {
3973  Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3974  }
3975  break;
3976  case ISD::FP_TO_FP16: {
3977  RTLIB::Libcall LC =
3979  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3980  Results.push_back(ExpandLibCall(LC, Node, false));
3981  break;
3982  }
3983  case ISD::FSUB:
3984  Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
3985  RTLIB::SUB_F80, RTLIB::SUB_F128,
3986  RTLIB::SUB_PPCF128));
3987  break;
3988  case ISD::SREM:
3989  Results.push_back(ExpandIntLibCall(Node, true,
3990  RTLIB::SREM_I8,
3991  RTLIB::SREM_I16, RTLIB::SREM_I32,
3992  RTLIB::SREM_I64, RTLIB::SREM_I128));
3993  break;
3994  case ISD::UREM:
3995  Results.push_back(ExpandIntLibCall(Node, false,
3996  RTLIB::UREM_I8,
3997  RTLIB::UREM_I16, RTLIB::UREM_I32,
3998  RTLIB::UREM_I64, RTLIB::UREM_I128));
3999  break;
4000  case ISD::SDIV:
4001  Results.push_back(ExpandIntLibCall(Node, true,
4002  RTLIB::SDIV_I8,
4003  RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4004  RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4005  break;
4006  case ISD::UDIV:
4007  Results.push_back(ExpandIntLibCall(Node, false,
4008  RTLIB::UDIV_I8,
4009  RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4010  RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4011  break;
4012  case ISD::SDIVREM:
4013  case ISD::UDIVREM:
4014  // Expand into divrem libcall
4015  ExpandDivRemLibCall(Node, Results);
4016  break;
4017  case ISD::MUL:
4018  Results.push_back(ExpandIntLibCall(Node, false,
4019  RTLIB::MUL_I8,
4020  RTLIB::MUL_I16, RTLIB::MUL_I32,
4021  RTLIB::MUL_I64, RTLIB::MUL_I128));
4022  break;
4023  case ISD::CTLZ_ZERO_UNDEF:
4024  switch (Node->getSimpleValueType(0).SimpleTy) {
4025  default:
4026  llvm_unreachable("LibCall explicitly requested, but not available");
4027  case MVT::i32:
4028  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false));
4029  break;
4030  case MVT::i64:
4031  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false));
4032  break;
4033  case MVT::i128:
4034  Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false));
4035  break;
4036  }
4037  break;
4038  }
4039 
4040  // Replace the original node with the legalized result.
4041  if (!Results.empty()) {
4042  LLVM_DEBUG(dbgs() << "Successfully converted node to libcall\n");
4043  ReplaceNode(Node, Results.data());
4044  } else
4045  LLVM_DEBUG(dbgs() << "Could not convert node to libcall\n");
4046 }
4047 
4048 // Determine the vector type to use in place of an original scalar element when
4049 // promoting equally sized vectors.
4051  MVT EltVT, MVT NewEltVT) {
4052  unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4053  MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4054  assert(TLI.isTypeLegal(MidVT) && "unexpected");
4055  return MidVT;
4056 }
4057 
4058 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4059  LLVM_DEBUG(dbgs() << "Trying to promote node\n");
4061  MVT OVT = Node->getSimpleValueType(0);
4062  if (Node->getOpcode() == ISD::UINT_TO_FP ||
4063  Node->getOpcode() == ISD::SINT_TO_FP ||
4064  Node->getOpcode() == ISD::SETCC ||
4065  Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4066  Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4067  OVT = Node->getOperand(0).getSimpleValueType();
4068  }
4069  if (Node->getOpcode() == ISD::BR_CC)
4070  OVT = Node->getOperand(2).getSimpleValueType();
4071  MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4072  SDLoc dl(Node);
4073  SDValue Tmp1, Tmp2, Tmp3;
4074  switch (Node->getOpcode()) {
4075  case ISD::CTTZ:
4076  case ISD::CTTZ_ZERO_UNDEF:
4077  case ISD::CTLZ:
4078  case ISD::CTLZ_ZERO_UNDEF:
4079  case ISD::CTPOP:
4080  // Zero extend the argument.
4081  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4082  if (Node->getOpcode() == ISD::CTTZ) {
4083  // The count is the same in the promoted type except if the original
4084  // value was zero. This can be handled by setting the bit just off
4085  // the top of the original type.
4086  auto TopBit = APInt::getOneBitSet(NVT.getSizeInBits(),
4087  OVT.getSizeInBits());
4088  Tmp1 = DAG.getNode(ISD::OR, dl, NVT, Tmp1,
4089  DAG.getConstant(TopBit, dl, NVT));
4090  }
4091  // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4092  // already the correct result.
4093  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4094  if (Node->getOpcode() == ISD::CTLZ ||
4095  Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4096  // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4097  Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4098  DAG.getConstant(NVT.getSizeInBits() -
4099  OVT.getSizeInBits(), dl, NVT));
4100  }
4101  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4102  break;
4103  case ISD::BITREVERSE:
4104  case ISD::BSWAP: {
4105  unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4106  Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4107  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4108  Tmp1 = DAG.getNode(
4109  ISD::SRL, dl, NVT, Tmp1,
4110  DAG.getConstant(DiffBits, dl,
4111  TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4112 
4113  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4114  break;
4115  }
4116  case ISD::FP_TO_UINT:
4117  case ISD::FP_TO_SINT:
4118  Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4119  Node->getOpcode() == ISD::FP_TO_SINT, dl);
4120  Results.push_back(Tmp1);
4121  break;
4122  case ISD::UINT_TO_FP:
4123  case ISD::SINT_TO_FP:
4124  Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4125  Node->getOpcode() == ISD::SINT_TO_FP, dl);
4126  Results.push_back(Tmp1);
4127  break;
4128  case ISD::VAARG: {
4129  SDValue Chain = Node->getOperand(0); // Get the chain.
4130  SDValue Ptr = Node->getOperand(1); // Get the pointer.
4131 
4132  unsigned TruncOp;
4133  if (OVT.isVector()) {
4134  TruncOp = ISD::BITCAST;
4135  } else {
4136  assert(OVT.isInteger()
4137  && "VAARG promotion is supported only for vectors or integer types");
4138  TruncOp = ISD::TRUNCATE;
4139  }
4140 
4141  // Perform the larger operation, then convert back
4142  Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4143  Node->getConstantOperandVal(3));
4144  Chain = Tmp1.getValue(1);
4145 
4146  Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4147 
4148  // Modified the chain result - switch anything that used the old chain to
4149  // use the new one.
4150  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4151  DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4152  if (UpdatedNodes) {
4153  UpdatedNodes->insert(Tmp2.getNode());
4154  UpdatedNodes->insert(Chain.getNode());
4155  }
4156  ReplacedNode(Node);
4157  break;
4158  }
4159  case ISD::MUL:
4160  case ISD::SDIV:
4161  case ISD::SREM:
4162  case ISD::UDIV:
4163  case ISD::UREM:
4164  case ISD::AND:
4165  case ISD::OR:
4166  case ISD::XOR: {
4167  unsigned ExtOp, TruncOp;
4168  if (OVT.isVector()) {
4169  ExtOp = ISD::BITCAST;
4170  TruncOp = ISD::BITCAST;
4171  } else {
4172  assert(OVT.isInteger() && "Cannot promote logic operation");
4173 
4174  switch (Node->getOpcode()) {
4175  default:
4176  ExtOp = ISD::ANY_EXTEND;
4177  break;
4178  case ISD::SDIV:
4179  case ISD::SREM:
4180  ExtOp = ISD::SIGN_EXTEND;
4181  break;
4182  case ISD::UDIV:
4183  case ISD::UREM:
4184  ExtOp = ISD::ZERO_EXTEND;
4185  break;
4186  }
4187  TruncOp = ISD::TRUNCATE;
4188  }
4189  // Promote each of the values to the new type.
4190  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4191  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4192  // Perform the larger operation, then convert back
4193  Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4194  Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4195  break;
4196  }
4197  case ISD::UMUL_LOHI:
4198  case ISD::SMUL_LOHI: {
4199  // Promote to a multiply in a wider integer type.
4200  unsigned ExtOp = Node->getOpcode() == ISD::UMUL_LOHI ? ISD::ZERO_EXTEND
4201  : ISD::SIGN_EXTEND;
4202  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4203  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4204  Tmp1 = DAG.getNode(ISD::MUL, dl, NVT, Tmp1, Tmp2);
4205 
4206  auto &DL = DAG.getDataLayout();
4207  unsigned OriginalSize = OVT.getScalarSizeInBits();
4208  Tmp2 = DAG.getNode(
4209  ISD::SRL, dl, NVT, Tmp1,
4210  DAG.getConstant(OriginalSize, dl, TLI.getScalarShiftAmountTy(DL, NVT)));
4211  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4212  Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp2));
4213  break;
4214  }
4215  case ISD::SELECT: {
4216  unsigned ExtOp, TruncOp;
4217  if (Node->getValueType(0).isVector() ||
4218  Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4219  ExtOp = ISD::BITCAST;
4220  TruncOp = ISD::BITCAST;
4221  } else if (Node->getValueType(0).isInteger()) {
4222  ExtOp = ISD::ANY_EXTEND;
4223  TruncOp = ISD::TRUNCATE;
4224  } else {
4225  ExtOp = ISD::FP_EXTEND;
4226  TruncOp = ISD::FP_ROUND;
4227  }
4228  Tmp1 = Node->getOperand(0);
4229  // Promote each of the values to the new type.
4230  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4231  Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4232  // Perform the larger operation, then round down.
4233  Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4234  if (TruncOp != ISD::FP_ROUND)
4235  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4236  else
4237  Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4238  DAG.getIntPtrConstant(0, dl));
4239  Results.push_back(Tmp1);
4240  break;
4241  }
4242  case ISD::VECTOR_SHUFFLE: {
4243  ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4244 
4245  // Cast the two input vectors.
4246  Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4247  Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4248 
4249  // Convert the shuffle mask to the right # elements.
4250  Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4251  Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4252  Results.push_back(Tmp1);
4253  break;
4254  }
4255  case ISD::SETCC: {
4256  unsigned ExtOp = ISD::FP_EXTEND;
4257  if (NVT.isInteger()) {
4258  ISD::CondCode CCCode =
4259  cast<CondCodeSDNode>(Node->getOperand(2))->get();
4261  }
4262  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4263  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4264  Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4265  Tmp1, Tmp2, Node->getOperand(2)));
4266  break;
4267  }
4268  case ISD::BR_CC: {
4269  unsigned ExtOp = ISD::FP_EXTEND;
4270  if (NVT.isInteger()) {
4271  ISD::CondCode CCCode =
4272  cast<CondCodeSDNode>(Node->getOperand(1))->get();
4274  }
4275  Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4276  Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4277  Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4278  Node->getOperand(0), Node->getOperand(1),
4279  Tmp1, Tmp2, Node->getOperand(4)));
4280  break;
4281  }
4282  case ISD::FADD:
4283  case ISD::FSUB:
4284  case ISD::FMUL:
4285  case ISD::FDIV:
4286  case ISD::FREM:
4287  case ISD::FMINNUM:
4288  case ISD::FMAXNUM:
4289  case ISD::FPOW:
4290  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4291  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4292  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4293  Node->getFlags());
4294  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4295  Tmp3, DAG.getIntPtrConstant(0, dl)));
4296  break;
4297  case ISD::FMA:
4298  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4299  Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4300  Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4301  Results.push_back(
4302  DAG.getNode(ISD::FP_ROUND, dl, OVT,
4303  DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4304  DAG.getIntPtrConstant(0, dl)));
4305  break;
4306  case ISD::FCOPYSIGN:
4307  case ISD::FPOWI: {
4308  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4309  Tmp2 = Node->getOperand(1);
4310  Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4311 
4312  // fcopysign doesn't change anything but the sign bit, so
4313  // (fp_round (fcopysign (fpext a), b))
4314  // is as precise as
4315  // (fp_round (fpext a))
4316  // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4317  const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4318  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4319  Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4320  break;
4321  }
4322  case ISD::FFLOOR:
4323  case ISD::FCEIL:
4324  case ISD::FRINT:
4325  case ISD::FNEARBYINT:
4326  case ISD::FROUND:
4327  case ISD::FTRUNC:
4328  case ISD::FNEG:
4329  case ISD::FSQRT:
4330  case ISD::FSIN:
4331  case ISD::FCOS:
4332  case ISD::FLOG:
4333  case ISD::FLOG2:
4334  case ISD::FLOG10:
4335  case ISD::FABS:
4336  case ISD::FEXP:
4337  case ISD::FEXP2:
4338  Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4339  Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4340  Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4341  Tmp2, DAG.getIntPtrConstant(0, dl)));
4342  break;
4343  case ISD::BUILD_VECTOR: {
4344  MVT EltVT = OVT.getVectorElementType();
4345  MVT NewEltVT = NVT.getVectorElementType();
4346 
4347  // Handle bitcasts to a different vector type with the same total bit size
4348  //
4349  // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4350  // =>
4351  // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4352 
4353  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4354  "Invalid promote type for build_vector");
4355  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4356 
4357  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4358 
4359  SmallVector<SDValue, 8> NewOps;
4360  for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4361  SDValue Op = Node->getOperand(I);
4362  NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4363  }
4364 
4365  SDLoc SL(Node);
4366  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4367  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4368  Results.push_back(CvtVec);
4369  break;
4370  }
4371  case ISD::EXTRACT_VECTOR_ELT: {
4372  MVT EltVT = OVT.getVectorElementType();
4373  MVT NewEltVT = NVT.getVectorElementType();
4374 
4375  // Handle bitcasts to a different vector type with the same total bit size.
4376  //
4377  // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4378  // =>
4379  // v4i32:castx = bitcast x:v2i64
4380  //
4381  // i64 = bitcast
4382  // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4383  // (i32 (extract_vector_elt castx, (2 * y + 1)))
4384  //
4385 
4386  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4387  "Invalid promote type for extract_vector_elt");
4388  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4389 
4390  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4391  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4392 
4393  SDValue Idx = Node->getOperand(1);
4394  EVT IdxVT = Idx.getValueType();
4395  SDLoc SL(Node);
4396  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4397  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4398 
4399  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4400 
4401  SmallVector<SDValue, 8> NewOps;
4402  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4403  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4404  SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4405 
4406  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4407  CastVec, TmpIdx);
4408  NewOps.push_back(Elt);
4409  }
4410 
4411  SDValue NewVec = DAG.getBuildVector(MidVT, SL, NewOps);
4412  Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4413  break;
4414  }
4415  case ISD::INSERT_VECTOR_ELT: {
4416  MVT EltVT = OVT.getVectorElementType();
4417  MVT NewEltVT = NVT.getVectorElementType();
4418 
4419  // Handle bitcasts to a different vector type with the same total bit size
4420  //
4421  // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4422  // =>
4423  // v4i32:castx = bitcast x:v2i64
4424  // v2i32:casty = bitcast y:i64
4425  //
4426  // v2i64 = bitcast
4427  // (v4i32 insert_vector_elt
4428  // (v4i32 insert_vector_elt v4i32:castx,
4429  // (extract_vector_elt casty, 0), 2 * z),
4430  // (extract_vector_elt casty, 1), (2 * z + 1))
4431 
4432  assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4433  "Invalid promote type for insert_vector_elt");
4434  assert(NewEltVT.bitsLT(EltVT) && "not handled");
4435 
4436  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4437  unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4438 
4439  SDValue Val = Node->getOperand(1);
4440  SDValue Idx = Node->getOperand(2);
4441  EVT IdxVT = Idx.getValueType();
4442  SDLoc SL(Node);
4443 
4444  SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4445  SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4446 
4447  SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4448  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4449 
4450  SDValue NewVec = CastVec;
4451  for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4452  SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4453  SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4454 
4455  SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4456  CastVal, IdxOffset);
4457 
4458  NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4459  NewVec, Elt, InEltIdx);
4460  }
4461 
4462  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4463  break;
4464  }
4465  case ISD::SCALAR_TO_VECTOR: {
4466  MVT EltVT = OVT.getVectorElementType();
4467  MVT NewEltVT = NVT.getVectorElementType();
4468 
4469  // Handle bitcasts to different vector type with the same total bit size.
4470  //
4471  // e.g. v2i64 = scalar_to_vector x:i64
4472  // =>
4473  // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4474  //
4475 
4476  MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4477  SDValue Val = Node->getOperand(0);
4478  SDLoc SL(Node);
4479 
4480  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4481  SDValue Undef = DAG.getUNDEF(MidVT);
4482 
4483  SmallVector<SDValue, 8> NewElts;
4484  NewElts.push_back(CastVal);
4485  for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4486  NewElts.push_back(Undef);
4487 
4488  SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4489  SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4490  Results.push_back(CvtVec);
4491  break;
4492  }
4493  case ISD::ATOMIC_SWAP: {
4494  AtomicSDNode *AM = cast<AtomicSDNode>(Node);
4495  SDLoc SL(Node);
4496  SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
4497  assert(NVT.getSizeInBits() == OVT.getSizeInBits() &&
4498  "unexpected promotion type");
4499  assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
4500  "unexpected atomic_swap with illegal type");
4501 
4502  SDValue NewAtomic
4503  = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, NVT,
4504  DAG.getVTList(NVT, MVT::Other),
4505  { AM->getChain(), AM->getBasePtr(), CastVal },
4506  AM->getMemOperand());
4507  Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
4508  Results.push_back(NewAtomic.getValue(1));
4509  break;
4510  }
4511  }
4512 
4513  // Replace the original node with the legalized result.
4514  if (!Results.empty()) {
4515  LLVM_DEBUG(dbgs() << "Successfully promoted node\n");
4516  ReplaceNode(Node, Results.data());
4517  } else
4518  LLVM_DEBUG(dbgs() << "Could not promote node\n");
4519 }
4520 
4521 /// This is the entry point for the file.
4523  AssignTopologicalOrder();
4524 
4525  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4526  // Use a delete listener to remove nodes which were deleted during
4527  // legalization from LegalizeNodes. This is needed to handle the situation
4528  // where a new node is allocated by the object pool to the same address of a
4529  // previously deleted node.
4530  DAGNodeDeletedListener DeleteListener(
4531  *this,
4532  [&LegalizedNodes](SDNode *N, SDNode *E) { LegalizedNodes.erase(N); });
4533 
4534  SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4535 
4536  // Visit all the nodes. We start in topological order, so that we see
4537  // nodes with their original operands intact. Legalization can produce
4538  // new nodes which may themselves need to be legalized. Iterate until all
4539  // nodes have been legalized.
4540  while (true) {
4541  bool AnyLegalized = false;
4542  for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4543  --NI;
4544 
4545  SDNode *N = &*NI;
4546  if (N->use_empty() && N != getRoot().getNode()) {
4547  ++NI;
4548  DeleteNode(N);
4549  continue;
4550  }
4551 
4552  if (LegalizedNodes.insert(N).second) {
4553  AnyLegalized = true;
4554  Legalizer.LegalizeOp(N);
4555 
4556  if (N->use_empty() && N != getRoot().getNode()) {
4557  ++NI;
4558  DeleteNode(N);
4559  }
4560  }
4561  }
4562  if (!AnyLegalized)
4563  break;
4564 
4565  }
4566 
4567  // Remove dead nodes now.
4568  RemoveDeadNodes();
4569 }
4570 
4572  SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4573  SmallPtrSet<SDNode *, 16> LegalizedNodes;
4574  SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4575 
4576  // Directly insert the node in question, and legalize it. This will recurse
4577  // as needed through operands.
4578  LegalizedNodes.insert(N);
4579  Legalizer.LegalizeOp(N);
4580 
4581  return LegalizedNodes.count(N);
4582 }
bool LegalizeOp(SDNode *N, SmallSetVector< SDNode *, 16 > &UpdatedNodes)
Transforms a SelectionDAG node and any operands to it into a node that is compatible with the target ...
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
Definition: ISDOpcodes.h:795
static Constant * getFPTrunc(Constant *C, Type *Ty, bool OnlyIfReduced=false)
Definition: Constants.cpp:1688
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:562
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:913
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
EVT getValueType() const
Return the ValueType of the referenced return value.
bool isInteger() const
Return true if this is an integer or a vector integer type.
static bool isConstant(const MachineInstr &MI)
bool isUndef() const
static MachinePointerInfo getJumpTable(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a jump table entry.
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant, which is required to be operand #1) half of the integer or float value specified as operand #0.
Definition: ISDOpcodes.h:183
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
Definition: APInt.h:561
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an vector value) starting with the ...
Definition: ISDOpcodes.h:382
BR_CC - Conditional branch.
Definition: ISDOpcodes.h:678
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static MVT getVectorVT(MVT VT, unsigned NumElements)
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:391
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
const SDValue & getVal() const
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
bool isVector() const
Return true if this is a vector value type.
CallLoweringInfo & setIsPostTypeLegalization(bool Value=true)
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
const SDValue & getBasePtr() const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
void push_back(const T &Elt)
Definition: SmallVector.h:211
const SDValue & getValue() const
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain...
Definition: ISDOpcodes.h:730
SDVTList getVTList() const
This file contains the declarations for metadata subclasses.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
const SDValue & getBasePtr() const
unsigned getVectorNumElements() const
const SDValue & getChain() const
Function Alias Analysis Results
static MVT getPromotedVectorElementType(const TargetLowering &TLI, MVT EltVT, MVT NewEltVT)
unsigned getAlignment() const
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:833
unsigned second
APInt trunc(unsigned width) const
Truncate to new width.
Definition: APInt.cpp:810
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
static uint32_t Concat[]
MVT getSimpleValueType(unsigned ResNo) const
Return the type of a specified result as a simple type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
static IntegerType * getInt64Ty(LLVMContext &C)
Definition: Type.cpp:176
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:408
const SDNodeFlags getFlags() const
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
Same for subtraction.
Definition: ISDOpcodes.h:253
void reserve(size_type N)
Definition: SmallVector.h:369
bool isByteSized() const
Return true if the bit size is a multiple of 8.
Definition: ValueTypes.h:211
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1 at the ...
Definition: ISDOpcodes.h:377
The address of the GOT.
Definition: ISDOpcodes.h:65
unsigned getValueSizeInBits() const
Returns the size of the value in bits.
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
Definition: ISDOpcodes.h:812
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
Definition: ISDOpcodes.h:459
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
const ConstantFP * getConstantFPValue() const
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
Definition: ISDOpcodes.h:158
bool isTruncatingStore() const
Return true if the op does a truncation before store.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode *> &Visited, SmallVectorImpl< const SDNode *> &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
unsigned getAddressSpace() const
Return the address space for the associated pointer.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
Definition: SmallPtrSet.h:343
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic...
Definition: ISDOpcodes.h:113
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
Definition: ISDOpcodes.h:209
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
Definition: ValueTypes.h:135
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations...
Definition: ISDOpcodes.h:480
static uint32_t getAlignment(const MCSectionCOFF &Sec)
Shift and rotation operations.
Definition: ISDOpcodes.h:434
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:417
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:651
CallLoweringInfo & setChain(SDValue InChain)
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
Definition: ISDOpcodes.h:190
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
op_iterator op_end() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
Definition: ISDOpcodes.h:570
SimpleValueType SimpleTy
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence, and carry arbitrary information that target might want to know.
Definition: ISDOpcodes.h:744
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA)...
Definition: ISDOpcodes.h:95
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:841
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:403
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG...
Definition: ISDOpcodes.h:72
This is an SDNode representing atomic operations.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
This file implements a class to represent arbitrary precision integral constant values and operations...
This represents a list of ValueType&#39;s that has been intern&#39;d by a SelectionDAG.
STACKSAVE - STACKSAVE has one operand, an input chain.
Definition: ISDOpcodes.h:726
FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to first (possible) on-stack ar...
Definition: ISDOpcodes.h:90
unsigned getSizeInBits() const
unsigned getScalarSizeInBits() const
Definition: ValueTypes.h:297
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:502
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here...
Definition: ISDOpcodes.h:117
falkor hwpf fix Falkor HW Prefetch Fix Late Phase
const TargetMachine & getTarget() const
Definition: SelectionDAG.h:404
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
bool bitsLT(MVT VT) const
Return true if this has less bits than VT.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:32
CallLoweringInfo & setZExtResult(bool Value=true)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
Definition: SelectionDAG.h:867
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
op_iterator op_begin() const
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:323
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification, or lowering of the constant.
Definition: ISDOpcodes.h:124
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:778
static bool useSinCos(SDNode *Node)
Only issue sincos libcall if both sin and cos are needed.
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
Definition: ISDOpcodes.h:1028
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
Definition: ISDOpcodes.h:150
MVT getVectorElementType() const
UNDEF - An undefined node.
Definition: ISDOpcodes.h:177
This class is used to represent ISD::STORE nodes.
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:548