LLVM 19.0.0git
TargetLoweringBase.cpp
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1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Twine.h"
19#include "llvm/Analysis/Loads.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/CallingConv.h"
40#include "llvm/IR/DataLayout.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/GlobalValue.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/Type.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <iterator>
62#include <string>
63#include <tuple>
64#include <utility>
65
66using namespace llvm;
67
69 "jump-is-expensive", cl::init(false),
70 cl::desc("Do not create extra branches to split comparison logic."),
72
74 ("min-jump-table-entries", cl::init(4), cl::Hidden,
75 cl::desc("Set minimum number of entries to use a jump table."));
76
78 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79 cl::desc("Set maximum size of jump tables."));
80
81/// Minimum jump table density for normal functions.
83 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
84 cl::desc("Minimum density for building a jump table in "
85 "a normal function"));
86
87/// Minimum jump table density for -Os or -Oz functions.
89 "optsize-jump-table-density", cl::init(40), cl::Hidden,
90 cl::desc("Minimum density for building a jump table in "
91 "an optsize function"));
92
93// FIXME: This option is only to test if the strict fp operation processed
94// correctly by preventing mutating strict fp operation to normal fp operation
95// during development. When the backend supports strict float operation, this
96// option will be meaningless.
97static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98 cl::desc("Don't mutate strict-float node to a legalize node"),
99 cl::init(false), cl::Hidden);
100
101static bool darwinHasSinCos(const Triple &TT) {
102 assert(TT.isOSDarwin() && "should be called with darwin triple");
103 // Don't bother with 32 bit x86.
104 if (TT.getArch() == Triple::x86)
105 return false;
106 // Macos < 10.9 has no sincos_stret.
107 if (TT.isMacOSX())
108 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
109 // iOS < 7.0 has no sincos_stret.
110 if (TT.isiOS())
111 return !TT.isOSVersionLT(7, 0);
112 // Any other darwin such as WatchOS/TvOS is new enough.
113 return true;
114}
115
116void TargetLoweringBase::InitLibcalls(const Triple &TT) {
117#define HANDLE_LIBCALL(code, name) \
118 setLibcallName(RTLIB::code, name);
119#include "llvm/IR/RuntimeLibcalls.def"
120#undef HANDLE_LIBCALL
121 // Initialize calling conventions to their default.
122 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124
125 // Use the f128 variants of math functions on x86_64
126 if (TT.getArch() == Triple::ArchType::x86_64 && TT.isGNUEnvironment()) {
127 setLibcallName(RTLIB::REM_F128, "fmodf128");
128 setLibcallName(RTLIB::FMA_F128, "fmaf128");
129 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
130 setLibcallName(RTLIB::CBRT_F128, "cbrtf128");
131 setLibcallName(RTLIB::LOG_F128, "logf128");
132 setLibcallName(RTLIB::LOG_FINITE_F128, "__logf128_finite");
133 setLibcallName(RTLIB::LOG2_F128, "log2f128");
134 setLibcallName(RTLIB::LOG2_FINITE_F128, "__log2f128_finite");
135 setLibcallName(RTLIB::LOG10_F128, "log10f128");
136 setLibcallName(RTLIB::LOG10_FINITE_F128, "__log10f128_finite");
137 setLibcallName(RTLIB::EXP_F128, "expf128");
138 setLibcallName(RTLIB::EXP_FINITE_F128, "__expf128_finite");
139 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
140 setLibcallName(RTLIB::EXP2_FINITE_F128, "__exp2f128_finite");
141 setLibcallName(RTLIB::EXP10_F128, "exp10f128");
142 setLibcallName(RTLIB::SIN_F128, "sinf128");
143 setLibcallName(RTLIB::COS_F128, "cosf128");
144 setLibcallName(RTLIB::SINCOS_F128, "sincosf128");
145 setLibcallName(RTLIB::POW_F128, "powf128");
146 setLibcallName(RTLIB::POW_FINITE_F128, "__powf128_finite");
147 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
148 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
149 setLibcallName(RTLIB::RINT_F128, "rintf128");
150 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
151 setLibcallName(RTLIB::ROUND_F128, "roundf128");
152 setLibcallName(RTLIB::ROUNDEVEN_F128, "roundevenf128");
153 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
154 setLibcallName(RTLIB::COPYSIGN_F128, "copysignf128");
155 setLibcallName(RTLIB::FMIN_F128, "fminf128");
156 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
157 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
158 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
159 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
160 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
161 setLibcallName(RTLIB::LDEXP_F128, "ldexpf128");
162 setLibcallName(RTLIB::FREXP_F128, "frexpf128");
163 }
164
165 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
166 if (TT.isPPC()) {
167 setLibcallName(RTLIB::ADD_F128, "__addkf3");
168 setLibcallName(RTLIB::SUB_F128, "__subkf3");
169 setLibcallName(RTLIB::MUL_F128, "__mulkf3");
170 setLibcallName(RTLIB::DIV_F128, "__divkf3");
171 setLibcallName(RTLIB::POWI_F128, "__powikf2");
172 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
173 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
174 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
175 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
176 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
177 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
178 setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
179 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
180 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
181 setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
182 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
183 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
184 setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
185 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
186 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
187 setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
188 setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
189 setLibcallName(RTLIB::UNE_F128, "__nekf2");
190 setLibcallName(RTLIB::OGE_F128, "__gekf2");
191 setLibcallName(RTLIB::OLT_F128, "__ltkf2");
192 setLibcallName(RTLIB::OLE_F128, "__lekf2");
193 setLibcallName(RTLIB::OGT_F128, "__gtkf2");
194 setLibcallName(RTLIB::UO_F128, "__unordkf2");
195 }
196
197 // A few names are different on particular architectures or environments.
198 if (TT.isOSDarwin()) {
199 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
200 // of the gnueabi-style __gnu_*_ieee.
201 // FIXME: What about other targets?
202 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
203 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
204
205 // Some darwins have an optimized __bzero/bzero function.
206 switch (TT.getArch()) {
207 case Triple::x86:
208 case Triple::x86_64:
209 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
210 setLibcallName(RTLIB::BZERO, "__bzero");
211 break;
212 case Triple::aarch64:
214 setLibcallName(RTLIB::BZERO, "bzero");
215 break;
216 default:
217 break;
218 }
219
220 if (darwinHasSinCos(TT)) {
221 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
222 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
223 if (TT.isWatchABI()) {
224 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
226 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
228 }
229 }
230 } else {
231 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
232 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
233 }
234
235 if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
236 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
237 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
238 setLibcallName(RTLIB::SINCOS_F64, "sincos");
239 setLibcallName(RTLIB::SINCOS_F80, "sincosl");
240 setLibcallName(RTLIB::SINCOS_F128, "sincosl");
241 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
242 }
243
244 if (TT.isPS()) {
245 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
246 setLibcallName(RTLIB::SINCOS_F64, "sincos");
247 }
248
249 if (TT.isOSOpenBSD()) {
250 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
251 }
252
253 if (TT.isOSWindows() && !TT.isOSCygMing()) {
254 setLibcallName(RTLIB::LDEXP_F32, nullptr);
255 setLibcallName(RTLIB::LDEXP_F80, nullptr);
256 setLibcallName(RTLIB::LDEXP_F128, nullptr);
257 setLibcallName(RTLIB::LDEXP_PPCF128, nullptr);
258
259 setLibcallName(RTLIB::FREXP_F32, nullptr);
260 setLibcallName(RTLIB::FREXP_F80, nullptr);
261 setLibcallName(RTLIB::FREXP_F128, nullptr);
262 setLibcallName(RTLIB::FREXP_PPCF128, nullptr);
263 }
264}
265
266/// GetFPLibCall - Helper to return the right libcall for the given floating
267/// point type, or UNKNOWN_LIBCALL if there is none.
269 RTLIB::Libcall Call_F32,
270 RTLIB::Libcall Call_F64,
271 RTLIB::Libcall Call_F80,
272 RTLIB::Libcall Call_F128,
273 RTLIB::Libcall Call_PPCF128) {
274 return
275 VT == MVT::f32 ? Call_F32 :
276 VT == MVT::f64 ? Call_F64 :
277 VT == MVT::f80 ? Call_F80 :
278 VT == MVT::f128 ? Call_F128 :
279 VT == MVT::ppcf128 ? Call_PPCF128 :
280 RTLIB::UNKNOWN_LIBCALL;
281}
282
283/// getFPEXT - Return the FPEXT_*_* value for the given types, or
284/// UNKNOWN_LIBCALL if there is none.
286 if (OpVT == MVT::f16) {
287 if (RetVT == MVT::f32)
288 return FPEXT_F16_F32;
289 if (RetVT == MVT::f64)
290 return FPEXT_F16_F64;
291 if (RetVT == MVT::f80)
292 return FPEXT_F16_F80;
293 if (RetVT == MVT::f128)
294 return FPEXT_F16_F128;
295 } else if (OpVT == MVT::f32) {
296 if (RetVT == MVT::f64)
297 return FPEXT_F32_F64;
298 if (RetVT == MVT::f128)
299 return FPEXT_F32_F128;
300 if (RetVT == MVT::ppcf128)
301 return FPEXT_F32_PPCF128;
302 } else if (OpVT == MVT::f64) {
303 if (RetVT == MVT::f128)
304 return FPEXT_F64_F128;
305 else if (RetVT == MVT::ppcf128)
306 return FPEXT_F64_PPCF128;
307 } else if (OpVT == MVT::f80) {
308 if (RetVT == MVT::f128)
309 return FPEXT_F80_F128;
310 }
311
312 return UNKNOWN_LIBCALL;
313}
314
315/// getFPROUND - Return the FPROUND_*_* value for the given types, or
316/// UNKNOWN_LIBCALL if there is none.
318 if (RetVT == MVT::f16) {
319 if (OpVT == MVT::f32)
320 return FPROUND_F32_F16;
321 if (OpVT == MVT::f64)
322 return FPROUND_F64_F16;
323 if (OpVT == MVT::f80)
324 return FPROUND_F80_F16;
325 if (OpVT == MVT::f128)
326 return FPROUND_F128_F16;
327 if (OpVT == MVT::ppcf128)
328 return FPROUND_PPCF128_F16;
329 } else if (RetVT == MVT::bf16) {
330 if (OpVT == MVT::f32)
331 return FPROUND_F32_BF16;
332 if (OpVT == MVT::f64)
333 return FPROUND_F64_BF16;
334 } else if (RetVT == MVT::f32) {
335 if (OpVT == MVT::f64)
336 return FPROUND_F64_F32;
337 if (OpVT == MVT::f80)
338 return FPROUND_F80_F32;
339 if (OpVT == MVT::f128)
340 return FPROUND_F128_F32;
341 if (OpVT == MVT::ppcf128)
342 return FPROUND_PPCF128_F32;
343 } else if (RetVT == MVT::f64) {
344 if (OpVT == MVT::f80)
345 return FPROUND_F80_F64;
346 if (OpVT == MVT::f128)
347 return FPROUND_F128_F64;
348 if (OpVT == MVT::ppcf128)
349 return FPROUND_PPCF128_F64;
350 } else if (RetVT == MVT::f80) {
351 if (OpVT == MVT::f128)
352 return FPROUND_F128_F80;
353 }
354
355 return UNKNOWN_LIBCALL;
356}
357
358/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
359/// UNKNOWN_LIBCALL if there is none.
361 if (OpVT == MVT::f16) {
362 if (RetVT == MVT::i32)
363 return FPTOSINT_F16_I32;
364 if (RetVT == MVT::i64)
365 return FPTOSINT_F16_I64;
366 if (RetVT == MVT::i128)
367 return FPTOSINT_F16_I128;
368 } else if (OpVT == MVT::f32) {
369 if (RetVT == MVT::i32)
370 return FPTOSINT_F32_I32;
371 if (RetVT == MVT::i64)
372 return FPTOSINT_F32_I64;
373 if (RetVT == MVT::i128)
374 return FPTOSINT_F32_I128;
375 } else if (OpVT == MVT::f64) {
376 if (RetVT == MVT::i32)
377 return FPTOSINT_F64_I32;
378 if (RetVT == MVT::i64)
379 return FPTOSINT_F64_I64;
380 if (RetVT == MVT::i128)
381 return FPTOSINT_F64_I128;
382 } else if (OpVT == MVT::f80) {
383 if (RetVT == MVT::i32)
384 return FPTOSINT_F80_I32;
385 if (RetVT == MVT::i64)
386 return FPTOSINT_F80_I64;
387 if (RetVT == MVT::i128)
388 return FPTOSINT_F80_I128;
389 } else if (OpVT == MVT::f128) {
390 if (RetVT == MVT::i32)
391 return FPTOSINT_F128_I32;
392 if (RetVT == MVT::i64)
393 return FPTOSINT_F128_I64;
394 if (RetVT == MVT::i128)
395 return FPTOSINT_F128_I128;
396 } else if (OpVT == MVT::ppcf128) {
397 if (RetVT == MVT::i32)
398 return FPTOSINT_PPCF128_I32;
399 if (RetVT == MVT::i64)
400 return FPTOSINT_PPCF128_I64;
401 if (RetVT == MVT::i128)
402 return FPTOSINT_PPCF128_I128;
403 }
404 return UNKNOWN_LIBCALL;
405}
406
407/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
408/// UNKNOWN_LIBCALL if there is none.
410 if (OpVT == MVT::f16) {
411 if (RetVT == MVT::i32)
412 return FPTOUINT_F16_I32;
413 if (RetVT == MVT::i64)
414 return FPTOUINT_F16_I64;
415 if (RetVT == MVT::i128)
416 return FPTOUINT_F16_I128;
417 } else if (OpVT == MVT::f32) {
418 if (RetVT == MVT::i32)
419 return FPTOUINT_F32_I32;
420 if (RetVT == MVT::i64)
421 return FPTOUINT_F32_I64;
422 if (RetVT == MVT::i128)
423 return FPTOUINT_F32_I128;
424 } else if (OpVT == MVT::f64) {
425 if (RetVT == MVT::i32)
426 return FPTOUINT_F64_I32;
427 if (RetVT == MVT::i64)
428 return FPTOUINT_F64_I64;
429 if (RetVT == MVT::i128)
430 return FPTOUINT_F64_I128;
431 } else if (OpVT == MVT::f80) {
432 if (RetVT == MVT::i32)
433 return FPTOUINT_F80_I32;
434 if (RetVT == MVT::i64)
435 return FPTOUINT_F80_I64;
436 if (RetVT == MVT::i128)
437 return FPTOUINT_F80_I128;
438 } else if (OpVT == MVT::f128) {
439 if (RetVT == MVT::i32)
440 return FPTOUINT_F128_I32;
441 if (RetVT == MVT::i64)
442 return FPTOUINT_F128_I64;
443 if (RetVT == MVT::i128)
444 return FPTOUINT_F128_I128;
445 } else if (OpVT == MVT::ppcf128) {
446 if (RetVT == MVT::i32)
447 return FPTOUINT_PPCF128_I32;
448 if (RetVT == MVT::i64)
449 return FPTOUINT_PPCF128_I64;
450 if (RetVT == MVT::i128)
451 return FPTOUINT_PPCF128_I128;
452 }
453 return UNKNOWN_LIBCALL;
454}
455
456/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
457/// UNKNOWN_LIBCALL if there is none.
459 if (OpVT == MVT::i32) {
460 if (RetVT == MVT::f16)
461 return SINTTOFP_I32_F16;
462 if (RetVT == MVT::f32)
463 return SINTTOFP_I32_F32;
464 if (RetVT == MVT::f64)
465 return SINTTOFP_I32_F64;
466 if (RetVT == MVT::f80)
467 return SINTTOFP_I32_F80;
468 if (RetVT == MVT::f128)
469 return SINTTOFP_I32_F128;
470 if (RetVT == MVT::ppcf128)
471 return SINTTOFP_I32_PPCF128;
472 } else if (OpVT == MVT::i64) {
473 if (RetVT == MVT::f16)
474 return SINTTOFP_I64_F16;
475 if (RetVT == MVT::f32)
476 return SINTTOFP_I64_F32;
477 if (RetVT == MVT::f64)
478 return SINTTOFP_I64_F64;
479 if (RetVT == MVT::f80)
480 return SINTTOFP_I64_F80;
481 if (RetVT == MVT::f128)
482 return SINTTOFP_I64_F128;
483 if (RetVT == MVT::ppcf128)
484 return SINTTOFP_I64_PPCF128;
485 } else if (OpVT == MVT::i128) {
486 if (RetVT == MVT::f16)
487 return SINTTOFP_I128_F16;
488 if (RetVT == MVT::f32)
489 return SINTTOFP_I128_F32;
490 if (RetVT == MVT::f64)
491 return SINTTOFP_I128_F64;
492 if (RetVT == MVT::f80)
493 return SINTTOFP_I128_F80;
494 if (RetVT == MVT::f128)
495 return SINTTOFP_I128_F128;
496 if (RetVT == MVT::ppcf128)
497 return SINTTOFP_I128_PPCF128;
498 }
499 return UNKNOWN_LIBCALL;
500}
501
502/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
503/// UNKNOWN_LIBCALL if there is none.
505 if (OpVT == MVT::i32) {
506 if (RetVT == MVT::f16)
507 return UINTTOFP_I32_F16;
508 if (RetVT == MVT::f32)
509 return UINTTOFP_I32_F32;
510 if (RetVT == MVT::f64)
511 return UINTTOFP_I32_F64;
512 if (RetVT == MVT::f80)
513 return UINTTOFP_I32_F80;
514 if (RetVT == MVT::f128)
515 return UINTTOFP_I32_F128;
516 if (RetVT == MVT::ppcf128)
517 return UINTTOFP_I32_PPCF128;
518 } else if (OpVT == MVT::i64) {
519 if (RetVT == MVT::f16)
520 return UINTTOFP_I64_F16;
521 if (RetVT == MVT::f32)
522 return UINTTOFP_I64_F32;
523 if (RetVT == MVT::f64)
524 return UINTTOFP_I64_F64;
525 if (RetVT == MVT::f80)
526 return UINTTOFP_I64_F80;
527 if (RetVT == MVT::f128)
528 return UINTTOFP_I64_F128;
529 if (RetVT == MVT::ppcf128)
530 return UINTTOFP_I64_PPCF128;
531 } else if (OpVT == MVT::i128) {
532 if (RetVT == MVT::f16)
533 return UINTTOFP_I128_F16;
534 if (RetVT == MVT::f32)
535 return UINTTOFP_I128_F32;
536 if (RetVT == MVT::f64)
537 return UINTTOFP_I128_F64;
538 if (RetVT == MVT::f80)
539 return UINTTOFP_I128_F80;
540 if (RetVT == MVT::f128)
541 return UINTTOFP_I128_F128;
542 if (RetVT == MVT::ppcf128)
543 return UINTTOFP_I128_PPCF128;
544 }
545 return UNKNOWN_LIBCALL;
546}
547
549 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
550 POWI_PPCF128);
551}
552
554 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,
555 LDEXP_PPCF128);
556}
557
559 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,
560 FREXP_PPCF128);
561}
562
564 AtomicOrdering Order,
565 uint64_t MemSize) {
566 unsigned ModeN, ModelN;
567 switch (MemSize) {
568 case 1:
569 ModeN = 0;
570 break;
571 case 2:
572 ModeN = 1;
573 break;
574 case 4:
575 ModeN = 2;
576 break;
577 case 8:
578 ModeN = 3;
579 break;
580 case 16:
581 ModeN = 4;
582 break;
583 default:
584 return RTLIB::UNKNOWN_LIBCALL;
585 }
586
587 switch (Order) {
589 ModelN = 0;
590 break;
592 ModelN = 1;
593 break;
595 ModelN = 2;
596 break;
599 ModelN = 3;
600 break;
601 default:
602 return UNKNOWN_LIBCALL;
603 }
604
605 return LC[ModeN][ModelN];
606}
607
609 MVT VT) {
610 if (!VT.isScalarInteger())
611 return UNKNOWN_LIBCALL;
612 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
613
614#define LCALLS(A, B) \
615 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
616#define LCALL5(A) \
617 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
618 switch (Opc) {
620 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
621 return getOutlineAtomicHelper(LC, Order, MemSize);
622 }
623 case ISD::ATOMIC_SWAP: {
624 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
625 return getOutlineAtomicHelper(LC, Order, MemSize);
626 }
628 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
629 return getOutlineAtomicHelper(LC, Order, MemSize);
630 }
631 case ISD::ATOMIC_LOAD_OR: {
632 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
633 return getOutlineAtomicHelper(LC, Order, MemSize);
634 }
636 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
637 return getOutlineAtomicHelper(LC, Order, MemSize);
638 }
640 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
641 return getOutlineAtomicHelper(LC, Order, MemSize);
642 }
643 default:
644 return UNKNOWN_LIBCALL;
645 }
646#undef LCALLS
647#undef LCALL5
648}
649
651#define OP_TO_LIBCALL(Name, Enum) \
652 case Name: \
653 switch (VT.SimpleTy) { \
654 default: \
655 return UNKNOWN_LIBCALL; \
656 case MVT::i8: \
657 return Enum##_1; \
658 case MVT::i16: \
659 return Enum##_2; \
660 case MVT::i32: \
661 return Enum##_4; \
662 case MVT::i64: \
663 return Enum##_8; \
664 case MVT::i128: \
665 return Enum##_16; \
666 }
667
668 switch (Opc) {
669 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
670 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
671 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
672 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
673 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
674 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
675 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
676 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
677 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
678 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
679 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
680 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
681 }
682
683#undef OP_TO_LIBCALL
684
685 return UNKNOWN_LIBCALL;
686}
687
689 switch (ElementSize) {
690 case 1:
691 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
692 case 2:
693 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
694 case 4:
695 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
696 case 8:
697 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
698 case 16:
699 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
700 default:
701 return UNKNOWN_LIBCALL;
702 }
703}
704
706 switch (ElementSize) {
707 case 1:
708 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
709 case 2:
710 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
711 case 4:
712 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
713 case 8:
714 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
715 case 16:
716 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
717 default:
718 return UNKNOWN_LIBCALL;
719 }
720}
721
723 switch (ElementSize) {
724 case 1:
725 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
726 case 2:
727 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
728 case 4:
729 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
730 case 8:
731 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
732 case 16:
733 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
734 default:
735 return UNKNOWN_LIBCALL;
736 }
737}
738
739/// InitCmpLibcallCCs - Set default comparison libcall CC.
741 std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID);
742 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
743 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
744 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
745 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
746 CCs[RTLIB::UNE_F32] = ISD::SETNE;
747 CCs[RTLIB::UNE_F64] = ISD::SETNE;
748 CCs[RTLIB::UNE_F128] = ISD::SETNE;
749 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
750 CCs[RTLIB::OGE_F32] = ISD::SETGE;
751 CCs[RTLIB::OGE_F64] = ISD::SETGE;
752 CCs[RTLIB::OGE_F128] = ISD::SETGE;
753 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
754 CCs[RTLIB::OLT_F32] = ISD::SETLT;
755 CCs[RTLIB::OLT_F64] = ISD::SETLT;
756 CCs[RTLIB::OLT_F128] = ISD::SETLT;
757 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
758 CCs[RTLIB::OLE_F32] = ISD::SETLE;
759 CCs[RTLIB::OLE_F64] = ISD::SETLE;
760 CCs[RTLIB::OLE_F128] = ISD::SETLE;
761 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
762 CCs[RTLIB::OGT_F32] = ISD::SETGT;
763 CCs[RTLIB::OGT_F64] = ISD::SETGT;
764 CCs[RTLIB::OGT_F128] = ISD::SETGT;
765 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
766 CCs[RTLIB::UO_F32] = ISD::SETNE;
767 CCs[RTLIB::UO_F64] = ISD::SETNE;
768 CCs[RTLIB::UO_F128] = ISD::SETNE;
769 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
770}
771
772/// NOTE: The TargetMachine owns TLOF.
774 initActions();
775
776 // Perform these initializations only once.
782 HasMultipleConditionRegisters = false;
783 HasExtractBitsInsn = false;
784 JumpIsExpensive = JumpIsExpensiveOverride;
786 EnableExtLdPromotion = false;
787 StackPointerRegisterToSaveRestore = 0;
788 BooleanContents = UndefinedBooleanContent;
789 BooleanFloatContents = UndefinedBooleanContent;
790 BooleanVectorContents = UndefinedBooleanContent;
791 SchedPreferenceInfo = Sched::ILP;
794 MaxBytesForAlignment = 0;
795 MaxAtomicSizeInBitsSupported = 0;
796
797 // Assume that even with libcalls, no target supports wider than 128 bit
798 // division.
799 MaxDivRemBitWidthSupported = 128;
800
801 MaxLargeFPConvertBitWidthSupported = llvm::IntegerType::MAX_INT_BITS;
802
803 MinCmpXchgSizeInBits = 0;
804 SupportsUnalignedAtomics = false;
805
806 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
807
808 InitLibcalls(TM.getTargetTriple());
809 InitCmpLibcallCCs(CmpLibcallCCs);
810}
811
813 // All operations default to being supported.
814 memset(OpActions, 0, sizeof(OpActions));
815 memset(LoadExtActions, 0, sizeof(LoadExtActions));
816 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
817 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
818 memset(CondCodeActions, 0, sizeof(CondCodeActions));
819 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
820 std::fill(std::begin(TargetDAGCombineArray),
821 std::end(TargetDAGCombineArray), 0);
822
823 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
824 // remove this and targets should individually set these types if not legal.
827 for (MVT VT : {MVT::i2, MVT::i4})
828 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
829 }
830 for (MVT AVT : MVT::all_valuetypes()) {
831 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
832 setTruncStoreAction(AVT, VT, Expand);
835 }
836 }
837 for (unsigned IM = (unsigned)ISD::PRE_INC;
838 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
839 for (MVT VT : {MVT::i2, MVT::i4}) {
844 }
845 }
846
847 for (MVT VT : MVT::fp_valuetypes()) {
848 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
849 if (IntVT.isValid()) {
852 }
853 }
854
855 // Set default actions for various operations.
856 for (MVT VT : MVT::all_valuetypes()) {
857 // Default all indexed load / store to expand.
858 for (unsigned IM = (unsigned)ISD::PRE_INC;
859 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
864 }
865
866 // Most backends expect to see the node which just returns the value loaded.
868
869 // These operations default to expand.
887 VT, Expand);
888
889 // Overflow operations default to expand
892 VT, Expand);
893
894 // Carry-using overflow operations default to expand.
897 VT, Expand);
898
899 // ADDC/ADDE/SUBC/SUBE default to expand.
901 Expand);
902
903 // Halving adds
906 Expand);
907
908 // Absolute difference
910
911 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
913 Expand);
914
916
917 // These library functions default to expand.
919 Expand);
920
921 // These operations default to expand for vector types.
922 if (VT.isVector())
927 VT, Expand);
928
929 // Constrained floating-point operations default to expand.
930#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
931 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
932#include "llvm/IR/ConstrainedOps.def"
933
934 // For most targets @llvm.get.dynamic.area.offset just returns 0.
936
937 // Vector reduction default to expand.
945 VT, Expand);
946
947 // Named vector shuffles default to expand.
949
950 // VP operations default to expand.
951#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
952 setOperationAction(ISD::SDOPC, VT, Expand);
953#include "llvm/IR/VPIntrinsics.def"
954
955 // FP environment operations default to expand.
959 }
960
961 // Most targets ignore the @llvm.prefetch intrinsic.
963
964 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
966
967 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
969
970 // ConstantFP nodes default to expand. Targets can either change this to
971 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
972 // to optimize expansions for certain constants.
974 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
975 Expand);
976
977 // These library functions default to expand.
982 {MVT::f32, MVT::f64, MVT::f128}, Expand);
983
984 // Default ISD::TRAP to expand (which turns it into abort).
985 setOperationAction(ISD::TRAP, MVT::Other, Expand);
986
987 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
988 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
990
992
995
996 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
999 }
1001}
1002
1004 EVT) const {
1005 return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
1006}
1007
1009 bool LegalTypes) const {
1010 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1011 if (LHSTy.isVector())
1012 return LHSTy;
1013 MVT ShiftVT =
1014 LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) : getPointerTy(DL);
1015 // If any possible shift value won't fit in the prefered type, just use
1016 // something safe. Assume it will be legalized when the shift is expanded.
1017 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits()))
1018 ShiftVT = MVT::i32;
1019 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1020 "ShiftVT is still too small!");
1021 return ShiftVT;
1022}
1023
1024bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1025 assert(isTypeLegal(VT));
1026 switch (Op) {
1027 default:
1028 return false;
1029 case ISD::SDIV:
1030 case ISD::UDIV:
1031 case ISD::SREM:
1032 case ISD::UREM:
1033 return true;
1034 }
1035}
1036
1038 unsigned DestAS) const {
1039 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1040}
1041
1043 // If the command-line option was specified, ignore this request.
1044 if (!JumpIsExpensiveOverride.getNumOccurrences())
1045 JumpIsExpensive = isExpensive;
1046}
1047
1050 // If this is a simple type, use the ComputeRegisterProp mechanism.
1051 if (VT.isSimple()) {
1052 MVT SVT = VT.getSimpleVT();
1053 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1054 MVT NVT = TransformToType[SVT.SimpleTy];
1055 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1056
1057 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1058 LA == TypeSoftPromoteHalf ||
1059 (NVT.isVector() ||
1060 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1061 "Promote may not follow Expand or Promote");
1062
1063 if (LA == TypeSplitVector)
1064 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1065 if (LA == TypeScalarizeVector)
1066 return LegalizeKind(LA, SVT.getVectorElementType());
1067 return LegalizeKind(LA, NVT);
1068 }
1069
1070 // Handle Extended Scalar Types.
1071 if (!VT.isVector()) {
1072 assert(VT.isInteger() && "Float types must be simple");
1073 unsigned BitSize = VT.getSizeInBits();
1074 // First promote to a power-of-two size, then expand if necessary.
1075 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1077 assert(NVT != VT && "Unable to round integer VT");
1078 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1079 // Avoid multi-step promotion.
1080 if (NextStep.first == TypePromoteInteger)
1081 return NextStep;
1082 // Return rounded integer type.
1083 return LegalizeKind(TypePromoteInteger, NVT);
1084 }
1085
1088 }
1089
1090 // Handle vector types.
1091 ElementCount NumElts = VT.getVectorElementCount();
1092 EVT EltVT = VT.getVectorElementType();
1093
1094 // Vectors with only one element are always scalarized.
1095 if (NumElts.isScalar())
1096 return LegalizeKind(TypeScalarizeVector, EltVT);
1097
1098 // Try to widen vector elements until the element type is a power of two and
1099 // promote it to a legal type later on, for example:
1100 // <3 x i8> -> <4 x i8> -> <4 x i32>
1101 if (EltVT.isInteger()) {
1102 // Vectors with a number of elements that is not a power of two are always
1103 // widened, for example <3 x i8> -> <4 x i8>.
1104 if (!VT.isPow2VectorType()) {
1105 NumElts = NumElts.coefficientNextPowerOf2();
1106 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1107 return LegalizeKind(TypeWidenVector, NVT);
1108 }
1109
1110 // Examine the element type.
1112
1113 // If type is to be expanded, split the vector.
1114 // <4 x i140> -> <2 x i140>
1115 if (LK.first == TypeExpandInteger) {
1120 }
1121
1122 // Promote the integer element types until a legal vector type is found
1123 // or until the element integer type is too big. If a legal type was not
1124 // found, fallback to the usual mechanism of widening/splitting the
1125 // vector.
1126 EVT OldEltVT = EltVT;
1127 while (true) {
1128 // Increase the bitwidth of the element to the next pow-of-two
1129 // (which is greater than 8 bits).
1130 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1132
1133 // Stop trying when getting a non-simple element type.
1134 // Note that vector elements may be greater than legal vector element
1135 // types. Example: X86 XMM registers hold 64bit element on 32bit
1136 // systems.
1137 if (!EltVT.isSimple())
1138 break;
1139
1140 // Build a new vector type and check if it is legal.
1141 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1142 // Found a legal promoted vector type.
1143 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1145 EVT::getVectorVT(Context, EltVT, NumElts));
1146 }
1147
1148 // Reset the type to the unexpanded type if we did not find a legal vector
1149 // type with a promoted vector element type.
1150 EltVT = OldEltVT;
1151 }
1152
1153 // Try to widen the vector until a legal type is found.
1154 // If there is no wider legal type, split the vector.
1155 while (true) {
1156 // Round up to the next power of 2.
1157 NumElts = NumElts.coefficientNextPowerOf2();
1158
1159 // If there is no simple vector type with this many elements then there
1160 // cannot be a larger legal vector type. Note that this assumes that
1161 // there are no skipped intermediate vector types in the simple types.
1162 if (!EltVT.isSimple())
1163 break;
1164 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1165 if (LargerVector == MVT())
1166 break;
1167
1168 // If this type is legal then widen the vector.
1169 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1170 return LegalizeKind(TypeWidenVector, LargerVector);
1171 }
1172
1173 // Widen odd vectors to next power of two.
1174 if (!VT.isPow2VectorType()) {
1175 EVT NVT = VT.getPow2VectorType(Context);
1176 return LegalizeKind(TypeWidenVector, NVT);
1177 }
1178
1181
1182 // Vectors with illegal element types are expanded.
1183 EVT NVT = EVT::getVectorVT(Context, EltVT,
1185 return LegalizeKind(TypeSplitVector, NVT);
1186}
1187
1188static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1189 unsigned &NumIntermediates,
1190 MVT &RegisterVT,
1191 TargetLoweringBase *TLI) {
1192 // Figure out the right, legal destination reg to copy into.
1194 MVT EltTy = VT.getVectorElementType();
1195
1196 unsigned NumVectorRegs = 1;
1197
1198 // Scalable vectors cannot be scalarized, so splitting or widening is
1199 // required.
1200 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1202 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1203
1204 // FIXME: We don't support non-power-of-2-sized vectors for now.
1205 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1206 if (!isPowerOf2_32(EC.getKnownMinValue())) {
1207 // Split EC to unit size (scalable property is preserved).
1208 NumVectorRegs = EC.getKnownMinValue();
1209 EC = ElementCount::getFixed(1);
1210 }
1211
1212 // Divide the input until we get to a supported size. This will
1213 // always end up with an EC that represent a scalar or a scalable
1214 // scalar.
1215 while (EC.getKnownMinValue() > 1 &&
1216 !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1217 EC = EC.divideCoefficientBy(2);
1218 NumVectorRegs <<= 1;
1219 }
1220
1221 NumIntermediates = NumVectorRegs;
1222
1223 MVT NewVT = MVT::getVectorVT(EltTy, EC);
1224 if (!TLI->isTypeLegal(NewVT))
1225 NewVT = EltTy;
1226 IntermediateVT = NewVT;
1227
1228 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1229
1230 // Convert sizes such as i33 to i64.
1231 LaneSizeInBits = llvm::bit_ceil(LaneSizeInBits);
1232
1233 MVT DestVT = TLI->getRegisterType(NewVT);
1234 RegisterVT = DestVT;
1235 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1236 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1237
1238 // Otherwise, promotion or legal types use the same number of registers as
1239 // the vector decimated to the appropriate level.
1240 return NumVectorRegs;
1241}
1242
1243/// isLegalRC - Return true if the value types that can be represented by the
1244/// specified register class are all legal.
1246 const TargetRegisterClass &RC) const {
1247 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1248 if (isTypeLegal(*I))
1249 return true;
1250 return false;
1251}
1252
1253/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1254/// sequence of memory operands that is recognized by PrologEpilogInserter.
1257 MachineBasicBlock *MBB) const {
1258 MachineInstr *MI = &InitialMI;
1259 MachineFunction &MF = *MI->getMF();
1260 MachineFrameInfo &MFI = MF.getFrameInfo();
1261
1262 // We're handling multiple types of operands here:
1263 // PATCHPOINT MetaArgs - live-in, read only, direct
1264 // STATEPOINT Deopt Spill - live-through, read only, indirect
1265 // STATEPOINT Deopt Alloca - live-through, read only, direct
1266 // (We're currently conservative and mark the deopt slots read/write in
1267 // practice.)
1268 // STATEPOINT GC Spill - live-through, read/write, indirect
1269 // STATEPOINT GC Alloca - live-through, read/write, direct
1270 // The live-in vs live-through is handled already (the live through ones are
1271 // all stack slots), but we need to handle the different type of stackmap
1272 // operands and memory effects here.
1273
1274 if (llvm::none_of(MI->operands(),
1275 [](MachineOperand &Operand) { return Operand.isFI(); }))
1276 return MBB;
1277
1278 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1279
1280 // Inherit previous memory operands.
1281 MIB.cloneMemRefs(*MI);
1282
1283 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1284 MachineOperand &MO = MI->getOperand(i);
1285 if (!MO.isFI()) {
1286 // Index of Def operand this Use it tied to.
1287 // Since Defs are coming before Uses, if Use is tied, then
1288 // index of Def must be smaller that index of that Use.
1289 // Also, Defs preserve their position in new MI.
1290 unsigned TiedTo = i;
1291 if (MO.isReg() && MO.isTied())
1292 TiedTo = MI->findTiedOperandIdx(i);
1293 MIB.add(MO);
1294 if (TiedTo < i)
1295 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1296 continue;
1297 }
1298
1299 // foldMemoryOperand builds a new MI after replacing a single FI operand
1300 // with the canonical set of five x86 addressing-mode operands.
1301 int FI = MO.getIndex();
1302
1303 // Add frame index operands recognized by stackmaps.cpp
1305 // indirect-mem-ref tag, size, #FI, offset.
1306 // Used for spills inserted by StatepointLowering. This codepath is not
1307 // used for patchpoints/stackmaps at all, for these spilling is done via
1308 // foldMemoryOperand callback only.
1309 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1310 MIB.addImm(StackMaps::IndirectMemRefOp);
1311 MIB.addImm(MFI.getObjectSize(FI));
1312 MIB.add(MO);
1313 MIB.addImm(0);
1314 } else {
1315 // direct-mem-ref tag, #FI, offset.
1316 // Used by patchpoint, and direct alloca arguments to statepoints
1317 MIB.addImm(StackMaps::DirectMemRefOp);
1318 MIB.add(MO);
1319 MIB.addImm(0);
1320 }
1321
1322 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1323
1324 // Add a new memory operand for this FI.
1325 assert(MFI.getObjectOffset(FI) != -1);
1326
1327 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1328 // PATCHPOINT should be updated to do the same. (TODO)
1329 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1330 auto Flags = MachineMemOperand::MOLoad;
1332 MachinePointerInfo::getFixedStack(MF, FI), Flags,
1334 MIB->addMemOperand(MF, MMO);
1335 }
1336 }
1338 MI->eraseFromParent();
1339 return MBB;
1340}
1341
1342/// findRepresentativeClass - Return the largest legal super-reg register class
1343/// of the register class for the specified type and its associated "cost".
1344// This function is in TargetLowering because it uses RegClassForVT which would
1345// need to be moved to TargetRegisterInfo and would necessitate moving
1346// isTypeLegal over as well - a massive change that would just require
1347// TargetLowering having a TargetRegisterInfo class member that it would use.
1348std::pair<const TargetRegisterClass *, uint8_t>
1350 MVT VT) const {
1351 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1352 if (!RC)
1353 return std::make_pair(RC, 0);
1354
1355 // Compute the set of all super-register classes.
1356 BitVector SuperRegRC(TRI->getNumRegClasses());
1357 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1358 SuperRegRC.setBitsInMask(RCI.getMask());
1359
1360 // Find the first legal register class with the largest spill size.
1361 const TargetRegisterClass *BestRC = RC;
1362 for (unsigned i : SuperRegRC.set_bits()) {
1363 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1364 // We want the largest possible spill size.
1365 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1366 continue;
1367 if (!isLegalRC(*TRI, *SuperRC))
1368 continue;
1369 BestRC = SuperRC;
1370 }
1371 return std::make_pair(BestRC, 1);
1372}
1373
1374/// computeRegisterProperties - Once all of the register classes are added,
1375/// this allows us to compute derived properties we expose.
1377 const TargetRegisterInfo *TRI) {
1379 "Too many value types for ValueTypeActions to hold!");
1380
1381 // Everything defaults to needing one register.
1382 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1383 NumRegistersForVT[i] = 1;
1384 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1385 }
1386 // ...except isVoid, which doesn't need any registers.
1387 NumRegistersForVT[MVT::isVoid] = 0;
1388
1389 // Find the largest integer register class.
1390 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1391 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1392 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1393
1394 // Every integer value type larger than this largest register takes twice as
1395 // many registers to represent as the previous ValueType.
1396 for (unsigned ExpandedReg = LargestIntReg + 1;
1397 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1398 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1399 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1400 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1401 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1403 }
1404
1405 // Inspect all of the ValueType's smaller than the largest integer
1406 // register to see which ones need promotion.
1407 unsigned LegalIntReg = LargestIntReg;
1408 for (unsigned IntReg = LargestIntReg - 1;
1409 IntReg >= (unsigned)MVT::i1; --IntReg) {
1410 MVT IVT = (MVT::SimpleValueType)IntReg;
1411 if (isTypeLegal(IVT)) {
1412 LegalIntReg = IntReg;
1413 } else {
1414 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1415 (MVT::SimpleValueType)LegalIntReg;
1416 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1417 }
1418 }
1419
1420 // ppcf128 type is really two f64's.
1421 if (!isTypeLegal(MVT::ppcf128)) {
1422 if (isTypeLegal(MVT::f64)) {
1423 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1424 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1425 TransformToType[MVT::ppcf128] = MVT::f64;
1426 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1427 } else {
1428 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1429 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1430 TransformToType[MVT::ppcf128] = MVT::i128;
1431 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1432 }
1433 }
1434
1435 // Decide how to handle f128. If the target does not have native f128 support,
1436 // expand it to i128 and we will be generating soft float library calls.
1437 if (!isTypeLegal(MVT::f128)) {
1438 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1439 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1440 TransformToType[MVT::f128] = MVT::i128;
1441 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1442 }
1443
1444 // Decide how to handle f80. If the target does not have native f80 support,
1445 // expand it to i96 and we will be generating soft float library calls.
1446 if (!isTypeLegal(MVT::f80)) {
1447 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1448 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1449 TransformToType[MVT::f80] = MVT::i32;
1450 ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat);
1451 }
1452
1453 // Decide how to handle f64. If the target does not have native f64 support,
1454 // expand it to i64 and we will be generating soft float library calls.
1455 if (!isTypeLegal(MVT::f64)) {
1456 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1457 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1458 TransformToType[MVT::f64] = MVT::i64;
1459 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1460 }
1461
1462 // Decide how to handle f32. If the target does not have native f32 support,
1463 // expand it to i32 and we will be generating soft float library calls.
1464 if (!isTypeLegal(MVT::f32)) {
1465 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1466 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1467 TransformToType[MVT::f32] = MVT::i32;
1468 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1469 }
1470
1471 // Decide how to handle f16. If the target does not have native f16 support,
1472 // promote it to f32, because there are no f16 library calls (except for
1473 // conversions).
1474 if (!isTypeLegal(MVT::f16)) {
1475 // Allow targets to control how we legalize half.
1476 bool SoftPromoteHalfType = softPromoteHalfType();
1477 bool UseFPRegsForHalfType = !SoftPromoteHalfType || useFPRegsForHalfType();
1478
1479 if (!UseFPRegsForHalfType) {
1480 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1481 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1482 } else {
1483 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1484 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1485 }
1486 TransformToType[MVT::f16] = MVT::f32;
1487 if (SoftPromoteHalfType) {
1488 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1489 } else {
1490 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1491 }
1492 }
1493
1494 // Decide how to handle bf16. If the target does not have native bf16 support,
1495 // promote it to f32, because there are no bf16 library calls (except for
1496 // converting from f32 to bf16).
1497 if (!isTypeLegal(MVT::bf16)) {
1498 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1499 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1500 TransformToType[MVT::bf16] = MVT::f32;
1501 ValueTypeActions.setTypeAction(MVT::bf16, TypeSoftPromoteHalf);
1502 }
1503
1504 // Loop over all of the vector value types to see which need transformations.
1505 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1506 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1507 MVT VT = (MVT::SimpleValueType) i;
1508 if (isTypeLegal(VT))
1509 continue;
1510
1511 MVT EltVT = VT.getVectorElementType();
1513 bool IsLegalWiderType = false;
1514 bool IsScalable = VT.isScalableVector();
1515 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1516 switch (PreferredAction) {
1517 case TypePromoteInteger: {
1518 MVT::SimpleValueType EndVT = IsScalable ?
1519 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1520 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1521 // Try to promote the elements of integer vectors. If no legal
1522 // promotion was found, fall through to the widen-vector method.
1523 for (unsigned nVT = i + 1;
1524 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1525 MVT SVT = (MVT::SimpleValueType) nVT;
1526 // Promote vectors of integers to vectors with the same number
1527 // of elements, with a wider element type.
1528 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1529 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1530 TransformToType[i] = SVT;
1531 RegisterTypeForVT[i] = SVT;
1532 NumRegistersForVT[i] = 1;
1533 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1534 IsLegalWiderType = true;
1535 break;
1536 }
1537 }
1538 if (IsLegalWiderType)
1539 break;
1540 [[fallthrough]];
1541 }
1542
1543 case TypeWidenVector:
1544 if (isPowerOf2_32(EC.getKnownMinValue())) {
1545 // Try to widen the vector.
1546 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1547 MVT SVT = (MVT::SimpleValueType) nVT;
1548 if (SVT.getVectorElementType() == EltVT &&
1549 SVT.isScalableVector() == IsScalable &&
1551 EC.getKnownMinValue() &&
1552 isTypeLegal(SVT)) {
1553 TransformToType[i] = SVT;
1554 RegisterTypeForVT[i] = SVT;
1555 NumRegistersForVT[i] = 1;
1556 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1557 IsLegalWiderType = true;
1558 break;
1559 }
1560 }
1561 if (IsLegalWiderType)
1562 break;
1563 } else {
1564 // Only widen to the next power of 2 to keep consistency with EVT.
1565 MVT NVT = VT.getPow2VectorType();
1566 if (isTypeLegal(NVT)) {
1567 TransformToType[i] = NVT;
1568 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1569 RegisterTypeForVT[i] = NVT;
1570 NumRegistersForVT[i] = 1;
1571 break;
1572 }
1573 }
1574 [[fallthrough]];
1575
1576 case TypeSplitVector:
1577 case TypeScalarizeVector: {
1578 MVT IntermediateVT;
1579 MVT RegisterVT;
1580 unsigned NumIntermediates;
1581 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1582 NumIntermediates, RegisterVT, this);
1583 NumRegistersForVT[i] = NumRegisters;
1584 assert(NumRegistersForVT[i] == NumRegisters &&
1585 "NumRegistersForVT size cannot represent NumRegisters!");
1586 RegisterTypeForVT[i] = RegisterVT;
1587
1588 MVT NVT = VT.getPow2VectorType();
1589 if (NVT == VT) {
1590 // Type is already a power of 2. The default action is to split.
1591 TransformToType[i] = MVT::Other;
1592 if (PreferredAction == TypeScalarizeVector)
1593 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1594 else if (PreferredAction == TypeSplitVector)
1595 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1596 else if (EC.getKnownMinValue() > 1)
1597 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1598 else
1599 ValueTypeActions.setTypeAction(VT, EC.isScalable()
1602 } else {
1603 TransformToType[i] = NVT;
1604 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1605 }
1606 break;
1607 }
1608 default:
1609 llvm_unreachable("Unknown vector legalization action!");
1610 }
1611 }
1612
1613 // Determine the 'representative' register class for each value type.
1614 // An representative register class is the largest (meaning one which is
1615 // not a sub-register class / subreg register class) legal register class for
1616 // a group of value types. For example, on i386, i8, i16, and i32
1617 // representative would be GR32; while on x86_64 it's GR64.
1618 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1619 const TargetRegisterClass* RRC;
1620 uint8_t Cost;
1622 RepRegClassForVT[i] = RRC;
1623 RepRegClassCostForVT[i] = Cost;
1624 }
1625}
1626
1628 EVT VT) const {
1629 assert(!VT.isVector() && "No default SetCC type for vectors!");
1630 return getPointerTy(DL).SimpleTy;
1631}
1632
1634 return MVT::i32; // return the default value
1635}
1636
1637/// getVectorTypeBreakdown - Vector types are broken down into some number of
1638/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1639/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1640/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1641///
1642/// This method returns the number of registers needed, and the VT for each
1643/// register. It also returns the VT and quantity of the intermediate values
1644/// before they are promoted/expanded.
1646 EVT VT, EVT &IntermediateVT,
1647 unsigned &NumIntermediates,
1648 MVT &RegisterVT) const {
1649 ElementCount EltCnt = VT.getVectorElementCount();
1650
1651 // If there is a wider vector type with the same element type as this one,
1652 // or a promoted vector type that has the same number of elements which
1653 // are wider, then we should convert to that legal vector type.
1654 // This handles things like <2 x float> -> <4 x float> and
1655 // <4 x i1> -> <4 x i32>.
1657 if (!EltCnt.isScalar() &&
1658 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1659 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1660 if (isTypeLegal(RegisterEVT)) {
1661 IntermediateVT = RegisterEVT;
1662 RegisterVT = RegisterEVT.getSimpleVT();
1663 NumIntermediates = 1;
1664 return 1;
1665 }
1666 }
1667
1668 // Figure out the right, legal destination reg to copy into.
1669 EVT EltTy = VT.getVectorElementType();
1670
1671 unsigned NumVectorRegs = 1;
1672
1673 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1674 // types like done elsewhere in SelectionDAG.
1675 if (EltCnt.isScalable()) {
1676 LegalizeKind LK;
1677 EVT PartVT = VT;
1678 do {
1679 // Iterate until we've found a legal (part) type to hold VT.
1680 LK = getTypeConversion(Context, PartVT);
1681 PartVT = LK.second;
1682 } while (LK.first != TypeLegal);
1683
1684 if (!PartVT.isVector()) {
1686 "Don't know how to legalize this scalable vector type");
1687 }
1688
1689 NumIntermediates =
1692 IntermediateVT = PartVT;
1693 RegisterVT = getRegisterType(Context, IntermediateVT);
1694 return NumIntermediates;
1695 }
1696
1697 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1698 // we could break down into LHS/RHS like LegalizeDAG does.
1699 if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1700 NumVectorRegs = EltCnt.getKnownMinValue();
1701 EltCnt = ElementCount::getFixed(1);
1702 }
1703
1704 // Divide the input until we get to a supported size. This will always
1705 // end with a scalar if the target doesn't support vectors.
1706 while (EltCnt.getKnownMinValue() > 1 &&
1707 !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1708 EltCnt = EltCnt.divideCoefficientBy(2);
1709 NumVectorRegs <<= 1;
1710 }
1711
1712 NumIntermediates = NumVectorRegs;
1713
1714 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1715 if (!isTypeLegal(NewVT))
1716 NewVT = EltTy;
1717 IntermediateVT = NewVT;
1718
1719 MVT DestVT = getRegisterType(Context, NewVT);
1720 RegisterVT = DestVT;
1721
1722 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1723 TypeSize NewVTSize = NewVT.getSizeInBits();
1724 // Convert sizes such as i33 to i64.
1725 if (!llvm::has_single_bit<uint32_t>(NewVTSize.getKnownMinValue()))
1726 NewVTSize = NewVTSize.coefficientNextPowerOf2();
1727 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1728 }
1729
1730 // Otherwise, promotion or legal types use the same number of registers as
1731 // the vector decimated to the appropriate level.
1732 return NumVectorRegs;
1733}
1734
1736 uint64_t NumCases,
1737 uint64_t Range,
1738 ProfileSummaryInfo *PSI,
1739 BlockFrequencyInfo *BFI) const {
1740 // FIXME: This function check the maximum table size and density, but the
1741 // minimum size is not checked. It would be nice if the minimum size is
1742 // also combined within this function. Currently, the minimum size check is
1743 // performed in findJumpTable() in SelectionDAGBuiler and
1744 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1745 const bool OptForSize =
1746 SI->getParent()->getParent()->hasOptSize() ||
1747 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1748 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1749 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1750
1751 // Check whether the number of cases is small enough and
1752 // the range is dense enough for a jump table.
1753 return (OptForSize || Range <= MaxJumpTableSize) &&
1754 (NumCases * 100 >= Range * MinDensity);
1755}
1756
1758 EVT ConditionVT) const {
1759 return getRegisterType(Context, ConditionVT);
1760}
1761
1762/// Get the EVTs and ArgFlags collections that represent the legalized return
1763/// type of the given function. This does not require a DAG or a return value,
1764/// and is suitable for use before any DAGs for the function are constructed.
1765/// TODO: Move this out of TargetLowering.cpp.
1767 AttributeList attr,
1769 const TargetLowering &TLI, const DataLayout &DL) {
1770 SmallVector<EVT, 4> ValueVTs;
1771 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1772 unsigned NumValues = ValueVTs.size();
1773 if (NumValues == 0) return;
1774
1775 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1776 EVT VT = ValueVTs[j];
1777 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1778
1779 if (attr.hasRetAttr(Attribute::SExt))
1780 ExtendKind = ISD::SIGN_EXTEND;
1781 else if (attr.hasRetAttr(Attribute::ZExt))
1782 ExtendKind = ISD::ZERO_EXTEND;
1783
1784 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1785 VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind);
1786
1787 unsigned NumParts =
1788 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1789 MVT PartVT =
1790 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1791
1792 // 'inreg' on function refers to return value
1794 if (attr.hasRetAttr(Attribute::InReg))
1795 Flags.setInReg();
1796
1797 // Propagate extension type if any
1798 if (attr.hasRetAttr(Attribute::SExt))
1799 Flags.setSExt();
1800 else if (attr.hasRetAttr(Attribute::ZExt))
1801 Flags.setZExt();
1802
1803 for (unsigned i = 0; i < NumParts; ++i)
1804 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1805 }
1806}
1807
1808/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1809/// function arguments in the caller parameter area. This is the actual
1810/// alignment, not its logarithm.
1812 const DataLayout &DL) const {
1813 return DL.getABITypeAlign(Ty).value();
1814}
1815
1817 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1818 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
1819 // Check if the specified alignment is sufficient based on the data layout.
1820 // TODO: While using the data layout works in practice, a better solution
1821 // would be to implement this check directly (make this a virtual function).
1822 // For example, the ABI alignment may change based on software platform while
1823 // this function should only be affected by hardware implementation.
1824 Type *Ty = VT.getTypeForEVT(Context);
1825 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1826 // Assume that an access that meets the ABI-specified alignment is fast.
1827 if (Fast != nullptr)
1828 *Fast = 1;
1829 return true;
1830 }
1831
1832 // This is a misaligned access.
1833 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1834}
1835
1837 LLVMContext &Context, const DataLayout &DL, EVT VT,
1838 const MachineMemOperand &MMO, unsigned *Fast) const {
1840 MMO.getAlign(), MMO.getFlags(), Fast);
1841}
1842
1844 const DataLayout &DL, EVT VT,
1845 unsigned AddrSpace, Align Alignment,
1847 unsigned *Fast) const {
1848 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1849 Flags, Fast);
1850}
1851
1853 const DataLayout &DL, EVT VT,
1854 const MachineMemOperand &MMO,
1855 unsigned *Fast) const {
1856 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1857 MMO.getFlags(), Fast);
1858}
1859
1861 const DataLayout &DL, LLT Ty,
1862 const MachineMemOperand &MMO,
1863 unsigned *Fast) const {
1865 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1866 MMO.getFlags(), Fast);
1867}
1868
1869//===----------------------------------------------------------------------===//
1870// TargetTransformInfo Helpers
1871//===----------------------------------------------------------------------===//
1872
1874 enum InstructionOpcodes {
1875#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1876#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1877#include "llvm/IR/Instruction.def"
1878 };
1879 switch (static_cast<InstructionOpcodes>(Opcode)) {
1880 case Ret: return 0;
1881 case Br: return 0;
1882 case Switch: return 0;
1883 case IndirectBr: return 0;
1884 case Invoke: return 0;
1885 case CallBr: return 0;
1886 case Resume: return 0;
1887 case Unreachable: return 0;
1888 case CleanupRet: return 0;
1889 case CatchRet: return 0;
1890 case CatchPad: return 0;
1891 case CatchSwitch: return 0;
1892 case CleanupPad: return 0;
1893 case FNeg: return ISD::FNEG;
1894 case Add: return ISD::ADD;
1895 case FAdd: return ISD::FADD;
1896 case Sub: return ISD::SUB;
1897 case FSub: return ISD::FSUB;
1898 case Mul: return ISD::MUL;
1899 case FMul: return ISD::FMUL;
1900 case UDiv: return ISD::UDIV;
1901 case SDiv: return ISD::SDIV;
1902 case FDiv: return ISD::FDIV;
1903 case URem: return ISD::UREM;
1904 case SRem: return ISD::SREM;
1905 case FRem: return ISD::FREM;
1906 case Shl: return ISD::SHL;
1907 case LShr: return ISD::SRL;
1908 case AShr: return ISD::SRA;
1909 case And: return ISD::AND;
1910 case Or: return ISD::OR;
1911 case Xor: return ISD::XOR;
1912 case Alloca: return 0;
1913 case Load: return ISD::LOAD;
1914 case Store: return ISD::STORE;
1915 case GetElementPtr: return 0;
1916 case Fence: return 0;
1917 case AtomicCmpXchg: return 0;
1918 case AtomicRMW: return 0;
1919 case Trunc: return ISD::TRUNCATE;
1920 case ZExt: return ISD::ZERO_EXTEND;
1921 case SExt: return ISD::SIGN_EXTEND;
1922 case FPToUI: return ISD::FP_TO_UINT;
1923 case FPToSI: return ISD::FP_TO_SINT;
1924 case UIToFP: return ISD::UINT_TO_FP;
1925 case SIToFP: return ISD::SINT_TO_FP;
1926 case FPTrunc: return ISD::FP_ROUND;
1927 case FPExt: return ISD::FP_EXTEND;
1928 case PtrToInt: return ISD::BITCAST;
1929 case IntToPtr: return ISD::BITCAST;
1930 case BitCast: return ISD::BITCAST;
1931 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1932 case ICmp: return ISD::SETCC;
1933 case FCmp: return ISD::SETCC;
1934 case PHI: return 0;
1935 case Call: return 0;
1936 case Select: return ISD::SELECT;
1937 case UserOp1: return 0;
1938 case UserOp2: return 0;
1939 case VAArg: return 0;
1940 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1941 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1942 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1943 case ExtractValue: return ISD::MERGE_VALUES;
1944 case InsertValue: return ISD::MERGE_VALUES;
1945 case LandingPad: return 0;
1946 case Freeze: return ISD::FREEZE;
1947 }
1948
1949 llvm_unreachable("Unknown instruction type encountered!");
1950}
1951
1952Value *
1954 bool UseTLS) const {
1955 // compiler-rt provides a variable with a magic name. Targets that do not
1956 // link with compiler-rt may also provide such a variable.
1957 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1958 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1959 auto UnsafeStackPtr =
1960 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1961
1962 Type *StackPtrTy = PointerType::getUnqual(M->getContext());
1963
1964 if (!UnsafeStackPtr) {
1965 auto TLSModel = UseTLS ?
1968 // The global variable is not defined yet, define it ourselves.
1969 // We use the initial-exec TLS model because we do not support the
1970 // variable living anywhere other than in the main executable.
1971 UnsafeStackPtr = new GlobalVariable(
1972 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1973 UnsafeStackPtrVar, nullptr, TLSModel);
1974 } else {
1975 // The variable exists, check its type and attributes.
1976 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1977 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1978 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1979 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1980 (UseTLS ? "" : "not ") + "be thread-local");
1981 }
1982 return UnsafeStackPtr;
1983}
1984
1985Value *
1987 if (!TM.getTargetTriple().isAndroid())
1988 return getDefaultSafeStackPointerLocation(IRB, true);
1989
1990 // Android provides a libc function to retrieve the address of the current
1991 // thread's unsafe stack pointer.
1992 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1993 auto *PtrTy = PointerType::getUnqual(M->getContext());
1994 FunctionCallee Fn =
1995 M->getOrInsertFunction("__safestack_pointer_address", PtrTy);
1996 return IRB.CreateCall(Fn);
1997}
1998
1999//===----------------------------------------------------------------------===//
2000// Loop Strength Reduction hooks
2001//===----------------------------------------------------------------------===//
2002
2003/// isLegalAddressingMode - Return true if the addressing mode represented
2004/// by AM is legal for this target, for a load/store of the specified type.
2006 const AddrMode &AM, Type *Ty,
2007 unsigned AS, Instruction *I) const {
2008 // The default implementation of this implements a conservative RISCy, r+r and
2009 // r+i addr mode.
2010
2011 // Allows a sign-extended 16-bit immediate field.
2012 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2013 return false;
2014
2015 // No global is ever allowed as a base.
2016 if (AM.BaseGV)
2017 return false;
2018
2019 // Only support r+r,
2020 switch (AM.Scale) {
2021 case 0: // "r+i" or just "i", depending on HasBaseReg.
2022 break;
2023 case 1:
2024 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2025 return false;
2026 // Otherwise we have r+r or r+i.
2027 break;
2028 case 2:
2029 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2030 return false;
2031 // Allow 2*r as r+r.
2032 break;
2033 default: // Don't allow n * r
2034 return false;
2035 }
2036
2037 return true;
2038}
2039
2040//===----------------------------------------------------------------------===//
2041// Stack Protector
2042//===----------------------------------------------------------------------===//
2043
2044// For OpenBSD return its special guard variable. Otherwise return nullptr,
2045// so that SelectionDAG handle SSP.
2047 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
2048 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
2049 PointerType *PtrTy = PointerType::getUnqual(M.getContext());
2050 Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
2051 if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
2052 G->setVisibility(GlobalValue::HiddenVisibility);
2053 return C;
2054 }
2055 return nullptr;
2056}
2057
2058// Currently only support "standard" __stack_chk_guard.
2059// TODO: add LOAD_STACK_GUARD support.
2061 if (!M.getNamedValue("__stack_chk_guard")) {
2062 auto *GV = new GlobalVariable(M, PointerType::getUnqual(M.getContext()),
2064 nullptr, "__stack_chk_guard");
2065
2066 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2067 if (M.getDirectAccessExternalData() &&
2069 !TM.getTargetTriple().isOSFreeBSD() &&
2070 (!TM.getTargetTriple().isOSDarwin() ||
2072 GV->setDSOLocal(true);
2073 }
2074}
2075
2076// Currently only support "standard" __stack_chk_guard.
2077// TODO: add LOAD_STACK_GUARD support.
2079 return M.getNamedValue("__stack_chk_guard");
2080}
2081
2083 return nullptr;
2084}
2085
2088}
2089
2092}
2093
2094unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2095 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2096}
2097
2099 return MaximumJumpTableSize;
2100}
2101
2104}
2105
2108}
2109
2111 if (TM.Options.LoopAlignment)
2112 return Align(TM.Options.LoopAlignment);
2113 return PrefLoopAlignment;
2114}
2115
2117 MachineBasicBlock *MBB) const {
2118 return MaxBytesForAlignment;
2119}
2120
2121//===----------------------------------------------------------------------===//
2122// Reciprocal Estimates
2123//===----------------------------------------------------------------------===//
2124
2125/// Get the reciprocal estimate attribute string for a function that will
2126/// override the target defaults.
2128 const Function &F = MF.getFunction();
2129 return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2130}
2131
2132/// Construct a string for the given reciprocal operation of the given type.
2133/// This string should match the corresponding option to the front-end's
2134/// "-mrecip" flag assuming those strings have been passed through in an
2135/// attribute string. For example, "vec-divf" for a division of a vXf32.
2136static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2137 std::string Name = VT.isVector() ? "vec-" : "";
2138
2139 Name += IsSqrt ? "sqrt" : "div";
2140
2141 // TODO: Handle other float types?
2142 if (VT.getScalarType() == MVT::f64) {
2143 Name += "d";
2144 } else if (VT.getScalarType() == MVT::f16) {
2145 Name += "h";
2146 } else {
2147 assert(VT.getScalarType() == MVT::f32 &&
2148 "Unexpected FP type for reciprocal estimate");
2149 Name += "f";
2150 }
2151
2152 return Name;
2153}
2154
2155/// Return the character position and value (a single numeric character) of a
2156/// customized refinement operation in the input string if it exists. Return
2157/// false if there is no customized refinement step count.
2158static bool parseRefinementStep(StringRef In, size_t &Position,
2159 uint8_t &Value) {
2160 const char RefStepToken = ':';
2161 Position = In.find(RefStepToken);
2162 if (Position == StringRef::npos)
2163 return false;
2164
2165 StringRef RefStepString = In.substr(Position + 1);
2166 // Allow exactly one numeric character for the additional refinement
2167 // step parameter.
2168 if (RefStepString.size() == 1) {
2169 char RefStepChar = RefStepString[0];
2170 if (isDigit(RefStepChar)) {
2171 Value = RefStepChar - '0';
2172 return true;
2173 }
2174 }
2175 report_fatal_error("Invalid refinement step for -recip.");
2176}
2177
2178/// For the input attribute string, return one of the ReciprocalEstimate enum
2179/// status values (enabled, disabled, or not specified) for this operation on
2180/// the specified data type.
2181static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2182 if (Override.empty())
2184
2185 SmallVector<StringRef, 4> OverrideVector;
2186 Override.split(OverrideVector, ',');
2187 unsigned NumArgs = OverrideVector.size();
2188
2189 // Check if "all", "none", or "default" was specified.
2190 if (NumArgs == 1) {
2191 // Look for an optional setting of the number of refinement steps needed
2192 // for this type of reciprocal operation.
2193 size_t RefPos;
2194 uint8_t RefSteps;
2195 if (parseRefinementStep(Override, RefPos, RefSteps)) {
2196 // Split the string for further processing.
2197 Override = Override.substr(0, RefPos);
2198 }
2199
2200 // All reciprocal types are enabled.
2201 if (Override == "all")
2203
2204 // All reciprocal types are disabled.
2205 if (Override == "none")
2207
2208 // Target defaults for enablement are used.
2209 if (Override == "default")
2211 }
2212
2213 // The attribute string may omit the size suffix ('f'/'d').
2214 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2215 std::string VTNameNoSize = VTName;
2216 VTNameNoSize.pop_back();
2217 static const char DisabledPrefix = '!';
2218
2219 for (StringRef RecipType : OverrideVector) {
2220 size_t RefPos;
2221 uint8_t RefSteps;
2222 if (parseRefinementStep(RecipType, RefPos, RefSteps))
2223 RecipType = RecipType.substr(0, RefPos);
2224
2225 // Ignore the disablement token for string matching.
2226 bool IsDisabled = RecipType[0] == DisabledPrefix;
2227 if (IsDisabled)
2228 RecipType = RecipType.substr(1);
2229
2230 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2233 }
2234
2236}
2237
2238/// For the input attribute string, return the customized refinement step count
2239/// for this operation on the specified data type. If the step count does not
2240/// exist, return the ReciprocalEstimate enum value for unspecified.
2241static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2242 if (Override.empty())
2244
2245 SmallVector<StringRef, 4> OverrideVector;
2246 Override.split(OverrideVector, ',');
2247 unsigned NumArgs = OverrideVector.size();
2248
2249 // Check if "all", "default", or "none" was specified.
2250 if (NumArgs == 1) {
2251 // Look for an optional setting of the number of refinement steps needed
2252 // for this type of reciprocal operation.
2253 size_t RefPos;
2254 uint8_t RefSteps;
2255 if (!parseRefinementStep(Override, RefPos, RefSteps))
2257
2258 // Split the string for further processing.
2259 Override = Override.substr(0, RefPos);
2260 assert(Override != "none" &&
2261 "Disabled reciprocals, but specifed refinement steps?");
2262
2263 // If this is a general override, return the specified number of steps.
2264 if (Override == "all" || Override == "default")
2265 return RefSteps;
2266 }
2267
2268 // The attribute string may omit the size suffix ('f'/'d').
2269 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2270 std::string VTNameNoSize = VTName;
2271 VTNameNoSize.pop_back();
2272
2273 for (StringRef RecipType : OverrideVector) {
2274 size_t RefPos;
2275 uint8_t RefSteps;
2276 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2277 continue;
2278
2279 RecipType = RecipType.substr(0, RefPos);
2280 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2281 return RefSteps;
2282 }
2283
2285}
2286
2288 MachineFunction &MF) const {
2289 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2290}
2291
2293 MachineFunction &MF) const {
2294 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2295}
2296
2298 MachineFunction &MF) const {
2299 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2300}
2301
2303 MachineFunction &MF) const {
2304 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2305}
2306
2308 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2309 const MachineMemOperand &MMO) const {
2310 // Single-element vectors are scalarized, so we should generally avoid having
2311 // any memory operations on such types, as they would get scalarized too.
2312 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2313 BitcastVT.getVectorNumElements() == 1)
2314 return false;
2315
2316 // Don't do if we could do an indexed load on the original type, but not on
2317 // the new one.
2318 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2319 return true;
2320
2321 MVT LoadMVT = LoadVT.getSimpleVT();
2322
2323 // Don't bother doing this if it's just going to be promoted again later, as
2324 // doing so might interfere with other combines.
2325 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
2326 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
2327 return false;
2328
2329 unsigned Fast = 0;
2330 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
2331 MMO, &Fast) &&
2332 Fast;
2333}
2334
2337}
2338
2340 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2341 const TargetLibraryInfo *LibInfo) const {
2343 if (LI.isVolatile())
2345
2346 if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2348
2349 if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2351
2353 LI.getAlign(), DL, &LI, AC,
2354 /*DT=*/nullptr, LibInfo))
2356
2357 Flags |= getTargetMMOFlags(LI);
2358 return Flags;
2359}
2360
2363 const DataLayout &DL) const {
2365
2366 if (SI.isVolatile())
2368
2369 if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2371
2372 // FIXME: Not preserving dereferenceable
2373 Flags |= getTargetMMOFlags(SI);
2374 return Flags;
2375}
2376
2379 const DataLayout &DL) const {
2381
2382 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2383 if (RMW->isVolatile())
2385 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2386 if (CmpX->isVolatile())
2388 } else
2389 llvm_unreachable("not an atomic instruction");
2390
2391 // FIXME: Not preserving dereferenceable
2392 Flags |= getTargetMMOFlags(AI);
2393 return Flags;
2394}
2395
2397 Instruction *Inst,
2398 AtomicOrdering Ord) const {
2399 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2400 return Builder.CreateFence(Ord);
2401 else
2402 return nullptr;
2403}
2404
2406 Instruction *Inst,
2407 AtomicOrdering Ord) const {
2408 if (isAcquireOrStronger(Ord))
2409 return Builder.CreateFence(Ord);
2410 else
2411 return nullptr;
2412}
2413
2414//===----------------------------------------------------------------------===//
2415// GlobalISel Hooks
2416//===----------------------------------------------------------------------===//
2417
2419 const TargetTransformInfo *TTI) const {
2420 auto &MF = *MI.getMF();
2421 auto &MRI = MF.getRegInfo();
2422 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2423 // this helper function computes the maximum number of uses we should consider
2424 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2425 // break even in terms of code size when the original MI has 2 users vs
2426 // choosing to potentially spill. Any more than 2 users we we have a net code
2427 // size increase. This doesn't take into account register pressure though.
2428 auto maxUses = [](unsigned RematCost) {
2429 // A cost of 1 means remats are basically free.
2430 if (RematCost == 1)
2431 return std::numeric_limits<unsigned>::max();
2432 if (RematCost == 2)
2433 return 2U;
2434
2435 // Remat is too expensive, only sink if there's one user.
2436 if (RematCost > 2)
2437 return 1U;
2438 llvm_unreachable("Unexpected remat cost");
2439 };
2440
2441 switch (MI.getOpcode()) {
2442 default:
2443 return false;
2444 // Constants-like instructions should be close to their users.
2445 // We don't want long live-ranges for them.
2446 case TargetOpcode::G_CONSTANT:
2447 case TargetOpcode::G_FCONSTANT:
2448 case TargetOpcode::G_FRAME_INDEX:
2449 case TargetOpcode::G_INTTOPTR:
2450 return true;
2451 case TargetOpcode::G_GLOBAL_VALUE: {
2452 unsigned RematCost = TTI->getGISelRematGlobalCost();
2453 Register Reg = MI.getOperand(0).getReg();
2454 unsigned MaxUses = maxUses(RematCost);
2455 if (MaxUses == UINT_MAX)
2456 return true; // Remats are "free" so always localize.
2457 return MRI.hasAtMostUserInstrs(Reg, MaxUses);
2458 }
2459 }
2460}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
Rewrite undef for PHI
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
std::string Name
IRTranslator LLVM IR MI
#define LCALL5(A)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
const char LLVMTargetMachineRef TM
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallVector class.
This file contains some functions that are useful when dealing with strings.
static bool darwinHasSinCos(const Triple &TT)
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
#define OP_TO_LIBCALL(Name, Enum)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
This file describes how to lower LLVM code to machine code.
This pass exposes codegen information to IR-level passes.
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:522
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:727
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
Definition: Attributes.h:782
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:214
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:707
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:140
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
Definition: DataLayout.cpp:750
static constexpr ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:299
static constexpr ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:296
constexpr bool isScalar() const
Exactly one element.
Definition: TypeSize.h:307
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:168
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:68
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:52
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1833
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:174
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=std::nullopt, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2395
bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:339
@ MAX_INT_BITS
Maximum number of bits that can be specified.
Definition: DerivedTypes.h:52
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:178
Value * getPointerOperand()
Definition: Instructions.h:265
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:215
Align getAlign() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:221
Machine Value Type.
SimpleValueType SimpleTy
uint64_t getScalarSizeInBits() const
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static auto all_valuetypes()
SimpleValueType Iteration.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
ElementCount getVectorElementCount() const
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
Definition: MachineInstr.h:68
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:546
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
A description of a memory reference used in the backend.
unsigned getAddrSpace() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Class to represent pointers.
Definition: DerivedTypes.h:646
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Definition: DerivedTypes.h:662
Analysis providing profile information.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:472
LLVMContext * getContext() const
Definition: SelectionDAG.h:485
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:302
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:567
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
static constexpr size_t npos
Definition: StringRef.h:52
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Multiway switch.
Provides information about what library functions are available for the current target.
LegalizeTypeAction getTypeAction(MVT VT) const
void setTypeAction(MVT VT, LegalizeTypeAction Action)
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
void initActions()
Initialize all of the actions to default values.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
const TargetMachine & getTargetMachine() const
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual bool useFPRegsForHalfType() const
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
virtual bool softPromoteHalfType() const
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual bool isJumpTableRelative() const
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to.
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
bool isPositionIndependent() const
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
TargetOptions Options
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
unsigned getGISelRematGlobalCost() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isWindowsGNUEnvironment() const
Definition: Triple.h:641
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:753
@ aarch64_32
Definition: Triple.h:53
bool isOSFreeBSD() const
Definition: Triple.h:568
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:542
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
constexpr LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:247
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:239
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ ARM_AAPCS_VFP
Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:114
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:750
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:723
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
@ SET_FPENV
Sets the current floating-point environment.
Definition: ISDOpcodes.h:996
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1337
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1368
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:497
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1267
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:367
@ ConstantFP
Definition: ISDOpcodes.h:77
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1269
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1270
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
@ RESET_FPENV
Set floating-point environment to default state.
Definition: ISDOpcodes.h:1000
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:487
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:977
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:1029
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:373
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1019
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:783
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1252
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:790
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:543
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1353
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
Definition: ISDOpcodes.h:1357
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:688
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
Definition: ISDOpcodes.h:1023
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:820
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1367
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1265
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:903
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1266
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
Definition: ISDOpcodes.h:937
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:380
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1389
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:662
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
Definition: ISDOpcodes.h:1186
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1350
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:722
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1219
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1354
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:758
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:928
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1268
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:507
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:349
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:727
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1369
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:627
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1362
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1014
@ GET_FPENV
Gets the current floating-point environment.
Definition: ISDOpcodes.h:991
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:705
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1264
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:600
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1263
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:976
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:535
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:780
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1209
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:856
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1246
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1271
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:969
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1213
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:359
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:809
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:798
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:674
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:386
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:888
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1370
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1261
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:982
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1262
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:836
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1180
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:680
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1206
@ GET_FPENV_MEM
Gets the current floating-point environment.
Definition: ISDOpcodes.h:1005
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:657
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1351
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:524
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:612
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1260
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
Definition: ISDOpcodes.h:942
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:869
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:831
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:907
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:855
@ VECREDUCE_FMINIMUM
Definition: ISDOpcodes.h:1358
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:786
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1338
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:493
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:340
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1318
@ SET_FPENV_MEM
Sets the current floating point environment.
Definition: ISDOpcodes.h:1010
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:313
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1512
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1463
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Libcall getLDEXP(EVT RetVT)
getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFREXP(EVT RetVT)
getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)
Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< TypeSize > *Offsets, TypeSize StartingOffset)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:122
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:326
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:417
auto enum_seq(EnumT Begin, EnumT End)
Iterate over an enum type from Begin up to - but not including - End.
Definition: Sequence.h:337
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:199
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum
Definition: Sequence.h:108
T bit_ceil(T Value)
Returns the smallest integral power of two no smaller than Value if Value is nonzero.
Definition: bit.h:342
bool isReleaseOrStronger(AtomicOrdering AO)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1745
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
@ Xor
Bitwise or logical XOR of integers.
@ FMul
Product of floats.
@ And
Bitwise or logical AND of integers.
@ Add
Sum of integers.
@ FAdd
Sum of floats.
bool isAcquireOrStronger(AtomicOrdering AO)
InstructionCost Cost
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:455
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:129
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:333
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:351
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:448
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:299
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
bool isFixedLengthVector() const
Definition: ValueTypes.h:170
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:397
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:160
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:306
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:311
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:319
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
Definition: ValueTypes.h:124
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:431
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:144
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...