LLVM 19.0.0git
TargetLoweringBase.cpp
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1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Twine.h"
19#include "llvm/Analysis/Loads.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/CallingConv.h"
40#include "llvm/IR/DataLayout.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/GlobalValue.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/Type.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <iterator>
62#include <string>
63#include <tuple>
64#include <utility>
65
66using namespace llvm;
67
69 "jump-is-expensive", cl::init(false),
70 cl::desc("Do not create extra branches to split comparison logic."),
72
74 ("min-jump-table-entries", cl::init(4), cl::Hidden,
75 cl::desc("Set minimum number of entries to use a jump table."));
76
78 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79 cl::desc("Set maximum size of jump tables."));
80
81/// Minimum jump table density for normal functions.
83 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
84 cl::desc("Minimum density for building a jump table in "
85 "a normal function"));
86
87/// Minimum jump table density for -Os or -Oz functions.
89 "optsize-jump-table-density", cl::init(40), cl::Hidden,
90 cl::desc("Minimum density for building a jump table in "
91 "an optsize function"));
92
93// FIXME: This option is only to test if the strict fp operation processed
94// correctly by preventing mutating strict fp operation to normal fp operation
95// during development. When the backend supports strict float operation, this
96// option will be meaningless.
97static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98 cl::desc("Don't mutate strict-float node to a legalize node"),
99 cl::init(false), cl::Hidden);
100
101static bool darwinHasSinCos(const Triple &TT) {
102 assert(TT.isOSDarwin() && "should be called with darwin triple");
103 // Don't bother with 32 bit x86.
104 if (TT.getArch() == Triple::x86)
105 return false;
106 // Macos < 10.9 has no sincos_stret.
107 if (TT.isMacOSX())
108 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
109 // iOS < 7.0 has no sincos_stret.
110 if (TT.isiOS())
111 return !TT.isOSVersionLT(7, 0);
112 // Any other darwin such as WatchOS/TvOS is new enough.
113 return true;
114}
115
116void TargetLoweringBase::InitLibcalls(const Triple &TT) {
117#define HANDLE_LIBCALL(code, name) \
118 setLibcallName(RTLIB::code, name);
119#include "llvm/IR/RuntimeLibcalls.def"
120#undef HANDLE_LIBCALL
121 // Initialize calling conventions to their default.
122 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124
125 // Use the f128 variants of math functions on x86_64
126 if (TT.getArch() == Triple::ArchType::x86_64 && TT.isGNUEnvironment()) {
127 setLibcallName(RTLIB::REM_F128, "fmodf128");
128 setLibcallName(RTLIB::FMA_F128, "fmaf128");
129 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
130 setLibcallName(RTLIB::CBRT_F128, "cbrtf128");
131 setLibcallName(RTLIB::LOG_F128, "logf128");
132 setLibcallName(RTLIB::LOG_FINITE_F128, "__logf128_finite");
133 setLibcallName(RTLIB::LOG2_F128, "log2f128");
134 setLibcallName(RTLIB::LOG2_FINITE_F128, "__log2f128_finite");
135 setLibcallName(RTLIB::LOG10_F128, "log10f128");
136 setLibcallName(RTLIB::LOG10_FINITE_F128, "__log10f128_finite");
137 setLibcallName(RTLIB::EXP_F128, "expf128");
138 setLibcallName(RTLIB::EXP_FINITE_F128, "__expf128_finite");
139 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
140 setLibcallName(RTLIB::EXP2_FINITE_F128, "__exp2f128_finite");
141 setLibcallName(RTLIB::EXP10_F128, "exp10f128");
142 setLibcallName(RTLIB::SIN_F128, "sinf128");
143 setLibcallName(RTLIB::COS_F128, "cosf128");
144 setLibcallName(RTLIB::SINCOS_F128, "sincosf128");
145 setLibcallName(RTLIB::POW_F128, "powf128");
146 setLibcallName(RTLIB::POW_FINITE_F128, "__powf128_finite");
147 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
148 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
149 setLibcallName(RTLIB::RINT_F128, "rintf128");
150 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
151 setLibcallName(RTLIB::ROUND_F128, "roundf128");
152 setLibcallName(RTLIB::ROUNDEVEN_F128, "roundevenf128");
153 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
154 setLibcallName(RTLIB::COPYSIGN_F128, "copysignf128");
155 setLibcallName(RTLIB::FMIN_F128, "fminf128");
156 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
157 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
158 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
159 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
160 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
161 setLibcallName(RTLIB::LDEXP_F128, "ldexpf128");
162 setLibcallName(RTLIB::FREXP_F128, "frexpf128");
163 }
164
165 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
166 if (TT.isPPC()) {
167 setLibcallName(RTLIB::ADD_F128, "__addkf3");
168 setLibcallName(RTLIB::SUB_F128, "__subkf3");
169 setLibcallName(RTLIB::MUL_F128, "__mulkf3");
170 setLibcallName(RTLIB::DIV_F128, "__divkf3");
171 setLibcallName(RTLIB::POWI_F128, "__powikf2");
172 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
173 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
174 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
175 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
176 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
177 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
178 setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
179 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
180 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
181 setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
182 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
183 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
184 setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
185 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
186 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
187 setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
188 setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
189 setLibcallName(RTLIB::UNE_F128, "__nekf2");
190 setLibcallName(RTLIB::OGE_F128, "__gekf2");
191 setLibcallName(RTLIB::OLT_F128, "__ltkf2");
192 setLibcallName(RTLIB::OLE_F128, "__lekf2");
193 setLibcallName(RTLIB::OGT_F128, "__gtkf2");
194 setLibcallName(RTLIB::UO_F128, "__unordkf2");
195 }
196
197 // A few names are different on particular architectures or environments.
198 if (TT.isOSDarwin()) {
199 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
200 // of the gnueabi-style __gnu_*_ieee.
201 // FIXME: What about other targets?
202 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
203 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
204
205 // Some darwins have an optimized __bzero/bzero function.
206 switch (TT.getArch()) {
207 case Triple::x86:
208 case Triple::x86_64:
209 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
210 setLibcallName(RTLIB::BZERO, "__bzero");
211 break;
212 case Triple::aarch64:
214 setLibcallName(RTLIB::BZERO, "bzero");
215 break;
216 default:
217 break;
218 }
219
220 if (darwinHasSinCos(TT)) {
221 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
222 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
223 if (TT.isWatchABI()) {
224 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
226 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
228 }
229 }
230 } else {
231 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
232 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
233 }
234
235 if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
236 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
237 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
238 setLibcallName(RTLIB::SINCOS_F64, "sincos");
239 setLibcallName(RTLIB::SINCOS_F80, "sincosl");
240 setLibcallName(RTLIB::SINCOS_F128, "sincosl");
241 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
242 }
243
244 if (TT.isPS()) {
245 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
246 setLibcallName(RTLIB::SINCOS_F64, "sincos");
247 }
248
249 if (TT.isOSOpenBSD()) {
250 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
251 }
252
253 if (TT.isOSWindows() && !TT.isOSCygMing()) {
254 setLibcallName(RTLIB::LDEXP_F32, nullptr);
255 setLibcallName(RTLIB::LDEXP_F80, nullptr);
256 setLibcallName(RTLIB::LDEXP_F128, nullptr);
257 setLibcallName(RTLIB::LDEXP_PPCF128, nullptr);
258
259 setLibcallName(RTLIB::FREXP_F32, nullptr);
260 setLibcallName(RTLIB::FREXP_F80, nullptr);
261 setLibcallName(RTLIB::FREXP_F128, nullptr);
262 setLibcallName(RTLIB::FREXP_PPCF128, nullptr);
263 }
264}
265
266/// GetFPLibCall - Helper to return the right libcall for the given floating
267/// point type, or UNKNOWN_LIBCALL if there is none.
269 RTLIB::Libcall Call_F32,
270 RTLIB::Libcall Call_F64,
271 RTLIB::Libcall Call_F80,
272 RTLIB::Libcall Call_F128,
273 RTLIB::Libcall Call_PPCF128) {
274 return
275 VT == MVT::f32 ? Call_F32 :
276 VT == MVT::f64 ? Call_F64 :
277 VT == MVT::f80 ? Call_F80 :
278 VT == MVT::f128 ? Call_F128 :
279 VT == MVT::ppcf128 ? Call_PPCF128 :
280 RTLIB::UNKNOWN_LIBCALL;
281}
282
283/// getFPEXT - Return the FPEXT_*_* value for the given types, or
284/// UNKNOWN_LIBCALL if there is none.
286 if (OpVT == MVT::f16) {
287 if (RetVT == MVT::f32)
288 return FPEXT_F16_F32;
289 if (RetVT == MVT::f64)
290 return FPEXT_F16_F64;
291 if (RetVT == MVT::f80)
292 return FPEXT_F16_F80;
293 if (RetVT == MVT::f128)
294 return FPEXT_F16_F128;
295 } else if (OpVT == MVT::f32) {
296 if (RetVT == MVT::f64)
297 return FPEXT_F32_F64;
298 if (RetVT == MVT::f128)
299 return FPEXT_F32_F128;
300 if (RetVT == MVT::ppcf128)
301 return FPEXT_F32_PPCF128;
302 } else if (OpVT == MVT::f64) {
303 if (RetVT == MVT::f128)
304 return FPEXT_F64_F128;
305 else if (RetVT == MVT::ppcf128)
306 return FPEXT_F64_PPCF128;
307 } else if (OpVT == MVT::f80) {
308 if (RetVT == MVT::f128)
309 return FPEXT_F80_F128;
310 } else if (OpVT == MVT::bf16) {
311 if (RetVT == MVT::f32)
312 return FPEXT_BF16_F32;
313 }
314
315 return UNKNOWN_LIBCALL;
316}
317
318/// getFPROUND - Return the FPROUND_*_* value for the given types, or
319/// UNKNOWN_LIBCALL if there is none.
321 if (RetVT == MVT::f16) {
322 if (OpVT == MVT::f32)
323 return FPROUND_F32_F16;
324 if (OpVT == MVT::f64)
325 return FPROUND_F64_F16;
326 if (OpVT == MVT::f80)
327 return FPROUND_F80_F16;
328 if (OpVT == MVT::f128)
329 return FPROUND_F128_F16;
330 if (OpVT == MVT::ppcf128)
331 return FPROUND_PPCF128_F16;
332 } else if (RetVT == MVT::bf16) {
333 if (OpVT == MVT::f32)
334 return FPROUND_F32_BF16;
335 if (OpVT == MVT::f64)
336 return FPROUND_F64_BF16;
337 } else if (RetVT == MVT::f32) {
338 if (OpVT == MVT::f64)
339 return FPROUND_F64_F32;
340 if (OpVT == MVT::f80)
341 return FPROUND_F80_F32;
342 if (OpVT == MVT::f128)
343 return FPROUND_F128_F32;
344 if (OpVT == MVT::ppcf128)
345 return FPROUND_PPCF128_F32;
346 } else if (RetVT == MVT::f64) {
347 if (OpVT == MVT::f80)
348 return FPROUND_F80_F64;
349 if (OpVT == MVT::f128)
350 return FPROUND_F128_F64;
351 if (OpVT == MVT::ppcf128)
352 return FPROUND_PPCF128_F64;
353 } else if (RetVT == MVT::f80) {
354 if (OpVT == MVT::f128)
355 return FPROUND_F128_F80;
356 }
357
358 return UNKNOWN_LIBCALL;
359}
360
361/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
362/// UNKNOWN_LIBCALL if there is none.
364 if (OpVT == MVT::f16) {
365 if (RetVT == MVT::i32)
366 return FPTOSINT_F16_I32;
367 if (RetVT == MVT::i64)
368 return FPTOSINT_F16_I64;
369 if (RetVT == MVT::i128)
370 return FPTOSINT_F16_I128;
371 } else if (OpVT == MVT::f32) {
372 if (RetVT == MVT::i32)
373 return FPTOSINT_F32_I32;
374 if (RetVT == MVT::i64)
375 return FPTOSINT_F32_I64;
376 if (RetVT == MVT::i128)
377 return FPTOSINT_F32_I128;
378 } else if (OpVT == MVT::f64) {
379 if (RetVT == MVT::i32)
380 return FPTOSINT_F64_I32;
381 if (RetVT == MVT::i64)
382 return FPTOSINT_F64_I64;
383 if (RetVT == MVT::i128)
384 return FPTOSINT_F64_I128;
385 } else if (OpVT == MVT::f80) {
386 if (RetVT == MVT::i32)
387 return FPTOSINT_F80_I32;
388 if (RetVT == MVT::i64)
389 return FPTOSINT_F80_I64;
390 if (RetVT == MVT::i128)
391 return FPTOSINT_F80_I128;
392 } else if (OpVT == MVT::f128) {
393 if (RetVT == MVT::i32)
394 return FPTOSINT_F128_I32;
395 if (RetVT == MVT::i64)
396 return FPTOSINT_F128_I64;
397 if (RetVT == MVT::i128)
398 return FPTOSINT_F128_I128;
399 } else if (OpVT == MVT::ppcf128) {
400 if (RetVT == MVT::i32)
401 return FPTOSINT_PPCF128_I32;
402 if (RetVT == MVT::i64)
403 return FPTOSINT_PPCF128_I64;
404 if (RetVT == MVT::i128)
405 return FPTOSINT_PPCF128_I128;
406 }
407 return UNKNOWN_LIBCALL;
408}
409
410/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
411/// UNKNOWN_LIBCALL if there is none.
413 if (OpVT == MVT::f16) {
414 if (RetVT == MVT::i32)
415 return FPTOUINT_F16_I32;
416 if (RetVT == MVT::i64)
417 return FPTOUINT_F16_I64;
418 if (RetVT == MVT::i128)
419 return FPTOUINT_F16_I128;
420 } else if (OpVT == MVT::f32) {
421 if (RetVT == MVT::i32)
422 return FPTOUINT_F32_I32;
423 if (RetVT == MVT::i64)
424 return FPTOUINT_F32_I64;
425 if (RetVT == MVT::i128)
426 return FPTOUINT_F32_I128;
427 } else if (OpVT == MVT::f64) {
428 if (RetVT == MVT::i32)
429 return FPTOUINT_F64_I32;
430 if (RetVT == MVT::i64)
431 return FPTOUINT_F64_I64;
432 if (RetVT == MVT::i128)
433 return FPTOUINT_F64_I128;
434 } else if (OpVT == MVT::f80) {
435 if (RetVT == MVT::i32)
436 return FPTOUINT_F80_I32;
437 if (RetVT == MVT::i64)
438 return FPTOUINT_F80_I64;
439 if (RetVT == MVT::i128)
440 return FPTOUINT_F80_I128;
441 } else if (OpVT == MVT::f128) {
442 if (RetVT == MVT::i32)
443 return FPTOUINT_F128_I32;
444 if (RetVT == MVT::i64)
445 return FPTOUINT_F128_I64;
446 if (RetVT == MVT::i128)
447 return FPTOUINT_F128_I128;
448 } else if (OpVT == MVT::ppcf128) {
449 if (RetVT == MVT::i32)
450 return FPTOUINT_PPCF128_I32;
451 if (RetVT == MVT::i64)
452 return FPTOUINT_PPCF128_I64;
453 if (RetVT == MVT::i128)
454 return FPTOUINT_PPCF128_I128;
455 }
456 return UNKNOWN_LIBCALL;
457}
458
459/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
460/// UNKNOWN_LIBCALL if there is none.
462 if (OpVT == MVT::i32) {
463 if (RetVT == MVT::f16)
464 return SINTTOFP_I32_F16;
465 if (RetVT == MVT::f32)
466 return SINTTOFP_I32_F32;
467 if (RetVT == MVT::f64)
468 return SINTTOFP_I32_F64;
469 if (RetVT == MVT::f80)
470 return SINTTOFP_I32_F80;
471 if (RetVT == MVT::f128)
472 return SINTTOFP_I32_F128;
473 if (RetVT == MVT::ppcf128)
474 return SINTTOFP_I32_PPCF128;
475 } else if (OpVT == MVT::i64) {
476 if (RetVT == MVT::f16)
477 return SINTTOFP_I64_F16;
478 if (RetVT == MVT::f32)
479 return SINTTOFP_I64_F32;
480 if (RetVT == MVT::f64)
481 return SINTTOFP_I64_F64;
482 if (RetVT == MVT::f80)
483 return SINTTOFP_I64_F80;
484 if (RetVT == MVT::f128)
485 return SINTTOFP_I64_F128;
486 if (RetVT == MVT::ppcf128)
487 return SINTTOFP_I64_PPCF128;
488 } else if (OpVT == MVT::i128) {
489 if (RetVT == MVT::f16)
490 return SINTTOFP_I128_F16;
491 if (RetVT == MVT::f32)
492 return SINTTOFP_I128_F32;
493 if (RetVT == MVT::f64)
494 return SINTTOFP_I128_F64;
495 if (RetVT == MVT::f80)
496 return SINTTOFP_I128_F80;
497 if (RetVT == MVT::f128)
498 return SINTTOFP_I128_F128;
499 if (RetVT == MVT::ppcf128)
500 return SINTTOFP_I128_PPCF128;
501 }
502 return UNKNOWN_LIBCALL;
503}
504
505/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
506/// UNKNOWN_LIBCALL if there is none.
508 if (OpVT == MVT::i32) {
509 if (RetVT == MVT::f16)
510 return UINTTOFP_I32_F16;
511 if (RetVT == MVT::f32)
512 return UINTTOFP_I32_F32;
513 if (RetVT == MVT::f64)
514 return UINTTOFP_I32_F64;
515 if (RetVT == MVT::f80)
516 return UINTTOFP_I32_F80;
517 if (RetVT == MVT::f128)
518 return UINTTOFP_I32_F128;
519 if (RetVT == MVT::ppcf128)
520 return UINTTOFP_I32_PPCF128;
521 } else if (OpVT == MVT::i64) {
522 if (RetVT == MVT::f16)
523 return UINTTOFP_I64_F16;
524 if (RetVT == MVT::f32)
525 return UINTTOFP_I64_F32;
526 if (RetVT == MVT::f64)
527 return UINTTOFP_I64_F64;
528 if (RetVT == MVT::f80)
529 return UINTTOFP_I64_F80;
530 if (RetVT == MVT::f128)
531 return UINTTOFP_I64_F128;
532 if (RetVT == MVT::ppcf128)
533 return UINTTOFP_I64_PPCF128;
534 } else if (OpVT == MVT::i128) {
535 if (RetVT == MVT::f16)
536 return UINTTOFP_I128_F16;
537 if (RetVT == MVT::f32)
538 return UINTTOFP_I128_F32;
539 if (RetVT == MVT::f64)
540 return UINTTOFP_I128_F64;
541 if (RetVT == MVT::f80)
542 return UINTTOFP_I128_F80;
543 if (RetVT == MVT::f128)
544 return UINTTOFP_I128_F128;
545 if (RetVT == MVT::ppcf128)
546 return UINTTOFP_I128_PPCF128;
547 }
548 return UNKNOWN_LIBCALL;
549}
550
552 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
553 POWI_PPCF128);
554}
555
557 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,
558 LDEXP_PPCF128);
559}
560
562 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,
563 FREXP_PPCF128);
564}
565
567 AtomicOrdering Order,
568 uint64_t MemSize) {
569 unsigned ModeN, ModelN;
570 switch (MemSize) {
571 case 1:
572 ModeN = 0;
573 break;
574 case 2:
575 ModeN = 1;
576 break;
577 case 4:
578 ModeN = 2;
579 break;
580 case 8:
581 ModeN = 3;
582 break;
583 case 16:
584 ModeN = 4;
585 break;
586 default:
587 return RTLIB::UNKNOWN_LIBCALL;
588 }
589
590 switch (Order) {
592 ModelN = 0;
593 break;
595 ModelN = 1;
596 break;
598 ModelN = 2;
599 break;
602 ModelN = 3;
603 break;
604 default:
605 return UNKNOWN_LIBCALL;
606 }
607
608 return LC[ModeN][ModelN];
609}
610
612 MVT VT) {
613 if (!VT.isScalarInteger())
614 return UNKNOWN_LIBCALL;
615 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
616
617#define LCALLS(A, B) \
618 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
619#define LCALL5(A) \
620 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
621 switch (Opc) {
623 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
624 return getOutlineAtomicHelper(LC, Order, MemSize);
625 }
626 case ISD::ATOMIC_SWAP: {
627 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
628 return getOutlineAtomicHelper(LC, Order, MemSize);
629 }
631 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
632 return getOutlineAtomicHelper(LC, Order, MemSize);
633 }
634 case ISD::ATOMIC_LOAD_OR: {
635 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
636 return getOutlineAtomicHelper(LC, Order, MemSize);
637 }
639 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
640 return getOutlineAtomicHelper(LC, Order, MemSize);
641 }
643 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
644 return getOutlineAtomicHelper(LC, Order, MemSize);
645 }
646 default:
647 return UNKNOWN_LIBCALL;
648 }
649#undef LCALLS
650#undef LCALL5
651}
652
654#define OP_TO_LIBCALL(Name, Enum) \
655 case Name: \
656 switch (VT.SimpleTy) { \
657 default: \
658 return UNKNOWN_LIBCALL; \
659 case MVT::i8: \
660 return Enum##_1; \
661 case MVT::i16: \
662 return Enum##_2; \
663 case MVT::i32: \
664 return Enum##_4; \
665 case MVT::i64: \
666 return Enum##_8; \
667 case MVT::i128: \
668 return Enum##_16; \
669 }
670
671 switch (Opc) {
672 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
673 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
674 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
675 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
676 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
677 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
678 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
679 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
680 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
681 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
682 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
683 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
684 }
685
686#undef OP_TO_LIBCALL
687
688 return UNKNOWN_LIBCALL;
689}
690
692 switch (ElementSize) {
693 case 1:
694 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
695 case 2:
696 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
697 case 4:
698 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
699 case 8:
700 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
701 case 16:
702 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
703 default:
704 return UNKNOWN_LIBCALL;
705 }
706}
707
709 switch (ElementSize) {
710 case 1:
711 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
712 case 2:
713 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
714 case 4:
715 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
716 case 8:
717 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
718 case 16:
719 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
720 default:
721 return UNKNOWN_LIBCALL;
722 }
723}
724
726 switch (ElementSize) {
727 case 1:
728 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
729 case 2:
730 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
731 case 4:
732 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
733 case 8:
734 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
735 case 16:
736 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
737 default:
738 return UNKNOWN_LIBCALL;
739 }
740}
741
742/// InitCmpLibcallCCs - Set default comparison libcall CC.
744 std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID);
745 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
746 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
747 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
748 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
749 CCs[RTLIB::UNE_F32] = ISD::SETNE;
750 CCs[RTLIB::UNE_F64] = ISD::SETNE;
751 CCs[RTLIB::UNE_F128] = ISD::SETNE;
752 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
753 CCs[RTLIB::OGE_F32] = ISD::SETGE;
754 CCs[RTLIB::OGE_F64] = ISD::SETGE;
755 CCs[RTLIB::OGE_F128] = ISD::SETGE;
756 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
757 CCs[RTLIB::OLT_F32] = ISD::SETLT;
758 CCs[RTLIB::OLT_F64] = ISD::SETLT;
759 CCs[RTLIB::OLT_F128] = ISD::SETLT;
760 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
761 CCs[RTLIB::OLE_F32] = ISD::SETLE;
762 CCs[RTLIB::OLE_F64] = ISD::SETLE;
763 CCs[RTLIB::OLE_F128] = ISD::SETLE;
764 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
765 CCs[RTLIB::OGT_F32] = ISD::SETGT;
766 CCs[RTLIB::OGT_F64] = ISD::SETGT;
767 CCs[RTLIB::OGT_F128] = ISD::SETGT;
768 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
769 CCs[RTLIB::UO_F32] = ISD::SETNE;
770 CCs[RTLIB::UO_F64] = ISD::SETNE;
771 CCs[RTLIB::UO_F128] = ISD::SETNE;
772 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
773}
774
775/// NOTE: The TargetMachine owns TLOF.
777 initActions();
778
779 // Perform these initializations only once.
785 HasMultipleConditionRegisters = false;
786 HasExtractBitsInsn = false;
787 JumpIsExpensive = JumpIsExpensiveOverride;
789 EnableExtLdPromotion = false;
790 StackPointerRegisterToSaveRestore = 0;
791 BooleanContents = UndefinedBooleanContent;
792 BooleanFloatContents = UndefinedBooleanContent;
793 BooleanVectorContents = UndefinedBooleanContent;
794 SchedPreferenceInfo = Sched::ILP;
797 MaxBytesForAlignment = 0;
798 MaxAtomicSizeInBitsSupported = 0;
799
800 // Assume that even with libcalls, no target supports wider than 128 bit
801 // division.
802 MaxDivRemBitWidthSupported = 128;
803
804 MaxLargeFPConvertBitWidthSupported = llvm::IntegerType::MAX_INT_BITS;
805
806 MinCmpXchgSizeInBits = 0;
807 SupportsUnalignedAtomics = false;
808
809 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
810
811 InitLibcalls(TM.getTargetTriple());
812 InitCmpLibcallCCs(CmpLibcallCCs);
813}
814
816 // All operations default to being supported.
817 memset(OpActions, 0, sizeof(OpActions));
818 memset(LoadExtActions, 0, sizeof(LoadExtActions));
819 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
820 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
821 memset(CondCodeActions, 0, sizeof(CondCodeActions));
822 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
823 std::fill(std::begin(TargetDAGCombineArray),
824 std::end(TargetDAGCombineArray), 0);
825
826 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
827 // remove this and targets should individually set these types if not legal.
830 for (MVT VT : {MVT::i2, MVT::i4})
831 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
832 }
833 for (MVT AVT : MVT::all_valuetypes()) {
834 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
835 setTruncStoreAction(AVT, VT, Expand);
838 }
839 }
840 for (unsigned IM = (unsigned)ISD::PRE_INC;
841 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
842 for (MVT VT : {MVT::i2, MVT::i4}) {
847 }
848 }
849
850 for (MVT VT : MVT::fp_valuetypes()) {
851 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
852 if (IntVT.isValid()) {
855 }
856 }
857
858 // Set default actions for various operations.
859 for (MVT VT : MVT::all_valuetypes()) {
860 // Default all indexed load / store to expand.
861 for (unsigned IM = (unsigned)ISD::PRE_INC;
862 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
867 }
868
869 // Most backends expect to see the node which just returns the value loaded.
871
872 // These operations default to expand.
890 VT, Expand);
891
892 // Overflow operations default to expand
895 VT, Expand);
896
897 // Carry-using overflow operations default to expand.
900 VT, Expand);
901
902 // ADDC/ADDE/SUBC/SUBE default to expand.
904 Expand);
905
906 // Halving adds
909 Expand);
910
911 // Absolute difference
913
914 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
916 Expand);
917
919
920 // These library functions default to expand.
922 Expand);
923
924 // These operations default to expand for vector types.
925 if (VT.isVector())
930 VT, Expand);
931
932 // Constrained floating-point operations default to expand.
933#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
934 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
935#include "llvm/IR/ConstrainedOps.def"
936
937 // For most targets @llvm.get.dynamic.area.offset just returns 0.
939
940 // Vector reduction default to expand.
948 VT, Expand);
949
950 // Named vector shuffles default to expand.
952
953 // VP operations default to expand.
954#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
955 setOperationAction(ISD::SDOPC, VT, Expand);
956#include "llvm/IR/VPIntrinsics.def"
957
958 // FP environment operations default to expand.
962 }
963
964 // Most targets ignore the @llvm.prefetch intrinsic.
966
967 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
969
970 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
972
973 // ConstantFP nodes default to expand. Targets can either change this to
974 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
975 // to optimize expansions for certain constants.
977 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
978 Expand);
979
980 // These library functions default to expand.
985 {MVT::f32, MVT::f64, MVT::f128}, Expand);
986
987 // Default ISD::TRAP to expand (which turns it into abort).
988 setOperationAction(ISD::TRAP, MVT::Other, Expand);
989
990 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
991 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
993
995
998
999 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1002 }
1004}
1005
1007 EVT) const {
1008 return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
1009}
1010
1012 bool LegalTypes) const {
1013 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1014 if (LHSTy.isVector())
1015 return LHSTy;
1016 MVT ShiftVT =
1017 LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) : getPointerTy(DL);
1018 // If any possible shift value won't fit in the prefered type, just use
1019 // something safe. Assume it will be legalized when the shift is expanded.
1020 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits()))
1021 ShiftVT = MVT::i32;
1022 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1023 "ShiftVT is still too small!");
1024 return ShiftVT;
1025}
1026
1027bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1028 assert(isTypeLegal(VT));
1029 switch (Op) {
1030 default:
1031 return false;
1032 case ISD::SDIV:
1033 case ISD::UDIV:
1034 case ISD::SREM:
1035 case ISD::UREM:
1036 return true;
1037 }
1038}
1039
1041 unsigned DestAS) const {
1042 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1043}
1044
1046 // If the command-line option was specified, ignore this request.
1047 if (!JumpIsExpensiveOverride.getNumOccurrences())
1048 JumpIsExpensive = isExpensive;
1049}
1050
1053 // If this is a simple type, use the ComputeRegisterProp mechanism.
1054 if (VT.isSimple()) {
1055 MVT SVT = VT.getSimpleVT();
1056 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1057 MVT NVT = TransformToType[SVT.SimpleTy];
1058 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1059
1060 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1061 LA == TypeSoftPromoteHalf ||
1062 (NVT.isVector() ||
1063 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1064 "Promote may not follow Expand or Promote");
1065
1066 if (LA == TypeSplitVector)
1067 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1068 if (LA == TypeScalarizeVector)
1069 return LegalizeKind(LA, SVT.getVectorElementType());
1070 return LegalizeKind(LA, NVT);
1071 }
1072
1073 // Handle Extended Scalar Types.
1074 if (!VT.isVector()) {
1075 assert(VT.isInteger() && "Float types must be simple");
1076 unsigned BitSize = VT.getSizeInBits();
1077 // First promote to a power-of-two size, then expand if necessary.
1078 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1080 assert(NVT != VT && "Unable to round integer VT");
1081 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1082 // Avoid multi-step promotion.
1083 if (NextStep.first == TypePromoteInteger)
1084 return NextStep;
1085 // Return rounded integer type.
1086 return LegalizeKind(TypePromoteInteger, NVT);
1087 }
1088
1091 }
1092
1093 // Handle vector types.
1094 ElementCount NumElts = VT.getVectorElementCount();
1095 EVT EltVT = VT.getVectorElementType();
1096
1097 // Vectors with only one element are always scalarized.
1098 if (NumElts.isScalar())
1099 return LegalizeKind(TypeScalarizeVector, EltVT);
1100
1101 // Try to widen vector elements until the element type is a power of two and
1102 // promote it to a legal type later on, for example:
1103 // <3 x i8> -> <4 x i8> -> <4 x i32>
1104 if (EltVT.isInteger()) {
1105 // Vectors with a number of elements that is not a power of two are always
1106 // widened, for example <3 x i8> -> <4 x i8>.
1107 if (!VT.isPow2VectorType()) {
1108 NumElts = NumElts.coefficientNextPowerOf2();
1109 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1110 return LegalizeKind(TypeWidenVector, NVT);
1111 }
1112
1113 // Examine the element type.
1115
1116 // If type is to be expanded, split the vector.
1117 // <4 x i140> -> <2 x i140>
1118 if (LK.first == TypeExpandInteger) {
1123 }
1124
1125 // Promote the integer element types until a legal vector type is found
1126 // or until the element integer type is too big. If a legal type was not
1127 // found, fallback to the usual mechanism of widening/splitting the
1128 // vector.
1129 EVT OldEltVT = EltVT;
1130 while (true) {
1131 // Increase the bitwidth of the element to the next pow-of-two
1132 // (which is greater than 8 bits).
1133 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1135
1136 // Stop trying when getting a non-simple element type.
1137 // Note that vector elements may be greater than legal vector element
1138 // types. Example: X86 XMM registers hold 64bit element on 32bit
1139 // systems.
1140 if (!EltVT.isSimple())
1141 break;
1142
1143 // Build a new vector type and check if it is legal.
1144 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1145 // Found a legal promoted vector type.
1146 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1148 EVT::getVectorVT(Context, EltVT, NumElts));
1149 }
1150
1151 // Reset the type to the unexpanded type if we did not find a legal vector
1152 // type with a promoted vector element type.
1153 EltVT = OldEltVT;
1154 }
1155
1156 // Try to widen the vector until a legal type is found.
1157 // If there is no wider legal type, split the vector.
1158 while (true) {
1159 // Round up to the next power of 2.
1160 NumElts = NumElts.coefficientNextPowerOf2();
1161
1162 // If there is no simple vector type with this many elements then there
1163 // cannot be a larger legal vector type. Note that this assumes that
1164 // there are no skipped intermediate vector types in the simple types.
1165 if (!EltVT.isSimple())
1166 break;
1167 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1168 if (LargerVector == MVT())
1169 break;
1170
1171 // If this type is legal then widen the vector.
1172 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1173 return LegalizeKind(TypeWidenVector, LargerVector);
1174 }
1175
1176 // Widen odd vectors to next power of two.
1177 if (!VT.isPow2VectorType()) {
1178 EVT NVT = VT.getPow2VectorType(Context);
1179 return LegalizeKind(TypeWidenVector, NVT);
1180 }
1181
1184
1185 // Vectors with illegal element types are expanded.
1186 EVT NVT = EVT::getVectorVT(Context, EltVT,
1188 return LegalizeKind(TypeSplitVector, NVT);
1189}
1190
1191static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1192 unsigned &NumIntermediates,
1193 MVT &RegisterVT,
1194 TargetLoweringBase *TLI) {
1195 // Figure out the right, legal destination reg to copy into.
1197 MVT EltTy = VT.getVectorElementType();
1198
1199 unsigned NumVectorRegs = 1;
1200
1201 // Scalable vectors cannot be scalarized, so splitting or widening is
1202 // required.
1203 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1205 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1206
1207 // FIXME: We don't support non-power-of-2-sized vectors for now.
1208 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1209 if (!isPowerOf2_32(EC.getKnownMinValue())) {
1210 // Split EC to unit size (scalable property is preserved).
1211 NumVectorRegs = EC.getKnownMinValue();
1212 EC = ElementCount::getFixed(1);
1213 }
1214
1215 // Divide the input until we get to a supported size. This will
1216 // always end up with an EC that represent a scalar or a scalable
1217 // scalar.
1218 while (EC.getKnownMinValue() > 1 &&
1219 !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1220 EC = EC.divideCoefficientBy(2);
1221 NumVectorRegs <<= 1;
1222 }
1223
1224 NumIntermediates = NumVectorRegs;
1225
1226 MVT NewVT = MVT::getVectorVT(EltTy, EC);
1227 if (!TLI->isTypeLegal(NewVT))
1228 NewVT = EltTy;
1229 IntermediateVT = NewVT;
1230
1231 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1232
1233 // Convert sizes such as i33 to i64.
1234 LaneSizeInBits = llvm::bit_ceil(LaneSizeInBits);
1235
1236 MVT DestVT = TLI->getRegisterType(NewVT);
1237 RegisterVT = DestVT;
1238 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1239 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1240
1241 // Otherwise, promotion or legal types use the same number of registers as
1242 // the vector decimated to the appropriate level.
1243 return NumVectorRegs;
1244}
1245
1246/// isLegalRC - Return true if the value types that can be represented by the
1247/// specified register class are all legal.
1249 const TargetRegisterClass &RC) const {
1250 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1251 if (isTypeLegal(*I))
1252 return true;
1253 return false;
1254}
1255
1256/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1257/// sequence of memory operands that is recognized by PrologEpilogInserter.
1260 MachineBasicBlock *MBB) const {
1261 MachineInstr *MI = &InitialMI;
1262 MachineFunction &MF = *MI->getMF();
1263 MachineFrameInfo &MFI = MF.getFrameInfo();
1264
1265 // We're handling multiple types of operands here:
1266 // PATCHPOINT MetaArgs - live-in, read only, direct
1267 // STATEPOINT Deopt Spill - live-through, read only, indirect
1268 // STATEPOINT Deopt Alloca - live-through, read only, direct
1269 // (We're currently conservative and mark the deopt slots read/write in
1270 // practice.)
1271 // STATEPOINT GC Spill - live-through, read/write, indirect
1272 // STATEPOINT GC Alloca - live-through, read/write, direct
1273 // The live-in vs live-through is handled already (the live through ones are
1274 // all stack slots), but we need to handle the different type of stackmap
1275 // operands and memory effects here.
1276
1277 if (llvm::none_of(MI->operands(),
1278 [](MachineOperand &Operand) { return Operand.isFI(); }))
1279 return MBB;
1280
1281 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1282
1283 // Inherit previous memory operands.
1284 MIB.cloneMemRefs(*MI);
1285
1286 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1287 MachineOperand &MO = MI->getOperand(i);
1288 if (!MO.isFI()) {
1289 // Index of Def operand this Use it tied to.
1290 // Since Defs are coming before Uses, if Use is tied, then
1291 // index of Def must be smaller that index of that Use.
1292 // Also, Defs preserve their position in new MI.
1293 unsigned TiedTo = i;
1294 if (MO.isReg() && MO.isTied())
1295 TiedTo = MI->findTiedOperandIdx(i);
1296 MIB.add(MO);
1297 if (TiedTo < i)
1298 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1299 continue;
1300 }
1301
1302 // foldMemoryOperand builds a new MI after replacing a single FI operand
1303 // with the canonical set of five x86 addressing-mode operands.
1304 int FI = MO.getIndex();
1305
1306 // Add frame index operands recognized by stackmaps.cpp
1308 // indirect-mem-ref tag, size, #FI, offset.
1309 // Used for spills inserted by StatepointLowering. This codepath is not
1310 // used for patchpoints/stackmaps at all, for these spilling is done via
1311 // foldMemoryOperand callback only.
1312 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1313 MIB.addImm(StackMaps::IndirectMemRefOp);
1314 MIB.addImm(MFI.getObjectSize(FI));
1315 MIB.add(MO);
1316 MIB.addImm(0);
1317 } else {
1318 // direct-mem-ref tag, #FI, offset.
1319 // Used by patchpoint, and direct alloca arguments to statepoints
1320 MIB.addImm(StackMaps::DirectMemRefOp);
1321 MIB.add(MO);
1322 MIB.addImm(0);
1323 }
1324
1325 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1326
1327 // Add a new memory operand for this FI.
1328 assert(MFI.getObjectOffset(FI) != -1);
1329
1330 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1331 // PATCHPOINT should be updated to do the same. (TODO)
1332 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1333 auto Flags = MachineMemOperand::MOLoad;
1335 MachinePointerInfo::getFixedStack(MF, FI), Flags,
1337 MIB->addMemOperand(MF, MMO);
1338 }
1339 }
1341 MI->eraseFromParent();
1342 return MBB;
1343}
1344
1345/// findRepresentativeClass - Return the largest legal super-reg register class
1346/// of the register class for the specified type and its associated "cost".
1347// This function is in TargetLowering because it uses RegClassForVT which would
1348// need to be moved to TargetRegisterInfo and would necessitate moving
1349// isTypeLegal over as well - a massive change that would just require
1350// TargetLowering having a TargetRegisterInfo class member that it would use.
1351std::pair<const TargetRegisterClass *, uint8_t>
1353 MVT VT) const {
1354 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1355 if (!RC)
1356 return std::make_pair(RC, 0);
1357
1358 // Compute the set of all super-register classes.
1359 BitVector SuperRegRC(TRI->getNumRegClasses());
1360 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1361 SuperRegRC.setBitsInMask(RCI.getMask());
1362
1363 // Find the first legal register class with the largest spill size.
1364 const TargetRegisterClass *BestRC = RC;
1365 for (unsigned i : SuperRegRC.set_bits()) {
1366 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1367 // We want the largest possible spill size.
1368 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1369 continue;
1370 if (!isLegalRC(*TRI, *SuperRC))
1371 continue;
1372 BestRC = SuperRC;
1373 }
1374 return std::make_pair(BestRC, 1);
1375}
1376
1377/// computeRegisterProperties - Once all of the register classes are added,
1378/// this allows us to compute derived properties we expose.
1380 const TargetRegisterInfo *TRI) {
1382 "Too many value types for ValueTypeActions to hold!");
1383
1384 // Everything defaults to needing one register.
1385 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1386 NumRegistersForVT[i] = 1;
1387 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1388 }
1389 // ...except isVoid, which doesn't need any registers.
1390 NumRegistersForVT[MVT::isVoid] = 0;
1391
1392 // Find the largest integer register class.
1393 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1394 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1395 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1396
1397 // Every integer value type larger than this largest register takes twice as
1398 // many registers to represent as the previous ValueType.
1399 for (unsigned ExpandedReg = LargestIntReg + 1;
1400 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1401 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1402 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1403 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1404 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1406 }
1407
1408 // Inspect all of the ValueType's smaller than the largest integer
1409 // register to see which ones need promotion.
1410 unsigned LegalIntReg = LargestIntReg;
1411 for (unsigned IntReg = LargestIntReg - 1;
1412 IntReg >= (unsigned)MVT::i1; --IntReg) {
1413 MVT IVT = (MVT::SimpleValueType)IntReg;
1414 if (isTypeLegal(IVT)) {
1415 LegalIntReg = IntReg;
1416 } else {
1417 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1418 (MVT::SimpleValueType)LegalIntReg;
1419 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1420 }
1421 }
1422
1423 // ppcf128 type is really two f64's.
1424 if (!isTypeLegal(MVT::ppcf128)) {
1425 if (isTypeLegal(MVT::f64)) {
1426 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1427 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1428 TransformToType[MVT::ppcf128] = MVT::f64;
1429 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1430 } else {
1431 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1432 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1433 TransformToType[MVT::ppcf128] = MVT::i128;
1434 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1435 }
1436 }
1437
1438 // Decide how to handle f128. If the target does not have native f128 support,
1439 // expand it to i128 and we will be generating soft float library calls.
1440 if (!isTypeLegal(MVT::f128)) {
1441 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1442 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1443 TransformToType[MVT::f128] = MVT::i128;
1444 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1445 }
1446
1447 // Decide how to handle f80. If the target does not have native f80 support,
1448 // expand it to i96 and we will be generating soft float library calls.
1449 if (!isTypeLegal(MVT::f80)) {
1450 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1451 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1452 TransformToType[MVT::f80] = MVT::i32;
1453 ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat);
1454 }
1455
1456 // Decide how to handle f64. If the target does not have native f64 support,
1457 // expand it to i64 and we will be generating soft float library calls.
1458 if (!isTypeLegal(MVT::f64)) {
1459 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1460 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1461 TransformToType[MVT::f64] = MVT::i64;
1462 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1463 }
1464
1465 // Decide how to handle f32. If the target does not have native f32 support,
1466 // expand it to i32 and we will be generating soft float library calls.
1467 if (!isTypeLegal(MVT::f32)) {
1468 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1469 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1470 TransformToType[MVT::f32] = MVT::i32;
1471 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1472 }
1473
1474 // Decide how to handle f16. If the target does not have native f16 support,
1475 // promote it to f32, because there are no f16 library calls (except for
1476 // conversions).
1477 if (!isTypeLegal(MVT::f16)) {
1478 // Allow targets to control how we legalize half.
1479 bool SoftPromoteHalfType = softPromoteHalfType();
1480 bool UseFPRegsForHalfType = !SoftPromoteHalfType || useFPRegsForHalfType();
1481
1482 if (!UseFPRegsForHalfType) {
1483 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1484 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1485 } else {
1486 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1487 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1488 }
1489 TransformToType[MVT::f16] = MVT::f32;
1490 if (SoftPromoteHalfType) {
1491 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1492 } else {
1493 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1494 }
1495 }
1496
1497 // Decide how to handle bf16. If the target does not have native bf16 support,
1498 // promote it to f32, because there are no bf16 library calls (except for
1499 // converting from f32 to bf16).
1500 if (!isTypeLegal(MVT::bf16)) {
1501 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1502 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1503 TransformToType[MVT::bf16] = MVT::f32;
1504 ValueTypeActions.setTypeAction(MVT::bf16, TypeSoftPromoteHalf);
1505 }
1506
1507 // Loop over all of the vector value types to see which need transformations.
1508 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1509 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1510 MVT VT = (MVT::SimpleValueType) i;
1511 if (isTypeLegal(VT))
1512 continue;
1513
1514 MVT EltVT = VT.getVectorElementType();
1516 bool IsLegalWiderType = false;
1517 bool IsScalable = VT.isScalableVector();
1518 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1519 switch (PreferredAction) {
1520 case TypePromoteInteger: {
1521 MVT::SimpleValueType EndVT = IsScalable ?
1522 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1523 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1524 // Try to promote the elements of integer vectors. If no legal
1525 // promotion was found, fall through to the widen-vector method.
1526 for (unsigned nVT = i + 1;
1527 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1528 MVT SVT = (MVT::SimpleValueType) nVT;
1529 // Promote vectors of integers to vectors with the same number
1530 // of elements, with a wider element type.
1531 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1532 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1533 TransformToType[i] = SVT;
1534 RegisterTypeForVT[i] = SVT;
1535 NumRegistersForVT[i] = 1;
1536 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1537 IsLegalWiderType = true;
1538 break;
1539 }
1540 }
1541 if (IsLegalWiderType)
1542 break;
1543 [[fallthrough]];
1544 }
1545
1546 case TypeWidenVector:
1547 if (isPowerOf2_32(EC.getKnownMinValue())) {
1548 // Try to widen the vector.
1549 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1550 MVT SVT = (MVT::SimpleValueType) nVT;
1551 if (SVT.getVectorElementType() == EltVT &&
1552 SVT.isScalableVector() == IsScalable &&
1554 EC.getKnownMinValue() &&
1555 isTypeLegal(SVT)) {
1556 TransformToType[i] = SVT;
1557 RegisterTypeForVT[i] = SVT;
1558 NumRegistersForVT[i] = 1;
1559 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1560 IsLegalWiderType = true;
1561 break;
1562 }
1563 }
1564 if (IsLegalWiderType)
1565 break;
1566 } else {
1567 // Only widen to the next power of 2 to keep consistency with EVT.
1568 MVT NVT = VT.getPow2VectorType();
1569 if (isTypeLegal(NVT)) {
1570 TransformToType[i] = NVT;
1571 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1572 RegisterTypeForVT[i] = NVT;
1573 NumRegistersForVT[i] = 1;
1574 break;
1575 }
1576 }
1577 [[fallthrough]];
1578
1579 case TypeSplitVector:
1580 case TypeScalarizeVector: {
1581 MVT IntermediateVT;
1582 MVT RegisterVT;
1583 unsigned NumIntermediates;
1584 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1585 NumIntermediates, RegisterVT, this);
1586 NumRegistersForVT[i] = NumRegisters;
1587 assert(NumRegistersForVT[i] == NumRegisters &&
1588 "NumRegistersForVT size cannot represent NumRegisters!");
1589 RegisterTypeForVT[i] = RegisterVT;
1590
1591 MVT NVT = VT.getPow2VectorType();
1592 if (NVT == VT) {
1593 // Type is already a power of 2. The default action is to split.
1594 TransformToType[i] = MVT::Other;
1595 if (PreferredAction == TypeScalarizeVector)
1596 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1597 else if (PreferredAction == TypeSplitVector)
1598 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1599 else if (EC.getKnownMinValue() > 1)
1600 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1601 else
1602 ValueTypeActions.setTypeAction(VT, EC.isScalable()
1605 } else {
1606 TransformToType[i] = NVT;
1607 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1608 }
1609 break;
1610 }
1611 default:
1612 llvm_unreachable("Unknown vector legalization action!");
1613 }
1614 }
1615
1616 // Determine the 'representative' register class for each value type.
1617 // An representative register class is the largest (meaning one which is
1618 // not a sub-register class / subreg register class) legal register class for
1619 // a group of value types. For example, on i386, i8, i16, and i32
1620 // representative would be GR32; while on x86_64 it's GR64.
1621 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1622 const TargetRegisterClass* RRC;
1623 uint8_t Cost;
1625 RepRegClassForVT[i] = RRC;
1626 RepRegClassCostForVT[i] = Cost;
1627 }
1628}
1629
1631 EVT VT) const {
1632 assert(!VT.isVector() && "No default SetCC type for vectors!");
1633 return getPointerTy(DL).SimpleTy;
1634}
1635
1637 return MVT::i32; // return the default value
1638}
1639
1640/// getVectorTypeBreakdown - Vector types are broken down into some number of
1641/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1642/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1643/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1644///
1645/// This method returns the number of registers needed, and the VT for each
1646/// register. It also returns the VT and quantity of the intermediate values
1647/// before they are promoted/expanded.
1649 EVT VT, EVT &IntermediateVT,
1650 unsigned &NumIntermediates,
1651 MVT &RegisterVT) const {
1652 ElementCount EltCnt = VT.getVectorElementCount();
1653
1654 // If there is a wider vector type with the same element type as this one,
1655 // or a promoted vector type that has the same number of elements which
1656 // are wider, then we should convert to that legal vector type.
1657 // This handles things like <2 x float> -> <4 x float> and
1658 // <4 x i1> -> <4 x i32>.
1660 if (!EltCnt.isScalar() &&
1661 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1662 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1663 if (isTypeLegal(RegisterEVT)) {
1664 IntermediateVT = RegisterEVT;
1665 RegisterVT = RegisterEVT.getSimpleVT();
1666 NumIntermediates = 1;
1667 return 1;
1668 }
1669 }
1670
1671 // Figure out the right, legal destination reg to copy into.
1672 EVT EltTy = VT.getVectorElementType();
1673
1674 unsigned NumVectorRegs = 1;
1675
1676 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1677 // types like done elsewhere in SelectionDAG.
1678 if (EltCnt.isScalable()) {
1679 LegalizeKind LK;
1680 EVT PartVT = VT;
1681 do {
1682 // Iterate until we've found a legal (part) type to hold VT.
1683 LK = getTypeConversion(Context, PartVT);
1684 PartVT = LK.second;
1685 } while (LK.first != TypeLegal);
1686
1687 if (!PartVT.isVector()) {
1689 "Don't know how to legalize this scalable vector type");
1690 }
1691
1692 NumIntermediates =
1695 IntermediateVT = PartVT;
1696 RegisterVT = getRegisterType(Context, IntermediateVT);
1697 return NumIntermediates;
1698 }
1699
1700 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1701 // we could break down into LHS/RHS like LegalizeDAG does.
1702 if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1703 NumVectorRegs = EltCnt.getKnownMinValue();
1704 EltCnt = ElementCount::getFixed(1);
1705 }
1706
1707 // Divide the input until we get to a supported size. This will always
1708 // end with a scalar if the target doesn't support vectors.
1709 while (EltCnt.getKnownMinValue() > 1 &&
1710 !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1711 EltCnt = EltCnt.divideCoefficientBy(2);
1712 NumVectorRegs <<= 1;
1713 }
1714
1715 NumIntermediates = NumVectorRegs;
1716
1717 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1718 if (!isTypeLegal(NewVT))
1719 NewVT = EltTy;
1720 IntermediateVT = NewVT;
1721
1722 MVT DestVT = getRegisterType(Context, NewVT);
1723 RegisterVT = DestVT;
1724
1725 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1726 TypeSize NewVTSize = NewVT.getSizeInBits();
1727 // Convert sizes such as i33 to i64.
1728 if (!llvm::has_single_bit<uint32_t>(NewVTSize.getKnownMinValue()))
1729 NewVTSize = NewVTSize.coefficientNextPowerOf2();
1730 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1731 }
1732
1733 // Otherwise, promotion or legal types use the same number of registers as
1734 // the vector decimated to the appropriate level.
1735 return NumVectorRegs;
1736}
1737
1739 uint64_t NumCases,
1740 uint64_t Range,
1741 ProfileSummaryInfo *PSI,
1742 BlockFrequencyInfo *BFI) const {
1743 // FIXME: This function check the maximum table size and density, but the
1744 // minimum size is not checked. It would be nice if the minimum size is
1745 // also combined within this function. Currently, the minimum size check is
1746 // performed in findJumpTable() in SelectionDAGBuiler and
1747 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1748 const bool OptForSize =
1749 SI->getParent()->getParent()->hasOptSize() ||
1750 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1751 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1752 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1753
1754 // Check whether the number of cases is small enough and
1755 // the range is dense enough for a jump table.
1756 return (OptForSize || Range <= MaxJumpTableSize) &&
1757 (NumCases * 100 >= Range * MinDensity);
1758}
1759
1761 EVT ConditionVT) const {
1762 return getRegisterType(Context, ConditionVT);
1763}
1764
1765/// Get the EVTs and ArgFlags collections that represent the legalized return
1766/// type of the given function. This does not require a DAG or a return value,
1767/// and is suitable for use before any DAGs for the function are constructed.
1768/// TODO: Move this out of TargetLowering.cpp.
1770 AttributeList attr,
1772 const TargetLowering &TLI, const DataLayout &DL) {
1773 SmallVector<EVT, 4> ValueVTs;
1774 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1775 unsigned NumValues = ValueVTs.size();
1776 if (NumValues == 0) return;
1777
1778 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1779 EVT VT = ValueVTs[j];
1780 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1781
1782 if (attr.hasRetAttr(Attribute::SExt))
1783 ExtendKind = ISD::SIGN_EXTEND;
1784 else if (attr.hasRetAttr(Attribute::ZExt))
1785 ExtendKind = ISD::ZERO_EXTEND;
1786
1787 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1788 VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind);
1789
1790 unsigned NumParts =
1791 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1792 MVT PartVT =
1793 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1794
1795 // 'inreg' on function refers to return value
1797 if (attr.hasRetAttr(Attribute::InReg))
1798 Flags.setInReg();
1799
1800 // Propagate extension type if any
1801 if (attr.hasRetAttr(Attribute::SExt))
1802 Flags.setSExt();
1803 else if (attr.hasRetAttr(Attribute::ZExt))
1804 Flags.setZExt();
1805
1806 for (unsigned i = 0; i < NumParts; ++i)
1807 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0));
1808 }
1809}
1810
1811/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1812/// function arguments in the caller parameter area. This is the actual
1813/// alignment, not its logarithm.
1815 const DataLayout &DL) const {
1816 return DL.getABITypeAlign(Ty).value();
1817}
1818
1820 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1821 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
1822 // Check if the specified alignment is sufficient based on the data layout.
1823 // TODO: While using the data layout works in practice, a better solution
1824 // would be to implement this check directly (make this a virtual function).
1825 // For example, the ABI alignment may change based on software platform while
1826 // this function should only be affected by hardware implementation.
1827 Type *Ty = VT.getTypeForEVT(Context);
1828 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1829 // Assume that an access that meets the ABI-specified alignment is fast.
1830 if (Fast != nullptr)
1831 *Fast = 1;
1832 return true;
1833 }
1834
1835 // This is a misaligned access.
1836 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1837}
1838
1840 LLVMContext &Context, const DataLayout &DL, EVT VT,
1841 const MachineMemOperand &MMO, unsigned *Fast) const {
1843 MMO.getAlign(), MMO.getFlags(), Fast);
1844}
1845
1847 const DataLayout &DL, EVT VT,
1848 unsigned AddrSpace, Align Alignment,
1850 unsigned *Fast) const {
1851 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1852 Flags, Fast);
1853}
1854
1856 const DataLayout &DL, EVT VT,
1857 const MachineMemOperand &MMO,
1858 unsigned *Fast) const {
1859 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1860 MMO.getFlags(), Fast);
1861}
1862
1864 const DataLayout &DL, LLT Ty,
1865 const MachineMemOperand &MMO,
1866 unsigned *Fast) const {
1868 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1869 MMO.getFlags(), Fast);
1870}
1871
1872//===----------------------------------------------------------------------===//
1873// TargetTransformInfo Helpers
1874//===----------------------------------------------------------------------===//
1875
1877 enum InstructionOpcodes {
1878#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1879#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1880#include "llvm/IR/Instruction.def"
1881 };
1882 switch (static_cast<InstructionOpcodes>(Opcode)) {
1883 case Ret: return 0;
1884 case Br: return 0;
1885 case Switch: return 0;
1886 case IndirectBr: return 0;
1887 case Invoke: return 0;
1888 case CallBr: return 0;
1889 case Resume: return 0;
1890 case Unreachable: return 0;
1891 case CleanupRet: return 0;
1892 case CatchRet: return 0;
1893 case CatchPad: return 0;
1894 case CatchSwitch: return 0;
1895 case CleanupPad: return 0;
1896 case FNeg: return ISD::FNEG;
1897 case Add: return ISD::ADD;
1898 case FAdd: return ISD::FADD;
1899 case Sub: return ISD::SUB;
1900 case FSub: return ISD::FSUB;
1901 case Mul: return ISD::MUL;
1902 case FMul: return ISD::FMUL;
1903 case UDiv: return ISD::UDIV;
1904 case SDiv: return ISD::SDIV;
1905 case FDiv: return ISD::FDIV;
1906 case URem: return ISD::UREM;
1907 case SRem: return ISD::SREM;
1908 case FRem: return ISD::FREM;
1909 case Shl: return ISD::SHL;
1910 case LShr: return ISD::SRL;
1911 case AShr: return ISD::SRA;
1912 case And: return ISD::AND;
1913 case Or: return ISD::OR;
1914 case Xor: return ISD::XOR;
1915 case Alloca: return 0;
1916 case Load: return ISD::LOAD;
1917 case Store: return ISD::STORE;
1918 case GetElementPtr: return 0;
1919 case Fence: return 0;
1920 case AtomicCmpXchg: return 0;
1921 case AtomicRMW: return 0;
1922 case Trunc: return ISD::TRUNCATE;
1923 case ZExt: return ISD::ZERO_EXTEND;
1924 case SExt: return ISD::SIGN_EXTEND;
1925 case FPToUI: return ISD::FP_TO_UINT;
1926 case FPToSI: return ISD::FP_TO_SINT;
1927 case UIToFP: return ISD::UINT_TO_FP;
1928 case SIToFP: return ISD::SINT_TO_FP;
1929 case FPTrunc: return ISD::FP_ROUND;
1930 case FPExt: return ISD::FP_EXTEND;
1931 case PtrToInt: return ISD::BITCAST;
1932 case IntToPtr: return ISD::BITCAST;
1933 case BitCast: return ISD::BITCAST;
1934 case AddrSpaceCast: return ISD::ADDRSPACECAST;
1935 case ICmp: return ISD::SETCC;
1936 case FCmp: return ISD::SETCC;
1937 case PHI: return 0;
1938 case Call: return 0;
1939 case Select: return ISD::SELECT;
1940 case UserOp1: return 0;
1941 case UserOp2: return 0;
1942 case VAArg: return 0;
1943 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1944 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1945 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1946 case ExtractValue: return ISD::MERGE_VALUES;
1947 case InsertValue: return ISD::MERGE_VALUES;
1948 case LandingPad: return 0;
1949 case Freeze: return ISD::FREEZE;
1950 }
1951
1952 llvm_unreachable("Unknown instruction type encountered!");
1953}
1954
1955Value *
1957 bool UseTLS) const {
1958 // compiler-rt provides a variable with a magic name. Targets that do not
1959 // link with compiler-rt may also provide such a variable.
1960 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1961 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1962 auto UnsafeStackPtr =
1963 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1964
1965 Type *StackPtrTy = PointerType::getUnqual(M->getContext());
1966
1967 if (!UnsafeStackPtr) {
1968 auto TLSModel = UseTLS ?
1971 // The global variable is not defined yet, define it ourselves.
1972 // We use the initial-exec TLS model because we do not support the
1973 // variable living anywhere other than in the main executable.
1974 UnsafeStackPtr = new GlobalVariable(
1975 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1976 UnsafeStackPtrVar, nullptr, TLSModel);
1977 } else {
1978 // The variable exists, check its type and attributes.
1979 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1980 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1981 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1982 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1983 (UseTLS ? "" : "not ") + "be thread-local");
1984 }
1985 return UnsafeStackPtr;
1986}
1987
1988Value *
1990 if (!TM.getTargetTriple().isAndroid())
1991 return getDefaultSafeStackPointerLocation(IRB, true);
1992
1993 // Android provides a libc function to retrieve the address of the current
1994 // thread's unsafe stack pointer.
1995 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1996 auto *PtrTy = PointerType::getUnqual(M->getContext());
1997 FunctionCallee Fn =
1998 M->getOrInsertFunction("__safestack_pointer_address", PtrTy);
1999 return IRB.CreateCall(Fn);
2000}
2001
2002//===----------------------------------------------------------------------===//
2003// Loop Strength Reduction hooks
2004//===----------------------------------------------------------------------===//
2005
2006/// isLegalAddressingMode - Return true if the addressing mode represented
2007/// by AM is legal for this target, for a load/store of the specified type.
2009 const AddrMode &AM, Type *Ty,
2010 unsigned AS, Instruction *I) const {
2011 // The default implementation of this implements a conservative RISCy, r+r and
2012 // r+i addr mode.
2013
2014 // Allows a sign-extended 16-bit immediate field.
2015 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2016 return false;
2017
2018 // No global is ever allowed as a base.
2019 if (AM.BaseGV)
2020 return false;
2021
2022 // Only support r+r,
2023 switch (AM.Scale) {
2024 case 0: // "r+i" or just "i", depending on HasBaseReg.
2025 break;
2026 case 1:
2027 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2028 return false;
2029 // Otherwise we have r+r or r+i.
2030 break;
2031 case 2:
2032 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2033 return false;
2034 // Allow 2*r as r+r.
2035 break;
2036 default: // Don't allow n * r
2037 return false;
2038 }
2039
2040 return true;
2041}
2042
2043//===----------------------------------------------------------------------===//
2044// Stack Protector
2045//===----------------------------------------------------------------------===//
2046
2047// For OpenBSD return its special guard variable. Otherwise return nullptr,
2048// so that SelectionDAG handle SSP.
2050 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
2051 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
2052 PointerType *PtrTy = PointerType::getUnqual(M.getContext());
2053 Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
2054 if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
2055 G->setVisibility(GlobalValue::HiddenVisibility);
2056 return C;
2057 }
2058 return nullptr;
2059}
2060
2061// Currently only support "standard" __stack_chk_guard.
2062// TODO: add LOAD_STACK_GUARD support.
2064 if (!M.getNamedValue("__stack_chk_guard")) {
2065 auto *GV = new GlobalVariable(M, PointerType::getUnqual(M.getContext()),
2067 nullptr, "__stack_chk_guard");
2068
2069 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2070 if (M.getDirectAccessExternalData() &&
2072 !TM.getTargetTriple().isOSFreeBSD() &&
2073 (!TM.getTargetTriple().isOSDarwin() ||
2075 GV->setDSOLocal(true);
2076 }
2077}
2078
2079// Currently only support "standard" __stack_chk_guard.
2080// TODO: add LOAD_STACK_GUARD support.
2082 return M.getNamedValue("__stack_chk_guard");
2083}
2084
2086 return nullptr;
2087}
2088
2091}
2092
2095}
2096
2097unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2098 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2099}
2100
2102 return MaximumJumpTableSize;
2103}
2104
2107}
2108
2111}
2112
2114 if (TM.Options.LoopAlignment)
2115 return Align(TM.Options.LoopAlignment);
2116 return PrefLoopAlignment;
2117}
2118
2120 MachineBasicBlock *MBB) const {
2121 return MaxBytesForAlignment;
2122}
2123
2124//===----------------------------------------------------------------------===//
2125// Reciprocal Estimates
2126//===----------------------------------------------------------------------===//
2127
2128/// Get the reciprocal estimate attribute string for a function that will
2129/// override the target defaults.
2131 const Function &F = MF.getFunction();
2132 return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2133}
2134
2135/// Construct a string for the given reciprocal operation of the given type.
2136/// This string should match the corresponding option to the front-end's
2137/// "-mrecip" flag assuming those strings have been passed through in an
2138/// attribute string. For example, "vec-divf" for a division of a vXf32.
2139static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2140 std::string Name = VT.isVector() ? "vec-" : "";
2141
2142 Name += IsSqrt ? "sqrt" : "div";
2143
2144 // TODO: Handle other float types?
2145 if (VT.getScalarType() == MVT::f64) {
2146 Name += "d";
2147 } else if (VT.getScalarType() == MVT::f16) {
2148 Name += "h";
2149 } else {
2150 assert(VT.getScalarType() == MVT::f32 &&
2151 "Unexpected FP type for reciprocal estimate");
2152 Name += "f";
2153 }
2154
2155 return Name;
2156}
2157
2158/// Return the character position and value (a single numeric character) of a
2159/// customized refinement operation in the input string if it exists. Return
2160/// false if there is no customized refinement step count.
2161static bool parseRefinementStep(StringRef In, size_t &Position,
2162 uint8_t &Value) {
2163 const char RefStepToken = ':';
2164 Position = In.find(RefStepToken);
2165 if (Position == StringRef::npos)
2166 return false;
2167
2168 StringRef RefStepString = In.substr(Position + 1);
2169 // Allow exactly one numeric character for the additional refinement
2170 // step parameter.
2171 if (RefStepString.size() == 1) {
2172 char RefStepChar = RefStepString[0];
2173 if (isDigit(RefStepChar)) {
2174 Value = RefStepChar - '0';
2175 return true;
2176 }
2177 }
2178 report_fatal_error("Invalid refinement step for -recip.");
2179}
2180
2181/// For the input attribute string, return one of the ReciprocalEstimate enum
2182/// status values (enabled, disabled, or not specified) for this operation on
2183/// the specified data type.
2184static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2185 if (Override.empty())
2187
2188 SmallVector<StringRef, 4> OverrideVector;
2189 Override.split(OverrideVector, ',');
2190 unsigned NumArgs = OverrideVector.size();
2191
2192 // Check if "all", "none", or "default" was specified.
2193 if (NumArgs == 1) {
2194 // Look for an optional setting of the number of refinement steps needed
2195 // for this type of reciprocal operation.
2196 size_t RefPos;
2197 uint8_t RefSteps;
2198 if (parseRefinementStep(Override, RefPos, RefSteps)) {
2199 // Split the string for further processing.
2200 Override = Override.substr(0, RefPos);
2201 }
2202
2203 // All reciprocal types are enabled.
2204 if (Override == "all")
2206
2207 // All reciprocal types are disabled.
2208 if (Override == "none")
2210
2211 // Target defaults for enablement are used.
2212 if (Override == "default")
2214 }
2215
2216 // The attribute string may omit the size suffix ('f'/'d').
2217 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2218 std::string VTNameNoSize = VTName;
2219 VTNameNoSize.pop_back();
2220 static const char DisabledPrefix = '!';
2221
2222 for (StringRef RecipType : OverrideVector) {
2223 size_t RefPos;
2224 uint8_t RefSteps;
2225 if (parseRefinementStep(RecipType, RefPos, RefSteps))
2226 RecipType = RecipType.substr(0, RefPos);
2227
2228 // Ignore the disablement token for string matching.
2229 bool IsDisabled = RecipType[0] == DisabledPrefix;
2230 if (IsDisabled)
2231 RecipType = RecipType.substr(1);
2232
2233 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2236 }
2237
2239}
2240
2241/// For the input attribute string, return the customized refinement step count
2242/// for this operation on the specified data type. If the step count does not
2243/// exist, return the ReciprocalEstimate enum value for unspecified.
2244static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2245 if (Override.empty())
2247
2248 SmallVector<StringRef, 4> OverrideVector;
2249 Override.split(OverrideVector, ',');
2250 unsigned NumArgs = OverrideVector.size();
2251
2252 // Check if "all", "default", or "none" was specified.
2253 if (NumArgs == 1) {
2254 // Look for an optional setting of the number of refinement steps needed
2255 // for this type of reciprocal operation.
2256 size_t RefPos;
2257 uint8_t RefSteps;
2258 if (!parseRefinementStep(Override, RefPos, RefSteps))
2260
2261 // Split the string for further processing.
2262 Override = Override.substr(0, RefPos);
2263 assert(Override != "none" &&
2264 "Disabled reciprocals, but specifed refinement steps?");
2265
2266 // If this is a general override, return the specified number of steps.
2267 if (Override == "all" || Override == "default")
2268 return RefSteps;
2269 }
2270
2271 // The attribute string may omit the size suffix ('f'/'d').
2272 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2273 std::string VTNameNoSize = VTName;
2274 VTNameNoSize.pop_back();
2275
2276 for (StringRef RecipType : OverrideVector) {
2277 size_t RefPos;
2278 uint8_t RefSteps;
2279 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2280 continue;
2281
2282 RecipType = RecipType.substr(0, RefPos);
2283 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2284 return RefSteps;
2285 }
2286
2288}
2289
2291 MachineFunction &MF) const {
2292 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2293}
2294
2296 MachineFunction &MF) const {
2297 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2298}
2299
2301 MachineFunction &MF) const {
2302 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2303}
2304
2306 MachineFunction &MF) const {
2307 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2308}
2309
2311 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2312 const MachineMemOperand &MMO) const {
2313 // Single-element vectors are scalarized, so we should generally avoid having
2314 // any memory operations on such types, as they would get scalarized too.
2315 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2316 BitcastVT.getVectorNumElements() == 1)
2317 return false;
2318
2319 // Don't do if we could do an indexed load on the original type, but not on
2320 // the new one.
2321 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2322 return true;
2323
2324 MVT LoadMVT = LoadVT.getSimpleVT();
2325
2326 // Don't bother doing this if it's just going to be promoted again later, as
2327 // doing so might interfere with other combines.
2328 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
2329 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
2330 return false;
2331
2332 unsigned Fast = 0;
2333 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
2334 MMO, &Fast) &&
2335 Fast;
2336}
2337
2340}
2341
2343 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2344 const TargetLibraryInfo *LibInfo) const {
2346 if (LI.isVolatile())
2348
2349 if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2351
2352 if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2354
2356 LI.getAlign(), DL, &LI, AC,
2357 /*DT=*/nullptr, LibInfo))
2359
2360 Flags |= getTargetMMOFlags(LI);
2361 return Flags;
2362}
2363
2366 const DataLayout &DL) const {
2368
2369 if (SI.isVolatile())
2371
2372 if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2374
2375 // FIXME: Not preserving dereferenceable
2376 Flags |= getTargetMMOFlags(SI);
2377 return Flags;
2378}
2379
2382 const DataLayout &DL) const {
2384
2385 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2386 if (RMW->isVolatile())
2388 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2389 if (CmpX->isVolatile())
2391 } else
2392 llvm_unreachable("not an atomic instruction");
2393
2394 // FIXME: Not preserving dereferenceable
2395 Flags |= getTargetMMOFlags(AI);
2396 return Flags;
2397}
2398
2400 Instruction *Inst,
2401 AtomicOrdering Ord) const {
2402 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2403 return Builder.CreateFence(Ord);
2404 else
2405 return nullptr;
2406}
2407
2409 Instruction *Inst,
2410 AtomicOrdering Ord) const {
2411 if (isAcquireOrStronger(Ord))
2412 return Builder.CreateFence(Ord);
2413 else
2414 return nullptr;
2415}
2416
2417//===----------------------------------------------------------------------===//
2418// GlobalISel Hooks
2419//===----------------------------------------------------------------------===//
2420
2422 const TargetTransformInfo *TTI) const {
2423 auto &MF = *MI.getMF();
2424 auto &MRI = MF.getRegInfo();
2425 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2426 // this helper function computes the maximum number of uses we should consider
2427 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2428 // break even in terms of code size when the original MI has 2 users vs
2429 // choosing to potentially spill. Any more than 2 users we we have a net code
2430 // size increase. This doesn't take into account register pressure though.
2431 auto maxUses = [](unsigned RematCost) {
2432 // A cost of 1 means remats are basically free.
2433 if (RematCost == 1)
2434 return std::numeric_limits<unsigned>::max();
2435 if (RematCost == 2)
2436 return 2U;
2437
2438 // Remat is too expensive, only sink if there's one user.
2439 if (RematCost > 2)
2440 return 1U;
2441 llvm_unreachable("Unexpected remat cost");
2442 };
2443
2444 switch (MI.getOpcode()) {
2445 default:
2446 return false;
2447 // Constants-like instructions should be close to their users.
2448 // We don't want long live-ranges for them.
2449 case TargetOpcode::G_CONSTANT:
2450 case TargetOpcode::G_FCONSTANT:
2451 case TargetOpcode::G_FRAME_INDEX:
2452 case TargetOpcode::G_INTTOPTR:
2453 return true;
2454 case TargetOpcode::G_GLOBAL_VALUE: {
2455 unsigned RematCost = TTI->getGISelRematGlobalCost();
2456 Register Reg = MI.getOperand(0).getReg();
2457 unsigned MaxUses = maxUses(RematCost);
2458 if (MaxUses == UINT_MAX)
2459 return true; // Remats are "free" so always localize.
2460 return MRI.hasAtMostUserInstrs(Reg, MaxUses);
2461 }
2462 }
2463}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
Rewrite undef for PHI
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
std::string Name
IRTranslator LLVM IR MI
#define LCALL5(A)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
LLVMContext & Context
const char LLVMTargetMachineRef TM
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallVector class.
This file contains some functions that are useful when dealing with strings.
static bool darwinHasSinCos(const Triple &TT)
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
#define OP_TO_LIBCALL(Name, Enum)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
This file describes how to lower LLVM code to machine code.
This pass exposes codegen information to IR-level passes.
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:539
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:748
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
Definition: Attributes.h:798
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:205
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:707
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:140
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
Definition: DataLayout.cpp:750
static constexpr ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:299
static constexpr ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:296
constexpr bool isScalar() const
Exactly one element.
Definition: TypeSize.h:307
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:168
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:68
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:52
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1833
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:174
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=std::nullopt, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2395
bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:340
@ MAX_INT_BITS
Maximum number of bits that can be specified.
Definition: DerivedTypes.h:52
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:184
Value * getPointerOperand()
Definition: Instructions.h:280
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:230
Align getAlign() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:236
Machine Value Type.
SimpleValueType SimpleTy
uint64_t getScalarSizeInBits() const
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static auto all_valuetypes()
SimpleValueType Iteration.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
ElementCount getVectorElementCount() const
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:547
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
A description of a memory reference used in the backend.
unsigned getAddrSpace() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Class to represent pointers.
Definition: DerivedTypes.h:646
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Definition: DerivedTypes.h:662
Analysis providing profile information.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:472
LLVMContext * getContext() const
Definition: SelectionDAG.h:485
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:317
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:567
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
static constexpr size_t npos
Definition: StringRef.h:52
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Multiway switch.
Provides information about what library functions are available for the current target.
LegalizeTypeAction getTypeAction(MVT VT) const
void setTypeAction(MVT VT, LegalizeTypeAction Action)
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
void initActions()
Initialize all of the actions to default values.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
const TargetMachine & getTargetMachine() const
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual bool useFPRegsForHalfType() const
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
virtual bool softPromoteHalfType() const
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual bool isJumpTableRelative() const
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to.
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
bool isPositionIndependent() const
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
TargetOptions Options
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
unsigned getGISelRematGlobalCost() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isWindowsGNUEnvironment() const
Definition: Triple.h:641
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:753
@ aarch64_32
Definition: Triple.h:53
bool isOSFreeBSD() const
Definition: Triple.h:568
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:542
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
constexpr LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:247
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:239
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ ARM_AAPCS_VFP
Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:114
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:750
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:236
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:723
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
@ SET_FPENV
Sets the current floating-point environment.
Definition: ISDOpcodes.h:998
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1339
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1370
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:497
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1269
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:367
@ ConstantFP
Definition: ISDOpcodes.h:77
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1271
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1272
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:269
@ RESET_FPENV
Set floating-point environment to default state.
Definition: ISDOpcodes.h:1002
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:487
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:979
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:239
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:1031
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:373
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1021
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:783
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1254
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:790
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:543
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1355
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:390
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
Definition: ISDOpcodes.h:1359
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:688
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
Definition: ISDOpcodes.h:1025
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:820
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1369
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1267
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:903
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1268
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
Definition: ISDOpcodes.h:939
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:380
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1400
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:774
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:662
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
Definition: ISDOpcodes.h:1188
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1352
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:722
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1221
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1356
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:758
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:930
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:327
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1270
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:507
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:349
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:727
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1371
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:627
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:323
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1364
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1016
@ GET_FPENV
Gets the current floating-point environment.
Definition: ISDOpcodes.h:993
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:705
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1266
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:600
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1265
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
Definition: ISDOpcodes.h:978
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:535
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:780
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1211
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:856
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1248
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1273
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:971
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1215
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:359
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:331
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:809
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:798
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:674
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:386
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:888
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:303
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1372
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1263
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:984
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1264
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:836
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1182
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:680
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1208
@ GET_FPENV_MEM
Gets the current floating-point environment.
Definition: ISDOpcodes.h:1007
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:657
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1353
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:279
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:524
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:612
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1262
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
Definition: ISDOpcodes.h:944
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:869
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:831
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:907
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:855
@ VECREDUCE_FMINIMUM
Definition: ISDOpcodes.h:1360
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:786
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1340
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:493
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:340
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1320
@ SET_FPENV_MEM
Sets the current floating point environment.
Definition: ISDOpcodes.h:1012
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:313
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1523
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1474
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Libcall getLDEXP(EVT RetVT)
getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFREXP(EVT RetVT)
getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)
Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:326
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:417
auto enum_seq(EnumT Begin, EnumT End)
Iterate over an enum type from Begin up to - but not including - End.
Definition: Sequence.h:337
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:199
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum
Definition: Sequence.h:108
T bit_ceil(T Value)
Returns the smallest integral power of two no smaller than Value if Value is nonzero.
Definition: bit.h:342
bool isReleaseOrStronger(AtomicOrdering AO)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1745
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
@ Xor
Bitwise or logical XOR of integers.
@ FMul
Product of floats.
@ And
Bitwise or logical AND of integers.
@ Add
Sum of integers.
@ FAdd
Sum of floats.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:79
bool isAcquireOrStronger(AtomicOrdering AO)
InstructionCost Cost
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:462
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:136
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:340
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:358
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:455
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:306
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
bool isFixedLengthVector() const
Definition: ValueTypes.h:177
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:404
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:167
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:313
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:202
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:318
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:326
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
Definition: ValueTypes.h:131
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:438
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:151
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...