69 "jump-is-expensive",
cl::init(
false),
70 cl::desc(
"Do not create extra branches to split comparison logic."),
75 cl::desc(
"Set minimum number of entries to use a jump table."));
79 cl::desc(
"Set maximum size of jump tables."));
84 cl::desc(
"Minimum density for building a jump table in "
85 "a normal function"));
90 cl::desc(
"Minimum density for building a jump table in "
91 "an optsize function"));
98 cl::desc(
"Don't mutate strict-float node to a legalize node"),
102 assert(TT.isOSDarwin() &&
"should be called with darwin triple");
108 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
111 return !TT.isOSVersionLT(7, 0);
116void TargetLoweringBase::InitLibcalls(
const Triple &TT) {
117#define HANDLE_LIBCALL(code, name) \
118 setLibcallName(RTLIB::code, name);
119#include "llvm/IR/RuntimeLibcalls.def"
122 for (
int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
199 if (
TT.isOSDarwin()) {
207 switch (
TT.getArch()) {
210 if (
TT.isMacOSX() && !
TT.isMacOSXVersionLT(10, 6))
224 if (
TT.isWatchABI()) {
232 switch (
TT.getOS()) {
234 if (
TT.isMacOSXVersionLT(10, 9)) {
246 if (!
TT.isWatchOS() &&
247 (
TT.isOSVersionLT(7, 0) || (
TT.isOSVersionLT(9, 0) &&
TT.isX86()))) {
264 if (
TT.isGNUEnvironment() ||
TT.isOSFuchsia() ||
265 (
TT.isAndroid() && !
TT.isAndroidVersionLT(9))) {
278 if (
TT.isOSOpenBSD()) {
282 if (
TT.isOSWindows() && !
TT.isOSCygMing()) {
304 VT == MVT::f32 ? Call_F32 :
305 VT == MVT::f64 ? Call_F64 :
306 VT == MVT::f80 ? Call_F80 :
307 VT == MVT::f128 ? Call_F128 :
308 VT == MVT::ppcf128 ? Call_PPCF128 :
309 RTLIB::UNKNOWN_LIBCALL;
315 if (OpVT == MVT::f16) {
316 if (RetVT == MVT::f32)
317 return FPEXT_F16_F32;
318 if (RetVT == MVT::f64)
319 return FPEXT_F16_F64;
320 if (RetVT == MVT::f80)
321 return FPEXT_F16_F80;
322 if (RetVT == MVT::f128)
323 return FPEXT_F16_F128;
324 }
else if (OpVT == MVT::f32) {
325 if (RetVT == MVT::f64)
326 return FPEXT_F32_F64;
327 if (RetVT == MVT::f128)
328 return FPEXT_F32_F128;
329 if (RetVT == MVT::ppcf128)
330 return FPEXT_F32_PPCF128;
331 }
else if (OpVT == MVT::f64) {
332 if (RetVT == MVT::f128)
333 return FPEXT_F64_F128;
334 else if (RetVT == MVT::ppcf128)
335 return FPEXT_F64_PPCF128;
336 }
else if (OpVT == MVT::f80) {
337 if (RetVT == MVT::f128)
338 return FPEXT_F80_F128;
339 }
else if (OpVT == MVT::bf16) {
340 if (RetVT == MVT::f32)
341 return FPEXT_BF16_F32;
344 return UNKNOWN_LIBCALL;
350 if (RetVT == MVT::f16) {
351 if (OpVT == MVT::f32)
352 return FPROUND_F32_F16;
353 if (OpVT == MVT::f64)
354 return FPROUND_F64_F16;
355 if (OpVT == MVT::f80)
356 return FPROUND_F80_F16;
357 if (OpVT == MVT::f128)
358 return FPROUND_F128_F16;
359 if (OpVT == MVT::ppcf128)
360 return FPROUND_PPCF128_F16;
361 }
else if (RetVT == MVT::bf16) {
362 if (OpVT == MVT::f32)
363 return FPROUND_F32_BF16;
364 if (OpVT == MVT::f64)
365 return FPROUND_F64_BF16;
366 }
else if (RetVT == MVT::f32) {
367 if (OpVT == MVT::f64)
368 return FPROUND_F64_F32;
369 if (OpVT == MVT::f80)
370 return FPROUND_F80_F32;
371 if (OpVT == MVT::f128)
372 return FPROUND_F128_F32;
373 if (OpVT == MVT::ppcf128)
374 return FPROUND_PPCF128_F32;
375 }
else if (RetVT == MVT::f64) {
376 if (OpVT == MVT::f80)
377 return FPROUND_F80_F64;
378 if (OpVT == MVT::f128)
379 return FPROUND_F128_F64;
380 if (OpVT == MVT::ppcf128)
381 return FPROUND_PPCF128_F64;
382 }
else if (RetVT == MVT::f80) {
383 if (OpVT == MVT::f128)
384 return FPROUND_F128_F80;
387 return UNKNOWN_LIBCALL;
393 if (OpVT == MVT::f16) {
394 if (RetVT == MVT::i32)
395 return FPTOSINT_F16_I32;
396 if (RetVT == MVT::i64)
397 return FPTOSINT_F16_I64;
398 if (RetVT == MVT::i128)
399 return FPTOSINT_F16_I128;
400 }
else if (OpVT == MVT::f32) {
401 if (RetVT == MVT::i32)
402 return FPTOSINT_F32_I32;
403 if (RetVT == MVT::i64)
404 return FPTOSINT_F32_I64;
405 if (RetVT == MVT::i128)
406 return FPTOSINT_F32_I128;
407 }
else if (OpVT == MVT::f64) {
408 if (RetVT == MVT::i32)
409 return FPTOSINT_F64_I32;
410 if (RetVT == MVT::i64)
411 return FPTOSINT_F64_I64;
412 if (RetVT == MVT::i128)
413 return FPTOSINT_F64_I128;
414 }
else if (OpVT == MVT::f80) {
415 if (RetVT == MVT::i32)
416 return FPTOSINT_F80_I32;
417 if (RetVT == MVT::i64)
418 return FPTOSINT_F80_I64;
419 if (RetVT == MVT::i128)
420 return FPTOSINT_F80_I128;
421 }
else if (OpVT == MVT::f128) {
422 if (RetVT == MVT::i32)
423 return FPTOSINT_F128_I32;
424 if (RetVT == MVT::i64)
425 return FPTOSINT_F128_I64;
426 if (RetVT == MVT::i128)
427 return FPTOSINT_F128_I128;
428 }
else if (OpVT == MVT::ppcf128) {
429 if (RetVT == MVT::i32)
430 return FPTOSINT_PPCF128_I32;
431 if (RetVT == MVT::i64)
432 return FPTOSINT_PPCF128_I64;
433 if (RetVT == MVT::i128)
434 return FPTOSINT_PPCF128_I128;
436 return UNKNOWN_LIBCALL;
442 if (OpVT == MVT::f16) {
443 if (RetVT == MVT::i32)
444 return FPTOUINT_F16_I32;
445 if (RetVT == MVT::i64)
446 return FPTOUINT_F16_I64;
447 if (RetVT == MVT::i128)
448 return FPTOUINT_F16_I128;
449 }
else if (OpVT == MVT::f32) {
450 if (RetVT == MVT::i32)
451 return FPTOUINT_F32_I32;
452 if (RetVT == MVT::i64)
453 return FPTOUINT_F32_I64;
454 if (RetVT == MVT::i128)
455 return FPTOUINT_F32_I128;
456 }
else if (OpVT == MVT::f64) {
457 if (RetVT == MVT::i32)
458 return FPTOUINT_F64_I32;
459 if (RetVT == MVT::i64)
460 return FPTOUINT_F64_I64;
461 if (RetVT == MVT::i128)
462 return FPTOUINT_F64_I128;
463 }
else if (OpVT == MVT::f80) {
464 if (RetVT == MVT::i32)
465 return FPTOUINT_F80_I32;
466 if (RetVT == MVT::i64)
467 return FPTOUINT_F80_I64;
468 if (RetVT == MVT::i128)
469 return FPTOUINT_F80_I128;
470 }
else if (OpVT == MVT::f128) {
471 if (RetVT == MVT::i32)
472 return FPTOUINT_F128_I32;
473 if (RetVT == MVT::i64)
474 return FPTOUINT_F128_I64;
475 if (RetVT == MVT::i128)
476 return FPTOUINT_F128_I128;
477 }
else if (OpVT == MVT::ppcf128) {
478 if (RetVT == MVT::i32)
479 return FPTOUINT_PPCF128_I32;
480 if (RetVT == MVT::i64)
481 return FPTOUINT_PPCF128_I64;
482 if (RetVT == MVT::i128)
483 return FPTOUINT_PPCF128_I128;
485 return UNKNOWN_LIBCALL;
491 if (OpVT == MVT::i32) {
492 if (RetVT == MVT::f16)
493 return SINTTOFP_I32_F16;
494 if (RetVT == MVT::f32)
495 return SINTTOFP_I32_F32;
496 if (RetVT == MVT::f64)
497 return SINTTOFP_I32_F64;
498 if (RetVT == MVT::f80)
499 return SINTTOFP_I32_F80;
500 if (RetVT == MVT::f128)
501 return SINTTOFP_I32_F128;
502 if (RetVT == MVT::ppcf128)
503 return SINTTOFP_I32_PPCF128;
504 }
else if (OpVT == MVT::i64) {
505 if (RetVT == MVT::f16)
506 return SINTTOFP_I64_F16;
507 if (RetVT == MVT::f32)
508 return SINTTOFP_I64_F32;
509 if (RetVT == MVT::f64)
510 return SINTTOFP_I64_F64;
511 if (RetVT == MVT::f80)
512 return SINTTOFP_I64_F80;
513 if (RetVT == MVT::f128)
514 return SINTTOFP_I64_F128;
515 if (RetVT == MVT::ppcf128)
516 return SINTTOFP_I64_PPCF128;
517 }
else if (OpVT == MVT::i128) {
518 if (RetVT == MVT::f16)
519 return SINTTOFP_I128_F16;
520 if (RetVT == MVT::f32)
521 return SINTTOFP_I128_F32;
522 if (RetVT == MVT::f64)
523 return SINTTOFP_I128_F64;
524 if (RetVT == MVT::f80)
525 return SINTTOFP_I128_F80;
526 if (RetVT == MVT::f128)
527 return SINTTOFP_I128_F128;
528 if (RetVT == MVT::ppcf128)
529 return SINTTOFP_I128_PPCF128;
531 return UNKNOWN_LIBCALL;
537 if (OpVT == MVT::i32) {
538 if (RetVT == MVT::f16)
539 return UINTTOFP_I32_F16;
540 if (RetVT == MVT::f32)
541 return UINTTOFP_I32_F32;
542 if (RetVT == MVT::f64)
543 return UINTTOFP_I32_F64;
544 if (RetVT == MVT::f80)
545 return UINTTOFP_I32_F80;
546 if (RetVT == MVT::f128)
547 return UINTTOFP_I32_F128;
548 if (RetVT == MVT::ppcf128)
549 return UINTTOFP_I32_PPCF128;
550 }
else if (OpVT == MVT::i64) {
551 if (RetVT == MVT::f16)
552 return UINTTOFP_I64_F16;
553 if (RetVT == MVT::f32)
554 return UINTTOFP_I64_F32;
555 if (RetVT == MVT::f64)
556 return UINTTOFP_I64_F64;
557 if (RetVT == MVT::f80)
558 return UINTTOFP_I64_F80;
559 if (RetVT == MVT::f128)
560 return UINTTOFP_I64_F128;
561 if (RetVT == MVT::ppcf128)
562 return UINTTOFP_I64_PPCF128;
563 }
else if (OpVT == MVT::i128) {
564 if (RetVT == MVT::f16)
565 return UINTTOFP_I128_F16;
566 if (RetVT == MVT::f32)
567 return UINTTOFP_I128_F32;
568 if (RetVT == MVT::f64)
569 return UINTTOFP_I128_F64;
570 if (RetVT == MVT::f80)
571 return UINTTOFP_I128_F80;
572 if (RetVT == MVT::f128)
573 return UINTTOFP_I128_F128;
574 if (RetVT == MVT::ppcf128)
575 return UINTTOFP_I128_PPCF128;
577 return UNKNOWN_LIBCALL;
581 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
586 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,
591 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,
598 unsigned ModeN, ModelN;
616 return RTLIB::UNKNOWN_LIBCALL;
634 return UNKNOWN_LIBCALL;
637 return LC[ModeN][ModelN];
643 return UNKNOWN_LIBCALL;
646#define LCALLS(A, B) \
647 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
649 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
676 return UNKNOWN_LIBCALL;
683#define OP_TO_LIBCALL(Name, Enum) \
685 switch (VT.SimpleTy) { \
687 return UNKNOWN_LIBCALL; \
717 return UNKNOWN_LIBCALL;
721 switch (ElementSize) {
723 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
725 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
727 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
729 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
731 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
733 return UNKNOWN_LIBCALL;
738 switch (ElementSize) {
740 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
742 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
744 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
746 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
748 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
750 return UNKNOWN_LIBCALL;
755 switch (ElementSize) {
757 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
759 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
761 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
763 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
765 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
767 return UNKNOWN_LIBCALL;
814 HasMultipleConditionRegisters =
false;
815 HasExtractBitsInsn =
false;
819 StackPointerRegisterToSaveRestore = 0;
826 MaxBytesForAlignment = 0;
827 MaxAtomicSizeInBitsSupported = 0;
831 MaxDivRemBitWidthSupported = 128;
835 MinCmpXchgSizeInBits = 0;
836 SupportsUnalignedAtomics =
false;
838 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames),
nullptr);
846 memset(OpActions, 0,
sizeof(OpActions));
847 memset(LoadExtActions, 0,
sizeof(LoadExtActions));
848 memset(TruncStoreActions, 0,
sizeof(TruncStoreActions));
849 memset(IndexedModeActions, 0,
sizeof(IndexedModeActions));
850 memset(CondCodeActions, 0,
sizeof(CondCodeActions));
851 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT),
nullptr);
852 std::fill(std::begin(TargetDAGCombineArray),
853 std::end(TargetDAGCombineArray), 0);
865 for (
MVT VT : {MVT::i2, MVT::i4})
866 OpActions[(
unsigned)VT.SimpleTy][NT] =
Expand;
869 for (
MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
877 for (
MVT VT : {MVT::i2, MVT::i4}) {
971#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
972 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
973#include "llvm/IR/ConstrainedOps.def"
992#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
993 setOperationAction(ISD::SDOPC, VT, Expand);
994#include "llvm/IR/VPIntrinsics.def"
1015 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
1024 {MVT::f32, MVT::f64, MVT::f128},
Expand);
1039 for (
MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1056 bool LegalTypes)
const {
1067 "ShiftVT is still too small!");
1085 unsigned DestAS)
const {
1094 if (EC.isScalable())
1100 unsigned EltWidth =
RetTy->getScalarSizeInBits();
1101 EltWidth = std::min(EltWidth, (
unsigned)CR.
getActiveBits());
1110 JumpIsExpensive = isExpensive;
1126 "Promote may not follow Expand or Promote");
1129 return LegalizeKind(LA,
EVT(SVT).getHalfNumVectorElementsVT(Context));
1142 assert(NVT != VT &&
"Unable to round integer VT");
1191 EVT OldEltVT = EltVT;
1230 if (LargerVector ==
MVT())
1254 unsigned &NumIntermediates,
1261 unsigned NumVectorRegs = 1;
1267 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1273 NumVectorRegs = EC.getKnownMinValue();
1280 while (EC.getKnownMinValue() > 1 &&
1282 EC = EC.divideCoefficientBy(2);
1283 NumVectorRegs <<= 1;
1286 NumIntermediates = NumVectorRegs;
1291 IntermediateVT = NewVT;
1299 RegisterVT = DestVT;
1300 if (
EVT(DestVT).bitsLT(NewVT))
1305 return NumVectorRegs;
1312 for (
const auto *
I =
TRI.legalclasstypes_begin(RC); *
I != MVT::Other; ++
I)
1348 for (
unsigned i = 0; i <
MI->getNumOperands(); ++i) {
1355 unsigned TiedTo = i;
1357 TiedTo =
MI->findTiedOperandIdx(i);
1374 assert(
MI->getOpcode() == TargetOpcode::STATEPOINT &&
"sanity");
1375 MIB.
addImm(StackMaps::IndirectMemRefOp);
1382 MIB.
addImm(StackMaps::DirectMemRefOp);
1387 assert(MIB->
mayLoad() &&
"Folded a stackmap use to a non-load!");
1394 if (
MI->getOpcode() != TargetOpcode::STATEPOINT) {
1403 MI->eraseFromParent();
1413std::pair<const TargetRegisterClass *, uint8_t>
1418 return std::make_pair(RC, 0);
1427 for (
unsigned i : SuperRegRC.
set_bits()) {
1430 if (
TRI->getSpillSize(*SuperRC) <=
TRI->getSpillSize(*BestRC))
1436 return std::make_pair(BestRC, 1);
1445 NumRegistersForVT[i] = 1;
1449 NumRegistersForVT[MVT::isVoid] = 0;
1452 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1453 for (; RegClassForVT[LargestIntReg] ==
nullptr; --LargestIntReg)
1454 assert(LargestIntReg != MVT::i1 &&
"No integer registers defined!");
1458 for (
unsigned ExpandedReg = LargestIntReg + 1;
1459 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1460 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1469 unsigned LegalIntReg = LargestIntReg;
1470 for (
unsigned IntReg = LargestIntReg - 1;
1471 IntReg >= (
unsigned)MVT::i1; --IntReg) {
1474 LegalIntReg = IntReg;
1476 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1485 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1486 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1487 TransformToType[MVT::ppcf128] = MVT::f64;
1490 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1491 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1492 TransformToType[MVT::ppcf128] = MVT::i128;
1500 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1501 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1502 TransformToType[MVT::f128] = MVT::i128;
1509 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1510 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1511 TransformToType[MVT::f80] = MVT::i32;
1518 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1519 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1520 TransformToType[MVT::f64] = MVT::i64;
1527 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1528 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1529 TransformToType[MVT::f32] = MVT::i32;
1541 if (!UseFPRegsForHalfType) {
1542 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1543 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1545 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1546 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1548 TransformToType[MVT::f16] = MVT::f32;
1549 if (SoftPromoteHalfType) {
1560 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1561 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1562 TransformToType[MVT::bf16] = MVT::f32;
1567 for (
unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1568 i <= (
unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1575 bool IsLegalWiderType =
false;
1578 switch (PreferredAction) {
1581 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1582 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1585 for (
unsigned nVT = i + 1;
1592 TransformToType[i] = SVT;
1593 RegisterTypeForVT[i] = SVT;
1594 NumRegistersForVT[i] = 1;
1596 IsLegalWiderType =
true;
1600 if (IsLegalWiderType)
1608 for (
unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1613 EC.getKnownMinValue() &&
1615 TransformToType[i] = SVT;
1616 RegisterTypeForVT[i] = SVT;
1617 NumRegistersForVT[i] = 1;
1619 IsLegalWiderType =
true;
1623 if (IsLegalWiderType)
1629 TransformToType[i] = NVT;
1631 RegisterTypeForVT[i] = NVT;
1632 NumRegistersForVT[i] = 1;
1642 unsigned NumIntermediates;
1644 NumIntermediates, RegisterVT,
this);
1645 NumRegistersForVT[i] = NumRegisters;
1646 assert(NumRegistersForVT[i] == NumRegisters &&
1647 "NumRegistersForVT size cannot represent NumRegisters!");
1648 RegisterTypeForVT[i] = RegisterVT;
1653 TransformToType[i] = MVT::Other;
1658 else if (EC.getKnownMinValue() > 1)
1665 TransformToType[i] = NVT;
1684 RepRegClassForVT[i] = RRC;
1685 RepRegClassCostForVT[i] =
Cost;
1708 EVT VT,
EVT &IntermediateVT,
1709 unsigned &NumIntermediates,
1710 MVT &RegisterVT)
const {
1723 IntermediateVT = RegisterEVT;
1725 NumIntermediates = 1;
1733 unsigned NumVectorRegs = 1;
1748 "Don't know how to legalize this scalable vector type");
1754 IntermediateVT = PartVT;
1756 return NumIntermediates;
1771 NumVectorRegs <<= 1;
1774 NumIntermediates = NumVectorRegs;
1779 IntermediateVT = NewVT;
1782 RegisterVT = DestVT;
1784 if (
EVT(DestVT).bitsLT(NewVT)) {
1794 return NumVectorRegs;
1807 const bool OptForSize =
1808 SI->getParent()->getParent()->hasOptSize() ||
1815 return (OptForSize ||
Range <= MaxJumpTableSize) &&
1816 (NumCases * 100 >=
Range * MinDensity);
1820 EVT ConditionVT)
const {
1834 unsigned NumValues = ValueVTs.
size();
1835 if (NumValues == 0)
return;
1837 for (
unsigned j = 0, f = NumValues; j != f; ++j) {
1838 EVT VT = ValueVTs[j];
1865 for (
unsigned i = 0; i < NumParts; ++i) {
1867 if (NumParts > 1 && i == 0)
1869 else if (i == NumParts - 1 && i != 0)
1883 return DL.getABITypeAlign(Ty).value();
1895 if (VT.
isZeroSized() || Alignment >=
DL.getABITypeAlign(Ty)) {
1897 if (
Fast !=
nullptr)
1915 unsigned AddrSpace,
Align Alignment,
1917 unsigned *
Fast)
const {
1925 unsigned *
Fast)
const {
1933 unsigned *
Fast)
const {
1944 enum InstructionOpcodes {
1945#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1946#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1947#include "llvm/IR/Instruction.def"
1949 switch (
static_cast<InstructionOpcodes
>(Opcode)) {
1952 case Switch:
return 0;
1953 case IndirectBr:
return 0;
1954 case Invoke:
return 0;
1955 case CallBr:
return 0;
1956 case Resume:
return 0;
1957 case Unreachable:
return 0;
1958 case CleanupRet:
return 0;
1959 case CatchRet:
return 0;
1960 case CatchPad:
return 0;
1961 case CatchSwitch:
return 0;
1962 case CleanupPad:
return 0;
1982 case Alloca:
return 0;
1985 case GetElementPtr:
return 0;
1986 case Fence:
return 0;
1987 case AtomicCmpXchg:
return 0;
1988 case AtomicRMW:
return 0;
2005 case Call:
return 0;
2007 case UserOp1:
return 0;
2008 case UserOp2:
return 0;
2009 case VAArg:
return 0;
2015 case LandingPad:
return 0;
2024 bool UseTLS)
const {
2028 const char *UnsafeStackPtrVar =
"__safestack_unsafe_stack_ptr";
2029 auto UnsafeStackPtr =
2030 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
2034 if (!UnsafeStackPtr) {
2035 auto TLSModel = UseTLS ?
2043 UnsafeStackPtrVar,
nullptr, TLSModel);
2046 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2048 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2050 (UseTLS ?
"" :
"not ") +
"be thread-local");
2052 return UnsafeStackPtr;
2065 M->getOrInsertFunction(
"__safestack_pointer_address", PtrTy);
2124 Constant *
C = M.getOrInsertGlobal(
"__guard_local", PtrTy);
2135 if (!M.getNamedValue(
"__stack_chk_guard")) {
2138 nullptr,
"__stack_chk_guard");
2141 if (M.getDirectAccessExternalData() &&
2147 GV->setDSOLocal(
true);
2154 return M.getNamedValue(
"__stack_chk_guard");
2188 return PrefLoopAlignment;
2193 return MaxBytesForAlignment;
2204 return F.getFnAttribute(
"reciprocal-estimates").getValueAsString();
2214 Name += IsSqrt ?
"sqrt" :
"div";
2223 "Unexpected FP type for reciprocal estimate");
2235 const char RefStepToken =
':';
2236 Position = In.find(RefStepToken);
2240 StringRef RefStepString = In.substr(Position + 1);
2243 if (RefStepString.
size() == 1) {
2244 char RefStepChar = RefStepString[0];
2246 Value = RefStepChar -
'0';
2257 if (Override.
empty())
2261 Override.
split(OverrideVector,
',');
2262 unsigned NumArgs = OverrideVector.
size();
2272 Override = Override.
substr(0, RefPos);
2276 if (Override ==
"all")
2280 if (Override ==
"none")
2284 if (Override ==
"default")
2290 std::string VTNameNoSize = VTName;
2291 VTNameNoSize.pop_back();
2292 static const char DisabledPrefix =
'!';
2294 for (
StringRef RecipType : OverrideVector) {
2298 RecipType = RecipType.substr(0, RefPos);
2301 bool IsDisabled = RecipType[0] == DisabledPrefix;
2303 RecipType = RecipType.substr(1);
2305 if (RecipType == VTName || RecipType == VTNameNoSize)
2317 if (Override.
empty())
2321 Override.
split(OverrideVector,
',');
2322 unsigned NumArgs = OverrideVector.
size();
2334 Override = Override.
substr(0, RefPos);
2335 assert(Override !=
"none" &&
2336 "Disabled reciprocals, but specifed refinement steps?");
2339 if (Override ==
"all" || Override ==
"default")
2345 std::string VTNameNoSize = VTName;
2346 VTNameNoSize.pop_back();
2348 for (
StringRef RecipType : OverrideVector) {
2354 RecipType = RecipType.substr(0, RefPos);
2355 if (RecipType == VTName || RecipType == VTNameNoSize)
2424 if (LI.
hasMetadata(LLVMContext::MD_invariant_load))
2441 if (SI.isVolatile())
2444 if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2457 if (
const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2458 if (RMW->isVolatile())
2461 if (CmpX->isVolatile())
2495 auto &MF = *
MI.getMF();
2496 auto &
MRI = MF.getRegInfo();
2503 auto maxUses = [](
unsigned RematCost) {
2506 return std::numeric_limits<unsigned>::max();
2516 switch (
MI.getOpcode()) {
2521 case TargetOpcode::G_CONSTANT:
2522 case TargetOpcode::G_FCONSTANT:
2523 case TargetOpcode::G_FRAME_INDEX:
2524 case TargetOpcode::G_INTTOPTR:
2526 case TargetOpcode::G_GLOBAL_VALUE: {
2529 unsigned MaxUses = maxUses(RematCost);
2530 if (MaxUses == UINT_MAX)
2532 return MRI.hasAtMostUserInstrs(Reg, MaxUses);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
const char LLVMTargetMachineRef TM
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static bool darwinHasSinCos(const Triple &TT)
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
#define OP_TO_LIBCALL(Name, Enum)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
This file describes how to lower LLVM code to machine code.
Class for arbitrary precision integers.
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
an instruction that atomically reads a memory location, combines it with another value,...
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
const Function * getParent() const
Return the enclosing method, or null if none.
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
iterator_range< const_set_bits_iterator > set_bits() const
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
This class represents a range of values.
unsigned getActiveBits() const
Compute the maximal number of active bits needed to represent every value in this range.
ConstantRange umul_sat(const ConstantRange &Other) const
Perform an unsigned saturating multiplication of two constant ranges.
ConstantRange subtract(const APInt &CI) const
Subtract the specified constant from the endpoints of this constant range.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
static constexpr ElementCount getScalable(ScalarTy MinVal)
static constexpr ElementCount getFixed(ScalarTy MinVal)
constexpr bool isScalar() const
Exactly one element.
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Module * getParent()
Get the module that this global value is contained inside of...
@ HiddenVisibility
The GV is hidden.
@ ExternalLinkage
Externally visible function.
Common base class shared among various IRBuilders.
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
BasicBlock * GetInsertBlock() const
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=std::nullopt, const Twine &Name="", MDNode *FPMathTag=nullptr)
bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
@ MAX_INT_BITS
Maximum number of bits that can be specified.
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
Value * getPointerOperand()
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Align getAlign() const
Return the alignment of the access that is being performed.
uint64_t getScalarSizeInBits() const
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static auto all_valuetypes()
SimpleValueType Iteration.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
ElementCount getVectorElementCount() const
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
unsigned getNumOperands() const
Retuns the total number of operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
A description of a memory reference used in the backend.
unsigned getAddrSpace() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
A Module instance is used to store all the information related to an LLVM module.
Class to represent pointers.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Analysis providing profile information.
Wrapper class representing virtual and physical registers.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const DataLayout & getDataLayout() const
LLVMContext * getContext() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
static constexpr size_t npos
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Provides information about what library functions are available for the current target.
LegalizeTypeAction getTypeAction(MVT VT) const
void setTypeAction(MVT VT, LegalizeTypeAction Action)
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
void initActions()
Initialize all of the actions to default values.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
const TargetMachine & getTargetMachine() const
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
@ TypeScalarizeScalableVector
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual bool useFPRegsForHalfType() const
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
virtual bool softPromoteHalfType() const
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const
Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Let target indicate that an extending atomic load of the specified type is legal.
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool EnableExtLdPromotion
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual bool isJumpTableRelative() const
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ UndefinedBooleanContent
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to.
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Primary interface to the complete machine description for the target machine.
bool isPositionIndependent() const
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Triple - Helper class for working with autoconf configuration names.
bool isWindowsGNUEnvironment() const
bool isAndroid() const
Tests whether the target is Android.
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
constexpr LeafTy coefficientNextPowerOf2() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ ARM_AAPCS_VFP
Same as ARM_AAPCS, but uses hard floating point ABI.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ SET_FPENV
Sets the current floating-point environment.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ RESET_FPENV
Set floating-point environment to default state.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ SSUBO
Same for subtraction.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
@ GET_FPENV
Gets the current floating-point environment.
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ GET_FPENV_MEM
Gets the current floating-point environment.
@ SCMP
[US]CMP - 3-way comparison of signed or unsigned integers.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ SET_FPENV_MEM
Sets the current floating point environment.
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
static const int LAST_INDEXED_MODE
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Libcall getLDEXP(EVT RetVT)
getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFREXP(EVT RetVT)
getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)
Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
auto enum_seq(EnumT Begin, EnumT End)
Iterate over an enum type from Begin up to - but not including - End.
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum
T bit_ceil(T Value)
Returns the smallest integral power of two no smaller than Value if Value is nonzero.
bool isReleaseOrStronger(AtomicOrdering AO)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
@ Xor
Bitwise or logical XOR of integers.
@ And
Bitwise or logical AND of integers.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
bool isAcquireOrStronger(AtomicOrdering AO)
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isFixedLengthVector() const
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...