LLVM 19.0.0git
TargetLoweringBase.cpp
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1//===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the TargetLoweringBase class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Twine.h"
19#include "llvm/Analysis/Loads.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/CallingConv.h"
40#include "llvm/IR/DataLayout.h"
42#include "llvm/IR/Function.h"
43#include "llvm/IR/GlobalValue.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/Module.h"
47#include "llvm/IR/Type.h"
57#include <algorithm>
58#include <cassert>
59#include <cstdint>
60#include <cstring>
61#include <iterator>
62#include <string>
63#include <tuple>
64#include <utility>
65
66using namespace llvm;
67
69 "jump-is-expensive", cl::init(false),
70 cl::desc("Do not create extra branches to split comparison logic."),
72
74 ("min-jump-table-entries", cl::init(4), cl::Hidden,
75 cl::desc("Set minimum number of entries to use a jump table."));
76
78 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
79 cl::desc("Set maximum size of jump tables."));
80
81/// Minimum jump table density for normal functions.
83 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
84 cl::desc("Minimum density for building a jump table in "
85 "a normal function"));
86
87/// Minimum jump table density for -Os or -Oz functions.
89 "optsize-jump-table-density", cl::init(40), cl::Hidden,
90 cl::desc("Minimum density for building a jump table in "
91 "an optsize function"));
92
93// FIXME: This option is only to test if the strict fp operation processed
94// correctly by preventing mutating strict fp operation to normal fp operation
95// during development. When the backend supports strict float operation, this
96// option will be meaningless.
97static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation",
98 cl::desc("Don't mutate strict-float node to a legalize node"),
99 cl::init(false), cl::Hidden);
100
101static bool darwinHasSinCos(const Triple &TT) {
102 assert(TT.isOSDarwin() && "should be called with darwin triple");
103 // Don't bother with 32 bit x86.
104 if (TT.getArch() == Triple::x86)
105 return false;
106 // Macos < 10.9 has no sincos_stret.
107 if (TT.isMacOSX())
108 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
109 // iOS < 7.0 has no sincos_stret.
110 if (TT.isiOS())
111 return !TT.isOSVersionLT(7, 0);
112 // Any other darwin such as WatchOS/TvOS is new enough.
113 return true;
114}
115
116void TargetLoweringBase::InitLibcalls(const Triple &TT) {
117#define HANDLE_LIBCALL(code, name) \
118 setLibcallName(RTLIB::code, name);
119#include "llvm/IR/RuntimeLibcalls.def"
120#undef HANDLE_LIBCALL
121 // Initialize calling conventions to their default.
122 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
124
125 // Use the f128 variants of math functions on x86_64
126 if (TT.getArch() == Triple::ArchType::x86_64 && TT.isGNUEnvironment()) {
127 setLibcallName(RTLIB::REM_F128, "fmodf128");
128 setLibcallName(RTLIB::FMA_F128, "fmaf128");
129 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
130 setLibcallName(RTLIB::CBRT_F128, "cbrtf128");
131 setLibcallName(RTLIB::LOG_F128, "logf128");
132 setLibcallName(RTLIB::LOG_FINITE_F128, "__logf128_finite");
133 setLibcallName(RTLIB::LOG2_F128, "log2f128");
134 setLibcallName(RTLIB::LOG2_FINITE_F128, "__log2f128_finite");
135 setLibcallName(RTLIB::LOG10_F128, "log10f128");
136 setLibcallName(RTLIB::LOG10_FINITE_F128, "__log10f128_finite");
137 setLibcallName(RTLIB::EXP_F128, "expf128");
138 setLibcallName(RTLIB::EXP_FINITE_F128, "__expf128_finite");
139 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
140 setLibcallName(RTLIB::EXP2_FINITE_F128, "__exp2f128_finite");
141 setLibcallName(RTLIB::EXP10_F128, "exp10f128");
142 setLibcallName(RTLIB::SIN_F128, "sinf128");
143 setLibcallName(RTLIB::COS_F128, "cosf128");
144 setLibcallName(RTLIB::TAN_F128, "tanf128");
145 setLibcallName(RTLIB::SINCOS_F128, "sincosf128");
146 setLibcallName(RTLIB::POW_F128, "powf128");
147 setLibcallName(RTLIB::POW_FINITE_F128, "__powf128_finite");
148 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
149 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
150 setLibcallName(RTLIB::RINT_F128, "rintf128");
151 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
152 setLibcallName(RTLIB::ROUND_F128, "roundf128");
153 setLibcallName(RTLIB::ROUNDEVEN_F128, "roundevenf128");
154 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
155 setLibcallName(RTLIB::COPYSIGN_F128, "copysignf128");
156 setLibcallName(RTLIB::FMIN_F128, "fminf128");
157 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
158 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
159 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
160 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
161 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
162 setLibcallName(RTLIB::LDEXP_F128, "ldexpf128");
163 setLibcallName(RTLIB::FREXP_F128, "frexpf128");
164 }
165
166 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf".
167 if (TT.isPPC()) {
168 setLibcallName(RTLIB::ADD_F128, "__addkf3");
169 setLibcallName(RTLIB::SUB_F128, "__subkf3");
170 setLibcallName(RTLIB::MUL_F128, "__mulkf3");
171 setLibcallName(RTLIB::DIV_F128, "__divkf3");
172 setLibcallName(RTLIB::POWI_F128, "__powikf2");
173 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2");
174 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2");
175 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2");
176 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2");
177 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi");
178 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi");
179 setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti");
180 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi");
181 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi");
182 setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti");
183 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf");
184 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf");
185 setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf");
186 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf");
187 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf");
188 setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf");
189 setLibcallName(RTLIB::OEQ_F128, "__eqkf2");
190 setLibcallName(RTLIB::UNE_F128, "__nekf2");
191 setLibcallName(RTLIB::OGE_F128, "__gekf2");
192 setLibcallName(RTLIB::OLT_F128, "__ltkf2");
193 setLibcallName(RTLIB::OLE_F128, "__lekf2");
194 setLibcallName(RTLIB::OGT_F128, "__gtkf2");
195 setLibcallName(RTLIB::UO_F128, "__unordkf2");
196 }
197
198 // A few names are different on particular architectures or environments.
199 if (TT.isOSDarwin()) {
200 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
201 // of the gnueabi-style __gnu_*_ieee.
202 // FIXME: What about other targets?
203 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
204 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
205
206 // Some darwins have an optimized __bzero/bzero function.
207 switch (TT.getArch()) {
208 case Triple::x86:
209 case Triple::x86_64:
210 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
211 setLibcallName(RTLIB::BZERO, "__bzero");
212 break;
213 case Triple::aarch64:
215 setLibcallName(RTLIB::BZERO, "bzero");
216 break;
217 default:
218 break;
219 }
220
221 if (darwinHasSinCos(TT)) {
222 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
223 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
224 if (TT.isWatchABI()) {
225 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
227 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
229 }
230 }
231
232 switch (TT.getOS()) {
233 case Triple::MacOSX:
234 if (TT.isMacOSXVersionLT(10, 9)) {
235 setLibcallName(RTLIB::EXP10_F32, nullptr);
236 setLibcallName(RTLIB::EXP10_F64, nullptr);
237 } else {
238 setLibcallName(RTLIB::EXP10_F32, "__exp10f");
239 setLibcallName(RTLIB::EXP10_F64, "__exp10");
240 }
241 break;
242 case Triple::IOS:
243 case Triple::TvOS:
244 case Triple::WatchOS:
245 case Triple::XROS:
246 if (!TT.isWatchOS() &&
247 (TT.isOSVersionLT(7, 0) || (TT.isOSVersionLT(9, 0) && TT.isX86()))) {
248 setLibcallName(RTLIB::EXP10_F32, nullptr);
249 setLibcallName(RTLIB::EXP10_F64, nullptr);
250 } else {
251 setLibcallName(RTLIB::EXP10_F32, "__exp10f");
252 setLibcallName(RTLIB::EXP10_F64, "__exp10");
253 }
254
255 break;
256 default:
257 break;
258 }
259 } else {
260 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
261 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
262 }
263
264 if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
265 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
266 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
267 setLibcallName(RTLIB::SINCOS_F64, "sincos");
268 setLibcallName(RTLIB::SINCOS_F80, "sincosl");
269 setLibcallName(RTLIB::SINCOS_F128, "sincosl");
270 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
271 }
272
273 if (TT.isPS()) {
274 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
275 setLibcallName(RTLIB::SINCOS_F64, "sincos");
276 }
277
278 if (TT.isOSOpenBSD()) {
279 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
280 }
281
282 if (TT.isOSWindows() && !TT.isOSCygMing()) {
283 setLibcallName(RTLIB::LDEXP_F32, nullptr);
284 setLibcallName(RTLIB::LDEXP_F80, nullptr);
285 setLibcallName(RTLIB::LDEXP_F128, nullptr);
286 setLibcallName(RTLIB::LDEXP_PPCF128, nullptr);
287
288 setLibcallName(RTLIB::FREXP_F32, nullptr);
289 setLibcallName(RTLIB::FREXP_F80, nullptr);
290 setLibcallName(RTLIB::FREXP_F128, nullptr);
291 setLibcallName(RTLIB::FREXP_PPCF128, nullptr);
292 }
293}
294
295/// GetFPLibCall - Helper to return the right libcall for the given floating
296/// point type, or UNKNOWN_LIBCALL if there is none.
298 RTLIB::Libcall Call_F32,
299 RTLIB::Libcall Call_F64,
300 RTLIB::Libcall Call_F80,
301 RTLIB::Libcall Call_F128,
302 RTLIB::Libcall Call_PPCF128) {
303 return
304 VT == MVT::f32 ? Call_F32 :
305 VT == MVT::f64 ? Call_F64 :
306 VT == MVT::f80 ? Call_F80 :
307 VT == MVT::f128 ? Call_F128 :
308 VT == MVT::ppcf128 ? Call_PPCF128 :
309 RTLIB::UNKNOWN_LIBCALL;
310}
311
312/// getFPEXT - Return the FPEXT_*_* value for the given types, or
313/// UNKNOWN_LIBCALL if there is none.
315 if (OpVT == MVT::f16) {
316 if (RetVT == MVT::f32)
317 return FPEXT_F16_F32;
318 if (RetVT == MVT::f64)
319 return FPEXT_F16_F64;
320 if (RetVT == MVT::f80)
321 return FPEXT_F16_F80;
322 if (RetVT == MVT::f128)
323 return FPEXT_F16_F128;
324 } else if (OpVT == MVT::f32) {
325 if (RetVT == MVT::f64)
326 return FPEXT_F32_F64;
327 if (RetVT == MVT::f128)
328 return FPEXT_F32_F128;
329 if (RetVT == MVT::ppcf128)
330 return FPEXT_F32_PPCF128;
331 } else if (OpVT == MVT::f64) {
332 if (RetVT == MVT::f128)
333 return FPEXT_F64_F128;
334 else if (RetVT == MVT::ppcf128)
335 return FPEXT_F64_PPCF128;
336 } else if (OpVT == MVT::f80) {
337 if (RetVT == MVT::f128)
338 return FPEXT_F80_F128;
339 } else if (OpVT == MVT::bf16) {
340 if (RetVT == MVT::f32)
341 return FPEXT_BF16_F32;
342 }
343
344 return UNKNOWN_LIBCALL;
345}
346
347/// getFPROUND - Return the FPROUND_*_* value for the given types, or
348/// UNKNOWN_LIBCALL if there is none.
350 if (RetVT == MVT::f16) {
351 if (OpVT == MVT::f32)
352 return FPROUND_F32_F16;
353 if (OpVT == MVT::f64)
354 return FPROUND_F64_F16;
355 if (OpVT == MVT::f80)
356 return FPROUND_F80_F16;
357 if (OpVT == MVT::f128)
358 return FPROUND_F128_F16;
359 if (OpVT == MVT::ppcf128)
360 return FPROUND_PPCF128_F16;
361 } else if (RetVT == MVT::bf16) {
362 if (OpVT == MVT::f32)
363 return FPROUND_F32_BF16;
364 if (OpVT == MVT::f64)
365 return FPROUND_F64_BF16;
366 } else if (RetVT == MVT::f32) {
367 if (OpVT == MVT::f64)
368 return FPROUND_F64_F32;
369 if (OpVT == MVT::f80)
370 return FPROUND_F80_F32;
371 if (OpVT == MVT::f128)
372 return FPROUND_F128_F32;
373 if (OpVT == MVT::ppcf128)
374 return FPROUND_PPCF128_F32;
375 } else if (RetVT == MVT::f64) {
376 if (OpVT == MVT::f80)
377 return FPROUND_F80_F64;
378 if (OpVT == MVT::f128)
379 return FPROUND_F128_F64;
380 if (OpVT == MVT::ppcf128)
381 return FPROUND_PPCF128_F64;
382 } else if (RetVT == MVT::f80) {
383 if (OpVT == MVT::f128)
384 return FPROUND_F128_F80;
385 }
386
387 return UNKNOWN_LIBCALL;
388}
389
390/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
391/// UNKNOWN_LIBCALL if there is none.
393 if (OpVT == MVT::f16) {
394 if (RetVT == MVT::i32)
395 return FPTOSINT_F16_I32;
396 if (RetVT == MVT::i64)
397 return FPTOSINT_F16_I64;
398 if (RetVT == MVT::i128)
399 return FPTOSINT_F16_I128;
400 } else if (OpVT == MVT::f32) {
401 if (RetVT == MVT::i32)
402 return FPTOSINT_F32_I32;
403 if (RetVT == MVT::i64)
404 return FPTOSINT_F32_I64;
405 if (RetVT == MVT::i128)
406 return FPTOSINT_F32_I128;
407 } else if (OpVT == MVT::f64) {
408 if (RetVT == MVT::i32)
409 return FPTOSINT_F64_I32;
410 if (RetVT == MVT::i64)
411 return FPTOSINT_F64_I64;
412 if (RetVT == MVT::i128)
413 return FPTOSINT_F64_I128;
414 } else if (OpVT == MVT::f80) {
415 if (RetVT == MVT::i32)
416 return FPTOSINT_F80_I32;
417 if (RetVT == MVT::i64)
418 return FPTOSINT_F80_I64;
419 if (RetVT == MVT::i128)
420 return FPTOSINT_F80_I128;
421 } else if (OpVT == MVT::f128) {
422 if (RetVT == MVT::i32)
423 return FPTOSINT_F128_I32;
424 if (RetVT == MVT::i64)
425 return FPTOSINT_F128_I64;
426 if (RetVT == MVT::i128)
427 return FPTOSINT_F128_I128;
428 } else if (OpVT == MVT::ppcf128) {
429 if (RetVT == MVT::i32)
430 return FPTOSINT_PPCF128_I32;
431 if (RetVT == MVT::i64)
432 return FPTOSINT_PPCF128_I64;
433 if (RetVT == MVT::i128)
434 return FPTOSINT_PPCF128_I128;
435 }
436 return UNKNOWN_LIBCALL;
437}
438
439/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
440/// UNKNOWN_LIBCALL if there is none.
442 if (OpVT == MVT::f16) {
443 if (RetVT == MVT::i32)
444 return FPTOUINT_F16_I32;
445 if (RetVT == MVT::i64)
446 return FPTOUINT_F16_I64;
447 if (RetVT == MVT::i128)
448 return FPTOUINT_F16_I128;
449 } else if (OpVT == MVT::f32) {
450 if (RetVT == MVT::i32)
451 return FPTOUINT_F32_I32;
452 if (RetVT == MVT::i64)
453 return FPTOUINT_F32_I64;
454 if (RetVT == MVT::i128)
455 return FPTOUINT_F32_I128;
456 } else if (OpVT == MVT::f64) {
457 if (RetVT == MVT::i32)
458 return FPTOUINT_F64_I32;
459 if (RetVT == MVT::i64)
460 return FPTOUINT_F64_I64;
461 if (RetVT == MVT::i128)
462 return FPTOUINT_F64_I128;
463 } else if (OpVT == MVT::f80) {
464 if (RetVT == MVT::i32)
465 return FPTOUINT_F80_I32;
466 if (RetVT == MVT::i64)
467 return FPTOUINT_F80_I64;
468 if (RetVT == MVT::i128)
469 return FPTOUINT_F80_I128;
470 } else if (OpVT == MVT::f128) {
471 if (RetVT == MVT::i32)
472 return FPTOUINT_F128_I32;
473 if (RetVT == MVT::i64)
474 return FPTOUINT_F128_I64;
475 if (RetVT == MVT::i128)
476 return FPTOUINT_F128_I128;
477 } else if (OpVT == MVT::ppcf128) {
478 if (RetVT == MVT::i32)
479 return FPTOUINT_PPCF128_I32;
480 if (RetVT == MVT::i64)
481 return FPTOUINT_PPCF128_I64;
482 if (RetVT == MVT::i128)
483 return FPTOUINT_PPCF128_I128;
484 }
485 return UNKNOWN_LIBCALL;
486}
487
488/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
489/// UNKNOWN_LIBCALL if there is none.
491 if (OpVT == MVT::i32) {
492 if (RetVT == MVT::f16)
493 return SINTTOFP_I32_F16;
494 if (RetVT == MVT::f32)
495 return SINTTOFP_I32_F32;
496 if (RetVT == MVT::f64)
497 return SINTTOFP_I32_F64;
498 if (RetVT == MVT::f80)
499 return SINTTOFP_I32_F80;
500 if (RetVT == MVT::f128)
501 return SINTTOFP_I32_F128;
502 if (RetVT == MVT::ppcf128)
503 return SINTTOFP_I32_PPCF128;
504 } else if (OpVT == MVT::i64) {
505 if (RetVT == MVT::f16)
506 return SINTTOFP_I64_F16;
507 if (RetVT == MVT::f32)
508 return SINTTOFP_I64_F32;
509 if (RetVT == MVT::f64)
510 return SINTTOFP_I64_F64;
511 if (RetVT == MVT::f80)
512 return SINTTOFP_I64_F80;
513 if (RetVT == MVT::f128)
514 return SINTTOFP_I64_F128;
515 if (RetVT == MVT::ppcf128)
516 return SINTTOFP_I64_PPCF128;
517 } else if (OpVT == MVT::i128) {
518 if (RetVT == MVT::f16)
519 return SINTTOFP_I128_F16;
520 if (RetVT == MVT::f32)
521 return SINTTOFP_I128_F32;
522 if (RetVT == MVT::f64)
523 return SINTTOFP_I128_F64;
524 if (RetVT == MVT::f80)
525 return SINTTOFP_I128_F80;
526 if (RetVT == MVT::f128)
527 return SINTTOFP_I128_F128;
528 if (RetVT == MVT::ppcf128)
529 return SINTTOFP_I128_PPCF128;
530 }
531 return UNKNOWN_LIBCALL;
532}
533
534/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
535/// UNKNOWN_LIBCALL if there is none.
537 if (OpVT == MVT::i32) {
538 if (RetVT == MVT::f16)
539 return UINTTOFP_I32_F16;
540 if (RetVT == MVT::f32)
541 return UINTTOFP_I32_F32;
542 if (RetVT == MVT::f64)
543 return UINTTOFP_I32_F64;
544 if (RetVT == MVT::f80)
545 return UINTTOFP_I32_F80;
546 if (RetVT == MVT::f128)
547 return UINTTOFP_I32_F128;
548 if (RetVT == MVT::ppcf128)
549 return UINTTOFP_I32_PPCF128;
550 } else if (OpVT == MVT::i64) {
551 if (RetVT == MVT::f16)
552 return UINTTOFP_I64_F16;
553 if (RetVT == MVT::f32)
554 return UINTTOFP_I64_F32;
555 if (RetVT == MVT::f64)
556 return UINTTOFP_I64_F64;
557 if (RetVT == MVT::f80)
558 return UINTTOFP_I64_F80;
559 if (RetVT == MVT::f128)
560 return UINTTOFP_I64_F128;
561 if (RetVT == MVT::ppcf128)
562 return UINTTOFP_I64_PPCF128;
563 } else if (OpVT == MVT::i128) {
564 if (RetVT == MVT::f16)
565 return UINTTOFP_I128_F16;
566 if (RetVT == MVT::f32)
567 return UINTTOFP_I128_F32;
568 if (RetVT == MVT::f64)
569 return UINTTOFP_I128_F64;
570 if (RetVT == MVT::f80)
571 return UINTTOFP_I128_F80;
572 if (RetVT == MVT::f128)
573 return UINTTOFP_I128_F128;
574 if (RetVT == MVT::ppcf128)
575 return UINTTOFP_I128_PPCF128;
576 }
577 return UNKNOWN_LIBCALL;
578}
579
581 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
582 POWI_PPCF128);
583}
584
586 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,
587 LDEXP_PPCF128);
588}
589
591 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,
592 FREXP_PPCF128);
593}
594
596 AtomicOrdering Order,
597 uint64_t MemSize) {
598 unsigned ModeN, ModelN;
599 switch (MemSize) {
600 case 1:
601 ModeN = 0;
602 break;
603 case 2:
604 ModeN = 1;
605 break;
606 case 4:
607 ModeN = 2;
608 break;
609 case 8:
610 ModeN = 3;
611 break;
612 case 16:
613 ModeN = 4;
614 break;
615 default:
616 return RTLIB::UNKNOWN_LIBCALL;
617 }
618
619 switch (Order) {
621 ModelN = 0;
622 break;
624 ModelN = 1;
625 break;
627 ModelN = 2;
628 break;
631 ModelN = 3;
632 break;
633 default:
634 return UNKNOWN_LIBCALL;
635 }
636
637 return LC[ModeN][ModelN];
638}
639
641 MVT VT) {
642 if (!VT.isScalarInteger())
643 return UNKNOWN_LIBCALL;
644 uint64_t MemSize = VT.getScalarSizeInBits() / 8;
645
646#define LCALLS(A, B) \
647 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
648#define LCALL5(A) \
649 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
650 switch (Opc) {
652 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
653 return getOutlineAtomicHelper(LC, Order, MemSize);
654 }
655 case ISD::ATOMIC_SWAP: {
656 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)};
657 return getOutlineAtomicHelper(LC, Order, MemSize);
658 }
660 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)};
661 return getOutlineAtomicHelper(LC, Order, MemSize);
662 }
663 case ISD::ATOMIC_LOAD_OR: {
664 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)};
665 return getOutlineAtomicHelper(LC, Order, MemSize);
666 }
668 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)};
669 return getOutlineAtomicHelper(LC, Order, MemSize);
670 }
672 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)};
673 return getOutlineAtomicHelper(LC, Order, MemSize);
674 }
675 default:
676 return UNKNOWN_LIBCALL;
677 }
678#undef LCALLS
679#undef LCALL5
680}
681
683#define OP_TO_LIBCALL(Name, Enum) \
684 case Name: \
685 switch (VT.SimpleTy) { \
686 default: \
687 return UNKNOWN_LIBCALL; \
688 case MVT::i8: \
689 return Enum##_1; \
690 case MVT::i16: \
691 return Enum##_2; \
692 case MVT::i32: \
693 return Enum##_4; \
694 case MVT::i64: \
695 return Enum##_8; \
696 case MVT::i128: \
697 return Enum##_16; \
698 }
699
700 switch (Opc) {
701 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
702 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
703 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
704 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
705 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
706 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
707 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
708 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
709 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
710 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
711 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
712 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
713 }
714
715#undef OP_TO_LIBCALL
716
717 return UNKNOWN_LIBCALL;
718}
719
721 switch (ElementSize) {
722 case 1:
723 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
724 case 2:
725 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
726 case 4:
727 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
728 case 8:
729 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
730 case 16:
731 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
732 default:
733 return UNKNOWN_LIBCALL;
734 }
735}
736
738 switch (ElementSize) {
739 case 1:
740 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
741 case 2:
742 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
743 case 4:
744 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
745 case 8:
746 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
747 case 16:
748 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
749 default:
750 return UNKNOWN_LIBCALL;
751 }
752}
753
755 switch (ElementSize) {
756 case 1:
757 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
758 case 2:
759 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
760 case 4:
761 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
762 case 8:
763 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
764 case 16:
765 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
766 default:
767 return UNKNOWN_LIBCALL;
768 }
769}
770
771/// InitCmpLibcallCCs - Set default comparison libcall CC.
773 std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID);
774 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
775 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
776 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
777 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
778 CCs[RTLIB::UNE_F32] = ISD::SETNE;
779 CCs[RTLIB::UNE_F64] = ISD::SETNE;
780 CCs[RTLIB::UNE_F128] = ISD::SETNE;
781 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
782 CCs[RTLIB::OGE_F32] = ISD::SETGE;
783 CCs[RTLIB::OGE_F64] = ISD::SETGE;
784 CCs[RTLIB::OGE_F128] = ISD::SETGE;
785 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
786 CCs[RTLIB::OLT_F32] = ISD::SETLT;
787 CCs[RTLIB::OLT_F64] = ISD::SETLT;
788 CCs[RTLIB::OLT_F128] = ISD::SETLT;
789 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
790 CCs[RTLIB::OLE_F32] = ISD::SETLE;
791 CCs[RTLIB::OLE_F64] = ISD::SETLE;
792 CCs[RTLIB::OLE_F128] = ISD::SETLE;
793 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
794 CCs[RTLIB::OGT_F32] = ISD::SETGT;
795 CCs[RTLIB::OGT_F64] = ISD::SETGT;
796 CCs[RTLIB::OGT_F128] = ISD::SETGT;
797 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
798 CCs[RTLIB::UO_F32] = ISD::SETNE;
799 CCs[RTLIB::UO_F64] = ISD::SETNE;
800 CCs[RTLIB::UO_F128] = ISD::SETNE;
801 CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
802}
803
804/// NOTE: The TargetMachine owns TLOF.
806 initActions();
807
808 // Perform these initializations only once.
814 HasMultipleConditionRegisters = false;
815 HasExtractBitsInsn = false;
816 JumpIsExpensive = JumpIsExpensiveOverride;
818 EnableExtLdPromotion = false;
819 StackPointerRegisterToSaveRestore = 0;
820 BooleanContents = UndefinedBooleanContent;
821 BooleanFloatContents = UndefinedBooleanContent;
822 BooleanVectorContents = UndefinedBooleanContent;
823 SchedPreferenceInfo = Sched::ILP;
826 MaxBytesForAlignment = 0;
827 MaxAtomicSizeInBitsSupported = 0;
828
829 // Assume that even with libcalls, no target supports wider than 128 bit
830 // division.
831 MaxDivRemBitWidthSupported = 128;
832
833 MaxLargeFPConvertBitWidthSupported = llvm::IntegerType::MAX_INT_BITS;
834
835 MinCmpXchgSizeInBits = 0;
836 SupportsUnalignedAtomics = false;
837
838 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
839
840 InitLibcalls(TM.getTargetTriple());
841 InitCmpLibcallCCs(CmpLibcallCCs);
842}
843
845 // All operations default to being supported.
846 memset(OpActions, 0, sizeof(OpActions));
847 memset(LoadExtActions, 0, sizeof(LoadExtActions));
848 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
849 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
850 memset(CondCodeActions, 0, sizeof(CondCodeActions));
851 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
852 std::fill(std::begin(TargetDAGCombineArray),
853 std::end(TargetDAGCombineArray), 0);
854
855 // Let extending atomic loads be unsupported by default.
856 for (MVT ValVT : MVT::all_valuetypes())
857 for (MVT MemVT : MVT::all_valuetypes())
859 Expand);
860
861 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to
862 // remove this and targets should individually set these types if not legal.
865 for (MVT VT : {MVT::i2, MVT::i4})
866 OpActions[(unsigned)VT.SimpleTy][NT] = Expand;
867 }
868 for (MVT AVT : MVT::all_valuetypes()) {
869 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
870 setTruncStoreAction(AVT, VT, Expand);
873 }
874 }
875 for (unsigned IM = (unsigned)ISD::PRE_INC;
876 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
877 for (MVT VT : {MVT::i2, MVT::i4}) {
882 }
883 }
884
885 for (MVT VT : MVT::fp_valuetypes()) {
886 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits());
887 if (IntVT.isValid()) {
890 }
891 }
892
893 // Set default actions for various operations.
894 for (MVT VT : MVT::all_valuetypes()) {
895 // Default all indexed load / store to expand.
896 for (unsigned IM = (unsigned)ISD::PRE_INC;
897 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
902 }
903
904 // Most backends expect to see the node which just returns the value loaded.
906
907 // These operations default to expand.
925 VT, Expand);
926
927 // Overflow operations default to expand
930 VT, Expand);
931
932 // Carry-using overflow operations default to expand.
935 VT, Expand);
936
937 // ADDC/ADDE/SUBC/SUBE default to expand.
939 Expand);
940
941 // [US]CMP default to expand
943
944 // Halving adds
947 Expand);
948
949 // Absolute difference
951
952 // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
954 Expand);
955
957
958 // These library functions default to expand.
960 Expand);
961
962 // These operations default to expand for vector types.
963 if (VT.isVector())
968 VT, Expand);
969
970 // Constrained floating-point operations default to expand.
971#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
972 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
973#include "llvm/IR/ConstrainedOps.def"
974
975 // For most targets @llvm.get.dynamic.area.offset just returns 0.
977
978 // Vector reduction default to expand.
986 VT, Expand);
987
988 // Named vector shuffles default to expand.
990
991 // VP operations default to expand.
992#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
993 setOperationAction(ISD::SDOPC, VT, Expand);
994#include "llvm/IR/VPIntrinsics.def"
995
996 // FP environment operations default to expand.
1000 }
1001
1002 // Most targets ignore the @llvm.prefetch intrinsic.
1004
1005 // Most targets also ignore the @llvm.readcyclecounter intrinsic.
1007
1008 // Most targets also ignore the @llvm.readsteadycounter intrinsic.
1010
1011 // ConstantFP nodes default to expand. Targets can either change this to
1012 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
1013 // to optimize expansions for certain constants.
1015 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
1016 Expand);
1017
1018 // These library functions default to expand.
1023 ISD::FTAN},
1024 {MVT::f32, MVT::f64, MVT::f128}, Expand);
1025
1027 // Default ISD::TRAP to expand (which turns it into abort).
1028 setOperationAction(ISD::TRAP, MVT::Other, Expand);
1029
1030 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
1031 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
1033
1035
1038
1039 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1042 }
1044
1045 // This one by default will call __clear_cache unless the target
1046 // wants something different.
1048}
1049
1051 EVT) const {
1052 return MVT::getIntegerVT(DL.getPointerSizeInBits(0));
1053}
1054
1056 bool LegalTypes) const {
1057 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
1058 if (LHSTy.isVector())
1059 return LHSTy;
1060 MVT ShiftVT =
1061 LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) : getPointerTy(DL);
1062 // If any possible shift value won't fit in the prefered type, just use
1063 // something safe. Assume it will be legalized when the shift is expanded.
1064 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits()))
1065 ShiftVT = MVT::i32;
1066 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) &&
1067 "ShiftVT is still too small!");
1068 return ShiftVT;
1069}
1070
1071bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
1072 assert(isTypeLegal(VT));
1073 switch (Op) {
1074 default:
1075 return false;
1076 case ISD::SDIV:
1077 case ISD::UDIV:
1078 case ISD::SREM:
1079 case ISD::UREM:
1080 return true;
1081 }
1082}
1083
1085 unsigned DestAS) const {
1086 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1087}
1088
1090 Type *RetTy, ElementCount EC, bool ZeroIsPoison,
1091 const ConstantRange *VScaleRange) const {
1092 // Find the smallest "sensible" element type to use for the expansion.
1093 ConstantRange CR(APInt(64, EC.getKnownMinValue()));
1094 if (EC.isScalable())
1095 CR = CR.umul_sat(*VScaleRange);
1096
1097 if (ZeroIsPoison)
1098 CR = CR.subtract(APInt(64, 1));
1099
1100 unsigned EltWidth = RetTy->getScalarSizeInBits();
1101 EltWidth = std::min(EltWidth, (unsigned)CR.getActiveBits());
1102 EltWidth = std::max(llvm::bit_ceil(EltWidth), (unsigned)8);
1103
1104 return EltWidth;
1105}
1106
1108 // If the command-line option was specified, ignore this request.
1109 if (!JumpIsExpensiveOverride.getNumOccurrences())
1110 JumpIsExpensive = isExpensive;
1111}
1112
1115 // If this is a simple type, use the ComputeRegisterProp mechanism.
1116 if (VT.isSimple()) {
1117 MVT SVT = VT.getSimpleVT();
1118 assert((unsigned)SVT.SimpleTy < std::size(TransformToType));
1119 MVT NVT = TransformToType[SVT.SimpleTy];
1120 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1121
1122 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
1123 LA == TypeSoftPromoteHalf ||
1124 (NVT.isVector() ||
1125 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) &&
1126 "Promote may not follow Expand or Promote");
1127
1128 if (LA == TypeSplitVector)
1129 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context));
1130 if (LA == TypeScalarizeVector)
1131 return LegalizeKind(LA, SVT.getVectorElementType());
1132 return LegalizeKind(LA, NVT);
1133 }
1134
1135 // Handle Extended Scalar Types.
1136 if (!VT.isVector()) {
1137 assert(VT.isInteger() && "Float types must be simple");
1138 unsigned BitSize = VT.getSizeInBits();
1139 // First promote to a power-of-two size, then expand if necessary.
1140 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1141 EVT NVT = VT.getRoundIntegerType(Context);
1142 assert(NVT != VT && "Unable to round integer VT");
1143 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1144 // Avoid multi-step promotion.
1145 if (NextStep.first == TypePromoteInteger)
1146 return NextStep;
1147 // Return rounded integer type.
1148 return LegalizeKind(TypePromoteInteger, NVT);
1149 }
1150
1152 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
1153 }
1154
1155 // Handle vector types.
1156 ElementCount NumElts = VT.getVectorElementCount();
1157 EVT EltVT = VT.getVectorElementType();
1158
1159 // Vectors with only one element are always scalarized.
1160 if (NumElts.isScalar())
1161 return LegalizeKind(TypeScalarizeVector, EltVT);
1162
1163 // Try to widen vector elements until the element type is a power of two and
1164 // promote it to a legal type later on, for example:
1165 // <3 x i8> -> <4 x i8> -> <4 x i32>
1166 if (EltVT.isInteger()) {
1167 // Vectors with a number of elements that is not a power of two are always
1168 // widened, for example <3 x i8> -> <4 x i8>.
1169 if (!VT.isPow2VectorType()) {
1170 NumElts = NumElts.coefficientNextPowerOf2();
1171 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1172 return LegalizeKind(TypeWidenVector, NVT);
1173 }
1174
1175 // Examine the element type.
1176 LegalizeKind LK = getTypeConversion(Context, EltVT);
1177
1178 // If type is to be expanded, split the vector.
1179 // <4 x i140> -> <2 x i140>
1180 if (LK.first == TypeExpandInteger) {
1184 VT.getHalfNumVectorElementsVT(Context));
1185 }
1186
1187 // Promote the integer element types until a legal vector type is found
1188 // or until the element integer type is too big. If a legal type was not
1189 // found, fallback to the usual mechanism of widening/splitting the
1190 // vector.
1191 EVT OldEltVT = EltVT;
1192 while (true) {
1193 // Increase the bitwidth of the element to the next pow-of-two
1194 // (which is greater than 8 bits).
1195 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1196 .getRoundIntegerType(Context);
1197
1198 // Stop trying when getting a non-simple element type.
1199 // Note that vector elements may be greater than legal vector element
1200 // types. Example: X86 XMM registers hold 64bit element on 32bit
1201 // systems.
1202 if (!EltVT.isSimple())
1203 break;
1204
1205 // Build a new vector type and check if it is legal.
1206 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1207 // Found a legal promoted vector type.
1208 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1210 EVT::getVectorVT(Context, EltVT, NumElts));
1211 }
1212
1213 // Reset the type to the unexpanded type if we did not find a legal vector
1214 // type with a promoted vector element type.
1215 EltVT = OldEltVT;
1216 }
1217
1218 // Try to widen the vector until a legal type is found.
1219 // If there is no wider legal type, split the vector.
1220 while (true) {
1221 // Round up to the next power of 2.
1222 NumElts = NumElts.coefficientNextPowerOf2();
1223
1224 // If there is no simple vector type with this many elements then there
1225 // cannot be a larger legal vector type. Note that this assumes that
1226 // there are no skipped intermediate vector types in the simple types.
1227 if (!EltVT.isSimple())
1228 break;
1229 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1230 if (LargerVector == MVT())
1231 break;
1232
1233 // If this type is legal then widen the vector.
1234 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1235 return LegalizeKind(TypeWidenVector, LargerVector);
1236 }
1237
1238 // Widen odd vectors to next power of two.
1239 if (!VT.isPow2VectorType()) {
1240 EVT NVT = VT.getPow2VectorType(Context);
1241 return LegalizeKind(TypeWidenVector, NVT);
1242 }
1243
1246
1247 // Vectors with illegal element types are expanded.
1248 EVT NVT = EVT::getVectorVT(Context, EltVT,
1250 return LegalizeKind(TypeSplitVector, NVT);
1251}
1252
1253static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1254 unsigned &NumIntermediates,
1255 MVT &RegisterVT,
1256 TargetLoweringBase *TLI) {
1257 // Figure out the right, legal destination reg to copy into.
1259 MVT EltTy = VT.getVectorElementType();
1260
1261 unsigned NumVectorRegs = 1;
1262
1263 // Scalable vectors cannot be scalarized, so splitting or widening is
1264 // required.
1265 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue()))
1267 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1268
1269 // FIXME: We don't support non-power-of-2-sized vectors for now.
1270 // Ideally we could break down into LHS/RHS like LegalizeDAG does.
1271 if (!isPowerOf2_32(EC.getKnownMinValue())) {
1272 // Split EC to unit size (scalable property is preserved).
1273 NumVectorRegs = EC.getKnownMinValue();
1274 EC = ElementCount::getFixed(1);
1275 }
1276
1277 // Divide the input until we get to a supported size. This will
1278 // always end up with an EC that represent a scalar or a scalable
1279 // scalar.
1280 while (EC.getKnownMinValue() > 1 &&
1281 !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) {
1282 EC = EC.divideCoefficientBy(2);
1283 NumVectorRegs <<= 1;
1284 }
1285
1286 NumIntermediates = NumVectorRegs;
1287
1288 MVT NewVT = MVT::getVectorVT(EltTy, EC);
1289 if (!TLI->isTypeLegal(NewVT))
1290 NewVT = EltTy;
1291 IntermediateVT = NewVT;
1292
1293 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits();
1294
1295 // Convert sizes such as i33 to i64.
1296 LaneSizeInBits = llvm::bit_ceil(LaneSizeInBits);
1297
1298 MVT DestVT = TLI->getRegisterType(NewVT);
1299 RegisterVT = DestVT;
1300 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1301 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits());
1302
1303 // Otherwise, promotion or legal types use the same number of registers as
1304 // the vector decimated to the appropriate level.
1305 return NumVectorRegs;
1306}
1307
1308/// isLegalRC - Return true if the value types that can be represented by the
1309/// specified register class are all legal.
1311 const TargetRegisterClass &RC) const {
1312 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
1313 if (isTypeLegal(*I))
1314 return true;
1315 return false;
1316}
1317
1318/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1319/// sequence of memory operands that is recognized by PrologEpilogInserter.
1322 MachineBasicBlock *MBB) const {
1323 MachineInstr *MI = &InitialMI;
1324 MachineFunction &MF = *MI->getMF();
1325 MachineFrameInfo &MFI = MF.getFrameInfo();
1326
1327 // We're handling multiple types of operands here:
1328 // PATCHPOINT MetaArgs - live-in, read only, direct
1329 // STATEPOINT Deopt Spill - live-through, read only, indirect
1330 // STATEPOINT Deopt Alloca - live-through, read only, direct
1331 // (We're currently conservative and mark the deopt slots read/write in
1332 // practice.)
1333 // STATEPOINT GC Spill - live-through, read/write, indirect
1334 // STATEPOINT GC Alloca - live-through, read/write, direct
1335 // The live-in vs live-through is handled already (the live through ones are
1336 // all stack slots), but we need to handle the different type of stackmap
1337 // operands and memory effects here.
1338
1339 if (llvm::none_of(MI->operands(),
1340 [](MachineOperand &Operand) { return Operand.isFI(); }))
1341 return MBB;
1342
1343 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1344
1345 // Inherit previous memory operands.
1346 MIB.cloneMemRefs(*MI);
1347
1348 for (unsigned i = 0; i < MI->getNumOperands(); ++i) {
1349 MachineOperand &MO = MI->getOperand(i);
1350 if (!MO.isFI()) {
1351 // Index of Def operand this Use it tied to.
1352 // Since Defs are coming before Uses, if Use is tied, then
1353 // index of Def must be smaller that index of that Use.
1354 // Also, Defs preserve their position in new MI.
1355 unsigned TiedTo = i;
1356 if (MO.isReg() && MO.isTied())
1357 TiedTo = MI->findTiedOperandIdx(i);
1358 MIB.add(MO);
1359 if (TiedTo < i)
1360 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1);
1361 continue;
1362 }
1363
1364 // foldMemoryOperand builds a new MI after replacing a single FI operand
1365 // with the canonical set of five x86 addressing-mode operands.
1366 int FI = MO.getIndex();
1367
1368 // Add frame index operands recognized by stackmaps.cpp
1370 // indirect-mem-ref tag, size, #FI, offset.
1371 // Used for spills inserted by StatepointLowering. This codepath is not
1372 // used for patchpoints/stackmaps at all, for these spilling is done via
1373 // foldMemoryOperand callback only.
1374 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1375 MIB.addImm(StackMaps::IndirectMemRefOp);
1376 MIB.addImm(MFI.getObjectSize(FI));
1377 MIB.add(MO);
1378 MIB.addImm(0);
1379 } else {
1380 // direct-mem-ref tag, #FI, offset.
1381 // Used by patchpoint, and direct alloca arguments to statepoints
1382 MIB.addImm(StackMaps::DirectMemRefOp);
1383 MIB.add(MO);
1384 MIB.addImm(0);
1385 }
1386
1387 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1388
1389 // Add a new memory operand for this FI.
1390 assert(MFI.getObjectOffset(FI) != -1);
1391
1392 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1393 // PATCHPOINT should be updated to do the same. (TODO)
1394 if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1395 auto Flags = MachineMemOperand::MOLoad;
1397 MachinePointerInfo::getFixedStack(MF, FI), Flags,
1399 MIB->addMemOperand(MF, MMO);
1400 }
1401 }
1403 MI->eraseFromParent();
1404 return MBB;
1405}
1406
1407/// findRepresentativeClass - Return the largest legal super-reg register class
1408/// of the register class for the specified type and its associated "cost".
1409// This function is in TargetLowering because it uses RegClassForVT which would
1410// need to be moved to TargetRegisterInfo and would necessitate moving
1411// isTypeLegal over as well - a massive change that would just require
1412// TargetLowering having a TargetRegisterInfo class member that it would use.
1413std::pair<const TargetRegisterClass *, uint8_t>
1415 MVT VT) const {
1416 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1417 if (!RC)
1418 return std::make_pair(RC, 0);
1419
1420 // Compute the set of all super-register classes.
1421 BitVector SuperRegRC(TRI->getNumRegClasses());
1422 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1423 SuperRegRC.setBitsInMask(RCI.getMask());
1424
1425 // Find the first legal register class with the largest spill size.
1426 const TargetRegisterClass *BestRC = RC;
1427 for (unsigned i : SuperRegRC.set_bits()) {
1428 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1429 // We want the largest possible spill size.
1430 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1431 continue;
1432 if (!isLegalRC(*TRI, *SuperRC))
1433 continue;
1434 BestRC = SuperRC;
1435 }
1436 return std::make_pair(BestRC, 1);
1437}
1438
1439/// computeRegisterProperties - Once all of the register classes are added,
1440/// this allows us to compute derived properties we expose.
1442 const TargetRegisterInfo *TRI) {
1443 // Everything defaults to needing one register.
1444 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1445 NumRegistersForVT[i] = 1;
1446 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1447 }
1448 // ...except isVoid, which doesn't need any registers.
1449 NumRegistersForVT[MVT::isVoid] = 0;
1450
1451 // Find the largest integer register class.
1452 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1453 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1454 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1455
1456 // Every integer value type larger than this largest register takes twice as
1457 // many registers to represent as the previous ValueType.
1458 for (unsigned ExpandedReg = LargestIntReg + 1;
1459 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1460 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1461 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1462 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1463 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1465 }
1466
1467 // Inspect all of the ValueType's smaller than the largest integer
1468 // register to see which ones need promotion.
1469 unsigned LegalIntReg = LargestIntReg;
1470 for (unsigned IntReg = LargestIntReg - 1;
1471 IntReg >= (unsigned)MVT::i1; --IntReg) {
1472 MVT IVT = (MVT::SimpleValueType)IntReg;
1473 if (isTypeLegal(IVT)) {
1474 LegalIntReg = IntReg;
1475 } else {
1476 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1477 (MVT::SimpleValueType)LegalIntReg;
1478 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1479 }
1480 }
1481
1482 // ppcf128 type is really two f64's.
1483 if (!isTypeLegal(MVT::ppcf128)) {
1484 if (isTypeLegal(MVT::f64)) {
1485 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1486 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1487 TransformToType[MVT::ppcf128] = MVT::f64;
1488 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1489 } else {
1490 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1491 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1492 TransformToType[MVT::ppcf128] = MVT::i128;
1493 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1494 }
1495 }
1496
1497 // Decide how to handle f128. If the target does not have native f128 support,
1498 // expand it to i128 and we will be generating soft float library calls.
1499 if (!isTypeLegal(MVT::f128)) {
1500 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1501 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1502 TransformToType[MVT::f128] = MVT::i128;
1503 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1504 }
1505
1506 // Decide how to handle f80. If the target does not have native f80 support,
1507 // expand it to i96 and we will be generating soft float library calls.
1508 if (!isTypeLegal(MVT::f80)) {
1509 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1510 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1511 TransformToType[MVT::f80] = MVT::i32;
1512 ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat);
1513 }
1514
1515 // Decide how to handle f64. If the target does not have native f64 support,
1516 // expand it to i64 and we will be generating soft float library calls.
1517 if (!isTypeLegal(MVT::f64)) {
1518 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1519 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1520 TransformToType[MVT::f64] = MVT::i64;
1521 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1522 }
1523
1524 // Decide how to handle f32. If the target does not have native f32 support,
1525 // expand it to i32 and we will be generating soft float library calls.
1526 if (!isTypeLegal(MVT::f32)) {
1527 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1528 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1529 TransformToType[MVT::f32] = MVT::i32;
1530 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
1531 }
1532
1533 // Decide how to handle f16. If the target does not have native f16 support,
1534 // promote it to f32, because there are no f16 library calls (except for
1535 // conversions).
1536 if (!isTypeLegal(MVT::f16)) {
1537 // Allow targets to control how we legalize half.
1538 bool SoftPromoteHalfType = softPromoteHalfType();
1539 bool UseFPRegsForHalfType = !SoftPromoteHalfType || useFPRegsForHalfType();
1540
1541 if (!UseFPRegsForHalfType) {
1542 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1543 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1544 } else {
1545 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1546 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1547 }
1548 TransformToType[MVT::f16] = MVT::f32;
1549 if (SoftPromoteHalfType) {
1550 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf);
1551 } else {
1552 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1553 }
1554 }
1555
1556 // Decide how to handle bf16. If the target does not have native bf16 support,
1557 // promote it to f32, because there are no bf16 library calls (except for
1558 // converting from f32 to bf16).
1559 if (!isTypeLegal(MVT::bf16)) {
1560 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1561 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1562 TransformToType[MVT::bf16] = MVT::f32;
1563 ValueTypeActions.setTypeAction(MVT::bf16, TypeSoftPromoteHalf);
1564 }
1565
1566 // Loop over all of the vector value types to see which need transformations.
1567 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1568 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1569 MVT VT = (MVT::SimpleValueType) i;
1570 if (isTypeLegal(VT))
1571 continue;
1572
1573 MVT EltVT = VT.getVectorElementType();
1575 bool IsLegalWiderType = false;
1576 bool IsScalable = VT.isScalableVector();
1577 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1578 switch (PreferredAction) {
1579 case TypePromoteInteger: {
1580 MVT::SimpleValueType EndVT = IsScalable ?
1581 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1582 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1583 // Try to promote the elements of integer vectors. If no legal
1584 // promotion was found, fall through to the widen-vector method.
1585 for (unsigned nVT = i + 1;
1586 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) {
1587 MVT SVT = (MVT::SimpleValueType) nVT;
1588 // Promote vectors of integers to vectors with the same number
1589 // of elements, with a wider element type.
1590 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() &&
1591 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) {
1592 TransformToType[i] = SVT;
1593 RegisterTypeForVT[i] = SVT;
1594 NumRegistersForVT[i] = 1;
1595 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1596 IsLegalWiderType = true;
1597 break;
1598 }
1599 }
1600 if (IsLegalWiderType)
1601 break;
1602 [[fallthrough]];
1603 }
1604
1605 case TypeWidenVector:
1606 if (isPowerOf2_32(EC.getKnownMinValue())) {
1607 // Try to widen the vector.
1608 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1609 MVT SVT = (MVT::SimpleValueType) nVT;
1610 if (SVT.getVectorElementType() == EltVT &&
1611 SVT.isScalableVector() == IsScalable &&
1613 EC.getKnownMinValue() &&
1614 isTypeLegal(SVT)) {
1615 TransformToType[i] = SVT;
1616 RegisterTypeForVT[i] = SVT;
1617 NumRegistersForVT[i] = 1;
1618 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1619 IsLegalWiderType = true;
1620 break;
1621 }
1622 }
1623 if (IsLegalWiderType)
1624 break;
1625 } else {
1626 // Only widen to the next power of 2 to keep consistency with EVT.
1627 MVT NVT = VT.getPow2VectorType();
1628 if (isTypeLegal(NVT)) {
1629 TransformToType[i] = NVT;
1630 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1631 RegisterTypeForVT[i] = NVT;
1632 NumRegistersForVT[i] = 1;
1633 break;
1634 }
1635 }
1636 [[fallthrough]];
1637
1638 case TypeSplitVector:
1639 case TypeScalarizeVector: {
1640 MVT IntermediateVT;
1641 MVT RegisterVT;
1642 unsigned NumIntermediates;
1643 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1644 NumIntermediates, RegisterVT, this);
1645 NumRegistersForVT[i] = NumRegisters;
1646 assert(NumRegistersForVT[i] == NumRegisters &&
1647 "NumRegistersForVT size cannot represent NumRegisters!");
1648 RegisterTypeForVT[i] = RegisterVT;
1649
1650 MVT NVT = VT.getPow2VectorType();
1651 if (NVT == VT) {
1652 // Type is already a power of 2. The default action is to split.
1653 TransformToType[i] = MVT::Other;
1654 if (PreferredAction == TypeScalarizeVector)
1655 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
1656 else if (PreferredAction == TypeSplitVector)
1657 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1658 else if (EC.getKnownMinValue() > 1)
1659 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
1660 else
1661 ValueTypeActions.setTypeAction(VT, EC.isScalable()
1664 } else {
1665 TransformToType[i] = NVT;
1666 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1667 }
1668 break;
1669 }
1670 default:
1671 llvm_unreachable("Unknown vector legalization action!");
1672 }
1673 }
1674
1675 // Determine the 'representative' register class for each value type.
1676 // An representative register class is the largest (meaning one which is
1677 // not a sub-register class / subreg register class) legal register class for
1678 // a group of value types. For example, on i386, i8, i16, and i32
1679 // representative would be GR32; while on x86_64 it's GR64.
1680 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) {
1681 const TargetRegisterClass* RRC;
1682 uint8_t Cost;
1684 RepRegClassForVT[i] = RRC;
1685 RepRegClassCostForVT[i] = Cost;
1686 }
1687}
1688
1690 EVT VT) const {
1691 assert(!VT.isVector() && "No default SetCC type for vectors!");
1692 return getPointerTy(DL).SimpleTy;
1693}
1694
1696 return MVT::i32; // return the default value
1697}
1698
1699/// getVectorTypeBreakdown - Vector types are broken down into some number of
1700/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1701/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1702/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1703///
1704/// This method returns the number of registers needed, and the VT for each
1705/// register. It also returns the VT and quantity of the intermediate values
1706/// before they are promoted/expanded.
1708 EVT VT, EVT &IntermediateVT,
1709 unsigned &NumIntermediates,
1710 MVT &RegisterVT) const {
1711 ElementCount EltCnt = VT.getVectorElementCount();
1712
1713 // If there is a wider vector type with the same element type as this one,
1714 // or a promoted vector type that has the same number of elements which
1715 // are wider, then we should convert to that legal vector type.
1716 // This handles things like <2 x float> -> <4 x float> and
1717 // <4 x i1> -> <4 x i32>.
1718 LegalizeTypeAction TA = getTypeAction(Context, VT);
1719 if (!EltCnt.isScalar() &&
1720 (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1721 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1722 if (isTypeLegal(RegisterEVT)) {
1723 IntermediateVT = RegisterEVT;
1724 RegisterVT = RegisterEVT.getSimpleVT();
1725 NumIntermediates = 1;
1726 return 1;
1727 }
1728 }
1729
1730 // Figure out the right, legal destination reg to copy into.
1731 EVT EltTy = VT.getVectorElementType();
1732
1733 unsigned NumVectorRegs = 1;
1734
1735 // Scalable vectors cannot be scalarized, so handle the legalisation of the
1736 // types like done elsewhere in SelectionDAG.
1737 if (EltCnt.isScalable()) {
1738 LegalizeKind LK;
1739 EVT PartVT = VT;
1740 do {
1741 // Iterate until we've found a legal (part) type to hold VT.
1742 LK = getTypeConversion(Context, PartVT);
1743 PartVT = LK.second;
1744 } while (LK.first != TypeLegal);
1745
1746 if (!PartVT.isVector()) {
1748 "Don't know how to legalize this scalable vector type");
1749 }
1750
1751 NumIntermediates =
1754 IntermediateVT = PartVT;
1755 RegisterVT = getRegisterType(Context, IntermediateVT);
1756 return NumIntermediates;
1757 }
1758
1759 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally
1760 // we could break down into LHS/RHS like LegalizeDAG does.
1761 if (!isPowerOf2_32(EltCnt.getKnownMinValue())) {
1762 NumVectorRegs = EltCnt.getKnownMinValue();
1763 EltCnt = ElementCount::getFixed(1);
1764 }
1765
1766 // Divide the input until we get to a supported size. This will always
1767 // end with a scalar if the target doesn't support vectors.
1768 while (EltCnt.getKnownMinValue() > 1 &&
1769 !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) {
1770 EltCnt = EltCnt.divideCoefficientBy(2);
1771 NumVectorRegs <<= 1;
1772 }
1773
1774 NumIntermediates = NumVectorRegs;
1775
1776 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt);
1777 if (!isTypeLegal(NewVT))
1778 NewVT = EltTy;
1779 IntermediateVT = NewVT;
1780
1781 MVT DestVT = getRegisterType(Context, NewVT);
1782 RegisterVT = DestVT;
1783
1784 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
1785 TypeSize NewVTSize = NewVT.getSizeInBits();
1786 // Convert sizes such as i33 to i64.
1787 if (!llvm::has_single_bit<uint32_t>(NewVTSize.getKnownMinValue()))
1788 NewVTSize = NewVTSize.coefficientNextPowerOf2();
1789 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1790 }
1791
1792 // Otherwise, promotion or legal types use the same number of registers as
1793 // the vector decimated to the appropriate level.
1794 return NumVectorRegs;
1795}
1796
1798 uint64_t NumCases,
1800 ProfileSummaryInfo *PSI,
1801 BlockFrequencyInfo *BFI) const {
1802 // FIXME: This function check the maximum table size and density, but the
1803 // minimum size is not checked. It would be nice if the minimum size is
1804 // also combined within this function. Currently, the minimum size check is
1805 // performed in findJumpTable() in SelectionDAGBuiler and
1806 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1807 const bool OptForSize =
1808 SI->getParent()->getParent()->hasOptSize() ||
1809 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI);
1810 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
1811 const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
1812
1813 // Check whether the number of cases is small enough and
1814 // the range is dense enough for a jump table.
1815 return (OptForSize || Range <= MaxJumpTableSize) &&
1816 (NumCases * 100 >= Range * MinDensity);
1817}
1818
1820 EVT ConditionVT) const {
1821 return getRegisterType(Context, ConditionVT);
1822}
1823
1824/// Get the EVTs and ArgFlags collections that represent the legalized return
1825/// type of the given function. This does not require a DAG or a return value,
1826/// and is suitable for use before any DAGs for the function are constructed.
1827/// TODO: Move this out of TargetLowering.cpp.
1829 AttributeList attr,
1831 const TargetLowering &TLI, const DataLayout &DL) {
1832 SmallVector<EVT, 4> ValueVTs;
1833 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1834 unsigned NumValues = ValueVTs.size();
1835 if (NumValues == 0) return;
1836
1837 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1838 EVT VT = ValueVTs[j];
1839 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1840
1841 if (attr.hasRetAttr(Attribute::SExt))
1842 ExtendKind = ISD::SIGN_EXTEND;
1843 else if (attr.hasRetAttr(Attribute::ZExt))
1844 ExtendKind = ISD::ZERO_EXTEND;
1845
1846 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1847 VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind);
1848
1849 unsigned NumParts =
1850 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1851 MVT PartVT =
1852 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1853
1854 // 'inreg' on function refers to return value
1856 if (attr.hasRetAttr(Attribute::InReg))
1857 Flags.setInReg();
1858
1859 // Propagate extension type if any
1860 if (attr.hasRetAttr(Attribute::SExt))
1861 Flags.setSExt();
1862 else if (attr.hasRetAttr(Attribute::ZExt))
1863 Flags.setZExt();
1864
1865 for (unsigned i = 0; i < NumParts; ++i) {
1866 ISD::ArgFlagsTy OutFlags = Flags;
1867 if (NumParts > 1 && i == 0)
1868 OutFlags.setSplit();
1869 else if (i == NumParts - 1 && i != 0)
1870 OutFlags.setSplitEnd();
1871
1872 Outs.push_back(
1873 ISD::OutputArg(OutFlags, PartVT, VT, /*isfixed=*/true, 0, 0));
1874 }
1875 }
1876}
1877
1878/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1879/// function arguments in the caller parameter area. This is the actual
1880/// alignment, not its logarithm.
1882 const DataLayout &DL) const {
1883 return DL.getABITypeAlign(Ty).value();
1884}
1885
1887 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace,
1888 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const {
1889 // Check if the specified alignment is sufficient based on the data layout.
1890 // TODO: While using the data layout works in practice, a better solution
1891 // would be to implement this check directly (make this a virtual function).
1892 // For example, the ABI alignment may change based on software platform while
1893 // this function should only be affected by hardware implementation.
1894 Type *Ty = VT.getTypeForEVT(Context);
1895 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) {
1896 // Assume that an access that meets the ABI-specified alignment is fast.
1897 if (Fast != nullptr)
1898 *Fast = 1;
1899 return true;
1900 }
1901
1902 // This is a misaligned access.
1903 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1904}
1905
1907 LLVMContext &Context, const DataLayout &DL, EVT VT,
1908 const MachineMemOperand &MMO, unsigned *Fast) const {
1909 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(),
1910 MMO.getAlign(), MMO.getFlags(), Fast);
1911}
1912
1914 const DataLayout &DL, EVT VT,
1915 unsigned AddrSpace, Align Alignment,
1917 unsigned *Fast) const {
1918 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment,
1919 Flags, Fast);
1920}
1921
1923 const DataLayout &DL, EVT VT,
1924 const MachineMemOperand &MMO,
1925 unsigned *Fast) const {
1926 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1927 MMO.getFlags(), Fast);
1928}
1929
1931 const DataLayout &DL, LLT Ty,
1932 const MachineMemOperand &MMO,
1933 unsigned *Fast) const {
1934 EVT VT = getApproximateEVTForLLT(Ty, DL, Context);
1935 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(),
1936 MMO.getFlags(), Fast);
1937}
1938
1939//===----------------------------------------------------------------------===//
1940// TargetTransformInfo Helpers
1941//===----------------------------------------------------------------------===//
1942
1944 enum InstructionOpcodes {
1945#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1946#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1947#include "llvm/IR/Instruction.def"
1948 };
1949 switch (static_cast<InstructionOpcodes>(Opcode)) {
1950 case Ret: return 0;
1951 case Br: return 0;
1952 case Switch: return 0;
1953 case IndirectBr: return 0;
1954 case Invoke: return 0;
1955 case CallBr: return 0;
1956 case Resume: return 0;
1957 case Unreachable: return 0;
1958 case CleanupRet: return 0;
1959 case CatchRet: return 0;
1960 case CatchPad: return 0;
1961 case CatchSwitch: return 0;
1962 case CleanupPad: return 0;
1963 case FNeg: return ISD::FNEG;
1964 case Add: return ISD::ADD;
1965 case FAdd: return ISD::FADD;
1966 case Sub: return ISD::SUB;
1967 case FSub: return ISD::FSUB;
1968 case Mul: return ISD::MUL;
1969 case FMul: return ISD::FMUL;
1970 case UDiv: return ISD::UDIV;
1971 case SDiv: return ISD::SDIV;
1972 case FDiv: return ISD::FDIV;
1973 case URem: return ISD::UREM;
1974 case SRem: return ISD::SREM;
1975 case FRem: return ISD::FREM;
1976 case Shl: return ISD::SHL;
1977 case LShr: return ISD::SRL;
1978 case AShr: return ISD::SRA;
1979 case And: return ISD::AND;
1980 case Or: return ISD::OR;
1981 case Xor: return ISD::XOR;
1982 case Alloca: return 0;
1983 case Load: return ISD::LOAD;
1984 case Store: return ISD::STORE;
1985 case GetElementPtr: return 0;
1986 case Fence: return 0;
1987 case AtomicCmpXchg: return 0;
1988 case AtomicRMW: return 0;
1989 case Trunc: return ISD::TRUNCATE;
1990 case ZExt: return ISD::ZERO_EXTEND;
1991 case SExt: return ISD::SIGN_EXTEND;
1992 case FPToUI: return ISD::FP_TO_UINT;
1993 case FPToSI: return ISD::FP_TO_SINT;
1994 case UIToFP: return ISD::UINT_TO_FP;
1995 case SIToFP: return ISD::SINT_TO_FP;
1996 case FPTrunc: return ISD::FP_ROUND;
1997 case FPExt: return ISD::FP_EXTEND;
1998 case PtrToInt: return ISD::BITCAST;
1999 case IntToPtr: return ISD::BITCAST;
2000 case BitCast: return ISD::BITCAST;
2001 case AddrSpaceCast: return ISD::ADDRSPACECAST;
2002 case ICmp: return ISD::SETCC;
2003 case FCmp: return ISD::SETCC;
2004 case PHI: return 0;
2005 case Call: return 0;
2006 case Select: return ISD::SELECT;
2007 case UserOp1: return 0;
2008 case UserOp2: return 0;
2009 case VAArg: return 0;
2010 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
2011 case InsertElement: return ISD::INSERT_VECTOR_ELT;
2012 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
2013 case ExtractValue: return ISD::MERGE_VALUES;
2014 case InsertValue: return ISD::MERGE_VALUES;
2015 case LandingPad: return 0;
2016 case Freeze: return ISD::FREEZE;
2017 }
2018
2019 llvm_unreachable("Unknown instruction type encountered!");
2020}
2021
2022Value *
2024 bool UseTLS) const {
2025 // compiler-rt provides a variable with a magic name. Targets that do not
2026 // link with compiler-rt may also provide such a variable.
2027 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2028 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
2029 auto UnsafeStackPtr =
2030 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
2031
2032 Type *StackPtrTy = PointerType::getUnqual(M->getContext());
2033
2034 if (!UnsafeStackPtr) {
2035 auto TLSModel = UseTLS ?
2038 // The global variable is not defined yet, define it ourselves.
2039 // We use the initial-exec TLS model because we do not support the
2040 // variable living anywhere other than in the main executable.
2041 UnsafeStackPtr = new GlobalVariable(
2042 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
2043 UnsafeStackPtrVar, nullptr, TLSModel);
2044 } else {
2045 // The variable exists, check its type and attributes.
2046 if (UnsafeStackPtr->getValueType() != StackPtrTy)
2047 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
2048 if (UseTLS != UnsafeStackPtr->isThreadLocal())
2049 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
2050 (UseTLS ? "" : "not ") + "be thread-local");
2051 }
2052 return UnsafeStackPtr;
2053}
2054
2055Value *
2057 if (!TM.getTargetTriple().isAndroid())
2058 return getDefaultSafeStackPointerLocation(IRB, true);
2059
2060 // Android provides a libc function to retrieve the address of the current
2061 // thread's unsafe stack pointer.
2062 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
2063 auto *PtrTy = PointerType::getUnqual(M->getContext());
2064 FunctionCallee Fn =
2065 M->getOrInsertFunction("__safestack_pointer_address", PtrTy);
2066 return IRB.CreateCall(Fn);
2067}
2068
2069//===----------------------------------------------------------------------===//
2070// Loop Strength Reduction hooks
2071//===----------------------------------------------------------------------===//
2072
2073/// isLegalAddressingMode - Return true if the addressing mode represented
2074/// by AM is legal for this target, for a load/store of the specified type.
2076 const AddrMode &AM, Type *Ty,
2077 unsigned AS, Instruction *I) const {
2078 // The default implementation of this implements a conservative RISCy, r+r and
2079 // r+i addr mode.
2080
2081 // Scalable offsets not supported
2082 if (AM.ScalableOffset)
2083 return false;
2084
2085 // Allows a sign-extended 16-bit immediate field.
2086 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2087 return false;
2088
2089 // No global is ever allowed as a base.
2090 if (AM.BaseGV)
2091 return false;
2092
2093 // Only support r+r,
2094 switch (AM.Scale) {
2095 case 0: // "r+i" or just "i", depending on HasBaseReg.
2096 break;
2097 case 1:
2098 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2099 return false;
2100 // Otherwise we have r+r or r+i.
2101 break;
2102 case 2:
2103 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2104 return false;
2105 // Allow 2*r as r+r.
2106 break;
2107 default: // Don't allow n * r
2108 return false;
2109 }
2110
2111 return true;
2112}
2113
2114//===----------------------------------------------------------------------===//
2115// Stack Protector
2116//===----------------------------------------------------------------------===//
2117
2118// For OpenBSD return its special guard variable. Otherwise return nullptr,
2119// so that SelectionDAG handle SSP.
2121 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
2122 Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
2123 PointerType *PtrTy = PointerType::getUnqual(M.getContext());
2124 Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy);
2125 if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C))
2126 G->setVisibility(GlobalValue::HiddenVisibility);
2127 return C;
2128 }
2129 return nullptr;
2130}
2131
2132// Currently only support "standard" __stack_chk_guard.
2133// TODO: add LOAD_STACK_GUARD support.
2135 if (!M.getNamedValue("__stack_chk_guard")) {
2136 auto *GV = new GlobalVariable(M, PointerType::getUnqual(M.getContext()),
2138 nullptr, "__stack_chk_guard");
2139
2140 // FreeBSD has "__stack_chk_guard" defined externally on libc.so
2141 if (M.getDirectAccessExternalData() &&
2143 !(TM.getTargetTriple().isPPC64() &&
2144 TM.getTargetTriple().isOSFreeBSD()) &&
2145 (!TM.getTargetTriple().isOSDarwin() ||
2147 GV->setDSOLocal(true);
2148 }
2149}
2150
2151// Currently only support "standard" __stack_chk_guard.
2152// TODO: add LOAD_STACK_GUARD support.
2154 return M.getNamedValue("__stack_chk_guard");
2155}
2156
2158 return nullptr;
2159}
2160
2163}
2164
2167}
2168
2169unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
2170 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
2171}
2172
2174 return MaximumJumpTableSize;
2175}
2176
2179}
2180
2183}
2184
2186 if (TM.Options.LoopAlignment)
2187 return Align(TM.Options.LoopAlignment);
2188 return PrefLoopAlignment;
2189}
2190
2192 MachineBasicBlock *MBB) const {
2193 return MaxBytesForAlignment;
2194}
2195
2196//===----------------------------------------------------------------------===//
2197// Reciprocal Estimates
2198//===----------------------------------------------------------------------===//
2199
2200/// Get the reciprocal estimate attribute string for a function that will
2201/// override the target defaults.
2203 const Function &F = MF.getFunction();
2204 return F.getFnAttribute("reciprocal-estimates").getValueAsString();
2205}
2206
2207/// Construct a string for the given reciprocal operation of the given type.
2208/// This string should match the corresponding option to the front-end's
2209/// "-mrecip" flag assuming those strings have been passed through in an
2210/// attribute string. For example, "vec-divf" for a division of a vXf32.
2211static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
2212 std::string Name = VT.isVector() ? "vec-" : "";
2213
2214 Name += IsSqrt ? "sqrt" : "div";
2215
2216 // TODO: Handle other float types?
2217 if (VT.getScalarType() == MVT::f64) {
2218 Name += "d";
2219 } else if (VT.getScalarType() == MVT::f16) {
2220 Name += "h";
2221 } else {
2222 assert(VT.getScalarType() == MVT::f32 &&
2223 "Unexpected FP type for reciprocal estimate");
2224 Name += "f";
2225 }
2226
2227 return Name;
2228}
2229
2230/// Return the character position and value (a single numeric character) of a
2231/// customized refinement operation in the input string if it exists. Return
2232/// false if there is no customized refinement step count.
2233static bool parseRefinementStep(StringRef In, size_t &Position,
2234 uint8_t &Value) {
2235 const char RefStepToken = ':';
2236 Position = In.find(RefStepToken);
2237 if (Position == StringRef::npos)
2238 return false;
2239
2240 StringRef RefStepString = In.substr(Position + 1);
2241 // Allow exactly one numeric character for the additional refinement
2242 // step parameter.
2243 if (RefStepString.size() == 1) {
2244 char RefStepChar = RefStepString[0];
2245 if (isDigit(RefStepChar)) {
2246 Value = RefStepChar - '0';
2247 return true;
2248 }
2249 }
2250 report_fatal_error("Invalid refinement step for -recip.");
2251}
2252
2253/// For the input attribute string, return one of the ReciprocalEstimate enum
2254/// status values (enabled, disabled, or not specified) for this operation on
2255/// the specified data type.
2256static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
2257 if (Override.empty())
2259
2260 SmallVector<StringRef, 4> OverrideVector;
2261 Override.split(OverrideVector, ',');
2262 unsigned NumArgs = OverrideVector.size();
2263
2264 // Check if "all", "none", or "default" was specified.
2265 if (NumArgs == 1) {
2266 // Look for an optional setting of the number of refinement steps needed
2267 // for this type of reciprocal operation.
2268 size_t RefPos;
2269 uint8_t RefSteps;
2270 if (parseRefinementStep(Override, RefPos, RefSteps)) {
2271 // Split the string for further processing.
2272 Override = Override.substr(0, RefPos);
2273 }
2274
2275 // All reciprocal types are enabled.
2276 if (Override == "all")
2278
2279 // All reciprocal types are disabled.
2280 if (Override == "none")
2282
2283 // Target defaults for enablement are used.
2284 if (Override == "default")
2286 }
2287
2288 // The attribute string may omit the size suffix ('f'/'d').
2289 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2290 std::string VTNameNoSize = VTName;
2291 VTNameNoSize.pop_back();
2292 static const char DisabledPrefix = '!';
2293
2294 for (StringRef RecipType : OverrideVector) {
2295 size_t RefPos;
2296 uint8_t RefSteps;
2297 if (parseRefinementStep(RecipType, RefPos, RefSteps))
2298 RecipType = RecipType.substr(0, RefPos);
2299
2300 // Ignore the disablement token for string matching.
2301 bool IsDisabled = RecipType[0] == DisabledPrefix;
2302 if (IsDisabled)
2303 RecipType = RecipType.substr(1);
2304
2305 if (RecipType == VTName || RecipType == VTNameNoSize)
2308 }
2309
2311}
2312
2313/// For the input attribute string, return the customized refinement step count
2314/// for this operation on the specified data type. If the step count does not
2315/// exist, return the ReciprocalEstimate enum value for unspecified.
2316static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
2317 if (Override.empty())
2319
2320 SmallVector<StringRef, 4> OverrideVector;
2321 Override.split(OverrideVector, ',');
2322 unsigned NumArgs = OverrideVector.size();
2323
2324 // Check if "all", "default", or "none" was specified.
2325 if (NumArgs == 1) {
2326 // Look for an optional setting of the number of refinement steps needed
2327 // for this type of reciprocal operation.
2328 size_t RefPos;
2329 uint8_t RefSteps;
2330 if (!parseRefinementStep(Override, RefPos, RefSteps))
2332
2333 // Split the string for further processing.
2334 Override = Override.substr(0, RefPos);
2335 assert(Override != "none" &&
2336 "Disabled reciprocals, but specifed refinement steps?");
2337
2338 // If this is a general override, return the specified number of steps.
2339 if (Override == "all" || Override == "default")
2340 return RefSteps;
2341 }
2342
2343 // The attribute string may omit the size suffix ('f'/'d').
2344 std::string VTName = getReciprocalOpName(IsSqrt, VT);
2345 std::string VTNameNoSize = VTName;
2346 VTNameNoSize.pop_back();
2347
2348 for (StringRef RecipType : OverrideVector) {
2349 size_t RefPos;
2350 uint8_t RefSteps;
2351 if (!parseRefinementStep(RecipType, RefPos, RefSteps))
2352 continue;
2353
2354 RecipType = RecipType.substr(0, RefPos);
2355 if (RecipType == VTName || RecipType == VTNameNoSize)
2356 return RefSteps;
2357 }
2358
2360}
2361
2363 MachineFunction &MF) const {
2364 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
2365}
2366
2368 MachineFunction &MF) const {
2369 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
2370}
2371
2373 MachineFunction &MF) const {
2374 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
2375}
2376
2378 MachineFunction &MF) const {
2379 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
2380}
2381
2383 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG,
2384 const MachineMemOperand &MMO) const {
2385 // Single-element vectors are scalarized, so we should generally avoid having
2386 // any memory operations on such types, as they would get scalarized too.
2387 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() &&
2388 BitcastVT.getVectorNumElements() == 1)
2389 return false;
2390
2391 // Don't do if we could do an indexed load on the original type, but not on
2392 // the new one.
2393 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
2394 return true;
2395
2396 MVT LoadMVT = LoadVT.getSimpleVT();
2397
2398 // Don't bother doing this if it's just going to be promoted again later, as
2399 // doing so might interfere with other combines.
2400 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
2401 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
2402 return false;
2403
2404 unsigned Fast = 0;
2405 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
2406 MMO, &Fast) &&
2407 Fast;
2408}
2409
2412}
2413
2415 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC,
2416 const TargetLibraryInfo *LibInfo) const {
2418 if (LI.isVolatile())
2420
2421 if (LI.hasMetadata(LLVMContext::MD_nontemporal))
2423
2424 if (LI.hasMetadata(LLVMContext::MD_invariant_load))
2426
2428 LI.getAlign(), DL, &LI, AC,
2429 /*DT=*/nullptr, LibInfo))
2431
2432 Flags |= getTargetMMOFlags(LI);
2433 return Flags;
2434}
2435
2438 const DataLayout &DL) const {
2440
2441 if (SI.isVolatile())
2443
2444 if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2446
2447 // FIXME: Not preserving dereferenceable
2448 Flags |= getTargetMMOFlags(SI);
2449 return Flags;
2450}
2451
2454 const DataLayout &DL) const {
2456
2457 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2458 if (RMW->isVolatile())
2460 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) {
2461 if (CmpX->isVolatile())
2463 } else
2464 llvm_unreachable("not an atomic instruction");
2465
2466 // FIXME: Not preserving dereferenceable
2467 Flags |= getTargetMMOFlags(AI);
2468 return Flags;
2469}
2470
2472 Instruction *Inst,
2473 AtomicOrdering Ord) const {
2474 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
2475 return Builder.CreateFence(Ord);
2476 else
2477 return nullptr;
2478}
2479
2481 Instruction *Inst,
2482 AtomicOrdering Ord) const {
2483 if (isAcquireOrStronger(Ord))
2484 return Builder.CreateFence(Ord);
2485 else
2486 return nullptr;
2487}
2488
2489//===----------------------------------------------------------------------===//
2490// GlobalISel Hooks
2491//===----------------------------------------------------------------------===//
2492
2494 const TargetTransformInfo *TTI) const {
2495 auto &MF = *MI.getMF();
2496 auto &MRI = MF.getRegInfo();
2497 // Assuming a spill and reload of a value has a cost of 1 instruction each,
2498 // this helper function computes the maximum number of uses we should consider
2499 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We
2500 // break even in terms of code size when the original MI has 2 users vs
2501 // choosing to potentially spill. Any more than 2 users we we have a net code
2502 // size increase. This doesn't take into account register pressure though.
2503 auto maxUses = [](unsigned RematCost) {
2504 // A cost of 1 means remats are basically free.
2505 if (RematCost == 1)
2506 return std::numeric_limits<unsigned>::max();
2507 if (RematCost == 2)
2508 return 2U;
2509
2510 // Remat is too expensive, only sink if there's one user.
2511 if (RematCost > 2)
2512 return 1U;
2513 llvm_unreachable("Unexpected remat cost");
2514 };
2515
2516 switch (MI.getOpcode()) {
2517 default:
2518 return false;
2519 // Constants-like instructions should be close to their users.
2520 // We don't want long live-ranges for them.
2521 case TargetOpcode::G_CONSTANT:
2522 case TargetOpcode::G_FCONSTANT:
2523 case TargetOpcode::G_FRAME_INDEX:
2524 case TargetOpcode::G_INTTOPTR:
2525 return true;
2526 case TargetOpcode::G_GLOBAL_VALUE: {
2527 unsigned RematCost = TTI->getGISelRematGlobalCost();
2528 Register Reg = MI.getOperand(0).getReg();
2529 unsigned MaxUses = maxUses(RematCost);
2530 if (MaxUses == UINT_MAX)
2531 return true; // Remats are "free" so always localize.
2532 return MRI.hasAtMostUserInstrs(Reg, MaxUses);
2533 }
2534 }
2535}
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
Rewrite undef for PHI
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
return RetTy
std::string Name
IRTranslator LLVM IR MI
#define LCALL5(A)
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
#define G(x, y, z)
Definition: MD5.cpp:56
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
ConstantRange Range(APInt(BitWidth, Low), APInt(BitWidth, High))
const char LLVMTargetMachineRef TM
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallVector class.
This file contains some functions that are useful when dealing with strings.
static bool darwinHasSinCos(const Triple &TT)
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
#define OP_TO_LIBCALL(Name, Enum)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
This file describes how to lower LLVM code to machine code.
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition: APInt.h:77
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
Definition: Instructions.h:540
an instruction that atomically reads a memory location, combines it with another value,...
Definition: Instructions.h:749
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
Definition: Attributes.h:803
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:208
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
Definition: BitVector.h:707
iterator_range< const_set_bits_iterator > set_bits() const
Definition: BitVector.h:140
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
This class represents a range of values.
Definition: ConstantRange.h:47
unsigned getActiveBits() const
Compute the maximal number of active bits needed to represent every value in this range.
ConstantRange umul_sat(const ConstantRange &Other) const
Perform an unsigned saturating multiplication of two constant ranges.
ConstantRange subtract(const APInt &CI) const
Subtract the specified constant from the endpoints of this constant range.
This is an important base class in LLVM.
Definition: Constant.h:41
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
Definition: DataLayout.cpp:750
static constexpr ElementCount getScalable(ScalarTy MinVal)
Definition: TypeSize.h:311
static constexpr ElementCount getFixed(ScalarTy MinVal)
Definition: TypeSize.h:308
constexpr bool isScalar() const
Exactly one element.
Definition: TypeSize.h:319
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:168
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:655
@ HiddenVisibility
The GV is hidden.
Definition: GlobalValue.h:67
@ ExternalLinkage
Externally visible function.
Definition: GlobalValue.h:51
Common base class shared among various IRBuilders.
Definition: IRBuilder.h:94
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
Definition: IRBuilder.h:1834
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:174
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=std::nullopt, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2412
bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
Definition: Instruction.h:340
@ MAX_INT_BITS
Maximum number of bits that can be specified.
Definition: DerivedTypes.h:52
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:185
Value * getPointerOperand()
Definition: Instructions.h:281
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Definition: Instructions.h:231
Align getAlign() const
Return the alignment of the access that is being performed.
Definition: Instructions.h:237
Machine Value Type.
SimpleValueType SimpleTy
uint64_t getScalarSizeInBits() const
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static auto all_valuetypes()
SimpleValueType Iteration.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
ElementCount getVectorElementCount() const
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
Definition: MachineInstr.h:69
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:569
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
A description of a memory reference used in the backend.
unsigned getAddrSpace() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
Class to represent pointers.
Definition: DerivedTypes.h:646
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Definition: DerivedTypes.h:662
Analysis providing profile information.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:227
const DataLayout & getDataLayout() const
Definition: SelectionDAG.h:486
LLVMContext * getContext() const
Definition: SelectionDAG.h:499
size_t size() const
Definition: SmallVector.h:91
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:318
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:693
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:564
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
static constexpr size_t npos
Definition: StringRef.h:52
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Multiway switch.
Provides information about what library functions are available for the current target.
LegalizeTypeAction getTypeAction(MVT VT) const
void setTypeAction(MVT VT, LegalizeTypeAction Action)
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
void initActions()
Initialize all of the actions to default values.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
const TargetMachine & getTargetMachine() const
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual bool useFPRegsForHalfType() const
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
virtual bool softPromoteHalfType() const
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const
Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Let target indicate that an extending atomic load of the specified type is legal.
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual bool isJumpTableRelative() const
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to.
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
bool isPositionIndependent() const
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
TargetOptions Options
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
unsigned getGISelRematGlobalCost() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isWindowsGNUEnvironment() const
Definition: Triple.h:657
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:769
@ aarch64_32
Definition: Triple.h:53
bool isOSFreeBSD() const
Definition: Triple.h:584
bool isPPC64() const
Tests whether the target is 64-bit PowerPC (little and big endian).
Definition: Triple.h:964
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Definition: Triple.h:558
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
constexpr LeafTy coefficientNextPowerOf2() const
Definition: TypeSize.h:259
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
Definition: TypeSize.h:168
constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
Definition: TypeSize.h:251
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ ARM_AAPCS_VFP
Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:114
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:40
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:758
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:237
@ CTLZ_ZERO_UNDEF
Definition: ISDOpcodes.h:731
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
Definition: ISDOpcodes.h:44
@ SET_FPENV
Sets the current floating-point environment.
Definition: ISDOpcodes.h:1013
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
Definition: ISDOpcodes.h:1354
@ VECREDUCE_SMIN
Definition: ISDOpcodes.h:1385
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:499
@ ATOMIC_LOAD_NAND
Definition: ISDOpcodes.h:1284
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:368
@ ConstantFP
Definition: ISDOpcodes.h:77
@ ATOMIC_LOAD_MAX
Definition: ISDOpcodes.h:1286
@ ATOMIC_LOAD_UMIN
Definition: ISDOpcodes.h:1287
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:270
@ RESET_FPENV
Set floating-point environment to default state.
Definition: ISDOpcodes.h:1017
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
Definition: ISDOpcodes.h:489
@ FMAXNUM_IEEE
Definition: ISDOpcodes.h:994
@ ADD
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:240
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:1046
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:374
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1036
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:791
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:1269
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:798
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:545
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:1370
@ FADD
Simple binary floating point operators.
Definition: ISDOpcodes.h:391
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
Definition: ISDOpcodes.h:1374
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
Definition: ISDOpcodes.h:696
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
Definition: ISDOpcodes.h:1040
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:828
@ VECREDUCE_SMAX
Definition: ISDOpcodes.h:1384
@ ATOMIC_LOAD_OR
Definition: ISDOpcodes.h:1282
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:911
@ ATOMIC_LOAD_XOR
Definition: ISDOpcodes.h:1283
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
Definition: ISDOpcodes.h:948
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
Definition: ISDOpcodes.h:381
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1425
@ SIGN_EXTEND
Conversion operators.
Definition: ISDOpcodes.h:782
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
Definition: ISDOpcodes.h:664
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
Definition: ISDOpcodes.h:1203
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
Definition: ISDOpcodes.h:1367
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:730
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:1236
@ VECREDUCE_FMIN
Definition: ISDOpcodes.h:1371
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:766
@ FNEG
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:938
@ SSUBO
Same for subtraction.
Definition: ISDOpcodes.h:328
@ ATOMIC_LOAD_MIN
Definition: ISDOpcodes.h:1285
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
Definition: ISDOpcodes.h:509
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:350
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:735
@ VECREDUCE_UMAX
Definition: ISDOpcodes.h:1386
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
Definition: ISDOpcodes.h:629
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:324
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:1379
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
Definition: ISDOpcodes.h:1031
@ GET_FPENV
Gets the current floating-point environment.
Definition: ISDOpcodes.h:1008
@ SHL
Shift and rotation operations.
Definition: ISDOpcodes.h:713
@ ATOMIC_LOAD_CLR
Definition: ISDOpcodes.h:1281
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:602
@ ATOMIC_LOAD_AND
Definition: ISDOpcodes.h:1280
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
Definition: ISDOpcodes.h:993
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:537
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:788
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:1226
@ FP_TO_UINT_SAT
Definition: ISDOpcodes.h:864
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
Definition: ISDOpcodes.h:1263
@ ATOMIC_LOAD_UMAX
Definition: ISDOpcodes.h:1288
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:980
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
Definition: ISDOpcodes.h:1230
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
Definition: ISDOpcodes.h:360
@ SMULO
Same for multiplication.
Definition: ISDOpcodes.h:332
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:817
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
Definition: ISDOpcodes.h:806
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
Definition: ISDOpcodes.h:676
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:387
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:896
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:304
@ VECREDUCE_UMIN
Definition: ISDOpcodes.h:1387
@ ATOMIC_LOAD_ADD
Definition: ISDOpcodes.h:1278
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
Definition: ISDOpcodes.h:999
@ ATOMIC_LOAD_SUB
Definition: ISDOpcodes.h:1279
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:844
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:1197
@ AND
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:688
@ TRAP
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:1223
@ GET_FPENV_MEM
Gets the current floating-point environment.
Definition: ISDOpcodes.h:1022
@ SCMP
[US]CMP - 3-way comparison of signed or unsigned integers.
Definition: ISDOpcodes.h:684
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
Definition: ISDOpcodes.h:659
@ VECREDUCE_FMUL
Definition: ISDOpcodes.h:1368
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:280
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
Definition: ISDOpcodes.h:526
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
Definition: ISDOpcodes.h:614
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
Definition: ISDOpcodes.h:1277
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
Definition: ISDOpcodes.h:953
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:877
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:839
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:915
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
Definition: ISDOpcodes.h:863
@ VECREDUCE_FMINIMUM
Definition: ISDOpcodes.h:1375
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:794
@ VECREDUCE_SEQ_FMUL
Definition: ISDOpcodes.h:1355
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:495
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:341
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
Definition: ISDOpcodes.h:1335
@ SET_FPENV_MEM
Sets the current floating point environment.
Definition: ISDOpcodes.h:1027
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:314
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Definition: ISDOpcodes.h:1548
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:1499
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Libcall getLDEXP(EVT RetVT)
getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFREXP(EVT RetVT)
getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)
Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
Definition: MathExtras.h:337
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:431
auto enum_seq(EnumT Begin, EnumT End)
Iterate over an enum type from Begin up to - but not including - End.
Definition: Sequence.h:337
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
Definition: Loads.cpp:201
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum
Definition: Sequence.h:108
T bit_ceil(T Value)
Returns the smallest integral power of two no smaller than Value if Value is nonzero.
Definition: bit.h:342
bool isReleaseOrStronger(AtomicOrdering AO)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:275
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1736
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
@ Xor
Bitwise or logical XOR of integers.
@ FMul
Product of floats.
@ And
Bitwise or logical AND of integers.
@ Add
Sum of integers.
@ FAdd
Sum of floats.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:79
bool isAcquireOrStronger(AtomicOrdering AO)
InstructionCost Cost
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Extended Value Type.
Definition: ValueTypes.h:34
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
Definition: ValueTypes.h:462
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:136
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
Definition: ValueTypes.h:73
ElementCount getVectorElementCount() const
Definition: ValueTypes.h:340
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:358
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:455
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:306
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:64
bool isFixedLengthVector() const
Definition: ValueTypes.h:177
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
Definition: ValueTypes.h:404
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:167
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:313
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:203
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:318
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:326
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
Definition: ValueTypes.h:131
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
Definition: ValueTypes.h:438
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:151
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...