69 "jump-is-expensive",
cl::init(
false),
70 cl::desc(
"Do not create extra branches to split comparison logic."),
75 cl::desc(
"Set minimum number of entries to use a jump table."));
79 cl::desc(
"Set maximum size of jump tables."));
84 cl::desc(
"Minimum density for building a jump table in "
85 "a normal function"));
90 cl::desc(
"Minimum density for building a jump table in "
91 "an optsize function"));
98 cl::desc(
"Don't mutate strict-float node to a legalize node"),
102 assert(TT.isOSDarwin() &&
"should be called with darwin triple");
108 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
111 return !TT.isOSVersionLT(7, 0);
116void TargetLoweringBase::InitLibcalls(
const Triple &TT) {
117#define HANDLE_LIBCALL(code, name) \
118 setLibcallName(RTLIB::code, name);
119#include "llvm/IR/RuntimeLibcalls.def"
122 for (
int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
198 if (
TT.isOSDarwin()) {
206 switch (
TT.getArch()) {
209 if (
TT.isMacOSX() && !
TT.isMacOSXVersionLT(10, 6))
223 if (
TT.isWatchABI()) {
235 if (
TT.isGNUEnvironment() ||
TT.isOSFuchsia() ||
236 (
TT.isAndroid() && !
TT.isAndroidVersionLT(9))) {
249 if (
TT.isOSOpenBSD()) {
253 if (
TT.isOSWindows() && !
TT.isOSCygMing()) {
275 VT == MVT::f32 ? Call_F32 :
276 VT == MVT::f64 ? Call_F64 :
277 VT == MVT::f80 ? Call_F80 :
278 VT == MVT::f128 ? Call_F128 :
279 VT == MVT::ppcf128 ? Call_PPCF128 :
280 RTLIB::UNKNOWN_LIBCALL;
286 if (OpVT == MVT::f16) {
287 if (RetVT == MVT::f32)
288 return FPEXT_F16_F32;
289 if (RetVT == MVT::f64)
290 return FPEXT_F16_F64;
291 if (RetVT == MVT::f80)
292 return FPEXT_F16_F80;
293 if (RetVT == MVT::f128)
294 return FPEXT_F16_F128;
295 }
else if (OpVT == MVT::f32) {
296 if (RetVT == MVT::f64)
297 return FPEXT_F32_F64;
298 if (RetVT == MVT::f128)
299 return FPEXT_F32_F128;
300 if (RetVT == MVT::ppcf128)
301 return FPEXT_F32_PPCF128;
302 }
else if (OpVT == MVT::f64) {
303 if (RetVT == MVT::f128)
304 return FPEXT_F64_F128;
305 else if (RetVT == MVT::ppcf128)
306 return FPEXT_F64_PPCF128;
307 }
else if (OpVT == MVT::f80) {
308 if (RetVT == MVT::f128)
309 return FPEXT_F80_F128;
310 }
else if (OpVT == MVT::bf16) {
311 if (RetVT == MVT::f32)
312 return FPEXT_BF16_F32;
315 return UNKNOWN_LIBCALL;
321 if (RetVT == MVT::f16) {
322 if (OpVT == MVT::f32)
323 return FPROUND_F32_F16;
324 if (OpVT == MVT::f64)
325 return FPROUND_F64_F16;
326 if (OpVT == MVT::f80)
327 return FPROUND_F80_F16;
328 if (OpVT == MVT::f128)
329 return FPROUND_F128_F16;
330 if (OpVT == MVT::ppcf128)
331 return FPROUND_PPCF128_F16;
332 }
else if (RetVT == MVT::bf16) {
333 if (OpVT == MVT::f32)
334 return FPROUND_F32_BF16;
335 if (OpVT == MVT::f64)
336 return FPROUND_F64_BF16;
337 }
else if (RetVT == MVT::f32) {
338 if (OpVT == MVT::f64)
339 return FPROUND_F64_F32;
340 if (OpVT == MVT::f80)
341 return FPROUND_F80_F32;
342 if (OpVT == MVT::f128)
343 return FPROUND_F128_F32;
344 if (OpVT == MVT::ppcf128)
345 return FPROUND_PPCF128_F32;
346 }
else if (RetVT == MVT::f64) {
347 if (OpVT == MVT::f80)
348 return FPROUND_F80_F64;
349 if (OpVT == MVT::f128)
350 return FPROUND_F128_F64;
351 if (OpVT == MVT::ppcf128)
352 return FPROUND_PPCF128_F64;
353 }
else if (RetVT == MVT::f80) {
354 if (OpVT == MVT::f128)
355 return FPROUND_F128_F80;
358 return UNKNOWN_LIBCALL;
364 if (OpVT == MVT::f16) {
365 if (RetVT == MVT::i32)
366 return FPTOSINT_F16_I32;
367 if (RetVT == MVT::i64)
368 return FPTOSINT_F16_I64;
369 if (RetVT == MVT::i128)
370 return FPTOSINT_F16_I128;
371 }
else if (OpVT == MVT::f32) {
372 if (RetVT == MVT::i32)
373 return FPTOSINT_F32_I32;
374 if (RetVT == MVT::i64)
375 return FPTOSINT_F32_I64;
376 if (RetVT == MVT::i128)
377 return FPTOSINT_F32_I128;
378 }
else if (OpVT == MVT::f64) {
379 if (RetVT == MVT::i32)
380 return FPTOSINT_F64_I32;
381 if (RetVT == MVT::i64)
382 return FPTOSINT_F64_I64;
383 if (RetVT == MVT::i128)
384 return FPTOSINT_F64_I128;
385 }
else if (OpVT == MVT::f80) {
386 if (RetVT == MVT::i32)
387 return FPTOSINT_F80_I32;
388 if (RetVT == MVT::i64)
389 return FPTOSINT_F80_I64;
390 if (RetVT == MVT::i128)
391 return FPTOSINT_F80_I128;
392 }
else if (OpVT == MVT::f128) {
393 if (RetVT == MVT::i32)
394 return FPTOSINT_F128_I32;
395 if (RetVT == MVT::i64)
396 return FPTOSINT_F128_I64;
397 if (RetVT == MVT::i128)
398 return FPTOSINT_F128_I128;
399 }
else if (OpVT == MVT::ppcf128) {
400 if (RetVT == MVT::i32)
401 return FPTOSINT_PPCF128_I32;
402 if (RetVT == MVT::i64)
403 return FPTOSINT_PPCF128_I64;
404 if (RetVT == MVT::i128)
405 return FPTOSINT_PPCF128_I128;
407 return UNKNOWN_LIBCALL;
413 if (OpVT == MVT::f16) {
414 if (RetVT == MVT::i32)
415 return FPTOUINT_F16_I32;
416 if (RetVT == MVT::i64)
417 return FPTOUINT_F16_I64;
418 if (RetVT == MVT::i128)
419 return FPTOUINT_F16_I128;
420 }
else if (OpVT == MVT::f32) {
421 if (RetVT == MVT::i32)
422 return FPTOUINT_F32_I32;
423 if (RetVT == MVT::i64)
424 return FPTOUINT_F32_I64;
425 if (RetVT == MVT::i128)
426 return FPTOUINT_F32_I128;
427 }
else if (OpVT == MVT::f64) {
428 if (RetVT == MVT::i32)
429 return FPTOUINT_F64_I32;
430 if (RetVT == MVT::i64)
431 return FPTOUINT_F64_I64;
432 if (RetVT == MVT::i128)
433 return FPTOUINT_F64_I128;
434 }
else if (OpVT == MVT::f80) {
435 if (RetVT == MVT::i32)
436 return FPTOUINT_F80_I32;
437 if (RetVT == MVT::i64)
438 return FPTOUINT_F80_I64;
439 if (RetVT == MVT::i128)
440 return FPTOUINT_F80_I128;
441 }
else if (OpVT == MVT::f128) {
442 if (RetVT == MVT::i32)
443 return FPTOUINT_F128_I32;
444 if (RetVT == MVT::i64)
445 return FPTOUINT_F128_I64;
446 if (RetVT == MVT::i128)
447 return FPTOUINT_F128_I128;
448 }
else if (OpVT == MVT::ppcf128) {
449 if (RetVT == MVT::i32)
450 return FPTOUINT_PPCF128_I32;
451 if (RetVT == MVT::i64)
452 return FPTOUINT_PPCF128_I64;
453 if (RetVT == MVT::i128)
454 return FPTOUINT_PPCF128_I128;
456 return UNKNOWN_LIBCALL;
462 if (OpVT == MVT::i32) {
463 if (RetVT == MVT::f16)
464 return SINTTOFP_I32_F16;
465 if (RetVT == MVT::f32)
466 return SINTTOFP_I32_F32;
467 if (RetVT == MVT::f64)
468 return SINTTOFP_I32_F64;
469 if (RetVT == MVT::f80)
470 return SINTTOFP_I32_F80;
471 if (RetVT == MVT::f128)
472 return SINTTOFP_I32_F128;
473 if (RetVT == MVT::ppcf128)
474 return SINTTOFP_I32_PPCF128;
475 }
else if (OpVT == MVT::i64) {
476 if (RetVT == MVT::f16)
477 return SINTTOFP_I64_F16;
478 if (RetVT == MVT::f32)
479 return SINTTOFP_I64_F32;
480 if (RetVT == MVT::f64)
481 return SINTTOFP_I64_F64;
482 if (RetVT == MVT::f80)
483 return SINTTOFP_I64_F80;
484 if (RetVT == MVT::f128)
485 return SINTTOFP_I64_F128;
486 if (RetVT == MVT::ppcf128)
487 return SINTTOFP_I64_PPCF128;
488 }
else if (OpVT == MVT::i128) {
489 if (RetVT == MVT::f16)
490 return SINTTOFP_I128_F16;
491 if (RetVT == MVT::f32)
492 return SINTTOFP_I128_F32;
493 if (RetVT == MVT::f64)
494 return SINTTOFP_I128_F64;
495 if (RetVT == MVT::f80)
496 return SINTTOFP_I128_F80;
497 if (RetVT == MVT::f128)
498 return SINTTOFP_I128_F128;
499 if (RetVT == MVT::ppcf128)
500 return SINTTOFP_I128_PPCF128;
502 return UNKNOWN_LIBCALL;
508 if (OpVT == MVT::i32) {
509 if (RetVT == MVT::f16)
510 return UINTTOFP_I32_F16;
511 if (RetVT == MVT::f32)
512 return UINTTOFP_I32_F32;
513 if (RetVT == MVT::f64)
514 return UINTTOFP_I32_F64;
515 if (RetVT == MVT::f80)
516 return UINTTOFP_I32_F80;
517 if (RetVT == MVT::f128)
518 return UINTTOFP_I32_F128;
519 if (RetVT == MVT::ppcf128)
520 return UINTTOFP_I32_PPCF128;
521 }
else if (OpVT == MVT::i64) {
522 if (RetVT == MVT::f16)
523 return UINTTOFP_I64_F16;
524 if (RetVT == MVT::f32)
525 return UINTTOFP_I64_F32;
526 if (RetVT == MVT::f64)
527 return UINTTOFP_I64_F64;
528 if (RetVT == MVT::f80)
529 return UINTTOFP_I64_F80;
530 if (RetVT == MVT::f128)
531 return UINTTOFP_I64_F128;
532 if (RetVT == MVT::ppcf128)
533 return UINTTOFP_I64_PPCF128;
534 }
else if (OpVT == MVT::i128) {
535 if (RetVT == MVT::f16)
536 return UINTTOFP_I128_F16;
537 if (RetVT == MVT::f32)
538 return UINTTOFP_I128_F32;
539 if (RetVT == MVT::f64)
540 return UINTTOFP_I128_F64;
541 if (RetVT == MVT::f80)
542 return UINTTOFP_I128_F80;
543 if (RetVT == MVT::f128)
544 return UINTTOFP_I128_F128;
545 if (RetVT == MVT::ppcf128)
546 return UINTTOFP_I128_PPCF128;
548 return UNKNOWN_LIBCALL;
552 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128,
557 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128,
562 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128,
569 unsigned ModeN, ModelN;
587 return RTLIB::UNKNOWN_LIBCALL;
605 return UNKNOWN_LIBCALL;
608 return LC[ModeN][ModelN];
614 return UNKNOWN_LIBCALL;
617#define LCALLS(A, B) \
618 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
620 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
647 return UNKNOWN_LIBCALL;
654#define OP_TO_LIBCALL(Name, Enum) \
656 switch (VT.SimpleTy) { \
658 return UNKNOWN_LIBCALL; \
688 return UNKNOWN_LIBCALL;
692 switch (ElementSize) {
694 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
696 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
698 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
700 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
702 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
704 return UNKNOWN_LIBCALL;
709 switch (ElementSize) {
711 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
713 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
715 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
717 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
719 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
721 return UNKNOWN_LIBCALL;
726 switch (ElementSize) {
728 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
730 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
732 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
734 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
736 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
738 return UNKNOWN_LIBCALL;
785 HasMultipleConditionRegisters =
false;
786 HasExtractBitsInsn =
false;
790 StackPointerRegisterToSaveRestore = 0;
797 MaxBytesForAlignment = 0;
798 MaxAtomicSizeInBitsSupported = 0;
802 MaxDivRemBitWidthSupported = 128;
806 MinCmpXchgSizeInBits = 0;
807 SupportsUnalignedAtomics =
false;
809 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames),
nullptr);
817 memset(OpActions, 0,
sizeof(OpActions));
818 memset(LoadExtActions, 0,
sizeof(LoadExtActions));
819 memset(TruncStoreActions, 0,
sizeof(TruncStoreActions));
820 memset(IndexedModeActions, 0,
sizeof(IndexedModeActions));
821 memset(CondCodeActions, 0,
sizeof(CondCodeActions));
822 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT),
nullptr);
823 std::fill(std::begin(TargetDAGCombineArray),
824 std::end(TargetDAGCombineArray), 0);
830 for (
MVT VT : {MVT::i2, MVT::i4})
831 OpActions[(
unsigned)VT.SimpleTy][NT] =
Expand;
834 for (
MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) {
842 for (
MVT VT : {MVT::i2, MVT::i4}) {
933#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
934 setOperationAction(ISD::STRICT_##DAGN, VT, Expand);
935#include "llvm/IR/ConstrainedOps.def"
954#define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \
955 setOperationAction(ISD::SDOPC, VT, Expand);
956#include "llvm/IR/VPIntrinsics.def"
977 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128},
985 {MVT::f32, MVT::f64, MVT::f128},
Expand);
999 for (
MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1012 bool LegalTypes)
const {
1023 "ShiftVT is still too small!");
1041 unsigned DestAS)
const {
1048 JumpIsExpensive = isExpensive;
1064 "Promote may not follow Expand or Promote");
1080 assert(NVT != VT &&
"Unable to round integer VT");
1129 EVT OldEltVT = EltVT;
1168 if (LargerVector ==
MVT())
1192 unsigned &NumIntermediates,
1199 unsigned NumVectorRegs = 1;
1205 "Splitting or widening of non-power-of-2 MVTs is not implemented.");
1211 NumVectorRegs = EC.getKnownMinValue();
1218 while (EC.getKnownMinValue() > 1 &&
1220 EC = EC.divideCoefficientBy(2);
1221 NumVectorRegs <<= 1;
1224 NumIntermediates = NumVectorRegs;
1229 IntermediateVT = NewVT;
1237 RegisterVT = DestVT;
1238 if (
EVT(DestVT).bitsLT(NewVT))
1243 return NumVectorRegs;
1250 for (
const auto *
I =
TRI.legalclasstypes_begin(RC); *
I != MVT::Other; ++
I)
1286 for (
unsigned i = 0; i <
MI->getNumOperands(); ++i) {
1293 unsigned TiedTo = i;
1295 TiedTo =
MI->findTiedOperandIdx(i);
1312 assert(
MI->getOpcode() == TargetOpcode::STATEPOINT &&
"sanity");
1313 MIB.
addImm(StackMaps::IndirectMemRefOp);
1320 MIB.
addImm(StackMaps::DirectMemRefOp);
1325 assert(MIB->
mayLoad() &&
"Folded a stackmap use to a non-load!");
1332 if (
MI->getOpcode() != TargetOpcode::STATEPOINT) {
1341 MI->eraseFromParent();
1351std::pair<const TargetRegisterClass *, uint8_t>
1356 return std::make_pair(RC, 0);
1365 for (
unsigned i : SuperRegRC.
set_bits()) {
1368 if (
TRI->getSpillSize(*SuperRC) <=
TRI->getSpillSize(*BestRC))
1374 return std::make_pair(BestRC, 1);
1382 "Too many value types for ValueTypeActions to hold!");
1386 NumRegistersForVT[i] = 1;
1390 NumRegistersForVT[MVT::isVoid] = 0;
1393 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1394 for (; RegClassForVT[LargestIntReg] ==
nullptr; --LargestIntReg)
1395 assert(LargestIntReg != MVT::i1 &&
"No integer registers defined!");
1399 for (
unsigned ExpandedReg = LargestIntReg + 1;
1400 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1401 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1410 unsigned LegalIntReg = LargestIntReg;
1411 for (
unsigned IntReg = LargestIntReg - 1;
1412 IntReg >= (
unsigned)MVT::i1; --IntReg) {
1415 LegalIntReg = IntReg;
1417 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1426 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1427 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1428 TransformToType[MVT::ppcf128] = MVT::f64;
1431 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1432 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1433 TransformToType[MVT::ppcf128] = MVT::i128;
1441 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1442 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1443 TransformToType[MVT::f128] = MVT::i128;
1450 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32];
1451 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32];
1452 TransformToType[MVT::f80] = MVT::i32;
1459 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1460 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1461 TransformToType[MVT::f64] = MVT::i64;
1468 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1469 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1470 TransformToType[MVT::f32] = MVT::i32;
1482 if (!UseFPRegsForHalfType) {
1483 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1484 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1486 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1487 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1489 TransformToType[MVT::f16] = MVT::f32;
1490 if (SoftPromoteHalfType) {
1501 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32];
1502 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32];
1503 TransformToType[MVT::bf16] = MVT::f32;
1508 for (
unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1509 i <= (
unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1516 bool IsLegalWiderType =
false;
1519 switch (PreferredAction) {
1522 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE :
1523 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE;
1526 for (
unsigned nVT = i + 1;
1533 TransformToType[i] = SVT;
1534 RegisterTypeForVT[i] = SVT;
1535 NumRegistersForVT[i] = 1;
1537 IsLegalWiderType =
true;
1541 if (IsLegalWiderType)
1549 for (
unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1554 EC.getKnownMinValue() &&
1556 TransformToType[i] = SVT;
1557 RegisterTypeForVT[i] = SVT;
1558 NumRegistersForVT[i] = 1;
1560 IsLegalWiderType =
true;
1564 if (IsLegalWiderType)
1570 TransformToType[i] = NVT;
1572 RegisterTypeForVT[i] = NVT;
1573 NumRegistersForVT[i] = 1;
1583 unsigned NumIntermediates;
1585 NumIntermediates, RegisterVT,
this);
1586 NumRegistersForVT[i] = NumRegisters;
1587 assert(NumRegistersForVT[i] == NumRegisters &&
1588 "NumRegistersForVT size cannot represent NumRegisters!");
1589 RegisterTypeForVT[i] = RegisterVT;
1594 TransformToType[i] = MVT::Other;
1599 else if (EC.getKnownMinValue() > 1)
1606 TransformToType[i] = NVT;
1625 RepRegClassForVT[i] = RRC;
1626 RepRegClassCostForVT[i] =
Cost;
1649 EVT VT,
EVT &IntermediateVT,
1650 unsigned &NumIntermediates,
1651 MVT &RegisterVT)
const {
1664 IntermediateVT = RegisterEVT;
1666 NumIntermediates = 1;
1674 unsigned NumVectorRegs = 1;
1689 "Don't know how to legalize this scalable vector type");
1695 IntermediateVT = PartVT;
1697 return NumIntermediates;
1712 NumVectorRegs <<= 1;
1715 NumIntermediates = NumVectorRegs;
1720 IntermediateVT = NewVT;
1723 RegisterVT = DestVT;
1725 if (
EVT(DestVT).bitsLT(NewVT)) {
1735 return NumVectorRegs;
1748 const bool OptForSize =
1749 SI->getParent()->getParent()->hasOptSize() ||
1756 return (OptForSize || Range <= MaxJumpTableSize) &&
1757 (NumCases * 100 >= Range * MinDensity);
1761 EVT ConditionVT)
const {
1775 unsigned NumValues = ValueVTs.
size();
1776 if (NumValues == 0)
return;
1778 for (
unsigned j = 0, f = NumValues; j != f; ++j) {
1779 EVT VT = ValueVTs[j];
1806 for (
unsigned i = 0; i < NumParts; ++i)
1816 return DL.getABITypeAlign(Ty).value();
1828 if (VT.
isZeroSized() || Alignment >=
DL.getABITypeAlign(Ty)) {
1830 if (
Fast !=
nullptr)
1848 unsigned AddrSpace,
Align Alignment,
1850 unsigned *
Fast)
const {
1858 unsigned *
Fast)
const {
1866 unsigned *
Fast)
const {
1877 enum InstructionOpcodes {
1878#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1879#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1880#include "llvm/IR/Instruction.def"
1882 switch (
static_cast<InstructionOpcodes
>(Opcode)) {
1885 case Switch:
return 0;
1886 case IndirectBr:
return 0;
1887 case Invoke:
return 0;
1888 case CallBr:
return 0;
1889 case Resume:
return 0;
1890 case Unreachable:
return 0;
1891 case CleanupRet:
return 0;
1892 case CatchRet:
return 0;
1893 case CatchPad:
return 0;
1894 case CatchSwitch:
return 0;
1895 case CleanupPad:
return 0;
1915 case Alloca:
return 0;
1918 case GetElementPtr:
return 0;
1919 case Fence:
return 0;
1920 case AtomicCmpXchg:
return 0;
1921 case AtomicRMW:
return 0;
1938 case Call:
return 0;
1940 case UserOp1:
return 0;
1941 case UserOp2:
return 0;
1942 case VAArg:
return 0;
1948 case LandingPad:
return 0;
1957 bool UseTLS)
const {
1961 const char *UnsafeStackPtrVar =
"__safestack_unsafe_stack_ptr";
1962 auto UnsafeStackPtr =
1963 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1967 if (!UnsafeStackPtr) {
1968 auto TLSModel = UseTLS ?
1976 UnsafeStackPtrVar,
nullptr, TLSModel);
1979 if (UnsafeStackPtr->getValueType() != StackPtrTy)
1981 if (UseTLS != UnsafeStackPtr->isThreadLocal())
1983 (UseTLS ?
"" :
"not ") +
"be thread-local");
1985 return UnsafeStackPtr;
1998 M->getOrInsertFunction(
"__safestack_pointer_address", PtrTy);
2053 Constant *
C = M.getOrInsertGlobal(
"__guard_local", PtrTy);
2064 if (!M.getNamedValue(
"__stack_chk_guard")) {
2067 nullptr,
"__stack_chk_guard");
2070 if (M.getDirectAccessExternalData() &&
2075 GV->setDSOLocal(
true);
2082 return M.getNamedValue(
"__stack_chk_guard");
2116 return PrefLoopAlignment;
2121 return MaxBytesForAlignment;
2132 return F.getFnAttribute(
"reciprocal-estimates").getValueAsString();
2142 Name += IsSqrt ?
"sqrt" :
"div";
2151 "Unexpected FP type for reciprocal estimate");
2163 const char RefStepToken =
':';
2164 Position = In.find(RefStepToken);
2168 StringRef RefStepString = In.substr(Position + 1);
2171 if (RefStepString.
size() == 1) {
2172 char RefStepChar = RefStepString[0];
2174 Value = RefStepChar -
'0';
2185 if (Override.
empty())
2189 Override.
split(OverrideVector,
',');
2190 unsigned NumArgs = OverrideVector.
size();
2200 Override = Override.
substr(0, RefPos);
2204 if (Override ==
"all")
2208 if (Override ==
"none")
2212 if (Override ==
"default")
2218 std::string VTNameNoSize = VTName;
2219 VTNameNoSize.pop_back();
2220 static const char DisabledPrefix =
'!';
2222 for (
StringRef RecipType : OverrideVector) {
2226 RecipType = RecipType.substr(0, RefPos);
2229 bool IsDisabled = RecipType[0] == DisabledPrefix;
2231 RecipType = RecipType.substr(1);
2233 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2245 if (Override.
empty())
2249 Override.
split(OverrideVector,
',');
2250 unsigned NumArgs = OverrideVector.
size();
2262 Override = Override.
substr(0, RefPos);
2263 assert(Override !=
"none" &&
2264 "Disabled reciprocals, but specifed refinement steps?");
2267 if (Override ==
"all" || Override ==
"default")
2273 std::string VTNameNoSize = VTName;
2274 VTNameNoSize.pop_back();
2276 for (
StringRef RecipType : OverrideVector) {
2282 RecipType = RecipType.substr(0, RefPos);
2283 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
2352 if (LI.
hasMetadata(LLVMContext::MD_invariant_load))
2369 if (SI.isVolatile())
2372 if (SI.hasMetadata(LLVMContext::MD_nontemporal))
2385 if (
const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) {
2386 if (RMW->isVolatile())
2389 if (CmpX->isVolatile())
2423 auto &MF = *
MI.getMF();
2424 auto &
MRI = MF.getRegInfo();
2431 auto maxUses = [](
unsigned RematCost) {
2434 return std::numeric_limits<unsigned>::max();
2444 switch (
MI.getOpcode()) {
2449 case TargetOpcode::G_CONSTANT:
2450 case TargetOpcode::G_FCONSTANT:
2451 case TargetOpcode::G_FRAME_INDEX:
2452 case TargetOpcode::G_INTTOPTR:
2454 case TargetOpcode::G_GLOBAL_VALUE: {
2457 unsigned MaxUses = maxUses(RematCost);
2458 if (MaxUses == UINT_MAX)
2460 return MRI.hasAtMostUserInstrs(Reg, MaxUses);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
This file contains the simple types necessary to represent the attributes associated with functions a...
This file implements the BitVector class.
unsigned const TargetRegisterInfo * TRI
Module.h This file contains the declarations for the Module class.
const char LLVMTargetMachineRef TM
static bool isDigit(const char C)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
static bool darwinHasSinCos(const Triple &TT)
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
#define OP_TO_LIBCALL(Name, Enum)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
static cl::opt< bool > DisableStrictNodeMutation("disable-strictnode-mutation", cl::desc("Don't mutate strict-float node to a legalize node"), cl::init(false), cl::Hidden)
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled,...
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults.
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
This file describes how to lower LLVM code to machine code.
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
an instruction that atomically reads a memory location, combines it with another value,...
bool hasRetAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the return value.
const Function * getParent() const
Return the enclosing method, or null if none.
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add '1' bits from Mask to this vector.
iterator_range< const_set_bits_iterator > set_bits() const
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
This is an important base class in LLVM.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size in bytes, rounded up to a whole number of bytes.
static constexpr ElementCount getScalable(ScalarTy MinVal)
static constexpr ElementCount getFixed(ScalarTy MinVal)
constexpr bool isScalar() const
Exactly one element.
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Module * getParent()
Get the module that this global value is contained inside of...
@ HiddenVisibility
The GV is hidden.
@ ExternalLinkage
Externally visible function.
Common base class shared among various IRBuilders.
FenceInst * CreateFence(AtomicOrdering Ordering, SyncScope::ID SSID=SyncScope::System, const Twine &Name="")
BasicBlock * GetInsertBlock() const
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value * > Args=std::nullopt, const Twine &Name="", MDNode *FPMathTag=nullptr)
bool hasAtomicStore() const LLVM_READONLY
Return true if this atomic instruction stores to memory.
bool hasMetadata() const
Return true if this instruction has any metadata attached to it.
@ MAX_INT_BITS
Maximum number of bits that can be specified.
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
Value * getPointerOperand()
bool isVolatile() const
Return true if this is a load from a volatile memory location.
Align getAlign() const
Return the alignment of the access that is being performed.
uint64_t getScalarSizeInBits() const
bool isVector() const
Return true if this is a vector value type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static auto all_valuetypes()
SimpleValueType Iteration.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
ElementCount getVectorElementCount() const
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isValid() const
Return true if this is a valid simple valuetype.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type.
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
unsigned getNumOperands() const
Retuns the total number of operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
A description of a memory reference used in the backend.
unsigned getAddrSpace() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
Flags getFlags() const
Return the raw flags of the source value,.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
void freezeReservedRegs()
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
A Module instance is used to store all the information related to an LLVM module.
Class to represent pointers.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
Analysis providing profile information.
Wrapper class representing virtual and physical registers.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
const DataLayout & getDataLayout() const
LLVMContext * getContext() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
StringRef - Represent a constant reference to a string, i.e.
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
constexpr StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
constexpr bool empty() const
empty - Check if the string is empty.
constexpr size_t size() const
size - Get the string size.
static constexpr size_t npos
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
Provides information about what library functions are available for the current target.
LegalizeTypeAction getTypeAction(MVT VT) const
void setTypeAction(MVT VT, LegalizeTypeAction Action)
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
void initActions()
Initialize all of the actions to default values.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual Value * getSafeStackPointerLocation(IRBuilderBase &IRB) const
Returns the target-specific address of the unsafe stack pointer.
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function's at...
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
virtual bool shouldLocalize(const MachineInstr &MI, const TargetTransformInfo *TTI) const
Check whether or not MI needs to be moved close to its uses.
virtual unsigned getMaxPermittedBytesForAlignment(MachineBasicBlock *MBB) const
Return the maximum amount of bytes allowed to be emitted when padding for alignment.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
const TargetMachine & getTargetMachine() const
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual MachineMemOperand::Flags getTargetMMOFlags(const Instruction &I) const
This callback is used to inspect load/store instructions and add target-specific MachineMemOperand fl...
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
@ TypeScalarizeScalableVector
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, uint64_t Range, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Return true if lowering to a jump table is suitable for a set of case clusters which may contain NumC...
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
void setIndexedMaskedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked load does or does not work with the specified type and ind...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual bool useFPRegsForHalfType() const
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, const MachineMemOperand &MMO) const
Return true if the following transform is beneficial: fold (conv (load x)) -> (load (conv*)x) On arch...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
virtual bool softPromoteHalfType() const
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal.
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
Value * getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function's attributes.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
virtual Value * getIRStackGuard(IRBuilderBase &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
virtual MVT getPreferredSwitchConditionType(LLVMContext &Context, EVT ConditionVT) const
Returns preferred type for switch condition.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool EnableExtLdPromotion
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function's attri...
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual bool isJumpTableRelative() const
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
Return the type to use for a scalar shift opcode, given the shifted amount type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g.
void setIndexedMaskedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed masked store does or does not work with the specified type and in...
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ UndefinedBooleanContent
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const
Return pair that represents the legalization kind (first) that needs to happen to EVT (second) in ord...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should continue looking for chain dependencies when trying to find a more...
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function's attribut...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
virtual Instruction * emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
virtual Instruction * emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const
If the action for this operation is to promote, this method returns the ValueType to promote to.
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
Primary interface to the complete machine description for the target machine.
bool isPositionIndependent() const
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
unsigned LoopAlignment
If greater than 0, override TargetLoweringBase::PrefLoopAlignment.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Triple - Helper class for working with autoconf configuration names.
bool isWindowsGNUEnvironment() const
bool isAndroid() const
Tests whether the target is Android.
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
constexpr LeafTy coefficientNextPowerOf2() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
constexpr LeafTy divideCoefficientBy(ScalarTy RHS) const
We do not provide the '/' operator here because division for polynomial types does not work in the sa...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ ARM_AAPCS_VFP
Same as ARM_AAPCS, but uses hard floating point ABI.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ SET_FPENV
Sets the current floating-point environment.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ RESET_FPENV
Set floating-point environment to default state.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ SSUBO
Same for subtraction.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
@ GET_FPENV
Gets the current floating-point environment.
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ GET_FPENV_MEM
Gets the current floating-point environment.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ SET_FPENV_MEM
Sets the current floating point environment.
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
static const int LAST_INDEXED_MODE
Libcall getPOWI(EVT RetVT)
getPOWI - Return the POWI_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none.
Libcall getLDEXP(EVT RetVT)
getLDEXP - Return the LDEXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFREXP(EVT RetVT)
getFREXP - Return the FREXP_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT)
Return the outline atomics value for the given opcode, atomic ordering and type, or UNKNOWN_LIBCALL i...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getOutlineAtomicHelper(const Libcall(&LC)[5][4], AtomicOrdering Order, uint64_t MemSize)
Return the outline atomics value for the given atomic ordering, access size and set of libcalls for a...
Libcall getFPLibCall(EVT VT, Libcall Call_F32, Libcall Call_F64, Libcall Call_F80, Libcall Call_F128, Libcall Call_PPCF128)
GetFPLibCall - Helper to return the right libcall for the given floating point type,...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
EVT getApproximateEVTForLLT(LLT Ty, const DataLayout &DL, LLVMContext &Ctx)
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
auto enum_seq(EnumT Begin, EnumT End)
Iterate over an enum type from Begin up to - but not including - End.
bool isDereferenceableAndAlignedPointer(const Value *V, Type *Ty, Align Alignment, const DataLayout &DL, const Instruction *CtxI=nullptr, AssumptionCache *AC=nullptr, const DominatorTree *DT=nullptr, const TargetLibraryInfo *TLI=nullptr)
Returns true if V is always a dereferenceable pointer with alignment greater or equal than requested.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
constexpr force_iteration_on_noniterable_enum_t force_iteration_on_noniterable_enum
T bit_ceil(T Value)
Returns the smallest integral power of two no smaller than Value if Value is nonzero.
bool isReleaseOrStronger(AtomicOrdering AO)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
@ Xor
Bitwise or logical XOR of integers.
@ And
Bitwise or logical AND of integers.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
bool isAcquireOrStronger(AtomicOrdering AO)
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isFixedLengthVector() const
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight),...
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isZeroSized() const
Test if the given EVT has zero size, this will fail if called on a scalable type.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...