LLVM  9.0.0svn
TargetLoweringBase.cpp
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1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This implements the TargetLoweringBase class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/ADT/BitVector.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringRef.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/CodeGen/Analysis.h"
31 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/Attributes.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalValue.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/IRBuilder.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/IR/Type.h"
47 #include "llvm/Support/Casting.h"
49 #include "llvm/Support/Compiler.h"
54 #include <algorithm>
55 #include <cassert>
56 #include <cstddef>
57 #include <cstdint>
58 #include <cstring>
59 #include <iterator>
60 #include <string>
61 #include <tuple>
62 #include <utility>
63 
64 using namespace llvm;
65 
67  "jump-is-expensive", cl::init(false),
68  cl::desc("Do not create extra branches to split comparison logic."),
69  cl::Hidden);
70 
72  ("min-jump-table-entries", cl::init(4), cl::Hidden,
73  cl::desc("Set minimum number of entries to use a jump table."));
74 
76  ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden,
77  cl::desc("Set maximum size of jump tables."));
78 
79 /// Minimum jump table density for normal functions.
80 static cl::opt<unsigned>
81  JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden,
82  cl::desc("Minimum density for building a jump table in "
83  "a normal function"));
84 
85 /// Minimum jump table density for -Os or -Oz functions.
87  "optsize-jump-table-density", cl::init(40), cl::Hidden,
88  cl::desc("Minimum density for building a jump table in "
89  "an optsize function"));
90 
91 static bool darwinHasSinCos(const Triple &TT) {
92  assert(TT.isOSDarwin() && "should be called with darwin triple");
93  // Don't bother with 32 bit x86.
94  if (TT.getArch() == Triple::x86)
95  return false;
96  // Macos < 10.9 has no sincos_stret.
97  if (TT.isMacOSX())
98  return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit();
99  // iOS < 7.0 has no sincos_stret.
100  if (TT.isiOS())
101  return !TT.isOSVersionLT(7, 0);
102  // Any other darwin such as WatchOS/TvOS is new enough.
103  return true;
104 }
105 
106 // Although this default value is arbitrary, it is not random. It is assumed
107 // that a condition that evaluates the same way by a higher percentage than this
108 // is best represented as control flow. Therefore, the default value N should be
109 // set such that the win from N% correct executions is greater than the loss
110 // from (100 - N)% mispredicted executions for the majority of intended targets.
112  "min-predictable-branch", cl::init(99),
113  cl::desc("Minimum percentage (0-100) that a condition must be either true "
114  "or false to assume that the condition is predictable"),
115  cl::Hidden);
116 
117 void TargetLoweringBase::InitLibcalls(const Triple &TT) {
118 #define HANDLE_LIBCALL(code, name) \
119  setLibcallName(RTLIB::code, name);
120 #include "llvm/IR/RuntimeLibcalls.def"
121 #undef HANDLE_LIBCALL
122  // Initialize calling conventions to their default.
123  for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC)
125 
126  // A few names are different on particular architectures or environments.
127  if (TT.isOSDarwin()) {
128  // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
129  // of the gnueabi-style __gnu_*_ieee.
130  // FIXME: What about other targets?
131  setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
132  setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
133 
134  // Some darwins have an optimized __bzero/bzero function.
135  switch (TT.getArch()) {
136  case Triple::x86:
137  case Triple::x86_64:
138  if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6))
139  setLibcallName(RTLIB::BZERO, "__bzero");
140  break;
141  case Triple::aarch64:
142  setLibcallName(RTLIB::BZERO, "bzero");
143  break;
144  default:
145  break;
146  }
147 
148  if (darwinHasSinCos(TT)) {
149  setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret");
150  setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret");
151  if (TT.isWatchABI()) {
152  setLibcallCallingConv(RTLIB::SINCOS_STRET_F32,
154  setLibcallCallingConv(RTLIB::SINCOS_STRET_F64,
156  }
157  }
158  } else {
159  setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee");
160  setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee");
161  }
162 
163  if (TT.isGNUEnvironment() || TT.isOSFuchsia() ||
164  (TT.isAndroid() && !TT.isAndroidVersionLT(9))) {
165  setLibcallName(RTLIB::SINCOS_F32, "sincosf");
166  setLibcallName(RTLIB::SINCOS_F64, "sincos");
167  setLibcallName(RTLIB::SINCOS_F80, "sincosl");
168  setLibcallName(RTLIB::SINCOS_F128, "sincosl");
169  setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl");
170  }
171 
172  if (TT.isOSOpenBSD()) {
173  setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr);
174  }
175 }
176 
177 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
178 /// UNKNOWN_LIBCALL if there is none.
180  if (OpVT == MVT::f16) {
181  if (RetVT == MVT::f32)
182  return FPEXT_F16_F32;
183  } else if (OpVT == MVT::f32) {
184  if (RetVT == MVT::f64)
185  return FPEXT_F32_F64;
186  if (RetVT == MVT::f128)
187  return FPEXT_F32_F128;
188  if (RetVT == MVT::ppcf128)
189  return FPEXT_F32_PPCF128;
190  } else if (OpVT == MVT::f64) {
191  if (RetVT == MVT::f128)
192  return FPEXT_F64_F128;
193  else if (RetVT == MVT::ppcf128)
194  return FPEXT_F64_PPCF128;
195  } else if (OpVT == MVT::f80) {
196  if (RetVT == MVT::f128)
197  return FPEXT_F80_F128;
198  }
199 
200  return UNKNOWN_LIBCALL;
201 }
202 
203 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
204 /// UNKNOWN_LIBCALL if there is none.
206  if (RetVT == MVT::f16) {
207  if (OpVT == MVT::f32)
208  return FPROUND_F32_F16;
209  if (OpVT == MVT::f64)
210  return FPROUND_F64_F16;
211  if (OpVT == MVT::f80)
212  return FPROUND_F80_F16;
213  if (OpVT == MVT::f128)
214  return FPROUND_F128_F16;
215  if (OpVT == MVT::ppcf128)
216  return FPROUND_PPCF128_F16;
217  } else if (RetVT == MVT::f32) {
218  if (OpVT == MVT::f64)
219  return FPROUND_F64_F32;
220  if (OpVT == MVT::f80)
221  return FPROUND_F80_F32;
222  if (OpVT == MVT::f128)
223  return FPROUND_F128_F32;
224  if (OpVT == MVT::ppcf128)
225  return FPROUND_PPCF128_F32;
226  } else if (RetVT == MVT::f64) {
227  if (OpVT == MVT::f80)
228  return FPROUND_F80_F64;
229  if (OpVT == MVT::f128)
230  return FPROUND_F128_F64;
231  if (OpVT == MVT::ppcf128)
232  return FPROUND_PPCF128_F64;
233  } else if (RetVT == MVT::f80) {
234  if (OpVT == MVT::f128)
235  return FPROUND_F128_F80;
236  }
237 
238  return UNKNOWN_LIBCALL;
239 }
240 
241 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
242 /// UNKNOWN_LIBCALL if there is none.
244  if (OpVT == MVT::f32) {
245  if (RetVT == MVT::i32)
246  return FPTOSINT_F32_I32;
247  if (RetVT == MVT::i64)
248  return FPTOSINT_F32_I64;
249  if (RetVT == MVT::i128)
250  return FPTOSINT_F32_I128;
251  } else if (OpVT == MVT::f64) {
252  if (RetVT == MVT::i32)
253  return FPTOSINT_F64_I32;
254  if (RetVT == MVT::i64)
255  return FPTOSINT_F64_I64;
256  if (RetVT == MVT::i128)
257  return FPTOSINT_F64_I128;
258  } else if (OpVT == MVT::f80) {
259  if (RetVT == MVT::i32)
260  return FPTOSINT_F80_I32;
261  if (RetVT == MVT::i64)
262  return FPTOSINT_F80_I64;
263  if (RetVT == MVT::i128)
264  return FPTOSINT_F80_I128;
265  } else if (OpVT == MVT::f128) {
266  if (RetVT == MVT::i32)
267  return FPTOSINT_F128_I32;
268  if (RetVT == MVT::i64)
269  return FPTOSINT_F128_I64;
270  if (RetVT == MVT::i128)
271  return FPTOSINT_F128_I128;
272  } else if (OpVT == MVT::ppcf128) {
273  if (RetVT == MVT::i32)
274  return FPTOSINT_PPCF128_I32;
275  if (RetVT == MVT::i64)
276  return FPTOSINT_PPCF128_I64;
277  if (RetVT == MVT::i128)
278  return FPTOSINT_PPCF128_I128;
279  }
280  return UNKNOWN_LIBCALL;
281 }
282 
283 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
284 /// UNKNOWN_LIBCALL if there is none.
286  if (OpVT == MVT::f32) {
287  if (RetVT == MVT::i32)
288  return FPTOUINT_F32_I32;
289  if (RetVT == MVT::i64)
290  return FPTOUINT_F32_I64;
291  if (RetVT == MVT::i128)
292  return FPTOUINT_F32_I128;
293  } else if (OpVT == MVT::f64) {
294  if (RetVT == MVT::i32)
295  return FPTOUINT_F64_I32;
296  if (RetVT == MVT::i64)
297  return FPTOUINT_F64_I64;
298  if (RetVT == MVT::i128)
299  return FPTOUINT_F64_I128;
300  } else if (OpVT == MVT::f80) {
301  if (RetVT == MVT::i32)
302  return FPTOUINT_F80_I32;
303  if (RetVT == MVT::i64)
304  return FPTOUINT_F80_I64;
305  if (RetVT == MVT::i128)
306  return FPTOUINT_F80_I128;
307  } else if (OpVT == MVT::f128) {
308  if (RetVT == MVT::i32)
309  return FPTOUINT_F128_I32;
310  if (RetVT == MVT::i64)
311  return FPTOUINT_F128_I64;
312  if (RetVT == MVT::i128)
313  return FPTOUINT_F128_I128;
314  } else if (OpVT == MVT::ppcf128) {
315  if (RetVT == MVT::i32)
316  return FPTOUINT_PPCF128_I32;
317  if (RetVT == MVT::i64)
318  return FPTOUINT_PPCF128_I64;
319  if (RetVT == MVT::i128)
320  return FPTOUINT_PPCF128_I128;
321  }
322  return UNKNOWN_LIBCALL;
323 }
324 
325 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
326 /// UNKNOWN_LIBCALL if there is none.
328  if (OpVT == MVT::i32) {
329  if (RetVT == MVT::f32)
330  return SINTTOFP_I32_F32;
331  if (RetVT == MVT::f64)
332  return SINTTOFP_I32_F64;
333  if (RetVT == MVT::f80)
334  return SINTTOFP_I32_F80;
335  if (RetVT == MVT::f128)
336  return SINTTOFP_I32_F128;
337  if (RetVT == MVT::ppcf128)
338  return SINTTOFP_I32_PPCF128;
339  } else if (OpVT == MVT::i64) {
340  if (RetVT == MVT::f32)
341  return SINTTOFP_I64_F32;
342  if (RetVT == MVT::f64)
343  return SINTTOFP_I64_F64;
344  if (RetVT == MVT::f80)
345  return SINTTOFP_I64_F80;
346  if (RetVT == MVT::f128)
347  return SINTTOFP_I64_F128;
348  if (RetVT == MVT::ppcf128)
349  return SINTTOFP_I64_PPCF128;
350  } else if (OpVT == MVT::i128) {
351  if (RetVT == MVT::f32)
352  return SINTTOFP_I128_F32;
353  if (RetVT == MVT::f64)
354  return SINTTOFP_I128_F64;
355  if (RetVT == MVT::f80)
356  return SINTTOFP_I128_F80;
357  if (RetVT == MVT::f128)
358  return SINTTOFP_I128_F128;
359  if (RetVT == MVT::ppcf128)
360  return SINTTOFP_I128_PPCF128;
361  }
362  return UNKNOWN_LIBCALL;
363 }
364 
365 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
366 /// UNKNOWN_LIBCALL if there is none.
368  if (OpVT == MVT::i32) {
369  if (RetVT == MVT::f32)
370  return UINTTOFP_I32_F32;
371  if (RetVT == MVT::f64)
372  return UINTTOFP_I32_F64;
373  if (RetVT == MVT::f80)
374  return UINTTOFP_I32_F80;
375  if (RetVT == MVT::f128)
376  return UINTTOFP_I32_F128;
377  if (RetVT == MVT::ppcf128)
378  return UINTTOFP_I32_PPCF128;
379  } else if (OpVT == MVT::i64) {
380  if (RetVT == MVT::f32)
381  return UINTTOFP_I64_F32;
382  if (RetVT == MVT::f64)
383  return UINTTOFP_I64_F64;
384  if (RetVT == MVT::f80)
385  return UINTTOFP_I64_F80;
386  if (RetVT == MVT::f128)
387  return UINTTOFP_I64_F128;
388  if (RetVT == MVT::ppcf128)
389  return UINTTOFP_I64_PPCF128;
390  } else if (OpVT == MVT::i128) {
391  if (RetVT == MVT::f32)
392  return UINTTOFP_I128_F32;
393  if (RetVT == MVT::f64)
394  return UINTTOFP_I128_F64;
395  if (RetVT == MVT::f80)
396  return UINTTOFP_I128_F80;
397  if (RetVT == MVT::f128)
398  return UINTTOFP_I128_F128;
399  if (RetVT == MVT::ppcf128)
400  return UINTTOFP_I128_PPCF128;
401  }
402  return UNKNOWN_LIBCALL;
403 }
404 
405 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
406 #define OP_TO_LIBCALL(Name, Enum) \
407  case Name: \
408  switch (VT.SimpleTy) { \
409  default: \
410  return UNKNOWN_LIBCALL; \
411  case MVT::i8: \
412  return Enum##_1; \
413  case MVT::i16: \
414  return Enum##_2; \
415  case MVT::i32: \
416  return Enum##_4; \
417  case MVT::i64: \
418  return Enum##_8; \
419  case MVT::i128: \
420  return Enum##_16; \
421  }
422 
423  switch (Opc) {
424  OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
425  OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
426  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
427  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
428  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
429  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
430  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
431  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
432  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
433  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
434  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
435  OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
436  }
437 
438 #undef OP_TO_LIBCALL
439 
440  return UNKNOWN_LIBCALL;
441 }
442 
444  switch (ElementSize) {
445  case 1:
446  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1;
447  case 2:
448  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2;
449  case 4:
450  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4;
451  case 8:
452  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8;
453  case 16:
454  return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16;
455  default:
456  return UNKNOWN_LIBCALL;
457  }
458 }
459 
461  switch (ElementSize) {
462  case 1:
463  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1;
464  case 2:
465  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2;
466  case 4:
467  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4;
468  case 8:
469  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8;
470  case 16:
471  return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16;
472  default:
473  return UNKNOWN_LIBCALL;
474  }
475 }
476 
478  switch (ElementSize) {
479  case 1:
480  return MEMSET_ELEMENT_UNORDERED_ATOMIC_1;
481  case 2:
482  return MEMSET_ELEMENT_UNORDERED_ATOMIC_2;
483  case 4:
484  return MEMSET_ELEMENT_UNORDERED_ATOMIC_4;
485  case 8:
486  return MEMSET_ELEMENT_UNORDERED_ATOMIC_8;
487  case 16:
488  return MEMSET_ELEMENT_UNORDERED_ATOMIC_16;
489  default:
490  return UNKNOWN_LIBCALL;
491  }
492 }
493 
494 /// InitCmpLibcallCCs - Set default comparison libcall CC.
495 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496  memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497  CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498  CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499  CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
500  CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ;
501  CCs[RTLIB::UNE_F32] = ISD::SETNE;
502  CCs[RTLIB::UNE_F64] = ISD::SETNE;
503  CCs[RTLIB::UNE_F128] = ISD::SETNE;
504  CCs[RTLIB::UNE_PPCF128] = ISD::SETNE;
505  CCs[RTLIB::OGE_F32] = ISD::SETGE;
506  CCs[RTLIB::OGE_F64] = ISD::SETGE;
507  CCs[RTLIB::OGE_F128] = ISD::SETGE;
508  CCs[RTLIB::OGE_PPCF128] = ISD::SETGE;
509  CCs[RTLIB::OLT_F32] = ISD::SETLT;
510  CCs[RTLIB::OLT_F64] = ISD::SETLT;
511  CCs[RTLIB::OLT_F128] = ISD::SETLT;
512  CCs[RTLIB::OLT_PPCF128] = ISD::SETLT;
513  CCs[RTLIB::OLE_F32] = ISD::SETLE;
514  CCs[RTLIB::OLE_F64] = ISD::SETLE;
515  CCs[RTLIB::OLE_F128] = ISD::SETLE;
516  CCs[RTLIB::OLE_PPCF128] = ISD::SETLE;
517  CCs[RTLIB::OGT_F32] = ISD::SETGT;
518  CCs[RTLIB::OGT_F64] = ISD::SETGT;
519  CCs[RTLIB::OGT_F128] = ISD::SETGT;
520  CCs[RTLIB::OGT_PPCF128] = ISD::SETGT;
521  CCs[RTLIB::UO_F32] = ISD::SETNE;
522  CCs[RTLIB::UO_F64] = ISD::SETNE;
523  CCs[RTLIB::UO_F128] = ISD::SETNE;
524  CCs[RTLIB::UO_PPCF128] = ISD::SETNE;
525  CCs[RTLIB::O_F32] = ISD::SETEQ;
526  CCs[RTLIB::O_F64] = ISD::SETEQ;
527  CCs[RTLIB::O_F128] = ISD::SETEQ;
528  CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
529 }
530 
531 /// NOTE: The TargetMachine owns TLOF.
533  initActions();
534 
535  // Perform these initializations only once.
537  MaxLoadsPerMemcmp = 8;
541  UseUnderscoreSetJmp = false;
542  UseUnderscoreLongJmp = false;
543  HasMultipleConditionRegisters = false;
544  HasExtractBitsInsn = false;
545  JumpIsExpensive = JumpIsExpensiveOverride;
547  EnableExtLdPromotion = false;
548  StackPointerRegisterToSaveRestore = 0;
549  BooleanContents = UndefinedBooleanContent;
550  BooleanFloatContents = UndefinedBooleanContent;
551  BooleanVectorContents = UndefinedBooleanContent;
552  SchedPreferenceInfo = Sched::ILP;
553  JumpBufSize = 0;
554  JumpBufAlignment = 0;
555  MinFunctionAlignment = 0;
556  PrefFunctionAlignment = 0;
557  PrefLoopAlignment = 0;
559  MinStackArgumentAlignment = 1;
560  // TODO: the default will be switched to 0 in the next commit, along
561  // with the Target-specific changes necessary.
562  MaxAtomicSizeInBitsSupported = 1024;
563 
564  MinCmpXchgSizeInBits = 0;
565  SupportsUnalignedAtomics = false;
566 
567  std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr);
568 
569  InitLibcalls(TM.getTargetTriple());
570  InitCmpLibcallCCs(CmpLibcallCCs);
571 }
572 
574  // All operations default to being supported.
575  memset(OpActions, 0, sizeof(OpActions));
576  memset(LoadExtActions, 0, sizeof(LoadExtActions));
577  memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
578  memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
579  memset(CondCodeActions, 0, sizeof(CondCodeActions));
580  std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr);
581  std::fill(std::begin(TargetDAGCombineArray),
582  std::end(TargetDAGCombineArray), 0);
583 
584  for (MVT VT : MVT::fp_valuetypes()) {
585  MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
586  if (IntVT.isValid()) {
589  }
590  }
591 
592  // Set default actions for various operations.
593  for (MVT VT : MVT::all_valuetypes()) {
594  // Default all indexed load / store to expand.
595  for (unsigned IM = (unsigned)ISD::PRE_INC;
596  IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
597  setIndexedLoadAction(IM, VT, Expand);
598  setIndexedStoreAction(IM, VT, Expand);
599  }
600 
601  // Most backends expect to see the node which just returns the value loaded.
603 
604  // These operations default to expand.
628 
629  // Overflow operations default to expand
636 
637  // ADDCARRY operations default to expand
641 
642  // ADDC/ADDE/SUBC/SUBE default to expand.
647 
648  // These default to Expand so they will be expanded to CTLZ/CTTZ by default.
651 
653 
654  // These library functions default to expand.
657 
658  // These operations default to expand for vector types.
659  if (VT.isVector()) {
664  }
665 
666  // Constrained floating-point operations default to expand.
693 
694  // For most targets @llvm.get.dynamic.area.offset just returns 0.
696 
697  // Vector reduction default to expand.
711  }
712 
713  // Most targets ignore the @llvm.prefetch intrinsic.
715 
716  // Most targets also ignore the @llvm.readcyclecounter intrinsic.
718 
719  // ConstantFP nodes default to expand. Targets can either change this to
720  // Legal, in which case all fp constants are legal, or use isFPImmLegal()
721  // to optimize expansions for certain constants.
727 
728  // These library functions default to expand.
729  for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
746  }
747 
748  // Default ISD::TRAP to expand (which turns it into abort).
750 
751  // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
752  // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
754 }
755 
757  EVT) const {
759 }
760 
762  bool LegalTypes) const {
763  assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
764  if (LHSTy.isVector())
765  return LHSTy;
766  return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy)
767  : getPointerTy(DL);
768 }
769 
770 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
771  assert(isTypeLegal(VT));
772  switch (Op) {
773  default:
774  return false;
775  case ISD::SDIV:
776  case ISD::UDIV:
777  case ISD::SREM:
778  case ISD::UREM:
779  return true;
780  }
781 }
782 
784  // If the command-line option was specified, ignore this request.
785  if (!JumpIsExpensiveOverride.getNumOccurrences())
786  JumpIsExpensive = isExpensive;
787 }
788 
790 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
791  // If this is a simple type, use the ComputeRegisterProp mechanism.
792  if (VT.isSimple()) {
793  MVT SVT = VT.getSimpleVT();
794  assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
795  MVT NVT = TransformToType[SVT.SimpleTy];
797 
798  assert((LA == TypeLegal || LA == TypeSoftenFloat ||
800  "Promote may not follow Expand or Promote");
801 
802  if (LA == TypeSplitVector)
803  return LegalizeKind(LA,
804  EVT::getVectorVT(Context, SVT.getVectorElementType(),
805  SVT.getVectorNumElements() / 2));
806  if (LA == TypeScalarizeVector)
807  return LegalizeKind(LA, SVT.getVectorElementType());
808  return LegalizeKind(LA, NVT);
809  }
810 
811  // Handle Extended Scalar Types.
812  if (!VT.isVector()) {
813  assert(VT.isInteger() && "Float types must be simple");
814  unsigned BitSize = VT.getSizeInBits();
815  // First promote to a power-of-two size, then expand if necessary.
816  if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
817  EVT NVT = VT.getRoundIntegerType(Context);
818  assert(NVT != VT && "Unable to round integer VT");
819  LegalizeKind NextStep = getTypeConversion(Context, NVT);
820  // Avoid multi-step promotion.
821  if (NextStep.first == TypePromoteInteger)
822  return NextStep;
823  // Return rounded integer type.
824  return LegalizeKind(TypePromoteInteger, NVT);
825  }
826 
828  EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
829  }
830 
831  // Handle vector types.
832  unsigned NumElts = VT.getVectorNumElements();
833  EVT EltVT = VT.getVectorElementType();
834 
835  // Vectors with only one element are always scalarized.
836  if (NumElts == 1)
837  return LegalizeKind(TypeScalarizeVector, EltVT);
838 
839  // Try to widen vector elements until the element type is a power of two and
840  // promote it to a legal type later on, for example:
841  // <3 x i8> -> <4 x i8> -> <4 x i32>
842  if (EltVT.isInteger()) {
843  // Vectors with a number of elements that is not a power of two are always
844  // widened, for example <3 x i8> -> <4 x i8>.
845  if (!VT.isPow2VectorType()) {
846  NumElts = (unsigned)NextPowerOf2(NumElts);
847  EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
848  return LegalizeKind(TypeWidenVector, NVT);
849  }
850 
851  // Examine the element type.
852  LegalizeKind LK = getTypeConversion(Context, EltVT);
853 
854  // If type is to be expanded, split the vector.
855  // <4 x i140> -> <2 x i140>
856  if (LK.first == TypeExpandInteger)
858  EVT::getVectorVT(Context, EltVT, NumElts / 2));
859 
860  // Promote the integer element types until a legal vector type is found
861  // or until the element integer type is too big. If a legal type was not
862  // found, fallback to the usual mechanism of widening/splitting the
863  // vector.
864  EVT OldEltVT = EltVT;
865  while (true) {
866  // Increase the bitwidth of the element to the next pow-of-two
867  // (which is greater than 8 bits).
868  EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
869  .getRoundIntegerType(Context);
870 
871  // Stop trying when getting a non-simple element type.
872  // Note that vector elements may be greater than legal vector element
873  // types. Example: X86 XMM registers hold 64bit element on 32bit
874  // systems.
875  if (!EltVT.isSimple())
876  break;
877 
878  // Build a new vector type and check if it is legal.
879  MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
880  // Found a legal promoted vector type.
881  if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
883  EVT::getVectorVT(Context, EltVT, NumElts));
884  }
885 
886  // Reset the type to the unexpanded type if we did not find a legal vector
887  // type with a promoted vector element type.
888  EltVT = OldEltVT;
889  }
890 
891  // Try to widen the vector until a legal type is found.
892  // If there is no wider legal type, split the vector.
893  while (true) {
894  // Round up to the next power of 2.
895  NumElts = (unsigned)NextPowerOf2(NumElts);
896 
897  // If there is no simple vector type with this many elements then there
898  // cannot be a larger legal vector type. Note that this assumes that
899  // there are no skipped intermediate vector types in the simple types.
900  if (!EltVT.isSimple())
901  break;
902  MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
903  if (LargerVector == MVT())
904  break;
905 
906  // If this type is legal then widen the vector.
907  if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
908  return LegalizeKind(TypeWidenVector, LargerVector);
909  }
910 
911  // Widen odd vectors to next power of two.
912  if (!VT.isPow2VectorType()) {
913  EVT NVT = VT.getPow2VectorType(Context);
914  return LegalizeKind(TypeWidenVector, NVT);
915  }
916 
917  // Vectors with illegal element types are expanded.
918  EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
919  return LegalizeKind(TypeSplitVector, NVT);
920 }
921 
922 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
923  unsigned &NumIntermediates,
924  MVT &RegisterVT,
925  TargetLoweringBase *TLI) {
926  // Figure out the right, legal destination reg to copy into.
927  unsigned NumElts = VT.getVectorNumElements();
928  MVT EltTy = VT.getVectorElementType();
929 
930  unsigned NumVectorRegs = 1;
931 
932  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
933  // could break down into LHS/RHS like LegalizeDAG does.
934  if (!isPowerOf2_32(NumElts)) {
935  NumVectorRegs = NumElts;
936  NumElts = 1;
937  }
938 
939  // Divide the input until we get to a supported size. This will always
940  // end with a scalar if the target doesn't support vectors.
941  while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
942  NumElts >>= 1;
943  NumVectorRegs <<= 1;
944  }
945 
946  NumIntermediates = NumVectorRegs;
947 
948  MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
949  if (!TLI->isTypeLegal(NewVT))
950  NewVT = EltTy;
951  IntermediateVT = NewVT;
952 
953  unsigned NewVTSize = NewVT.getSizeInBits();
954 
955  // Convert sizes such as i33 to i64.
956  if (!isPowerOf2_32(NewVTSize))
957  NewVTSize = NextPowerOf2(NewVTSize);
958 
959  MVT DestVT = TLI->getRegisterType(NewVT);
960  RegisterVT = DestVT;
961  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
962  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
963 
964  // Otherwise, promotion or legal types use the same number of registers as
965  // the vector decimated to the appropriate level.
966  return NumVectorRegs;
967 }
968 
969 /// isLegalRC - Return true if the value types that can be represented by the
970 /// specified register class are all legal.
972  const TargetRegisterClass &RC) const {
973  for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I)
974  if (isTypeLegal(*I))
975  return true;
976  return false;
977 }
978 
979 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
980 /// sequence of memory operands that is recognized by PrologEpilogInserter.
983  MachineBasicBlock *MBB) const {
984  MachineInstr *MI = &InitialMI;
985  MachineFunction &MF = *MI->getMF();
986  MachineFrameInfo &MFI = MF.getFrameInfo();
987 
988  // We're handling multiple types of operands here:
989  // PATCHPOINT MetaArgs - live-in, read only, direct
990  // STATEPOINT Deopt Spill - live-through, read only, indirect
991  // STATEPOINT Deopt Alloca - live-through, read only, direct
992  // (We're currently conservative and mark the deopt slots read/write in
993  // practice.)
994  // STATEPOINT GC Spill - live-through, read/write, indirect
995  // STATEPOINT GC Alloca - live-through, read/write, direct
996  // The live-in vs live-through is handled already (the live through ones are
997  // all stack slots), but we need to handle the different type of stackmap
998  // operands and memory effects here.
999 
1000  // MI changes inside this loop as we grow operands.
1001  for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1002  MachineOperand &MO = MI->getOperand(OperIdx);
1003  if (!MO.isFI())
1004  continue;
1005 
1006  // foldMemoryOperand builds a new MI after replacing a single FI operand
1007  // with the canonical set of five x86 addressing-mode operands.
1008  int FI = MO.getIndex();
1009  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1010 
1011  // Copy operands before the frame-index.
1012  for (unsigned i = 0; i < OperIdx; ++i)
1013  MIB.add(MI->getOperand(i));
1014  // Add frame index operands recognized by stackmaps.cpp
1015  if (MFI.isStatepointSpillSlotObjectIndex(FI)) {
1016  // indirect-mem-ref tag, size, #FI, offset.
1017  // Used for spills inserted by StatepointLowering. This codepath is not
1018  // used for patchpoints/stackmaps at all, for these spilling is done via
1019  // foldMemoryOperand callback only.
1020  assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity");
1021  MIB.addImm(StackMaps::IndirectMemRefOp);
1022  MIB.addImm(MFI.getObjectSize(FI));
1023  MIB.add(MI->getOperand(OperIdx));
1024  MIB.addImm(0);
1025  } else {
1026  // direct-mem-ref tag, #FI, offset.
1027  // Used by patchpoint, and direct alloca arguments to statepoints
1028  MIB.addImm(StackMaps::DirectMemRefOp);
1029  MIB.add(MI->getOperand(OperIdx));
1030  MIB.addImm(0);
1031  }
1032  // Copy the operands after the frame index.
1033  for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1034  MIB.add(MI->getOperand(i));
1035 
1036  // Inherit previous memory operands.
1037  MIB.cloneMemRefs(*MI);
1038  assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1039 
1040  // Add a new memory operand for this FI.
1041  assert(MFI.getObjectOffset(FI) != -1);
1042 
1043  // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and
1044  // PATCHPOINT should be updated to do the same. (TODO)
1045  if (MI->getOpcode() != TargetOpcode::STATEPOINT) {
1046  auto Flags = MachineMemOperand::MOLoad;
1048  MachinePointerInfo::getFixedStack(MF, FI), Flags,
1050  MIB->addMemOperand(MF, MMO);
1051  }
1052 
1053  // Replace the instruction and update the operand index.
1054  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1055  OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1056  MI->eraseFromParent();
1057  MI = MIB;
1058  }
1059  return MBB;
1060 }
1061 
1064  MachineBasicBlock *MBB) const {
1065  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL &&
1066  "Called emitXRayCustomEvent on the wrong MI!");
1067  auto &MF = *MI.getMF();
1068  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1069  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1070  MIB.add(MI.getOperand(OpIdx));
1071 
1072  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1073  MI.eraseFromParent();
1074  return MBB;
1075 }
1076 
1079  MachineBasicBlock *MBB) const {
1080  assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL &&
1081  "Called emitXRayTypedEvent on the wrong MI!");
1082  auto &MF = *MI.getMF();
1083  auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1084  for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx)
1085  MIB.add(MI.getOperand(OpIdx));
1086 
1087  MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1088  MI.eraseFromParent();
1089  return MBB;
1090 }
1091 
1092 /// findRepresentativeClass - Return the largest legal super-reg register class
1093 /// of the register class for the specified type and its associated "cost".
1094 // This function is in TargetLowering because it uses RegClassForVT which would
1095 // need to be moved to TargetRegisterInfo and would necessitate moving
1096 // isTypeLegal over as well - a massive change that would just require
1097 // TargetLowering having a TargetRegisterInfo class member that it would use.
1098 std::pair<const TargetRegisterClass *, uint8_t>
1100  MVT VT) const {
1101  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1102  if (!RC)
1103  return std::make_pair(RC, 0);
1104 
1105  // Compute the set of all super-register classes.
1106  BitVector SuperRegRC(TRI->getNumRegClasses());
1107  for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1108  SuperRegRC.setBitsInMask(RCI.getMask());
1109 
1110  // Find the first legal register class with the largest spill size.
1111  const TargetRegisterClass *BestRC = RC;
1112  for (unsigned i : SuperRegRC.set_bits()) {
1113  const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1114  // We want the largest possible spill size.
1115  if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
1116  continue;
1117  if (!isLegalRC(*TRI, *SuperRC))
1118  continue;
1119  BestRC = SuperRC;
1120  }
1121  return std::make_pair(BestRC, 1);
1122 }
1123 
1124 /// computeRegisterProperties - Once all of the register classes are added,
1125 /// this allows us to compute derived properties we expose.
1127  const TargetRegisterInfo *TRI) {
1129  "Too many value types for ValueTypeActions to hold!");
1130 
1131  // Everything defaults to needing one register.
1132  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1133  NumRegistersForVT[i] = 1;
1134  RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1135  }
1136  // ...except isVoid, which doesn't need any registers.
1137  NumRegistersForVT[MVT::isVoid] = 0;
1138 
1139  // Find the largest integer register class.
1140  unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
1141  for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
1142  assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1143 
1144  // Every integer value type larger than this largest register takes twice as
1145  // many registers to represent as the previous ValueType.
1146  for (unsigned ExpandedReg = LargestIntReg + 1;
1147  ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1148  NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1149  RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1150  TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1153  }
1154 
1155  // Inspect all of the ValueType's smaller than the largest integer
1156  // register to see which ones need promotion.
1157  unsigned LegalIntReg = LargestIntReg;
1158  for (unsigned IntReg = LargestIntReg - 1;
1159  IntReg >= (unsigned)MVT::i1; --IntReg) {
1160  MVT IVT = (MVT::SimpleValueType)IntReg;
1161  if (isTypeLegal(IVT)) {
1162  LegalIntReg = IntReg;
1163  } else {
1164  RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1165  (MVT::SimpleValueType)LegalIntReg;
1167  }
1168  }
1169 
1170  // ppcf128 type is really two f64's.
1171  if (!isTypeLegal(MVT::ppcf128)) {
1172  if (isTypeLegal(MVT::f64)) {
1173  NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1174  RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1175  TransformToType[MVT::ppcf128] = MVT::f64;
1177  } else {
1178  NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1179  RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1180  TransformToType[MVT::ppcf128] = MVT::i128;
1182  }
1183  }
1184 
1185  // Decide how to handle f128. If the target does not have native f128 support,
1186  // expand it to i128 and we will be generating soft float library calls.
1187  if (!isTypeLegal(MVT::f128)) {
1188  NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1189  RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1190  TransformToType[MVT::f128] = MVT::i128;
1192  }
1193 
1194  // Decide how to handle f64. If the target does not have native f64 support,
1195  // expand it to i64 and we will be generating soft float library calls.
1196  if (!isTypeLegal(MVT::f64)) {
1197  NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1198  RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1199  TransformToType[MVT::f64] = MVT::i64;
1201  }
1202 
1203  // Decide how to handle f32. If the target does not have native f32 support,
1204  // expand it to i32 and we will be generating soft float library calls.
1205  if (!isTypeLegal(MVT::f32)) {
1206  NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1207  RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1208  TransformToType[MVT::f32] = MVT::i32;
1210  }
1211 
1212  // Decide how to handle f16. If the target does not have native f16 support,
1213  // promote it to f32, because there are no f16 library calls (except for
1214  // conversions).
1215  if (!isTypeLegal(MVT::f16)) {
1216  NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1217  RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1218  TransformToType[MVT::f16] = MVT::f32;
1220  }
1221 
1222  // Loop over all of the vector value types to see which need transformations.
1223  for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1224  i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1225  MVT VT = (MVT::SimpleValueType) i;
1226  if (isTypeLegal(VT))
1227  continue;
1228 
1229  MVT EltVT = VT.getVectorElementType();
1230  unsigned NElts = VT.getVectorNumElements();
1231  bool IsLegalWiderType = false;
1232  LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1233  switch (PreferredAction) {
1234  case TypePromoteInteger:
1235  // Try to promote the elements of integer vectors. If no legal
1236  // promotion was found, fall through to the widen-vector method.
1237  for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) {
1238  MVT SVT = (MVT::SimpleValueType) nVT;
1239  // Promote vectors of integers to vectors with the same number
1240  // of elements, with a wider element type.
1241  if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() &&
1242  SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) {
1243  TransformToType[i] = SVT;
1244  RegisterTypeForVT[i] = SVT;
1245  NumRegistersForVT[i] = 1;
1247  IsLegalWiderType = true;
1248  break;
1249  }
1250  }
1251  if (IsLegalWiderType)
1252  break;
1254 
1255  case TypeWidenVector:
1256  // Try to widen the vector.
1257  for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1258  MVT SVT = (MVT::SimpleValueType) nVT;
1259  if (SVT.getVectorElementType() == EltVT
1260  && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
1261  TransformToType[i] = SVT;
1262  RegisterTypeForVT[i] = SVT;
1263  NumRegistersForVT[i] = 1;
1265  IsLegalWiderType = true;
1266  break;
1267  }
1268  }
1269  if (IsLegalWiderType)
1270  break;
1272 
1273  case TypeSplitVector:
1274  case TypeScalarizeVector: {
1275  MVT IntermediateVT;
1276  MVT RegisterVT;
1277  unsigned NumIntermediates;
1278  NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1279  NumIntermediates, RegisterVT, this);
1280  RegisterTypeForVT[i] = RegisterVT;
1281 
1282  MVT NVT = VT.getPow2VectorType();
1283  if (NVT == VT) {
1284  // Type is already a power of 2. The default action is to split.
1285  TransformToType[i] = MVT::Other;
1286  if (PreferredAction == TypeScalarizeVector)
1288  else if (PreferredAction == TypeSplitVector)
1290  else
1291  // Set type action according to the number of elements.
1293  : TypeSplitVector);
1294  } else {
1295  TransformToType[i] = NVT;
1297  }
1298  break;
1299  }
1300  default:
1301  llvm_unreachable("Unknown vector legalization action!");
1302  }
1303  }
1304 
1305  // Determine the 'representative' register class for each value type.
1306  // An representative register class is the largest (meaning one which is
1307  // not a sub-register class / subreg register class) legal register class for
1308  // a group of value types. For example, on i386, i8, i16, and i32
1309  // representative would be GR32; while on x86_64 it's GR64.
1310  for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1311  const TargetRegisterClass* RRC;
1312  uint8_t Cost;
1313  std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
1314  RepRegClassForVT[i] = RRC;
1315  RepRegClassCostForVT[i] = Cost;
1316  }
1317 }
1318 
1320  EVT VT) const {
1321  assert(!VT.isVector() && "No default SetCC type for vectors!");
1322  return getPointerTy(DL).SimpleTy;
1323 }
1324 
1326  return MVT::i32; // return the default value
1327 }
1328 
1329 /// getVectorTypeBreakdown - Vector types are broken down into some number of
1330 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1331 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1332 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1333 ///
1334 /// This method returns the number of registers needed, and the VT for each
1335 /// register. It also returns the VT and quantity of the intermediate values
1336 /// before they are promoted/expanded.
1338  EVT &IntermediateVT,
1339  unsigned &NumIntermediates,
1340  MVT &RegisterVT) const {
1341  unsigned NumElts = VT.getVectorNumElements();
1342 
1343  // If there is a wider vector type with the same element type as this one,
1344  // or a promoted vector type that has the same number of elements which
1345  // are wider, then we should convert to that legal vector type.
1346  // This handles things like <2 x float> -> <4 x float> and
1347  // <4 x i1> -> <4 x i32>.
1348  LegalizeTypeAction TA = getTypeAction(Context, VT);
1349  if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1350  EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1351  if (isTypeLegal(RegisterEVT)) {
1352  IntermediateVT = RegisterEVT;
1353  RegisterVT = RegisterEVT.getSimpleVT();
1354  NumIntermediates = 1;
1355  return 1;
1356  }
1357  }
1358 
1359  // Figure out the right, legal destination reg to copy into.
1360  EVT EltTy = VT.getVectorElementType();
1361 
1362  unsigned NumVectorRegs = 1;
1363 
1364  // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1365  // could break down into LHS/RHS like LegalizeDAG does.
1366  if (!isPowerOf2_32(NumElts)) {
1367  NumVectorRegs = NumElts;
1368  NumElts = 1;
1369  }
1370 
1371  // Divide the input until we get to a supported size. This will always
1372  // end with a scalar if the target doesn't support vectors.
1373  while (NumElts > 1 && !isTypeLegal(
1374  EVT::getVectorVT(Context, EltTy, NumElts))) {
1375  NumElts >>= 1;
1376  NumVectorRegs <<= 1;
1377  }
1378 
1379  NumIntermediates = NumVectorRegs;
1380 
1381  EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1382  if (!isTypeLegal(NewVT))
1383  NewVT = EltTy;
1384  IntermediateVT = NewVT;
1385 
1386  MVT DestVT = getRegisterType(Context, NewVT);
1387  RegisterVT = DestVT;
1388  unsigned NewVTSize = NewVT.getSizeInBits();
1389 
1390  // Convert sizes such as i33 to i64.
1391  if (!isPowerOf2_32(NewVTSize))
1392  NewVTSize = NextPowerOf2(NewVTSize);
1393 
1394  if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1395  return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1396 
1397  // Otherwise, promotion or legal types use the same number of registers as
1398  // the vector decimated to the appropriate level.
1399  return NumVectorRegs;
1400 }
1401 
1402 /// Get the EVTs and ArgFlags collections that represent the legalized return
1403 /// type of the given function. This does not require a DAG or a return value,
1404 /// and is suitable for use before any DAGs for the function are constructed.
1405 /// TODO: Move this out of TargetLowering.cpp.
1407  AttributeList attr,
1409  const TargetLowering &TLI, const DataLayout &DL) {
1410  SmallVector<EVT, 4> ValueVTs;
1411  ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
1412  unsigned NumValues = ValueVTs.size();
1413  if (NumValues == 0) return;
1414 
1415  for (unsigned j = 0, f = NumValues; j != f; ++j) {
1416  EVT VT = ValueVTs[j];
1417  ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1418 
1419  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1420  ExtendKind = ISD::SIGN_EXTEND;
1421  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1422  ExtendKind = ISD::ZERO_EXTEND;
1423 
1424  // FIXME: C calling convention requires the return type to be promoted to
1425  // at least 32-bit. But this is not necessary for non-C calling
1426  // conventions. The frontend should mark functions whose return values
1427  // require promoting with signext or zeroext attributes.
1428  if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1429  MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1430  if (VT.bitsLT(MinVT))
1431  VT = MinVT;
1432  }
1433 
1434  unsigned NumParts =
1435  TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT);
1436  MVT PartVT =
1437  TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT);
1438 
1439  // 'inreg' on function refers to return value
1440  ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1441  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg))
1442  Flags.setInReg();
1443 
1444  // Propagate extension type if any
1445  if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
1446  Flags.setSExt();
1447  else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
1448  Flags.setZExt();
1449 
1450  for (unsigned i = 0; i < NumParts; ++i)
1451  Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
1452  }
1453 }
1454 
1455 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1456 /// function arguments in the caller parameter area. This is the actual
1457 /// alignment, not its logarithm.
1459  const DataLayout &DL) const {
1460  return DL.getABITypeAlignment(Ty);
1461 }
1462 
1464  const DataLayout &DL, EVT VT,
1465  unsigned AddrSpace,
1466  unsigned Alignment,
1468  bool *Fast) const {
1469  // Check if the specified alignment is sufficient based on the data layout.
1470  // TODO: While using the data layout works in practice, a better solution
1471  // would be to implement this check directly (make this a virtual function).
1472  // For example, the ABI alignment may change based on software platform while
1473  // this function should only be affected by hardware implementation.
1474  Type *Ty = VT.getTypeForEVT(Context);
1475  if (Alignment >= DL.getABITypeAlignment(Ty)) {
1476  // Assume that an access that meets the ABI-specified alignment is fast.
1477  if (Fast != nullptr)
1478  *Fast = true;
1479  return true;
1480  }
1481 
1482  // This is a misaligned access.
1483  return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast);
1484 }
1485 
1487  const DataLayout &DL, EVT VT,
1488  const MachineMemOperand &MMO,
1489  bool *Fast) const {
1490  return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(),
1491  MMO.getAlignment(), MMO.getFlags(), Fast);
1492 }
1493 
1495  return BranchProbability(MinPercentageForPredictableBranch, 100);
1496 }
1497 
1498 //===----------------------------------------------------------------------===//
1499 // TargetTransformInfo Helpers
1500 //===----------------------------------------------------------------------===//
1501 
1503  enum InstructionOpcodes {
1504 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1505 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1506 #include "llvm/IR/Instruction.def"
1507  };
1508  switch (static_cast<InstructionOpcodes>(Opcode)) {
1509  case Ret: return 0;
1510  case Br: return 0;
1511  case Switch: return 0;
1512  case IndirectBr: return 0;
1513  case Invoke: return 0;
1514  case CallBr: return 0;
1515  case Resume: return 0;
1516  case Unreachable: return 0;
1517  case CleanupRet: return 0;
1518  case CatchRet: return 0;
1519  case CatchPad: return 0;
1520  case CatchSwitch: return 0;
1521  case CleanupPad: return 0;
1522  case FNeg: return ISD::FNEG;
1523  case Add: return ISD::ADD;
1524  case FAdd: return ISD::FADD;
1525  case Sub: return ISD::SUB;
1526  case FSub: return ISD::FSUB;
1527  case Mul: return ISD::MUL;
1528  case FMul: return ISD::FMUL;
1529  case UDiv: return ISD::UDIV;
1530  case SDiv: return ISD::SDIV;
1531  case FDiv: return ISD::FDIV;
1532  case URem: return ISD::UREM;
1533  case SRem: return ISD::SREM;
1534  case FRem: return ISD::FREM;
1535  case Shl: return ISD::SHL;
1536  case LShr: return ISD::SRL;
1537  case AShr: return ISD::SRA;
1538  case And: return ISD::AND;
1539  case Or: return ISD::OR;
1540  case Xor: return ISD::XOR;
1541  case Alloca: return 0;
1542  case Load: return ISD::LOAD;
1543  case Store: return ISD::STORE;
1544  case GetElementPtr: return 0;
1545  case Fence: return 0;
1546  case AtomicCmpXchg: return 0;
1547  case AtomicRMW: return 0;
1548  case Trunc: return ISD::TRUNCATE;
1549  case ZExt: return ISD::ZERO_EXTEND;
1550  case SExt: return ISD::SIGN_EXTEND;
1551  case FPToUI: return ISD::FP_TO_UINT;
1552  case FPToSI: return ISD::FP_TO_SINT;
1553  case UIToFP: return ISD::UINT_TO_FP;
1554  case SIToFP: return ISD::SINT_TO_FP;
1555  case FPTrunc: return ISD::FP_ROUND;
1556  case FPExt: return ISD::FP_EXTEND;
1557  case PtrToInt: return ISD::BITCAST;
1558  case IntToPtr: return ISD::BITCAST;
1559  case BitCast: return ISD::BITCAST;
1560  case AddrSpaceCast: return ISD::ADDRSPACECAST;
1561  case ICmp: return ISD::SETCC;
1562  case FCmp: return ISD::SETCC;
1563  case PHI: return 0;
1564  case Call: return 0;
1565  case Select: return ISD::SELECT;
1566  case UserOp1: return 0;
1567  case UserOp2: return 0;
1568  case VAArg: return 0;
1569  case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1570  case InsertElement: return ISD::INSERT_VECTOR_ELT;
1571  case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1572  case ExtractValue: return ISD::MERGE_VALUES;
1573  case InsertValue: return ISD::MERGE_VALUES;
1574  case LandingPad: return 0;
1575  }
1576 
1577  llvm_unreachable("Unknown instruction type encountered!");
1578 }
1579 
1580 std::pair<int, MVT>
1582  Type *Ty) const {
1583  LLVMContext &C = Ty->getContext();
1584  EVT MTy = getValueType(DL, Ty);
1585 
1586  int Cost = 1;
1587  // We keep legalizing the type until we find a legal kind. We assume that
1588  // the only operation that costs anything is the split. After splitting
1589  // we need to handle two types.
1590  while (true) {
1591  LegalizeKind LK = getTypeConversion(C, MTy);
1592 
1593  if (LK.first == TypeLegal)
1594  return std::make_pair(Cost, MTy.getSimpleVT());
1595 
1596  if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1597  Cost *= 2;
1598 
1599  // Do not loop with f128 type.
1600  if (MTy == LK.second)
1601  return std::make_pair(Cost, MTy.getSimpleVT());
1602 
1603  // Keep legalizing the type.
1604  MTy = LK.second;
1605  }
1606 }
1607 
1609  bool UseTLS) const {
1610  // compiler-rt provides a variable with a magic name. Targets that do not
1611  // link with compiler-rt may also provide such a variable.
1612  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1613  const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr";
1614  auto UnsafeStackPtr =
1615  dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar));
1616 
1617  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1618 
1619  if (!UnsafeStackPtr) {
1620  auto TLSModel = UseTLS ?
1623  // The global variable is not defined yet, define it ourselves.
1624  // We use the initial-exec TLS model because we do not support the
1625  // variable living anywhere other than in the main executable.
1626  UnsafeStackPtr = new GlobalVariable(
1627  *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr,
1628  UnsafeStackPtrVar, nullptr, TLSModel);
1629  } else {
1630  // The variable exists, check its type and attributes.
1631  if (UnsafeStackPtr->getValueType() != StackPtrTy)
1632  report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type");
1633  if (UseTLS != UnsafeStackPtr->isThreadLocal())
1634  report_fatal_error(Twine(UnsafeStackPtrVar) + " must " +
1635  (UseTLS ? "" : "not ") + "be thread-local");
1636  }
1637  return UnsafeStackPtr;
1638 }
1639 
1641  if (!TM.getTargetTriple().isAndroid())
1642  return getDefaultSafeStackPointerLocation(IRB, true);
1643 
1644  // Android provides a libc function to retrieve the address of the current
1645  // thread's unsafe stack pointer.
1646  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
1647  Type *StackPtrTy = Type::getInt8PtrTy(M->getContext());
1648  FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address",
1649  StackPtrTy->getPointerTo(0));
1650  return IRB.CreateCall(Fn);
1651 }
1652 
1653 //===----------------------------------------------------------------------===//
1654 // Loop Strength Reduction hooks
1655 //===----------------------------------------------------------------------===//
1656 
1657 /// isLegalAddressingMode - Return true if the addressing mode represented
1658 /// by AM is legal for this target, for a load/store of the specified type.
1660  const AddrMode &AM, Type *Ty,
1661  unsigned AS, Instruction *I) const {
1662  // The default implementation of this implements a conservative RISCy, r+r and
1663  // r+i addr mode.
1664 
1665  // Allows a sign-extended 16-bit immediate field.
1666  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1667  return false;
1668 
1669  // No global is ever allowed as a base.
1670  if (AM.BaseGV)
1671  return false;
1672 
1673  // Only support r+r,
1674  switch (AM.Scale) {
1675  case 0: // "r+i" or just "i", depending on HasBaseReg.
1676  break;
1677  case 1:
1678  if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1679  return false;
1680  // Otherwise we have r+r or r+i.
1681  break;
1682  case 2:
1683  if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1684  return false;
1685  // Allow 2*r as r+r.
1686  break;
1687  default: // Don't allow n * r
1688  return false;
1689  }
1690 
1691  return true;
1692 }
1693 
1694 //===----------------------------------------------------------------------===//
1695 // Stack Protector
1696 //===----------------------------------------------------------------------===//
1697 
1698 // For OpenBSD return its special guard variable. Otherwise return nullptr,
1699 // so that SelectionDAG handle SSP.
1701  if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
1702  Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
1704  return M.getOrInsertGlobal("__guard_local", PtrTy);
1705  }
1706  return nullptr;
1707 }
1708 
1709 // Currently only support "standard" __stack_chk_guard.
1710 // TODO: add LOAD_STACK_GUARD support.
1712  if (!M.getNamedValue("__stack_chk_guard"))
1713  new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false,
1715  nullptr, "__stack_chk_guard");
1716 }
1717 
1718 // Currently only support "standard" __stack_chk_guard.
1719 // TODO: add LOAD_STACK_GUARD support.
1721  return M.getNamedValue("__stack_chk_guard");
1722 }
1723 
1725  return nullptr;
1726 }
1727 
1729  return MinimumJumpTableEntries;
1730 }
1731 
1734 }
1735 
1736 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const {
1737  return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity;
1738 }
1739 
1741  return MaximumJumpTableSize;
1742 }
1743 
1745  MaximumJumpTableSize = Val;
1746 }
1747 
1748 //===----------------------------------------------------------------------===//
1749 // Reciprocal Estimates
1750 //===----------------------------------------------------------------------===//
1751 
1752 /// Get the reciprocal estimate attribute string for a function that will
1753 /// override the target defaults.
1755  const Function &F = MF.getFunction();
1756  return F.getFnAttribute("reciprocal-estimates").getValueAsString();
1757 }
1758 
1759 /// Construct a string for the given reciprocal operation of the given type.
1760 /// This string should match the corresponding option to the front-end's
1761 /// "-mrecip" flag assuming those strings have been passed through in an
1762 /// attribute string. For example, "vec-divf" for a division of a vXf32.
1763 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) {
1764  std::string Name = VT.isVector() ? "vec-" : "";
1765 
1766  Name += IsSqrt ? "sqrt" : "div";
1767 
1768  // TODO: Handle "half" or other float types?
1769  if (VT.getScalarType() == MVT::f64) {
1770  Name += "d";
1771  } else {
1772  assert(VT.getScalarType() == MVT::f32 &&
1773  "Unexpected FP type for reciprocal estimate");
1774  Name += "f";
1775  }
1776 
1777  return Name;
1778 }
1779 
1780 /// Return the character position and value (a single numeric character) of a
1781 /// customized refinement operation in the input string if it exists. Return
1782 /// false if there is no customized refinement step count.
1784  uint8_t &Value) {
1785  const char RefStepToken = ':';
1786  Position = In.find(RefStepToken);
1787  if (Position == StringRef::npos)
1788  return false;
1789 
1790  StringRef RefStepString = In.substr(Position + 1);
1791  // Allow exactly one numeric character for the additional refinement
1792  // step parameter.
1793  if (RefStepString.size() == 1) {
1794  char RefStepChar = RefStepString[0];
1795  if (RefStepChar >= '0' && RefStepChar <= '9') {
1796  Value = RefStepChar - '0';
1797  return true;
1798  }
1799  }
1800  report_fatal_error("Invalid refinement step for -recip.");
1801 }
1802 
1803 /// For the input attribute string, return one of the ReciprocalEstimate enum
1804 /// status values (enabled, disabled, or not specified) for this operation on
1805 /// the specified data type.
1806 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) {
1807  if (Override.empty())
1808  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1809 
1810  SmallVector<StringRef, 4> OverrideVector;
1811  Override.split(OverrideVector, ',');
1812  unsigned NumArgs = OverrideVector.size();
1813 
1814  // Check if "all", "none", or "default" was specified.
1815  if (NumArgs == 1) {
1816  // Look for an optional setting of the number of refinement steps needed
1817  // for this type of reciprocal operation.
1818  size_t RefPos;
1819  uint8_t RefSteps;
1820  if (parseRefinementStep(Override, RefPos, RefSteps)) {
1821  // Split the string for further processing.
1822  Override = Override.substr(0, RefPos);
1823  }
1824 
1825  // All reciprocal types are enabled.
1826  if (Override == "all")
1828 
1829  // All reciprocal types are disabled.
1830  if (Override == "none")
1831  return TargetLoweringBase::ReciprocalEstimate::Disabled;
1832 
1833  // Target defaults for enablement are used.
1834  if (Override == "default")
1835  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1836  }
1837 
1838  // The attribute string may omit the size suffix ('f'/'d').
1839  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1840  std::string VTNameNoSize = VTName;
1841  VTNameNoSize.pop_back();
1842  static const char DisabledPrefix = '!';
1843 
1844  for (StringRef RecipType : OverrideVector) {
1845  size_t RefPos;
1846  uint8_t RefSteps;
1847  if (parseRefinementStep(RecipType, RefPos, RefSteps))
1848  RecipType = RecipType.substr(0, RefPos);
1849 
1850  // Ignore the disablement token for string matching.
1851  bool IsDisabled = RecipType[0] == DisabledPrefix;
1852  if (IsDisabled)
1853  RecipType = RecipType.substr(1);
1854 
1855  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1856  return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled
1858  }
1859 
1860  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1861 }
1862 
1863 /// For the input attribute string, return the customized refinement step count
1864 /// for this operation on the specified data type. If the step count does not
1865 /// exist, return the ReciprocalEstimate enum value for unspecified.
1866 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) {
1867  if (Override.empty())
1868  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1869 
1870  SmallVector<StringRef, 4> OverrideVector;
1871  Override.split(OverrideVector, ',');
1872  unsigned NumArgs = OverrideVector.size();
1873 
1874  // Check if "all", "default", or "none" was specified.
1875  if (NumArgs == 1) {
1876  // Look for an optional setting of the number of refinement steps needed
1877  // for this type of reciprocal operation.
1878  size_t RefPos;
1879  uint8_t RefSteps;
1880  if (!parseRefinementStep(Override, RefPos, RefSteps))
1881  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1882 
1883  // Split the string for further processing.
1884  Override = Override.substr(0, RefPos);
1885  assert(Override != "none" &&
1886  "Disabled reciprocals, but specifed refinement steps?");
1887 
1888  // If this is a general override, return the specified number of steps.
1889  if (Override == "all" || Override == "default")
1890  return RefSteps;
1891  }
1892 
1893  // The attribute string may omit the size suffix ('f'/'d').
1894  std::string VTName = getReciprocalOpName(IsSqrt, VT);
1895  std::string VTNameNoSize = VTName;
1896  VTNameNoSize.pop_back();
1897 
1898  for (StringRef RecipType : OverrideVector) {
1899  size_t RefPos;
1900  uint8_t RefSteps;
1901  if (!parseRefinementStep(RecipType, RefPos, RefSteps))
1902  continue;
1903 
1904  RecipType = RecipType.substr(0, RefPos);
1905  if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize))
1906  return RefSteps;
1907  }
1908 
1909  return TargetLoweringBase::ReciprocalEstimate::Unspecified;
1910 }
1911 
1913  MachineFunction &MF) const {
1914  return getOpEnabled(true, VT, getRecipEstimateForFunc(MF));
1915 }
1916 
1918  MachineFunction &MF) const {
1919  return getOpEnabled(false, VT, getRecipEstimateForFunc(MF));
1920 }
1921 
1923  MachineFunction &MF) const {
1924  return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF));
1925 }
1926 
1928  MachineFunction &MF) const {
1929  return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF));
1930 }
1931 
1933  MF.getRegInfo().freezeReservedRegs(MF);
1934 }
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
static bool darwinHasSinCos(const Triple &TT)
uint64_t CallInst * C
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
Definition: ISDOpcodes.h:595
X = FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision of the ...
Definition: ISDOpcodes.h:562
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:480
static MVT getIntegerVT(unsigned BitWidth)
const MachineInstrBuilder & add(const MachineOperand &MO) const
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:110
const_iterator end(StringRef path)
Get end iterator over path.
Definition: Path.cpp:233
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
Definition: ISDOpcodes.h:622
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
Constrained versions of libm-equivalent floating point intrinsics.
Definition: ISDOpcodes.h:300
LLVMContext & Context
unsigned getAddrSpace() const
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
Definition: ValueTypes.h:358
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
Definition: Path.cpp:224
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isMacOSX() const
isMacOSX - Is this a Mac OS X triple.
Definition: Triple.h:452
static MVT getVectorVT(MVT VT, unsigned NumElements)
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0...
Definition: ISDOpcodes.h:633
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
Definition: ISDOpcodes.h:391
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Definition: ValueTypes.h:259
virtual MVT::SimpleValueType getCmpLibcallReturnType() const
Return the ValueType for comparison libcalls.
A Module instance is used to store all the information related to an LLVM module. ...
Definition: Module.h:65
static cl::opt< unsigned > MaximumJumpTableSize("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, cl::desc("Set maximum size of jump tables."))
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
Definition: ISDOpcodes.h:284
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
Definition: ISDOpcodes.h:543
Libcall getSYNC(unsigned Opc, MVT VT)
Return the SYNC_FETCH_AND_* value for the given opcode and type, or UNKNOWN_LIBCALL if there is none...
A handy container for a FunctionType+Callee-pointer pair, which can be passed around as a single enti...
Definition: DerivedTypes.h:164
Carry-setting nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:222
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:384
Y = RRC X, rotate right via carry.
static cl::opt< bool > JumpIsExpensiveOverride("jump-is-expensive", cl::init(false), cl::desc("Do not create extra branches to split comparison logic."), cl::Hidden)
static cl::opt< unsigned > MinimumJumpTableEntries("min-jump-table-entries", cl::init(4), cl::Hidden, cl::desc("Set minimum number of entries to use a jump table."))
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
Definition: ValueTypes.h:252
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
MVT getPow2VectorType() const
Widens the length of the given vector MVT up to the nearest power of 2 and returns that type...
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
Definition: ISDOpcodes.h:250
static cl::opt< int > MinPercentageForPredictableBranch("min-predictable-branch", cl::init(99), cl::desc("Minimum percentage (0-100) that a condition must be either true " "or false to assume that the condition is predictable"), cl::Hidden)
static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return one of the ReciprocalEstimate enum status values (enabled...
unsigned getVectorNumElements() const
Externally visible function.
Definition: GlobalValue.h:48
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
Definition: ISDOpcodes.h:833
unsigned getPointerSizeInBits(unsigned AS=0) const
Layout pointer size, in bits FIXME: The defaults need to be removed once all of the backends/clients ...
Definition: DataLayout.h:388
Constrained versions of the binary floating point operators.
Definition: ISDOpcodes.h:293
unsigned const TargetRegisterInfo * TRI
bool isInteger() const
Return true if this is an integer or a vector integer type.
Definition: ValueTypes.h:140
F(f)
bool isOSFuchsia() const
Definition: Triple.h:500
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
Definition: ISDOpcodes.h:532
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
Definition: ISDOpcodes.h:408
Same for subtraction.
Definition: ISDOpcodes.h:253
std::pair< LegalizeTypeAction, EVT > LegalizeKind
LegalizeKind holds the legalization kind that needs to happen to EVT in order to type-legalize it...
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
unsigned getSpillSize(const TargetRegisterClass &RC) const
Return the size in bytes of the stack slot allocated to hold a spilled copy of a register from class ...
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
Definition: ISDOpcodes.h:38
bool hasAttribute(unsigned Index, Attribute::AttrKind Kind) const
Return true if the attribute exists at the given index.
Libcall getFPROUND(EVT OpVT, EVT RetVT)
getFPROUND - Return the FPROUND_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
Definition: ISDOpcodes.h:340
bool isValid() const
Return true if this is a valid simple valuetype.
EVT getPow2VectorType(LLVMContext &Context) const
Widens the length of the given vector EVT up to the nearest power of 2 and returns that type...
Definition: ValueTypes.h:365
const TargetRegisterClass * getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
Definition: Type.h:129
ARM_AAPCS_VFP - Same as ARM_AAPCS, but uses hard floating point ABI.
Definition: CallingConv.h:102
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a square root of the given type based on the function&#39;s at...
Libcall getUINTTOFP(EVT OpVT, EVT RetVT)
getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
A description of a memory reference used in the backend.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:80
Shift and rotation operations.
Definition: ISDOpcodes.h:434
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:413
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
Definition: ValueTypes.cpp:205
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LLVMContext & getContext() const
Get the global data context.
Definition: Module.h:244
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth...
Definition: ISDOpcodes.h:417
PointerType * getPointerTo(unsigned AddrSpace=0) const
Return a pointer to the current type.
Definition: Type.cpp:651
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
Definition: ISDOpcodes.h:279
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:41
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:742
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
void freezeReservedRegs(const MachineFunction &)
freezeReservedRegs - Called by the register allocator to freeze the set of reserved registers before ...
This file contains the simple types necessary to represent the attributes associated with functions a...
SimpleValueType SimpleTy
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) For double-word atomic operations: ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) These correspond to the atomicrmw instruction.
Definition: ISDOpcodes.h:841
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:410
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
LLVM_NODISCARD StringRef substr(size_t Start, size_t N=npos) const
Return a reference to the substring from [Start, Start + N).
Definition: StringRef.h:578
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, unsigned base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Position
Position to insert a new instruction relative to an existing instruction.
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
unsigned getNumRegClasses() const
unsigned getSizeInBits() const
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:291
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:407
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
Definition: ISDOpcodes.h:502
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose...
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:295
BasicBlock * GetInsertBlock() const
Definition: IRBuilder.h:120
Simple integer binary arithmetic operators.
Definition: ISDOpcodes.h:200
GlobalValue * getNamedValue(StringRef Name) const
Return the global value in the module with the specified name, of arbitrary type. ...
Definition: Module.cpp:113
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:461
static StringRef getRecipEstimateForFunc(MachineFunction &MF)
Get the reciprocal estimate attribute string for a function that will override the target defaults...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:995
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:323
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AddrSpace, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
Definition: ISDOpcodes.h:778
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO)
Add a MachineMemOperand to the machine instruction.
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
Definition: ISDOpcodes.h:521
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< uint64_t > *Offsets=nullptr, uint64_t StartingOffset=0)
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
Definition: Analysis.cpp:119
MVT getVectorElementType() const
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const
Return a ReciprocalEstimate enum value for a division of the given type based on the function&#39;s attri...
Class to represent pointers.
Definition: DerivedTypes.h:498
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
Definition: ISDOpcodes.h:548
static cl::opt< unsigned > JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, cl::desc("Minimum density for building a jump table in " "a normal function"))
Minimum jump table density for normal functions.
virtual Value * getIRStackGuard(IRBuilder<> &IRB) const
If the target has a standard location for the stack protector guard, returns the address of that loca...
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static std::string getReciprocalOpName(bool IsSqrt, EVT VT)
Construct a string for the given reciprocal operation of the given type.
unsigned getObjectAlignment(int ObjectIdx) const
Return the alignment of the specified stack object.
static void InitCmpLibcallCCs(ISD::CondCode *CCs)
InitCmpLibcallCCs - Set default comparison libcall CC.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
These reductions are non-strict, and have a single vector operand.
Definition: ISDOpcodes.h:901
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:428
Machine Value Type.
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:45
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:64
Simple binary floating point operators.
Definition: ISDOpcodes.h:287
bool isOSOpenBSD() const
Definition: Triple.h:492
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
Definition: ValueTypes.h:272
unsigned getScalarSizeInBits() const
unsigned getPointerSize(unsigned AS=0) const
Layout pointer size FIXME: The defaults need to be removed once all of the backends/clients are updat...
Definition: DataLayout.cpp:648
bool isWatchABI() const
Definition: Triple.h:475
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL...
Definition: ISDOpcodes.h:356
TargetLoweringBase(const TargetMachine &TM)
NOTE: The TargetMachine owns TLOF.
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *=nullptr) const
Determine if the target supports unaligned memory accesses.
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:231
Libcall getFPTOSINT(EVT OpVT, EVT RetVT)
getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
LLVM_NODISCARD size_t find(char C, size_t From=0) const
Search for the first character C in the string.
Definition: StringRef.h:285
static mvt_range fp_valuetypes()
bool isAndroidVersionLT(unsigned Major) const
Definition: Triple.h:658
TRAP - Trapping instruction.
Definition: ISDOpcodes.h:798
const Triple & getTargetTriple() const
DEBUGTRAP - Trap intended to get the attention of a debugger.
Definition: ISDOpcodes.h:801
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
unsigned MaxStoresPerMemmove
Specify maximum bytes of store instructions per memmove call.
Bit counting operators with an undefined result for zero inputs.
Definition: ISDOpcodes.h:440
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo...
Definition: ISDOpcodes.h:827
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
Definition: ISDOpcodes.h:580
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual Value * getSafeStackPointerLocation(IRBuilder<> &IRB) const
Returns the target-specific address of the unsafe stack pointer.
Extended Value Type.
Definition: ValueTypes.h:33
uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
Definition: MathExtras.h:639
static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT, TargetLoweringBase *TLI)
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
size_t size() const
Definition: SmallVector.h:52
static PointerType * getInt8PtrTy(LLVMContext &C, unsigned AS=0)
Definition: Type.cpp:219
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a division of the given type based on the function&#39;s attributes...
const TargetMachine & getTargetMachine() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)
Set the CallingConv that should be used for the specified libcall.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
uint64_t getAlignment() const
Return the minimum known alignment in bytes of the actual memory reference.
Value * getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, bool UseTLS) const
unsigned GatherAllAliasesMaxDepth
Depth that GatherAllAliases should should continue looking for chain dependencies when trying to find...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
This base class for TargetLowering contains the SelectionDAG-independent parts that can be used from ...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags...
Libcall getFPEXT(EVT OpVT, EVT RetVT)
getFPEXT - Return the FPEXT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
void initActions()
Initialize all of the actions to default values.
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
Definition: ISDOpcodes.h:264
bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const
Return true if the value types that can be represented by the specified register class are all legal...
EVT getRoundIntegerType(LLVMContext &Context) const
Rounds the bit-width of the given integer EVT up to the nearest power of two (and at least to eight)...
Definition: ValueTypes.h:316
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool canOpTrap(unsigned Op, EVT VT) const
Returns true if the operation can trap for the value type.
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
Definition: ISDOpcodes.h:363
EVT getVectorElementType() const
Given a vector type, return the type of each element.
Definition: ValueTypes.h:264
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
Definition: ISDOpcodes.h:475
ADDRSPACECAST - This operator converts between pointers of different address spaces.
Definition: ISDOpcodes.h:599
MachineOperand class - Representation of each machine instruction operand.
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:837
Module.h This file contains the declarations for the Module class.
unsigned getMaximumJumpTableSize() const
Return upper limit for number of entries in a jump table.
LLVM_NODISCARD std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:696
static cl::opt< unsigned > OptsizeJumpTableDensity("optsize-jump-table-density", cl::init(40), cl::Hidden, cl::desc("Minimum density for building a jump table in " "an optsize function"))
Minimum jump table density for -Os or -Oz functions.
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1050
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const
EVT is not used in-tree, but is used by out-of-tree target.
unsigned getABITypeAlignment(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
Definition: DataLayout.cpp:749
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values, following the IEEE-754 2008 definition.
Definition: ISDOpcodes.h:628
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
FunctionCallee getOrInsertFunction(StringRef Name, FunctionType *T, AttributeList AttributeList)
Look up the specified function in the module symbol table.
Definition: Module.cpp:143
static bool Enabled
Definition: Statistic.cpp:50
const Function & getFunction() const
Return the LLVM function that this machine code represents.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT...
Definition: ValueTypes.h:72
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
bool isStatepointSpillSlotObjectIndex(int ObjectIdx) const
Select(COND, TRUEVAL, FALSEVAL).
Definition: ISDOpcodes.h:444
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
Definition: ValueTypes.h:240
unsigned getMinimumJumpTableDensity(bool OptForSize) const
Return lower limit of the density in a jump table.
void setMaximumJumpTableSize(unsigned)
Indicate the maximum number of entries in jump tables.
ZERO_EXTEND - Used for integer types, zeroing the new bits.
Definition: ISDOpcodes.h:492
ANY_EXTEND - Used for integer types. The high bits are undefined.
Definition: ISDOpcodes.h:495
ValueTypeActionImpl ValueTypeActions
#define OP_TO_LIBCALL(Name, Enum)
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
Definition: ISDOpcodes.h:336
int InstructionOpcodeToISD(unsigned Opcode) const
Get the ISD node that corresponds to the Instruction class opcode.
Flags
Flags values. These may be or&#39;d together.
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const
Return the refinement step count for a square root of the given type based on the function&#39;s attribut...
The memory access reads data.
static bool parseRefinementStep(StringRef In, size_t &Position, uint8_t &Value)
Return the character position and value (a single numeric character) of a customized refinement opera...
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca...
Definition: ISDOpcodes.h:892
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
static mvt_range all_valuetypes()
SimpleValueType Iteration.
Representation of each machine instruction.
Definition: MachineInstr.h:63
Libcall getFPTOUINT(EVT OpVT, EVT RetVT)
getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
bool isVector() const
Return true if this is a vector value type.
Definition: ValueTypes.h:150
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Constant * getOrInsertGlobal(StringRef Name, Type *Ty, function_ref< GlobalVariable *()> CreateGlobalCallback)
Look up the specified global in the module symbol table.
Definition: Module.cpp:204
Bitwise operators - logical and, logical or, logical xor.
Definition: ISDOpcodes.h:411
static const size_t npos
Definition: StringRef.h:50
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * emitXRayCustomEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay custom event operands with target-dependent details.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1290
void setTypeAction(MVT VT, LegalizeTypeAction Action)
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
Definition: ISDOpcodes.h:642
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return &#39;Legal&#39;) or we ...
const Function * getParent() const
Return the enclosing method, or null if none.
Definition: BasicBlock.h:106
MachineBasicBlock * emitXRayTypedEvent(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify the XRay typed event operands with target-dependent details.
#define I(x, y, z)
Definition: MD5.cpp:58
Flags getFlags() const
Return the raw flags of the source value,.
unsigned MaxGluedStoresPerMemcpy
Specify max number of store instructions to glue in inlined memcpy.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
unsigned MaxStoresPerMemmoveOptSize
Maximum number of store instructions that may be substituted for a call to memmove, used for functions with OptSize attribute.
bool isGNUEnvironment() const
Definition: Triple.h:516
unsigned MaxStoresPerMemcpyOptSize
Maximum number of store operations that may be substituted for a call to memcpy, used for functions w...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
Definition: ISDOpcodes.h:272
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding &#39;Y&#39; from a larger floating point type down to the precision ...
Definition: ISDOpcodes.h:318
Same for multiplication.
Definition: ISDOpcodes.h:256
static const int LAST_INDEXED_MODE
Definition: ISDOpcodes.h:958
CallInst * CreateCall(FunctionType *FTy, Value *Callee, ArrayRef< Value *> Args=None, const Twine &Name="", MDNode *FPMathTag=nullptr)
Definition: IRBuilder.h:2051
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that&#39;s previously inserted by insertSSPDeclarations, if any, otherwise return nul...
unsigned MaxStoresPerMemcpy
Specify maximum bytes of store instructions per memcpy call.
bool isMacOSXVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isMacOSXVersionLT - Comparison function for checking OS X version compatibility, which handles suppor...
Definition: Triple.h:437
Libcall getSINTTOFP(EVT OpVT, EVT RetVT)
getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or UNKNOWN_LIBCALL if there is none...
virtual unsigned getMinimumJumpTableEntries() const
Return lower limit for number of blocks in a jump table.
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
Definition: ISDOpcodes.h:369
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
Definition: MachineInstr.h:808
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:575
LLVM Value Representation.
Definition: Value.h:72
Integer reductions may have a result type larger than the vector element type.
Definition: ISDOpcodes.h:907
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
Definition: ISDOpcodes.h:903
virtual void finalizeLowering(MachineFunction &MF) const
Execute target specific actions to finalize target lowering.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Definition: Compiler.h:250
PREFETCH - This corresponds to a prefetch intrinsic.
Definition: ISDOpcodes.h:807
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:656
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations...
Definition: ISDOpcodes.h:330
SetCC operator - This evaluates to a true value iff the condition is true.
Definition: ISDOpcodes.h:467
bool isOSVersionLT(unsigned Major, unsigned Minor=0, unsigned Micro=0) const
isOSVersionLT - Helper function for doing comparisons against version numbers included in the target ...
Definition: Triple.h:413
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
unsigned MaxStoresPerMemsetOptSize
Maximum number of stores operations that may be substituted for the call to memset, used for functions with OptSize attribute.
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
Definition: ISDOpcodes.h:197
Conversion operators.
Definition: ISDOpcodes.h:489
static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override)
For the input attribute string, return the customized refinement step count for this operation on the...
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:498
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
Definition: ValueTypes.h:125
virtual BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor, it is very likely to be predicted correctly.
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:415
Perform various unary floating-point operations inspired by libm.
Definition: ISDOpcodes.h:610
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
Definition: ValueTypes.h:63
virtual TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const
Return the preferred vector type legalization action.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, unsigned Alignment=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
void setBitsInMask(const uint32_t *Mask, unsigned MaskWords=~0u)
setBitsInMask - Add &#39;1&#39; bits from Mask to this vector.
Definition: BitVector.h:775
std::pair< int, MVT > getTypeLegalizationCost(const DataLayout &DL, Type *Ty) const
Estimate the cost of type-legalization and the legalized type.
bool isValid() const
Returns true if this iterator is still pointing at a valid entry.
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Carry-using nodes for multiple precision addition and subtraction.
Definition: ISDOpcodes.h:241
LegalizeTypeAction getTypeAction(MVT VT) const
This file describes how to lower LLVM code to machine code.
vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const
Loop over all of the value types that can be represented by values in the given register class...
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...