LLVM  16.0.0git
TargetTransformInfo.h
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1 //===- TargetTransformInfo.h ------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This pass exposes codegen information to IR-level passes. Every
10 /// transformation that uses codegen information is broken into three parts:
11 /// 1. The IR-level analysis pass.
12 /// 2. The IR-level transformation interface which provides the needed
13 /// information.
14 /// 3. Codegen-level implementation which uses target-specific hooks.
15 ///
16 /// This file defines #2, which is the interface that IR-level transformations
17 /// use for querying the codegen.
18 ///
19 //===----------------------------------------------------------------------===//
20 
21 #ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
22 #define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
23 
25 #include "llvm/IR/FMF.h"
26 #include "llvm/IR/InstrTypes.h"
27 #include "llvm/IR/PassManager.h"
28 #include "llvm/Pass.h"
32 #include <functional>
33 #include <utility>
34 
35 namespace llvm {
36 
37 namespace Intrinsic {
38 typedef unsigned ID;
39 }
40 
41 class AssumptionCache;
42 class BlockFrequencyInfo;
43 class DominatorTree;
44 class BranchInst;
45 class CallBase;
46 class Function;
47 class GlobalValue;
48 class InstCombiner;
51 class IntrinsicInst;
52 class LoadInst;
53 class Loop;
54 class LoopInfo;
56 class ProfileSummaryInfo;
58 class SCEV;
59 class ScalarEvolution;
60 class StoreInst;
61 class SwitchInst;
62 class TargetLibraryInfo;
63 class Type;
64 class User;
65 class Value;
66 class VPIntrinsic;
67 struct KnownBits;
68 template <typename T> class Optional;
69 
70 /// Information about a load/store intrinsic defined by the target.
72  /// This is the pointer that the intrinsic is loading from or storing to.
73  /// If this is non-null, then analysis/optimization passes can assume that
74  /// this intrinsic is functionally equivalent to a load/store from this
75  /// pointer.
76  Value *PtrVal = nullptr;
77 
78  // Ordering for atomic operations.
80 
81  // Same Id is set by the target for corresponding load/store intrinsics.
82  unsigned short MatchingId = 0;
83 
84  bool ReadMem = false;
85  bool WriteMem = false;
86  bool IsVolatile = false;
87 
88  bool isUnordered() const {
91  !IsVolatile;
92  }
93 };
94 
95 /// Attributes of a target dependent hardware loop.
97  HardwareLoopInfo() = delete;
99  Loop *L = nullptr;
100  BasicBlock *ExitBlock = nullptr;
101  BranchInst *ExitBranch = nullptr;
102  const SCEV *ExitCount = nullptr;
103  IntegerType *CountType = nullptr;
104  Value *LoopDecrement = nullptr; // Decrement the loop counter by this
105  // value in every iteration.
106  bool IsNestingLegal = false; // Can a hardware loop be a parent to
107  // another hardware loop?
108  bool CounterInReg = false; // Should loop counter be updated in
109  // the loop via a phi?
110  bool PerformEntryTest = false; // Generate the intrinsic which also performs
111  // icmp ne zero on the loop counter value and
112  // produces an i1 to guard the loop entry.
114  DominatorTree &DT, bool ForceNestedLoop = false,
115  bool ForceHardwareLoopPHI = false);
116  bool canAnalyze(LoopInfo &LI);
117 };
118 
120  const IntrinsicInst *II = nullptr;
121  Type *RetTy = nullptr;
122  Intrinsic::ID IID;
123  SmallVector<Type *, 4> ParamTys;
125  FastMathFlags FMF;
126  // If ScalarizationCost is UINT_MAX, the cost of scalarizing the
127  // arguments and the return value will be computed based on types.
128  InstructionCost ScalarizationCost = InstructionCost::getInvalid();
129 
130 public:
132  Intrinsic::ID Id, const CallBase &CI,
134  bool TypeBasedOnly = false);
135 
138  FastMathFlags Flags = FastMathFlags(), const IntrinsicInst *I = nullptr,
140 
143 
147  const IntrinsicInst *I = nullptr,
149 
150  Intrinsic::ID getID() const { return IID; }
151  const IntrinsicInst *getInst() const { return II; }
152  Type *getReturnType() const { return RetTy; }
153  FastMathFlags getFlags() const { return FMF; }
154  InstructionCost getScalarizationCost() const { return ScalarizationCost; }
156  const SmallVectorImpl<Type *> &getArgTypes() const { return ParamTys; }
157 
158  bool isTypeBasedOnly() const {
159  return Arguments.empty();
160  }
161 
162  bool skipScalarizationCost() const { return ScalarizationCost.isValid(); }
163 };
164 
166 
168 typedef TargetTransformInfo TTI;
169 
170 /// This pass provides access to the codegen interfaces that are needed
171 /// for IR-level transformations.
173 public:
174  /// Construct a TTI object using a type implementing the \c Concept
175  /// API below.
176  ///
177  /// This is used by targets to construct a TTI wrapping their target-specific
178  /// implementation that encodes appropriate costs for their target.
179  template <typename T> TargetTransformInfo(T Impl);
180 
181  /// Construct a baseline TTI object using a minimal implementation of
182  /// the \c Concept API below.
183  ///
184  /// The TTI implementation will reflect the information in the DataLayout
185  /// provided if non-null.
186  explicit TargetTransformInfo(const DataLayout &DL);
187 
188  // Provide move semantics.
191 
192  // We need to define the destructor out-of-line to define our sub-classes
193  // out-of-line.
195 
196  /// Handle the invalidation of this information.
197  ///
198  /// When used as a result of \c TargetIRAnalysis this method will be called
199  /// when the function this was computed for changes. When it returns false,
200  /// the information is preserved across those changes.
203  // FIXME: We should probably in some way ensure that the subtarget
204  // information for a function hasn't changed.
205  return false;
206  }
207 
208  /// \name Generic Target Information
209  /// @{
210 
211  /// The kind of cost model.
212  ///
213  /// There are several different cost models that can be customized by the
214  /// target. The normalization of each cost model may be target specific.
215  /// e.g. TCK_SizeAndLatency should be comparable to target thresholds such as
216  /// those derived from MCSchedModel::LoopMicroOpBufferSize etc.
218  TCK_RecipThroughput, ///< Reciprocal throughput.
219  TCK_Latency, ///< The latency of instruction.
220  TCK_CodeSize, ///< Instruction code size.
221  TCK_SizeAndLatency ///< The weighted sum of size and latency.
222  };
223 
224  /// Underlying constants for 'cost' values in this interface.
225  ///
226  /// Many APIs in this interface return a cost. This enum defines the
227  /// fundamental values that should be used to interpret (and produce) those
228  /// costs. The costs are returned as an int rather than a member of this
229  /// enumeration because it is expected that the cost of one IR instruction
230  /// may have a multiplicative factor to it or otherwise won't fit directly
231  /// into the enum. Moreover, it is common to sum or average costs which works
232  /// better as simple integral values. Thus this enum only provides constants.
233  /// Also note that the returned costs are signed integers to make it natural
234  /// to add, subtract, and test with zero (a common boundary condition). It is
235  /// not expected that 2^32 is a realistic cost to be modeling at any point.
236  ///
237  /// Note that these costs should usually reflect the intersection of code-size
238  /// cost and execution cost. A free instruction is typically one that folds
239  /// into another instruction. For example, reg-to-reg moves can often be
240  /// skipped by renaming the registers in the CPU, but they still are encoded
241  /// and thus wouldn't be considered 'free' here.
243  TCC_Free = 0, ///< Expected to fold away in lowering.
244  TCC_Basic = 1, ///< The cost of a typical 'add' instruction.
245  TCC_Expensive = 4 ///< The cost of a 'div' instruction on x86.
246  };
247 
248  /// Estimate the cost of a GEP operation when lowered.
250  getGEPCost(Type *PointeeType, const Value *Ptr,
253 
254  /// \returns A value by which our inlining threshold should be multiplied.
255  /// This is primarily used to bump up the inlining threshold wholesale on
256  /// targets where calls are unusually expensive.
257  ///
258  /// TODO: This is a rather blunt instrument. Perhaps altering the costs of
259  /// individual classes of instructions would be better.
260  unsigned getInliningThresholdMultiplier() const;
261 
262  /// \returns A value to be added to the inlining threshold.
263  unsigned adjustInliningThreshold(const CallBase *CB) const;
264 
265  /// \returns Vector bonus in percent.
266  ///
267  /// Vector bonuses: We want to more aggressively inline vector-dense kernels
268  /// and apply this bonus based on the percentage of vector instructions. A
269  /// bonus is applied if the vector instructions exceed 50% and half that
270  /// amount is applied if it exceeds 10%. Note that these bonuses are some what
271  /// arbitrary and evolved over time by accident as much as because they are
272  /// principled bonuses.
273  /// FIXME: It would be nice to base the bonus values on something more
274  /// scientific. A target may has no bonus on vector instructions.
275  int getInlinerVectorBonusPercent() const;
276 
277  /// \return the expected cost of a memcpy, which could e.g. depend on the
278  /// source/destination type and alignment and the number of bytes copied.
280 
281  /// \return The estimated number of case clusters when lowering \p 'SI'.
282  /// \p JTSize Set a jump table size only when \p SI is suitable for a jump
283  /// table.
285  unsigned &JTSize,
286  ProfileSummaryInfo *PSI,
287  BlockFrequencyInfo *BFI) const;
288 
289  /// Estimate the cost of a given IR user when lowered.
290  ///
291  /// This can estimate the cost of either a ConstantExpr or Instruction when
292  /// lowered.
293  ///
294  /// \p Operands is a list of operands which can be a result of transformations
295  /// of the current operands. The number of the operands on the list must equal
296  /// to the number of the current operands the IR user has. Their order on the
297  /// list must be the same as the order of the current operands the IR user
298  /// has.
299  ///
300  /// The returned cost is defined in terms of \c TargetCostConstants, see its
301  /// comments for a detailed explanation of the cost values.
304  TargetCostKind CostKind) const;
305 
306  /// This is a helper function which calls the three-argument
307  /// getInstructionCost with \p Operands which are the current operands U has.
309  TargetCostKind CostKind) const {
312  }
313 
314  /// If a branch or a select condition is skewed in one direction by more than
315  /// this factor, it is very likely to be predicted correctly.
317 
318  /// Return true if branch divergence exists.
319  ///
320  /// Branch divergence has a significantly negative impact on GPU performance
321  /// when threads in the same wavefront take different paths due to conditional
322  /// branches.
323  bool hasBranchDivergence() const;
324 
325  /// Return true if the target prefers to use GPU divergence analysis to
326  /// replace the legacy version.
327  bool useGPUDivergenceAnalysis() const;
328 
329  /// Returns whether V is a source of divergence.
330  ///
331  /// This function provides the target-dependent information for
332  /// the target-independent LegacyDivergenceAnalysis. LegacyDivergenceAnalysis
333  /// first builds the dependency graph, and then runs the reachability
334  /// algorithm starting with the sources of divergence.
335  bool isSourceOfDivergence(const Value *V) const;
336 
337  // Returns true for the target specific
338  // set of operations which produce uniform result
339  // even taking non-uniform arguments
340  bool isAlwaysUniform(const Value *V) const;
341 
342  /// Returns the address space ID for a target's 'flat' address space. Note
343  /// this is not necessarily the same as addrspace(0), which LLVM sometimes
344  /// refers to as the generic address space. The flat address space is a
345  /// generic address space that can be used access multiple segments of memory
346  /// with different address spaces. Access of a memory location through a
347  /// pointer with this address space is expected to be legal but slower
348  /// compared to the same memory location accessed through a pointer with a
349  /// different address space.
350  //
351  /// This is for targets with different pointer representations which can
352  /// be converted with the addrspacecast instruction. If a pointer is converted
353  /// to this address space, optimizations should attempt to replace the access
354  /// with the source address space.
355  ///
356  /// \returns ~0u if the target does not have such a flat address space to
357  /// optimize away.
358  unsigned getFlatAddressSpace() const;
359 
360  /// Return any intrinsic address operand indexes which may be rewritten if
361  /// they use a flat address space pointer.
362  ///
363  /// \returns true if the intrinsic was handled.
365  Intrinsic::ID IID) const;
366 
367  bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const;
368 
369  /// Return true if globals in this address space can have initializers other
370  /// than `undef`.
371  bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const;
372 
373  unsigned getAssumedAddrSpace(const Value *V) const;
374 
375  bool isSingleThreaded() const;
376 
377  std::pair<const Value *, unsigned>
378  getPredicatedAddrSpace(const Value *V) const;
379 
380  /// Rewrite intrinsic call \p II such that \p OldV will be replaced with \p
381  /// NewV, which has a different address space. This should happen for every
382  /// operand index that collectFlatAddressOperands returned for the intrinsic.
383  /// \returns nullptr if the intrinsic was not handled. Otherwise, returns the
384  /// new value (which may be the original \p II with modified operands).
386  Value *NewV) const;
387 
388  /// Test whether calls to a function lower to actual program function
389  /// calls.
390  ///
391  /// The idea is to test whether the program is likely to require a 'call'
392  /// instruction or equivalent in order to call the given function.
393  ///
394  /// FIXME: It's not clear that this is a good or useful query API. Client's
395  /// should probably move to simpler cost metrics using the above.
396  /// Alternatively, we could split the cost interface into distinct code-size
397  /// and execution-speed costs. This would allow modelling the core of this
398  /// query more accurately as a call is a single small instruction, but
399  /// incurs significant execution cost.
400  bool isLoweredToCall(const Function *F) const;
401 
402  struct LSRCost {
403  /// TODO: Some of these could be merged. Also, a lexical ordering
404  /// isn't always optimal.
405  unsigned Insns;
406  unsigned NumRegs;
407  unsigned AddRecCost;
408  unsigned NumIVMuls;
409  unsigned NumBaseAdds;
410  unsigned ImmCost;
411  unsigned SetupCost;
412  unsigned ScaleCost;
413  };
414 
415  /// Parameters that control the generic loop unrolling transformation.
417  /// The cost threshold for the unrolled loop. Should be relative to the
418  /// getInstructionCost values returned by this API, and the expectation is
419  /// that the unrolled loop's instructions when run through that interface
420  /// should not exceed this cost. However, this is only an estimate. Also,
421  /// specific loops may be unrolled even with a cost above this threshold if
422  /// deemed profitable. Set this to UINT_MAX to disable the loop body cost
423  /// restriction.
424  unsigned Threshold;
425  /// If complete unrolling will reduce the cost of the loop, we will boost
426  /// the Threshold by a certain percent to allow more aggressive complete
427  /// unrolling. This value provides the maximum boost percentage that we
428  /// can apply to Threshold (The value should be no less than 100).
429  /// BoostedThreshold = Threshold * min(RolledCost / UnrolledCost,
430  /// MaxPercentThresholdBoost / 100)
431  /// E.g. if complete unrolling reduces the loop execution time by 50%
432  /// then we boost the threshold by the factor of 2x. If unrolling is not
433  /// expected to reduce the running time, then we do not increase the
434  /// threshold.
436  /// The cost threshold for the unrolled loop when optimizing for size (set
437  /// to UINT_MAX to disable).
439  /// The cost threshold for the unrolled loop, like Threshold, but used
440  /// for partial/runtime unrolling (set to UINT_MAX to disable).
442  /// The cost threshold for the unrolled loop when optimizing for size, like
443  /// OptSizeThreshold, but used for partial/runtime unrolling (set to
444  /// UINT_MAX to disable).
446  /// A forced unrolling factor (the number of concatenated bodies of the
447  /// original loop in the unrolled loop body). When set to 0, the unrolling
448  /// transformation will select an unrolling factor based on the current cost
449  /// threshold and other factors.
450  unsigned Count;
451  /// Default unroll count for loops with run-time trip count.
453  // Set the maximum unrolling factor. The unrolling factor may be selected
454  // using the appropriate cost threshold, but may not exceed this number
455  // (set to UINT_MAX to disable). This does not apply in cases where the
456  // loop is being fully unrolled.
457  unsigned MaxCount;
458  /// Set the maximum unrolling factor for full unrolling. Like MaxCount, but
459  /// applies even if full unrolling is selected. This allows a target to fall
460  /// back to Partial unrolling if full unrolling is above FullUnrollMaxCount.
462  // Represents number of instructions optimized when "back edge"
463  // becomes "fall through" in unrolled loop.
464  // For now we count a conditional branch on a backedge and a comparison
465  // feeding it.
466  unsigned BEInsns;
467  /// Allow partial unrolling (unrolling of loops to expand the size of the
468  /// loop body, not only to eliminate small constant-trip-count loops).
469  bool Partial;
470  /// Allow runtime unrolling (unrolling of loops to expand the size of the
471  /// loop body even when the number of loop iterations is not known at
472  /// compile time).
473  bool Runtime;
474  /// Allow generation of a loop remainder (extra iterations after unroll).
476  /// Allow emitting expensive instructions (such as divisions) when computing
477  /// the trip count of a loop for runtime unrolling.
479  /// Apply loop unroll on any kind of loop
480  /// (mainly to loops that fail runtime unrolling).
481  bool Force;
482  /// Allow using trip count upper bound to unroll loops.
484  /// Allow unrolling of all the iterations of the runtime loop remainder.
486  /// Allow unroll and jam. Used to enable unroll and jam for the target.
488  /// Threshold for unroll and jam, for inner loop size. The 'Threshold'
489  /// value above is used during unroll and jam for the outer loop size.
490  /// This value is used in the same manner to limit the size of the inner
491  /// loop.
493  /// Don't allow loop unrolling to simulate more than this number of
494  /// iterations when checking full unroll profitability
496  };
497 
498  /// Get target-customized preferences for the generic loop unrolling
499  /// transformation. The caller will initialize UP with the current
500  /// target-independent defaults.
503  OptimizationRemarkEmitter *ORE) const;
504 
505  /// Query the target whether it would be profitable to convert the given loop
506  /// into a hardware loop.
508  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
509  HardwareLoopInfo &HWLoopInfo) const;
510 
511  /// Query the target whether it would be prefered to create a predicated
512  /// vector loop, which can avoid the need to emit a scalar epilogue loop.
515  DominatorTree *DT,
517  InterleavedAccessInfo *IAI) const;
518 
519  /// Query the target whether lowering of the llvm.get.active.lane.mask
520  /// intrinsic is supported and how the mask should be used. A return value
521  /// of PredicationStyle::Data indicates the mask is used as data only,
522  /// whereas PredicationStyle::DataAndControlFlow indicates we should also use
523  /// the mask for control flow in the loop. If unsupported the return value is
524  /// PredicationStyle::None.
526 
527  // Parameters that control the loop peeling transformation
529  /// A forced peeling factor (the number of bodied of the original loop
530  /// that should be peeled off before the loop body). When set to 0, the
531  /// a peeling factor based on profile information and other factors.
532  unsigned PeelCount;
533  /// Allow peeling off loop iterations.
535  /// Allow peeling off loop iterations for loop nests.
537  /// Allow peeling basing on profile. Uses to enable peeling off all
538  /// iterations basing on provided profile.
539  /// If the value is true the peeling cost model can decide to peel only
540  /// some iterations and in this case it will set this to false.
542  };
543 
544  /// Get target-customized preferences for the generic loop peeling
545  /// transformation. The caller will initialize \p PP with the current
546  /// target-independent defaults with information from \p L and \p SE.
548  PeelingPreferences &PP) const;
549 
550  /// Targets can implement their own combinations for target-specific
551  /// intrinsics. This function will be called from the InstCombine pass every
552  /// time a target-specific intrinsic is encountered.
553  ///
554  /// \returns None to not do anything target specific or a value that will be
555  /// returned from the InstCombiner. It is possible to return null and stop
556  /// further processing of the intrinsic by returning nullptr.
558  IntrinsicInst &II) const;
559  /// Can be used to implement target-specific instruction combining.
560  /// \see instCombineIntrinsic
563  APInt DemandedMask, KnownBits &Known,
564  bool &KnownBitsComputed) const;
565  /// Can be used to implement target-specific instruction combining.
566  /// \see instCombineIntrinsic
568  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
569  APInt &UndefElts2, APInt &UndefElts3,
570  std::function<void(Instruction *, unsigned, APInt, APInt &)>
571  SimplifyAndSetOp) const;
572  /// @}
573 
574  /// \name Scalar Target Information
575  /// @{
576 
577  /// Flags indicating the kind of support for population count.
578  ///
579  /// Compared to the SW implementation, HW support is supposed to
580  /// significantly boost the performance when the population is dense, and it
581  /// may or may not degrade performance if the population is sparse. A HW
582  /// support is considered as "Fast" if it can outperform, or is on a par
583  /// with, SW implementation when the population is sparse; otherwise, it is
584  /// considered as "Slow".
586 
587  /// Return true if the specified immediate is legal add immediate, that
588  /// is the target has add instructions which can add a register with the
589  /// immediate without having to materialize the immediate into a register.
590  bool isLegalAddImmediate(int64_t Imm) const;
591 
592  /// Return true if the specified immediate is legal icmp immediate,
593  /// that is the target has icmp instructions which can compare a register
594  /// against the immediate without having to materialize the immediate into a
595  /// register.
596  bool isLegalICmpImmediate(int64_t Imm) const;
597 
598  /// Return true if the addressing mode represented by AM is legal for
599  /// this target, for a load/store of the specified type.
600  /// The type may be VoidTy, in which case only return true if the addressing
601  /// mode is legal for a load/store of any legal type.
602  /// If target returns true in LSRWithInstrQueries(), I may be valid.
603  /// TODO: Handle pre/postinc as well.
604  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
605  bool HasBaseReg, int64_t Scale,
606  unsigned AddrSpace = 0,
607  Instruction *I = nullptr) const;
608 
609  /// Return true if LSR cost of C1 is lower than C2.
611  const TargetTransformInfo::LSRCost &C2) const;
612 
613  /// Return true if LSR major cost is number of registers. Targets which
614  /// implement their own isLSRCostLess and unset number of registers as major
615  /// cost should return false, otherwise return true.
616  bool isNumRegsMajorCostOfLSR() const;
617 
618  /// \returns true if LSR should not optimize a chain that includes \p I.
620 
621  /// Return true if the target can fuse a compare and branch.
622  /// Loop-strength-reduction (LSR) uses that knowledge to adjust its cost
623  /// calculation for the instructions in a loop.
624  bool canMacroFuseCmp() const;
625 
626  /// Return true if the target can save a compare for loop count, for example
627  /// hardware loop saves a compare.
628  bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
630  TargetLibraryInfo *LibInfo) const;
631 
636  };
637 
638  /// Return the preferred addressing mode LSR should make efforts to generate.
640  ScalarEvolution *SE) const;
641 
642  /// Return true if the target supports masked store.
643  bool isLegalMaskedStore(Type *DataType, Align Alignment) const;
644  /// Return true if the target supports masked load.
645  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const;
646 
647  /// Return true if the target supports nontemporal store.
648  bool isLegalNTStore(Type *DataType, Align Alignment) const;
649  /// Return true if the target supports nontemporal load.
650  bool isLegalNTLoad(Type *DataType, Align Alignment) const;
651 
652  /// \Returns true if the target supports broadcasting a load to a vector of
653  /// type <NumElements x ElementTy>.
654  bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const;
655 
656  /// Return true if the target supports masked scatter.
657  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const;
658  /// Return true if the target supports masked gather.
659  bool isLegalMaskedGather(Type *DataType, Align Alignment) const;
660  /// Return true if the target forces scalarizing of llvm.masked.gather
661  /// intrinsics.
662  bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const;
663  /// Return true if the target forces scalarizing of llvm.masked.scatter
664  /// intrinsics.
665  bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const;
666 
667  /// Return true if the target supports masked compress store.
668  bool isLegalMaskedCompressStore(Type *DataType) const;
669  /// Return true if the target supports masked expand load.
670  bool isLegalMaskedExpandLoad(Type *DataType) const;
671 
672  /// Return true if this is an alternating opcode pattern that can be lowered
673  /// to a single instruction on the target. In X86 this is for the addsub
674  /// instruction which corrsponds to a Shuffle + Fadd + FSub pattern in IR.
675  /// This function expectes two opcodes: \p Opcode1 and \p Opcode2 being
676  /// selected by \p OpcodeMask. The mask contains one bit per lane and is a `0`
677  /// when \p Opcode0 is selected and `1` when Opcode1 is selected.
678  /// \p VecTy is the vector type of the instruction to be generated.
679  bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
680  const SmallBitVector &OpcodeMask) const;
681 
682  /// Return true if we should be enabling ordered reductions for the target.
683  bool enableOrderedReductions() const;
684 
685  /// Return true if the target has a unified operation to calculate division
686  /// and remainder. If so, the additional implicit multiplication and
687  /// subtraction required to calculate a remainder from division are free. This
688  /// can enable more aggressive transformations for division and remainder than
689  /// would typically be allowed using throughput or size cost models.
690  bool hasDivRemOp(Type *DataType, bool IsSigned) const;
691 
692  /// Return true if the given instruction (assumed to be a memory access
693  /// instruction) has a volatile variant. If that's the case then we can avoid
694  /// addrspacecast to generic AS for volatile loads/stores. Default
695  /// implementation returns false, which prevents address space inference for
696  /// volatile loads/stores.
697  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const;
698 
699  /// Return true if target doesn't mind addresses in vectors.
700  bool prefersVectorizedAddressing() const;
701 
702  /// Return the cost of the scaling factor used in the addressing
703  /// mode represented by AM for this target, for a load/store
704  /// of the specified type.
705  /// If the AM is supported, the return value must be >= 0.
706  /// If the AM is not supported, it returns a negative value.
707  /// TODO: Handle pre/postinc as well.
709  int64_t BaseOffset, bool HasBaseReg,
710  int64_t Scale,
711  unsigned AddrSpace = 0) const;
712 
713  /// Return true if the loop strength reduce pass should make
714  /// Instruction* based TTI queries to isLegalAddressingMode(). This is
715  /// needed on SystemZ, where e.g. a memcpy can only have a 12 bit unsigned
716  /// immediate offset and no index register.
717  bool LSRWithInstrQueries() const;
718 
719  /// Return true if it's free to truncate a value of type Ty1 to type
720  /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
721  /// by referencing its sub-register AX.
722  bool isTruncateFree(Type *Ty1, Type *Ty2) const;
723 
724  /// Return true if it is profitable to hoist instruction in the
725  /// then/else to before if.
726  bool isProfitableToHoist(Instruction *I) const;
727 
728  bool useAA() const;
729 
730  /// Return true if this type is legal.
731  bool isTypeLegal(Type *Ty) const;
732 
733  /// Returns the estimated number of registers required to represent \p Ty.
734  unsigned getRegUsageForType(Type *Ty) const;
735 
736  /// Return true if switches should be turned into lookup tables for the
737  /// target.
738  bool shouldBuildLookupTables() const;
739 
740  /// Return true if switches should be turned into lookup tables
741  /// containing this constant value for the target.
743 
744  /// Return true if lookup tables should be turned into relative lookup tables.
745  bool shouldBuildRelLookupTables() const;
746 
747  /// Return true if the input function which is cold at all call sites,
748  /// should use coldcc calling convention.
749  bool useColdCCForColdCall(Function &F) const;
750 
751  /// Estimate the overhead of scalarizing an instruction. Insert and Extract
752  /// are set if the demanded result elements need to be inserted and/or
753  /// extracted from vectors.
755  const APInt &DemandedElts,
756  bool Insert, bool Extract) const;
757 
758  /// Estimate the overhead of scalarizing an instructions unique
759  /// non-constant operands. The (potentially vector) types to use for each of
760  /// argument are passes via Tys.
762  ArrayRef<Type *> Tys) const;
763 
764  /// If target has efficient vector element load/store instructions, it can
765  /// return true here so that insertion/extraction costs are not added to
766  /// the scalarization cost of a load/store.
768 
769  /// If the target supports tail calls.
770  bool supportsTailCalls() const;
771 
772  /// If target supports tail call on \p CB
773  bool supportsTailCallFor(const CallBase *CB) const;
774 
775  /// Don't restrict interleaved unrolling to small loops.
776  bool enableAggressiveInterleaving(bool LoopHasReductions) const;
777 
778  /// Returns options for expansion of memcmp. IsZeroCmp is
779  // true if this is the expansion of memcmp(p1, p2, s) == 0.
781  // Return true if memcmp expansion is enabled.
782  operator bool() const { return MaxNumLoads > 0; }
783 
784  // Maximum number of load operations.
785  unsigned MaxNumLoads = 0;
786 
787  // The list of available load sizes (in bytes), sorted in decreasing order.
789 
790  // For memcmp expansion when the memcmp result is only compared equal or
791  // not-equal to 0, allow up to this number of load pairs per block. As an
792  // example, this may allow 'memcmp(a, b, 3) == 0' in a single block:
793  // a0 = load2bytes &a[0]
794  // b0 = load2bytes &b[0]
795  // a2 = load1byte &a[2]
796  // b2 = load1byte &b[2]
797  // r = cmp eq (a0 ^ b0 | a2 ^ b2), 0
798  unsigned NumLoadsPerBlock = 1;
799 
800  // Set to true to allow overlapping loads. For example, 7-byte compares can
801  // be done with two 4-byte compares instead of 4+2+1-byte compares. This
802  // requires all loads in LoadSizes to be doable in an unaligned way.
803  bool AllowOverlappingLoads = false;
804  };
806  bool IsZeroCmp) const;
807 
808  /// Enable matching of interleaved access groups.
810 
811  /// Enable matching of interleaved access groups that contain predicated
812  /// accesses or gaps and therefore vectorized using masked
813  /// vector loads/stores.
815 
816  /// Indicate that it is potentially unsafe to automatically vectorize
817  /// floating-point operations because the semantics of vector and scalar
818  /// floating-point semantics may differ. For example, ARM NEON v7 SIMD math
819  /// does not support IEEE-754 denormal numbers, while depending on the
820  /// platform, scalar floating-point math does.
821  /// This applies to floating-point math operations and calls, not memory
822  /// operations, shuffles, or casts.
824 
825  /// Determine if the target supports unaligned memory accesses.
827  unsigned AddressSpace = 0,
828  Align Alignment = Align(1),
829  unsigned *Fast = nullptr) const;
830 
831  /// Return hardware support for population count.
832  PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const;
833 
834  /// Return true if the hardware has a fast square-root instruction.
835  bool haveFastSqrt(Type *Ty) const;
836 
837  /// Return true if the cost of the instruction is too high to speculatively
838  /// execute and should be kept behind a branch.
839  /// This normally just wraps around a getInstructionCost() call, but some
840  /// targets might report a low TCK_SizeAndLatency value that is incompatible
841  /// with the fixed TCC_Expensive value.
842  /// NOTE: This assumes the instruction passes isSafeToSpeculativelyExecute().
844 
845  /// Return true if it is faster to check if a floating-point value is NaN
846  /// (or not-NaN) versus a comparison against a constant FP zero value.
847  /// Targets should override this if materializing a 0.0 for comparison is
848  /// generally as cheap as checking for ordered/unordered.
849  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const;
850 
851  /// Return the expected cost of supporting the floating point operation
852  /// of the specified type.
853  InstructionCost getFPOpCost(Type *Ty) const;
854 
855  /// Return the expected cost of materializing for the given integer
856  /// immediate of the specified type.
858  TargetCostKind CostKind) const;
859 
860  /// Return the expected cost of materialization for the given integer
861  /// immediate of the specified type for a given instruction. The cost can be
862  /// zero if the immediate can be folded into the specified instruction.
863  InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx,
864  const APInt &Imm, Type *Ty,
866  Instruction *Inst = nullptr) const;
868  const APInt &Imm, Type *Ty,
869  TargetCostKind CostKind) const;
870 
871  /// Return the expected cost for the given integer when optimising
872  /// for size. This is different than the other integer immediate cost
873  /// functions in that it is subtarget agnostic. This is useful when you e.g.
874  /// target one ISA such as Aarch32 but smaller encodings could be possible
875  /// with another such as Thumb. This return value is used as a penalty when
876  /// the total costs for a constant is calculated (the bigger the cost, the
877  /// more beneficial constant hoisting is).
878  InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,
879  const APInt &Imm, Type *Ty) const;
880  /// @}
881 
882  /// \name Vector Target Information
883  /// @{
884 
885  /// The various kinds of shuffle patterns for vector queries.
886  enum ShuffleKind {
887  SK_Broadcast, ///< Broadcast element 0 to all other elements.
888  SK_Reverse, ///< Reverse the order of the vector.
889  SK_Select, ///< Selects elements from the corresponding lane of
890  ///< either source operand. This is equivalent to a
891  ///< vector select with a constant condition operand.
892  SK_Transpose, ///< Transpose two vectors.
893  SK_InsertSubvector, ///< InsertSubvector. Index indicates start offset.
894  SK_ExtractSubvector, ///< ExtractSubvector Index indicates start offset.
895  SK_PermuteTwoSrc, ///< Merge elements from two source vectors into one
896  ///< with any shuffle mask.
897  SK_PermuteSingleSrc, ///< Shuffle elements of single source vector with any
898  ///< shuffle mask.
899  SK_Splice ///< Concatenates elements from the first input vector
900  ///< with elements of the second input vector. Returning
901  ///< a vector of the same type as the input vectors.
902  ///< Index indicates start offset in first input vector.
903  };
904 
905  /// Additional information about an operand's possible values.
907  OK_AnyValue, // Operand can have any value.
908  OK_UniformValue, // Operand is uniform (splat of a value).
909  OK_UniformConstantValue, // Operand is uniform constant.
910  OK_NonUniformConstantValue // Operand is a non uniform constant value.
911  };
912 
913  /// Additional properties of an operand's values.
915  OP_None = 0,
918  };
919 
920  // Describe the values an operand can take. We're in the process
921  // of migrating uses of OperandValueKind and OperandValueProperties
922  // to use this class, and then will change the internal representation.
926 
927  bool isConstant() const {
929  }
930  bool isUniform() const {
932  }
933  bool isPowerOf2() const {
934  return Properties == OP_PowerOf2;
935  }
936  bool isNegatedPowerOf2() const {
937  return Properties == OP_NegatedPowerOf2;
938  }
939 
941  return {Kind, OP_None};
942  }
943  };
944 
945  /// \return the number of registers in the target-provided register class.
946  unsigned getNumberOfRegisters(unsigned ClassID) const;
947 
948  /// \return the target-provided register class ID for the provided type,
949  /// accounting for type promotion and other type-legalization techniques that
950  /// the target might apply. However, it specifically does not account for the
951  /// scalarization or splitting of vector types. Should a vector type require
952  /// scalarization or splitting into multiple underlying vector registers, that
953  /// type should be mapped to a register class containing no registers.
954  /// Specifically, this is designed to provide a simple, high-level view of the
955  /// register allocation later performed by the backend. These register classes
956  /// don't necessarily map onto the register classes used by the backend.
957  /// FIXME: It's not currently possible to determine how many registers
958  /// are used by the provided type.
959  unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const;
960 
961  /// \return the target-provided register class name
962  const char *getRegisterClassName(unsigned ClassID) const;
963 
965 
966  /// \return The width of the largest scalar or vector register type.
968 
969  /// \return The width of the smallest vector register type.
970  unsigned getMinVectorRegisterBitWidth() const;
971 
972  /// \return The maximum value of vscale if the target specifies an
973  /// architectural maximum vector length, and None otherwise.
975 
976  /// \return the value of vscale to tune the cost model for.
978 
979  /// \return True if the vectorization factor should be chosen to
980  /// make the vector of the smallest element type match the size of a
981  /// vector register. For wider element types, this could result in
982  /// creating vectors that span multiple vector registers.
983  /// If false, the vectorization factor will be chosen based on the
984  /// size of the widest element type.
985  /// \p K Register Kind for vectorization.
987 
988  /// \return The minimum vectorization factor for types of given element
989  /// bit width, or 0 if there is no minimum VF. The returned value only
990  /// applies when shouldMaximizeVectorBandwidth returns true.
991  /// If IsScalable is true, the returned ElementCount must be a scalable VF.
992  ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const;
993 
994  /// \return The maximum vectorization factor for types of given element
995  /// bit width and opcode, or 0 if there is no maximum VF.
996  /// Currently only used by the SLP vectorizer.
997  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
998 
999  /// \return The minimum vectorization factor for the store instruction. Given
1000  /// the initial estimation of the minimum vector factor and store value type,
1001  /// it tries to find possible lowest VF, which still might be profitable for
1002  /// the vectorization.
1003  /// \param VF Initial estimation of the minimum vector factor.
1004  /// \param ScalarMemTy Scalar memory type of the store operation.
1005  /// \param ScalarValTy Scalar type of the stored value.
1006  /// Currently only used by the SLP vectorizer.
1007  unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
1008  Type *ScalarValTy) const;
1009 
1010  /// \return True if it should be considered for address type promotion.
1011  /// \p AllowPromotionWithoutCommonHeader Set true if promoting \p I is
1012  /// profitable without finding other extensions fed by the same input.
1014  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const;
1015 
1016  /// \return The size of a cache line in bytes.
1017  unsigned getCacheLineSize() const;
1018 
1019  /// The possible cache levels
1020  enum class CacheLevel {
1021  L1D, // The L1 data cache
1022  L2D, // The L2 data cache
1023 
1024  // We currently do not model L3 caches, as their sizes differ widely between
1025  // microarchitectures. Also, we currently do not have a use for L3 cache
1026  // size modeling yet.
1027  };
1028 
1029  /// \return The size of the cache level in bytes, if available.
1031 
1032  /// \return The associativity of the cache level, if available.
1034 
1035  /// \return How much before a load we should place the prefetch
1036  /// instruction. This is currently measured in number of
1037  /// instructions.
1038  unsigned getPrefetchDistance() const;
1039 
1040  /// Some HW prefetchers can handle accesses up to a certain constant stride.
1041  /// Sometimes prefetching is beneficial even below the HW prefetcher limit,
1042  /// and the arguments provided are meant to serve as a basis for deciding this
1043  /// for a particular loop.
1044  ///
1045  /// \param NumMemAccesses Number of memory accesses in the loop.
1046  /// \param NumStridedMemAccesses Number of the memory accesses that
1047  /// ScalarEvolution could find a known stride
1048  /// for.
1049  /// \param NumPrefetches Number of software prefetches that will be
1050  /// emitted as determined by the addresses
1051  /// involved and the cache line size.
1052  /// \param HasCall True if the loop contains a call.
1053  ///
1054  /// \return This is the minimum stride in bytes where it makes sense to start
1055  /// adding SW prefetches. The default is 1, i.e. prefetch with any
1056  /// stride.
1057  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
1058  unsigned NumStridedMemAccesses,
1059  unsigned NumPrefetches, bool HasCall) const;
1060 
1061  /// \return The maximum number of iterations to prefetch ahead. If
1062  /// the required number of iterations is more than this number, no
1063  /// prefetching is performed.
1064  unsigned getMaxPrefetchIterationsAhead() const;
1065 
1066  /// \return True if prefetching should also be done for writes.
1067  bool enableWritePrefetching() const;
1068 
1069  /// \return if target want to issue a prefetch in address space \p AS.
1070  bool shouldPrefetchAddressSpace(unsigned AS) const;
1071 
1072  /// \return The maximum interleave factor that any transform should try to
1073  /// perform for this target. This number depends on the level of parallelism
1074  /// and the number of execution units in the CPU.
1075  unsigned getMaxInterleaveFactor(unsigned VF) const;
1076 
1077  /// Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
1078  static OperandValueInfo getOperandInfo(const Value *V);
1079 
1080  /// This is an approximation of reciprocal throughput of a math/logic op.
1081  /// A higher cost indicates less expected throughput.
1082  /// From Agner Fog's guides, reciprocal throughput is "the average number of
1083  /// clock cycles per instruction when the instructions are not part of a
1084  /// limiting dependency chain."
1085  /// Therefore, costs should be scaled to account for multiple execution units
1086  /// on the target that can process this type of instruction. For example, if
1087  /// there are 5 scalar integer units and 2 vector integer units that can
1088  /// calculate an 'add' in a single cycle, this model should indicate that the
1089  /// cost of the vector add instruction is 2.5 times the cost of the scalar
1090  /// add instruction.
1091  /// \p Args is an optional argument which holds the instruction operands
1092  /// values so the TTI can analyze those values searching for special
1093  /// cases or optimizations based on those values.
1094  /// \p CxtI is the optional original context instruction, if one exists, to
1095  /// provide even more information.
1097  unsigned Opcode, Type *Ty,
1100  TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None},
1101  ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
1102  const Instruction *CxtI = nullptr) const;
1103 
1104  /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
1105  /// The exact mask may be passed as Mask, or else the array will be empty.
1106  /// The index and subtype parameters are used by the subvector insertion and
1107  /// extraction shuffle kinds to show the insert/extract point and the type of
1108  /// the subvector being inserted/extracted. The operands of the shuffle can be
1109  /// passed through \p Args, which helps improve the cost estimation in some
1110  /// cases, like in broadcast loads.
1111  /// NOTE: For subvector extractions Tp represents the source type.
1112  InstructionCost
1113  getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef<int> Mask = None,
1115  int Index = 0, VectorType *SubTp = nullptr,
1116  ArrayRef<const Value *> Args = None) const;
1117 
1118  /// Represents a hint about the context in which a cast is used.
1119  ///
1120  /// For zext/sext, the context of the cast is the operand, which must be a
1121  /// load of some kind. For trunc, the context is of the cast is the single
1122  /// user of the instruction, which must be a store of some kind.
1123  ///
1124  /// This enum allows the vectorizer to give getCastInstrCost an idea of the
1125  /// type of cast it's dealing with, as not every cast is equal. For instance,
1126  /// the zext of a load may be free, but the zext of an interleaving load can
1127  //// be (very) expensive!
1128  ///
1129  /// See \c getCastContextHint to compute a CastContextHint from a cast
1130  /// Instruction*. Callers can use it if they don't need to override the
1131  /// context and just want it to be calculated from the instruction.
1132  ///
1133  /// FIXME: This handles the types of load/store that the vectorizer can
1134  /// produce, which are the cases where the context instruction is most
1135  /// likely to be incorrect. There are other situations where that can happen
1136  /// too, which might be handled here but in the long run a more general
1137  /// solution of costing multiple instructions at the same times may be better.
1138  enum class CastContextHint : uint8_t {
1139  None, ///< The cast is not used with a load/store of any kind.
1140  Normal, ///< The cast is used with a normal load/store.
1141  Masked, ///< The cast is used with a masked load/store.
1142  GatherScatter, ///< The cast is used with a gather/scatter.
1143  Interleave, ///< The cast is used with an interleaved load/store.
1144  Reversed, ///< The cast is used with a reversed load/store.
1145  };
1146 
1147  /// Calculates a CastContextHint from \p I.
1148  /// This should be used by callers of getCastInstrCost if they wish to
1149  /// determine the context from some instruction.
1150  /// \returns the CastContextHint for ZExt/SExt/Trunc, None if \p I is nullptr,
1151  /// or if it's another type of cast.
1153 
1154  /// \return The expected cost of cast instructions, such as bitcast, trunc,
1155  /// zext, etc. If there is an existing instruction that holds Opcode, it
1156  /// may be passed in the 'I' parameter.
1158  getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
1161  const Instruction *I = nullptr) const;
1162 
1163  /// \return The expected cost of a sign- or zero-extended vector extract. Use
1164  /// Index = -1 to indicate that there is no information about the index value.
1165  InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
1166  VectorType *VecTy,
1167  unsigned Index) const;
1168 
1169  /// \return The expected cost of control-flow related instructions such as
1170  /// Phi, Ret, Br, Switch.
1172  getCFInstrCost(unsigned Opcode,
1174  const Instruction *I = nullptr) const;
1175 
1176  /// \returns The expected cost of compare and select instructions. If there
1177  /// is an existing instruction that holds Opcode, it may be passed in the
1178  /// 'I' parameter. The \p VecPred parameter can be used to indicate the select
1179  /// is using a compare with the specified predicate as condition. When vector
1180  /// types are passed, \p VecPred must be used for all lanes.
1182  getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
1183  CmpInst::Predicate VecPred,
1185  const Instruction *I = nullptr) const;
1186 
1187  /// \return The expected cost of vector Insert and Extract.
1188  /// Use -1 to indicate that there is no information on the index value.
1189  /// This is used when the instruction is not available; a typical use
1190  /// case is to provision the cost of vectorization/scalarization in
1191  /// vectorizer passes.
1192  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
1193  unsigned Index = -1) const;
1194 
1195  /// \return The expected cost of vector Insert and Extract.
1196  /// This is used when instruction is available, and implementation
1197  /// asserts 'I' is not nullptr.
1198  ///
1199  /// A typical suitable use case is cost estimation when vector instruction
1200  /// exists (e.g., from basic blocks during transformation).
1202  unsigned Index = -1) const;
1203 
1204  /// \return The cost of replication shuffle of \p VF elements typed \p EltTy
1205  /// \p ReplicationFactor times.
1206  ///
1207  /// For example, the mask for \p ReplicationFactor=3 and \p VF=4 is:
1208  /// <0,0,0,1,1,1,2,2,2,3,3,3>
1209  InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
1210  int VF,
1211  const APInt &DemandedDstElts,
1213 
1214  /// \return The cost of Load and Store instructions.
1216  getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
1217  unsigned AddressSpace,
1219  OperandValueInfo OpdInfo = {OK_AnyValue, OP_None},
1220  const Instruction *I = nullptr) const;
1221 
1222  /// \return The cost of VP Load and Store instructions.
1223  InstructionCost
1224  getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
1225  unsigned AddressSpace,
1227  const Instruction *I = nullptr) const;
1228 
1229  /// \return The cost of masked Load and Store instructions.
1230  InstructionCost getMaskedMemoryOpCost(
1231  unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
1233 
1234  /// \return The cost of Gather or Scatter operation
1235  /// \p Opcode - is a type of memory access Load or Store
1236  /// \p DataTy - a vector type of the data to be loaded or stored
1237  /// \p Ptr - pointer [or vector of pointers] - address[es] in memory
1238  /// \p VariableMask - true when the memory access is predicated with a mask
1239  /// that is not a compile-time constant
1240  /// \p Alignment - alignment of single element
1241  /// \p I - the optional original context instruction, if one exists, e.g. the
1242  /// load/store to transform or the call to the gather/scatter intrinsic
1243  InstructionCost getGatherScatterOpCost(
1244  unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
1246  const Instruction *I = nullptr) const;
1247 
1248  /// \return The cost of the interleaved memory operation.
1249  /// \p Opcode is the memory operation code
1250  /// \p VecTy is the vector type of the interleaved access.
1251  /// \p Factor is the interleave factor
1252  /// \p Indices is the indices for interleaved load members (as interleaved
1253  /// load allows gaps)
1254  /// \p Alignment is the alignment of the memory operation
1255  /// \p AddressSpace is address space of the pointer.
1256  /// \p UseMaskForCond indicates if the memory access is predicated.
1257  /// \p UseMaskForGaps indicates if gaps should be masked.
1258  InstructionCost getInterleavedMemoryOpCost(
1259  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1260  Align Alignment, unsigned AddressSpace,
1262  bool UseMaskForCond = false, bool UseMaskForGaps = false) const;
1263 
1264  /// A helper function to determine the type of reduction algorithm used
1265  /// for a given \p Opcode and set of FastMathFlags \p FMF.
1267  return FMF != None && !(*FMF).allowReassoc();
1268  }
1269 
1270  /// Calculate the cost of vector reduction intrinsics.
1271  ///
1272  /// This is the cost of reducing the vector value of type \p Ty to a scalar
1273  /// value using the operation denoted by \p Opcode. The FastMathFlags
1274  /// parameter \p FMF indicates what type of reduction we are performing:
1275  /// 1. Tree-wise. This is the typical 'fast' reduction performed that
1276  /// involves successively splitting a vector into half and doing the
1277  /// operation on the pair of halves until you have a scalar value. For
1278  /// example:
1279  /// (v0, v1, v2, v3)
1280  /// ((v0+v2), (v1+v3), undef, undef)
1281  /// ((v0+v2+v1+v3), undef, undef, undef)
1282  /// This is the default behaviour for integer operations, whereas for
1283  /// floating point we only do this if \p FMF indicates that
1284  /// reassociation is allowed.
1285  /// 2. Ordered. For a vector with N elements this involves performing N
1286  /// operations in lane order, starting with an initial scalar value, i.e.
1287  /// result = InitVal + v0
1288  /// result = result + v1
1289  /// result = result + v2
1290  /// result = result + v3
1291  /// This is only the case for FP operations and when reassociation is not
1292  /// allowed.
1293  ///
1295  unsigned Opcode, VectorType *Ty, Optional<FastMathFlags> FMF,
1297 
1299  VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
1301 
1302  /// Calculate the cost of an extended reduction pattern, similar to
1303  /// getArithmeticReductionCost of an Add reduction with multiply and optional
1304  /// extensions. This is the cost of as:
1305  /// ResTy vecreduce.add(mul (A, B)).
1306  /// ResTy vecreduce.add(mul(ext(Ty A), ext(Ty B)).
1308  bool IsUnsigned, Type *ResTy, VectorType *Ty,
1310 
1311  /// Calculate the cost of an extended reduction pattern, similar to
1312  /// getArithmeticReductionCost of a reduction with an extension.
1313  /// This is the cost of as:
1314  /// ResTy vecreduce.opcode(ext(Ty A)).
1316  unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1319 
1320  /// \returns The cost of Intrinsic instructions. Analyses the real arguments.
1321  /// Three cases are handled: 1. scalar instruction 2. vector instruction
1322  /// 3. scalar instruction which is to be vectorized.
1325 
1326  /// \returns The cost of Call instructions.
1328  Function *F, Type *RetTy, ArrayRef<Type *> Tys,
1330 
1331  /// \returns The number of pieces into which the provided type must be
1332  /// split during legalization. Zero is returned when the answer is unknown.
1333  unsigned getNumberOfParts(Type *Tp) const;
1334 
1335  /// \returns The cost of the address computation. For most targets this can be
1336  /// merged into the instruction indexing mode. Some targets might want to
1337  /// distinguish between address computation for memory operations on vector
1338  /// types and scalar types. Such targets should override this function.
1339  /// The 'SE' parameter holds pointer for the scalar evolution object which
1340  /// is used in order to get the Ptr step value in case of constant stride.
1341  /// The 'Ptr' parameter holds SCEV of the access pointer.
1343  ScalarEvolution *SE = nullptr,
1344  const SCEV *Ptr = nullptr) const;
1345 
1346  /// \returns The cost, if any, of keeping values of the given types alive
1347  /// over a callsite.
1348  ///
1349  /// Some types may require the use of register classes that do not have
1350  /// any callee-saved registers, so would require a spill and fill.
1352 
1353  /// \returns True if the intrinsic is a supported memory intrinsic. Info
1354  /// will contain additional information - whether the intrinsic may write
1355  /// or read to memory, volatility and the pointer. Info is undefined
1356  /// if false is returned.
1358 
1359  /// \returns The maximum element size, in bytes, for an element
1360  /// unordered-atomic memory intrinsic.
1361  unsigned getAtomicMemIntrinsicMaxElementSize() const;
1362 
1363  /// \returns A value which is the result of the given memory intrinsic. New
1364  /// instructions may be created to extract the result from the given intrinsic
1365  /// memory operation. Returns nullptr if the target cannot create a result
1366  /// from the given intrinsic.
1368  Type *ExpectedType) const;
1369 
1370  /// \returns The type to use in a loop expansion of a memcpy call.
1371  Type *
1373  unsigned SrcAddrSpace, unsigned DestAddrSpace,
1374  unsigned SrcAlign, unsigned DestAlign,
1375  Optional<uint32_t> AtomicElementSize = None) const;
1376 
1377  /// \param[out] OpsOut The operand types to copy RemainingBytes of memory.
1378  /// \param RemainingBytes The number of bytes to copy.
1379  ///
1380  /// Calculates the operand types to use when copying \p RemainingBytes of
1381  /// memory, where source and destination alignments are \p SrcAlign and
1382  /// \p DestAlign respectively.
1385  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1386  unsigned SrcAlign, unsigned DestAlign,
1387  Optional<uint32_t> AtomicCpySize = None) const;
1388 
1389  /// \returns True if the two functions have compatible attributes for inlining
1390  /// purposes.
1391  bool areInlineCompatible(const Function *Caller,
1392  const Function *Callee) const;
1393 
1394  /// \returns True if the caller and callee agree on how \p Types will be
1395  /// passed to or returned from the callee.
1396  /// to the callee.
1397  /// \param Types List of types to check.
1398  bool areTypesABICompatible(const Function *Caller, const Function *Callee,
1399  const ArrayRef<Type *> &Types) const;
1400 
1401  /// The type of load/store indexing.
1403  MIM_Unindexed, ///< No indexing.
1404  MIM_PreInc, ///< Pre-incrementing.
1405  MIM_PreDec, ///< Pre-decrementing.
1406  MIM_PostInc, ///< Post-incrementing.
1407  MIM_PostDec ///< Post-decrementing.
1408  };
1409 
1410  /// \returns True if the specified indexed load for the given type is legal.
1411  bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const;
1412 
1413  /// \returns True if the specified indexed store for the given type is legal.
1414  bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const;
1415 
1416  /// \returns The bitwidth of the largest vector type that should be used to
1417  /// load/store in the given address space.
1418  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
1419 
1420  /// \returns True if the load instruction is legal to vectorize.
1421  bool isLegalToVectorizeLoad(LoadInst *LI) const;
1422 
1423  /// \returns True if the store instruction is legal to vectorize.
1424  bool isLegalToVectorizeStore(StoreInst *SI) const;
1425 
1426  /// \returns True if it is legal to vectorize the given load chain.
1427  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
1428  unsigned AddrSpace) const;
1429 
1430  /// \returns True if it is legal to vectorize the given store chain.
1431  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
1432  unsigned AddrSpace) const;
1433 
1434  /// \returns True if it is legal to vectorize the given reduction kind.
1436  ElementCount VF) const;
1437 
1438  /// \returns True if the given type is supported for scalable vectors
1439  bool isElementTypeLegalForScalableVector(Type *Ty) const;
1440 
1441  /// \returns The new vector factor value if the target doesn't support \p
1442  /// SizeInBytes loads or has a better vector factor.
1443  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
1444  unsigned ChainSizeInBytes,
1445  VectorType *VecTy) const;
1446 
1447  /// \returns The new vector factor value if the target doesn't support \p
1448  /// SizeInBytes stores or has a better vector factor.
1449  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
1450  unsigned ChainSizeInBytes,
1451  VectorType *VecTy) const;
1452 
1453  /// Flags describing the kind of vector reduction.
1455  ReductionFlags() = default;
1456  bool IsMaxOp =
1457  false; ///< If the op a min/max kind, true if it's a max operation.
1458  bool IsSigned = false; ///< Whether the operation is a signed int reduction.
1459  bool NoNaN =
1460  false; ///< If op is an fp min/max, whether NaNs may be present.
1461  };
1462 
1463  /// \returns True if the target prefers reductions in loop.
1464  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
1465  ReductionFlags Flags) const;
1466 
1467  /// \returns True if the target prefers reductions select kept in the loop
1468  /// when tail folding. i.e.
1469  /// loop:
1470  /// p = phi (0, s)
1471  /// a = add (p, x)
1472  /// s = select (mask, a, p)
1473  /// vecreduce.add(s)
1474  ///
1475  /// As opposed to the normal scheme of p = phi (0, a) which allows the select
1476  /// to be pulled out of the loop. If the select(.., add, ..) can be predicated
1477  /// by the target, this can lead to cleaner code generation.
1478  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
1479  ReductionFlags Flags) const;
1480 
1481  /// Return true if the loop vectorizer should consider vectorizing an
1482  /// otherwise scalar epilogue loop.
1483  bool preferEpilogueVectorization() const;
1484 
1485  /// \returns True if the target wants to expand the given reduction intrinsic
1486  /// into a shuffle sequence.
1487  bool shouldExpandReduction(const IntrinsicInst *II) const;
1488 
1489  /// \returns the size cost of rematerializing a GlobalValue address relative
1490  /// to a stack reload.
1491  unsigned getGISelRematGlobalCost() const;
1492 
1493  /// \returns the lower bound of a trip count to decide on vectorization
1494  /// while tail-folding.
1495  unsigned getMinTripCountTailFoldingThreshold() const;
1496 
1497  /// \returns True if the target supports scalable vectors.
1498  bool supportsScalableVectors() const;
1499 
1500  /// \return true when scalable vectorization is preferred.
1501  bool enableScalableVectorization() const;
1502 
1503  /// \name Vector Predication Information
1504  /// @{
1505  /// Whether the target supports the %evl parameter of VP intrinsic efficiently
1506  /// in hardware, for the given opcode and type/alignment. (see LLVM Language
1507  /// Reference - "Vector Predication Intrinsics").
1508  /// Use of %evl is discouraged when that is not the case.
1509  bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
1510  Align Alignment) const;
1511 
1514  // keep the predicating parameter
1515  Legal = 0,
1516  // where legal, discard the predicate parameter
1517  Discard = 1,
1518  // transform into something else that is also predicating
1520  };
1521 
1522  // How to transform the EVL parameter.
1523  // Legal: keep the EVL parameter as it is.
1524  // Discard: Ignore the EVL parameter where it is safe to do so.
1525  // Convert: Fold the EVL into the mask parameter.
1527 
1528  // How to transform the operator.
1529  // Legal: The target supports this operator.
1530  // Convert: Convert this to a non-VP operation.
1531  // The 'Discard' strategy is invalid.
1533 
1534  bool shouldDoNothing() const {
1535  return (EVLParamStrategy == Legal) && (OpStrategy == Legal);
1536  }
1539  };
1540 
1541  /// \returns How the target needs this vector-predicated operation to be
1542  /// transformed.
1544  /// @}
1545 
1546  /// @}
1547 
1548 private:
1549  /// The abstract base class used to type erase specific TTI
1550  /// implementations.
1551  class Concept;
1552 
1553  /// The template model for the base class which wraps a concrete
1554  /// implementation in a type erased interface.
1555  template <typename T> class Model;
1556 
1557  std::unique_ptr<Concept> TTIImpl;
1558 };
1559 
1561 public:
1562  virtual ~Concept() = 0;
1563  virtual const DataLayout &getDataLayout() const = 0;
1564  virtual InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
1567  virtual unsigned getInliningThresholdMultiplier() = 0;
1568  virtual unsigned adjustInliningThreshold(const CallBase *CB) = 0;
1569  virtual int getInlinerVectorBonusPercent() = 0;
1570  virtual InstructionCost getMemcpyCost(const Instruction *I) = 0;
1571  virtual unsigned
1572  getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize,
1573  ProfileSummaryInfo *PSI,
1574  BlockFrequencyInfo *BFI) = 0;
1575  virtual InstructionCost getInstructionCost(const User *U,
1577  TargetCostKind CostKind) = 0;
1579  virtual bool hasBranchDivergence() = 0;
1580  virtual bool useGPUDivergenceAnalysis() = 0;
1581  virtual bool isSourceOfDivergence(const Value *V) = 0;
1582  virtual bool isAlwaysUniform(const Value *V) = 0;
1583  virtual unsigned getFlatAddressSpace() = 0;
1584  virtual bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
1585  Intrinsic::ID IID) const = 0;
1586  virtual bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const = 0;
1587  virtual bool
1588  canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const = 0;
1589  virtual unsigned getAssumedAddrSpace(const Value *V) const = 0;
1590  virtual bool isSingleThreaded() const = 0;
1591  virtual std::pair<const Value *, unsigned>
1592  getPredicatedAddrSpace(const Value *V) const = 0;
1594  Value *OldV,
1595  Value *NewV) const = 0;
1596  virtual bool isLoweredToCall(const Function *F) = 0;
1597  virtual void getUnrollingPreferences(Loop *L, ScalarEvolution &,
1599  OptimizationRemarkEmitter *ORE) = 0;
1600  virtual void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
1601  PeelingPreferences &PP) = 0;
1602  virtual bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
1603  AssumptionCache &AC,
1604  TargetLibraryInfo *LibInfo,
1605  HardwareLoopInfo &HWLoopInfo) = 0;
1606  virtual bool
1610  InterleavedAccessInfo *IAI) = 0;
1613  IntrinsicInst &II) = 0;
1614  virtual Optional<Value *>
1616  APInt DemandedMask, KnownBits &Known,
1617  bool &KnownBitsComputed) = 0;
1619  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
1620  APInt &UndefElts2, APInt &UndefElts3,
1621  std::function<void(Instruction *, unsigned, APInt, APInt &)>
1622  SimplifyAndSetOp) = 0;
1623  virtual bool isLegalAddImmediate(int64_t Imm) = 0;
1624  virtual bool isLegalICmpImmediate(int64_t Imm) = 0;
1625  virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
1626  int64_t BaseOffset, bool HasBaseReg,
1627  int64_t Scale, unsigned AddrSpace,
1628  Instruction *I) = 0;
1629  virtual bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
1630  const TargetTransformInfo::LSRCost &C2) = 0;
1631  virtual bool isNumRegsMajorCostOfLSR() = 0;
1632  virtual bool isProfitableLSRChainElement(Instruction *I) = 0;
1633  virtual bool canMacroFuseCmp() = 0;
1634  virtual bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE,
1635  LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC,
1636  TargetLibraryInfo *LibInfo) = 0;
1637  virtual AddressingModeKind
1638  getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const = 0;
1639  virtual bool isLegalMaskedStore(Type *DataType, Align Alignment) = 0;
1640  virtual bool isLegalMaskedLoad(Type *DataType, Align Alignment) = 0;
1641  virtual bool isLegalNTStore(Type *DataType, Align Alignment) = 0;
1642  virtual bool isLegalNTLoad(Type *DataType, Align Alignment) = 0;
1643  virtual bool isLegalBroadcastLoad(Type *ElementTy,
1644  ElementCount NumElements) const = 0;
1645  virtual bool isLegalMaskedScatter(Type *DataType, Align Alignment) = 0;
1646  virtual bool isLegalMaskedGather(Type *DataType, Align Alignment) = 0;
1647  virtual bool forceScalarizeMaskedGather(VectorType *DataType,
1648  Align Alignment) = 0;
1649  virtual bool forceScalarizeMaskedScatter(VectorType *DataType,
1650  Align Alignment) = 0;
1651  virtual bool isLegalMaskedCompressStore(Type *DataType) = 0;
1652  virtual bool isLegalMaskedExpandLoad(Type *DataType) = 0;
1653  virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0,
1654  unsigned Opcode1,
1655  const SmallBitVector &OpcodeMask) const = 0;
1656  virtual bool enableOrderedReductions() = 0;
1657  virtual bool hasDivRemOp(Type *DataType, bool IsSigned) = 0;
1658  virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0;
1659  virtual bool prefersVectorizedAddressing() = 0;
1661  int64_t BaseOffset,
1662  bool HasBaseReg, int64_t Scale,
1663  unsigned AddrSpace) = 0;
1664  virtual bool LSRWithInstrQueries() = 0;
1665  virtual bool isTruncateFree(Type *Ty1, Type *Ty2) = 0;
1666  virtual bool isProfitableToHoist(Instruction *I) = 0;
1667  virtual bool useAA() = 0;
1668  virtual bool isTypeLegal(Type *Ty) = 0;
1669  virtual unsigned getRegUsageForType(Type *Ty) = 0;
1670  virtual bool shouldBuildLookupTables() = 0;
1671  virtual bool shouldBuildLookupTablesForConstant(Constant *C) = 0;
1672  virtual bool shouldBuildRelLookupTables() = 0;
1673  virtual bool useColdCCForColdCall(Function &F) = 0;
1675  const APInt &DemandedElts,
1676  bool Insert,
1677  bool Extract) = 0;
1678  virtual InstructionCost
1680  ArrayRef<Type *> Tys) = 0;
1681  virtual bool supportsEfficientVectorElementLoadStore() = 0;
1682  virtual bool supportsTailCalls() = 0;
1683  virtual bool supportsTailCallFor(const CallBase *CB) = 0;
1684  virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
1685  virtual MemCmpExpansionOptions
1686  enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const = 0;
1687  virtual bool enableInterleavedAccessVectorization() = 0;
1688  virtual bool enableMaskedInterleavedAccessVectorization() = 0;
1689  virtual bool isFPVectorizationPotentiallyUnsafe() = 0;
1691  unsigned BitWidth,
1692  unsigned AddressSpace,
1693  Align Alignment,
1694  unsigned *Fast) = 0;
1695  virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) = 0;
1696  virtual bool haveFastSqrt(Type *Ty) = 0;
1697  virtual bool isExpensiveToSpeculativelyExecute(const Instruction *I) = 0;
1698  virtual bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) = 0;
1699  virtual InstructionCost getFPOpCost(Type *Ty) = 0;
1700  virtual InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,
1701  const APInt &Imm, Type *Ty) = 0;
1702  virtual InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
1703  TargetCostKind CostKind) = 0;
1704  virtual InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx,
1705  const APInt &Imm, Type *Ty,
1707  Instruction *Inst = nullptr) = 0;
1708  virtual InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
1709  const APInt &Imm, Type *Ty,
1710  TargetCostKind CostKind) = 0;
1711  virtual unsigned getNumberOfRegisters(unsigned ClassID) const = 0;
1712  virtual unsigned getRegisterClassForType(bool Vector,
1713  Type *Ty = nullptr) const = 0;
1714  virtual const char *getRegisterClassName(unsigned ClassID) const = 0;
1715  virtual TypeSize getRegisterBitWidth(RegisterKind K) const = 0;
1716  virtual unsigned getMinVectorRegisterBitWidth() const = 0;
1717  virtual Optional<unsigned> getMaxVScale() const = 0;
1718  virtual Optional<unsigned> getVScaleForTuning() const = 0;
1719  virtual bool
1721  virtual ElementCount getMinimumVF(unsigned ElemWidth,
1722  bool IsScalable) const = 0;
1723  virtual unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const = 0;
1724  virtual unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
1725  Type *ScalarValTy) const = 0;
1727  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) = 0;
1728  virtual unsigned getCacheLineSize() const = 0;
1729  virtual Optional<unsigned> getCacheSize(CacheLevel Level) const = 0;
1730  virtual Optional<unsigned> getCacheAssociativity(CacheLevel Level) const = 0;
1731 
1732  /// \return How much before a load we should place the prefetch
1733  /// instruction. This is currently measured in number of
1734  /// instructions.
1735  virtual unsigned getPrefetchDistance() const = 0;
1736 
1737  /// \return Some HW prefetchers can handle accesses up to a certain
1738  /// constant stride. This is the minimum stride in bytes where it
1739  /// makes sense to start adding SW prefetches. The default is 1,
1740  /// i.e. prefetch with any stride. Sometimes prefetching is beneficial
1741  /// even below the HW prefetcher limit, and the arguments provided are
1742  /// meant to serve as a basis for deciding this for a particular loop.
1743  virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses,
1744  unsigned NumStridedMemAccesses,
1745  unsigned NumPrefetches,
1746  bool HasCall) const = 0;
1747 
1748  /// \return The maximum number of iterations to prefetch ahead. If
1749  /// the required number of iterations is more than this number, no
1750  /// prefetching is performed.
1751  virtual unsigned getMaxPrefetchIterationsAhead() const = 0;
1752 
1753  /// \return True if prefetching should also be done for writes.
1754  virtual bool enableWritePrefetching() const = 0;
1755 
1756  /// \return if target want to issue a prefetch in address space \p AS.
1757  virtual bool shouldPrefetchAddressSpace(unsigned AS) const = 0;
1758 
1759  virtual unsigned getMaxInterleaveFactor(unsigned VF) = 0;
1761  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
1762  OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
1763  ArrayRef<const Value *> Args, const Instruction *CxtI = nullptr) = 0;
1764 
1768  int Index, VectorType *SubTp,
1770  virtual InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst,
1771  Type *Src, CastContextHint CCH,
1773  const Instruction *I) = 0;
1774  virtual InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
1775  VectorType *VecTy,
1776  unsigned Index) = 0;
1777  virtual InstructionCost getCFInstrCost(unsigned Opcode,
1779  const Instruction *I = nullptr) = 0;
1780  virtual InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
1781  Type *CondTy,
1782  CmpInst::Predicate VecPred,
1784  const Instruction *I) = 0;
1785  virtual InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
1786  unsigned Index) = 0;
1787  virtual InstructionCost getVectorInstrCost(const Instruction &I, Type *Val,
1788  unsigned Index) = 0;
1789 
1790  virtual InstructionCost
1791  getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
1792  const APInt &DemandedDstElts,
1794 
1795  virtual InstructionCost
1796  getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
1798  OperandValueInfo OpInfo, const Instruction *I) = 0;
1799  virtual InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src,
1800  Align Alignment,
1801  unsigned AddressSpace,
1803  const Instruction *I) = 0;
1804  virtual InstructionCost
1805  getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
1806  unsigned AddressSpace,
1808  virtual InstructionCost
1809  getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr,
1810  bool VariableMask, Align Alignment,
1812  const Instruction *I = nullptr) = 0;
1813 
1815  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
1816  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
1817  bool UseMaskForCond = false, bool UseMaskForGaps = false) = 0;
1818  virtual InstructionCost
1819  getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
1822  virtual InstructionCost
1823  getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
1826  unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
1830  bool IsUnsigned, Type *ResTy, VectorType *Ty,
1832  virtual InstructionCost
1835  virtual InstructionCost getCallInstrCost(Function *F, Type *RetTy,
1836  ArrayRef<Type *> Tys,
1838  virtual unsigned getNumberOfParts(Type *Tp) = 0;
1839  virtual InstructionCost
1840  getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr) = 0;
1841  virtual InstructionCost
1843  virtual bool getTgtMemIntrinsic(IntrinsicInst *Inst,
1844  MemIntrinsicInfo &Info) = 0;
1845  virtual unsigned getAtomicMemIntrinsicMaxElementSize() const = 0;
1847  Type *ExpectedType) = 0;
1848  virtual Type *
1850  unsigned SrcAddrSpace, unsigned DestAddrSpace,
1851  unsigned SrcAlign, unsigned DestAlign,
1852  Optional<uint32_t> AtomicElementSize) const = 0;
1853 
1854  virtual void getMemcpyLoopResidualLoweringType(
1856  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
1857  unsigned SrcAlign, unsigned DestAlign,
1858  Optional<uint32_t> AtomicCpySize) const = 0;
1859  virtual bool areInlineCompatible(const Function *Caller,
1860  const Function *Callee) const = 0;
1861  virtual bool areTypesABICompatible(const Function *Caller,
1862  const Function *Callee,
1863  const ArrayRef<Type *> &Types) const = 0;
1864  virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const = 0;
1865  virtual bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const = 0;
1866  virtual unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const = 0;
1867  virtual bool isLegalToVectorizeLoad(LoadInst *LI) const = 0;
1868  virtual bool isLegalToVectorizeStore(StoreInst *SI) const = 0;
1869  virtual bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
1870  Align Alignment,
1871  unsigned AddrSpace) const = 0;
1872  virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
1873  Align Alignment,
1874  unsigned AddrSpace) const = 0;
1875  virtual bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc,
1876  ElementCount VF) const = 0;
1877  virtual bool isElementTypeLegalForScalableVector(Type *Ty) const = 0;
1878  virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
1879  unsigned ChainSizeInBytes,
1880  VectorType *VecTy) const = 0;
1881  virtual unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
1882  unsigned ChainSizeInBytes,
1883  VectorType *VecTy) const = 0;
1884  virtual bool preferInLoopReduction(unsigned Opcode, Type *Ty,
1885  ReductionFlags) const = 0;
1886  virtual bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
1887  ReductionFlags) const = 0;
1888  virtual bool preferEpilogueVectorization() const = 0;
1889 
1890  virtual bool shouldExpandReduction(const IntrinsicInst *II) const = 0;
1891  virtual unsigned getGISelRematGlobalCost() const = 0;
1892  virtual unsigned getMinTripCountTailFoldingThreshold() const = 0;
1893  virtual bool enableScalableVectorization() const = 0;
1894  virtual bool supportsScalableVectors() const = 0;
1895  virtual bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
1896  Align Alignment) const = 0;
1897  virtual VPLegalization
1898  getVPLegalizationStrategy(const VPIntrinsic &PI) const = 0;
1899 };
1900 
1901 template <typename T>
1903  T Impl;
1904 
1905 public:
1906  Model(T Impl) : Impl(std::move(Impl)) {}
1907  ~Model() override = default;
1908 
1909  const DataLayout &getDataLayout() const override {
1910  return Impl.getDataLayout();
1911  }
1912 
1913  InstructionCost
1914  getGEPCost(Type *PointeeType, const Value *Ptr,
1915  ArrayRef<const Value *> Operands,
1917  return Impl.getGEPCost(PointeeType, Ptr, Operands, CostKind);
1918  }
1919  unsigned getInliningThresholdMultiplier() override {
1920  return Impl.getInliningThresholdMultiplier();
1921  }
1922  unsigned adjustInliningThreshold(const CallBase *CB) override {
1923  return Impl.adjustInliningThreshold(CB);
1924  }
1925  int getInlinerVectorBonusPercent() override {
1926  return Impl.getInlinerVectorBonusPercent();
1927  }
1928  InstructionCost getMemcpyCost(const Instruction *I) override {
1929  return Impl.getMemcpyCost(I);
1930  }
1931  InstructionCost getInstructionCost(const User *U,
1932  ArrayRef<const Value *> Operands,
1933  TargetCostKind CostKind) override {
1934  return Impl.getInstructionCost(U, Operands, CostKind);
1935  }
1936  BranchProbability getPredictableBranchThreshold() override {
1937  return Impl.getPredictableBranchThreshold();
1938  }
1939  bool hasBranchDivergence() override { return Impl.hasBranchDivergence(); }
1940  bool useGPUDivergenceAnalysis() override {
1941  return Impl.useGPUDivergenceAnalysis();
1942  }
1943  bool isSourceOfDivergence(const Value *V) override {
1944  return Impl.isSourceOfDivergence(V);
1945  }
1946 
1947  bool isAlwaysUniform(const Value *V) override {
1948  return Impl.isAlwaysUniform(V);
1949  }
1950 
1951  unsigned getFlatAddressSpace() override { return Impl.getFlatAddressSpace(); }
1952 
1953  bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
1954  Intrinsic::ID IID) const override {
1955  return Impl.collectFlatAddressOperands(OpIndexes, IID);
1956  }
1957 
1958  bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override {
1959  return Impl.isNoopAddrSpaceCast(FromAS, ToAS);
1960  }
1961 
1962  bool
1963  canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override {
1964  return Impl.canHaveNonUndefGlobalInitializerInAddressSpace(AS);
1965  }
1966 
1967  unsigned getAssumedAddrSpace(const Value *V) const override {
1968  return Impl.getAssumedAddrSpace(V);
1969  }
1970 
1971  bool isSingleThreaded() const override { return Impl.isSingleThreaded(); }
1972 
1973  std::pair<const Value *, unsigned>
1974  getPredicatedAddrSpace(const Value *V) const override {
1975  return Impl.getPredicatedAddrSpace(V);
1976  }
1977 
1978  Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
1979  Value *NewV) const override {
1980  return Impl.rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
1981  }
1982 
1983  bool isLoweredToCall(const Function *F) override {
1984  return Impl.isLoweredToCall(F);
1985  }
1986  void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
1987  UnrollingPreferences &UP,
1988  OptimizationRemarkEmitter *ORE) override {
1989  return Impl.getUnrollingPreferences(L, SE, UP, ORE);
1990  }
1991  void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
1992  PeelingPreferences &PP) override {
1993  return Impl.getPeelingPreferences(L, SE, PP);
1994  }
1995  bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
1996  AssumptionCache &AC, TargetLibraryInfo *LibInfo,
1997  HardwareLoopInfo &HWLoopInfo) override {
1998  return Impl.isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
1999  }
2000  bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE,
2001  AssumptionCache &AC, TargetLibraryInfo *TLI,
2002  DominatorTree *DT,
2003  LoopVectorizationLegality *LVL,
2004  InterleavedAccessInfo *IAI) override {
2005  return Impl.preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LVL, IAI);
2006  }
2008  return Impl.emitGetActiveLaneMask();
2009  }
2010  Optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
2011  IntrinsicInst &II) override {
2012  return Impl.instCombineIntrinsic(IC, II);
2013  }
2014  Optional<Value *>
2015  simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
2016  APInt DemandedMask, KnownBits &Known,
2017  bool &KnownBitsComputed) override {
2018  return Impl.simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
2019  KnownBitsComputed);
2020  }
2021  Optional<Value *> simplifyDemandedVectorEltsIntrinsic(
2022  InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
2023  APInt &UndefElts2, APInt &UndefElts3,
2024  std::function<void(Instruction *, unsigned, APInt, APInt &)>
2025  SimplifyAndSetOp) override {
2026  return Impl.simplifyDemandedVectorEltsIntrinsic(
2027  IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
2028  SimplifyAndSetOp);
2029  }
2030  bool isLegalAddImmediate(int64_t Imm) override {
2031  return Impl.isLegalAddImmediate(Imm);
2032  }
2033  bool isLegalICmpImmediate(int64_t Imm) override {
2034  return Impl.isLegalICmpImmediate(Imm);
2035  }
2036  bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
2037  bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
2038  Instruction *I) override {
2039  return Impl.isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
2040  AddrSpace, I);
2041  }
2042  bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
2043  const TargetTransformInfo::LSRCost &C2) override {
2044  return Impl.isLSRCostLess(C1, C2);
2045  }
2046  bool isNumRegsMajorCostOfLSR() override {
2047  return Impl.isNumRegsMajorCostOfLSR();
2048  }
2049  bool isProfitableLSRChainElement(Instruction *I) override {
2050  return Impl.isProfitableLSRChainElement(I);
2051  }
2052  bool canMacroFuseCmp() override { return Impl.canMacroFuseCmp(); }
2053  bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
2054  DominatorTree *DT, AssumptionCache *AC,
2055  TargetLibraryInfo *LibInfo) override {
2056  return Impl.canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
2057  }
2059  getPreferredAddressingMode(const Loop *L,
2060  ScalarEvolution *SE) const override {
2061  return Impl.getPreferredAddressingMode(L, SE);
2062  }
2063  bool isLegalMaskedStore(Type *DataType, Align Alignment) override {
2064  return Impl.isLegalMaskedStore(DataType, Alignment);
2065  }
2066  bool isLegalMaskedLoad(Type *DataType, Align Alignment) override {
2067  return Impl.isLegalMaskedLoad(DataType, Alignment);
2068  }
2069  bool isLegalNTStore(Type *DataType, Align Alignment) override {
2070  return Impl.isLegalNTStore(DataType, Alignment);
2071  }
2072  bool isLegalNTLoad(Type *DataType, Align Alignment) override {
2073  return Impl.isLegalNTLoad(DataType, Alignment);
2074  }
2075  bool isLegalBroadcastLoad(Type *ElementTy,
2076  ElementCount NumElements) const override {
2077  return Impl.isLegalBroadcastLoad(ElementTy, NumElements);
2078  }
2079  bool isLegalMaskedScatter(Type *DataType, Align Alignment) override {
2080  return Impl.isLegalMaskedScatter(DataType, Alignment);
2081  }
2082  bool isLegalMaskedGather(Type *DataType, Align Alignment) override {
2083  return Impl.isLegalMaskedGather(DataType, Alignment);
2084  }
2085  bool forceScalarizeMaskedGather(VectorType *DataType,
2086  Align Alignment) override {
2087  return Impl.forceScalarizeMaskedGather(DataType, Alignment);
2088  }
2089  bool forceScalarizeMaskedScatter(VectorType *DataType,
2090  Align Alignment) override {
2091  return Impl.forceScalarizeMaskedScatter(DataType, Alignment);
2092  }
2093  bool isLegalMaskedCompressStore(Type *DataType) override {
2094  return Impl.isLegalMaskedCompressStore(DataType);
2095  }
2096  bool isLegalMaskedExpandLoad(Type *DataType) override {
2097  return Impl.isLegalMaskedExpandLoad(DataType);
2098  }
2099  bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
2100  const SmallBitVector &OpcodeMask) const override {
2101  return Impl.isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask);
2102  }
2103  bool enableOrderedReductions() override {
2104  return Impl.enableOrderedReductions();
2105  }
2106  bool hasDivRemOp(Type *DataType, bool IsSigned) override {
2107  return Impl.hasDivRemOp(DataType, IsSigned);
2108  }
2109  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) override {
2110  return Impl.hasVolatileVariant(I, AddrSpace);
2111  }
2112  bool prefersVectorizedAddressing() override {
2113  return Impl.prefersVectorizedAddressing();
2114  }
2115  InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
2116  int64_t BaseOffset, bool HasBaseReg,
2117  int64_t Scale,
2118  unsigned AddrSpace) override {
2119  return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
2120  AddrSpace);
2121  }
2122  bool LSRWithInstrQueries() override { return Impl.LSRWithInstrQueries(); }
2123  bool isTruncateFree(Type *Ty1, Type *Ty2) override {
2124  return Impl.isTruncateFree(Ty1, Ty2);
2125  }
2126  bool isProfitableToHoist(Instruction *I) override {
2127  return Impl.isProfitableToHoist(I);
2128  }
2129  bool useAA() override { return Impl.useAA(); }
2130  bool isTypeLegal(Type *Ty) override { return Impl.isTypeLegal(Ty); }
2131  unsigned getRegUsageForType(Type *Ty) override {
2132  return Impl.getRegUsageForType(Ty);
2133  }
2134  bool shouldBuildLookupTables() override {
2135  return Impl.shouldBuildLookupTables();
2136  }
2137  bool shouldBuildLookupTablesForConstant(Constant *C) override {
2138  return Impl.shouldBuildLookupTablesForConstant(C);
2139  }
2140  bool shouldBuildRelLookupTables() override {
2141  return Impl.shouldBuildRelLookupTables();
2142  }
2143  bool useColdCCForColdCall(Function &F) override {
2144  return Impl.useColdCCForColdCall(F);
2145  }
2146 
2147  InstructionCost getScalarizationOverhead(VectorType *Ty,
2148  const APInt &DemandedElts,
2149  bool Insert, bool Extract) override {
2150  return Impl.getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
2151  }
2152  InstructionCost
2153  getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
2154  ArrayRef<Type *> Tys) override {
2155  return Impl.getOperandsScalarizationOverhead(Args, Tys);
2156  }
2157 
2158  bool supportsEfficientVectorElementLoadStore() override {
2159  return Impl.supportsEfficientVectorElementLoadStore();
2160  }
2161 
2162  bool supportsTailCalls() override { return Impl.supportsTailCalls(); }
2163  bool supportsTailCallFor(const CallBase *CB) override {
2164  return Impl.supportsTailCallFor(CB);
2165  }
2166 
2167  bool enableAggressiveInterleaving(bool LoopHasReductions) override {
2168  return Impl.enableAggressiveInterleaving(LoopHasReductions);
2169  }
2170  MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
2171  bool IsZeroCmp) const override {
2172  return Impl.enableMemCmpExpansion(OptSize, IsZeroCmp);
2173  }
2174  bool enableInterleavedAccessVectorization() override {
2175  return Impl.enableInterleavedAccessVectorization();
2176  }
2178  return Impl.enableMaskedInterleavedAccessVectorization();
2179  }
2180  bool isFPVectorizationPotentiallyUnsafe() override {
2181  return Impl.isFPVectorizationPotentiallyUnsafe();
2182  }
2183  bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,
2184  unsigned AddressSpace, Align Alignment,
2185  unsigned *Fast) override {
2186  return Impl.allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
2187  Alignment, Fast);
2188  }
2189  PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) override {
2190  return Impl.getPopcntSupport(IntTyWidthInBit);
2191  }
2192  bool haveFastSqrt(Type *Ty) override { return Impl.haveFastSqrt(Ty); }
2193 
2194  bool isExpensiveToSpeculativelyExecute(const Instruction* I) override {
2195  return Impl.isExpensiveToSpeculativelyExecute(I);
2196  }
2197 
2198  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) override {
2199  return Impl.isFCmpOrdCheaperThanFCmpZero(Ty);
2200  }
2201 
2202  InstructionCost getFPOpCost(Type *Ty) override {
2203  return Impl.getFPOpCost(Ty);
2204  }
2205 
2206  InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx,
2207  const APInt &Imm, Type *Ty) override {
2208  return Impl.getIntImmCodeSizeCost(Opc, Idx, Imm, Ty);
2209  }
2210  InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
2211  TargetCostKind CostKind) override {
2212  return Impl.getIntImmCost(Imm, Ty, CostKind);
2213  }
2214  InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx,
2215  const APInt &Imm, Type *Ty,
2217  Instruction *Inst = nullptr) override {
2218  return Impl.getIntImmCostInst(Opc, Idx, Imm, Ty, CostKind, Inst);
2219  }
2220  InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
2221  const APInt &Imm, Type *Ty,
2222  TargetCostKind CostKind) override {
2223  return Impl.getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
2224  }
2225  unsigned getNumberOfRegisters(unsigned ClassID) const override {
2226  return Impl.getNumberOfRegisters(ClassID);
2227  }
2228  unsigned getRegisterClassForType(bool Vector,
2229  Type *Ty = nullptr) const override {
2230  return Impl.getRegisterClassForType(Vector, Ty);
2231  }
2232  const char *getRegisterClassName(unsigned ClassID) const override {
2233  return Impl.getRegisterClassName(ClassID);
2234  }
2235  TypeSize getRegisterBitWidth(RegisterKind K) const override {
2236  return Impl.getRegisterBitWidth(K);
2237  }
2238  unsigned getMinVectorRegisterBitWidth() const override {
2239  return Impl.getMinVectorRegisterBitWidth();
2240  }
2241  Optional<unsigned> getMaxVScale() const override {
2242  return Impl.getMaxVScale();
2243  }
2244  Optional<unsigned> getVScaleForTuning() const override {
2245  return Impl.getVScaleForTuning();
2246  }
2248  TargetTransformInfo::RegisterKind K) const override {
2249  return Impl.shouldMaximizeVectorBandwidth(K);
2250  }
2251  ElementCount getMinimumVF(unsigned ElemWidth,
2252  bool IsScalable) const override {
2253  return Impl.getMinimumVF(ElemWidth, IsScalable);
2254  }
2255  unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override {
2256  return Impl.getMaximumVF(ElemWidth, Opcode);
2257  }
2258  unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy,
2259  Type *ScalarValTy) const override {
2260  return Impl.getStoreMinimumVF(VF, ScalarMemTy, ScalarValTy);
2261  }
2263  const Instruction &I, bool &AllowPromotionWithoutCommonHeader) override {
2264  return Impl.shouldConsiderAddressTypePromotion(
2265  I, AllowPromotionWithoutCommonHeader);
2266  }
2267  unsigned getCacheLineSize() const override { return Impl.getCacheLineSize(); }
2268  Optional<unsigned> getCacheSize(CacheLevel Level) const override {
2269  return Impl.getCacheSize(Level);
2270  }
2271  Optional<unsigned> getCacheAssociativity(CacheLevel Level) const override {
2272  return Impl.getCacheAssociativity(Level);
2273  }
2274 
2275  /// Return the preferred prefetch distance in terms of instructions.
2276  ///
2277  unsigned getPrefetchDistance() const override {
2278  return Impl.getPrefetchDistance();
2279  }
2280 
2281  /// Return the minimum stride necessary to trigger software
2282  /// prefetching.
2283  ///
2284  unsigned getMinPrefetchStride(unsigned NumMemAccesses,
2285  unsigned NumStridedMemAccesses,
2286  unsigned NumPrefetches,
2287  bool HasCall) const override {
2288  return Impl.getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
2289  NumPrefetches, HasCall);
2290  }
2291 
2292  /// Return the maximum prefetch distance in terms of loop
2293  /// iterations.
2294  ///
2295  unsigned getMaxPrefetchIterationsAhead() const override {
2296  return Impl.getMaxPrefetchIterationsAhead();
2297  }
2298 
2299  /// \return True if prefetching should also be done for writes.
2300  bool enableWritePrefetching() const override {
2301  return Impl.enableWritePrefetching();
2302  }
2303 
2304  /// \return if target want to issue a prefetch in address space \p AS.
2305  bool shouldPrefetchAddressSpace(unsigned AS) const override {
2306  return Impl.shouldPrefetchAddressSpace(AS);
2307  }
2308 
2309  unsigned getMaxInterleaveFactor(unsigned VF) override {
2310  return Impl.getMaxInterleaveFactor(VF);
2311  }
2312  unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
2313  unsigned &JTSize,
2314  ProfileSummaryInfo *PSI,
2315  BlockFrequencyInfo *BFI) override {
2316  return Impl.getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
2317  }
2318  InstructionCost getArithmeticInstrCost(
2319  unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
2320  OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
2321  ArrayRef<const Value *> Args,
2322  const Instruction *CxtI = nullptr) override {
2323  return Impl.getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
2324  Args, CxtI);
2325  }
2326 
2327  InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp,
2328  ArrayRef<int> Mask,
2330  VectorType *SubTp,
2331  ArrayRef<const Value *> Args) override {
2332  return Impl.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args);
2333  }
2334  InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
2335  CastContextHint CCH,
2337  const Instruction *I) override {
2338  return Impl.getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
2339  }
2340  InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst,
2341  VectorType *VecTy,
2342  unsigned Index) override {
2343  return Impl.getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
2344  }
2345  InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
2346  const Instruction *I = nullptr) override {
2347  return Impl.getCFInstrCost(Opcode, CostKind, I);
2348  }
2349  InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
2350  CmpInst::Predicate VecPred,
2352  const Instruction *I) override {
2353  return Impl.getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
2354  }
2355  InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
2356  unsigned Index) override {
2357  return Impl.getVectorInstrCost(Opcode, Val, Index);
2358  }
2359  InstructionCost getVectorInstrCost(const Instruction &I, Type *Val,
2360  unsigned Index) override {
2361  return Impl.getVectorInstrCost(I, Val, Index);
2362  }
2363  InstructionCost
2364  getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
2365  const APInt &DemandedDstElts,
2366  TTI::TargetCostKind CostKind) override {
2367  return Impl.getReplicationShuffleCost(EltTy, ReplicationFactor, VF,
2368  DemandedDstElts, CostKind);
2369  }
2370  InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
2371  unsigned AddressSpace,
2373  OperandValueInfo OpInfo,
2374  const Instruction *I) override {
2375  return Impl.getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind,
2376  OpInfo, I);
2377  }
2378  InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
2379  unsigned AddressSpace,
2381  const Instruction *I) override {
2382  return Impl.getVPMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
2383  CostKind, I);
2384  }
2385  InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
2386  Align Alignment, unsigned AddressSpace,
2387  TTI::TargetCostKind CostKind) override {
2388  return Impl.getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
2389  CostKind);
2390  }
2391  InstructionCost
2392  getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr,
2393  bool VariableMask, Align Alignment,
2395  const Instruction *I = nullptr) override {
2396  return Impl.getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
2397  Alignment, CostKind, I);
2398  }
2399  InstructionCost getInterleavedMemoryOpCost(
2400  unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
2401  Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
2402  bool UseMaskForCond, bool UseMaskForGaps) override {
2403  return Impl.getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
2404  Alignment, AddressSpace, CostKind,
2405  UseMaskForCond, UseMaskForGaps);
2406  }
2407  InstructionCost
2408  getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
2409  Optional<FastMathFlags> FMF,
2410  TTI::TargetCostKind CostKind) override {
2411  return Impl.getArithmeticReductionCost(Opcode, Ty, FMF, CostKind);
2412  }
2413  InstructionCost
2414  getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned,
2415  TTI::TargetCostKind CostKind) override {
2416  return Impl.getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
2417  }
2418  InstructionCost getExtendedReductionCost(
2419  unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty,
2420  Optional<FastMathFlags> FMF,
2422  return Impl.getExtendedReductionCost(Opcode, IsUnsigned, ResTy, Ty, FMF,
2423  CostKind);
2424  }
2425  InstructionCost getMulAccReductionCost(
2426  bool IsUnsigned, Type *ResTy, VectorType *Ty,
2428  return Impl.getMulAccReductionCost(IsUnsigned, ResTy, Ty, CostKind);
2429  }
2430  InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
2431  TTI::TargetCostKind CostKind) override {
2432  return Impl.getIntrinsicInstrCost(ICA, CostKind);
2433  }
2434  InstructionCost getCallInstrCost(Function *F, Type *RetTy,
2435  ArrayRef<Type *> Tys,
2436  TTI::TargetCostKind CostKind) override {
2437  return Impl.getCallInstrCost(F, RetTy, Tys, CostKind);
2438  }
2439  unsigned getNumberOfParts(Type *Tp) override {
2440  return Impl.getNumberOfParts(Tp);
2441  }
2442  InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE,
2443  const SCEV *Ptr) override {
2444  return Impl.getAddressComputationCost(Ty, SE, Ptr);
2445  }
2446  InstructionCost getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) override {
2447  return Impl.getCostOfKeepingLiveOverCall(Tys);
2448  }
2449  bool getTgtMemIntrinsic(IntrinsicInst *Inst,
2450  MemIntrinsicInfo &Info) override {
2451  return Impl.getTgtMemIntrinsic(Inst, Info);
2452  }
2453  unsigned getAtomicMemIntrinsicMaxElementSize() const override {
2454  return Impl.getAtomicMemIntrinsicMaxElementSize();
2455  }
2456  Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
2457  Type *ExpectedType) override {
2458  return Impl.getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
2459  }
2461  LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
2462  unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign,
2463  Optional<uint32_t> AtomicElementSize) const override {
2464  return Impl.getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
2465  DestAddrSpace, SrcAlign, DestAlign,
2466  AtomicElementSize);
2467  }
2469  SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
2470  unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
2471  unsigned SrcAlign, unsigned DestAlign,
2472  Optional<uint32_t> AtomicCpySize) const override {
2473  Impl.getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
2474  SrcAddrSpace, DestAddrSpace,
2475  SrcAlign, DestAlign, AtomicCpySize);
2476  }
2477  bool areInlineCompatible(const Function *Caller,
2478  const Function *Callee) const override {
2479  return Impl.areInlineCompatible(Caller, Callee);
2480  }
2481  bool areTypesABICompatible(const Function *Caller, const Function *Callee,
2482  const ArrayRef<Type *> &Types) const override {
2483  return Impl.areTypesABICompatible(Caller, Callee, Types);
2484  }
2485  bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const override {
2486  return Impl.isIndexedLoadLegal(Mode, Ty, getDataLayout());
2487  }
2488  bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const override {
2489  return Impl.isIndexedStoreLegal(Mode, Ty, getDataLayout());
2490  }
2491  unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override {
2492  return Impl.getLoadStoreVecRegBitWidth(AddrSpace);
2493  }
2494  bool isLegalToVectorizeLoad(LoadInst *LI) const override {
2495  return Impl.isLegalToVectorizeLoad(LI);
2496  }
2497  bool isLegalToVectorizeStore(StoreInst *SI) const override {
2498  return Impl.isLegalToVectorizeStore(SI);
2499  }
2500  bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
2501  unsigned AddrSpace) const override {
2502  return Impl.isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
2503  AddrSpace);
2504  }
2505  bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
2506  unsigned AddrSpace) const override {
2507  return Impl.isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
2508  AddrSpace);
2509  }
2510  bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc,
2511  ElementCount VF) const override {
2512  return Impl.isLegalToVectorizeReduction(RdxDesc, VF);
2513  }
2514  bool isElementTypeLegalForScalableVector(Type *Ty) const override {
2515  return Impl.isElementTypeLegalForScalableVector(Ty);
2516  }
2517  unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
2518  unsigned ChainSizeInBytes,
2519  VectorType *VecTy) const override {
2520  return Impl.getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
2521  }
2522  unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
2523  unsigned ChainSizeInBytes,
2524  VectorType *VecTy) const override {
2525  return Impl.getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
2526  }
2527  bool preferInLoopReduction(unsigned Opcode, Type *Ty,
2528  ReductionFlags Flags) const override {
2529  return Impl.preferInLoopReduction(Opcode, Ty, Flags);
2530  }
2531  bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
2532  ReductionFlags Flags) const override {
2533  return Impl.preferPredicatedReductionSelect(Opcode, Ty, Flags);
2534  }
2535  bool preferEpilogueVectorization() const override {
2536  return Impl.preferEpilogueVectorization();
2537  }
2538 
2539  bool shouldExpandReduction(const IntrinsicInst *II) const override {
2540  return Impl.shouldExpandReduction(II);
2541  }
2542 
2543  unsigned getGISelRematGlobalCost() const override {
2544  return Impl.getGISelRematGlobalCost();
2545  }
2546 
2547  unsigned getMinTripCountTailFoldingThreshold() const override {
2548  return Impl.getMinTripCountTailFoldingThreshold();
2549  }
2550 
2551  bool supportsScalableVectors() const override {
2552  return Impl.supportsScalableVectors();
2553  }
2554 
2555  bool enableScalableVectorization() const override {
2556  return Impl.enableScalableVectorization();
2557  }
2558 
2559  bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
2560  Align Alignment) const override {
2561  return Impl.hasActiveVectorLength(Opcode, DataType, Alignment);
2562  }
2563 
2565  getVPLegalizationStrategy(const VPIntrinsic &PI) const override {
2566  return Impl.getVPLegalizationStrategy(PI);
2567  }
2568 };
2569 
2570 template <typename T>
2572  : TTIImpl(new Model<T>(Impl)) {}
2573 
2574 /// Analysis pass providing the \c TargetTransformInfo.
2575 ///
2576 /// The core idea of the TargetIRAnalysis is to expose an interface through
2577 /// which LLVM targets can analyze and provide information about the middle
2578 /// end's target-independent IR. This supports use cases such as target-aware
2579 /// cost modeling of IR constructs.
2580 ///
2581 /// This is a function analysis because much of the cost modeling for targets
2582 /// is done in a subtarget specific way and LLVM supports compiling different
2583 /// functions targeting different subtargets in order to support runtime
2584 /// dispatch according to the observed subtarget.
2585 class TargetIRAnalysis : public AnalysisInfoMixin<TargetIRAnalysis> {
2586 public:
2588 
2589  /// Default construct a target IR analysis.
2590  ///
2591  /// This will use the module's datalayout to construct a baseline
2592  /// conservative TTI result.
2593  TargetIRAnalysis();
2594 
2595  /// Construct an IR analysis pass around a target-provide callback.
2596  ///
2597  /// The callback will be called with a particular function for which the TTI
2598  /// is needed and must return a TTI object for that function.
2599  TargetIRAnalysis(std::function<Result(const Function &)> TTICallback);
2600 
2601  // Value semantics. We spell out the constructors for MSVC.
2603  : TTICallback(Arg.TTICallback) {}
2605  : TTICallback(std::move(Arg.TTICallback)) {}
2607  TTICallback = RHS.TTICallback;
2608  return *this;
2609  }
2611  TTICallback = std::move(RHS.TTICallback);
2612  return *this;
2613  }
2614 
2616 
2617 private:
2619  static AnalysisKey Key;
2620 
2621  /// The callback used to produce a result.
2622  ///
2623  /// We use a completely opaque callback so that targets can provide whatever
2624  /// mechanism they desire for constructing the TTI for a given function.
2625  ///
2626  /// FIXME: Should we really use std::function? It's relatively inefficient.
2627  /// It might be possible to arrange for even stateful callbacks to outlive
2628  /// the analysis and thus use a function_ref which would be lighter weight.
2629  /// This may also be less error prone as the callback is likely to reference
2630  /// the external TargetMachine, and that reference needs to never dangle.
2631  std::function<Result(const Function &)> TTICallback;
2632 
2633  /// Helper function used as the callback in the default constructor.
2634  static Result getDefaultTTI(const Function &F);
2635 };
2636 
2637 /// Wrapper pass for TargetTransformInfo.
2638 ///
2639 /// This pass can be constructed from a TTI object which it stores internally
2640 /// and is queried by passes.
2642  TargetIRAnalysis TIRA;
2644 
2645  virtual void anchor();
2646 
2647 public:
2648  static char ID;
2649 
2650  /// We must provide a default constructor for the pass but it should
2651  /// never be used.
2652  ///
2653  /// Use the constructor below or call one of the creation routines.
2655 
2657 
2659 };
2660 
2661 /// Create an analysis pass wrapper around a TTI object.
2662 ///
2663 /// This analysis pass just holds the TTI instance and makes it available to
2664 /// clients.
2666 
2667 } // namespace llvm
2668 
2669 #endif
llvm::TargetTransformInfo::ReductionFlags::IsMaxOp
bool IsMaxOp
If the op a min/max kind, true if it's a max operation.
Definition: TargetTransformInfo.h:1456
llvm::TargetTransformInfo::CastContextHint::GatherScatter
@ GatherScatter
The cast is used with a gather/scatter.
llvm::TargetTransformInfo::isHardwareLoopProfitable
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
Query the target whether it would be profitable to convert the given loop into a hardware loop.
Definition: TargetTransformInfo.cpp:294
llvm::InstructionCost
Definition: InstructionCost.h:29
llvm::TargetTransformInfo::Concept::getExtractWithExtendCost
virtual InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index)=0
llvm::TargetTransformInfo::CacheLevel::L1D
@ L1D
llvm::PreservedAnalyses
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:152
llvm::TargetTransformInfo::PSK_FastHardware
@ PSK_FastHardware
Definition: TargetTransformInfo.h:585
llvm::TargetTransformInfo::Concept::getPopcntSupport
virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit)=0
llvm::TargetTransformInfo::Concept::getGEPCost
virtual InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)=0
llvm::TargetTransformInfo::CastContextHint::Masked
@ Masked
The cast is used with a masked load/store.
llvm::TargetTransformInfo::UnrollingPreferences::BEInsns
unsigned BEInsns
Definition: TargetTransformInfo.h:466
llvm::TargetTransformInfo::UnrollingPreferences::PartialOptSizeThreshold
unsigned PartialOptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size, like OptSizeThreshold,...
Definition: TargetTransformInfo.h:445
llvm::TargetTransformInfo::SK_Select
@ SK_Select
Selects elements from the corresponding lane of either source operand.
Definition: TargetTransformInfo.h:889
llvm::TargetIRAnalysis
Analysis pass providing the TargetTransformInfo.
Definition: TargetTransformInfo.h:2585
llvm::TargetTransformInfo::UnrollingPreferences::Runtime
bool Runtime
Allow runtime unrolling (unrolling of loops to expand the size of the loop body even when the number ...
Definition: TargetTransformInfo.h:473
llvm::TargetTransformInfo::TargetCostKind
TargetCostKind
The kind of cost model.
Definition: TargetTransformInfo.h:217
llvm::TargetTransformInfo::LSRCost::NumRegs
unsigned NumRegs
Definition: TargetTransformInfo.h:406
llvm::TargetTransformInfo::TCC_Expensive
@ TCC_Expensive
The cost of a 'div' instruction on x86.
Definition: TargetTransformInfo.h:245
llvm::TargetTransformInfo::getShuffleCost
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask=None, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, int Index=0, VectorType *SubTp=nullptr, ArrayRef< const Value * > Args=None) const
Definition: TargetTransformInfo.cpp:802
llvm::TargetTransformInfo::UnrollingPreferences::PartialThreshold
unsigned PartialThreshold
The cost threshold for the unrolled loop, like Threshold, but used for partial/runtime unrolling (set...
Definition: TargetTransformInfo.h:441
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::TargetTransformInfo::ReductionFlags
Flags describing the kind of vector reduction.
Definition: TargetTransformInfo.h:1454
FMF.h
llvm::TargetTransformInfo::instCombineIntrinsic
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
Targets can implement their own combinations for target-specific intrinsics.
Definition: TargetTransformInfo.cpp:312
llvm::TargetTransformInfo::Concept::isHardwareLoopProfitable
virtual bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo)=0
llvm::TargetTransformInfo::Concept::isSourceOfDivergence
virtual bool isSourceOfDivergence(const Value *V)=0
llvm::TargetTransformInfo::getInstructionCost
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind) const
Estimate the cost of a given IR user when lowered.
Definition: TargetTransformInfo.cpp:224
llvm::TargetTransformInfo::Concept::enableMaskedInterleavedAccessVectorization
virtual bool enableMaskedInterleavedAccessVectorization()=0
llvm::MemIntrinsicInfo::PtrVal
Value * PtrVal
This is the pointer that the intrinsic is loading from or storing to.
Definition: TargetTransformInfo.h:76
llvm::TargetTransformInfo::Concept::rewriteIntrinsicWithAddressSpace
virtual Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const =0
llvm::TargetTransformInfo::getMinVectorRegisterBitWidth
unsigned getMinVectorRegisterBitWidth() const
Definition: TargetTransformInfo.cpp:649
llvm::TargetTransformInfo::OperandValueInfo::isNegatedPowerOf2
bool isNegatedPowerOf2() const
Definition: TargetTransformInfo.h:936
llvm::TargetTransformInfo::Concept::enableOrderedReductions
virtual bool enableOrderedReductions()=0
llvm::HardwareLoopInfo::LoopDecrement
Value * LoopDecrement
Definition: TargetTransformInfo.h:104
llvm::DataLayout
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:113
llvm::TargetTransformInfo::OperandValueInfo::Properties
OperandValueProperties Properties
Definition: TargetTransformInfo.h:925
llvm::TargetTransformInfo::Concept::areTypesABICompatible
virtual bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const =0
llvm::TargetTransformInfo::MemIndexedMode
MemIndexedMode
The type of load/store indexing.
Definition: TargetTransformInfo.h:1402
llvm::TargetTransformInfo::TCK_Latency
@ TCK_Latency
The latency of instruction.
Definition: TargetTransformInfo.h:219
Insert
Vector Rotate Left Mask Mask Insert
Definition: README_P9.txt:112
llvm::CmpInst::Predicate
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:719
llvm::TargetTransformInfo::getVScaleForTuning
Optional< unsigned > getVScaleForTuning() const
Definition: TargetTransformInfo.cpp:657
llvm::TargetTransformInfo::UnrollingPreferences::MaxCount
unsigned MaxCount
Definition: TargetTransformInfo.h:457
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:279
llvm::TargetTransformInfo::getRegisterClassName
const char * getRegisterClassName(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:640
AtomicOrdering.h
llvm::ElementCount
Definition: TypeSize.h:404
llvm::TargetTransformInfo::OK_UniformValue
@ OK_UniformValue
Definition: TargetTransformInfo.h:908
llvm::TargetTransformInfo::getCmpSelInstrCost
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:884
llvm::TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass
TargetTransformInfoWrapperPass()
We must provide a default constructor for the pass but it should never be used.
Definition: TargetTransformInfo.cpp:1209
llvm::TargetTransformInfo::Concept::enableMemCmpExpansion
virtual MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const =0
llvm::TargetTransformInfo::canMacroFuseCmp
bool canMacroFuseCmp() const
Return true if the target can fuse a compare and branch.
Definition: TargetTransformInfo.cpp:375
llvm::Function
Definition: Function.h:60
llvm::Loop
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:547
llvm::TargetTransformInfo::Concept::isLegalMaskedScatter
virtual bool isLegalMaskedScatter(Type *DataType, Align Alignment)=0
Pass.h
llvm::TargetTransformInfo::getRegisterBitWidth
TypeSize getRegisterBitWidth(RegisterKind K) const
Definition: TargetTransformInfo.cpp:644
llvm::TargetTransformInfo::PopcntSupportKind
PopcntSupportKind
Flags indicating the kind of support for population count.
Definition: TargetTransformInfo.h:585
llvm::TargetTransformInfo::Concept::getIntImmCost
virtual InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind)=0
llvm::TargetTransformInfo::getVPLegalizationStrategy
VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
Definition: TargetTransformInfo.cpp:1154
llvm::TargetTransformInfo::AMK_PostIndexed
@ AMK_PostIndexed
Definition: TargetTransformInfo.h:634
llvm::TargetTransformInfoWrapperPass::getTTI
TargetTransformInfo & getTTI(const Function &F)
Definition: TargetTransformInfo.cpp:1222
C1
instcombine should handle this C2 when C1
Definition: README.txt:263
llvm::TargetTransformInfo::getAddressComputationCost
InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE=nullptr, const SCEV *Ptr=nullptr) const
Definition: TargetTransformInfo.cpp:989
InstCombiner
Machine InstCombiner
Definition: MachineCombiner.cpp:137
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1199
llvm::TargetTransformInfo::PeelingPreferences::AllowPeeling
bool AllowPeeling
Allow peeling off loop iterations.
Definition: TargetTransformInfo.h:534
llvm::TargetTransformInfo::Concept::hasVolatileVariant
virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace)=0
llvm::TargetTransformInfo::Concept::isFPVectorizationPotentiallyUnsafe
virtual bool isFPVectorizationPotentiallyUnsafe()=0
llvm::TargetTransformInfo::Concept::isLegalMaskedExpandLoad
virtual bool isLegalMaskedExpandLoad(Type *DataType)=0
llvm::TargetTransformInfo::Concept::isAlwaysUniform
virtual bool isAlwaysUniform(const Value *V)=0
llvm::TargetTransformInfo::Concept::getMaxPrefetchIterationsAhead
virtual unsigned getMaxPrefetchIterationsAhead() const =0
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:172
llvm::TargetTransformInfo::MemCmpExpansionOptions::AllowOverlappingLoads
bool AllowOverlappingLoads
Definition: TargetTransformInfo.h:803
llvm::TargetTransformInfo::getScalingFactorCost
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0) const
Return the cost of the scaling factor used in the addressing mode represented by AM for this target,...
Definition: TargetTransformInfo.cpp:467
llvm::IntrinsicCostAttributes::getReturnType
Type * getReturnType() const
Definition: TargetTransformInfo.h:152
llvm::ScalarEvolution
The main scalar evolution driver.
Definition: ScalarEvolution.h:449
llvm::TargetTransformInfo::getIntrinsicInstrCost
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:968
llvm::TargetTransformInfo::Concept::getRegisterClassForType
virtual unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const =0
llvm::TargetTransformInfo::RGK_Scalar
@ RGK_Scalar
Definition: TargetTransformInfo.h:964
llvm::TargetTransformInfo::Concept::enableInterleavedAccessVectorization
virtual bool enableInterleavedAccessVectorization()=0
llvm::LoopVectorizationLegality
LoopVectorizationLegality checks if it is legal to vectorize a loop, and to what vectorization factor...
Definition: LoopVectorizationLegality.h:241
llvm::TargetTransformInfo::getAssumedAddrSpace
unsigned getAssumedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:272
llvm::IntrinsicCostAttributes::getInst
const IntrinsicInst * getInst() const
Definition: TargetTransformInfo.h:151
llvm::TargetTransformInfo::Concept::useGPUDivergenceAnalysis
virtual bool useGPUDivergenceAnalysis()=0
llvm::TargetTransformInfo::isLegalICmpImmediate
bool isLegalICmpImmediate(int64_t Imm) const
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Definition: TargetTransformInfo.cpp:349
llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJamInnerLoopThreshold
unsigned UnrollAndJamInnerLoopThreshold
Threshold for unroll and jam, for inner loop size.
Definition: TargetTransformInfo.h:492
llvm::TargetTransformInfo::Concept::getMinMaxReductionCost
virtual InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)=0
llvm::TargetTransformInfo::isLegalBroadcastLoad
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
\Returns true if the target supports broadcasting a load to a vector of type <NumElements x ElementTy...
Definition: TargetTransformInfo.cpp:411
llvm::TargetTransformInfo::getExtendedReductionCost
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of a reduc...
Definition: TargetTransformInfo.cpp:1020
llvm::TargetIRAnalysis::operator=
TargetIRAnalysis & operator=(const TargetIRAnalysis &RHS)
Definition: TargetTransformInfo.h:2606
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis(TargetIRAnalysis &&Arg)
Definition: TargetTransformInfo.h:2604
llvm::DominatorTree
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:166
llvm::HardwareLoopInfo::ExitBranch
BranchInst * ExitBranch
Definition: TargetTransformInfo.h:101
llvm::TargetTransformInfo::UnrollingPreferences::UnrollRemainder
bool UnrollRemainder
Allow unrolling of all the iterations of the runtime loop remainder.
Definition: TargetTransformInfo.h:485
llvm::TargetTransformInfo::Concept::isExpensiveToSpeculativelyExecute
virtual bool isExpensiveToSpeculativelyExecute(const Instruction *I)=0
llvm::TargetTransformInfo::UnrollingPreferences::Count
unsigned Count
A forced unrolling factor (the number of concatenated bodies of the original loop in the unrolled loo...
Definition: TargetTransformInfo.h:450
llvm::TargetTransformInfo::TCK_CodeSize
@ TCK_CodeSize
Instruction code size.
Definition: TargetTransformInfo.h:220
llvm::TargetTransformInfo::VPLegalization
Definition: TargetTransformInfo.h:1512
llvm::TargetTransformInfo::shouldBuildLookupTables
bool shouldBuildLookupTables() const
Return true if switches should be turned into lookup tables for the target.
Definition: TargetTransformInfo.cpp:498
llvm::TargetTransformInfo::LSRCost::NumIVMuls
unsigned NumIVMuls
Definition: TargetTransformInfo.h:408
llvm::TargetTransformInfo::Concept::isLegalToVectorizeReduction
virtual bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const =0
llvm::HardwareLoopInfo::isHardwareLoopCandidate
bool isHardwareLoopCandidate(ScalarEvolution &SE, LoopInfo &LI, DominatorTree &DT, bool ForceNestedLoop=false, bool ForceHardwareLoopPHI=false)
Definition: TargetTransformInfo.cpp:105
llvm::TargetTransformInfo::UnrollingPreferences::Partial
bool Partial
Allow partial unrolling (unrolling of loops to expand the size of the loop body, not only to eliminat...
Definition: TargetTransformInfo.h:469
llvm::TargetTransformInfo::getMaximumVF
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
Definition: TargetTransformInfo.cpp:671
llvm::TargetTransformInfo::Concept::getEstimatedNumberOfCaseClusters
virtual unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI)=0
llvm::Type
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
llvm::TargetTransformInfo::useColdCCForColdCall
bool useColdCCForColdCall(Function &F) const
Return true if the input function which is cold at all call sites, should use coldcc calling conventi...
Definition: TargetTransformInfo.cpp:511
llvm::TargetTransformInfo::VPLegalization::Convert
@ Convert
Definition: TargetTransformInfo.h:1519
llvm::TargetTransformInfo::Concept::getGatherScatterOpCost
virtual InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)=0
llvm::TargetTransformInfo::PeelingPreferences
Definition: TargetTransformInfo.h:528
llvm::TargetTransformInfo::operator=
TargetTransformInfo & operator=(TargetTransformInfo &&RHS)
Definition: TargetTransformInfo.cpp:192
llvm::TargetTransformInfo::Concept::getPeelingPreferences
virtual void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP)=0
llvm::HardwareLoopInfo::L
Loop * L
Definition: TargetTransformInfo.h:99
llvm::TargetTransformInfo::Concept::preferEpilogueVectorization
virtual bool preferEpilogueVectorization() const =0
llvm::TargetTransformInfo::isLegalNTLoad
bool isLegalNTLoad(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal load.
Definition: TargetTransformInfo.cpp:407
llvm::TargetTransformInfo::isLegalNTStore
bool isLegalNTStore(Type *DataType, Align Alignment) const
Return true if the target supports nontemporal store.
Definition: TargetTransformInfo.cpp:402
llvm::TargetTransformInfo::UnrollingPreferences::FullUnrollMaxCount
unsigned FullUnrollMaxCount
Set the maximum unrolling factor for full unrolling.
Definition: TargetTransformInfo.h:461
llvm::TargetTransformInfo::Concept::getMemcpyLoopLoweringType
virtual Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize) const =0
llvm::Optional
Definition: APInt.h:33
ForceNestedLoop
static cl::opt< bool > ForceNestedLoop("force-nested-hardware-loop", cl::Hidden, cl::init(false), cl::desc("Force allowance of nested hardware loops"))
llvm::TargetTransformInfo::getCFInstrCost
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:875
Vector
So we should use XX3Form_Rcr to implement intrinsic Convert DP outs ins xscvdpsp No builtin are required Round &Convert QP DP(dword[1] is set to zero) No builtin are required Round to Quad Precision because you need to assign rounding mode in instruction Provide builtin(set f128:$vT,(int_ppc_vsx_xsrqpi f128:$vB))(set f128 yields< n x< ty > >< result > yields< ty >< result > No builtin are required Load Store Vector
Definition: README_P9.txt:497
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::IntrinsicCostAttributes::IntrinsicCostAttributes
IntrinsicCostAttributes(Intrinsic::ID Id, const CallBase &CI, InstructionCost ScalarCost=InstructionCost::getInvalid(), bool TypeBasedOnly=false)
Definition: TargetTransformInfo.cpp:60
llvm::TargetTransformInfo::OP_PowerOf2
@ OP_PowerOf2
Definition: TargetTransformInfo.h:916
llvm::TargetTransformInfo::getPredictableBranchThreshold
BranchProbability getPredictableBranchThreshold() const
If a branch or a select condition is skewed in one direction by more than this factor,...
Definition: TargetTransformInfo.cpp:233
llvm::TargetTransformInfo::getIntImmCodeSizeCost
InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty) const
Return the expected cost for the given integer when optimising for size.
Definition: TargetTransformInfo.cpp:595
llvm::TargetTransformInfo::getInlinerVectorBonusPercent
int getInlinerVectorBonusPercent() const
Definition: TargetTransformInfo.cpp:206
llvm::TargetTransformInfo::getIntImmCostIntrin
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Definition: TargetTransformInfo.cpp:622
RHS
Value * RHS
Definition: X86PartialReduction.cpp:76
VectorType
Definition: ItaniumDemangle.h:1075
llvm::TargetTransformInfo::Concept::isTruncateFree
virtual bool isTruncateFree(Type *Ty1, Type *Ty2)=0
llvm::TargetTransformInfo::getIntImmCostInst
InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr) const
Return the expected cost of materialization for the given integer immediate of the specified type for...
Definition: TargetTransformInfo.cpp:612
llvm::FastMathFlags
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:21
llvm::TargetTransformInfo::Concept::getAtomicMemIntrinsicMaxElementSize
virtual unsigned getAtomicMemIntrinsicMaxElementSize() const =0
llvm::TargetTransformInfo::OperandValueInfo
Definition: TargetTransformInfo.h:923
llvm::TargetTransformInfo::enableInterleavedAccessVectorization
bool enableInterleavedAccessVectorization() const
Enable matching of interleaved access groups.
Definition: TargetTransformInfo.cpp:549
llvm::TargetTransformInfo::Concept::prefersVectorizedAddressing
virtual bool prefersVectorizedAddressing()=0
llvm::TargetTransformInfo::SK_PermuteSingleSrc
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
Definition: TargetTransformInfo.h:897
llvm::TargetTransformInfo::Concept::getOrCreateResultFromMemIntrinsic
virtual Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType)=0
llvm::TargetTransformInfo::Concept::getCostOfKeepingLiveOverCall
virtual InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys)=0
llvm::TargetTransformInfo::getOperandsScalarizationOverhead
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys) const
Estimate the overhead of scalarizing an instructions unique non-constant operands.
Definition: TargetTransformInfo.cpp:522
llvm::TargetTransformInfo::Concept::getRegisterBitWidth
virtual TypeSize getRegisterBitWidth(RegisterKind K) const =0
llvm::TargetTransformInfo::UnrollingPreferences::AllowExpensiveTripCount
bool AllowExpensiveTripCount
Allow emitting expensive instructions (such as divisions) when computing the trip count of a loop for...
Definition: TargetTransformInfo.h:478
llvm::TargetTransformInfo::preferInLoopReduction
bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1139
llvm::TargetTransformInfo::CacheLevel
CacheLevel
The possible cache levels.
Definition: TargetTransformInfo.h:1020
llvm::TargetTransformInfo::Concept
Definition: TargetTransformInfo.h:1560
llvm::TargetTransformInfo::Concept::isLegalNTStore
virtual bool isLegalNTStore(Type *DataType, Align Alignment)=0
new
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32 n y store obj * new
Definition: README.txt:125
llvm::TargetTransformInfo::LSRCost::Insns
unsigned Insns
TODO: Some of these could be merged.
Definition: TargetTransformInfo.h:405
llvm::IntrinsicCostAttributes::getScalarizationCost
InstructionCost getScalarizationCost() const
Definition: TargetTransformInfo.h:154
llvm::TargetTransformInfo::SK_Broadcast
@ SK_Broadcast
Broadcast element 0 to all other elements.
Definition: TargetTransformInfo.h:887
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::TargetTransformInfo::Concept::getAddressComputationCost
virtual InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, const SCEV *Ptr)=0
llvm::TargetTransformInfo::Concept::getIntImmCodeSizeCost
virtual InstructionCost getIntImmCodeSizeCost(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty)=0
llvm::TargetTransformInfo::canHaveNonUndefGlobalInitializerInAddressSpace
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
Return true if globals in this address space can have initializers other than undef.
Definition: TargetTransformInfo.cpp:267
llvm::TargetTransformInfo::Concept::isLegalNTLoad
virtual bool isLegalNTLoad(Type *DataType, Align Alignment)=0
llvm::IntrinsicCostAttributes::skipScalarizationCost
bool skipScalarizationCost() const
Definition: TargetTransformInfo.h:162
llvm::TargetTransformInfo::requiresOrderedReduction
static bool requiresOrderedReduction(Optional< FastMathFlags > FMF)
A helper function to determine the type of reduction algorithm used for a given Opcode and set of Fas...
Definition: TargetTransformInfo.h:1266
llvm::BasicBlock
LLVM Basic Block Representation.
Definition: BasicBlock.h:55
llvm::HardwareLoopInfo::IsNestingLegal
bool IsNestingLegal
Definition: TargetTransformInfo.h:106
llvm::TargetTransformInfo::LSRCost::AddRecCost
unsigned AddRecCost
Definition: TargetTransformInfo.h:407
llvm::IntrinsicCostAttributes::getFlags
FastMathFlags getFlags() const
Definition: TargetTransformInfo.h:153
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::TargetTransformInfo::getUnrollingPreferences
void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE) const
Get target-customized preferences for the generic loop unrolling transformation.
Definition: TargetTransformInfo.cpp:334
Context
LLVMContext & Context
Definition: NVVMIntrRange.cpp:66
llvm::SmallBitVector
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
Definition: SmallBitVector.h:35
llvm::TargetTransformInfo::isLegalMaskedScatter
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
Return true if the target supports masked scatter.
Definition: TargetTransformInfo.cpp:427
Arg
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
Definition: AMDGPULibCalls.cpp:187
llvm::TargetTransformInfo::LSRCost::SetupCost
unsigned SetupCost
Definition: TargetTransformInfo.h:411
llvm::TargetTransformInfo::Concept::isLegalMaskedLoad
virtual bool isLegalMaskedLoad(Type *DataType, Align Alignment)=0
llvm::BitmaskEnumDetail::Mask
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::TargetTransformInfo::Concept::canMacroFuseCmp
virtual bool canMacroFuseCmp()=0
llvm::TargetTransformInfo::Concept::isTypeLegal
virtual bool isTypeLegal(Type *Ty)=0
llvm::TargetTransformInfo::getGISelRematGlobalCost
unsigned getGISelRematGlobalCost() const
Definition: TargetTransformInfo.cpp:1162
llvm::IntrinsicCostAttributes::getArgTypes
const SmallVectorImpl< Type * > & getArgTypes() const
Definition: TargetTransformInfo.h:156
llvm::TargetTransformInfo::areInlineCompatible
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
Definition: TargetTransformInfo.cpp:1071
llvm::TargetTransformInfo::Concept::getMinimumVF
virtual ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const =0
llvm::TargetTransformInfo::isTypeLegal
bool isTypeLegal(Type *Ty) const
Return true if this type is legal.
Definition: TargetTransformInfo.cpp:490
llvm::HardwareLoopInfo::ExitCount
const SCEV * ExitCount
Definition: TargetTransformInfo.h:102
llvm::TargetTransformInfo::SK_PermuteTwoSrc
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
Definition: TargetTransformInfo.h:895
llvm::TargetTransformInfo::Concept::getCacheSize
virtual Optional< unsigned > getCacheSize(CacheLevel Level) const =0
llvm::TargetTransformInfo::PeelingPreferences::PeelProfiledIterations
bool PeelProfiledIterations
Allow peeling basing on profile.
Definition: TargetTransformInfo.h:541
llvm::BlockFrequencyInfo
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Definition: BlockFrequencyInfo.h:37
llvm::TargetTransformInfo::getMinimumVF
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
Definition: TargetTransformInfo.cpp:666
llvm::MemIntrinsicInfo::isUnordered
bool isUnordered() const
Definition: TargetTransformInfo.h:88
llvm::TargetTransformInfo::Concept::getPredictableBranchThreshold
virtual BranchProbability getPredictableBranchThreshold()=0
llvm::TargetTransformInfo::isProfitableLSRChainElement
bool isProfitableLSRChainElement(Instruction *I) const
Definition: TargetTransformInfo.cpp:371
llvm::TargetTransformInfo::Concept::useAA
virtual bool useAA()=0
llvm::TargetTransformInfo::getCastContextHint
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
Definition: TargetTransformInfo.cpp:813
llvm::TargetTransformInfo::getOrCreateResultFromMemIntrinsic
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
Definition: TargetTransformInfo.cpp:1047
llvm::TargetTransformInfo::isLegalToVectorizeLoad
bool isLegalToVectorizeLoad(LoadInst *LI) const
Definition: TargetTransformInfo.cpp:1096
llvm::TargetTransformInfo::supportsTailCallFor
bool supportsTailCallFor(const CallBase *CB) const
If target supports tail call on CB.
Definition: TargetTransformInfo.cpp:535
llvm::MemIntrinsicInfo::Ordering
AtomicOrdering Ordering
Definition: TargetTransformInfo.h:79
llvm::TargetTransformInfo::getArithmeticInstrCost
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info={TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info={TTI::OK_AnyValue, TTI::OP_None}, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr) const
This is an approximation of reciprocal throughput of a math/logic op.
Definition: TargetTransformInfo.cpp:790
llvm::TargetTransformInfo::Concept::useColdCCForColdCall
virtual bool useColdCCForColdCall(Function &F)=0
llvm::TargetTransformInfoWrapperPass::ID
static char ID
Definition: TargetTransformInfo.h:2648
llvm::TargetTransformInfo::TargetCostConstants
TargetCostConstants
Underlying constants for 'cost' values in this interface.
Definition: TargetTransformInfo.h:242
llvm::TargetTransformInfo::getPopcntSupport
PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
Return hardware support for population count.
Definition: TargetTransformInfo.cpp:572
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis(const TargetIRAnalysis &Arg)
Definition: TargetTransformInfo.h:2602
llvm::TargetTransformInfo::OP_None
@ OP_None
Definition: TargetTransformInfo.h:915
llvm::TargetTransformInfo::ShuffleKind
ShuffleKind
The various kinds of shuffle patterns for vector queries.
Definition: TargetTransformInfo.h:886
llvm::TargetTransformInfo::getPreferredAddressingMode
AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
Return the preferred addressing mode LSR should make efforts to generate.
Definition: TargetTransformInfo.cpp:387
llvm::TargetTransformInfo::CastContextHint
CastContextHint
Represents a hint about the context in which a cast is used.
Definition: TargetTransformInfo.h:1138
llvm::TargetTransformInfo::Concept::getVPLegalizationStrategy
virtual VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const =0
llvm::User
Definition: User.h:44
llvm::TargetTransformInfo::Concept::allowsMisalignedMemoryAccesses
virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast)=0
llvm::TargetTransformInfo::useGPUDivergenceAnalysis
bool useGPUDivergenceAnalysis() const
Return true if the target prefers to use GPU divergence analysis to replace the legacy version.
Definition: TargetTransformInfo.cpp:241
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::TargetTransformInfo::UnrollingPreferences::Force
bool Force
Apply loop unroll on any kind of loop (mainly to loops that fail runtime unrolling).
Definition: TargetTransformInfo.h:481
InstrTypes.h
llvm::TargetTransformInfo::Concept::getMaxVScale
virtual Optional< unsigned > getMaxVScale() const =0
llvm::TargetTransformInfo::Concept::getPrefetchDistance
virtual unsigned getPrefetchDistance() const =0
llvm::TargetTransformInfo::hasBranchDivergence
bool hasBranchDivergence() const
Return true if branch divergence exists.
Definition: TargetTransformInfo.cpp:237
llvm::TargetTransformInfo::isLegalToVectorizeReduction
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
Definition: TargetTransformInfo.cpp:1116
llvm::TargetTransformInfo::getIntImmCost
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TargetCostKind CostKind) const
Return the expected cost of materializing for the given integer immediate of the specified type.
Definition: TargetTransformInfo.cpp:605
SI
@ SI
Definition: SIInstrInfo.cpp:7882
llvm::TargetTransformInfo::Concept::supportsEfficientVectorElementLoadStore
virtual bool supportsEfficientVectorElementLoadStore()=0
llvm::TargetTransformInfo::Concept::canSaveCmp
virtual bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo)=0
llvm::TargetTransformInfo::getNumberOfParts
unsigned getNumberOfParts(Type *Tp) const
Definition: TargetTransformInfo.cpp:984
llvm::TargetTransformInfo::Concept::isFCmpOrdCheaperThanFCmpZero
virtual bool isFCmpOrdCheaperThanFCmpZero(Type *Ty)=0
llvm::TargetTransformInfo::Concept::isNumRegsMajorCostOfLSR
virtual bool isNumRegsMajorCostOfLSR()=0
llvm::TargetTransformInfo::supportsScalableVectors
bool supportsScalableVectors() const
Definition: TargetTransformInfo.cpp:1170
llvm::TargetTransformInfo::isIndexedLoadLegal
bool isIndexedLoadLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1082
llvm::TargetTransformInfo::CastContextHint::Interleave
@ Interleave
The cast is used with an interleaved load/store.
llvm::TargetTransformInfo::UnrollingPreferences::MaxIterationsCountToAnalyze
unsigned MaxIterationsCountToAnalyze
Don't allow loop unrolling to simulate more than this number of iterations when checking full unroll ...
Definition: TargetTransformInfo.h:495
llvm::TargetTransformInfo::Concept::getNumberOfRegisters
virtual unsigned getNumberOfRegisters(unsigned ClassID) const =0
llvm::dwarf::Index
Index
Definition: Dwarf.h:472
llvm::TargetTransformInfo::Concept::isLegalToVectorizeLoadChain
virtual bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const =0
llvm::TargetTransformInfo::Concept::getInstructionCost
virtual InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TargetCostKind CostKind)=0
llvm::IntegerType
Class to represent integer types.
Definition: DerivedTypes.h:40
llvm::TargetTransformInfo::UnrollingPreferences::UnrollAndJam
bool UnrollAndJam
Allow unroll and jam. Used to enable unroll and jam for the target.
Definition: TargetTransformInfo.h:487
llvm::TargetTransformInfo::isLegalMaskedExpandLoad
bool isLegalMaskedExpandLoad(Type *DataType) const
Return true if the target supports masked expand load.
Definition: TargetTransformInfo.cpp:446
llvm::TargetTransformInfo::enableScalableVectorization
bool enableScalableVectorization() const
Definition: TargetTransformInfo.cpp:1174
llvm::TargetTransformInfo::Concept::supportsTailCalls
virtual bool supportsTailCalls()=0
llvm::TargetTransformInfo::Concept::simplifyDemandedVectorEltsIntrinsic
virtual Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp)=0
llvm::TargetTransformInfo::Concept::isLegalMaskedGather
virtual bool isLegalMaskedGather(Type *DataType, Align Alignment)=0
llvm::TargetTransformInfo::Concept::hasBranchDivergence
virtual bool hasBranchDivergence()=0
llvm::Instruction
Definition: Instruction.h:42
llvm::TargetTransformInfo::Concept::enableWritePrefetching
virtual bool enableWritePrefetching() const =0
llvm::TargetTransformInfo::MIM_PreDec
@ MIM_PreDec
Pre-decrementing.
Definition: TargetTransformInfo.h:1405
llvm::InterleavedAccessInfo
Drive the analysis of interleaved memory accesses in the loop.
Definition: VectorUtils.h:759
llvm::HardwareLoopInfo::PerformEntryTest
bool PerformEntryTest
Definition: TargetTransformInfo.h:110
llvm::TargetTransformInfo::Concept::getMaskedMemoryOpCost
virtual InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)=0
llvm::TargetTransformInfo::isLegalMaskedLoad
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
Return true if the target supports masked load.
Definition: TargetTransformInfo.cpp:397
llvm::TargetTransformInfo::isSourceOfDivergence
bool isSourceOfDivergence(const Value *V) const
Returns whether V is a source of divergence.
Definition: TargetTransformInfo.cpp:245
llvm::TargetTransformInfo::Concept::getReplicationShuffleCost
virtual InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)=0
llvm::TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:324
llvm::TargetTransformInfo::CastContextHint::Reversed
@ Reversed
The cast is used with a reversed load/store.
llvm::TargetTransformInfo::getPrefetchDistance
unsigned getPrefetchDistance() const
Definition: TargetTransformInfo.cpp:702
llvm::HardwareLoopInfo::CounterInReg
bool CounterInReg
Definition: TargetTransformInfo.h:108
llvm::TargetTransformInfo::Concept::isIndexedStoreLegal
virtual bool isIndexedStoreLegal(MemIndexedMode Mode, Type *Ty) const =0
llvm::TargetTransformInfo::Concept::supportsScalableVectors
virtual bool supportsScalableVectors() const =0
llvm::TargetTransformInfo::Concept::isLegalToVectorizeLoad
virtual bool isLegalToVectorizeLoad(LoadInst *LI) const =0
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::TargetTransformInfo::Concept::isLegalToVectorizeStoreChain
virtual bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const =0
llvm::TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const
Return true if it is faster to check if a floating-point value is NaN (or not-NaN) versus a compariso...
Definition: TargetTransformInfo.cpp:585
llvm::AnalysisManager::Invalidator
API to communicate dependencies between analyses during invalidation.
Definition: PassManager.h:661
Align
uint64_t Align
Definition: ELFObjHandler.cpp:82
llvm::TargetTransformInfo::Concept::getMemoryOpCost
virtual InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, OperandValueInfo OpInfo, const Instruction *I)=0
llvm::TargetTransformInfo::RGK_FixedWidthVector
@ RGK_FixedWidthVector
Definition: TargetTransformInfo.h:964
llvm::TargetTransformInfo::OperandValueInfo::Kind
OperandValueKind Kind
Definition: TargetTransformInfo.h:924
llvm::Align
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
llvm::TargetTransformInfo::OperandValueInfo::isUniform
bool isUniform() const
Definition: TargetTransformInfo.h:930
llvm::AddressSpace
AddressSpace
Definition: NVPTXBaseInfo.h:21
llvm::TargetTransformInfo::areTypesABICompatible
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
Definition: TargetTransformInfo.cpp:1076
llvm::IntrinsicCostAttributes
Definition: TargetTransformInfo.h:119
BranchProbability.h
llvm::TargetTransformInfo::VPLegalization::VPLegalization
VPLegalization(VPTransform EVLParamStrategy, VPTransform OpStrategy)
Definition: TargetTransformInfo.h:1537
llvm::TargetTransformInfo::Concept::getDataLayout
virtual const DataLayout & getDataLayout() const =0
llvm::TargetTransformInfo::hasVolatileVariant
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
Return true if the given instruction (assumed to be a memory access instruction) has a volatile varia...
Definition: TargetTransformInfo.cpp:458
llvm::TargetTransformInfo::PSK_Software
@ PSK_Software
Definition: TargetTransformInfo.h:585
llvm::ProfileSummaryInfo
Analysis providing profile information.
Definition: ProfileSummaryInfo.h:39
llvm::TargetTransformInfo::Concept::isElementTypeLegalForScalableVector
virtual bool isElementTypeLegalForScalableVector(Type *Ty) const =0
Operands
mir Rename Register Operands
Definition: MIRNamerPass.cpp:74
llvm::TargetTransformInfo::isLegalMaskedCompressStore
bool isLegalMaskedCompressStore(Type *DataType) const
Return true if the target supports masked compress store.
Definition: TargetTransformInfo.cpp:442
llvm::PredicationStyle::DataAndControlFlow
@ DataAndControlFlow
llvm::TargetTransformInfo::haveFastSqrt
bool haveFastSqrt(Type *Ty) const
Return true if the hardware has a fast square-root instruction.
Definition: TargetTransformInfo.cpp:576
llvm::createTargetTransformInfoWrapperPass
ImmutablePass * createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA)
Create an analysis pass wrapper around a TTI object.
Definition: TargetTransformInfo.cpp:1229
llvm::TargetTransformInfo::VPLegalization::EVLParamStrategy
VPTransform EVLParamStrategy
Definition: TargetTransformInfo.h:1526
llvm::TargetTransformInfo::SK_Reverse
@ SK_Reverse
Reverse the order of the vector.
Definition: TargetTransformInfo.h:888
llvm::TargetTransformInfo::preferPredicateOverEpilogue
bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI) const
Query the target whether it would be prefered to create a predicated vector loop, which can avoid the...
Definition: TargetTransformInfo.cpp:300
llvm::TargetTransformInfo::Concept::collectFlatAddressOperands
virtual bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const =0
llvm::TargetTransformInfo::VPLegalization::VPTransform
VPTransform
Definition: TargetTransformInfo.h:1513
llvm::TargetTransformInfo::getFlatAddressSpace
unsigned getFlatAddressSpace() const
Returns the address space ID for a target's 'flat' address space.
Definition: TargetTransformInfo.cpp:253
llvm::VectorType
Base class of all SIMD vector types.
Definition: DerivedTypes.h:389
llvm::AtomicOrdering
AtomicOrdering
Atomic ordering for LLVM's memory model.
Definition: AtomicOrdering.h:56
llvm::TargetTransformInfo::CastContextHint::Normal
@ Normal
The cast is used with a normal load/store.
llvm::TargetTransformInfo::Concept::~Concept
virtual ~Concept()=0
llvm::TargetTransformInfo::Concept::getIntrinsicInstrCost
virtual InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)=0
llvm::SCEV
This class represents an analyzed expression in the program.
Definition: ScalarEvolution.h:75
llvm::StoreInst
An instruction for storing to memory.
Definition: Instructions.h:297
llvm::GlobalValue
Definition: GlobalValue.h:44
llvm::TargetTransformInfo::Concept::preferPredicateOverEpilogue
virtual bool preferPredicateOverEpilogue(Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI, DominatorTree *DT, LoopVectorizationLegality *LVL, InterleavedAccessInfo *IAI)=0
llvm::TargetTransformInfo::Concept::hasActiveVectorLength
virtual bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const =0
llvm::TargetTransformInfo::SK_InsertSubvector
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
Definition: TargetTransformInfo.h:893
llvm::Constant
This is an important base class in LLVM.
Definition: Constant.h:41
llvm::TargetTransformInfo::OperandValueInfo::isPowerOf2
bool isPowerOf2() const
Definition: TargetTransformInfo.h:933
llvm::TargetTransformInfo::Concept::isProfitableLSRChainElement
virtual bool isProfitableLSRChainElement(Instruction *I)=0
llvm::TargetTransformInfo::shouldBuildLookupTablesForConstant
bool shouldBuildLookupTablesForConstant(Constant *C) const
Return true if switches should be turned into lookup tables containing this constant value for the ta...
Definition: TargetTransformInfo.cpp:502
llvm::TargetTransformInfo::Concept::shouldMaximizeVectorBandwidth
virtual bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const =0
llvm::TargetTransformInfo::MIM_PostInc
@ MIM_PostInc
Post-incrementing.
Definition: TargetTransformInfo.h:1406
llvm::HardwareLoopInfo::HardwareLoopInfo
HardwareLoopInfo()=delete
llvm::TargetTransformInfo::Concept::getMemcpyLoopResidualLoweringType
virtual void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize) const =0
Index
uint32_t Index
Definition: ELFObjHandler.cpp:83
llvm::TargetTransformInfo::LSRCost
Definition: TargetTransformInfo.h:402
llvm::TargetTransformInfo::collectFlatAddressOperands
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
Return any intrinsic address operand indexes which may be rewritten if they use a flat address space ...
Definition: TargetTransformInfo.cpp:257
llvm::TargetTransformInfo::VPLegalization::OpStrategy
VPTransform OpStrategy
Definition: TargetTransformInfo.h:1532
llvm::TargetTransformInfo::isLegalMaskedGather
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
Return true if the target supports masked gather.
Definition: TargetTransformInfo.cpp:416
llvm::TargetTransformInfoWrapperPass
Wrapper pass for TargetTransformInfo.
Definition: TargetTransformInfo.h:2641
llvm::TargetTransformInfo::Concept::getInterleavedMemoryOpCost
virtual InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)=0
llvm::TargetTransformInfo::preferPredicatedReductionSelect
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags Flags) const
Definition: TargetTransformInfo.cpp:1144
llvm::TargetTransformInfo::Concept::hasDivRemOp
virtual bool hasDivRemOp(Type *DataType, bool IsSigned)=0
llvm::TargetTransformInfo::Concept::isLSRCostLess
virtual bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)=0
llvm::TargetTransformInfo::getInterleavedMemoryOpCost
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, bool UseMaskForCond=false, bool UseMaskForGaps=false) const
Definition: TargetTransformInfo.cpp:956
llvm::TargetTransformInfo::ReductionFlags::NoNaN
bool NoNaN
If op is an fp min/max, whether NaNs may be present.
Definition: TargetTransformInfo.h:1459
llvm::TargetTransformInfo::Concept::shouldBuildLookupTables
virtual bool shouldBuildLookupTables()=0
llvm::TargetTransformInfo::OK_UniformConstantValue
@ OK_UniformConstantValue
Definition: TargetTransformInfo.h:909
llvm::TargetTransformInfo::forceScalarizeMaskedGather
bool forceScalarizeMaskedGather(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.gather intrinsics.
Definition: TargetTransformInfo.cpp:432
llvm::TargetIRAnalysis::Result
TargetTransformInfo Result
Definition: TargetTransformInfo.h:2587
llvm::TargetTransformInfo::getMaxInterleaveFactor
unsigned getMaxInterleaveFactor(unsigned VF) const
Definition: TargetTransformInfo.cpp:725
llvm::TargetTransformInfo::VPLegalization::shouldDoNothing
bool shouldDoNothing() const
Definition: TargetTransformInfo.h:1534
llvm::TargetTransformInfo::getRegisterClassForType
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
Definition: TargetTransformInfo.cpp:635
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::TargetTransformInfo::Concept::getMaximumVF
virtual unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const =0
llvm::LLVMContext
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
llvm::TargetTransformInfo::preferEpilogueVectorization
bool preferEpilogueVectorization() const
Return true if the loop vectorizer should consider vectorizing an otherwise scalar epilogue loop.
Definition: TargetTransformInfo.cpp:1149
llvm::TargetTransformInfo::isLegalAltInstr
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
Return true if this is an alternating opcode pattern that can be lowered to a single instruction on t...
Definition: TargetTransformInfo.cpp:421
llvm::AnalysisKey
A special type used by analysis passes to provide an address that identifies that particular analysis...
Definition: PassManager.h:69
llvm::TargetTransformInfo::UnrollingPreferences
Parameters that control the generic loop unrolling transformation.
Definition: TargetTransformInfo.h:416
llvm::TargetTransformInfo::getCostOfKeepingLiveOverCall
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
Definition: TargetTransformInfo.cpp:1034
llvm::AtomicOrdering::Unordered
@ Unordered
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetTransformInfo::OperandValueProperties
OperandValueProperties
Additional properties of an operand's values.
Definition: TargetTransformInfo.h:914
llvm::TargetTransformInfo::Concept::isLegalMaskedStore
virtual bool isLegalMaskedStore(Type *DataType, Align Alignment)=0
llvm::TargetTransformInfo::shouldConsiderAddressTypePromotion
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
Definition: TargetTransformInfo.cpp:681
llvm::TargetTransformInfo::Concept::getExtendedReductionCost
virtual InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput)=0
llvm::TargetTransformInfo::Concept::getScalarizationOverhead
virtual InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)=0
llvm::TargetTransformInfo::Concept::getVPMemoryOpCost
virtual InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I)=0
llvm::TargetTransformInfo::Concept::getTgtMemIntrinsic
virtual bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info)=0
llvm::TargetTransformInfo::getScalarizationOverhead
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract) const
Estimate the overhead of scalarizing an instruction.
Definition: TargetTransformInfo.cpp:516
llvm::TargetTransformInfo::getReplicationShuffleCost
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
Definition: TargetTransformInfo.cpp:917
llvm::TargetTransformInfo::isExpensiveToSpeculativelyExecute
bool isExpensiveToSpeculativelyExecute(const Instruction *I) const
Return true if the cost of the instruction is too high to speculatively execute and should be kept be...
Definition: TargetTransformInfo.cpp:580
llvm::TargetTransformInfo::PeelingPreferences::AllowLoopNestsPeeling
bool AllowLoopNestsPeeling
Allow peeling off loop iterations for loop nests.
Definition: TargetTransformInfo.h:536
llvm::TargetTransformInfo::rewriteIntrinsicWithAddressSpace
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
Rewrite intrinsic call II such that OldV will be replaced with NewV, which has a different address sp...
Definition: TargetTransformInfo.cpp:285
llvm::TargetTransformInfo::isLSRCostLess
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2) const
Return true if LSR cost of C1 is lower than C2.
Definition: TargetTransformInfo.cpp:362
llvm::TargetTransformInfo::Concept::shouldExpandReduction
virtual bool shouldExpandReduction(const IntrinsicInst *II) const =0
llvm::TargetTransformInfo::Concept::getLoadVectorFactor
virtual unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const =0
llvm::TargetTransformInfo::getGatherScatterOpCost
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:947
llvm::TargetTransformInfo::VPLegalization::Discard
@ Discard
Definition: TargetTransformInfo.h:1517
llvm::TargetTransformInfo::Concept::getCastInstrCost
virtual InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I)=0
llvm::move
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1836
llvm::TargetTransformInfo::Concept::isLoweredToCall
virtual bool isLoweredToCall(const Function *F)=0
llvm::TargetTransformInfo::LSRWithInstrQueries
bool LSRWithInstrQueries() const
Return true if the loop strength reduce pass should make Instruction* based TTI queries to isLegalAdd...
Definition: TargetTransformInfo.cpp:476
llvm::TargetTransformInfo::Concept::getScalingFactorCost
virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace)=0
llvm::TargetTransformInfo::getMinMaxReductionCost
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:1011
llvm::TargetTransformInfo::isLegalToVectorizeLoadChain
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1104
Ptr
@ Ptr
Definition: TargetLibraryInfo.cpp:60
llvm::TargetTransformInfo::getGEPCost
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, TargetCostKind CostKind=TCK_SizeAndLatency) const
Estimate the cost of a GEP operation when lowered.
Definition: TargetTransformInfo.cpp:211
llvm::TargetTransformInfo::Concept::isSingleThreaded
virtual bool isSingleThreaded() const =0
llvm::TargetTransformInfo::isLegalAddImmediate
bool isLegalAddImmediate(int64_t Imm) const
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
Definition: TargetTransformInfo.cpp:345
llvm::TTI
TargetTransformInfo TTI
Definition: TargetTransformInfo.h:167
llvm::TargetTransformInfo::Concept::getOperandsScalarizationOverhead
virtual InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys)=0
Mode
SI Whole Quad Mode
Definition: SIWholeQuadMode.cpp:264
function
print Print MemDeps of function
Definition: MemDepPrinter.cpp:82
llvm::TargetTransformInfo::LSRCost::ScaleCost
unsigned ScaleCost
Definition: TargetTransformInfo.h:412
llvm::TargetTransformInfo::isLoweredToCall
bool isLoweredToCall(const Function *F) const
Test whether calls to a function lower to actual program function calls.
Definition: TargetTransformInfo.cpp:290
llvm::TargetTransformInfo::OperandValueInfo::getNoProps
OperandValueInfo getNoProps() const
Definition: TargetTransformInfo.h:940
llvm::TargetTransformInfo::SK_Splice
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
Definition: TargetTransformInfo.h:899
llvm::TargetTransformInfo::Concept::getVScaleForTuning
virtual Optional< unsigned > getVScaleForTuning() const =0
llvm::TargetTransformInfo::getCastInstrCost
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:856
llvm::TargetTransformInfo::Concept::shouldBuildRelLookupTables
virtual bool shouldBuildRelLookupTables()=0
llvm::TargetTransformInfo::PSK_SlowHardware
@ PSK_SlowHardware
Definition: TargetTransformInfo.h:585
llvm::TargetTransformInfo::Concept::getRegisterClassName
virtual const char * getRegisterClassName(unsigned ClassID) const =0
llvm::AnalysisInfoMixin
A CRTP mix-in that provides informational APIs needed for analysis passes.
Definition: PassManager.h:394
llvm::TargetTransformInfo::ReductionFlags::IsSigned
bool IsSigned
Whether the operation is a signed int reduction.
Definition: TargetTransformInfo.h:1458
llvm::TargetTransformInfo::OperandValueKind
OperandValueKind
Additional information about an operand's possible values.
Definition: TargetTransformInfo.h:906
llvm::TargetTransformInfo::Concept::instCombineIntrinsic
virtual Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II)=0
llvm::MemIntrinsicInfo::ReadMem
bool ReadMem
Definition: TargetTransformInfo.h:84
llvm::TargetTransformInfo::Concept::getCmpSelInstrCost
virtual InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I)=0
llvm::TargetTransformInfo::MemCmpExpansionOptions::MaxNumLoads
unsigned MaxNumLoads
Definition: TargetTransformInfo.h:785
InstructionCost.h
llvm::APInt
Class for arbitrary precision integers.
Definition: APInt.h:75
llvm::TargetTransformInfo::canSaveCmp
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
Return true if the target can save a compare for loop count, for example hardware loop saves a compar...
Definition: TargetTransformInfo.cpp:379
llvm::TargetTransformInfo::isTruncateFree
bool isTruncateFree(Type *Ty1, Type *Ty2) const
Return true if it's free to truncate a value of type Ty1 to type Ty2.
Definition: TargetTransformInfo.cpp:480
llvm::TargetTransformInfo::prefersVectorizedAddressing
bool prefersVectorizedAddressing() const
Return true if target doesn't mind addresses in vectors.
Definition: TargetTransformInfo.cpp:463
llvm::TargetTransformInfo::MemCmpExpansionOptions
Returns options for expansion of memcmp. IsZeroCmp is.
Definition: TargetTransformInfo.h:780
llvm::TargetTransformInfo::TCC_Free
@ TCC_Free
Expected to fold away in lowering.
Definition: TargetTransformInfo.h:243
llvm::TargetTransformInfo::PeelingPreferences::PeelCount
unsigned PeelCount
A forced peeling factor (the number of bodied of the original loop that should be peeled off before t...
Definition: TargetTransformInfo.h:532
llvm::TargetTransformInfo::Concept::getMulAccReductionCost
virtual InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput)=0
llvm::TargetTransformInfo::supportsEfficientVectorElementLoadStore
bool supportsEfficientVectorElementLoadStore() const
If target has efficient vector element load/store instructions, it can return true here so that inser...
Definition: TargetTransformInfo.cpp:527
llvm::TargetTransformInfo::emitGetActiveLaneMask
PredicationStyle emitGetActiveLaneMask() const
Query the target whether lowering of the llvm.get.active.lane.mask intrinsic is supported and how the...
Definition: TargetTransformInfo.cpp:307
llvm::TargetTransformInfo::enableMemCmpExpansion
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
Definition: TargetTransformInfo.cpp:545
llvm::TargetTransformInfo::Concept::shouldConsiderAddressTypePromotion
virtual bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader)=0
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::LoopInfo
Definition: LoopInfo.h:1108
llvm::OptimizationRemarkEmitter
The optimization diagnostic interface.
Definition: OptimizationRemarkEmitter.h:33
llvm::AssumptionCache
A cache of @llvm.assume calls within a function.
Definition: AssumptionCache.h:42
llvm::TargetTransformInfo::TCK_SizeAndLatency
@ TCK_SizeAndLatency
The weighted sum of size and latency.
Definition: TargetTransformInfo.h:221
llvm::TargetTransformInfo::Concept::haveFastSqrt
virtual bool haveFastSqrt(Type *Ty)=0
llvm::TargetTransformInfo::Concept::isNoopAddrSpaceCast
virtual bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const =0
llvm::TargetTransformInfo::isElementTypeLegalForScalableVector
bool isElementTypeLegalForScalableVector(Type *Ty) const
Definition: TargetTransformInfo.cpp:1121
llvm::TargetTransformInfo::isLegalMaskedStore
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
Return true if the target supports masked store.
Definition: TargetTransformInfo.cpp:392
llvm::TargetTransformInfo::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
Definition: TargetTransformInfo.cpp:281
llvm::TargetTransformInfo::Concept::isIndexedLoadLegal
virtual bool isIndexedLoadLegal(MemIndexedMode Mode, Type *Ty) const =0
CostKind
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
llvm::BranchProbability
Definition: BranchProbability.h:30
llvm::TargetTransformInfo::Concept::getMinTripCountTailFoldingThreshold
virtual unsigned getMinTripCountTailFoldingThreshold() const =0
llvm::TargetTransformInfo::Concept::getFlatAddressSpace
virtual unsigned getFlatAddressSpace()=0
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::TargetTransformInfo::Concept::emitGetActiveLaneMask
virtual PredicationStyle emitGetActiveLaneMask()=0
llvm::TargetTransformInfo::UnrollingPreferences::DefaultUnrollRuntimeCount
unsigned DefaultUnrollRuntimeCount
Default unroll count for loops with run-time trip count.
Definition: TargetTransformInfo.h:452
llvm::TargetTransformInfo::hasDivRemOp
bool hasDivRemOp(Type *DataType, bool IsSigned) const
Return true if the target has a unified operation to calculate division and remainder.
Definition: TargetTransformInfo.cpp:454
llvm::TargetTransformInfo::Concept::LSRWithInstrQueries
virtual bool LSRWithInstrQueries()=0
llvm::TargetTransformInfo::simplifyDemandedUseBitsIntrinsic
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Can be used to implement target-specific instruction combining.
Definition: TargetTransformInfo.cpp:317
llvm::TargetTransformInfo::getCacheSize
Optional< unsigned > getCacheSize(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:693
llvm::TargetTransformInfo::getNumberOfRegisters
unsigned getNumberOfRegisters(unsigned ClassID) const
Definition: TargetTransformInfo.cpp:631
llvm::TargetTransformInfo::shouldPrefetchAddressSpace
bool shouldPrefetchAddressSpace(unsigned AS) const
Definition: TargetTransformInfo.cpp:721
llvm::InstructionCost::isValid
bool isValid() const
Definition: InstructionCost.h:79
llvm::TargetTransformInfo::AddressingModeKind
AddressingModeKind
Definition: TargetTransformInfo.h:632
llvm::TargetTransformInfo::getMaxPrefetchIterationsAhead
unsigned getMaxPrefetchIterationsAhead() const
Definition: TargetTransformInfo.cpp:713
llvm::TargetTransformInfo::MIM_Unindexed
@ MIM_Unindexed
No indexing.
Definition: TargetTransformInfo.h:1403
llvm::AMDGPUISD::BFI
@ BFI
Definition: AMDGPUISelLowering.h:432
llvm::TargetTransformInfo::OK_AnyValue
@ OK_AnyValue
Definition: TargetTransformInfo.h:907
llvm::TargetTransformInfo::getLoadVectorFactor
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1125
llvm::LoadInst
An instruction for reading from memory.
Definition: Instructions.h:173
llvm::TargetTransformInfo::SK_Transpose
@ SK_Transpose
Transpose two vectors.
Definition: TargetTransformInfo.h:892
llvm::TargetTransformInfo::CastContextHint::None
@ None
The cast is not used with a load/store of any kind.
llvm::TargetTransformInfo::isLegalToVectorizeStore
bool isLegalToVectorizeStore(StoreInst *SI) const
Definition: TargetTransformInfo.cpp:1100
llvm::TargetTransformInfo::CacheLevel::L2D
@ L2D
llvm::TargetTransformInfo::Concept::getAssumedAddrSpace
virtual unsigned getAssumedAddrSpace(const Value *V) const =0
llvm::TargetTransformInfo::MIM_PreInc
@ MIM_PreInc
Pre-incrementing.
Definition: TargetTransformInfo.h:1404
llvm::TargetTransformInfo::MemCmpExpansionOptions::LoadSizes
SmallVector< unsigned, 8 > LoadSizes
Definition: TargetTransformInfo.h:788
llvm::TargetIRAnalysis::TargetIRAnalysis
TargetIRAnalysis()
Default construct a target IR analysis.
Definition: TargetTransformInfo.cpp:1185
llvm::TargetTransformInfo::Concept::preferInLoopReduction
virtual bool preferInLoopReduction(unsigned Opcode, Type *Ty, ReductionFlags) const =0
Callee
amdgpu Simplify well known AMD library false FunctionCallee Callee
Definition: AMDGPULibCalls.cpp:187
llvm::TargetTransformInfo::enableOrderedReductions
bool enableOrderedReductions() const
Return true if we should be enabling ordered reductions for the target.
Definition: TargetTransformInfo.cpp:450
llvm::TargetTransformInfo::getMaxVScale
Optional< unsigned > getMaxVScale() const
Definition: TargetTransformInfo.cpp:653
llvm::TargetTransformInfo::Concept::forceScalarizeMaskedGather
virtual bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment)=0
llvm::TargetTransformInfo::OP_NegatedPowerOf2
@ OP_NegatedPowerOf2
Definition: TargetTransformInfo.h:917
llvm::TargetTransformInfo::Concept::getStoreMinimumVF
virtual unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const =0
llvm::TargetTransformInfo::getMemcpyLoopResidualLoweringType
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicCpySize=None) const
Definition: TargetTransformInfo.cpp:1061
llvm::TargetTransformInfo::Concept::supportsTailCallFor
virtual bool supportsTailCallFor(const CallBase *CB)=0
llvm::TargetTransformInfo::getMemcpyLoopLoweringType
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, Optional< uint32_t > AtomicElementSize=None) const
Definition: TargetTransformInfo.cpp:1052
llvm::TargetTransformInfo::Concept::isLegalICmpImmediate
virtual bool isLegalICmpImmediate(int64_t Imm)=0
llvm::TargetTransformInfo::getCacheAssociativity
Optional< unsigned > getCacheAssociativity(CacheLevel Level) const
Definition: TargetTransformInfo.cpp:698
llvm::TargetTransformInfo::getCacheLineSize
unsigned getCacheLineSize() const
Definition: TargetTransformInfo.cpp:687
llvm::TargetTransformInfo::supportsTailCalls
bool supportsTailCalls() const
If the target supports tail calls.
Definition: TargetTransformInfo.cpp:531
std
Definition: BitVector.h:851
llvm::TargetTransformInfo::enableMaskedInterleavedAccessVectorization
bool enableMaskedInterleavedAccessVectorization() const
Enable matching of interleaved access groups that contain predicated accesses or gaps and therefore v...
Definition: TargetTransformInfo.cpp:553
llvm::KnownBits
Definition: KnownBits.h:23
llvm::TargetTransformInfo::LSRCost::NumBaseAdds
unsigned NumBaseAdds
Definition: TargetTransformInfo.h:409
llvm::TargetIRAnalysis::operator=
TargetIRAnalysis & operator=(TargetIRAnalysis &&RHS)
Definition: TargetTransformInfo.h:2610
llvm::None
constexpr std::nullopt_t None
Definition: None.h:27
llvm::HardwareLoopInfo::ExitBlock
BasicBlock * ExitBlock
Definition: TargetTransformInfo.h:100
llvm::MemIntrinsicInfo::WriteMem
bool WriteMem
Definition: TargetTransformInfo.h:85
llvm::TargetTransformInfo::UnrollingPreferences::UpperBound
bool UpperBound
Allow using trip count upper bound to unroll loops.
Definition: TargetTransformInfo.h:483
llvm::TargetTransformInfo::getMulAccReductionCost
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of an extended reduction pattern, similar to getArithmeticReductionCost of an Add ...
Definition: TargetTransformInfo.cpp:1027
llvm::VPIntrinsic
This is the common base class for vector predication intrinsics.
Definition: IntrinsicInst.h:475
llvm::TargetTransformInfo::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
Definition: TargetTransformInfo.cpp:262
llvm::TargetTransformInfo::getOperandInfo
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
Definition: TargetTransformInfo.cpp:730
llvm::TypeSize
Definition: TypeSize.h:435
llvm::TargetTransformInfo::getLoadStoreVecRegBitWidth
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1092
llvm::TargetTransformInfo::UnrollingPreferences::AllowRemainder
bool AllowRemainder
Allow generation of a loop remainder (extra iterations after unroll).
Definition: TargetTransformInfo.h:475
llvm::TargetTransformInfo::Concept::enableAggressiveInterleaving
virtual bool enableAggressiveInterleaving(bool LoopHasReductions)=0
llvm::BitWidth
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:147
llvm::TargetTransformInfo::shouldMaximizeVectorBandwidth
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
Definition: TargetTransformInfo.cpp:661
llvm::TargetTransformInfo::isFPVectorizationPotentiallyUnsafe
bool isFPVectorizationPotentiallyUnsafe() const
Indicate that it is potentially unsafe to automatically vectorize floating-point operations because t...
Definition: TargetTransformInfo.cpp:557
llvm::TargetTransformInfo::Concept::isLegalBroadcastLoad
virtual bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const =0
llvm::TargetStackID::Value
Value
Definition: TargetFrameLowering.h:27
PassManager.h
Arguments
AMDGPU Lower Kernel Arguments
Definition: AMDGPULowerKernelArguments.cpp:242
llvm::TargetLibraryInfo
Provides information about what library functions are available for the current target.
Definition: TargetLibraryInfo.h:225
llvm::User::operand_values
iterator_range< value_op_iterator > operand_values()
Definition: User.h:266
llvm::TargetTransformInfo::LSRCost::ImmCost
unsigned ImmCost
Definition: TargetTransformInfo.h:410
llvm::TargetTransformInfo::hasActiveVectorLength
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
Definition: TargetTransformInfo.cpp:1178
llvm::TargetTransformInfo::forceScalarizeMaskedScatter
bool forceScalarizeMaskedScatter(VectorType *Type, Align Alignment) const
Return true if the target forces scalarizing of llvm.masked.scatter intrinsics.
Definition: TargetTransformInfo.cpp:437
llvm::TargetTransformInfo::getMemoryOpCost
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, OperandValueInfo OpdInfo={OK_AnyValue, OP_None}, const Instruction *I=nullptr) const
Definition: TargetTransformInfo.cpp:926
llvm::TargetIRAnalysis::run
Result run(const Function &F, FunctionAnalysisManager &)
Definition: TargetTransformInfo.cpp:1191
llvm::TargetTransformInfo::getInstructionCost
InstructionCost getInstructionCost(const User *U, TargetCostKind CostKind) const
This is a helper function which calls the three-argument getInstructionCost with Operands which are t...
Definition: TargetTransformInfo.h:308
llvm::HardwareLoopInfo::HardwareLoopInfo
HardwareLoopInfo(Loop *L)
Definition: TargetTransformInfo.h:98
llvm::TargetTransformInfo::Concept::getFPOpCost
virtual InstructionCost getFPOpCost(Type *Ty)=0
llvm::TargetTransformInfo::getInliningThresholdMultiplier
unsigned getInliningThresholdMultiplier() const
Definition: TargetTransformInfo.cpp:197
llvm::TargetTransformInfo::getVectorInstrCost
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index=-1) const
Definition: TargetTransformInfo.cpp:895
llvm::PredicationStyle
PredicationStyle
Definition: TargetTransformInfo.h:165
llvm::InstCombiner
The core instruction combiner logic.
Definition: InstCombiner.h:45
llvm::TargetTransformInfo::adjustInliningThreshold
unsigned adjustInliningThreshold(const CallBase *CB) const
Definition: TargetTransformInfo.cpp:202
llvm::TargetTransformInfo::getMaskedMemoryOpCost
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Definition: TargetTransformInfo.cpp:938
llvm::TargetTransformInfo::RGK_ScalableVector
@ RGK_ScalableVector
Definition: TargetTransformInfo.h:964
llvm::TargetTransformInfo::getMinTripCountTailFoldingThreshold
unsigned getMinTripCountTailFoldingThreshold() const
Definition: TargetTransformInfo.cpp:1166
llvm::IntrinsicInst
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:46
llvm::HardwareLoopInfo
Attributes of a target dependent hardware loop.
Definition: TargetTransformInfo.h:96
llvm::InstructionCost::getInvalid
static InstructionCost getInvalid(CostType Val=0)
Definition: InstructionCost.h:73
llvm::TargetTransformInfo::getEstimatedNumberOfCaseClusters
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
Definition: TargetTransformInfo.cpp:217
llvm::RISCVMatInt::Imm
@ Imm
Definition: RISCVMatInt.h:23
llvm::TargetTransformInfo::TargetTransformInfo
TargetTransformInfo(T Impl)
Construct a TTI object using a type implementing the Concept API below.
Definition: TargetTransformInfo.h:2571
llvm::RecurrenceDescriptor
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:69
llvm::TargetTransformInfo::Concept::isLegalAltInstr
virtual bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const =0
llvm::TargetTransformInfo::Concept::getCallInstrCost
virtual InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind)=0
llvm::TargetTransformInfo::Concept::getArithmeticReductionCost
virtual InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)=0
llvm::TargetTransformInfo::MemCmpExpansionOptions::NumLoadsPerBlock
unsigned NumLoadsPerBlock
Definition: TargetTransformInfo.h:798
llvm::TargetTransformInfo::getArithmeticReductionCost
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput) const
Calculate the cost of vector reduction intrinsics.
Definition: TargetTransformInfo.cpp:1002
llvm::IntrinsicCostAttributes::getID
Intrinsic::ID getID() const
Definition: TargetTransformInfo.h:150
llvm::TargetTransformInfo::Concept::getGISelRematGlobalCost
virtual unsigned getGISelRematGlobalCost() const =0
llvm::TargetTransformInfo::RegisterKind
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Definition: TargetTransformInfo.h:964
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virtual InstructionCost getIntImmCostInst(unsigned Opc, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind, Instruction *Inst=nullptr)=0
llvm::TargetTransformInfo::Concept::getCFInstrCost
virtual InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)=0
llvm::TargetTransformInfo::invalidate
bool invalidate(Function &, const PreservedAnalyses &, FunctionAnalysisManager::Invalidator &)
Handle the invalidation of this information.
Definition: TargetTransformInfo.h:201
llvm::TargetTransformInfo::Concept::getInlinerVectorBonusPercent
virtual int getInlinerVectorBonusPercent()=0
llvm::TargetTransformInfo::Concept::isLegalAddImmediate
virtual bool isLegalAddImmediate(int64_t Imm)=0
SmallBitVector.h
llvm::TargetTransformInfo::UnrollingPreferences::Threshold
unsigned Threshold
The cost threshold for the unrolled loop.
Definition: TargetTransformInfo.h:424
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ReductionFlags()=default
llvm::TargetTransformInfo::Concept::enableScalableVectorization
virtual bool enableScalableVectorization() const =0
llvm::TargetTransformInfo::Concept::getNumberOfParts
virtual unsigned getNumberOfParts(Type *Tp)=0
llvm::TargetTransformInfo::Concept::getPredicatedAddrSpace
virtual std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const =0
llvm::TargetTransformInfo::VPLegalization::Legal
@ Legal
Definition: TargetTransformInfo.h:1515
llvm::TargetTransformInfo::Concept::shouldBuildLookupTablesForConstant
virtual bool shouldBuildLookupTablesForConstant(Constant *C)=0
llvm::TargetTransformInfo::Concept::isProfitableToHoist
virtual bool isProfitableToHoist(Instruction *I)=0
llvm::TargetTransformInfo::getMinPrefetchStride
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Some HW prefetchers can handle accesses up to a certain constant stride.
Definition: TargetTransformInfo.cpp:706
llvm::TargetTransformInfo::isIndexedStoreLegal
bool isIndexedStoreLegal(enum MemIndexedMode Mode, Type *Ty) const
Definition: TargetTransformInfo.cpp:1087
llvm::TargetTransformInfo::isNumRegsMajorCostOfLSR
bool isNumRegsMajorCostOfLSR() const
Return true if LSR major cost is number of registers.
Definition: TargetTransformInfo.cpp:367
llvm::TargetTransformInfo::shouldExpandReduction
bool shouldExpandReduction(const IntrinsicInst *II) const
Definition: TargetTransformInfo.cpp:1158
llvm::TargetTransformInfo::getExtractWithExtendCost
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
Definition: TargetTransformInfo.cpp:867
llvm::TargetTransformInfo::Concept::isLegalAddressingMode
virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I)=0
llvm::TargetTransformInfo::getPeelingPreferences
void getPeelingPreferences(Loop *L, ScalarEvolution &SE, PeelingPreferences &PP) const
Get target-customized preferences for the generic loop peeling transformation.
Definition: TargetTransformInfo.cpp:340
llvm::TargetTransformInfo::getStoreVectorFactor
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
Definition: TargetTransformInfo.cpp:1132
llvm::TargetTransformInfo::Concept::getCacheAssociativity
virtual Optional< unsigned > getCacheAssociativity(CacheLevel Level) const =0
llvm::TargetTransformInfo::MIM_PostDec
@ MIM_PostDec
Post-decrementing.
Definition: TargetTransformInfo.h:1407
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bool canAnalyze(LoopInfo &LI)
Definition: TargetTransformInfo.cpp:50
llvm::TargetTransformInfo::isLegalToVectorizeStoreChain
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
Definition: TargetTransformInfo.cpp:1110
llvm::SmallVectorImpl< const Value * >
llvm::TargetTransformInfo::Concept::getArithmeticInstrCost
virtual InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, OperandValueInfo Opd1Info, OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr)=0
ForceHardwareLoopPHI
static cl::opt< bool > ForceHardwareLoopPHI("force-hardware-loop-phi", cl::Hidden, cl::init(false), cl::desc("Force hardware loop counter to be updated through a phi"))
llvm::TargetTransformInfo::Concept::preferPredicatedReductionSelect
virtual bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, ReductionFlags) const =0
llvm::MemIntrinsicInfo
Information about a load/store intrinsic defined by the target.
Definition: TargetTransformInfo.h:71
llvm::TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize
unsigned getAtomicMemIntrinsicMaxElementSize() const
Definition: TargetTransformInfo.cpp:1043
llvm::msgpack::Type
Type
MessagePack types as defined in the standard, with the exception of Integer being divided into a sign...
Definition: MsgPackReader.h:48
llvm::CallBase
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1174
llvm::TargetTransformInfo::enableAggressiveInterleaving
bool enableAggressiveInterleaving(bool LoopHasReductions) const
Don't restrict interleaved unrolling to small loops.
Definition: TargetTransformInfo.cpp:539
llvm::TargetTransformInfo::Concept::areInlineCompatible
virtual bool areInlineCompatible(const Function *Caller, const Function *Callee) const =0
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:42
llvm::TargetTransformInfo::Concept::getShuffleCost
virtual InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args)=0
llvm::TargetTransformInfo::UnrollingPreferences::OptSizeThreshold
unsigned OptSizeThreshold
The cost threshold for the unrolled loop when optimizing for size (set to UINT_MAX to disable).
Definition: TargetTransformInfo.h:438
llvm::TargetTransformInfo::allowsMisalignedMemoryAccesses
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace=0, Align Alignment=Align(1), unsigned *Fast=nullptr) const
Determine if the target supports unaligned memory accesses.
Definition: TargetTransformInfo.cpp:562
llvm::TargetTransformInfo::Concept::getMinVectorRegisterBitWidth
virtual unsigned getMinVectorRegisterBitWidth() const =0
llvm::TargetTransformInfo::getCallInstrCost
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind=TTI::TCK_SizeAndLatency) const
Definition: TargetTransformInfo.cpp:976
llvm::MemIntrinsicInfo::MatchingId
unsigned short MatchingId
Definition: TargetTransformInfo.h:82
llvm::TargetTransformInfo::TCC_Basic
@ TCC_Basic
The cost of a typical 'add' instruction.
Definition: TargetTransformInfo.h:244
llvm::SwitchInst
Multiway switch.
Definition: Instructions.h:3277
llvm::AMDGPU::HSAMD::Kernel::Key::Args
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
Definition: AMDGPUMetadata.h:394
llvm::TargetTransformInfo::Concept::getPreferredAddressingMode
virtual AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const =0
llvm::IntrinsicCostAttributes::isTypeBasedOnly
bool isTypeBasedOnly() const
Definition: TargetTransformInfo.h:158
llvm::TargetTransformInfo::isProfitableToHoist
bool isProfitableToHoist(Instruction *I) const
Return true if it is profitable to hoist instruction in the then/else to before if.
Definition: TargetTransformInfo.cpp:484
llvm::TargetTransformInfo::shouldBuildRelLookupTables
bool shouldBuildRelLookupTables() const
Return true if lookup tables should be turned into relative lookup tables.
Definition: TargetTransformInfo.cpp:507
llvm::TargetTransformInfo::Concept::getMaxInterleaveFactor
virtual unsigned getMaxInterleaveFactor(unsigned VF)=0
llvm::TargetTransformInfo::Concept::getStoreVectorFactor
virtual unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const =0
llvm::BranchInst
Conditional or Unconditional Branch instruction.
Definition: Instructions.h:3133
llvm::TargetTransformInfo::Concept::getLoadStoreVecRegBitWidth
virtual unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const =0
llvm::TargetTransformInfo::Concept::getRegUsageForType
virtual unsigned getRegUsageForType(Type *Ty)=0
llvm::TargetTransformInfo::~TargetTransformInfo
~TargetTransformInfo()
llvm::TargetTransformInfo::Concept::getCacheLineSize
virtual unsigned getCacheLineSize() const =0
llvm::AMDGPU::VGPRIndexMode::Id
Id
Definition: SIDefines.h:241
llvm::TargetTransformInfo::OperandValueInfo::isConstant
bool isConstant() const
Definition: TargetTransformInfo.h:927
llvm::TargetTransformInfo::isSingleThreaded
bool isSingleThreaded() const
Definition: TargetTransformInfo.cpp:276
llvm::TargetTransformInfo::Concept::canHaveNonUndefGlobalInitializerInAddressSpace
virtual bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const =0
llvm::TargetTransformInfo::Concept::adjustInliningThreshold
virtual unsigned adjustInliningThreshold(const CallBase *CB)=0
llvm::TargetTransformInfo::Concept::getIntImmCostIntrin
virtual InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TargetCostKind CostKind)=0
llvm::TargetTransformInfo::OK_NonUniformConstantValue
@ OK_NonUniformConstantValue
Definition: TargetTransformInfo.h:910
llvm::TargetTransformInfo::getTgtMemIntrinsic
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
Definition: TargetTransformInfo.cpp:1038
llvm::TargetTransformInfo::getStoreMinimumVF
unsigned getStoreMinimumVF(unsigned VF, Type *ScalarMemTy, Type *ScalarValTy) const
Definition: TargetTransformInfo.cpp:676
llvm::TargetTransformInfo::getRegUsageForType
unsigned getRegUsageForType(Type *Ty) const
Returns the estimated number of registers required to represent Ty.
Definition: TargetTransformInfo.cpp:494
llvm::TargetTransformInfo::Concept::isLegalMaskedCompressStore
virtual bool isLegalMaskedCompressStore(Type *DataType)=0
llvm::TargetTransformInfo::useAA
bool useAA() const
Definition: TargetTransformInfo.cpp:488
llvm::TargetTransformInfo::Concept::getInliningThresholdMultiplier
virtual unsigned getInliningThresholdMultiplier()=0
llvm::HardwareLoopInfo::CountType
IntegerType * CountType
Definition: TargetTransformInfo.h:103
llvm::TargetTransformInfo::enableWritePrefetching
bool enableWritePrefetching() const
Definition: TargetTransformInfo.cpp:717
llvm::TargetTransformInfo::getFPOpCost
InstructionCost getFPOpCost(Type *Ty) const
Return the expected cost of supporting the floating point operation of the specified type.
Definition: TargetTransformInfo.cpp:589
llvm::PredicationStyle::None
@ None
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::TargetTransformInfo::TCK_RecipThroughput
@ TCK_RecipThroughput
Reciprocal throughput.
Definition: TargetTransformInfo.h:218
llvm::IntrinsicCostAttributes::getArgs
const SmallVectorImpl< const Value * > & getArgs() const
Definition: TargetTransformInfo.h:155
llvm::TargetTransformInfo::Concept::shouldPrefetchAddressSpace
virtual bool shouldPrefetchAddressSpace(unsigned AS) const =0
llvm::TargetTransformInfo::AMK_None
@ AMK_None
Definition: TargetTransformInfo.h:635
llvm::TargetTransformInfo::SK_ExtractSubvector
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
Definition: TargetTransformInfo.h:894
llvm::TargetTransformInfo::AMK_PreIndexed
@ AMK_PreIndexed
Definition: TargetTransformInfo.h:633
llvm::AtomicOrdering::NotAtomic
@ NotAtomic
llvm::Data
@ Data
llvm::TargetTransformInfo::Concept::isLegalToVectorizeStore
virtual bool isLegalToVectorizeStore(StoreInst *SI) const =0
llvm::TargetTransformInfo::getVPMemoryOpCost
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind=TTI::TCK_RecipThroughput, const Instruction *I=nullptr) const
llvm::TargetTransformInfo::isAlwaysUniform
bool isAlwaysUniform(const Value *V) const
Definition: TargetTransformInfo.cpp:249
llvm::TargetTransformInfo::Concept::getMemcpyCost
virtual InstructionCost getMemcpyCost(const Instruction *I)=0
llvm::TargetTransformInfo::isLegalAddressingMode
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace=0, Instruction *I=nullptr) const
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
Definition: TargetTransformInfo.cpp:353
llvm::TargetTransformInfo::getMemcpyCost
InstructionCost getMemcpyCost(const Instruction *I) const
Definition: TargetTransformInfo.cpp:996
llvm::TargetTransformInfo::Concept::simplifyDemandedUseBitsIntrinsic
virtual Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed)=0
llvm::TargetTransformInfo::UnrollingPreferences::MaxPercentThresholdBoost
unsigned MaxPercentThresholdBoost
If complete unrolling will reduce the cost of the loop, we will boost the Threshold by a certain perc...
Definition: TargetTransformInfo.h:435
llvm::TargetTransformInfo::Concept::getVectorInstrCost
virtual InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)=0
llvm::TargetTransformInfo::Concept::forceScalarizeMaskedScatter
virtual bool forceScalarizeMaskedScatter(VectorType *DataType, Align Alignment)=0
llvm::TargetTransformInfo::Concept::getUnrollingPreferences
virtual void getUnrollingPreferences(Loop *L, ScalarEvolution &, UnrollingPreferences &UP, OptimizationRemarkEmitter *ORE)=0
llvm::MemIntrinsicInfo::IsVolatile
bool IsVolatile
Definition: TargetTransformInfo.h:86
llvm::TargetTransformInfo::Concept::getMinPrefetchStride
virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const =0
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38