LLVM 19.0.0git
AMDGPULowerKernelArguments.cpp
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1//===-- AMDGPULowerKernelArguments.cpp ------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This pass replaces accesses to kernel arguments with loads from
10/// offsets from the kernarg base pointer.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPU.h"
15#include "GCNSubtarget.h"
17#include "llvm/IR/IRBuilder.h"
18#include "llvm/IR/IntrinsicsAMDGPU.h"
19#include "llvm/IR/MDBuilder.h"
21
22#define DEBUG_TYPE "amdgpu-lower-kernel-arguments"
23
24using namespace llvm;
25
26namespace {
27
28class PreloadKernelArgInfo {
29private:
30 Function &F;
31 const GCNSubtarget &ST;
32 unsigned NumFreeUserSGPRs;
33
34public:
35 SmallVector<llvm::Metadata *, 8> KernelArgMetadata;
36
37 PreloadKernelArgInfo(Function &F, const GCNSubtarget &ST) : F(F), ST(ST) {
38 setInitialFreeUserSGPRsCount();
39 }
40
41 // Returns the maximum number of user SGPRs that we have available to preload
42 // arguments.
43 void setInitialFreeUserSGPRsCount() {
44 const unsigned MaxUserSGPRs = ST.getMaxNumUserSGPRs();
45 GCNUserSGPRUsageInfo UserSGPRInfo(F, ST);
46
47 NumFreeUserSGPRs = MaxUserSGPRs - UserSGPRInfo.getNumUsedUserSGPRs();
48 }
49
50 bool tryAllocPreloadSGPRs(unsigned AllocSize, uint64_t ArgOffset,
51 uint64_t LastExplicitArgOffset) {
52 // Check if this argument may be loaded into the same register as the
53 // previous argument.
54 if (!isAligned(Align(4), ArgOffset) && AllocSize < 4)
55 return true;
56
57 // Pad SGPRs for kernarg alignment.
58 unsigned Padding = ArgOffset - LastExplicitArgOffset;
59 unsigned PaddingSGPRs = alignTo(Padding, 4) / 4;
60 unsigned NumPreloadSGPRs = alignTo(AllocSize, 4) / 4;
61 if (NumPreloadSGPRs + PaddingSGPRs > NumFreeUserSGPRs)
62 return false;
63
64 NumFreeUserSGPRs -= (NumPreloadSGPRs + PaddingSGPRs);
65 return true;
66 }
67};
68
69class AMDGPULowerKernelArguments : public FunctionPass {
70public:
71 static char ID;
72
73 AMDGPULowerKernelArguments() : FunctionPass(ID) {}
74
75 bool runOnFunction(Function &F) override;
76
77 void getAnalysisUsage(AnalysisUsage &AU) const override {
79 AU.setPreservesAll();
80 }
81};
82
83} // end anonymous namespace
84
85// skip allocas
88 for (BasicBlock::iterator E = BB.end(); InsPt != E; ++InsPt) {
89 AllocaInst *AI = dyn_cast<AllocaInst>(&*InsPt);
90
91 // If this is a dynamic alloca, the value may depend on the loaded kernargs,
92 // so loads will need to be inserted before it.
93 if (!AI || !AI->isStaticAlloca())
94 break;
95 }
96
97 return InsPt;
98}
99
101 CallingConv::ID CC = F.getCallingConv();
102 if (CC != CallingConv::AMDGPU_KERNEL || F.arg_empty())
103 return false;
104
105 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
106 LLVMContext &Ctx = F.getParent()->getContext();
107 const DataLayout &DL = F.getParent()->getDataLayout();
108 BasicBlock &EntryBlock = *F.begin();
109 IRBuilder<> Builder(&EntryBlock, getInsertPt(EntryBlock));
110
111 const Align KernArgBaseAlign(16); // FIXME: Increase if necessary
112 const uint64_t BaseOffset = ST.getExplicitKernelArgOffset();
113
114 Align MaxAlign;
115 // FIXME: Alignment is broken with explicit arg offset.;
116 const uint64_t TotalKernArgSize = ST.getKernArgSegmentSize(F, MaxAlign);
117 if (TotalKernArgSize == 0)
118 return false;
119
120 CallInst *KernArgSegment =
121 Builder.CreateIntrinsic(Intrinsic::amdgcn_kernarg_segment_ptr, {}, {},
122 nullptr, F.getName() + ".kernarg.segment");
123 KernArgSegment->addRetAttr(Attribute::NonNull);
124 KernArgSegment->addRetAttr(
125 Attribute::getWithDereferenceableBytes(Ctx, TotalKernArgSize));
126
127 uint64_t ExplicitArgOffset = 0;
128 // Preloaded kernel arguments must be sequential.
129 bool InPreloadSequence = true;
130 PreloadKernelArgInfo PreloadInfo(F, ST);
131
132 for (Argument &Arg : F.args()) {
133 const bool IsByRef = Arg.hasByRefAttr();
134 Type *ArgTy = IsByRef ? Arg.getParamByRefType() : Arg.getType();
135 MaybeAlign ParamAlign = IsByRef ? Arg.getParamAlign() : std::nullopt;
136 Align ABITypeAlign = DL.getValueOrABITypeAlignment(ParamAlign, ArgTy);
137
138 uint64_t Size = DL.getTypeSizeInBits(ArgTy);
139 uint64_t AllocSize = DL.getTypeAllocSize(ArgTy);
140
141 uint64_t EltOffset = alignTo(ExplicitArgOffset, ABITypeAlign) + BaseOffset;
142 uint64_t LastExplicitArgOffset = ExplicitArgOffset;
143 ExplicitArgOffset = alignTo(ExplicitArgOffset, ABITypeAlign) + AllocSize;
144
145 // Try to preload this argument into user SGPRs.
146 if (Arg.hasInRegAttr() && InPreloadSequence && ST.hasKernargPreload() &&
147 !Arg.getType()->isAggregateType())
148 if (PreloadInfo.tryAllocPreloadSGPRs(AllocSize, EltOffset,
149 LastExplicitArgOffset))
150 continue;
151
152 InPreloadSequence = false;
153
154 if (Arg.use_empty())
155 continue;
156
157 // If this is byval, the loads are already explicit in the function. We just
158 // need to rewrite the pointer values.
159 if (IsByRef) {
160 Value *ArgOffsetPtr = Builder.CreateConstInBoundsGEP1_64(
161 Builder.getInt8Ty(), KernArgSegment, EltOffset,
162 Arg.getName() + ".byval.kernarg.offset");
163
164 Value *CastOffsetPtr =
165 Builder.CreateAddrSpaceCast(ArgOffsetPtr, Arg.getType());
166 Arg.replaceAllUsesWith(CastOffsetPtr);
167 continue;
168 }
169
170 if (PointerType *PT = dyn_cast<PointerType>(ArgTy)) {
171 // FIXME: Hack. We rely on AssertZext to be able to fold DS addressing
172 // modes on SI to know the high bits are 0 so pointer adds don't wrap. We
173 // can't represent this with range metadata because it's only allowed for
174 // integer types.
175 if ((PT->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
176 PT->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) &&
177 !ST.hasUsableDSOffset())
178 continue;
179
180 // FIXME: We can replace this with equivalent alias.scope/noalias
181 // metadata, but this appears to be a lot of work.
182 if (Arg.hasNoAliasAttr())
183 continue;
184 }
185
186 auto *VT = dyn_cast<FixedVectorType>(ArgTy);
187 bool IsV3 = VT && VT->getNumElements() == 3;
188 bool DoShiftOpt = Size < 32 && !ArgTy->isAggregateType();
189
190 VectorType *V4Ty = nullptr;
191
192 int64_t AlignDownOffset = alignDown(EltOffset, 4);
193 int64_t OffsetDiff = EltOffset - AlignDownOffset;
194 Align AdjustedAlign = commonAlignment(
195 KernArgBaseAlign, DoShiftOpt ? AlignDownOffset : EltOffset);
196
197 Value *ArgPtr;
198 Type *AdjustedArgTy;
199 if (DoShiftOpt) { // FIXME: Handle aggregate types
200 // Since we don't have sub-dword scalar loads, avoid doing an extload by
201 // loading earlier than the argument address, and extracting the relevant
202 // bits.
203 // TODO: Update this for GFX12 which does have scalar sub-dword loads.
204 //
205 // Additionally widen any sub-dword load to i32 even if suitably aligned,
206 // so that CSE between different argument loads works easily.
207 ArgPtr = Builder.CreateConstInBoundsGEP1_64(
208 Builder.getInt8Ty(), KernArgSegment, AlignDownOffset,
209 Arg.getName() + ".kernarg.offset.align.down");
210 AdjustedArgTy = Builder.getInt32Ty();
211 } else {
212 ArgPtr = Builder.CreateConstInBoundsGEP1_64(
213 Builder.getInt8Ty(), KernArgSegment, EltOffset,
214 Arg.getName() + ".kernarg.offset");
215 AdjustedArgTy = ArgTy;
216 }
217
218 if (IsV3 && Size >= 32) {
219 V4Ty = FixedVectorType::get(VT->getElementType(), 4);
220 // Use the hack that clang uses to avoid SelectionDAG ruining v3 loads
221 AdjustedArgTy = V4Ty;
222 }
223
224 LoadInst *Load =
225 Builder.CreateAlignedLoad(AdjustedArgTy, ArgPtr, AdjustedAlign);
226 Load->setMetadata(LLVMContext::MD_invariant_load, MDNode::get(Ctx, {}));
227
228 MDBuilder MDB(Ctx);
229
230 if (isa<PointerType>(ArgTy)) {
231 if (Arg.hasNonNullAttr())
232 Load->setMetadata(LLVMContext::MD_nonnull, MDNode::get(Ctx, {}));
233
234 uint64_t DerefBytes = Arg.getDereferenceableBytes();
235 if (DerefBytes != 0) {
236 Load->setMetadata(
237 LLVMContext::MD_dereferenceable,
238 MDNode::get(Ctx,
239 MDB.createConstant(
240 ConstantInt::get(Builder.getInt64Ty(), DerefBytes))));
241 }
242
243 uint64_t DerefOrNullBytes = Arg.getDereferenceableOrNullBytes();
244 if (DerefOrNullBytes != 0) {
245 Load->setMetadata(
246 LLVMContext::MD_dereferenceable_or_null,
247 MDNode::get(Ctx,
248 MDB.createConstant(ConstantInt::get(Builder.getInt64Ty(),
249 DerefOrNullBytes))));
250 }
251
252 if (MaybeAlign ParamAlign = Arg.getParamAlign()) {
253 Load->setMetadata(
254 LLVMContext::MD_align,
255 MDNode::get(Ctx, MDB.createConstant(ConstantInt::get(
256 Builder.getInt64Ty(), ParamAlign->value()))));
257 }
258 }
259
260 // TODO: Convert noalias arg to !noalias
261
262 if (DoShiftOpt) {
263 Value *ExtractBits = OffsetDiff == 0 ?
264 Load : Builder.CreateLShr(Load, OffsetDiff * 8);
265
266 IntegerType *ArgIntTy = Builder.getIntNTy(Size);
267 Value *Trunc = Builder.CreateTrunc(ExtractBits, ArgIntTy);
268 Value *NewVal = Builder.CreateBitCast(Trunc, ArgTy,
269 Arg.getName() + ".load");
270 Arg.replaceAllUsesWith(NewVal);
271 } else if (IsV3) {
272 Value *Shuf = Builder.CreateShuffleVector(Load, ArrayRef<int>{0, 1, 2},
273 Arg.getName() + ".load");
274 Arg.replaceAllUsesWith(Shuf);
275 } else {
276 Load->setName(Arg.getName() + ".load");
277 Arg.replaceAllUsesWith(Load);
278 }
279 }
280
281 KernArgSegment->addRetAttr(
282 Attribute::getWithAlignment(Ctx, std::max(KernArgBaseAlign, MaxAlign)));
283
284 return true;
285}
286
287bool AMDGPULowerKernelArguments::runOnFunction(Function &F) {
288 auto &TPC = getAnalysis<TargetPassConfig>();
289 const TargetMachine &TM = TPC.getTM<TargetMachine>();
290 return lowerKernelArguments(F, TM);
291}
292
293INITIALIZE_PASS_BEGIN(AMDGPULowerKernelArguments, DEBUG_TYPE,
294 "AMDGPU Lower Kernel Arguments", false, false)
295INITIALIZE_PASS_END(AMDGPULowerKernelArguments, DEBUG_TYPE, "AMDGPU Lower Kernel Arguments",
297
298char AMDGPULowerKernelArguments::ID = 0;
299
301 return new AMDGPULowerKernelArguments();
302}
303
306 bool Changed = lowerKernelArguments(F, TM);
307 if (Changed) {
308 // TODO: Preserves a lot more.
311 return PA;
312 }
313
314 return PreservedAnalyses::all();
315}
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
AMDGPU Lower Kernel Arguments
static BasicBlock::iterator getInsertPt(BasicBlock &BB)
static bool lowerKernelArguments(Function &F, const TargetMachine &TM)
#define DEBUG_TYPE
uint64_t Size
AMD GCN specific subclass of TargetSubtarget.
#define F(x, y, z)
Definition: MD5.cpp:55
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Target-Independent Code Generator Pass Configuration Options pass.
PreservedAnalyses run(Function &, FunctionAnalysisManager &)
an instruction to allocate memory on the stack
Definition: Instructions.h:60
bool isStaticAlloca() const
Return true if this alloca is in the entry block of the function and is a constant size.
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:321
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesAll()
Set by analyses that do not transform their input at all.
This class represents an incoming formal argument to a Function.
Definition: Argument.h:31
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
static Attribute getWithDereferenceableBytes(LLVMContext &Context, uint64_t Bytes)
Definition: Attributes.cpp:204
static Attribute getWithAlignment(LLVMContext &Context, Align Alignment)
Return a uniquified Attribute object that has the specific alignment set.
Definition: Attributes.cpp:194
LLVM Basic Block Representation.
Definition: BasicBlock.h:60
iterator end()
Definition: BasicBlock.h:443
const_iterator getFirstInsertionPt() const
Returns an iterator to the first instruction in this block that is suitable for inserting a non-PHI i...
Definition: BasicBlock.cpp:409
InstListType::iterator iterator
Instruction iterators...
Definition: BasicBlock.h:165
Represents analyses that only rely on functions' control flow.
Definition: Analysis.h:70
void addRetAttr(Attribute::AttrKind Kind)
Adds the attribute to the return value.
Definition: InstrTypes.h:1869
This class represents a function call, abstracting a target machine's calling convention.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:692
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
virtual bool runOnFunction(Function &F)=0
runOnFunction - Virtual method overriden by subclasses to do the per-function processing of the pass.
unsigned getNumUsedUserSGPRs() const
IntegerType * getIntNTy(unsigned N)
Fetch the type representing an N-bit integer.
Definition: IRBuilder.h:539
LoadInst * CreateAlignedLoad(Type *Ty, Value *Ptr, MaybeAlign Align, const char *Name)
Definition: IRBuilder.h:1807
CallInst * CreateIntrinsic(Intrinsic::ID ID, ArrayRef< Type * > Types, ArrayRef< Value * > Args, Instruction *FMFSource=nullptr, const Twine &Name="")
Create a call to intrinsic ID with Args, mangled using Types.
Definition: IRBuilder.cpp:932
Value * CreateLShr(Value *LHS, Value *RHS, const Twine &Name="", bool isExact=false)
Definition: IRBuilder.h:1437
IntegerType * getInt32Ty()
Fetch the type representing a 32-bit integer.
Definition: IRBuilder.h:526
IntegerType * getInt64Ty()
Fetch the type representing a 64-bit integer.
Definition: IRBuilder.h:531
Value * CreateBitCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:2127
Value * CreateShuffleVector(Value *V1, Value *V2, Value *Mask, const Twine &Name="")
Definition: IRBuilder.h:2494
Value * CreateTrunc(Value *V, Type *DestTy, const Twine &Name="", bool IsNUW=false, bool IsNSW=false)
Definition: IRBuilder.h:2007
Value * CreateConstInBoundsGEP1_64(Type *Ty, Value *Ptr, uint64_t Idx0, const Twine &Name="")
Definition: IRBuilder.h:1935
IntegerType * getInt8Ty()
Fetch the type representing an 8-bit integer.
Definition: IRBuilder.h:516
Value * CreateAddrSpaceCast(Value *V, Type *DestTy, const Twine &Name="")
Definition: IRBuilder.h:2132
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:2666
Class to represent integer types.
Definition: DerivedTypes.h:40
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:185
ConstantAsMetadata * createConstant(Constant *C)
Return the given constant as metadata.
Definition: MDBuilder.cpp:24
static MDTuple * get(LLVMContext &Context, ArrayRef< Metadata * > MDs)
Definition: Metadata.h:1541
virtual void getAnalysisUsage(AnalysisUsage &) const
getAnalysisUsage - This function should be overriden by passes that need analysis information to do t...
Definition: Pass.cpp:98
A set of analyses that are preserved following a run of a transformation pass.
Definition: Analysis.h:109
static PreservedAnalyses all()
Construct a special preserved set that preserves all passes.
Definition: Analysis.h:115
void preserveSet()
Mark an analysis set as preserved.
Definition: Analysis.h:144
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
Target-Independent Code Generator Pass Configuration Options.
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isAggregateType() const
Return true if the type is an aggregate type.
Definition: Type.h:295
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
void replaceAllUsesWith(Value *V)
Change all uses of this to point to a new Value.
Definition: Value.cpp:534
StringRef getName() const
Return a constant reference to the value's name.
Definition: Value.cpp:309
@ REGION_ADDRESS
Address space for region memory. (GDS)
@ LOCAL_ADDRESS
Address space for local memory.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:200
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
Definition: Alignment.h:145
FunctionPass * createAMDGPULowerKernelArgumentsPass()
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
Definition: Alignment.h:212
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:439
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117