#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/IR/PassManager.h"
#include "llvm/Pass.h"
#include "llvm/Support/AMDGPUAddrSpace.h"
#include "llvm/Support/CodeGen.h"

Go to the source code of this file.

Classes
struct	llvm::AMDGPUSimplifyLibCallsPass

struct	llvm::AMDGPUImageIntrinsicOptimizerPass

struct	llvm::AMDGPUUseNativeCallsPass

class	llvm::SILowerI1CopiesPass

struct	llvm::AMDGPUPromoteKernelArgumentsPass

struct	llvm::AMDGPULowerKernelAttributesPass

struct	llvm::AMDGPULowerModuleLDSPass

struct	llvm::AMDGPULowerBufferFatPointersPass

struct	llvm::AMDGPUPromoteAllocaPass

struct	llvm::AMDGPUPromoteAllocaToVectorPass

struct	llvm::AMDGPUAtomicOptimizerPass

struct	llvm::AMDGPUAlwaysInlinePass

struct	llvm::AMDGPUSwLowerLDSPass

class	llvm::AMDGPUCodeGenPreparePass

class	llvm::AMDGPULateCodeGenPreparePass

class	llvm::AMDGPULowerKernelArgumentsPass

struct	llvm::AMDGPUAttributorOptions

class	llvm::AMDGPUAttributorPass

class	llvm::AMDGPUAnnotateUniformValuesPass

struct	llvm::AMDGPUPrintfRuntimeBindingPass

struct	llvm::AMDGPUUnifyMetadataPass

class	llvm::AMDGPURewriteUndefForPHIPass

class	llvm::SIAnnotateControlFlowPass

Namespaces
namespace	llvm
	This is an optimization pass for GlobalISel generic memory operations.

namespace	llvm::AMDGPU

Enumerations
enum class	llvm::ScanOptions { llvm::DPP , llvm::Iterative , llvm::None }

enum	llvm::AMDGPU::TargetIndex { llvm::AMDGPU::TI_CONSTDATA_START , llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0 , llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1 , llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2 , llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3 }

Functions
void	llvm::initializeAMDGPUPreLegalizerCombinerPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPUPreLegalizeCombiner (bool IsOptNone)

void	llvm::initializeAMDGPUPostLegalizerCombinerPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPUPostLegalizeCombiner (bool IsOptNone)

FunctionPass *	llvm::createAMDGPURegBankCombiner (bool IsOptNone)

void	llvm::initializeAMDGPURegBankCombinerPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPUGlobalISelDivergenceLoweringPass ()

FunctionPass *	llvm::createAMDGPURegBankSelectPass ()

FunctionPass *	llvm::createAMDGPURegBankLegalizePass ()

FunctionPass *	llvm::createGCNDPPCombinePass ()

FunctionPass *	llvm::createSIAnnotateControlFlowLegacyPass ()
	Create the annotation pass.

FunctionPass *	llvm::createSIFoldOperandsLegacyPass ()

FunctionPass *	llvm::createSIPeepholeSDWALegacyPass ()

FunctionPass *	llvm::createSILowerI1CopiesLegacyPass ()

FunctionPass *	llvm::createSIShrinkInstructionsLegacyPass ()

FunctionPass *	llvm::createSILoadStoreOptimizerLegacyPass ()

FunctionPass *	llvm::createSIWholeQuadModePass ()

FunctionPass *	llvm::createSIFixControlFlowLiveIntervalsPass ()

FunctionPass *	llvm::createSIOptimizeExecMaskingPreRAPass ()

FunctionPass *	llvm::createSIOptimizeVGPRLiveRangeLegacyPass ()

FunctionPass *	llvm::createSIFixSGPRCopiesLegacyPass ()

FunctionPass *	llvm::createLowerWWMCopiesPass ()

FunctionPass *	llvm::createSIMemoryLegalizerPass ()

FunctionPass *	llvm::createSIInsertWaitcntsPass ()

FunctionPass *	llvm::createSIPreAllocateWWMRegsLegacyPass ()

FunctionPass *	llvm::createSIFormMemoryClausesPass ()

FunctionPass *	llvm::createSIPostRABundlerPass ()

FunctionPass *	llvm::createAMDGPUImageIntrinsicOptimizerPass (const TargetMachine *)

ModulePass *	llvm::createAMDGPURemoveIncompatibleFunctionsPass (const TargetMachine *)

FunctionPass *	llvm::createAMDGPUCodeGenPreparePass ()

FunctionPass *	llvm::createAMDGPULateCodeGenPrepareLegacyPass ()

FunctionPass *	llvm::createAMDGPUReserveWWMRegsPass ()

FunctionPass *	llvm::createAMDGPURewriteOutArgumentsPass ()

ModulePass *	llvm::createAMDGPULowerModuleLDSLegacyPass (const AMDGPUTargetMachine *TM=nullptr)

ModulePass *	llvm::createAMDGPULowerBufferFatPointersPass ()

FunctionPass *	llvm::createSIModeRegisterPass ()

FunctionPass *	llvm::createGCNPreRAOptimizationsPass ()

void	llvm::initializeAMDGPUDAGToDAGISelLegacyPass (PassRegistry &)

void	llvm::initializeAMDGPUAlwaysInlinePass (PassRegistry &)

Pass *	llvm::createAMDGPUAnnotateKernelFeaturesPass ()

Pass *	llvm::createAMDGPUAttributorLegacyPass ()

void	llvm::initializeAMDGPUAttributorLegacyPass (PassRegistry &)

void	llvm::initializeAMDGPUAnnotateKernelFeaturesPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPUAtomicOptimizerPass (ScanOptions ScanStrategy)

void	llvm::initializeAMDGPUAtomicOptimizerPass (PassRegistry &)

ModulePass *	llvm::createAMDGPUCtorDtorLoweringLegacyPass ()

void	llvm::initializeAMDGPUCtorDtorLoweringLegacyPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPULowerKernelArgumentsPass ()

void	llvm::initializeAMDGPULowerKernelArgumentsPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPUPromoteKernelArgumentsPass ()

void	llvm::initializeAMDGPUPromoteKernelArgumentsPass (PassRegistry &)

ModulePass *	llvm::createAMDGPULowerKernelAttributesPass ()

void	llvm::initializeAMDGPULowerKernelAttributesPass (PassRegistry &)

void	llvm::initializeAMDGPULowerModuleLDSLegacyPass (PassRegistry &)

void	llvm::initializeAMDGPULowerBufferFatPointersPass (PassRegistry &)

void	llvm::initializeAMDGPUReserveWWMRegsPass (PassRegistry &)

void	llvm::initializeAMDGPURewriteOutArgumentsPass (PassRegistry &)

void	llvm::initializeGCNDPPCombineLegacyPass (PassRegistry &)

void	llvm::initializeSIFoldOperandsLegacyPass (PassRegistry &)

void	llvm::initializeSIPeepholeSDWALegacyPass (PassRegistry &)

void	llvm::initializeSIShrinkInstructionsLegacyPass (PassRegistry &)

void	llvm::initializeSIFixSGPRCopiesLegacyPass (PassRegistry &)

void	llvm::initializeSIFixVGPRCopiesPass (PassRegistry &)

void	llvm::initializeSILowerWWMCopiesPass (PassRegistry &)

void	llvm::initializeSILowerI1CopiesLegacyPass (PassRegistry &)

void	llvm::initializeAMDGPUGlobalISelDivergenceLoweringPass (PassRegistry &)

void	llvm::initializeAMDGPURegBankSelectPass (PassRegistry &)

void	llvm::initializeAMDGPURegBankLegalizePass (PassRegistry &)

void	llvm::initializeAMDGPUMarkLastScratchLoadPass (PassRegistry &)

void	llvm::initializeSILowerSGPRSpillsLegacyPass (PassRegistry &)

void	llvm::initializeSILoadStoreOptimizerLegacyPass (PassRegistry &)

void	llvm::initializeSIWholeQuadModePass (PassRegistry &)

void	llvm::initializeSILowerControlFlowPass (PassRegistry &)

void	llvm::initializeSIPreEmitPeepholePass (PassRegistry &)

void	llvm::initializeSILateBranchLoweringPass (PassRegistry &)

void	llvm::initializeSIOptimizeExecMaskingPass (PassRegistry &)

void	llvm::initializeSIPreAllocateWWMRegsLegacyPass (PassRegistry &)

void	llvm::initializeAMDGPUImageIntrinsicOptimizerPass (PassRegistry &)

void	llvm::initializeAMDGPUPerfHintAnalysisLegacyPass (PassRegistry &)

void	llvm::initializeGCNRegPressurePrinterPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPUPromoteAlloca ()

void	llvm::initializeAMDGPUPromoteAllocaPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPUPromoteAllocaToVector ()

void	llvm::initializeAMDGPUPromoteAllocaToVectorPass (PassRegistry &)

Pass *	llvm::createAMDGPUStructurizeCFGPass ()

FunctionPass *	llvm::createAMDGPUISelDag (TargetMachine &TM, CodeGenOptLevel OptLevel)
	This pass converts a legalized DAG into a AMDGPU-specific.

ModulePass *	llvm::createAMDGPUAlwaysInlinePass (bool GlobalOpt=true)

void	llvm::initializeAMDGPUSwLowerLDSLegacyPass (PassRegistry &)

ModulePass *	llvm::createAMDGPUSwLowerLDSLegacyPass (const AMDGPUTargetMachine *TM=nullptr)

FunctionPass *	llvm::createAMDGPUAnnotateUniformValuesLegacy ()

ModulePass *	llvm::createAMDGPUPrintfRuntimeBinding ()

void	llvm::initializeAMDGPUPrintfRuntimeBindingPass (PassRegistry &)

void	llvm::initializeAMDGPUResourceUsageAnalysisPass (PassRegistry &)

ModulePass *	llvm::createAMDGPUUnifyMetadataPass ()

void	llvm::initializeAMDGPUUnifyMetadataPass (PassRegistry &)

void	llvm::initializeSIOptimizeExecMaskingPreRAPass (PassRegistry &)

void	llvm::initializeSIOptimizeVGPRLiveRangeLegacyPass (PassRegistry &)

void	llvm::initializeAMDGPUAnnotateUniformValuesLegacyPass (PassRegistry &)

void	llvm::initializeAMDGPUCodeGenPreparePass (PassRegistry &)

void	llvm::initializeAMDGPURemoveIncompatibleFunctionsPass (PassRegistry &)

void	llvm::initializeAMDGPULateCodeGenPrepareLegacyPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPURewriteUndefForPHILegacyPass ()

void	llvm::initializeAMDGPURewriteUndefForPHILegacyPass (PassRegistry &)

void	llvm::initializeSIAnnotateControlFlowLegacyPass (PassRegistry &)

void	llvm::initializeSIMemoryLegalizerPass (PassRegistry &)

void	llvm::initializeSIModeRegisterPass (PassRegistry &)

void	llvm::initializeAMDGPUInsertDelayAluPass (PassRegistry &)

void	llvm::initializeSIInsertHardClausesPass (PassRegistry &)

void	llvm::initializeSIInsertWaitcntsPass (PassRegistry &)

void	llvm::initializeSIFormMemoryClausesPass (PassRegistry &)

void	llvm::initializeSIPostRABundlerPass (PassRegistry &)

void	llvm::initializeGCNCreateVOPDPass (PassRegistry &)

void	llvm::initializeAMDGPUUnifyDivergentExitNodesPass (PassRegistry &)

ImmutablePass *	llvm::createAMDGPUAAWrapperPass ()

void	llvm::initializeAMDGPUAAWrapperPassPass (PassRegistry &)

ImmutablePass *	llvm::createAMDGPUExternalAAWrapperPass ()

void	llvm::initializeAMDGPUExternalAAWrapperPass (PassRegistry &)

void	llvm::initializeAMDGPUArgumentUsageInfoPass (PassRegistry &)

ModulePass *	llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass ()

void	llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass (PassRegistry &)

void	llvm::initializeGCNNSAReassignPass (PassRegistry &)

void	llvm::initializeGCNPreRALongBranchRegPass (PassRegistry &)

void	llvm::initializeGCNPreRAOptimizationsPass (PassRegistry &)

FunctionPass *	llvm::createAMDGPUSetWavePriorityPass ()

void	llvm::initializeAMDGPUSetWavePriorityPass (PassRegistry &)

void	llvm::initializeGCNRewritePartialRegUsesPass (llvm::PassRegistry &)

static bool	llvm::AMDGPU::addrspacesMayAlias (unsigned AS1, unsigned AS2)

Variables
char &	llvm::AMDGPUAnnotateKernelFeaturesID = AMDGPUAnnotateKernelFeatures::ID

char &	llvm::AMDGPUAtomicOptimizerID = AMDGPUAtomicOptimizer::ID

char &	llvm::AMDGPUCtorDtorLoweringLegacyPassID

char &	llvm::AMDGPULowerKernelArgumentsID

char &	llvm::AMDGPUPromoteKernelArgumentsID

char &	llvm::AMDGPULowerKernelAttributesID

char &	llvm::AMDGPULowerModuleLDSLegacyPassID = AMDGPULowerModuleLDSLegacy::ID

char &	llvm::AMDGPULowerBufferFatPointersID = AMDGPULowerBufferFatPointers::ID

char &	llvm::AMDGPUReserveWWMRegsID

char &	llvm::AMDGPURewriteOutArgumentsID

char &	llvm::GCNDPPCombineLegacyID

char &	llvm::SIFoldOperandsLegacyID

char &	llvm::SIPeepholeSDWALegacyID

char &	llvm::SIShrinkInstructionsLegacyID

char &	llvm::SIFixSGPRCopiesLegacyID = SIFixSGPRCopiesLegacy::ID

char &	llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID

char &	llvm::SILowerWWMCopiesID = SILowerWWMCopies::ID

char &	llvm::SILowerI1CopiesLegacyID = SILowerI1CopiesLegacy::ID

char &	llvm::AMDGPUGlobalISelDivergenceLoweringID

char &	llvm::AMDGPURegBankSelectID = AMDGPURegBankSelect::ID

char &	llvm::AMDGPURegBankLegalizeID = AMDGPURegBankLegalize::ID

char &	llvm::AMDGPUMarkLastScratchLoadID = AMDGPUMarkLastScratchLoad::ID

char &	llvm::SILowerSGPRSpillsLegacyID = SILowerSGPRSpillsLegacy::ID

char &	llvm::SILoadStoreOptimizerLegacyID = SILoadStoreOptimizerLegacy::ID

char &	llvm::SIWholeQuadModeID = SIWholeQuadMode::ID

char &	llvm::SILowerControlFlowID = SILowerControlFlow::ID

char &	llvm::SIPreEmitPeepholeID

char &	llvm::SILateBranchLoweringPassID = SILateBranchLowering::ID

char &	llvm::SIOptimizeExecMaskingID = SIOptimizeExecMasking::ID

char &	llvm::SIPreAllocateWWMRegsLegacyID = SIPreAllocateWWMRegsLegacy::ID

char &	llvm::AMDGPUImageIntrinsicOptimizerID

char &	llvm::AMDGPUPerfHintAnalysisLegacyID = AMDGPUPerfHintAnalysisLegacy::ID

char &	llvm::GCNRegPressurePrinterID = GCNRegPressurePrinter::ID

char &	llvm::AMDGPUPromoteAllocaID = AMDGPUPromoteAlloca::ID

char &	llvm::AMDGPUPromoteAllocaToVectorID = AMDGPUPromoteAllocaToVector::ID

char &	llvm::AMDGPUSwLowerLDSLegacyPassID = AMDGPUSwLowerLDSLegacy::ID

char &	llvm::AMDGPUPrintfRuntimeBindingID = AMDGPUPrintfRuntimeBinding::ID

char &	llvm::AMDGPUResourceUsageAnalysisID = AMDGPUResourceUsageAnalysis::ID

char &	llvm::AMDGPUUnifyMetadataID = AMDGPUUnifyMetadata::ID

char &	llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID

char &	llvm::SIOptimizeVGPRLiveRangeLegacyID = SIOptimizeVGPRLiveRangeLegacy::ID

char &	llvm::AMDGPUAnnotateUniformValuesLegacyPassID

char &	llvm::AMDGPUCodeGenPrepareID

char &	llvm::AMDGPURemoveIncompatibleFunctionsID

char &	llvm::AMDGPULateCodeGenPrepareLegacyID

char &	llvm::AMDGPURewriteUndefForPHILegacyPassID

char &	llvm::SIAnnotateControlFlowLegacyPassID

char &	llvm::SIMemoryLegalizerID = SIMemoryLegalizer::ID

char &	llvm::SIModeRegisterID

char &	llvm::AMDGPUInsertDelayAluID = AMDGPUInsertDelayAlu::ID

char &	llvm::SIInsertHardClausesID = SIInsertHardClauses::ID

char &	llvm::SIInsertWaitcntsID = SIInsertWaitcnts::ID

char &	llvm::SIFormMemoryClausesID = SIFormMemoryClauses::ID

char &	llvm::SIPostRABundlerID = SIPostRABundler::ID

char &	llvm::GCNCreateVOPDID = GCNCreateVOPD::ID

char &	llvm::AMDGPUUnifyDivergentExitNodesID = AMDGPUUnifyDivergentExitNodes::ID

char &	llvm::AMDGPUOpenCLEnqueuedBlockLoweringID

char &	llvm::GCNNSAReassignID = GCNNSAReassign::ID

char &	llvm::GCNPreRALongBranchRegID

char &	llvm::GCNPreRAOptimizationsID = GCNPreRAOptimizations::ID

char &	llvm::GCNRewritePartialRegUsesID = GCNRewritePartialRegUses::ID

Classes

Namespaces

Enumerations

Functions

Variables