LLVM  9.0.0svn
Namespaces | Enumerations | Functions | Variables
AMDGPU.h File Reference
#include "llvm/Target/TargetMachine.h"
Include dependency graph for AMDGPU.h:

Go to the source code of this file.

Namespaces

 llvm
 This class represents lattice values for constants.
 
 llvm::AMDGPU
 
 AMDGPUAS
 OpenCL uses address spaces to differentiate between various memory regions on the hardware.
 

Enumerations

enum  llvm::AMDGPU::TargetIndex {
  llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2,
  llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3
}
 
enum  : unsigned {
  AMDGPUAS::MAX_AMDGPU_ADDRESS = 7, AMDGPUAS::FLAT_ADDRESS = 0, AMDGPUAS::GLOBAL_ADDRESS = 1, AMDGPUAS::REGION_ADDRESS = 2,
  AMDGPUAS::CONSTANT_ADDRESS = 4, AMDGPUAS::LOCAL_ADDRESS = 3, AMDGPUAS::PRIVATE_ADDRESS = 5, AMDGPUAS::CONSTANT_ADDRESS_32BIT = 6,
  AMDGPUAS::BUFFER_FAT_POINTER = 7, AMDGPUAS::PARAM_D_ADDRESS = 6, AMDGPUAS::PARAM_I_ADDRESS = 7, AMDGPUAS::CONSTANT_BUFFER_0 = 8,
  AMDGPUAS::CONSTANT_BUFFER_1 = 9, AMDGPUAS::CONSTANT_BUFFER_2 = 10, AMDGPUAS::CONSTANT_BUFFER_3 = 11, AMDGPUAS::CONSTANT_BUFFER_4 = 12,
  AMDGPUAS::CONSTANT_BUFFER_5 = 13, AMDGPUAS::CONSTANT_BUFFER_6 = 14, AMDGPUAS::CONSTANT_BUFFER_7 = 15, AMDGPUAS::CONSTANT_BUFFER_8 = 16,
  AMDGPUAS::CONSTANT_BUFFER_9 = 17, AMDGPUAS::CONSTANT_BUFFER_10 = 18, AMDGPUAS::CONSTANT_BUFFER_11 = 19, AMDGPUAS::CONSTANT_BUFFER_12 = 20,
  AMDGPUAS::CONSTANT_BUFFER_13 = 21, AMDGPUAS::CONSTANT_BUFFER_14 = 22, AMDGPUAS::CONSTANT_BUFFER_15 = 23, AMDGPUAS::UNKNOWN_ADDRESS_SPACE = ~0u
}
 

Functions

FunctionPass * llvm::createR600VectorRegMerger ()
 
FunctionPass * llvm::createR600ExpandSpecialInstrsPass ()
 
FunctionPass * llvm::createR600EmitClauseMarkers ()
 
FunctionPass * llvm::createR600ClauseMergePass ()
 
FunctionPass * llvm::createR600Packetizer ()
 
FunctionPass * llvm::createR600ControlFlowFinalizer ()
 
FunctionPass * llvm::createAMDGPUCFGStructurizerPass ()
 
FunctionPass * llvm::createR600ISelDag (TargetMachine *TM, CodeGenOpt::Level OptLevel)
 This pass converts a legalized DAG into a R600-specific. More...
 
FunctionPass * llvm::createGCNDPPCombinePass ()
 
FunctionPass * llvm::createSIAnnotateControlFlowPass ()
 Create the annotation pass. More...
 
FunctionPass * llvm::createSIFoldOperandsPass ()
 
FunctionPass * llvm::createSIPeepholeSDWAPass ()
 
FunctionPass * llvm::createSILowerI1CopiesPass ()
 
FunctionPass * llvm::createSIFixupVectorISelPass ()
 
FunctionPass * llvm::createSIAddIMGInitPass ()
 
FunctionPass * llvm::createSIShrinkInstructionsPass ()
 
FunctionPass * llvm::createSILoadStoreOptimizerPass ()
 
FunctionPass * llvm::createSIWholeQuadModePass ()
 
FunctionPass * llvm::createSIFixControlFlowLiveIntervalsPass ()
 
FunctionPass * llvm::createSIOptimizeExecMaskingPreRAPass ()
 
FunctionPass * llvm::createSIFixSGPRCopiesPass ()
 
FunctionPass * llvm::createSIMemoryLegalizerPass ()
 
FunctionPass * llvm::createSIInsertWaitcntsPass ()
 
FunctionPass * llvm::createSIPreAllocateWWMRegsPass ()
 
FunctionPass * llvm::createSIFormMemoryClausesPass ()
 
FunctionPass * llvm::createAMDGPUSimplifyLibCallsPass (const TargetOptions &)
 
FunctionPass * llvm::createAMDGPUUseNativeCallsPass ()
 
FunctionPass * llvm::createAMDGPUCodeGenPreparePass ()
 
FunctionPass * llvm::createAMDGPUMachineCFGStructurizerPass ()
 
FunctionPass * llvm::createAMDGPURewriteOutArgumentsPass ()
 
FunctionPass * llvm::createSIModeRegisterPass ()
 
void llvm::initializeAMDGPUDAGToDAGISelPass (PassRegistry &)
 
void llvm::initializeAMDGPUMachineCFGStructurizerPass (PassRegistry &)
 
void llvm::initializeAMDGPUAlwaysInlinePass (PassRegistry &)
 
Pass * llvm::createAMDGPUAnnotateKernelFeaturesPass ()
 
void llvm::initializeAMDGPUAnnotateKernelFeaturesPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUAtomicOptimizerPass ()
 
void llvm::initializeAMDGPUAtomicOptimizerPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPULowerIntrinsicsPass ()
 
void llvm::initializeAMDGPULowerIntrinsicsPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPUFixFunctionBitcastsPass ()
 
void llvm::initializeAMDGPUFixFunctionBitcastsPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPULowerKernelArgumentsPass ()
 
void llvm::initializeAMDGPULowerKernelArgumentsPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPULowerKernelAttributesPass ()
 
void llvm::initializeAMDGPULowerKernelAttributesPass (PassRegistry &)
 
void llvm::initializeAMDGPURewriteOutArgumentsPass (PassRegistry &)
 
void llvm::initializeGCNDPPCombinePass (PassRegistry &)
 
void llvm::initializeR600ClauseMergePassPass (PassRegistry &)
 
void llvm::initializeR600ControlFlowFinalizerPass (PassRegistry &)
 
void llvm::initializeR600ExpandSpecialInstrsPassPass (PassRegistry &)
 
void llvm::initializeR600VectorRegMergerPass (PassRegistry &)
 
void llvm::initializeR600PacketizerPass (PassRegistry &)
 
void llvm::initializeSIFoldOperandsPass (PassRegistry &)
 
void llvm::initializeSIPeepholeSDWAPass (PassRegistry &)
 
void llvm::initializeSIShrinkInstructionsPass (PassRegistry &)
 
void llvm::initializeSIFixSGPRCopiesPass (PassRegistry &)
 
void llvm::initializeSIFixVGPRCopiesPass (PassRegistry &)
 
void llvm::initializeSIFixupVectorISelPass (PassRegistry &)
 
void llvm::initializeSILowerI1CopiesPass (PassRegistry &)
 
void llvm::initializeSILoadStoreOptimizerPass (PassRegistry &)
 
void llvm::initializeSIWholeQuadModePass (PassRegistry &)
 
void llvm::initializeSILowerControlFlowPass (PassRegistry &)
 
void llvm::initializeSIInsertSkipsPass (PassRegistry &)
 
void llvm::initializeSIOptimizeExecMaskingPass (PassRegistry &)
 
void llvm::initializeSIPreAllocateWWMRegsPass (PassRegistry &)
 
void llvm::initializeAMDGPUSimplifyLibCallsPass (PassRegistry &)
 
void llvm::initializeAMDGPUUseNativeCallsPass (PassRegistry &)
 
void llvm::initializeSIAddIMGInitPass (PassRegistry &)
 
void llvm::initializeAMDGPUPerfHintAnalysisPass (PassRegistry &)
 
FunctionPass * llvm::createAMDGPUPromoteAlloca ()
 
void llvm::initializeAMDGPUPromoteAllocaPass (PassRegistry &)
 
Pass * llvm::createAMDGPUStructurizeCFGPass ()
 
FunctionPass * llvm::createAMDGPUISelDag (TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
 This pass converts a legalized DAG into a AMDGPU-specific. More...
 
ModulePass * llvm::createAMDGPUAlwaysInlinePass (bool GlobalOpt=true)
 
ModulePass * llvm::createR600OpenCLImageTypeLoweringPass ()
 
FunctionPass * llvm::createAMDGPUAnnotateUniformValues ()
 
ModulePass * llvm::createAMDGPUUnifyMetadataPass ()
 
void llvm::initializeAMDGPUUnifyMetadataPass (PassRegistry &)
 
void llvm::initializeSIOptimizeExecMaskingPreRAPass (PassRegistry &)
 
void llvm::initializeAMDGPUAnnotateUniformValuesPass (PassRegistry &)
 
void llvm::initializeAMDGPUCodeGenPreparePass (PassRegistry &)
 
void llvm::initializeSIAnnotateControlFlowPass (PassRegistry &)
 
void llvm::initializeSIMemoryLegalizerPass (PassRegistry &)
 
void llvm::initializeSIModeRegisterPass (PassRegistry &)
 
void llvm::initializeSIInsertWaitcntsPass (PassRegistry &)
 
void llvm::initializeSIFormMemoryClausesPass (PassRegistry &)
 
void llvm::initializeAMDGPUUnifyDivergentExitNodesPass (PassRegistry &)
 
ImmutablePass * llvm::createAMDGPUAAWrapperPass ()
 
void llvm::initializeAMDGPUAAWrapperPassPass (PassRegistry &)
 
ImmutablePass * llvm::createAMDGPUExternalAAWrapperPass ()
 
void llvm::initializeAMDGPUExternalAAWrapperPass (PassRegistry &)
 
void llvm::initializeAMDGPUArgumentUsageInfoPass (PassRegistry &)
 
Pass * llvm::createAMDGPUFunctionInliningPass ()
 
void llvm::initializeAMDGPUInlinerPass (PassRegistry &)
 
ModulePass * llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass ()
 
void llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass (PassRegistry &)
 
void llvm::initializeGCNRegBankReassignPass (PassRegistry &)
 
void llvm::initializeGCNNSAReassignPass (PassRegistry &)
 

Variables

char & llvm::AMDGPUMachineCFGStructurizerID
 
char & llvm::AMDGPUAnnotateKernelFeaturesID = AMDGPUAnnotateKernelFeatures::ID
 
char & llvm::AMDGPUAtomicOptimizerID = AMDGPUAtomicOptimizer::ID
 
char & llvm::AMDGPULowerIntrinsicsID = AMDGPULowerIntrinsics::ID
 
char & llvm::AMDGPUFixFunctionBitcastsID = AMDGPUFixFunctionBitcasts::ID
 
char & llvm::AMDGPULowerKernelArgumentsID
 
char & llvm::AMDGPULowerKernelAttributesID
 
char & llvm::AMDGPURewriteOutArgumentsID
 
char & llvm::GCNDPPCombineID = GCNDPPCombine::ID
 
char & llvm::R600ClauseMergePassID = R600ClauseMergePass::ID
 
char & llvm::R600ControlFlowFinalizerID = R600ControlFlowFinalizer::ID
 
char & llvm::R600ExpandSpecialInstrsPassID = R600ExpandSpecialInstrsPass::ID
 
char & llvm::R600VectorRegMergerID = R600VectorRegMerger::ID
 
char & llvm::R600PacketizerID = R600Packetizer::ID
 
char & llvm::SIFoldOperandsID
 
char & llvm::SIPeepholeSDWAID = SIPeepholeSDWA::ID
 
char & llvm::SIShrinkInstructionsID
 
char & llvm::SIFixSGPRCopiesID = SIFixSGPRCopies::ID
 
char & llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID
 
char & llvm::SIFixupVectorISelID
 
char & llvm::SILowerI1CopiesID = SILowerI1Copies::ID
 
char & llvm::SILoadStoreOptimizerID = SILoadStoreOptimizer::ID
 
char & llvm::SIWholeQuadModeID = SIWholeQuadMode::ID
 
char & llvm::SILowerControlFlowID = SILowerControlFlow::ID
 
char & llvm::SIInsertSkipsPassID
 
char & llvm::SIOptimizeExecMaskingID = SIOptimizeExecMasking::ID
 
char & llvm::SIPreAllocateWWMRegsID = SIPreAllocateWWMRegs::ID
 
char & llvm::AMDGPUSimplifyLibCallsID
 
char & llvm::AMDGPUUseNativeCallsID
 
char & llvm::SIAddIMGInitID = SIAddIMGInit::ID
 
char & llvm::AMDGPUPerfHintAnalysisID = AMDGPUPerfHintAnalysis::ID
 
char & llvm::AMDGPUPromoteAllocaID
 
char & llvm::AMDGPUUnifyMetadataID = AMDGPUUnifyMetadata::ID
 
char & llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID
 
char & llvm::AMDGPUAnnotateUniformValuesPassID
 
char & llvm::AMDGPUCodeGenPrepareID
 
char & llvm::SIAnnotateControlFlowPassID
 
char & llvm::SIMemoryLegalizerID = SIMemoryLegalizer::ID
 
char & llvm::SIModeRegisterID
 
char & llvm::SIInsertWaitcntsID = SIInsertWaitcnts::ID
 
char & llvm::SIFormMemoryClausesID = SIFormMemoryClauses::ID
 
char & llvm::AMDGPUUnifyDivergentExitNodesID = AMDGPUUnifyDivergentExitNodes::ID
 
char & llvm::AMDGPUOpenCLEnqueuedBlockLoweringID
 
char & llvm::GCNRegBankReassignID = GCNRegBankReassign::ID
 
char & llvm::GCNNSAReassignID = GCNNSAReassign::ID
 
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