LLVM 18.0.0git
AMDGPU.h
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1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
13#include "llvm/IR/PassManager.h"
14#include "llvm/Pass.h"
16
17namespace llvm {
18
19class AMDGPUTargetMachine;
20class TargetMachine;
21
22// GlobalISel passes
29
31
32// SI Passes
50
61
62struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
65};
66
67struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
69};
70
72
75
77
83
84// DPP/Iterative option enables the atomic optimizer with given strategy
85// whereas None disables the atomic optimizer.
86enum class ScanOptions { DPP, Iterative, None };
87FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
89extern char &AMDGPUAtomicOptimizerID;
90
94
98
102
104 : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
106};
107
111
113 : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
115};
116
119
120struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
123
125};
126
128extern char &AMDGPURewriteOutArgumentsID;
129
131extern char &GCNDPPCombineID;
132
134extern char &SIFoldOperandsID;
135
137extern char &SIPeepholeSDWAID;
138
140extern char &SIShrinkInstructionsID;
141
143extern char &SIFixSGPRCopiesID;
144
146extern char &SIFixVGPRCopiesID;
147
149extern char &SILowerWWMCopiesID;
150
152extern char &SILowerI1CopiesID;
153
155extern char &SILowerSGPRSpillsID;
156
158extern char &SILoadStoreOptimizerID;
159
161extern char &SIWholeQuadModeID;
162
164extern char &SILowerControlFlowID;
165
167extern char &SIPreEmitPeepholeID;
168
170extern char &SILateBranchLoweringPassID;
171
173extern char &SIOptimizeExecMaskingID;
174
176extern char &SIPreAllocateWWMRegsID;
177
179extern char &AMDGPUPerfHintAnalysisID;
180
181// Passes common to R600 and SI
184extern char &AMDGPUPromoteAllocaID;
185
189
190struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
193
194private:
195 TargetMachine &TM;
196};
197
199 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
202
203private:
204 TargetMachine &TM;
205};
206
207struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
209 : TM(TM), ScanImpl(ScanImpl) {}
211
212private:
213 TargetMachine &TM;
214 ScanOptions ScanImpl;
215};
216
219ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
220
221struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
222 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
224
225private:
226 bool GlobalOpt;
227};
228
230 : public PassInfoMixin<AMDGPUCodeGenPreparePass> {
231private:
232 TargetMachine &TM;
233
234public:
237};
238
240 : public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
241private:
242 TargetMachine &TM;
243
244public:
247};
248
250
254
257
259 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
261};
262
265extern char &AMDGPUUnifyMetadataID;
266
267struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
269};
270
273
275extern char &SIOptimizeVGPRLiveRangeID;
276
279
281extern char &AMDGPUCodeGenPrepareID;
282
285
287extern char &AMDGPULateCodeGenPrepareID;
288
292
294 : public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
295public:
298};
299
301extern char &SIAnnotateControlFlowPassID;
302
304extern char &SIMemoryLegalizerID;
305
307extern char &SIModeRegisterID;
308
310extern char &AMDGPUInsertDelayAluID;
311
313extern char &SIInsertHardClausesID;
314
316extern char &SIInsertWaitcntsID;
317
319extern char &SIFormMemoryClausesID;
320
322extern char &SIPostRABundlerID;
323
325extern char &GCNCreateVOPDID;
326
329
334
336
340
342extern char &GCNNSAReassignID;
343
345extern char &GCNPreRALongBranchRegID;
346
348extern char &GCNPreRAOptimizationsID;
349
352
354extern char &GCNRewritePartialRegUsesID;
355
356namespace AMDGPU {
364}
365
366/// OpenCL uses address spaces to differentiate between
367/// various memory regions on the hardware. On the CPU
368/// all of the address spaces point to the same memory,
369/// however on the GPU, each address space points to
370/// a separate piece of memory that is unique from other
371/// memory locations.
372namespace AMDGPUAS {
373enum : unsigned {
374 // The maximum value for flat, generic, local, private, constant and region.
376
377 FLAT_ADDRESS = 0, ///< Address space for flat memory.
378 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
379 REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
380
381 CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
382 LOCAL_ADDRESS = 3, ///< Address space for local memory.
383 PRIVATE_ADDRESS = 5, ///< Address space for private memory.
384
385 CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
386
387 BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
388 ///< Not used in backend.
389
390 BUFFER_RESOURCE = 8, ///< Address space for 128-bit buffer resources.
391
392 /// Internal address spaces. Can be freely renumbered.
393 STREAMOUT_REGISTER = 128, ///< Address space for GS NGG Streamout registers.
394 /// end Internal address spaces.
395
396 /// Address space for direct addressable parameter memory (CONST0).
398 /// Address space for indirect addressable parameter memory (VTX1).
400
401 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
402 // this order to be able to dynamically index a constant buffer, for
403 // example:
404 //
405 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
406
423
424 // Some places use this if the address space can't be determined.
426};
427}
428
429namespace AMDGPU {
430
431// FIXME: Missing constant_32bit
432inline bool isFlatGlobalAddrSpace(unsigned AS) {
433 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
437}
438
439inline bool isExtendedGlobalAddrSpace(unsigned AS) {
443}
444
445static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
446 static_assert(AMDGPUAS::MAX_AMDGPU_ADDRESS <= 8, "Addr space out of range");
447
449 return true;
450
451 // This array is indexed by address space value enum elements 0 ... to 8
452 // clang-format off
453 static const bool ASAliasRules[9][9] = {
454 /* Flat Global Region Group Constant Private Const32 BufFatPtr BufRsrc */
455 /* Flat */ {true, true, false, true, true, true, true, true, true},
456 /* Global */ {true, true, false, false, true, false, true, true, true},
457 /* Region */ {false, false, true, false, false, false, false, false, false},
458 /* Group */ {true, false, false, true, false, false, false, false, false},
459 /* Constant */ {true, true, false, false, false, false, true, true, true},
460 /* Private */ {true, false, false, false, false, true, false, false, false},
461 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true},
462 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true},
463 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true},
464 };
465 // clang-format on
466
467 return ASAliasRules[AS1][AS2];
468}
469
470}
471
472} // End namespace llvm
473
474#endif
#define F(x, y, z)
Definition: MD5.cpp:55
const char LLVMTargetMachineRef TM
This header defines various interfaces for pass management in LLVM.
PreservedAnalyses run(Function &, FunctionAnalysisManager &)
AMDGPUCodeGenPreparePass(TargetMachine &TM)
Definition: AMDGPU.h:235
AMDGPULowerKernelArgumentsPass(TargetMachine &TM)
Definition: AMDGPU.h:245
PreservedAnalyses run(Function &, FunctionAnalysisManager &)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:620
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:282
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:251
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:152
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:78
@ CONSTANT_BUFFER_5
Definition: AMDGPU.h:412
@ CONSTANT_BUFFER_15
Definition: AMDGPU.h:422
@ MAX_AMDGPU_ADDRESS
Definition: AMDGPU.h:375
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:385
@ CONSTANT_BUFFER_11
Definition: AMDGPU.h:418
@ CONSTANT_BUFFER_6
Definition: AMDGPU.h:413
@ CONSTANT_BUFFER_12
Definition: AMDGPU.h:419
@ PARAM_D_ADDRESS
end Internal address spaces.
Definition: AMDGPU.h:397
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:379
@ CONSTANT_BUFFER_2
Definition: AMDGPU.h:409
@ CONSTANT_BUFFER_1
Definition: AMDGPU.h:408
@ CONSTANT_BUFFER_0
Definition: AMDGPU.h:407
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:382
@ STREAMOUT_REGISTER
Internal address spaces. Can be freely renumbered.
Definition: AMDGPU.h:393
@ CONSTANT_BUFFER_8
Definition: AMDGPU.h:415
@ CONSTANT_BUFFER_4
Definition: AMDGPU.h:411
@ CONSTANT_BUFFER_3
Definition: AMDGPU.h:410
@ CONSTANT_BUFFER_10
Definition: AMDGPU.h:417
@ PARAM_I_ADDRESS
Address space for indirect addressable parameter memory (VTX1).
Definition: AMDGPU.h:399
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:381
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:425
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:377
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:378
@ CONSTANT_BUFFER_14
Definition: AMDGPU.h:421
@ CONSTANT_BUFFER_9
Definition: AMDGPU.h:416
@ CONSTANT_BUFFER_7
Definition: AMDGPU.h:414
@ CONSTANT_BUFFER_13
Definition: AMDGPU.h:420
@ BUFFER_FAT_POINTER
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:387
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:383
@ BUFFER_RESOURCE
Address space for 128-bit buffer resources.
Definition: AMDGPU.h:390
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:432
static bool addrspacesMayAlias(unsigned AS1, unsigned AS2)
Definition: AMDGPU.h:445
@ TI_SCRATCH_RSRC_DWORD1
Definition: AMDGPU.h:360
@ TI_SCRATCH_RSRC_DWORD3
Definition: AMDGPU.h:362
@ TI_SCRATCH_RSRC_DWORD0
Definition: AMDGPU.h:359
@ TI_SCRATCH_RSRC_DWORD2
Definition: AMDGPU.h:361
@ TI_CONSTDATA_START
Definition: AMDGPU.h:358
bool isExtendedGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:439
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeSIFormMemoryClausesPass(PassRegistry &)
char & SIPreAllocateWWMRegsID
ScanOptions
Definition: AMDGPU.h:86
ImmutablePass * createAMDGPUAAWrapperPass()
FunctionPass * createSIPreAllocateWWMRegsPass()
FunctionPass * createAMDGPUSetWavePriorityPass()
char & AMDGPUCtorDtorLoweringLegacyPassID
void initializeGCNCreateVOPDPass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
char & AMDGPUAnnotateKernelFeaturesID
char & GCNPreRAOptimizationsID
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
void initializeGCNRewritePartialRegUsesPass(llvm::PassRegistry &)
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
char & SIMemoryLegalizerID
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
char & SIPostRABundlerID
FunctionPass * createSIModeRegisterPass()
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeSIModeRegisterPass(PassRegistry &)
ModulePass * createAMDGPUCtorDtorLoweringLegacyPass()
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &)
char & AMDGPUPromoteKernelArgumentsID
void initializeAMDGPUAttributorPass(PassRegistry &)
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
char & GCNRewritePartialRegUsesID
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
void initializeSIShrinkInstructionsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
void initializeGCNPreRALongBranchRegPass(PassRegistry &)
char & SILowerI1CopiesID
char & AMDGPUResourceUsageAnalysisID
char & SILoadStoreOptimizerID
FunctionPass * createSIWholeQuadModePass()
ModulePass * createAMDGPULowerKernelAttributesPass()
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
FunctionPass * createSIPeepholeSDWAPass()
void initializeSIPreEmitPeepholePass(PassRegistry &)
FunctionPass * createSILoadStoreOptimizerPass()
char & SILowerWWMCopiesID
void initializeSIFixVGPRCopiesPass(PassRegistry &)
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
void initializeAMDGPURemoveIncompatibleFunctionsPass(PassRegistry &)
void initializeSILowerWWMCopiesPass(PassRegistry &)
void initializeGCNNSAReassignPass(PassRegistry &)
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & SIFormMemoryClausesID
char & AMDGPURemoveIncompatibleFunctionsID
void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &)
void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &)
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
void initializeSILoadStoreOptimizerPass(PassRegistry &)
void initializeSILateBranchLoweringPass(PassRegistry &)
void initializeSIPeepholeSDWAPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAllocaToVector()
char & AMDGPULateCodeGenPrepareID
char & AMDGPUUnifyDivergentExitNodesID
char & SIInsertWaitcntsID
FunctionPass * createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy)
char & AMDGPUPrintfRuntimeBindingID
char & GCNNSAReassignID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
char & AMDGPUPerfHintAnalysisID
char & SILowerSGPRSpillsID
char & SILateBranchLoweringPassID
char & SIModeRegisterID
FunctionPass * createGCNPreRAOptimizationsPass()
FunctionPass * createSIShrinkInstructionsPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
void initializeSIPostRABundlerPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
void initializeSIWholeQuadModePass(PassRegistry &)
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUInsertDelayAluID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
char & SIOptimizeVGPRLiveRangeID
char & SIOptimizeExecMaskingPreRAID
char & AMDGPULowerModuleLDSLegacyPassID
void initializeSIInsertHardClausesPass(PassRegistry &)
FunctionPass * createSIPostRABundlerPass()
FunctionPass * createSIFormMemoryClausesPass()
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
Pass * createAMDGPUStructurizeCFGPass()
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
void initializeSIAnnotateControlFlowPass(PassRegistry &)
ModulePass * createAMDGPUPrintfRuntimeBinding()
void initializeSIMemoryLegalizerPass(PassRegistry &)
char & AMDGPUUnifyMetadataID
FunctionPass * createAMDGPUAnnotateUniformValues()
ModulePass * createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM=nullptr)
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAlloca()
char & SIPreEmitPeepholeID
ModulePass * createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *)
FunctionPass * createSILowerI1CopiesPass()
char & AMDGPURewriteOutArgumentsID
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
FunctionPass * createAMDGPUCodeGenPreparePass()
FunctionPass * createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a AMDGPU-specific.
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
char & AMDGPUMachineCFGStructurizerID
char & AMDGPULowerKernelAttributesID
@ None
Not a recurrence.
char & GCNDPPCombineID
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
char & AMDGPUPromoteAllocaID
FunctionPass * createSIFoldOperandsPass()
char & SIWholeQuadModeID
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
ImmutablePass * createAMDGPUExternalAAWrapperPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
FunctionPass * createAMDGPURewriteUndefForPHILegacyPass()
void initializeSILowerSGPRSpillsPass(PassRegistry &)
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
char & SIInsertHardClausesID
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
char & GCNCreateVOPDID
Pass * createAMDGPUAttributorPass()
void initializeSILowerI1CopiesPass(PassRegistry &)
char & SILowerControlFlowID
char & AMDGPUAtomicOptimizerID
char & SIAnnotateControlFlowPassID
FunctionPass * createLowerWWMCopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
char & AMDGPUAnnotateUniformValuesPassID
FunctionPass * createSIMemoryLegalizerPass()
void initializeSIFoldOperandsPass(PassRegistry &)
void initializeSILowerControlFlowPass(PassRegistry &)
char & SIPeepholeSDWAID
char & AMDGPUOpenCLEnqueuedBlockLoweringID
char & SIFixVGPRCopiesID
void initializeAMDGPURegBankSelectPass(PassRegistry &)
char & AMDGPURewriteUndefForPHILegacyPassID
FunctionPass * createSIOptimizeVGPRLiveRangePass()
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
FunctionPass * createSIInsertWaitcntsPass()
void initializeGCNDPPCombinePass(PassRegistry &)
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
FunctionPass * createGCNDPPCombinePass()
FunctionPass * createAMDGPULateCodeGenPreparePass()
FunctionPass * createSIFixSGPRCopiesPass()
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
char & AMDGPUPromoteAllocaToVectorID
void initializeAMDGPUInsertDelayAluPass(PassRegistry &)
char & SIOptimizeExecMaskingID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
char & SIFixSGPRCopiesID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
char & AMDGPULowerKernelArgumentsID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
char & AMDGPUCodeGenPrepareID
void initializeAMDGPUSetWavePriorityPass(PassRegistry &)
char & SIShrinkInstructionsID
FunctionPass * createAMDGPUPromoteKernelArgumentsPass()
char & GCNPreRALongBranchRegID
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
AMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPU.h:222
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
Definition: AMDGPU.h:208
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_)
Definition: AMDGPU.h:122
const AMDGPUTargetMachine & TM
Definition: AMDGPU.h:121
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPUPromoteAllocaPass(TargetMachine &TM)
Definition: AMDGPU.h:191
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM)
Definition: AMDGPU.h:200
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
A CRTP mix-in to automatically provide informational APIs needed for passes.
Definition: PassManager.h:371