LLVM  14.0.0git
AMDGPU.h
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1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
13 #include "llvm/IR/PassManager.h"
14 #include "llvm/Support/CodeGen.h"
15 
16 namespace llvm {
17 
18 class TargetMachine;
19 
20 // GlobalISel passes
21 void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &);
22 FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone);
24 FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone);
25 FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone);
26 void initializeAMDGPURegBankCombinerPass(PassRegistry &);
27 
28 // SI Passes
29 FunctionPass *createGCNDPPCombinePass();
30 FunctionPass *createSIAnnotateControlFlowPass();
31 FunctionPass *createSIFoldOperandsPass();
32 FunctionPass *createSIPeepholeSDWAPass();
33 FunctionPass *createSILowerI1CopiesPass();
34 FunctionPass *createSIShrinkInstructionsPass();
35 FunctionPass *createSILoadStoreOptimizerPass();
36 FunctionPass *createSIWholeQuadModePass();
39 FunctionPass *createSIOptimizeVGPRLiveRangePass();
40 FunctionPass *createSIFixSGPRCopiesPass();
41 FunctionPass *createSIMemoryLegalizerPass();
42 FunctionPass *createSIInsertWaitcntsPass();
43 FunctionPass *createSIPreAllocateWWMRegsPass();
44 FunctionPass *createSIFormMemoryClausesPass();
45 
46 FunctionPass *createSIPostRABundlerPass();
47 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetMachine *);
48 FunctionPass *createAMDGPUUseNativeCallsPass();
49 FunctionPass *createAMDGPUCodeGenPreparePass();
52 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
53 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
56 ModulePass *createAMDGPULowerModuleLDSPass();
57 FunctionPass *createSIModeRegisterPass();
58 FunctionPass *createGCNPreRAOptimizationsPass();
59 
60 struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
63 
64 private:
65  TargetMachine &TM;
66 };
67 
68 struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
70 };
71 
73 
76 
78 
84 
87 extern char &AMDGPUAtomicOptimizerID;
88 
91 extern char &AMDGPULowerIntrinsicsID;
92 
95 extern char &AMDGPUFixFunctionBitcastsID;
96 
99 extern char &AMDGPUCtorDtorLoweringID;
100 
103 extern char &AMDGPULowerKernelArgumentsID;
104 
107 extern char &AMDGPUPromoteKernelArgumentsID;
108 
110  : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
112 };
113 
116 extern char &AMDGPULowerKernelAttributesID;
117 
119  : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
121 };
122 
125 
127  : PassInfoMixin<AMDGPUPropagateAttributesEarlyPass> {
130 
131 private:
132  TargetMachine &TM;
133 };
134 
137 
139  : PassInfoMixin<AMDGPUPropagateAttributesLatePass> {
142 
143 private:
144  TargetMachine &TM;
145 };
146 
149 
151  : PassInfoMixin<AMDGPUReplaceLDSUseWithPointerPass> {
153 };
154 
156 extern char &AMDGPULowerModuleLDSID;
157 
158 struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
160 };
161 
163 extern char &AMDGPURewriteOutArgumentsID;
164 
166 extern char &GCNDPPCombineID;
167 
169 extern char &SIFoldOperandsID;
170 
172 extern char &SIPeepholeSDWAID;
173 
175 extern char &SIShrinkInstructionsID;
176 
178 extern char &SIFixSGPRCopiesID;
179 
181 extern char &SIFixVGPRCopiesID;
182 
184 extern char &SILowerI1CopiesID;
185 
187 extern char &SILowerSGPRSpillsID;
188 
190 extern char &SILoadStoreOptimizerID;
191 
193 extern char &SIWholeQuadModeID;
194 
196 extern char &SILowerControlFlowID;
197 
199 extern char &SIPreEmitPeepholeID;
200 
202 extern char &SILateBranchLoweringPassID;
203 
205 extern char &SIOptimizeExecMaskingID;
206 
208 extern char &SIPreAllocateWWMRegsID;
209 
211 extern char &AMDGPUSimplifyLibCallsID;
212 
214 extern char &AMDGPUUseNativeCallsID;
215 
217 extern char &AMDGPUPerfHintAnalysisID;
218 
219 // Passes common to R600 and SI
222 extern char &AMDGPUPromoteAllocaID;
223 
226 extern char &AMDGPUPromoteAllocaToVectorID;
227 
228 struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
231 
232 private:
233  TargetMachine &TM;
234 };
235 
237  : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
240 
241 private:
242  TargetMachine &TM;
243 };
244 
246 FunctionPass *createAMDGPUISelDag(
247  TargetMachine *TM = nullptr,
249 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
250 
251 struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
252  AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
254 
255 private:
256  bool GlobalOpt;
257 };
258 
259 FunctionPass *createAMDGPUAnnotateUniformValues();
260 
262 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
263 extern char &AMDGPUPrintfRuntimeBindingID;
264 
265 void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
266 extern char &AMDGPUResourceUsageAnalysisID;
267 
269  : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
271 };
272 
275 extern char &AMDGPUUnifyMetadataID;
276 
277 struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
279 };
280 
282 extern char &SIOptimizeExecMaskingPreRAID;
283 
285 extern char &SIOptimizeVGPRLiveRangeID;
286 
289 
291 extern char &AMDGPUCodeGenPrepareID;
292 
294 extern char &AMDGPULateCodeGenPrepareID;
295 
297 extern char &SIAnnotateControlFlowPassID;
298 
300 extern char &SIMemoryLegalizerID;
301 
303 extern char &SIModeRegisterID;
304 
306 extern char &SIInsertHardClausesID;
307 
309 extern char &SIInsertWaitcntsID;
310 
312 extern char &SIFormMemoryClausesID;
313 
315 extern char &SIPostRABundlerID;
316 
319 
324 
326 
330 
332 extern char &GCNNSAReassignID;
333 
335 extern char &GCNPreRAOptimizationsID;
336 
337 namespace AMDGPU {
344 };
345 }
346 
347 /// OpenCL uses address spaces to differentiate between
348 /// various memory regions on the hardware. On the CPU
349 /// all of the address spaces point to the same memory,
350 /// however on the GPU, each address space points to
351 /// a separate piece of memory that is unique from other
352 /// memory locations.
353 namespace AMDGPUAS {
354  enum : unsigned {
355  // The maximum value for flat, generic, local, private, constant and region.
357 
358  FLAT_ADDRESS = 0, ///< Address space for flat memory.
359  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
360  REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
361 
362  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
363  LOCAL_ADDRESS = 3, ///< Address space for local memory.
364  PRIVATE_ADDRESS = 5, ///< Address space for private memory.
365 
366  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
367 
368  BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
369 
370  /// Address space for direct addressable parameter memory (CONST0).
372  /// Address space for indirect addressable parameter memory (VTX1).
374 
375  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
376  // this order to be able to dynamically index a constant buffer, for
377  // example:
378  //
379  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
380 
397 
398  // Some places use this if the address space can't be determined.
400  };
401 }
402 
403 namespace AMDGPU {
404 
405 // FIXME: Missing constant_32bit
406 inline bool isFlatGlobalAddrSpace(unsigned AS) {
407  return AS == AMDGPUAS::GLOBAL_ADDRESS ||
408  AS == AMDGPUAS::FLAT_ADDRESS ||
411 }
412 }
413 
414 } // End namespace llvm
415 
416 #endif
llvm::PreservedAnalyses
A set of analyses that are preserved following a run of a transformation pass.
Definition: PassManager.h:155
llvm::AMDGPUPropagateAttributesEarlyPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPropagateAttributes.cpp:411
llvm::createSIPostRABundlerPass
FunctionPass * createSIPostRABundlerPass()
Definition: SIPostRABundler.cpp:71
llvm::createAMDGPUCtorDtorLoweringPass
ModulePass * createAMDGPUCtorDtorLoweringPass()
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::AMDGPUPromoteAllocaToVectorPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPromoteAlloca.cpp:1150
llvm::createAMDGPUAttributorPass
Pass * createAMDGPUAttributorPass()
Definition: AMDGPUAttributor.cpp:649
llvm::createSIFixControlFlowLiveIntervalsPass
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::AMDGPUMachineCFGStructurizerID
char & AMDGPUMachineCFGStructurizerID
Definition: AMDGPUMachineCFGStructurizer.cpp:2878
Pass
print lazy value Lazy Value Info Printer Pass
Definition: LazyValueInfo.cpp:1965
llvm::AMDGPULowerModuleLDSPass
Definition: AMDGPU.h:158
llvm::initializeAMDGPUPostLegalizerCombinerPass
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
llvm::initializeAMDGPUPromoteAllocaPass
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
llvm::createSIMemoryLegalizerPass
FunctionPass * createSIMemoryLegalizerPass()
Definition: SIMemoryLegalizer.cpp:1861
llvm::AMDGPUAS::CONSTANT_BUFFER_8
@ CONSTANT_BUFFER_8
Definition: AMDGPU.h:389
llvm::SILowerSGPRSpillsID
char & SILowerSGPRSpillsID
Definition: SILowerSGPRSpills.cpp:72
llvm::ModulePass
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:238
llvm::createSIFixSGPRCopiesPass
FunctionPass * createSIFixSGPRCopiesPass()
Definition: SIFixSGPRCopies.cpp:123
llvm::ImmutablePass
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:269
llvm::AMDGPUAlwaysInlinePass
Definition: AMDGPU.h:251
llvm::PassInfoMixin
A CRTP mix-in to automatically provide informational APIs needed for passes.
Definition: PassManager.h:374
llvm::initializeGCNPreRAOptimizationsPass
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
llvm::AMDGPUPrintfRuntimeBindingPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUPrintfRuntimeBinding.cpp:591
llvm::Function
Definition: Function.h:62
llvm::initializeAMDGPUAlwaysInlinePass
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
llvm::initializeAMDGPUOpenCLEnqueuedBlockLoweringPass
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
llvm::initializeSIInsertHardClausesPass
void initializeSIInsertHardClausesPass(PassRegistry &)
llvm::initializeSIPreAllocateWWMRegsPass
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
llvm::AMDGPUPropagateAttributesEarlyPass::AMDGPUPropagateAttributesEarlyPass
AMDGPUPropagateAttributesEarlyPass(TargetMachine &TM)
Definition: AMDGPU.h:128
llvm::initializeAMDGPUPropagateAttributesLatePass
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
llvm::AMDGPUPromoteAllocaToVectorPass
Definition: AMDGPU.h:236
llvm::initializeAMDGPULateCodeGenPreparePass
void initializeAMDGPULateCodeGenPreparePass(PassRegistry &)
llvm::AMDGPUPromoteKernelArgumentsID
char & AMDGPUPromoteKernelArgumentsID
llvm::AMDGPUReplaceLDSUseWithPointerID
char & AMDGPUReplaceLDSUseWithPointerID
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:431
llvm::AMDGPULowerModuleLDSID
char & AMDGPULowerModuleLDSID
Definition: AMDGPULowerModuleLDSPass.cpp:431
llvm::AMDGPUAS::CONSTANT_BUFFER_6
@ CONSTANT_BUFFER_6
Definition: AMDGPU.h:387
llvm::createAMDGPULateCodeGenPreparePass
FunctionPass * createAMDGPULateCodeGenPreparePass()
Definition: AMDGPULateCodeGenPrepare.cpp:195
llvm::AMDGPUUnifyMetadataID
char & AMDGPUUnifyMetadataID
Definition: AMDGPUUnifyMetadata.cpp:127
llvm::createSILowerI1CopiesPass
FunctionPass * createSILowerI1CopiesPass()
Definition: SILowerI1Copies.cpp:413
llvm::initializeSIOptimizeExecMaskingPreRAPass
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
llvm::createSIWholeQuadModePass
FunctionPass * createSIWholeQuadModePass()
Definition: SIWholeQuadMode.cpp:267
llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS
@ MAX_AMDGPU_ADDRESS
Definition: AMDGPU.h:356
llvm::initializeSILowerI1CopiesPass
void initializeSILowerI1CopiesPass(PassRegistry &)
llvm::SIPreEmitPeepholeID
char & SIPreEmitPeepholeID
llvm::createAMDGPUPostLegalizeCombiner
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPostLegalizerCombiner.cpp:400
llvm::initializeAMDGPUDAGToDAGISelPass
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
llvm::initializeSIPeepholeSDWAPass
void initializeSIPeepholeSDWAPass(PassRegistry &)
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:168
llvm::SIOptimizeVGPRLiveRangeID
char & SIOptimizeVGPRLiveRangeID
Definition: SIOptimizeVGPRLiveRange.cpp:572
llvm::createAMDGPUUnifyMetadataPass
ModulePass * createAMDGPUUnifyMetadataPass()
llvm::AMDGPUSimplifyLibCallsID
char & AMDGPUSimplifyLibCallsID
llvm::AMDGPUFixFunctionBitcastsID
char & AMDGPUFixFunctionBitcastsID
Definition: AMDGPUFixFunctionBitcasts.cpp:52
llvm::SIInsertWaitcntsID
char & SIInsertWaitcntsID
Definition: SIInsertWaitcnts.cpp:800
llvm::createSILoadStoreOptimizerPass
FunctionPass * createSILoadStoreOptimizerPass()
Definition: SILoadStoreOptimizer.cpp:577
llvm::initializeSIFoldOperandsPass
void initializeSIFoldOperandsPass(PassRegistry &)
llvm::createAMDGPUISelDag
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
Definition: AMDGPUISelDAGToDAG.cpp:112
llvm::initializeAMDGPUMachineCFGStructurizerPass
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_2
@ CONSTANT_BUFFER_2
Definition: AMDGPU.h:383
llvm::createSIPreAllocateWWMRegsPass
FunctionPass * createSIPreAllocateWWMRegsPass()
Definition: SIPreAllocateWWMRegs.cpp:83
llvm::AMDGPUUseNativeCallsPass
Definition: AMDGPU.h:68
llvm::AMDGPULowerKernelAttributesPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULowerKernelAttributes.cpp:263
llvm::initializeAMDGPUPropagateAttributesEarlyPass
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
llvm::SIPreAllocateWWMRegsID
char & SIPreAllocateWWMRegsID
Definition: SIPreAllocateWWMRegs.cpp:81
llvm::initializeAMDGPUPromoteKernelArgumentsPass
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
llvm::AMDGPUResourceUsageAnalysisID
char & AMDGPUResourceUsageAnalysisID
Definition: AMDGPUResourceUsageAnalysis.cpp:42
llvm::SIPostRABundlerID
char & SIPostRABundlerID
Definition: SIPostRABundler.cpp:69
llvm::initializeSIShrinkInstructionsPass
void initializeSIShrinkInstructionsPass(PassRegistry &)
llvm::initializeAMDGPUSimplifyLibCallsPass
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
llvm::AMDGPUAS::PARAM_D_ADDRESS
@ PARAM_D_ADDRESS
Address space for direct addressable parameter memory (CONST0).
Definition: AMDGPU.h:371
llvm::createAMDGPUStructurizeCFGPass
Pass * createAMDGPUStructurizeCFGPass()
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::createAMDGPUExternalAAWrapperPass
ImmutablePass * createAMDGPUExternalAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:37
llvm::initializeAMDGPULowerIntrinsicsPass
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
llvm::initializeGCNDPPCombinePass
void initializeGCNDPPCombinePass(PassRegistry &)
llvm::AMDGPUUnifyMetadataPass
Definition: AMDGPU.h:277
llvm::AMDGPUPromoteAllocaPass::AMDGPUPromoteAllocaPass
AMDGPUPromoteAllocaPass(TargetMachine &TM)
Definition: AMDGPU.h:229
llvm::AMDGPUUnifyMetadataPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUUnifyMetadata.cpp:140
llvm::SIOptimizeExecMaskingID
char & SIOptimizeExecMaskingID
Definition: SIOptimizeExecMasking.cpp:52
llvm::initializeAMDGPUUnifyMetadataPass
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
llvm::initializeAMDGPUArgumentUsageInfoPass
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
llvm::AMDGPUCodeGenPrepareID
char & AMDGPUCodeGenPrepareID
llvm::AMDGPU::TargetIndex
TargetIndex
Definition: AMDGPU.h:338
llvm::initializeSILateBranchLoweringPass
void initializeSILateBranchLoweringPass(PassRegistry &)
llvm::AMDGPUAS::BUFFER_FAT_POINTER
@ BUFFER_FAT_POINTER
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:368
llvm::AMDGPUAS::CONSTANT_BUFFER_15
@ CONSTANT_BUFFER_15
Definition: AMDGPU.h:396
llvm::createAMDGPUUseNativeCallsPass
FunctionPass * createAMDGPUUseNativeCallsPass()
Definition: AMDGPULibCalls.cpp:1702
llvm::SILowerI1CopiesID
char & SILowerI1CopiesID
Definition: SILowerI1Copies.cpp:411
llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
Definition: AMDGPU.h:366
llvm::AMDGPUAS::CONSTANT_BUFFER_13
@ CONSTANT_BUFFER_13
Definition: AMDGPU.h:394
llvm::initializeAMDGPULowerKernelArgumentsPass
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
llvm::initializeSIWholeQuadModePass
void initializeSIWholeQuadModePass(PassRegistry &)
llvm::initializeAMDGPUAtomicOptimizerPass
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
llvm::createGCNPreRAOptimizationsPass
FunctionPass * createGCNPreRAOptimizationsPass()
Definition: GCNPreRAOptimizations.cpp:81
llvm::createAMDGPULowerModuleLDSPass
ModulePass * createAMDGPULowerModuleLDSPass()
llvm::createSIOptimizeVGPRLiveRangePass
FunctionPass * createSIOptimizeVGPRLiveRangePass()
Definition: SIOptimizeVGPRLiveRange.cpp:574
llvm::initializeAMDGPUUseNativeCallsPass
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
llvm::createSIInsertWaitcntsPass
FunctionPass * createSIInsertWaitcntsPass()
Definition: SIInsertWaitcnts.cpp:802
llvm::AMDGPUAtomicOptimizerID
char & AMDGPUAtomicOptimizerID
Definition: AMDGPUAtomicOptimizer.cpp:80
llvm::createAMDGPUAnnotateUniformValues
FunctionPass * createAMDGPUAnnotateUniformValues()
Definition: AMDGPUAnnotateUniformValues.cpp:150
llvm::AMDGPUPropagateAttributesEarlyID
char & AMDGPUPropagateAttributesEarlyID
llvm::initializeAMDGPUUnifyDivergentExitNodesPass
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_7
@ CONSTANT_BUFFER_7
Definition: AMDGPU.h:388
llvm::AMDGPUPromoteAllocaPass
Definition: AMDGPU.h:228
llvm::AMDGPUOpenCLEnqueuedBlockLoweringID
char & AMDGPUOpenCLEnqueuedBlockLoweringID
Definition: AMDGPUOpenCLEnqueuedBlockLowering.cpp:64
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createSIPeepholeSDWAPass
FunctionPass * createSIPeepholeSDWAPass()
Definition: SIPeepholeSDWA.cpp:193
llvm::AMDGPULowerKernelAttributesPass
Definition: AMDGPU.h:118
llvm::createAMDGPUPropagateAttributesLatePass
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:406
llvm::initializeSIMemoryLegalizerPass
void initializeSIMemoryLegalizerPass(PassRegistry &)
llvm::initializeAMDGPUResourceUsageAnalysisPass
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
llvm::createAMDGPULowerIntrinsicsPass
ModulePass * createAMDGPULowerIntrinsicsPass()
Definition: AMDGPULowerIntrinsics.cpp:180
llvm::createAMDGPUAnnotateKernelFeaturesPass
Pass * createAMDGPUAnnotateKernelFeaturesPass()
Definition: AMDGPUAnnotateKernelFeatures.cpp:137
llvm::initializeAMDGPUReplaceLDSUseWithPointerPass
void initializeAMDGPUReplaceLDSUseWithPointerPass(PassRegistry &)
llvm::AMDGPUReplaceLDSUseWithPointerPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:454
llvm::SILoadStoreOptimizerID
char & SILoadStoreOptimizerID
Definition: SILoadStoreOptimizer.cpp:575
llvm::AMDGPUSimplifyLibCallsPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULibCalls.cpp:1738
llvm::SIMemoryLegalizerID
char & SIMemoryLegalizerID
Definition: SIMemoryLegalizer.cpp:1859
llvm::initializeSIOptimizeVGPRLiveRangePass
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
llvm::createAMDGPUAAWrapperPass
ImmutablePass * createAMDGPUAAWrapperPass()
Definition: AMDGPUAliasAnalysis.cpp:33
llvm::createAMDGPUPrintfRuntimeBinding
ModulePass * createAMDGPUPrintfRuntimeBinding()
Definition: AMDGPUPrintfRuntimeBinding.cpp:92
llvm::createSIFoldOperandsPass
FunctionPass * createSIFoldOperandsPass()
Definition: SIFoldOperands.cpp:198
llvm::createAMDGPUAlwaysInlinePass
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPUAlwaysInlinePass.cpp:163
llvm::initializeSILowerSGPRSpillsPass
void initializeSILowerSGPRSpillsPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_9
@ CONSTANT_BUFFER_9
Definition: AMDGPU.h:390
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
llvm::AMDGPUUnifyDivergentExitNodesID
char & AMDGPUUnifyDivergentExitNodesID
Definition: AMDGPUUnifyDivergentExitNodes.cpp:79
llvm::initializeSIInsertWaitcntsPass
void initializeSIInsertWaitcntsPass(PassRegistry &)
llvm::initializeSIAnnotateControlFlowPass
void initializeSIAnnotateControlFlowPass(PassRegistry &)
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1
@ TI_SCRATCH_RSRC_DWORD1
Definition: AMDGPU.h:341
llvm::createAMDGPUAtomicOptimizerPass
FunctionPass * createAMDGPUAtomicOptimizerPass()
Definition: AMDGPUAtomicOptimizer.cpp:707
llvm::SIPeepholeSDWAID
char & SIPeepholeSDWAID
Definition: SIPeepholeSDWA.cpp:191
llvm::SIFixVGPRCopiesID
char & SIFixVGPRCopiesID
Definition: SIFixVGPRCopies.cpp:45
llvm::initializeAMDGPURewriteOutArgumentsPass
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
llvm::AMDGPU::TI_CONSTDATA_START
@ TI_CONSTDATA_START
Definition: AMDGPU.h:339
llvm::AMDGPUSimplifyLibCallsPass
Definition: AMDGPU.h:60
llvm::AMDGPUUseNativeCallsPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPULibCalls.cpp:1795
llvm::AMDGPUPropagateAttributesLateID
char & AMDGPUPropagateAttributesLateID
llvm::SIFormMemoryClausesID
char & SIFormMemoryClausesID
Definition: SIFormMemoryClauses.cpp:91
llvm::SIFixSGPRCopiesID
char & SIFixSGPRCopiesID
Definition: SIFixSGPRCopies.cpp:121
llvm::SIAnnotateControlFlowPassID
char & SIAnnotateControlFlowPassID
llvm::AMDGPUPromoteKernelArgumentsPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPromoteKernelArguments.cpp:185
llvm::GCNDPPCombineID
char & GCNDPPCombineID
Definition: GCNDPPCombine.cpp:111
llvm::AMDGPUAS::LOCAL_ADDRESS
@ LOCAL_ADDRESS
Address space for local memory.
Definition: AMDGPU.h:363
llvm::AMDGPUPrintfRuntimeBindingID
char & AMDGPUPrintfRuntimeBindingID
Definition: AMDGPUPrintfRuntimeBinding.cpp:89
llvm::SIInsertHardClausesID
char & SIInsertHardClausesID
Definition: SIInsertHardClauses.cpp:220
llvm::TargetMachine
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:79
llvm::AMDGPU::isFlatGlobalAddrSpace
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:406
llvm::AMDGPUAS::CONSTANT_BUFFER_4
@ CONSTANT_BUFFER_4
Definition: AMDGPU.h:385
llvm::initializeSIOptimizeExecMaskingPass
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
llvm::initializeSIPostRABundlerPass
void initializeSIPostRABundlerPass(PassRegistry &)
llvm::AMDGPUCtorDtorLoweringID
char & AMDGPUCtorDtorLoweringID
Definition: AMDGPUCtorDtorLowering.cpp:78
llvm::initializeAMDGPUAAWrapperPassPass
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:67
llvm::initializeAMDGPUCodeGenPreparePass
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
llvm::SIModeRegisterID
char & SIModeRegisterID
llvm::createAMDGPUOpenCLEnqueuedBlockLoweringPass
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
llvm::initializeGCNNSAReassignPass
void initializeGCNNSAReassignPass(PassRegistry &)
llvm::AMDGPUPropagateAttributesLatePass::AMDGPUPropagateAttributesLatePass
AMDGPUPropagateAttributesLatePass(TargetMachine &TM)
Definition: AMDGPU.h:140
llvm::AMDGPUAS::REGION_ADDRESS
@ REGION_ADDRESS
Address space for region memory. (GDS)
Definition: AMDGPU.h:360
llvm::createSIShrinkInstructionsPass
FunctionPass * createSIShrinkInstructionsPass()
llvm::createAMDGPUMachineCFGStructurizerPass
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
Definition: AMDGPUMachineCFGStructurizer.cpp:2886
llvm::createSIFormMemoryClausesPass
FunctionPass * createSIFormMemoryClausesPass()
Definition: SIFormMemoryClauses.cpp:93
llvm::SIShrinkInstructionsID
char & SIShrinkInstructionsID
llvm::AMDGPUAlwaysInlinePass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUAlwaysInlinePass.cpp:167
llvm::AMDGPUPromoteAllocaToVectorPass::AMDGPUPromoteAllocaToVectorPass
AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM)
Definition: AMDGPU.h:238
llvm::initializeSIFormMemoryClausesPass
void initializeSIFormMemoryClausesPass(PassRegistry &)
llvm::createAMDGPURewriteOutArgumentsPass
FunctionPass * createAMDGPURewriteOutArgumentsPass()
Definition: AMDGPURewriteOutArguments.cpp:462
llvm::AMDGPUSimplifyLibCallsPass::AMDGPUSimplifyLibCallsPass
AMDGPUSimplifyLibCallsPass(TargetMachine &TM)
Definition: AMDGPU.h:61
llvm::AMDGPUAS::PARAM_I_ADDRESS
@ PARAM_I_ADDRESS
Address space for indirect addressable parameter memory (VTX1).
Definition: AMDGPU.h:373
llvm::initializeAMDGPUExternalAAWrapperPass
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
llvm::AMDGPUAlwaysInlinePass::AMDGPUAlwaysInlinePass
AMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPU.h:252
llvm::AMDGPUAS::CONSTANT_BUFFER_10
@ CONSTANT_BUFFER_10
Definition: AMDGPU.h:391
llvm::AMDGPUAS::CONSTANT_ADDRESS
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
Definition: AMDGPU.h:362
llvm::createAMDGPURegBankCombiner
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
Definition: AMDGPURegBankCombiner.cpp:272
llvm::AMDGPUAS::CONSTANT_BUFFER_1
@ CONSTANT_BUFFER_1
Definition: AMDGPU.h:382
llvm::AMDGPUAS::CONSTANT_BUFFER_14
@ CONSTANT_BUFFER_14
Definition: AMDGPU.h:395
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::SIWholeQuadModeID
char & SIWholeQuadModeID
Definition: SIWholeQuadMode.cpp:265
llvm::initializeAMDGPULowerKernelAttributesPass
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
llvm::AMDGPUPromoteAllocaPass::run
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
Definition: AMDGPUPromoteAlloca.cpp:154
llvm::initializeAMDGPUAnnotateUniformValuesPass
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
llvm::AMDGPUPrintfRuntimeBindingPass
Definition: AMDGPU.h:268
llvm::AMDGPUReplaceLDSUseWithPointerPass
Definition: AMDGPU.h:150
llvm::createGCNDPPCombinePass
FunctionPass * createGCNDPPCombinePass()
Definition: GCNDPPCombine.cpp:113
llvm::AMDGPUAS::FLAT_ADDRESS
@ FLAT_ADDRESS
Address space for flat memory.
Definition: AMDGPU.h:358
llvm::createAMDGPULowerKernelAttributesPass
ModulePass * createAMDGPULowerKernelAttributesPass()
Definition: AMDGPULowerKernelAttributes.cpp:258
llvm::initializeSIFixSGPRCopiesPass
void initializeSIFixSGPRCopiesPass(PassRegistry &)
llvm::createAMDGPUPromoteAllocaToVector
FunctionPass * createAMDGPUPromoteAllocaToVector()
Definition: AMDGPUPromoteAlloca.cpp:1164
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3
@ TI_SCRATCH_RSRC_DWORD3
Definition: AMDGPU.h:343
llvm::AMDGPUAS::CONSTANT_BUFFER_3
@ CONSTANT_BUFFER_3
Definition: AMDGPU.h:384
llvm::initializeAMDGPULowerModuleLDSPass
void initializeAMDGPULowerModuleLDSPass(PassRegistry &)
llvm::initializeSIFixVGPRCopiesPass
void initializeSIFixVGPRCopiesPass(PassRegistry &)
llvm::AMDGPUAS::PRIVATE_ADDRESS
@ PRIVATE_ADDRESS
Address space for private memory.
Definition: AMDGPU.h:364
llvm::initializeAMDGPUPromoteAllocaToVectorPass
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
llvm::AMDGPUPromoteKernelArgumentsPass
Definition: AMDGPU.h:109
llvm::AMDGPULowerKernelAttributesID
char & AMDGPULowerKernelAttributesID
llvm::initializeSIPreEmitPeepholePass
void initializeSIPreEmitPeepholePass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_11
@ CONSTANT_BUFFER_11
Definition: AMDGPU.h:392
llvm::createAMDGPUPropagateAttributesEarlyPass
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Definition: AMDGPUPropagateAttributes.cpp:401
llvm::AMDGPUPropagateAttributesEarlyPass
Definition: AMDGPU.h:126
llvm::initializeSIModeRegisterPass
void initializeSIModeRegisterPass(PassRegistry &)
llvm::createSIOptimizeExecMaskingPreRAPass
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
Definition: SIOptimizeExecMaskingPreRA.cpp:77
llvm::createAMDGPULowerKernelArgumentsPass
FunctionPass * createAMDGPULowerKernelArgumentsPass()
Definition: AMDGPULowerKernelArguments.cpp:248
llvm::AMDGPUPromoteAllocaID
char & AMDGPUPromoteAllocaID
llvm::AMDGPUAS::CONSTANT_BUFFER_0
@ CONSTANT_BUFFER_0
Definition: AMDGPU.h:381
llvm::createSIModeRegisterPass
FunctionPass * createSIModeRegisterPass()
Definition: SIModeRegister.cpp:157
PassManager.h
llvm::AMDGPUAS::UNKNOWN_ADDRESS_SPACE
@ UNKNOWN_ADDRESS_SPACE
Definition: AMDGPU.h:399
llvm::createAMDGPUReplaceLDSUseWithPointerPass
ModulePass * createAMDGPUReplaceLDSUseWithPointerPass()
Definition: AMDGPUReplaceLDSUseWithPointer.cpp:449
llvm::AMDGPUPropagateAttributesLatePass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPUPropagateAttributes.cpp:422
llvm::AMDGPURewriteOutArgumentsID
char & AMDGPURewriteOutArgumentsID
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0
@ TI_SCRATCH_RSRC_DWORD0
Definition: AMDGPU.h:340
llvm::createAMDGPUPromoteAlloca
FunctionPass * createAMDGPUPromoteAlloca()
Definition: AMDGPUPromoteAlloca.cpp:1160
llvm::initializeAMDGPUPrintfRuntimeBindingPass
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
llvm::initializeAMDGPUPreLegalizerCombinerPass
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
llvm::createAMDGPUCodeGenPreparePass
FunctionPass * createAMDGPUCodeGenPreparePass()
Definition: AMDGPUCodeGenPrepare.cpp:1465
llvm::createAMDGPUPromoteKernelArgumentsPass
FunctionPass * createAMDGPUPromoteKernelArgumentsPass()
Definition: AMDGPUPromoteKernelArguments.cpp:180
CodeGen.h
llvm::initializeAMDGPUAttributorPass
void initializeAMDGPUAttributorPass(PassRegistry &)
llvm::AMDGPULowerModuleLDSPass::run
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
Definition: AMDGPULowerModuleLDSPass.cpp:441
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::createAMDGPUFixFunctionBitcastsPass
ModulePass * createAMDGPUFixFunctionBitcastsPass()
llvm::GCNNSAReassignID
char & GCNNSAReassignID
Definition: GCNNSAReassign.cpp:104
llvm::initializeAMDGPUAnnotateKernelFeaturesPass
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
llvm::createAMDGPUPreLegalizeCombiner
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
Definition: AMDGPUPreLegalizerCombiner.cpp:296
llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2
@ TI_SCRATCH_RSRC_DWORD2
Definition: AMDGPU.h:342
llvm::initializeAMDGPUFixFunctionBitcastsPass
void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &)
llvm::AMDGPUPromoteAllocaToVectorID
char & AMDGPUPromoteAllocaToVectorID
llvm::GCNPreRAOptimizationsID
char & GCNPreRAOptimizationsID
Definition: GCNPreRAOptimizations.cpp:79
llvm::AMDGPUAnnotateUniformValuesPassID
char & AMDGPUAnnotateUniformValuesPassID
llvm::initializeSILoadStoreOptimizerPass
void initializeSILoadStoreOptimizerPass(PassRegistry &)
llvm::initializeAMDGPURegBankCombinerPass
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
llvm::createSIAnnotateControlFlowPass
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
Definition: SIAnnotateControlFlow.cpp:375
llvm::initializeAMDGPUCtorDtorLoweringPass
void initializeAMDGPUCtorDtorLoweringPass(PassRegistry &)
llvm::AnalysisManager
A container for analyses that lazily runs them and caches their results.
Definition: InstructionSimplify.h:44
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::SIFoldOperandsID
char & SIFoldOperandsID
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::AMDGPUUseNativeCallsID
char & AMDGPUUseNativeCallsID
llvm::AMDGPUAS::GLOBAL_ADDRESS
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:359
llvm::AMDGPUAnnotateKernelFeaturesID
char & AMDGPUAnnotateKernelFeaturesID
Definition: AMDGPUAnnotateKernelFeatures.cpp:57
llvm::AMDGPUPerfHintAnalysisID
char & AMDGPUPerfHintAnalysisID
Definition: AMDGPUPerfHintAnalysis.cpp:58
llvm::AMDGPUPropagateAttributesLatePass
Definition: AMDGPU.h:138
llvm::SIOptimizeExecMaskingPreRAID
char & SIOptimizeExecMaskingPreRAID
Definition: SIOptimizeExecMaskingPreRA.cpp:75
llvm::AMDGPULateCodeGenPrepareID
char & AMDGPULateCodeGenPrepareID
llvm::initializeSILowerControlFlowPass
void initializeSILowerControlFlowPass(PassRegistry &)
llvm::SILateBranchLoweringPassID
char & SILateBranchLoweringPassID
Definition: SILateBranchLowering.cpp:66
llvm::initializeAMDGPUPerfHintAnalysisPass
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
llvm::AMDGPUAS::CONSTANT_BUFFER_5
@ CONSTANT_BUFFER_5
Definition: AMDGPU.h:386
llvm::AMDGPULowerKernelArgumentsID
char & AMDGPULowerKernelArgumentsID
llvm::AMDGPULowerIntrinsicsID
char & AMDGPULowerIntrinsicsID
Definition: AMDGPULowerIntrinsics.cpp:63
llvm::AMDGPUAS::CONSTANT_BUFFER_12
@ CONSTANT_BUFFER_12
Definition: AMDGPU.h:393
llvm::createAMDGPUSimplifyLibCallsPass
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetMachine *)
Definition: AMDGPULibCalls.cpp:1698