LLVM 20.0.0git
AMDGPU.h
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1//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// \file
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12
14#include "llvm/IR/PassManager.h"
15#include "llvm/Pass.h"
18
19namespace llvm {
20
21class AMDGPUTargetMachine;
22class GCNTargetMachine;
23class TargetMachine;
24
25// GlobalISel passes
32
34
35// SI Passes
54
67
68struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
71};
72
74 : PassInfoMixin<AMDGPUImageIntrinsicOptimizerPass> {
77
78private:
79 TargetMachine &TM;
80};
81
82struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
84};
85
86class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
87public:
91};
92
94
97
99
105
106// DPP/Iterative option enables the atomic optimizer with given strategy
107// whereas None disables the atomic optimizer.
108enum class ScanOptions { DPP, Iterative, None };
109FunctionPass *createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy);
111extern char &AMDGPUAtomicOptimizerID;
112
116
120
124
126 : PassInfoMixin<AMDGPUPromoteKernelArgumentsPass> {
128};
129
133
135 : PassInfoMixin<AMDGPULowerKernelAttributesPass> {
137};
138
141
142struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
145
147};
148
151
153 : PassInfoMixin<AMDGPULowerBufferFatPointersPass> {
156
157private:
158 const TargetMachine &TM;
159};
160
162extern char &AMDGPURewriteOutArgumentsID;
163
165extern char &GCNDPPCombineID;
166
168extern char &SIFoldOperandsID;
169
171extern char &SIPeepholeSDWAID;
172
174extern char &SIShrinkInstructionsID;
175
177extern char &SIFixSGPRCopiesLegacyID;
178
180extern char &SIFixVGPRCopiesID;
181
183extern char &SILowerWWMCopiesID;
184
186extern char &SILowerI1CopiesLegacyID;
187
190
192extern char &AMDGPUMarkLastScratchLoadID;
193
195extern char &SILowerSGPRSpillsID;
196
198extern char &SILoadStoreOptimizerID;
199
201extern char &SIWholeQuadModeID;
202
204extern char &SILowerControlFlowID;
205
207extern char &SIPreEmitPeepholeID;
208
210extern char &SILateBranchLoweringPassID;
211
213extern char &SIOptimizeExecMaskingID;
214
216extern char &SIPreAllocateWWMRegsID;
217
220
223
225extern char &GCNRegPressurePrinterID;
226
227// Passes common to R600 and SI
230extern char &AMDGPUPromoteAllocaID;
231
235
236struct AMDGPUPromoteAllocaPass : PassInfoMixin<AMDGPUPromoteAllocaPass> {
239
240private:
241 TargetMachine &TM;
242};
243
245 : PassInfoMixin<AMDGPUPromoteAllocaToVectorPass> {
248
249private:
250 TargetMachine &TM;
251};
252
253struct AMDGPUAtomicOptimizerPass : PassInfoMixin<AMDGPUAtomicOptimizerPass> {
255 : TM(TM), ScanImpl(ScanImpl) {}
257
258private:
259 TargetMachine &TM;
260 ScanOptions ScanImpl;
261};
262
265ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
266
267struct AMDGPUAlwaysInlinePass : PassInfoMixin<AMDGPUAlwaysInlinePass> {
268 AMDGPUAlwaysInlinePass(bool GlobalOpt = true) : GlobalOpt(GlobalOpt) {}
270
271private:
272 bool GlobalOpt;
273};
274
276 : public PassInfoMixin<AMDGPUCodeGenPreparePass> {
277private:
278 TargetMachine &TM;
279
280public:
283};
284
286 : public PassInfoMixin<AMDGPULateCodeGenPreparePass> {
287private:
288 const GCNTargetMachine &TM;
289
290public:
293};
294
296 : public PassInfoMixin<AMDGPULowerKernelArgumentsPass> {
297private:
298 TargetMachine &TM;
299
300public:
303};
304
306 bool IsClosedWorld = false;
307};
308
309class AMDGPUAttributorPass : public PassInfoMixin<AMDGPUAttributorPass> {
310private:
311 TargetMachine &TM;
312
314
315public:
317 : TM(TM), Options(Options) {};
318 PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
319};
320
322 : public PassInfoMixin<AMDGPUAnnotateUniformValuesPass> {
323public:
326};
327
329
333
336
338 : PassInfoMixin<AMDGPUPrintfRuntimeBindingPass> {
340};
341
344extern char &AMDGPUUnifyMetadataID;
345
346struct AMDGPUUnifyMetadataPass : PassInfoMixin<AMDGPUUnifyMetadataPass> {
348};
349
352
354extern char &SIOptimizeVGPRLiveRangeID;
355
358
360extern char &AMDGPUCodeGenPrepareID;
361
364
367
371
373 : public PassInfoMixin<AMDGPURewriteUndefForPHIPass> {
374public:
377};
378
380 : public PassInfoMixin<SIAnnotateControlFlowPass> {
381private:
382 const AMDGPUTargetMachine &TM;
383
384public:
387};
388
391
393extern char &SIMemoryLegalizerID;
394
396extern char &SIModeRegisterID;
397
399extern char &AMDGPUInsertDelayAluID;
400
402extern char &AMDGPUInsertSingleUseVDSTID;
403
405extern char &SIInsertHardClausesID;
406
408extern char &SIInsertWaitcntsID;
409
411extern char &SIFormMemoryClausesID;
412
414extern char &SIPostRABundlerID;
415
417extern char &GCNCreateVOPDID;
418
421
426
428
432
434extern char &GCNNSAReassignID;
435
437extern char &GCNPreRALongBranchRegID;
438
440extern char &GCNPreRAOptimizationsID;
441
444
446extern char &GCNRewritePartialRegUsesID;
447
448namespace AMDGPU {
456
457// FIXME: Missing constant_32bit
458inline bool isFlatGlobalAddrSpace(unsigned AS) {
459 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
463}
464
465inline bool isExtendedGlobalAddrSpace(unsigned AS) {
469}
470
471static inline bool addrspacesMayAlias(unsigned AS1, unsigned AS2) {
472 static_assert(AMDGPUAS::MAX_AMDGPU_ADDRESS <= 9, "Addr space out of range");
473
475 return true;
476
477 // This array is indexed by address space value enum elements 0 ... to 9
478 // clang-format off
479 static const bool ASAliasRules[10][10] = {
480 /* Flat Global Region Group Constant Private Const32 BufFatPtr BufRsrc BufStrdPtr */
481 /* Flat */ {true, true, false, true, true, true, true, true, true, true},
482 /* Global */ {true, true, false, false, true, false, true, true, true, true},
483 /* Region */ {false, false, true, false, false, false, false, false, false, false},
484 /* Group */ {true, false, false, true, false, false, false, false, false, false},
485 /* Constant */ {true, true, false, false, false, false, true, true, true, true},
486 /* Private */ {true, false, false, false, false, true, false, false, false, false},
487 /* Constant 32-bit */ {true, true, false, false, true, false, false, true, true, true},
488 /* Buffer Fat Ptr */ {true, true, false, false, true, false, true, true, true, true},
489 /* Buffer Resource */ {true, true, false, false, true, false, true, true, true, true},
490 /* Buffer Strided Ptr */ {true, true, false, false, true, false, true, true, true, true},
491 };
492 // clang-format on
493
494 return ASAliasRules[AS1][AS2];
495}
496
497}
498
499} // End namespace llvm
500
501#endif
AMDGPU address space definition.
#define F(x, y, z)
Definition: MD5.cpp:55
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
const char LLVMTargetMachineRef TM
This header defines various interfaces for pass management in LLVM.
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPUAttributorPass(TargetMachine &TM, AMDGPUAttributorOptions Options={})
Definition: AMDGPU.h:316
PreservedAnalyses run(Function &, FunctionAnalysisManager &)
AMDGPUCodeGenPreparePass(TargetMachine &TM)
Definition: AMDGPU.h:281
AMDGPULateCodeGenPreparePass(const GCNTargetMachine &TM)
Definition: AMDGPU.h:291
PreservedAnalyses run(Function &, FunctionAnalysisManager &)
AMDGPULowerKernelArgumentsPass(TargetMachine &TM)
Definition: AMDGPU.h:301
PreservedAnalyses run(Function &, FunctionAnalysisManager &)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:253
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:310
ImmutablePass class - This class is used to provide information that does not need to be run.
Definition: Pass.h:281
ModulePass class - This class is used to implement unstructured interprocedural optimizations and ana...
Definition: Pass.h:251
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
A set of analyses that are preserved following a run of a transformation pass.
Definition: Analysis.h:111
SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM)
Definition: AMDGPU.h:385
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(MachineFunction &MF, MachineFunctionAnalysisManager &MFAM)
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:77
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ FLAT_ADDRESS
Address space for flat memory.
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
bool isFlatGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:458
static bool addrspacesMayAlias(unsigned AS1, unsigned AS2)
Definition: AMDGPU.h:471
@ TI_SCRATCH_RSRC_DWORD1
Definition: AMDGPU.h:452
@ TI_SCRATCH_RSRC_DWORD3
Definition: AMDGPU.h:454
@ TI_SCRATCH_RSRC_DWORD0
Definition: AMDGPU.h:451
@ TI_SCRATCH_RSRC_DWORD2
Definition: AMDGPU.h:453
@ TI_CONSTDATA_START
Definition: AMDGPU.h:450
bool isExtendedGlobalAddrSpace(unsigned AS)
Definition: AMDGPU.h:465
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeSIFormMemoryClausesPass(PassRegistry &)
char & SIPreAllocateWWMRegsID
ScanOptions
Definition: AMDGPU.h:108
ImmutablePass * createAMDGPUAAWrapperPass()
char & SIAnnotateControlFlowLegacyPassID
FunctionPass * createSIPreAllocateWWMRegsPass()
FunctionPass * createAMDGPUSetWavePriorityPass()
char & AMDGPUCtorDtorLoweringLegacyPassID
void initializeAMDGPUInsertSingleUseVDSTPass(PassRegistry &)
void initializeGCNCreateVOPDPass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
char & AMDGPUAnnotateKernelFeaturesID
char & GCNPreRAOptimizationsID
void initializeGCNPreRAOptimizationsPass(PassRegistry &)
void initializeGCNRewritePartialRegUsesPass(llvm::PassRegistry &)
char & SIMemoryLegalizerID
void initializeAMDGPUAttributorLegacyPass(PassRegistry &)
char & SIPostRABundlerID
FunctionPass * createSIAnnotateControlFlowLegacyPass()
Create the annotation pass.
FunctionPass * createSIModeRegisterPass()
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
ModulePass * createAMDGPULowerBufferFatPointersPass()
void initializeSIModeRegisterPass(PassRegistry &)
ModulePass * createAMDGPUCtorDtorLoweringLegacyPass()
void initializeSIOptimizeVGPRLiveRangePass(PassRegistry &)
char & AMDGPUImageIntrinsicOptimizerID
void initializeAMDGPURewriteUndefForPHILegacyPass(PassRegistry &)
char & AMDGPUPromoteKernelArgumentsID
FunctionPass * createAMDGPUPreLegalizeCombiner(bool IsOptNone)
char & GCNRewritePartialRegUsesID
FunctionPass * createAMDGPUPostLegalizeCombiner(bool IsOptNone)
void initializeSIShrinkInstructionsPass(PassRegistry &)
char & SIFoldOperandsID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
void initializeGCNPreRALongBranchRegPass(PassRegistry &)
char & AMDGPUResourceUsageAnalysisID
char & SILoadStoreOptimizerID
FunctionPass * createSIWholeQuadModePass()
void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &)
ModulePass * createAMDGPULowerKernelAttributesPass()
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
FunctionPass * createSIPeepholeSDWAPass()
void initializeSIPreEmitPeepholePass(PassRegistry &)
char & AMDGPUPromoteAllocaToVectorID
FunctionPass * createSILoadStoreOptimizerPass()
char & SILowerWWMCopiesID
void initializeSIFixVGPRCopiesPass(PassRegistry &)
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
void initializeAMDGPUGlobalISelDivergenceLoweringPass(PassRegistry &)
void initializeAMDGPURemoveIncompatibleFunctionsPass(PassRegistry &)
void initializeSILowerWWMCopiesPass(PassRegistry &)
void initializeGCNNSAReassignPass(PassRegistry &)
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & AMDGPUInsertSingleUseVDSTID
char & SIFormMemoryClausesID
char & AMDGPURemoveIncompatibleFunctionsID
void initializeAMDGPULowerModuleLDSLegacyPass(PassRegistry &)
void initializeAMDGPUCtorDtorLoweringLegacyPass(PassRegistry &)
void initializeAMDGPURegBankCombinerPass(PassRegistry &)
void initializeSILoadStoreOptimizerPass(PassRegistry &)
void initializeSILateBranchLoweringPass(PassRegistry &)
void initializeSIPeepholeSDWAPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAllocaToVector()
char & AMDGPUUnifyDivergentExitNodesID
char & SIInsertWaitcntsID
FunctionPass * createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy)
char & AMDGPUPrintfRuntimeBindingID
char & GCNNSAReassignID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
char & SILowerSGPRSpillsID
char & SILateBranchLoweringPassID
char & SIModeRegisterID
FunctionPass * createGCNPreRAOptimizationsPass()
FunctionPass * createSIShrinkInstructionsPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
void initializeSIPostRABundlerPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaToVectorPass(PassRegistry &)
Pass * createAMDGPUAttributorLegacyPass()
void initializeSIWholeQuadModePass(PassRegistry &)
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUInsertDelayAluID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
char & SIOptimizeVGPRLiveRangeID
char & SIOptimizeExecMaskingPreRAID
char & AMDGPULowerModuleLDSLegacyPassID
void initializeSIInsertHardClausesPass(PassRegistry &)
FunctionPass * createSIPostRABundlerPass()
FunctionPass * createSIFormMemoryClausesPass()
void initializeAMDGPUPostLegalizerCombinerPass(PassRegistry &)
Pass * createAMDGPUStructurizeCFGPass()
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
char & AMDGPULowerBufferFatPointersID
ModulePass * createAMDGPUPrintfRuntimeBinding()
void initializeSIMemoryLegalizerPass(PassRegistry &)
char & AMDGPUUnifyMetadataID
void initializeAMDGPUImageIntrinsicOptimizerPass(PassRegistry &)
ModulePass * createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM=nullptr)
void initializeAMDGPUPreLegalizerCombinerPass(PassRegistry &)
FunctionPass * createAMDGPUPromoteAlloca()
char & SIPreEmitPeepholeID
ModulePass * createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *)
void initializeGCNRegPressurePrinterPass(PassRegistry &)
char & AMDGPURewriteOutArgumentsID
void initializeSILowerI1CopiesLegacyPass(PassRegistry &)
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
char & AMDGPUPromoteAllocaID
FunctionPass * createAMDGPUCodeGenPreparePass()
void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &)
FunctionPass * createAMDGPUISelDag(TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a AMDGPU-specific.
void initializeSIFixSGPRCopiesLegacyPass(PassRegistry &)
char & AMDGPUAnnotateUniformValuesLegacyPassID
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
char & AMDGPUMachineCFGStructurizerID
char & AMDGPULowerKernelAttributesID
char & GCNDPPCombineID
char & GCNRegPressurePrinterID
FunctionPass * createAMDGPURegBankCombiner(bool IsOptNone)
FunctionPass * createSIFoldOperandsPass()
char & SIWholeQuadModeID
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
void initializeAMDGPUMarkLastScratchLoadPass(PassRegistry &)
ImmutablePass * createAMDGPUExternalAAWrapperPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
FunctionPass * createAMDGPURewriteUndefForPHILegacyPass()
void initializeSILowerSGPRSpillsPass(PassRegistry &)
FunctionPass * createSILowerI1CopiesLegacyPass()
char & AMDGPULateCodeGenPrepareLegacyID
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
char & SIInsertHardClausesID
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &)
char & SIFixSGPRCopiesLegacyID
char & GCNCreateVOPDID
char & SILowerControlFlowID
char & AMDGPUAtomicOptimizerID
char & SILowerI1CopiesLegacyID
FunctionPass * createLowerWWMCopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
FunctionPass * createAMDGPUGlobalISelDivergenceLoweringPass()
FunctionPass * createSIMemoryLegalizerPass()
void initializeAMDGPULateCodeGenPrepareLegacyPass(PassRegistry &)
void initializeSIFoldOperandsPass(PassRegistry &)
void initializeSILowerControlFlowPass(PassRegistry &)
char & SIPeepholeSDWAID
char & AMDGPUOpenCLEnqueuedBlockLoweringID
char & SIFixVGPRCopiesID
void initializeAMDGPURegBankSelectPass(PassRegistry &)
FunctionPass * createAMDGPULateCodeGenPrepareLegacyPass()
char & AMDGPURewriteUndefForPHILegacyPassID
FunctionPass * createSIOptimizeVGPRLiveRangePass()
FunctionPass * createAMDGPUImageIntrinsicOptimizerPass(const TargetMachine *)
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
void initializeAMDGPULowerBufferFatPointersPass(PassRegistry &)
FunctionPass * createSIInsertWaitcntsPass()
FunctionPass * createAMDGPUAnnotateUniformValuesLegacy()
void initializeGCNDPPCombinePass(PassRegistry &)
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
FunctionPass * createGCNDPPCombinePass()
AnalysisManager< Module > ModuleAnalysisManager
Convenience typedef for the Module analysis manager.
Definition: MIRParser.h:38
char & AMDGPUMarkLastScratchLoadID
void initializeAMDGPUAnnotateUniformValuesLegacyPass(PassRegistry &)
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
void initializeAMDGPUInsertDelayAluPass(PassRegistry &)
char & SIOptimizeExecMaskingID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
char & AMDGPULowerKernelArgumentsID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
char & AMDGPUCodeGenPrepareID
void initializeAMDGPUSetWavePriorityPass(PassRegistry &)
FunctionPass * createSIFixSGPRCopiesLegacyPass()
char & SIShrinkInstructionsID
char & AMDGPUPerfHintAnalysisLegacyID
FunctionPass * createAMDGPUPromoteKernelArgumentsPass()
char & GCNPreRALongBranchRegID
void initializeAMDGPUPerfHintAnalysisLegacyPass(PassRegistry &)
void initializeAMDGPUPromoteKernelArgumentsPass(PassRegistry &)
AMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Definition: AMDGPU.h:268
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUAtomicOptimizerPass(TargetMachine &TM, ScanOptions ScanImpl)
Definition: AMDGPU.h:254
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUImageIntrinsicOptimizerPass(TargetMachine &TM)
Definition: AMDGPU.h:75
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPULowerBufferFatPointersPass(const TargetMachine &TM)
Definition: AMDGPU.h:154
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPULowerModuleLDSPass(const AMDGPUTargetMachine &TM_)
Definition: AMDGPU.h:144
const AMDGPUTargetMachine & TM
Definition: AMDGPU.h:143
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
AMDGPUPromoteAllocaPass(TargetMachine &TM)
Definition: AMDGPU.h:237
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
AMDGPUPromoteAllocaToVectorPass(TargetMachine &TM)
Definition: AMDGPU.h:246
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM)
PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM)
A CRTP mix-in to automatically provide informational APIs needed for passes.
Definition: PassManager.h:69