LLVM  10.0.0svn
AMDGPU.h
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1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 /// \file
8 //===----------------------------------------------------------------------===//
9 
10 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
11 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12 
14 
15 namespace llvm {
16 
17 class AMDGPUTargetMachine;
18 class FunctionPass;
19 class GCNTargetMachine;
20 class ModulePass;
21 class Pass;
22 class Target;
23 class TargetMachine;
24 class TargetOptions;
25 class PassRegistry;
26 class Module;
27 
28 // R600 Passes
29 FunctionPass *createR600VectorRegMerger();
30 FunctionPass *createR600ExpandSpecialInstrsPass();
31 FunctionPass *createR600EmitClauseMarkers();
32 FunctionPass *createR600ClauseMergePass();
33 FunctionPass *createR600Packetizer();
34 FunctionPass *createR600ControlFlowFinalizer();
35 FunctionPass *createAMDGPUCFGStructurizerPass();
36 FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
37 
38 // SI Passes
39 FunctionPass *createGCNDPPCombinePass();
40 FunctionPass *createSIAnnotateControlFlowPass();
41 FunctionPass *createSIFoldOperandsPass();
42 FunctionPass *createSIPeepholeSDWAPass();
43 FunctionPass *createSILowerI1CopiesPass();
44 FunctionPass *createSIFixupVectorISelPass();
45 FunctionPass *createSIAddIMGInitPass();
46 FunctionPass *createSIShrinkInstructionsPass();
47 FunctionPass *createSILoadStoreOptimizerPass();
48 FunctionPass *createSIWholeQuadModePass();
51 FunctionPass *createSIFixSGPRCopiesPass();
52 FunctionPass *createSIMemoryLegalizerPass();
53 FunctionPass *createSIInsertWaitcntsPass();
54 FunctionPass *createSIPreAllocateWWMRegsPass();
55 FunctionPass *createSIFormMemoryClausesPass();
56 FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &,
57  const TargetMachine *);
58 FunctionPass *createAMDGPUUseNativeCallsPass();
59 FunctionPass *createAMDGPUCodeGenPreparePass();
61 FunctionPass *createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *);
62 ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
64 FunctionPass *createSIModeRegisterPass();
65 
66 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
67 
70 
71 void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
72 
76 
77 FunctionPass *createAMDGPUAtomicOptimizerPass();
78 void initializeAMDGPUAtomicOptimizerPass(PassRegistry &);
79 extern char &AMDGPUAtomicOptimizerID;
80 
82 void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
83 extern char &AMDGPULowerIntrinsicsID;
84 
86 void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &);
87 extern char &AMDGPUFixFunctionBitcastsID;
88 
90 void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &);
91 extern char &AMDGPULowerKernelArgumentsID;
92 
96 
99 
102 
103 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
104 extern char &AMDGPURewriteOutArgumentsID;
105 
106 void initializeGCNDPPCombinePass(PassRegistry &);
107 extern char &GCNDPPCombineID;
108 
109 void initializeR600ClauseMergePassPass(PassRegistry &);
110 extern char &R600ClauseMergePassID;
111 
112 void initializeR600ControlFlowFinalizerPass(PassRegistry &);
113 extern char &R600ControlFlowFinalizerID;
114 
115 void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
116 extern char &R600ExpandSpecialInstrsPassID;
117 
118 void initializeR600VectorRegMergerPass(PassRegistry &);
119 extern char &R600VectorRegMergerID;
120 
121 void initializeR600PacketizerPass(PassRegistry &);
122 extern char &R600PacketizerID;
123 
124 void initializeSIFoldOperandsPass(PassRegistry &);
125 extern char &SIFoldOperandsID;
126 
127 void initializeSIPeepholeSDWAPass(PassRegistry &);
128 extern char &SIPeepholeSDWAID;
129 
130 void initializeSIShrinkInstructionsPass(PassRegistry&);
131 extern char &SIShrinkInstructionsID;
132 
133 void initializeSIFixSGPRCopiesPass(PassRegistry &);
134 extern char &SIFixSGPRCopiesID;
135 
136 void initializeSIFixVGPRCopiesPass(PassRegistry &);
137 extern char &SIFixVGPRCopiesID;
138 
139 void initializeSIFixupVectorISelPass(PassRegistry &);
140 extern char &SIFixupVectorISelID;
141 
142 void initializeSILowerI1CopiesPass(PassRegistry &);
143 extern char &SILowerI1CopiesID;
144 
145 void initializeSILowerSGPRSpillsPass(PassRegistry &);
146 extern char &SILowerSGPRSpillsID;
147 
148 void initializeSILoadStoreOptimizerPass(PassRegistry &);
149 extern char &SILoadStoreOptimizerID;
150 
151 void initializeSIWholeQuadModePass(PassRegistry &);
152 extern char &SIWholeQuadModeID;
153 
154 void initializeSILowerControlFlowPass(PassRegistry &);
155 extern char &SILowerControlFlowID;
156 
157 void initializeSIInsertSkipsPass(PassRegistry &);
158 extern char &SIInsertSkipsPassID;
159 
160 void initializeSIOptimizeExecMaskingPass(PassRegistry &);
161 extern char &SIOptimizeExecMaskingID;
162 
163 void initializeSIPreAllocateWWMRegsPass(PassRegistry &);
164 extern char &SIPreAllocateWWMRegsID;
165 
166 void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
167 extern char &AMDGPUSimplifyLibCallsID;
168 
169 void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
170 extern char &AMDGPUUseNativeCallsID;
171 
172 void initializeSIAddIMGInitPass(PassRegistry &);
173 extern char &SIAddIMGInitID;
174 
175 void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &);
176 extern char &AMDGPUPerfHintAnalysisID;
177 
178 // Passes common to R600 and SI
179 FunctionPass *createAMDGPUPromoteAlloca();
180 void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
181 extern char &AMDGPUPromoteAllocaID;
182 
184 FunctionPass *createAMDGPUISelDag(
185  TargetMachine *TM = nullptr,
187 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
189 FunctionPass *createAMDGPUAnnotateUniformValues();
190 
192 void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry&);
193 extern char &AMDGPUPrintfRuntimeBindingID;
194 
195 ModulePass* createAMDGPUUnifyMetadataPass();
196 void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
197 extern char &AMDGPUUnifyMetadataID;
198 
199 void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
200 extern char &SIOptimizeExecMaskingPreRAID;
201 
204 
205 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
206 extern char &AMDGPUCodeGenPrepareID;
207 
208 void initializeSIAnnotateControlFlowPass(PassRegistry&);
209 extern char &SIAnnotateControlFlowPassID;
210 
211 void initializeSIMemoryLegalizerPass(PassRegistry&);
212 extern char &SIMemoryLegalizerID;
213 
214 void initializeSIModeRegisterPass(PassRegistry&);
215 extern char &SIModeRegisterID;
216 
217 void initializeSIInsertWaitcntsPass(PassRegistry&);
218 extern char &SIInsertWaitcntsID;
219 
220 void initializeSIFormMemoryClausesPass(PassRegistry&);
221 extern char &SIFormMemoryClausesID;
222 
225 
226 ImmutablePass *createAMDGPUAAWrapperPass();
227 void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
228 ImmutablePass *createAMDGPUExternalAAWrapperPass();
229 void initializeAMDGPUExternalAAWrapperPass(PassRegistry&);
230 
231 void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
232 
234 void initializeAMDGPUInlinerPass(PassRegistry&);
235 
239 
240 void initializeGCNRegBankReassignPass(PassRegistry &);
241 extern char &GCNRegBankReassignID;
242 
243 void initializeGCNNSAReassignPass(PassRegistry &);
244 extern char &GCNNSAReassignID;
245 
246 namespace AMDGPU {
253 };
254 }
255 
256 } // End namespace llvm
257 
258 /// OpenCL uses address spaces to differentiate between
259 /// various memory regions on the hardware. On the CPU
260 /// all of the address spaces point to the same memory,
261 /// however on the GPU, each address space points to
262 /// a separate piece of memory that is unique from other
263 /// memory locations.
264 namespace AMDGPUAS {
265  enum : unsigned {
266  // The maximum value for flat, generic, local, private, constant and region.
268 
269  FLAT_ADDRESS = 0, ///< Address space for flat memory.
270  GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
271  REGION_ADDRESS = 2, ///< Address space for region memory. (GDS)
272 
273  CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2).
274  LOCAL_ADDRESS = 3, ///< Address space for local memory.
275  PRIVATE_ADDRESS = 5, ///< Address space for private memory.
276 
277  CONSTANT_ADDRESS_32BIT = 6, ///< Address space for 32-bit constant memory.
278 
279  BUFFER_FAT_POINTER = 7, ///< Address space for 160-bit buffer fat pointers.
280 
281  /// Address space for direct addressible parameter memory (CONST0).
283  /// Address space for indirect addressible parameter memory (VTX1).
285 
286  // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
287  // this order to be able to dynamically index a constant buffer, for
288  // example:
289  //
290  // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
291 
308 
309  // Some places use this if the address space can't be determined.
311  };
312 }
313 
314 #endif
char & SIFormMemoryClausesID
FunctionPass * createAMDGPUPropagateAttributesEarlyPass(const TargetMachine *)
Pass * createAMDGPUStructurizeCFGPass()
void initializeAMDGPUDAGToDAGISelPass(PassRegistry &)
char & SIWholeQuadModeID
FunctionPass * createSIAnnotateControlFlowPass()
Create the annotation pass.
ModulePass * createAMDGPUAlwaysInlinePass(bool GlobalOpt=true)
Address space for 160-bit buffer fat pointers.
Definition: AMDGPU.h:279
FunctionPass * createSIPeepholeSDWAPass()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
FunctionPass * createSIFormMemoryClausesPass()
char & SIShrinkInstructionsID
void initializeSIFixVGPRCopiesPass(PassRegistry &)
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
void initializeSIInsertWaitcntsPass(PassRegistry &)
char & AMDGPULowerKernelAttributesID
char & GCNNSAReassignID
void initializeSIFormMemoryClausesPass(PassRegistry &)
ModulePass * createR600OpenCLImageTypeLoweringPass()
void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &)
void initializeAMDGPUAtomicOptimizerPass(PassRegistry &)
char & SILoadStoreOptimizerID
Address space for 32-bit constant memory.
Definition: AMDGPU.h:277
char & SIPeepholeSDWAID
void initializeSIModeRegisterPass(PassRegistry &)
void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &)
char & AMDGPULowerKernelArgumentsID
void initializeAMDGPULowerKernelAttributesPass(PassRegistry &)
void initializeR600ControlFlowFinalizerPass(PassRegistry &)
void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry &)
char & AMDGPUOpenCLEnqueuedBlockLoweringID
FunctionPass * createAMDGPUPromoteAlloca()
ModulePass * createAMDGPULowerKernelAttributesPass()
FunctionPass * createAMDGPUCodeGenPreparePass()
char & SIFixupVectorISelID
FunctionPass * createAMDGPUCFGStructurizerPass()
Address space for region memory. (GDS)
Definition: AMDGPU.h:271
void initializeAMDGPUAAWrapperPassPass(PassRegistry &)
void initializeAMDGPUPromoteAllocaPass(PassRegistry &)
void initializeAMDGPULowerKernelArgumentsPass(PassRegistry &)
FunctionPass * createSIAddIMGInitPass()
FunctionPass * createSIMemoryLegalizerPass()
FunctionPass * createAMDGPUMachineCFGStructurizerPass()
FunctionPass * createSIInsertWaitcntsPass()
char & AMDGPUAtomicOptimizerID
ModulePass * createAMDGPUPrintfRuntimeBinding()
Address space for global memory (RAT0, VTX0).
Definition: AMDGPU.h:270
char & AMDGPURewriteOutArgumentsID
Pass * createAMDGPUFunctionInliningPass()
char & AMDGPUUnifyMetadataID
Pass * createAMDGPUAnnotateKernelFeaturesPass()
void initializeAMDGPUCodeGenPreparePass(PassRegistry &)
ModulePass * createAMDGPUOpenCLEnqueuedBlockLoweringPass()
void initializeGCNNSAReassignPass(PassRegistry &)
void initializeAMDGPUInlinerPass(PassRegistry &)
char & SIOptimizeExecMaskingPreRAID
char & R600ControlFlowFinalizerID
FunctionPass * createR600ExpandSpecialInstrsPass()
FunctionPass * createSIFixupVectorISelPass()
char & R600PacketizerID
FunctionPass * createSILowerI1CopiesPass()
void initializeSIOptimizeExecMaskingPass(PassRegistry &)
void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry &)
void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &)
void initializeSIFixSGPRCopiesPass(PassRegistry &)
void initializeAMDGPULowerIntrinsicsPass(PassRegistry &)
FunctionPass * createR600VectorRegMerger()
void initializeSIFixupVectorISelPass(PassRegistry &)
char & R600ExpandSpecialInstrsPassID
FunctionPass * createAMDGPURewriteOutArgumentsPass()
void initializeAMDGPUExternalAAWrapperPass(PassRegistry &)
Address space for private memory.
Definition: AMDGPU.h:275
FunctionPass * createAMDGPUISelDag(TargetMachine *TM=nullptr, CodeGenOpt::Level OptLevel=CodeGenOpt::Default)
This pass converts a legalized DAG into a AMDGPU-specific.
char & GCNDPPCombineID
char & AMDGPUPrintfRuntimeBindingID
FunctionPass * createSIOptimizeExecMaskingPreRAPass()
FunctionPass * createAMDGPULowerKernelArgumentsPass()
char & AMDGPUAnnotateUniformValuesPassID
FunctionPass * createSIWholeQuadModePass()
FunctionPass * createSIFixControlFlowLiveIntervalsPass()
Address space for local memory.
Definition: AMDGPU.h:274
char & AMDGPUUseNativeCallsID
Address space for flat memory.
Definition: AMDGPU.h:269
FunctionPass * createGCNDPPCombinePass()
void initializeAMDGPUPrintfRuntimeBindingPass(PassRegistry &)
char & SIInsertSkipsPassID
char & AMDGPUPropagateAttributesEarlyID
void initializeSIPeepholeSDWAPass(PassRegistry &)
char & AMDGPUAnnotateKernelFeaturesID
char & AMDGPUPerfHintAnalysisID
FunctionPass * createR600ControlFlowFinalizer()
void initializeSILowerControlFlowPass(PassRegistry &)
void initializeAMDGPUPerfHintAnalysisPass(PassRegistry &)
ModulePass * createAMDGPULowerIntrinsicsPass()
FunctionPass * createSIModeRegisterPass()
FunctionPass * createR600ClauseMergePass()
char & SILowerI1CopiesID
void initializeSIShrinkInstructionsPass(PassRegistry &)
void initializeAMDGPUUseNativeCallsPass(PassRegistry &)
void initializeSIAddIMGInitPass(PassRegistry &)
void initializeSIInsertSkipsPass(PassRegistry &)
Address space for indirect addressible parameter memory (VTX1).
Definition: AMDGPU.h:284
void initializeR600PacketizerPass(PassRegistry &)
FunctionPass * createAMDGPUAnnotateUniformValues()
char & SIOptimizeExecMaskingID
void initializeGCNRegBankReassignPass(PassRegistry &)
char & SIInsertWaitcntsID
print lazy value Lazy Value Info Printer Pass
void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry &)
void initializeAMDGPUFixFunctionBitcastsPass(PassRegistry &)
char & AMDGPUUnifyDivergentExitNodesID
void initializeSIMemoryLegalizerPass(PassRegistry &)
FunctionPass * createSIPreAllocateWWMRegsPass()
char & SIPreAllocateWWMRegsID
void initializeSIWholeQuadModePass(PassRegistry &)
FunctionPass * createAMDGPUAtomicOptimizerPass()
void initializeR600VectorRegMergerPass(PassRegistry &)
char & SIMemoryLegalizerID
char & SIFixVGPRCopiesID
void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &)
OpenCL uses address spaces to differentiate between various memory regions on the hardware...
Definition: AMDGPU.h:264
void initializeGCNDPPCombinePass(PassRegistry &)
ImmutablePass * createAMDGPUAAWrapperPass()
FunctionPass * createR600EmitClauseMarkers()
char & AMDGPUPropagateAttributesLateID
void initializeR600ClauseMergePassPass(PassRegistry &)
ModulePass * createAMDGPUFixFunctionBitcastsPass()
char & SIAnnotateControlFlowPassID
void initializeAMDGPUUnifyMetadataPass(PassRegistry &)
void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &)
Address space for constant memory (VTX2).
Definition: AMDGPU.h:273
char & SILowerSGPRSpillsID
FunctionPass * createSIFixSGPRCopiesPass()
FunctionPass * createR600Packetizer()
void initializeSILoadStoreOptimizerPass(PassRegistry &)
char & SILowerControlFlowID
ModulePass * createAMDGPUUnifyMetadataPass()
void initializeSIAnnotateControlFlowPass(PassRegistry &)
char & SIModeRegisterID
char & AMDGPUSimplifyLibCallsID
void initializeSIFoldOperandsPass(PassRegistry &)
char & SIFoldOperandsID
void initializeAMDGPUPropagateAttributesLatePass(PassRegistry &)
FunctionPass * createSIShrinkInstructionsPass()
FunctionPass * createSIFoldOperandsPass()
char & SIFixSGPRCopiesID
void initializeSILowerSGPRSpillsPass(PassRegistry &)
char & AMDGPUMachineCFGStructurizerID
ImmutablePass * createAMDGPUExternalAAWrapperPass()
ModulePass * createAMDGPUPropagateAttributesLatePass(const TargetMachine *)
char & AMDGPULowerIntrinsicsID
char & GCNRegBankReassignID
FunctionPass * createSILoadStoreOptimizerPass()
FunctionPass * createAMDGPUSimplifyLibCallsPass(const TargetOptions &, const TargetMachine *)
FunctionPass * createAMDGPUUseNativeCallsPass()
void initializeAMDGPUPropagateAttributesEarlyPass(PassRegistry &)
char & AMDGPUPromoteAllocaID
void initializeSILowerI1CopiesPass(PassRegistry &)
void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry &)
char & AMDGPUCodeGenPrepareID
char & AMDGPUFixFunctionBitcastsID
char & SIAddIMGInitID
void initializeAMDGPUAlwaysInlinePass(PassRegistry &)
Address space for direct addressible parameter memory (CONST0).
Definition: AMDGPU.h:282
void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &)
void initializeSIPreAllocateWWMRegsPass(PassRegistry &)
char & R600ClauseMergePassID