LLVM  14.0.0git
SILowerControlFlow.cpp
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1 //===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This pass lowers the pseudo control flow instructions to real
11 /// machine instructions.
12 ///
13 /// All control flow is handled using predicated instructions and
14 /// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
15 /// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
16 /// by writting to the 64-bit EXEC register (each bit corresponds to a
17 /// single vector ALU). Typically, for predicates, a vector ALU will write
18 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
19 /// Vector ALU) and then the ScalarALU will AND the VCC register with the
20 /// EXEC to update the predicates.
21 ///
22 /// For example:
23 /// %vcc = V_CMP_GT_F32 %vgpr1, %vgpr2
24 /// %sgpr0 = SI_IF %vcc
25 /// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0
26 /// %sgpr0 = SI_ELSE %sgpr0
27 /// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr0
28 /// SI_END_CF %sgpr0
29 ///
30 /// becomes:
31 ///
32 /// %sgpr0 = S_AND_SAVEEXEC_B64 %vcc // Save and update the exec mask
33 /// %sgpr0 = S_XOR_B64 %sgpr0, %exec // Clear live bits from saved exec mask
34 /// S_CBRANCH_EXECZ label0 // This instruction is an optional
35 /// // optimization which allows us to
36 /// // branch if all the bits of
37 /// // EXEC are zero.
38 /// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0 // Do the IF block of the branch
39 ///
40 /// label0:
41 /// %sgpr0 = S_OR_SAVEEXEC_B64 %sgpr0 // Restore the exec mask for the Then block
42 /// %exec = S_XOR_B64 %sgpr0, %exec // Update the exec mask
43 /// S_BRANCH_EXECZ label1 // Use our branch optimization
44 /// // instruction again.
45 /// %vgpr0 = V_SUB_F32 %vgpr0, %vgpr // Do the THEN block
46 /// label1:
47 /// %exec = S_OR_B64 %exec, %sgpr0 // Re-enable saved exec mask bits
48 //===----------------------------------------------------------------------===//
49 
50 #include "AMDGPU.h"
51 #include "GCNSubtarget.h"
53 #include "llvm/ADT/SmallSet.h"
57 
58 using namespace llvm;
59 
60 #define DEBUG_TYPE "si-lower-control-flow"
61 
62 static cl::opt<bool>
63 RemoveRedundantEndcf("amdgpu-remove-redundant-endcf",
64  cl::init(true), cl::ReallyHidden);
65 
66 namespace {
67 
68 class SILowerControlFlow : public MachineFunctionPass {
69 private:
70  const SIRegisterInfo *TRI = nullptr;
71  const SIInstrInfo *TII = nullptr;
72  LiveIntervals *LIS = nullptr;
73  MachineDominatorTree *MDT = nullptr;
74  MachineRegisterInfo *MRI = nullptr;
75  SetVector<MachineInstr*> LoweredEndCf;
76  DenseSet<Register> LoweredIf;
78 
79  const TargetRegisterClass *BoolRC = nullptr;
80  unsigned AndOpc;
81  unsigned OrOpc;
82  unsigned XorOpc;
83  unsigned MovTermOpc;
84  unsigned Andn2TermOpc;
85  unsigned XorTermrOpc;
86  unsigned OrTermrOpc;
87  unsigned OrSaveExecOpc;
88  unsigned Exec;
89 
90  bool hasKill(const MachineBasicBlock *Begin, const MachineBasicBlock *End);
91 
92  void emitIf(MachineInstr &MI);
93  void emitElse(MachineInstr &MI);
94  void emitIfBreak(MachineInstr &MI);
95  void emitLoop(MachineInstr &MI);
96 
97  MachineBasicBlock *emitEndCf(MachineInstr &MI);
98 
99  void lowerInitExec(MachineBasicBlock *MBB, MachineInstr &MI);
100 
101  void findMaskOperands(MachineInstr &MI, unsigned OpNo,
103 
104  void combineMasks(MachineInstr &MI);
105 
106  bool removeMBBifRedundant(MachineBasicBlock &MBB);
107 
108  MachineBasicBlock *process(MachineInstr &MI);
109 
110  // Skip to the next instruction, ignoring debug instructions, and trivial
111  // block boundaries (blocks that have one (typically fallthrough) successor,
112  // and the successor has one predecessor.
114  skipIgnoreExecInstsTrivialSucc(MachineBasicBlock &MBB,
115  MachineBasicBlock::iterator It) const;
116 
117  /// Find the insertion point for a new conditional branch.
119  skipToUncondBrOrEnd(MachineBasicBlock &MBB,
121  assert(I->isTerminator());
122 
123  // FIXME: What if we had multiple pre-existing conditional branches?
125  while (I != End && !I->isUnconditionalBranch())
126  ++I;
127  return I;
128  }
129 
130  // Remove redundant SI_END_CF instructions.
131  void optimizeEndCf();
132 
133 public:
134  static char ID;
135 
136  SILowerControlFlow() : MachineFunctionPass(ID) {}
137 
138  bool runOnMachineFunction(MachineFunction &MF) override;
139 
140  StringRef getPassName() const override {
141  return "SI Lower control flow pseudo instructions";
142  }
143 
144  void getAnalysisUsage(AnalysisUsage &AU) const override {
145  // Should preserve the same set that TwoAddressInstructions does.
151  }
152 };
153 
154 } // end anonymous namespace
155 
156 char SILowerControlFlow::ID = 0;
157 
158 INITIALIZE_PASS(SILowerControlFlow, DEBUG_TYPE,
159  "SI lower control flow", false, false)
160 
161 static void setImpSCCDefDead(MachineInstr &MI, bool IsDead) {
162  MachineOperand &ImpDefSCC = MI.getOperand(3);
163  assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
164 
165  ImpDefSCC.setIsDead(IsDead);
166 }
167 
169 
170 bool SILowerControlFlow::hasKill(const MachineBasicBlock *Begin,
171  const MachineBasicBlock *End) {
174 
175  while (!Worklist.empty()) {
176  MachineBasicBlock *MBB = Worklist.pop_back_val();
177 
178  if (MBB == End || !Visited.insert(MBB).second)
179  continue;
180  if (KillBlocks.contains(MBB))
181  return true;
182 
183  Worklist.append(MBB->succ_begin(), MBB->succ_end());
184  }
185 
186  return false;
187 }
188 
189 static bool isSimpleIf(const MachineInstr &MI, const MachineRegisterInfo *MRI) {
190  Register SaveExecReg = MI.getOperand(0).getReg();
191  auto U = MRI->use_instr_nodbg_begin(SaveExecReg);
192 
193  if (U == MRI->use_instr_nodbg_end() ||
194  std::next(U) != MRI->use_instr_nodbg_end() ||
195  U->getOpcode() != AMDGPU::SI_END_CF)
196  return false;
197 
198  return true;
199 }
200 
201 void SILowerControlFlow::emitIf(MachineInstr &MI) {
202  MachineBasicBlock &MBB = *MI.getParent();
203  const DebugLoc &DL = MI.getDebugLoc();
205  Register SaveExecReg = MI.getOperand(0).getReg();
206  MachineOperand& Cond = MI.getOperand(1);
207  assert(Cond.getSubReg() == AMDGPU::NoSubRegister);
208 
209  MachineOperand &ImpDefSCC = MI.getOperand(4);
210  assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
211 
212  // If there is only one use of save exec register and that use is SI_END_CF,
213  // we can optimize SI_IF by returning the full saved exec mask instead of
214  // just cleared bits.
215  bool SimpleIf = isSimpleIf(MI, MRI);
216 
217  if (SimpleIf) {
218  // Check for SI_KILL_*_TERMINATOR on path from if to endif.
219  // if there is any such terminator simplifications are not safe.
220  auto UseMI = MRI->use_instr_nodbg_begin(SaveExecReg);
221  SimpleIf = !hasKill(MI.getParent(), UseMI->getParent());
222  }
223 
224  // Add an implicit def of exec to discourage scheduling VALU after this which
225  // will interfere with trying to form s_and_saveexec_b64 later.
226  Register CopyReg = SimpleIf ? SaveExecReg
227  : MRI->createVirtualRegister(BoolRC);
228  MachineInstr *CopyExec =
229  BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
230  .addReg(Exec)
232  LoweredIf.insert(CopyReg);
233 
234  Register Tmp = MRI->createVirtualRegister(BoolRC);
235 
236  MachineInstr *And =
237  BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp)
238  .addReg(CopyReg)
239  .add(Cond);
240 
241  setImpSCCDefDead(*And, true);
242 
243  MachineInstr *Xor = nullptr;
244  if (!SimpleIf) {
245  Xor =
246  BuildMI(MBB, I, DL, TII->get(XorOpc), SaveExecReg)
247  .addReg(Tmp)
248  .addReg(CopyReg);
249  setImpSCCDefDead(*Xor, ImpDefSCC.isDead());
250  }
251 
252  // Use a copy that is a terminator to get correct spill code placement it with
253  // fast regalloc.
254  MachineInstr *SetExec =
255  BuildMI(MBB, I, DL, TII->get(MovTermOpc), Exec)
256  .addReg(Tmp, RegState::Kill);
257 
258  // Skip ahead to the unconditional branch in case there are other terminators
259  // present.
260  I = skipToUncondBrOrEnd(MBB, I);
261 
262  // Insert the S_CBRANCH_EXECZ instruction which will be optimized later
263  // during SIRemoveShortExecBranches.
264  MachineInstr *NewBr = BuildMI(MBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
265  .add(MI.getOperand(2));
266 
267  if (!LIS) {
268  MI.eraseFromParent();
269  return;
270  }
271 
272  LIS->InsertMachineInstrInMaps(*CopyExec);
273 
274  // Replace with and so we don't need to fix the live interval for condition
275  // register.
276  LIS->ReplaceMachineInstrInMaps(MI, *And);
277 
278  if (!SimpleIf)
279  LIS->InsertMachineInstrInMaps(*Xor);
280  LIS->InsertMachineInstrInMaps(*SetExec);
281  LIS->InsertMachineInstrInMaps(*NewBr);
282 
283  LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
284  MI.eraseFromParent();
285 
286  // FIXME: Is there a better way of adjusting the liveness? It shouldn't be
287  // hard to add another def here but I'm not sure how to correctly update the
288  // valno.
289  LIS->removeInterval(SaveExecReg);
290  LIS->createAndComputeVirtRegInterval(SaveExecReg);
292  if (!SimpleIf)
293  LIS->createAndComputeVirtRegInterval(CopyReg);
294 }
295 
296 void SILowerControlFlow::emitElse(MachineInstr &MI) {
297  MachineBasicBlock &MBB = *MI.getParent();
298  const DebugLoc &DL = MI.getDebugLoc();
299 
300  Register DstReg = MI.getOperand(0).getReg();
301 
303 
304  // This must be inserted before phis and any spill code inserted before the
305  // else.
306  Register SaveReg = MRI->createVirtualRegister(BoolRC);
307  MachineInstr *OrSaveExec =
308  BuildMI(MBB, Start, DL, TII->get(OrSaveExecOpc), SaveReg)
309  .add(MI.getOperand(1)); // Saved EXEC
310 
311  MachineBasicBlock *DestBB = MI.getOperand(2).getMBB();
312 
314 
315  // This accounts for any modification of the EXEC mask within the block and
316  // can be optimized out pre-RA when not required.
317  MachineInstr *And = BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg)
318  .addReg(Exec)
319  .addReg(SaveReg);
320 
321  if (LIS)
322  LIS->InsertMachineInstrInMaps(*And);
323 
324  MachineInstr *Xor =
325  BuildMI(MBB, ElsePt, DL, TII->get(XorTermrOpc), Exec)
326  .addReg(Exec)
327  .addReg(DstReg);
328 
329  // Skip ahead to the unconditional branch in case there are other terminators
330  // present.
331  ElsePt = skipToUncondBrOrEnd(MBB, ElsePt);
332 
334  BuildMI(MBB, ElsePt, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
335  .addMBB(DestBB);
336 
337  if (!LIS) {
338  MI.eraseFromParent();
339  return;
340  }
341 
343  MI.eraseFromParent();
344 
345  LIS->InsertMachineInstrInMaps(*OrSaveExec);
346 
347  LIS->InsertMachineInstrInMaps(*Xor);
349 
350  LIS->removeInterval(DstReg);
351  LIS->createAndComputeVirtRegInterval(DstReg);
352  LIS->createAndComputeVirtRegInterval(SaveReg);
353 
354  // Let this be recomputed.
355  LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
356 }
357 
358 void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {
359  MachineBasicBlock &MBB = *MI.getParent();
360  const DebugLoc &DL = MI.getDebugLoc();
361  auto Dst = MI.getOperand(0).getReg();
362 
363  // Skip ANDing with exec if the break condition is already masked by exec
364  // because it is a V_CMP in the same basic block. (We know the break
365  // condition operand was an i1 in IR, so if it is a VALU instruction it must
366  // be one with a carry-out.)
367  bool SkipAnding = false;
368  if (MI.getOperand(1).isReg()) {
369  if (MachineInstr *Def = MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) {
370  SkipAnding = Def->getParent() == MI.getParent()
372  }
373  }
374 
375  // AND the break condition operand with exec, then OR that into the "loop
376  // exit" mask.
377  MachineInstr *And = nullptr, *Or = nullptr;
378  if (!SkipAnding) {
379  Register AndReg = MRI->createVirtualRegister(BoolRC);
380  And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg)
381  .addReg(Exec)
382  .add(MI.getOperand(1));
383  Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
384  .addReg(AndReg)
385  .add(MI.getOperand(2));
386  if (LIS)
387  LIS->createAndComputeVirtRegInterval(AndReg);
388  } else
389  Or = BuildMI(MBB, &MI, DL, TII->get(OrOpc), Dst)
390  .add(MI.getOperand(1))
391  .add(MI.getOperand(2));
392 
393  if (LIS) {
394  if (And)
395  LIS->InsertMachineInstrInMaps(*And);
396  LIS->ReplaceMachineInstrInMaps(MI, *Or);
397  }
398 
399  MI.eraseFromParent();
400 }
401 
402 void SILowerControlFlow::emitLoop(MachineInstr &MI) {
403  MachineBasicBlock &MBB = *MI.getParent();
404  const DebugLoc &DL = MI.getDebugLoc();
405 
406  MachineInstr *AndN2 =
407  BuildMI(MBB, &MI, DL, TII->get(Andn2TermOpc), Exec)
408  .addReg(Exec)
409  .add(MI.getOperand(0));
410 
411  auto BranchPt = skipToUncondBrOrEnd(MBB, MI.getIterator());
413  BuildMI(MBB, BranchPt, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
414  .add(MI.getOperand(1));
415 
416  if (LIS) {
417  LIS->ReplaceMachineInstrInMaps(MI, *AndN2);
419  }
420 
421  MI.eraseFromParent();
422 }
423 
425 SILowerControlFlow::skipIgnoreExecInstsTrivialSucc(
427 
429  MachineBasicBlock *B = &MBB;
430  do {
431  if (!Visited.insert(B).second)
432  return MBB.end();
433 
434  auto E = B->end();
435  for ( ; It != E; ++It) {
436  if (TII->mayReadEXEC(*MRI, *It))
437  break;
438  }
439 
440  if (It != E)
441  return It;
442 
443  if (B->succ_size() != 1)
444  return MBB.end();
445 
446  // If there is one trivial successor, advance to the next block.
447  MachineBasicBlock *Succ = *B->succ_begin();
448 
449  It = Succ->begin();
450  B = Succ;
451  } while (true);
452 }
453 
454 MachineBasicBlock *SILowerControlFlow::emitEndCf(MachineInstr &MI) {
455  MachineBasicBlock &MBB = *MI.getParent();
456  const DebugLoc &DL = MI.getDebugLoc();
457 
459 
460  // If we have instructions that aren't prolog instructions, split the block
461  // and emit a terminator instruction. This ensures correct spill placement.
462  // FIXME: We should unconditionally split the block here.
463  bool NeedBlockSplit = false;
464  Register DataReg = MI.getOperand(0).getReg();
465  for (MachineBasicBlock::iterator I = InsPt, E = MI.getIterator();
466  I != E; ++I) {
467  if (I->modifiesRegister(DataReg, TRI)) {
468  NeedBlockSplit = true;
469  break;
470  }
471  }
472 
473  unsigned Opcode = OrOpc;
474  MachineBasicBlock *SplitBB = &MBB;
475  if (NeedBlockSplit) {
476  SplitBB = MBB.splitAt(MI, /*UpdateLiveIns*/true, LIS);
477  if (MDT && SplitBB != &MBB) {
478  MachineDomTreeNode *MBBNode = (*MDT)[&MBB];
479  SmallVector<MachineDomTreeNode *> Children(MBBNode->begin(),
480  MBBNode->end());
481  MachineDomTreeNode *SplitBBNode = MDT->addNewBlock(SplitBB, &MBB);
482  for (MachineDomTreeNode *Child : Children)
483  MDT->changeImmediateDominator(Child, SplitBBNode);
484  }
485  Opcode = OrTermrOpc;
486  InsPt = MI;
487  }
488 
489  MachineInstr *NewMI =
490  BuildMI(MBB, InsPt, DL, TII->get(Opcode), Exec)
491  .addReg(Exec)
492  .add(MI.getOperand(0));
493 
494  LoweredEndCf.insert(NewMI);
495 
496  if (LIS)
497  LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
498 
499  MI.eraseFromParent();
500 
501  if (LIS)
502  LIS->handleMove(*NewMI);
503  return SplitBB;
504 }
505 
506 // Returns replace operands for a logical operation, either single result
507 // for exec or two operands if source was another equivalent operation.
508 void SILowerControlFlow::findMaskOperands(MachineInstr &MI, unsigned OpNo,
509  SmallVectorImpl<MachineOperand> &Src) const {
510  MachineOperand &Op = MI.getOperand(OpNo);
511  if (!Op.isReg() || !Op.getReg().isVirtual()) {
512  Src.push_back(Op);
513  return;
514  }
515 
516  MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
517  if (!Def || Def->getParent() != MI.getParent() ||
518  !(Def->isFullCopy() || (Def->getOpcode() == MI.getOpcode())))
519  return;
520 
521  // Make sure we do not modify exec between def and use.
522  // A copy with implcitly defined exec inserted earlier is an exclusion, it
523  // does not really modify exec.
524  for (auto I = Def->getIterator(); I != MI.getIterator(); ++I)
525  if (I->modifiesRegister(AMDGPU::EXEC, TRI) &&
526  !(I->isCopy() && I->getOperand(0).getReg() != Exec))
527  return;
528 
529  for (const auto &SrcOp : Def->explicit_operands())
530  if (SrcOp.isReg() && SrcOp.isUse() &&
531  (SrcOp.getReg().isVirtual() || SrcOp.getReg() == Exec))
532  Src.push_back(SrcOp);
533 }
534 
535 // Search and combine pairs of equivalent instructions, like
536 // S_AND_B64 x, (S_AND_B64 x, y) => S_AND_B64 x, y
537 // S_OR_B64 x, (S_OR_B64 x, y) => S_OR_B64 x, y
538 // One of the operands is exec mask.
539 void SILowerControlFlow::combineMasks(MachineInstr &MI) {
540  assert(MI.getNumExplicitOperands() == 3);
542  unsigned OpToReplace = 1;
543  findMaskOperands(MI, 1, Ops);
544  if (Ops.size() == 1) OpToReplace = 2; // First operand can be exec or its copy
545  findMaskOperands(MI, 2, Ops);
546  if (Ops.size() != 3) return;
547 
548  unsigned UniqueOpndIdx;
549  if (Ops[0].isIdenticalTo(Ops[1])) UniqueOpndIdx = 2;
550  else if (Ops[0].isIdenticalTo(Ops[2])) UniqueOpndIdx = 1;
551  else if (Ops[1].isIdenticalTo(Ops[2])) UniqueOpndIdx = 1;
552  else return;
553 
554  Register Reg = MI.getOperand(OpToReplace).getReg();
555  MI.RemoveOperand(OpToReplace);
556  MI.addOperand(Ops[UniqueOpndIdx]);
557  if (MRI->use_empty(Reg))
559 }
560 
561 void SILowerControlFlow::optimizeEndCf() {
562  // If the only instruction immediately following this END_CF is an another
563  // END_CF in the only successor we can avoid emitting exec mask restore here.
565  return;
566 
567  for (MachineInstr *MI : LoweredEndCf) {
568  MachineBasicBlock &MBB = *MI->getParent();
569  auto Next =
570  skipIgnoreExecInstsTrivialSucc(MBB, std::next(MI->getIterator()));
571  if (Next == MBB.end() || !LoweredEndCf.count(&*Next))
572  continue;
573  // Only skip inner END_CF if outer ENDCF belongs to SI_IF.
574  // If that belongs to SI_ELSE then saved mask has an inverted value.
575  Register SavedExec
576  = TII->getNamedOperand(*Next, AMDGPU::OpName::src1)->getReg();
577  assert(SavedExec.isVirtual() && "Expected saved exec to be src1!");
578 
579  const MachineInstr *Def = MRI->getUniqueVRegDef(SavedExec);
580  if (Def && LoweredIf.count(SavedExec)) {
581  LLVM_DEBUG(dbgs() << "Skip redundant "; MI->dump());
582  if (LIS)
584  MI->eraseFromParent();
585  removeMBBifRedundant(MBB);
586  }
587  }
588 }
589 
590 MachineBasicBlock *SILowerControlFlow::process(MachineInstr &MI) {
591  MachineBasicBlock &MBB = *MI.getParent();
593  MachineInstr *Prev = (I != MBB.begin()) ? &*(std::prev(I)) : nullptr;
594 
595  MachineBasicBlock *SplitBB = &MBB;
596 
597  switch (MI.getOpcode()) {
598  case AMDGPU::SI_IF:
599  emitIf(MI);
600  break;
601 
602  case AMDGPU::SI_ELSE:
603  emitElse(MI);
604  break;
605 
606  case AMDGPU::SI_IF_BREAK:
607  emitIfBreak(MI);
608  break;
609 
610  case AMDGPU::SI_LOOP:
611  emitLoop(MI);
612  break;
613 
614  case AMDGPU::SI_WATERFALL_LOOP:
615  MI.setDesc(TII->get(AMDGPU::S_CBRANCH_EXECNZ));
616  break;
617 
618  case AMDGPU::SI_END_CF:
619  SplitBB = emitEndCf(MI);
620  break;
621 
622  default:
623  assert(false && "Attempt to process unsupported instruction");
624  break;
625  }
626 
628  for (I = Prev ? Prev->getIterator() : MBB.begin(); I != MBB.end(); I = Next) {
629  Next = std::next(I);
630  MachineInstr &MaskMI = *I;
631  switch (MaskMI.getOpcode()) {
632  case AMDGPU::S_AND_B64:
633  case AMDGPU::S_OR_B64:
634  case AMDGPU::S_AND_B32:
635  case AMDGPU::S_OR_B32:
636  // Cleanup bit manipulations on exec mask
637  combineMasks(MaskMI);
638  break;
639  default:
640  I = MBB.end();
641  break;
642  }
643  }
644 
645  return SplitBB;
646 }
647 
648 void SILowerControlFlow::lowerInitExec(MachineBasicBlock *MBB,
649  MachineInstr &MI) {
650  MachineFunction &MF = *MBB->getParent();
651  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
652  bool IsWave32 = ST.isWave32();
653 
654  if (MI.getOpcode() == AMDGPU::SI_INIT_EXEC) {
655  // This should be before all vector instructions.
656  BuildMI(*MBB, MBB->begin(), MI.getDebugLoc(),
657  TII->get(IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), Exec)
658  .addImm(MI.getOperand(0).getImm());
659  if (LIS)
661  MI.eraseFromParent();
662  return;
663  }
664 
665  // Extract the thread count from an SGPR input and set EXEC accordingly.
666  // Since BFM can't shift by 64, handle that case with CMP + CMOV.
667  //
668  // S_BFE_U32 count, input, {shift, 7}
669  // S_BFM_B64 exec, count, 0
670  // S_CMP_EQ_U32 count, 64
671  // S_CMOV_B64 exec, -1
672  Register InputReg = MI.getOperand(0).getReg();
673  MachineInstr *FirstMI = &*MBB->begin();
674  if (InputReg.isVirtual()) {
675  MachineInstr *DefInstr = MRI->getVRegDef(InputReg);
676  assert(DefInstr && DefInstr->isCopy());
677  if (DefInstr->getParent() == MBB) {
678  if (DefInstr != FirstMI) {
679  // If the `InputReg` is defined in current block, we also need to
680  // move that instruction to the beginning of the block.
681  DefInstr->removeFromParent();
682  MBB->insert(FirstMI, DefInstr);
683  if (LIS)
684  LIS->handleMove(*DefInstr);
685  } else {
686  // If first instruction is definition then move pointer after it.
687  FirstMI = &*std::next(FirstMI->getIterator());
688  }
689  }
690  }
691 
692  // Insert instruction sequence at block beginning (before vector operations).
693  const DebugLoc DL = MI.getDebugLoc();
694  const unsigned WavefrontSize = ST.getWavefrontSize();
695  const unsigned Mask = (WavefrontSize << 1) - 1;
696  Register CountReg = MRI->createVirtualRegister(&AMDGPU::SGPR_32RegClass);
697  auto BfeMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_BFE_U32), CountReg)
698  .addReg(InputReg)
699  .addImm((MI.getOperand(1).getImm() & Mask) | 0x70000);
700  auto BfmMI =
701  BuildMI(*MBB, FirstMI, DL,
702  TII->get(IsWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64), Exec)
703  .addReg(CountReg)
704  .addImm(0);
705  auto CmpMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_CMP_EQ_U32))
706  .addReg(CountReg, RegState::Kill)
708  auto CmovMI =
709  BuildMI(*MBB, FirstMI, DL,
710  TII->get(IsWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
711  Exec)
712  .addImm(-1);
713 
714  if (!LIS) {
715  MI.eraseFromParent();
716  return;
717  }
718 
720  MI.eraseFromParent();
721 
722  LIS->InsertMachineInstrInMaps(*BfeMI);
723  LIS->InsertMachineInstrInMaps(*BfmMI);
724  LIS->InsertMachineInstrInMaps(*CmpMI);
725  LIS->InsertMachineInstrInMaps(*CmovMI);
726 
727  LIS->removeInterval(InputReg);
728  LIS->createAndComputeVirtRegInterval(InputReg);
729  LIS->createAndComputeVirtRegInterval(CountReg);
730 }
731 
732 bool SILowerControlFlow::removeMBBifRedundant(MachineBasicBlock &MBB) {
733  auto GetFallThroughSucc = [=](MachineBasicBlock *B) -> MachineBasicBlock * {
734  auto *S = B->getNextNode();
735  if (!S)
736  return nullptr;
737  if (B->isSuccessor(S)) {
738  // The only fallthrough candidate
739  MachineBasicBlock::iterator I(B->getFirstInstrTerminator());
741  for (; I != E; I++) {
742  if (I->isBranch() && TII->getBranchDestBlock(*I) == S)
743  // We have unoptimized branch to layout successor
744  return nullptr;
745  }
746  }
747  return S;
748  };
749 
750  for (auto &I : MBB.instrs()) {
751  if (!I.isDebugInstr() && !I.isUnconditionalBranch())
752  return false;
753  }
754 
755  assert(MBB.succ_size() == 1 && "MBB has more than one successor");
756 
757  MachineBasicBlock *Succ = *MBB.succ_begin();
758  MachineBasicBlock *FallThrough = nullptr;
759 
760  while (!MBB.predecessors().empty()) {
762  if (GetFallThroughSucc(P) == &MBB)
763  FallThrough = P;
764  P->ReplaceUsesOfBlockWith(&MBB, Succ);
765  }
766  MBB.removeSuccessor(Succ);
767  if (LIS) {
768  for (auto &I : MBB.instrs())
770  }
771  if (MDT) {
772  // If Succ, the single successor of MBB, is dominated by MBB, MDT needs
773  // updating by changing Succ's idom to the one of MBB; otherwise, MBB must
774  // be a leaf node in MDT and could be erased directly.
775  if (MDT->dominates(&MBB, Succ))
776  MDT->changeImmediateDominator(MDT->getNode(Succ),
777  MDT->getNode(&MBB)->getIDom());
778  MDT->eraseNode(&MBB);
779  }
780  MBB.clear();
782  if (FallThrough && !FallThrough->isLayoutSuccessor(Succ)) {
783  if (!GetFallThroughSucc(Succ)) {
784  MachineFunction *MF = FallThrough->getParent();
785  MachineFunction::iterator FallThroughPos(FallThrough);
786  MF->splice(std::next(FallThroughPos), Succ);
787  } else
788  BuildMI(*FallThrough, FallThrough->end(),
789  FallThrough->findBranchDebugLoc(), TII->get(AMDGPU::S_BRANCH))
790  .addMBB(Succ);
791  }
792 
793  return true;
794 }
795 
796 bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
797  // FIXME: This pass causes verification failures.
798  // See: https://bugs.llvm.org/show_bug.cgi?id=52204
799  MF.getProperties().set(
801 
802  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
803  TII = ST.getInstrInfo();
804  TRI = &TII->getRegisterInfo();
805 
806  // This doesn't actually need LiveIntervals, but we can preserve them.
807  LIS = getAnalysisIfAvailable<LiveIntervals>();
808  MDT = getAnalysisIfAvailable<MachineDominatorTree>();
809  MRI = &MF.getRegInfo();
810  BoolRC = TRI->getBoolRC();
811 
812  if (ST.isWave32()) {
813  AndOpc = AMDGPU::S_AND_B32;
814  OrOpc = AMDGPU::S_OR_B32;
815  XorOpc = AMDGPU::S_XOR_B32;
816  MovTermOpc = AMDGPU::S_MOV_B32_term;
817  Andn2TermOpc = AMDGPU::S_ANDN2_B32_term;
818  XorTermrOpc = AMDGPU::S_XOR_B32_term;
819  OrTermrOpc = AMDGPU::S_OR_B32_term;
820  OrSaveExecOpc = AMDGPU::S_OR_SAVEEXEC_B32;
821  Exec = AMDGPU::EXEC_LO;
822  } else {
823  AndOpc = AMDGPU::S_AND_B64;
824  OrOpc = AMDGPU::S_OR_B64;
825  XorOpc = AMDGPU::S_XOR_B64;
826  MovTermOpc = AMDGPU::S_MOV_B64_term;
827  Andn2TermOpc = AMDGPU::S_ANDN2_B64_term;
828  XorTermrOpc = AMDGPU::S_XOR_B64_term;
829  OrTermrOpc = AMDGPU::S_OR_B64_term;
830  OrSaveExecOpc = AMDGPU::S_OR_SAVEEXEC_B64;
831  Exec = AMDGPU::EXEC;
832  }
833 
834  // Compute set of blocks with kills
835  const bool CanDemote =
837  for (auto &MBB : MF) {
838  bool IsKillBlock = false;
839  for (auto &Term : MBB.terminators()) {
840  if (TII->isKillTerminator(Term.getOpcode())) {
841  KillBlocks.insert(&MBB);
842  IsKillBlock = true;
843  break;
844  }
845  }
846  if (CanDemote && !IsKillBlock) {
847  for (auto &MI : MBB) {
848  if (MI.getOpcode() == AMDGPU::SI_DEMOTE_I1) {
849  KillBlocks.insert(&MBB);
850  break;
851  }
852  }
853  }
854  }
855 
857  for (MachineFunction::iterator BI = MF.begin();
858  BI != MF.end(); BI = NextBB) {
859  NextBB = std::next(BI);
860  MachineBasicBlock *MBB = &*BI;
861 
863  E = MBB->end();
864  for (I = MBB->begin(); I != E; I = Next) {
865  Next = std::next(I);
866  MachineInstr &MI = *I;
867  MachineBasicBlock *SplitMBB = MBB;
868 
869  switch (MI.getOpcode()) {
870  case AMDGPU::SI_IF:
871  case AMDGPU::SI_ELSE:
872  case AMDGPU::SI_IF_BREAK:
873  case AMDGPU::SI_WATERFALL_LOOP:
874  case AMDGPU::SI_LOOP:
875  case AMDGPU::SI_END_CF:
876  SplitMBB = process(MI);
877  break;
878 
879  // FIXME: find a better place for this
880  case AMDGPU::SI_INIT_EXEC:
881  case AMDGPU::SI_INIT_EXEC_FROM_INPUT:
882  lowerInitExec(MBB, MI);
883  if (LIS)
884  LIS->removeAllRegUnitsForPhysReg(AMDGPU::EXEC);
885  break;
886 
887  default:
888  break;
889  }
890 
891  if (SplitMBB != MBB) {
892  MBB = Next->getParent();
893  E = MBB->end();
894  }
895  }
896  }
897 
898  optimizeEndCf();
899 
900  LoweredEndCf.clear();
901  LoweredIf.clear();
902  KillBlocks.clear();
903 
904  return true;
905 }
llvm::MachineBasicBlock::succ_size
unsigned succ_size() const
Definition: MachineBasicBlock.h:344
IsDead
bool IsDead
Definition: SILowerControlFlow.cpp:161
llvm::MachineBasicBlock::pred_begin
pred_iterator pred_begin()
Definition: MachineBasicBlock.h:316
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
llvm::MachineInstrBuilder::addImm
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
Definition: MachineInstrBuilder.h:131
llvm
This file implements support for optimizing divisions by a constant.
Definition: AllocatorList.h:23
llvm::tgtok::Def
@ Def
Definition: TGLexer.h:50
Reg
unsigned Reg
Definition: MachineSink.cpp:1566
llvm::MachineRegisterInfo::use_instr_nodbg_end
static use_instr_nodbg_iterator use_instr_nodbg_end()
Definition: MachineRegisterInfo.h:538
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:102
llvm::RecurKind::Or
@ Or
Bitwise or logical OR of integers.
llvm::MachineRegisterInfo::createVirtualRegister
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
Definition: MachineRegisterInfo.cpp:158
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:52
llvm::MachineInstrBuilder::add
const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
P
This currently compiles esp xmm0 movsd esp eax eax esp ret We should use not the dag combiner This is because dagcombine2 needs to be able to see through the X86ISD::Wrapper which DAGCombine can t really do The code for turning x load into a single vector load is target independent and should be moved to the dag combiner The code for turning x load into a vector load can only handle a direct load from a global or a direct load from the stack It should be generalized to handle any load from P
Definition: README-SSE.txt:411
llvm::MachineBasicBlock::instrs
instr_range instrs()
Definition: MachineBasicBlock.h:263
llvm::MachineBasicBlock::clear
void clear()
Definition: MachineBasicBlock.h:942
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
INITIALIZE_PASS
INITIALIZE_PASS(SILowerControlFlow, DEBUG_TYPE, "SI lower control flow", false, false) static void setImpSCCDefDead(MachineInstr &MI
llvm::MachineRegisterInfo::getUniqueVRegDef
MachineInstr * getUniqueVRegDef(Register Reg) const
getUniqueVRegDef - Return the unique machine instr that defines the specified virtual register or nul...
Definition: MachineRegisterInfo.cpp:411
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::MachineRegisterInfo::use_instr_nodbg_begin
use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const
Definition: MachineRegisterInfo.h:535
llvm::LiveIntervals::removeAllRegUnitsForPhysReg
void removeAllRegUnitsForPhysReg(MCRegister Reg)
Remove associated live ranges for the register units associated with Reg.
Definition: LiveIntervals.h:425
llvm::LiveIntervals::removeInterval
void removeInterval(Register Reg)
Interval removal.
Definition: LiveIntervals.h:145
llvm::SILowerControlFlowID
char & SILowerControlFlowID
Definition: SILowerControlFlow.cpp:168
llvm::CallingConv::AMDGPU_PS
@ AMDGPU_PS
Calling convention used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:210
llvm::SmallSet
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
Definition: SmallSet.h:134
llvm::MachineInstr::isCopy
bool isCopy() const
Definition: MachineInstr.h:1291
llvm::GCNSubtarget
Definition: GCNSubtarget.h:31
RemoveRedundantEndcf
static cl::opt< bool > RemoveRedundantEndcf("amdgpu-remove-redundant-endcf", cl::init(true), cl::ReallyHidden)
llvm::MachineDominatorTree::dominates
bool dominates(const MachineDomTreeNode *A, const MachineDomTreeNode *B) const
Definition: MachineDominators.h:109
llvm::SmallVectorImpl::pop_back_val
LLVM_NODISCARD T pop_back_val()
Definition: SmallVector.h:635
llvm::MachineBasicBlock::terminators
iterator_range< iterator > terminators()
Definition: MachineBasicBlock.h:288
llvm::DomTreeNodeBase::getIDom
DomTreeNodeBase * getIDom() const
Definition: GenericDomTree.h:89
llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::insert
std::pair< iterator, bool > insert(const ValueT &V)
Definition: DenseSet.h:206
llvm::BitmaskEnumDetail::Mask
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:80
llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::count
size_type count(const_arg_type_t< ValueT > V) const
Return 1 if the specified key is in the set, 0 otherwise.
Definition: DenseSet.h:97
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1567
llvm::cl::ReallyHidden
@ ReallyHidden
Definition: CommandLine.h:144
llvm::LiveIntervals::createAndComputeVirtRegInterval
LiveInterval & createAndComputeVirtRegInterval(Register Reg)
Definition: LiveIntervals.h:138
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
LLVM_DEBUG
#define LLVM_DEBUG(X)
Definition: Debug.h:101
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition: MachineInstrBuilder.h:48
llvm::LiveIntervals::handleMove
void handleMove(MachineInstr &MI, bool UpdateFlags=false)
Call this method to notify LiveIntervals that instruction MI has been moved within a basic block.
Definition: LiveIntervals.cpp:1512
llvm::dbgs
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:640
llvm::RecurKind::And
@ And
Bitwise or logical AND of integers.
llvm::MachineInstrBuilder::addMBB
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Definition: MachineInstrBuilder.h:146
llvm::MachineDominatorTree::addNewBlock
MachineDomTreeNode * addNewBlock(MachineBasicBlock *BB, MachineBasicBlock *DomBB)
addNewBlock - Add a new node to the dominator tree information.
Definition: MachineDominators.h:177
GCNSubtarget.h
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
llvm::SmallVectorImpl::append
void append(in_iter in_start, in_iter in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:648
llvm::MachineBasicBlock::succ_end
succ_iterator succ_end()
Definition: MachineBasicBlock.h:334
llvm::LiveIntervals::InsertMachineInstrInMaps
SlotIndex InsertMachineInstrInMaps(MachineInstr &MI)
Definition: LiveIntervals.h:266
DEBUG_TYPE
#define DEBUG_TYPE
Definition: SILowerControlFlow.cpp:60
llvm::MachineBasicBlock::eraseFromParent
void eraseFromParent()
This method unlinks 'this' from the containing function and deletes it.
Definition: MachineBasicBlock.cpp:1337
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::TargetRegisterClass
Definition: TargetRegisterInfo.h:46
llvm::MachineInstr::removeFromParent
MachineInstr * removeFromParent()
Unlink 'this' from the containing basic block, and return it without deleting it.
Definition: MachineInstr.cpp:670
llvm::MachineDominatorTree::changeImmediateDominator
void changeImmediateDominator(MachineBasicBlock *N, MachineBasicBlock *NewIDom)
changeImmediateDominator - This method is used to update the dominator tree information when a node's...
Definition: MachineDominators.h:186
llvm::MachineFunction::getProperties
const MachineFunctionProperties & getProperties() const
Get the function properties.
Definition: MachineFunction.h:721
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:129
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:49
llvm::MachineFunctionProperties::set
MachineFunctionProperties & set(Property P)
Definition: MachineFunction.h:173
llvm::MachineBasicBlock::splitAt
MachineBasicBlock * splitAt(MachineInstr &SplitInst, bool UpdateLiveIns=true, LiveIntervals *LIS=nullptr)
Split a basic block into 2 pieces at SplitPoint.
Definition: MachineBasicBlock.cpp:970
llvm::SlotIndexes
SlotIndexes pass.
Definition: SlotIndexes.h:314
llvm::SIRegisterInfo
Definition: SIRegisterInfo.h:30
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:400
llvm::MachineRegisterInfo::use_empty
bool use_empty(Register RegNo) const
use_empty - Return true if there are no instructions using the specified register.
Definition: MachineRegisterInfo.h:506
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:95
llvm::MachineFunctionProperties::Property::FailsVerification
@ FailsVerification
llvm::Register::isVirtual
bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
Definition: Register.h:91
llvm::DenseSet
Implements a dense probed hash-table based set.
Definition: DenseSet.h:268
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:630
llvm::cl::opt< bool >
AMDGPUMCTargetDesc.h
llvm::MachineOperand::setIsDead
void setIsDead(bool Val=true)
Definition: MachineOperand.h:506
llvm::RegState::ImplicitDefine
@ ImplicitDefine
Definition: MachineInstrBuilder.h:63
llvm::LiveIntervals::ReplaceMachineInstrInMaps
SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI)
Definition: LiveIntervals.h:280
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:64
LiveIntervals.h
llvm::Function::getCallingConv
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:240
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
llvm::MachineFunction::splice
void splice(iterator InsertPt, iterator MBBI)
Definition: MachineFunction.h:834
llvm::MachineDominatorTree::getNode
MachineDomTreeNode * getNode(MachineBasicBlock *BB) const
getNode - return the (Post)DominatorTree node for the specified basic block.
Definition: MachineDominators.h:169
llvm::MachineOperand::isDead
bool isDead() const
Definition: MachineOperand.h:385
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineBasicBlock::succ_begin
succ_iterator succ_begin()
Definition: MachineBasicBlock.h:332
llvm::MachineBasicBlock::getParent
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
Definition: MachineBasicBlock.h:225
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::MachineBasicBlock::predecessors
iterator_range< pred_iterator > predecessors()
Definition: MachineBasicBlock.h:349
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::SetVector::insert
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
llvm::detail::DenseSetImpl< ValueT, DenseMap< ValueT, detail::DenseSetEmpty, DenseMapInfo< ValueT >, detail::DenseSetPair< ValueT > >, DenseMapInfo< ValueT > >::clear
void clear()
Definition: DenseSet.h:92
llvm::AMDGPU::CPol::SCC
@ SCC
Definition: SIDefines.h:295
llvm::MachineDominatorTree::eraseNode
void eraseNode(MachineBasicBlock *BB)
eraseNode - Removes a node from the dominator tree.
Definition: MachineDominators.h:201
llvm::SrcOp::getReg
Register getReg() const
Definition: MachineIRBuilder.h:171
Cond
SmallVector< MachineOperand, 4 > Cond
Definition: BasicBlockSections.cpp:179
llvm::MachineBasicBlock::successors
iterator_range< succ_iterator > successors()
Definition: MachineBasicBlock.h:355
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
AMDGPU.h
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition: PassAnalysisSupport.h:88
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::MachineBasicBlock::findBranchDebugLoc
DebugLoc findBranchDebugLoc()
Find and return the merged DebugLoc of the branch instructions of the block.
Definition: MachineBasicBlock.cpp:1417
llvm::AnalysisUsage::addPreserved
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
Definition: PassAnalysisSupport.h:98
llvm::ilist_node_impl::getIterator
self_iterator getIterator()
Definition: ilist_node.h:81
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition: AArch64SLSHardening.cpp:76
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:375
llvm::DomTreeNodeBase::begin
iterator begin()
Definition: GenericDomTree.h:75
S
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
Definition: README.txt:210
llvm::SmallSet::insert
std::pair< NoneType, bool > insert(const T &V)
insert - Insert an element into the set if it isn't already there.
Definition: SmallSet.h:180
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:286
llvm::Pass::dump
void dump() const
Definition: Pass.cpp:131
llvm::DomTreeNodeBase
Base class for the actual dominator tree node.
Definition: LiveIntervalCalc.h:24
isSimpleIf
static bool isSimpleIf(const MachineInstr &MI, const MachineRegisterInfo *MRI)
Definition: SILowerControlFlow.cpp:189
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:596
llvm::MachineBasicBlock::removeSuccessor
void removeSuccessor(MachineBasicBlock *Succ, bool NormalizeSuccProbs=false)
Remove successor from the successors list of this MachineBasicBlock.
Definition: MachineBasicBlock.cpp:789
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:324
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1317
llvm::ilist_iterator
Iterator for intrusive lists based on ilist_node.
Definition: ilist_iterator.h:57
llvm::DomTreeNodeBase::end
iterator end()
Definition: GenericDomTree.h:76
llvm::MCID::Branch
@ Branch
Definition: MCInstrDesc.h:156
llvm::LiveIntervals
Definition: LiveIntervals.h:54
llvm::MachineBasicBlock::isLayoutSuccessor
bool isLayoutSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB will be emitted immediately after this block, such that if this bloc...
Definition: MachineBasicBlock.cpp:917
llvm::SIInstrInfo
Definition: SIInstrInfo.h:38
llvm::M68kBeads::Term
@ Term
Definition: M68kBaseInfo.h:71
llvm::MachineBasicBlock::begin
iterator begin()
Definition: MachineBasicBlock.h:268
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::SIInstrInfo::isVALU
static bool isVALU(const MachineInstr &MI)
Definition: SIInstrInfo.h:359
llvm::LiveIntervals::RemoveMachineInstrFromMaps
void RemoveMachineInstrFromMaps(MachineInstr &MI)
Definition: LiveIntervals.h:276
llvm::SmallSet::clear
void clear()
Definition: SmallSet.h:218
llvm::SmallVectorImpl
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::WavefrontSize
constexpr char WavefrontSize[]
Key for Kernel::CodeProps::Metadata::mWavefrontSize.
Definition: AMDGPUMetadata.h:251
llvm::DebugLoc
A debug info location.
Definition: DebugLoc.h:33
llvm::MachineDominatorTree
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
Definition: MachineDominators.h:45
llvm::SetVector
A vector that has set insertion semantics.
Definition: SetVector.h:40
llvm::MachineInstr::eraseFromParent
void eraseFromParent()
Unlink 'this' from the containing basic block and delete it.
Definition: MachineInstr.cpp:680
llvm::MachineInstrBundleIterator< MachineInstr >
llvm::MachineBasicBlock::end
iterator end()
Definition: MachineBasicBlock.h:270
llvm::SrcOp
Definition: MachineIRBuilder.h:119
llvm::RecurKind::Xor
@ Xor
Bitwise or logical XOR of integers.
llvm::SmallSet::contains
bool contains(const T &V) const
Check if the SmallSet contains the given element.
Definition: SmallSet.h:236
MachineDominators.h
SmallSet.h
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:37