#include "Target/AMDGPU/SIInstrInfo.h"

Inheritance diagram for llvm::SIInstrInfo:

Collaboration diagram for llvm::SIInstrInfo:

Public Types
enum	TargetOperandFlags { MO_MASK = 0xf , MO_NONE = 0 , MO_GOTPCREL = 1 , MO_GOTPCREL32 = 2 , MO_GOTPCREL32_LO = 2 , MO_GOTPCREL32_HI = 3 , MO_REL32 = 4 , MO_REL32_LO = 4 , MO_REL32_HI = 5 , MO_FAR_BRANCH_OFFSET = 6 , MO_ABS32_LO = 8 , MO_ABS32_HI = 9 }

Public Member Functions
unsigned	buildExtractSubReg (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass SuperRC, unsigned SubIdx, const TargetRegisterClass SubRC) const

MachineOperand	buildExtractSubRegOrImm (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass SuperRC, unsigned SubIdx, const TargetRegisterClass SubRC) const

	SIInstrInfo (const GCNSubtarget &ST)

const SIRegisterInfo &	getRegisterInfo () const

const GCNSubtarget &	getSubtarget () const

bool	isReallyTriviallyReMaterializable (const MachineInstr &MI) const override

bool	isIgnorableUse (const MachineOperand &MO) const override

bool	areLoadsFromSameBasePtr (SDNode Load0, SDNode Load1, int64_t &Offset0, int64_t &Offset1) const override

bool	getMemOperandsWithOffsetWidth (const MachineInstr &LdSt, SmallVectorImpl< const MachineOperand * > &BaseOps, int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, const TargetRegisterInfo *TRI) const final

bool	shouldClusterMemOps (ArrayRef< const MachineOperand * > BaseOps1, ArrayRef< const MachineOperand * > BaseOps2, unsigned NumLoads, unsigned NumBytes) const override

bool	shouldScheduleLoadsNear (SDNode Load0, SDNode Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override

void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const override

void	materializeImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, Register DestReg, int64_t Value) const

const TargetRegisterClass *	getPreferredSelectRegClass (unsigned Size) const

Register	insertNE (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const

Register	insertEQ (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register SrcReg, int Value) const

void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg) const override

void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI, Register VReg) const override

bool	expandPostRAPseudo (MachineInstr &MI) const override

std::pair< MachineInstr , MachineInstr >	expandMovDPP64 (MachineInstr &MI) const

unsigned	getMovOpcode (const TargetRegisterClass *DstRC) const

const MCInstrDesc &	getIndirectRegWriteMovRelPseudo (unsigned VecSize, unsigned EltSize, bool IsSGPR) const

const MCInstrDesc &	getIndirectGPRIDXPseudo (unsigned VecSize, bool IsIndirectSrc) const

LLVM_READONLY int	commuteOpcode (unsigned Opc) const

LLVM_READONLY int	commuteOpcode (const MachineInstr &MI) const

bool	findCommutedOpIndices (const MachineInstr &MI, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const override

bool	findCommutedOpIndices (const MCInstrDesc &Desc, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const

bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override

MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override

bool	hasDivergentBranch (const MachineBasicBlock *MBB) const
	Return whether the block terminate with divergent branch.

void	insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, MachineBasicBlock &RestoreBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS) const override

bool	analyzeBranchImpl (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const

bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override

unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override

bool	canInsertSelect (const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, Register DstReg, Register TrueReg, Register FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override

void	insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const override

void	insertVectorSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DstReg, ArrayRef< MachineOperand > Cond, Register TrueReg, Register FalseReg) const

bool	analyzeCompare (const MachineInstr &MI, Register &SrcReg, Register &SrcReg2, int64_t &CmpMask, int64_t &CmpValue) const override

bool	optimizeCompareInstr (MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask, int64_t CmpValue, const MachineRegisterInfo *MRI) const override

bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb) const override

void	removeModOperands (MachineInstr &MI) const

bool	FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, MachineRegisterInfo *MRI) const final

unsigned	getMachineCSELookAheadLimit () const override

MachineInstr *	convertToThreeAddress (MachineInstr &MI, LiveVariables LV, LiveIntervals LIS) const override

bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

bool	isSALU (uint16_t Opcode) const

bool	isVALU (uint16_t Opcode) const

bool	isVMEM (uint16_t Opcode) const

bool	isSOP1 (uint16_t Opcode) const

bool	isSOP2 (uint16_t Opcode) const

bool	isSOPC (uint16_t Opcode) const

bool	isSOPK (uint16_t Opcode) const

bool	isSOPP (uint16_t Opcode) const

bool	isPacked (uint16_t Opcode) const

bool	isVOP1 (uint16_t Opcode) const

bool	isVOP2 (uint16_t Opcode) const

bool	isVOP3 (uint16_t Opcode) const

bool	isSDWA (uint16_t Opcode) const

bool	isVOPC (uint16_t Opcode) const

bool	isMUBUF (uint16_t Opcode) const

bool	isMTBUF (uint16_t Opcode) const

bool	isSMRD (uint16_t Opcode) const

bool	isBufferSMRD (const MachineInstr &MI) const

bool	isDS (uint16_t Opcode) const

bool	isAlwaysGDS (uint16_t Opcode) const

bool	isMIMG (uint16_t Opcode) const

bool	isGather4 (uint16_t Opcode) const

bool	isSegmentSpecificFLAT (uint16_t Opcode) const

bool	isFLATGlobal (uint16_t Opcode) const

bool	isFLATScratch (uint16_t Opcode) const

bool	isFLAT (uint16_t Opcode) const

bool	isEXP (uint16_t Opcode) const

bool	isAtomicNoRet (uint16_t Opcode) const

bool	isAtomicRet (uint16_t Opcode) const

bool	isAtomic (uint16_t Opcode) const

bool	isWQM (uint16_t Opcode) const

bool	isDisableWQM (uint16_t Opcode) const

bool	isVGPRSpill (uint16_t Opcode) const

bool	isSGPRSpill (uint16_t Opcode) const

bool	isDPP (uint16_t Opcode) const

bool	isTRANS (uint16_t Opcode) const

bool	isVOP3P (uint16_t Opcode) const

bool	isVINTRP (uint16_t Opcode) const

bool	isMAI (uint16_t Opcode) const

bool	isWMMA (uint16_t Opcode) const

bool	isDOT (uint16_t Opcode) const

bool	isLDSDIR (uint16_t Opcode) const

bool	isVINTERP (uint16_t Opcode) const

bool	sopkIsZext (uint16_t Opcode) const

bool	isScalarStore (uint16_t Opcode) const

bool	isFixedSize (uint16_t Opcode) const

bool	hasFPClamp (uint16_t Opcode) const

uint64_t	getClampMask (const MachineInstr &MI) const

bool	usesFPDPRounding (uint16_t Opcode) const

bool	isFPAtomic (uint16_t Opcode) const

bool	doesNotReadTiedSource (uint16_t Opcode) const

bool	isVGPRCopy (const MachineInstr &MI) const

bool	hasVGPRUses (const MachineInstr &MI) const

bool	hasUnwantedEffectsWhenEXECEmpty (const MachineInstr &MI) const
	Whether we must prevent this instruction from executing with EXEC = 0.

bool	mayReadEXEC (const MachineRegisterInfo &MRI, const MachineInstr &MI) const
	Returns true if the instruction could potentially depend on the value of exec.

bool	isInlineConstant (const APInt &Imm) const

bool	isInlineConstant (const APFloat &Imm) const

bool	isInlineConstant (const MachineOperand &MO, uint8_t OperandType) const

bool	isInlineConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const

bool	isInlineConstant (const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
	`returns` true if `UseMO` is substituted with `DefMO` in `MI` it would be an inline immediate.

bool	isInlineConstant (const MachineInstr &MI, unsigned OpIdx) const
	`returns` true if the operand `OpIdx` in `MI` is a valid inline immediate.

bool	isInlineConstant (const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const

bool	isInlineConstant (const MachineOperand &MO) const

bool	isImmOperandLegal (const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const

bool	hasVALU32BitEncoding (unsigned Opcode) const
	Return true if this 64-bit VALU instruction has a 32-bit encoding.

bool	usesConstantBus (const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
	Returns true if this operand uses the constant bus.

bool	hasModifiers (unsigned Opcode) const
	Return true if this instruction has any modifiers.

bool	hasModifiersSet (const MachineInstr &MI, unsigned OpName) const

bool	hasAnyModifiersSet (const MachineInstr &MI) const

bool	canShrink (const MachineInstr &MI, const MachineRegisterInfo &MRI) const

MachineInstr *	buildShrunkInst (MachineInstr &MI, unsigned NewOpcode) const

bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override

unsigned	getVALUOp (const MachineInstr &MI) const

const TargetRegisterClass *	getOpRegClass (const MachineInstr &MI, unsigned OpNo) const
	Return the correct register class for `OpNo`.

unsigned	getOpSize (uint16_t Opcode, unsigned OpNo) const
	Return the size in bytes of the operand OpNo on the given.

unsigned	getOpSize (const MachineInstr &MI, unsigned OpNo) const
	This form should usually be preferred since it handles operands with unknown register classes.

void	legalizeOpWithMove (MachineInstr &MI, unsigned OpIdx) const
	Legalize the `OpIndex` operand of this instruction by inserting a MOV.

bool	isOperandLegal (const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
	Check if `MO` is a legal operand if it was the `OpIdx` Operand for `MI`.

bool	isLegalVSrcOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
	Check if `MO` would be a valid operand for the given operand definition `OpInfo`.

bool	isLegalRegOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
	Check if `MO` (a register operand) is a legal register for the given operand description.

void	legalizeOperandsVOP2 (MachineRegisterInfo &MRI, MachineInstr &MI) const
	Legalize operands in `MI` by either commuting it or inserting a copy of src1.

void	legalizeOperandsVOP3 (MachineRegisterInfo &MRI, MachineInstr &MI) const
	Fix operands in `MI` to satisfy constant bus requirements.

Register	readlaneVGPRToSGPR (Register SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
	Copy a value from a VGPR (`SrcReg`) to SGPR.

void	legalizeOperandsSMRD (MachineRegisterInfo &MRI, MachineInstr &MI) const

void	legalizeOperandsFLAT (MachineRegisterInfo &MRI, MachineInstr &MI) const

void	legalizeGenericOperand (MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const

MachineBasicBlock *	legalizeOperands (MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
	Legalize all operands in this instruction.

bool	moveFlatAddrToVGPR (MachineInstr &Inst) const
	Change SADDR form of a FLAT `Inst` to its VADDR form if saddr operand was moved to VGPR.

MachineBasicBlock *	moveToVALU (MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
	Replace this instruction's opcode with the equivalent VALU opcode.

void	insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

void	insertNoops (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Quantity) const override

void	insertReturn (MachineBasicBlock &MBB) const

LLVM_READONLY MachineOperand *	getNamedOperand (MachineInstr &MI, unsigned OperandName) const
	Returns the operand named `Op`.

LLVM_READONLY const MachineOperand *	getNamedOperand (const MachineInstr &MI, unsigned OpName) const

int64_t	getNamedImmOperand (const MachineInstr &MI, unsigned OpName) const
	Get required immediate operand.

uint64_t	getDefaultRsrcDataFormat () const

uint64_t	getScratchRsrcWords23 () const

bool	isLowLatencyInstruction (const MachineInstr &MI) const

bool	isHighLatencyDef (int Opc) const override

const MCInstrDesc &	getMCOpcodeFromPseudo (unsigned Opcode) const
	Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.

unsigned	isStackAccess (const MachineInstr &MI, int &FrameIndex) const

unsigned	isSGPRStackAccess (const MachineInstr &MI, int &FrameIndex) const

unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override

unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override

unsigned	getInstBundleSize (const MachineInstr &MI) const

unsigned	getInstSizeInBytes (const MachineInstr &MI) const override

bool	mayAccessFlatAddressSpace (const MachineInstr &MI) const

bool	isNonUniformBranchInstr (MachineInstr &Instr) const

void	convertNonUniformIfRegion (MachineBasicBlock IfEntry, MachineBasicBlock IfEnd) const

void	convertNonUniformLoopRegion (MachineBasicBlock LoopEntry, MachineBasicBlock LoopEnd) const

std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override

ArrayRef< std::pair< int, const char * > >	getSerializableTargetIndices () const override

ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > >	getSerializableMachineMemOperandTargetFlags () const override

ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData II, const ScheduleDAG DAG) const override
	This is used by the post-RA scheduler (SchedulePostRAList.cpp).

ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const override
	This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.

ScheduleHazardRecognizer *	CreateTargetMIHazardRecognizer (const InstrItineraryData II, const ScheduleDAGMI DAG) const override

bool	isBasicBlockPrologue (const MachineInstr &MI) const override

MachineInstr *	createPHIDestinationCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override

MachineInstr *	createPHISourceCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, unsigned SrcSubReg, Register Dst) const override

bool	isWave32 () const

MachineInstrBuilder	getAddNoCarry (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg) const
	Return a partially built integer add instruction without carry.

MachineInstrBuilder	getAddNoCarry (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, RegScavenger &RS) const

const MCInstrDesc &	getKillTerminatorFromPseudo (unsigned Opcode) const

bool	isLegalFLATOffset (int64_t Offset, unsigned AddrSpace, uint64_t FlatVariant) const
	Returns if `Offset` is legal for the subtarget as the offset to a FLAT encoded instruction.

std::pair< int64_t, int64_t >	splitFlatOffset (int64_t COffsetVal, unsigned AddrSpace, uint64_t FlatVariant) const
	Split `COffsetVal` into {immediate offset field, remainder offset} values.

int	pseudoToMCOpcode (int Opcode) const
	Return a target-specific opcode if Opcode is a pseudo instruction.

bool	isAsmOnlyOpcode (int MCOp) const
	Check if this instruction should only be used by assembler.

const TargetRegisterClass *	getRegClass (const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override

void	fixImplicitOperands (MachineInstr &MI) const

MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr &MI, ArrayRef< unsigned > Ops, MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals LIS=nullptr, VirtRegMap VRM=nullptr) const override

unsigned	getInstrLatency (const InstrItineraryData ItinData, const MachineInstr &MI, unsigned PredCost=nullptr) const override

InstructionUniformity	getInstructionUniformity (const MachineInstr &MI) const override final

InstructionUniformity	getGenericInstructionUniformity (const MachineInstr &MI) const

const MIRFormatter *	getMIRFormatter () const override

const TargetSchedModel &	getSchedModel () const

void	enforceOperandRCAlignment (MachineInstr &MI, unsigned OpName) const

Static Public Member Functions
static bool	isFoldableCopy (const MachineInstr &MI)

static bool	isSALU (const MachineInstr &MI)

static bool	isVALU (const MachineInstr &MI)

static bool	isVMEM (const MachineInstr &MI)

static bool	isSOP1 (const MachineInstr &MI)

static bool	isSOP2 (const MachineInstr &MI)

static bool	isSOPC (const MachineInstr &MI)

static bool	isSOPK (const MachineInstr &MI)

static bool	isSOPP (const MachineInstr &MI)

static bool	isPacked (const MachineInstr &MI)

static bool	isVOP1 (const MachineInstr &MI)

static bool	isVOP2 (const MachineInstr &MI)

static bool	isVOP3 (const MachineInstr &MI)

static bool	isSDWA (const MachineInstr &MI)

static bool	isVOPC (const MachineInstr &MI)

static bool	isMUBUF (const MachineInstr &MI)

static bool	isMTBUF (const MachineInstr &MI)

static bool	isSMRD (const MachineInstr &MI)

static bool	isDS (const MachineInstr &MI)

static bool	isMIMG (const MachineInstr &MI)

static bool	isGather4 (const MachineInstr &MI)

static bool	isFLAT (const MachineInstr &MI)

static bool	isSegmentSpecificFLAT (const MachineInstr &MI)

static bool	isFLATGlobal (const MachineInstr &MI)

static bool	isFLATScratch (const MachineInstr &MI)

static bool	isEXP (const MachineInstr &MI)

static bool	isDualSourceBlendEXP (const MachineInstr &MI)

static bool	isAtomicNoRet (const MachineInstr &MI)

static bool	isAtomicRet (const MachineInstr &MI)

static bool	isAtomic (const MachineInstr &MI)

static bool	isWQM (const MachineInstr &MI)

static bool	isDisableWQM (const MachineInstr &MI)

static bool	isVGPRSpill (const MachineInstr &MI)

static bool	isSGPRSpill (const MachineInstr &MI)

static bool	isDPP (const MachineInstr &MI)

static bool	isTRANS (const MachineInstr &MI)

static bool	isVOP3P (const MachineInstr &MI)

static bool	isVINTRP (const MachineInstr &MI)

static bool	isMAI (const MachineInstr &MI)

static bool	isMFMA (const MachineInstr &MI)

static bool	isDOT (const MachineInstr &MI)

static bool	isWMMA (const MachineInstr &MI)

static bool	isMFMAorWMMA (const MachineInstr &MI)

static bool	isLDSDIR (const MachineInstr &MI)

static bool	isVINTERP (const MachineInstr &MI)

static bool	isScalarUnit (const MachineInstr &MI)

static bool	usesVM_CNT (const MachineInstr &MI)

static bool	usesLGKM_CNT (const MachineInstr &MI)

static bool	sopkIsZext (const MachineInstr &MI)

static bool	isScalarStore (const MachineInstr &MI)

static bool	isFixedSize (const MachineInstr &MI)

static bool	hasFPClamp (const MachineInstr &MI)

static bool	hasIntClamp (const MachineInstr &MI)

static bool	usesFPDPRounding (const MachineInstr &MI)

static bool	isFPAtomic (const MachineInstr &MI)

static bool	doesNotReadTiedSource (const MachineInstr &MI)

static bool	modifiesModeRegister (const MachineInstr &MI)
	Return true if the instruction modifies the mode register.q.

static unsigned	getNumWaitStates (const MachineInstr &MI)
	Return the number of wait states that result from executing this instruction.

static bool	isKillTerminator (unsigned Opcode)

static bool	isLegalMUBUFImmOffset (unsigned Imm)

static unsigned	getDSShaderTypeValue (const MachineFunction &MF)

Protected Member Functions
bool	swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const

MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override

Detailed Description

Definition at line 44 of file SIInstrInfo.h.

Member Enumeration Documentation

◆ TargetOperandFlags

enum llvm::SIInstrInfo::TargetOperandFlags

Enumerator
MO_MASK
MO_NONE
MO_GOTPCREL
MO_GOTPCREL32
MO_GOTPCREL32_LO
MO_GOTPCREL32_HI
MO_REL32
MO_REL32_LO
MO_REL32_HI
MO_FAR_BRANCH_OFFSET
MO_ABS32_LO
MO_ABS32_HI

Definition at line 154 of file SIInstrInfo.h.

Constructor & Destructor Documentation

◆ SIInstrInfo()

SIInstrInfo::SIInstrInfo ( const GCNSubtarget & ST )

explicit

Definition at line 64 of file SIInstrInfo.cpp.

References llvm::TargetSchedModel::init().

Member Function Documentation

◆ analyzeBranch()

bool SIInstrInfo::analyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify = `false`
	)		const

override

Definition at line 2705 of file SIInstrInfo.cpp.

References analyzeBranchImpl(), Cond, E, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), I, llvm_unreachable, MBB, and TBB.

◆ analyzeBranchImpl()

bool SIInstrInfo::analyzeBranchImpl	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify
	)		const

Definition at line 2662 of file SIInstrInfo.cpp.

References Cond, llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), I, MBB, and TBB.

Referenced by analyzeBranch().

◆ analyzeCompare()

bool SIInstrInfo::analyzeCompare	(	const MachineInstr &	MI,
		Register &	SrcReg,
		Register &	SrcReg2,
		int64_t &	CmpMask,
		int64_t &	CmpValue
	)		const

override

Definition at line 8519 of file SIInstrInfo.cpp.

References MI.

◆ areLoadsFromSameBasePtr()

bool SIInstrInfo::areLoadsFromSameBasePtr	(	SDNode *	Load0,
		SDNode *	Load1,
		int64_t &	Offset0,
		int64_t &	Offset1
	)		const

override

Definition at line 172 of file SIInstrInfo.cpp.

References assert(), llvm::get(), llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::AMDGPU::hasNamedOperand(), isDS(), llvm::SDNode::isMachineOpcode(), isMTBUF(), isMUBUF(), isSMRD(), and nodesHaveSameOperandValue().

◆ areMemAccessesTriviallyDisjoint()

bool SIInstrInfo::areMemAccessesTriviallyDisjoint	(	const MachineInstr &	MIa,
		const MachineInstr &	MIb
	)		const

override

Definition at line 3295 of file SIInstrInfo.cpp.

References assert(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), isDS(), isFLAT(), isMTBUF(), isMUBUF(), isSegmentSpecificFLAT(), isSMRD(), and llvm::MachineInstr::mayLoadOrStore().

◆ buildExtractSubReg()

unsigned SIInstrInfo::buildExtractSubReg	(	MachineBasicBlock::iterator	MI,
		MachineRegisterInfo &	MRI,
		MachineOperand &	SuperReg,
		const TargetRegisterClass *	SuperRC,
		unsigned	SubIdx,
		const TargetRegisterClass *	SubRC
	)		const

Definition at line 4994 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), MBB, MI, MRI, and SubReg.

Referenced by buildExtractSubRegOrImm().

◆ buildExtractSubRegOrImm()

MachineOperand SIInstrInfo::buildExtractSubRegOrImm	(	MachineBasicBlock::iterator	MI,
		MachineRegisterInfo &	MRI,
		MachineOperand &	SuperReg,
		const TargetRegisterClass *	SuperRC,
		unsigned	SubIdx,
		const TargetRegisterClass *	SubRC
	)		const

Definition at line 5026 of file SIInstrInfo.cpp.

References buildExtractSubReg(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm_unreachable, MRI, and SubReg.

◆ buildShrunkInst()

MachineInstr * SIInstrInfo::buildShrunkInst	(	MachineInstr &	MI,
		unsigned	NewOpcode
	)		const

Definition at line 3976 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), copyFlagsToImplicitVCC(), fixImplicitOperands(), llvm::get(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::AMDGPU::hasNamedOperand(), MBB, MI, and llvm::MachineInstrBuilder::setMIFlags().

◆ canInsertSelect()

bool SIInstrInfo::canInsertSelect	(	const MachineBasicBlock &	MBB,
		ArrayRef< MachineOperand >	Cond,
		Register	DstReg,
		Register	TrueReg,
		Register	FalseReg,
		int &	CondCycles,
		int &	TrueCycles,
		int &	FalseCycles
	)		const

override

Definition at line 2848 of file SIInstrInfo.cpp.

References Cond, llvm::TargetRegisterClass::getID(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPU::getRegBitWidth(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::hasVGPRs(), llvm::SIRegisterInfo::isSGPRClass(), MBB, and MRI.

◆ canShrink()

bool SIInstrInfo::canShrink	(	const MachineInstr &	MI,
		const MachineRegisterInfo &	MRI
	)		const

Definition at line 3906 of file SIInstrInfo.cpp.

References getNamedOperand(), llvm::MachineOperand::getReg(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isVGPR(), MI, and MRI.

◆ commuteInstructionImpl()

MachineInstr * SIInstrInfo::commuteInstructionImpl	(	MachineInstr &	MI,
		bool	NewMI,
		unsigned	OpIdx0,
		unsigned	OpIdx1
	)		const

overrideprotected

Definition at line 2398 of file SIInstrInfo.cpp.

References assert(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteOpcode(), llvm::get(), llvm::AMDGPU::getNamedOperandIdx(), isOperandLegal(), llvm::MachineOperand::isReg(), MI, llvm::MachineInstr::setDesc(), swapRegAndNonRegOperand(), and swapSourceModifiers().

◆ commuteOpcode() [1/2]

LLVM_READONLY int llvm::SIInstrInfo::commuteOpcode ( const MachineInstr & MI ) const

inline

Definition at line 264 of file SIInstrInfo.h.

References commuteOpcode(), and MI.

◆ commuteOpcode() [2/2]

int SIInstrInfo::commuteOpcode ( unsigned Opc ) const

Definition at line 1050 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getCommuteOrig(), llvm::AMDGPU::getCommuteRev(), and pseudoToMCOpcode().

Referenced by commuteInstructionImpl(), commuteOpcode(), and legalizeOperandsVOP2().

◆ convertNonUniformIfRegion()

void SIInstrInfo::convertNonUniformIfRegion	(	MachineBasicBlock *	IfEntry,
		MachineBasicBlock *	IfEnd
	)		const

Definition at line 7675 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getFirstNonPHI(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineBasicBlock::insert(), and MRI.

◆ convertNonUniformLoopRegion()

void SIInstrInfo::convertNonUniformLoopRegion	(	MachineBasicBlock *	LoopEntry,
		MachineBasicBlock *	LoopEnd
	)		const

Definition at line 7700 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineBasicBlock::insert(), materializeImmediate(), MRI, and llvm::MachineBasicBlock::predecessors().

◆ convertToThreeAddress()

MachineInstr * SIInstrInfo::convertToThreeAddress	(	MachineInstr &	MI,
		LiveVariables *	LV,
		LiveIntervals *	LIS
	)		const

override

Definition at line 3380 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addOperand(), llvm::LiveVariables::VarInfo::AliveBlocks, assert(), llvm::BuildMI(), llvm::SparseBitVector< ElementSize >::clear(), DefMI, E, llvm::get(), llvm::GCNSubtarget::getConstantBusLimit(), getFoldableImm(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getMFMAEarlyClobberOp(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::LiveVariables::getVarInfo(), llvm::AMDGPU::hasNamedOperand(), llvm::AMDGPUSubtarget::hasTrue16BitInsts(), llvm::GCNSubtarget::hasVOP3Literal(), I, llvm::MachineOperand::isImm(), isInlineConstant(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), isWMMA(), llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode(), MBB, MI, MRI, pseudoToMCOpcode(), llvm::MachineInstr::removeOperand(), llvm::LiveIntervals::ReplaceMachineInstrInMaps(), llvm::MachineInstr::setDesc(), llvm::MachineInstrBuilder::setMIFlags(), and updateLiveVariables().

◆ copyPhysReg()

void SIInstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		MCRegister	DestReg,
		MCRegister	SrcReg,
		bool	KillSrc
	)		const

override

Definition at line 716 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), Builder, llvm::BuildMI(), contains(), copyPhysReg(), llvm::RegState::Define, DL, expandSGPRCopy(), Fix16BitCopies, llvm::get(), llvm::SIRegisterInfo::get32BitRegister(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::getKillRegState(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::SIRegisterInfo::getVGPR64Class(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMovB64(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm::GCNSubtarget::hasScalarCompareEq64(), llvm::GCNSubtarget::hasSDWAScalar(), llvm::SIRegisterInfo::hasVGPRs(), Idx, llvm::RegState::Implicit, indirectCopyToAGPR(), llvm::SIRegisterInfo::isAGPRClass(), llvm::SIRegisterInfo::isProperlyAlignedRC(), llvm::SIRegisterInfo::isSGPRClass(), MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, reportIllegalCopy(), llvm::ArrayRef< T >::size(), Size, llvm::MachineInstr::tieOperands(), llvm::RegState::Undef, llvm::AMDGPU::SDWA::UNUSED_PRESERVE, llvm::AMDGPU::SDWA::WORD_0, and llvm::AMDGPU::SDWA::WORD_1.

Referenced by copyPhysReg().

◆ createPHIDestinationCopy()

MachineInstr * SIInstrInfo::createPHIDestinationCopy	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	InsPt,
		const DebugLoc &	DL,
		Register	Src,
		Register	Dst
	)		const

override

Definition at line 8275 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHIDestinationCopy(), DL, llvm::MachineBasicBlock::end(), llvm::get(), and MBB.

◆ createPHISourceCopy()

MachineInstr * SIInstrInfo::createPHISourceCopy	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	InsPt,
		const DebugLoc &	DL,
		Register	Src,
		unsigned	SrcSubReg,
		Register	Dst
	)		const

override

Definition at line 8290 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHISourceCopy(), DL, llvm::MachineBasicBlock::end(), llvm::get(), llvm::RegState::Implicit, llvm::GCNSubtarget::isWave32(), and MBB.

◆ CreateTargetMIHazardRecognizer()

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetMIHazardRecognizer	(	const InstrItineraryData *	II,
		const ScheduleDAGMI *	DAG
	)		const

override

Definition at line 7773 of file SIInstrInfo.cpp.

References llvm::TargetInstrInfo::CreateTargetMIHazardRecognizer(), llvm::ScheduleDAGMI::hasVRegLiveness(), and llvm::ScheduleDAG::MF.

◆ CreateTargetPostRAHazardRecognizer() [1/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer	(	const InstrItineraryData *	II,
		const ScheduleDAG *	DAG
	)		const

override

This is used by the post-RA scheduler (SchedulePostRAList.cpp).

The post-RA version of misched uses CreateTargetMIHazardRecognizer.

Definition at line 7758 of file SIInstrInfo.cpp.

References llvm::ScheduleDAG::MF.

◆ CreateTargetPostRAHazardRecognizer() [2/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const MachineFunction & MF ) const

override

This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.

Definition at line 7766 of file SIInstrInfo.cpp.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > SIInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned TF ) const

override

Definition at line 7785 of file SIInstrInfo.cpp.

References MO_MASK.

◆ doesNotReadTiedSource() [1/2]

static bool llvm::SIInstrInfo::doesNotReadTiedSource ( const MachineInstr & MI )

inlinestatic

Definition at line 784 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::TiedSourceNotRead.

◆ doesNotReadTiedSource() [2/2]

bool llvm::SIInstrInfo::doesNotReadTiedSource ( uint16_t Opcode ) const

inline

Definition at line 788 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::TiedSourceNotRead.

◆ enforceOperandRCAlignment()

void SIInstrInfo::enforceOperandRCAlignment	(	MachineInstr &	MI,
		unsigned	OpName
	)		const

Definition at line 8725 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::CreateReg(), DL, llvm::get(), llvm::AMDGPU::getNamedOperandIdx(), getOpSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::isAGPR(), MI, MRI, and llvm::GCNSubtarget::needsAlignedVGPRs().

◆ expandMovDPP64()

std::pair< MachineInstr *, MachineInstr * > SIInstrInfo::expandMovDPP64 ( MachineInstr & MI ) const

◆ expandPostRAPseudo()

bool SIInstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

Definition at line 1880 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstr::addRegisterDead(), llvm::MIBundleBuilder::append(), assert(), llvm::MIBundleBuilder::begin(), llvm::BuildMI(), llvm::MachineInstrBuilder::copyImplicitOps(), llvm::RegState::Define, DL, llvm::AMDGPU::VGPRIndexMode::DST_ENABLE, expandMovDPP64(), llvm::TargetInstrInfo::expandPostRAPseudo(), expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::SrcOp::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::SrcOp::getReg(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::GCNSubtarget::hasMovB64(), llvm::GCNSubtarget::hasPackedFP32Ops(), llvm::SIRegisterInfo::hasVGPRs(), llvm::Hi, Idx, llvm::RegState::Implicit, llvm::MCInstrDesc::implicit_uses(), llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isAGPR(), isInlineConstant(), llvm::GCNSubtarget::isWave32(), llvm::Lo, MBB, MI, llvm::SISrcMods::OP_SEL_0, llvm::SISrcMods::OP_SEL_1, llvm::MachineOperand::setIsUndef(), llvm::AMDGPU::VGPRIndexMode::SRC0_ENABLE, SubReg, llvm::MachineInstr::tieOperands(), TRI, llvm::RegState::Undef, and llvm::GCNSubtarget::useVGPRIndexMode().

Referenced by expandPostRAPseudo().

◆ findCommutedOpIndices() [1/2]

bool SIInstrInfo::findCommutedOpIndices	(	const MachineInstr &	MI,
		unsigned &	SrcOpIdx0,
		unsigned &	SrcOpIdx1
	)		const

override

Definition at line 2450 of file SIInstrInfo.cpp.

References findCommutedOpIndices(), and MI.

Referenced by findCommutedOpIndices().

◆ findCommutedOpIndices() [2/2]

bool SIInstrInfo::findCommutedOpIndices	(	const MCInstrDesc &	Desc,
		unsigned &	SrcOpIdx0,
		unsigned &	SrcOpIdx1
	)		const

Definition at line 2456 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getOpcode(), and llvm::MCInstrDesc::isCommutable().

◆ fixImplicitOperands()

void SIInstrInfo::fixImplicitOperands ( MachineInstr & MI ) const

Definition at line 7877 of file SIInstrInfo.cpp.

References llvm::GCNSubtarget::isWave32(), and MI.

Referenced by buildShrunkInst(), insertBranch(), insertSelect(), legalizeOperandsVOP2(), and moveToVALU().

◆ FoldImmediate()

bool SIInstrInfo::FoldImmediate	(	MachineInstr &	UseMI,
		MachineInstr &	DefMI,
		Register	Reg,
		MachineRegisterInfo *	MRI
	)		const

final

Definition at line 3030 of file SIInstrInfo.cpp.

Referenced by legalizeGenericOperand().

◆ foldMemoryOperandImpl()

MachineInstr * SIInstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr &	MI,
		ArrayRef< unsigned >	Ops,
		MachineBasicBlock::iterator	InsertPt,
		int	FrameIndex,
		LiveIntervals *	LIS = `nullptr`,
		VirtRegMap *	VRM = `nullptr`
	)		const

override

Definition at line 8312 of file SIInstrInfo.cpp.

References llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::Register::isVirtual(), MI, and MRI.

◆ getAddNoCarry() [1/2]

MachineInstrBuilder SIInstrInfo::getAddNoCarry	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	DestReg
	)		const

Return a partially built integer add instruction without carry.

Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.

Definition at line 7820 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getVCC(), llvm::GCNSubtarget::hasAddNoCarry(), I, MBB, and MRI.

◆ getAddNoCarry() [2/2]

MachineInstrBuilder SIInstrInfo::getAddNoCarry	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	DestReg,
		RegScavenger &	RS
	)		const

Definition at line 7835 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::SIRegisterInfo::getVCC(), llvm::GCNSubtarget::hasAddNoCarry(), I, llvm::RegScavenger::isRegUsed(), llvm::Register::isValid(), MBB, and llvm::RegScavenger::scavengeRegister().

◆ getBranchDestBlock()

MachineBasicBlock * SIInstrInfo::getBranchDestBlock ( const MachineInstr & MI ) const

override

Definition at line 2490 of file SIInstrInfo.cpp.

References MI.

◆ getClampMask()

uint64_t llvm::SIInstrInfo::getClampMask ( const MachineInstr & MI ) const

inline

Definition at line 760 of file SIInstrInfo.h.

References llvm::SIInstrFlags::ClampHi, llvm::SIInstrFlags::ClampLo, llvm::SIInstrFlags::FPClamp, llvm::SIInstrFlags::IntClamp, and MI.

◆ getDefaultRsrcDataFormat()

uint64_t SIInstrInfo::getDefaultRsrcDataFormat ( ) const

Definition at line 7475 of file SIInstrInfo.cpp.

References llvm::Format, llvm::GCNSubtarget::getGeneration(), llvm::AMDGPUSubtarget::GFX10, llvm::AMDGPUSubtarget::GFX11, llvm::AMDGPUSubtarget::isAmdHsaOS(), llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPU::UfmtGFX10::UFMT_32_FLOAT, llvm::AMDGPU::UfmtGFX11::UFMT_32_FLOAT, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by getScratchRsrcWords23().

◆ getDSShaderTypeValue()

unsigned SIInstrInfo::getDSShaderTypeValue ( const MachineFunction & MF )

static

Definition at line 8497 of file SIInstrInfo.cpp.

References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, llvm::CallingConv::C, llvm::CallingConv::Fast, llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), and llvm::report_fatal_error().

◆ getGenericInstructionUniformity()

InstructionUniformity SIInstrInfo::getGenericInstructionUniformity ( const MachineInstr & MI ) const

Definition at line 8367 of file SIInstrInfo.cpp.

References llvm::AlwaysUniform, llvm::any_of(), llvm::Default, llvm::AMDGPU::isIntrinsicAlwaysUniform(), llvm::AMDGPU::isIntrinsicSourceOfDivergence(), MI, and llvm::NeverUniform.

Referenced by getInstructionUniformity().

◆ getIndirectGPRIDXPseudo()

const MCInstrDesc & SIInstrInfo::getIndirectGPRIDXPseudo	(	unsigned	VecSize,
		bool	IsIndirectSrc
	)		const

Definition at line 1296 of file SIInstrInfo.cpp.

References llvm::get(), and llvm_unreachable.

◆ getIndirectRegWriteMovRelPseudo()

const MCInstrDesc & SIInstrInfo::getIndirectRegWriteMovRelPseudo	(	unsigned	VecSize,
		unsigned	EltSize,
		bool	IsSGPR
	)		const

Definition at line 1421 of file SIInstrInfo.cpp.

References assert(), llvm::get(), getIndirectSGPRWriteMovRelPseudo32(), getIndirectSGPRWriteMovRelPseudo64(), getIndirectVGPRWriteMovRelPseudoOpc(), and llvm_unreachable.

◆ getInstBundleSize()

unsigned SIInstrInfo::getInstBundleSize ( const MachineInstr & MI ) const

Definition at line 7584 of file SIInstrInfo.cpp.

References assert(), E, getInstSizeInBytes(), I, MI, and Size.

Referenced by getInstSizeInBytes().

◆ getInstrLatency()

unsigned SIInstrInfo::getInstrLatency	(	const InstrItineraryData *	ItinData,
		const MachineInstr &	MI,
		unsigned *	PredCost = `nullptr`
	)		const

override

Definition at line 8349 of file SIInstrInfo.cpp.

References E, I, and MI.

Referenced by llvm::GCNSubtarget::adjustSchedDependency().

◆ getInstructionUniformity()

InstructionUniformity SIInstrInfo::getInstructionUniformity ( const MachineInstr & MI ) const

finaloverride

◆ getInstSizeInBytes()

unsigned SIInstrInfo::getInstSizeInBytes ( const MachineInstr & MI ) const

override

Definition at line 7596 of file SIInstrInfo.cpp.

References E, getInstBundleSize(), llvm::TargetMachine::getMCAsmInfo(), getMCOpcodeFromPseudo(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getSize(), llvm::MachineFunction::getTarget(), llvm::GCNSubtarget::hasOffset3fBug(), I, isDPP(), isFixedSize(), isInlineConstant(), isMIMG(), isSALU(), isVALU(), MI, llvm::MCInstrDesc::operands(), and Size.

Referenced by llvm::AMDGPUAsmPrinter::emitInstruction(), getInstBundleSize(), and removeBranch().

◆ getKillTerminatorFromPseudo()

const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo ( unsigned Opcode ) const

Definition at line 7866 of file SIInstrInfo.cpp.

References llvm::get(), and llvm_unreachable.

◆ getMachineCSELookAheadLimit()

unsigned llvm::SIInstrInfo::getMachineCSELookAheadLimit ( ) const

inlineoverride

Definition at line 345 of file SIInstrInfo.h.

◆ getMCOpcodeFromPseudo()

const MCInstrDesc & llvm::SIInstrInfo::getMCOpcodeFromPseudo ( unsigned Opcode ) const

inline

Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.

Definition at line 1050 of file SIInstrInfo.h.

References llvm::get(), and pseudoToMCOpcode().

Referenced by getInstSizeInBytes().

◆ getMemOperandsWithOffsetWidth()

bool SIInstrInfo::getMemOperandsWithOffsetWidth	(	const MachineInstr &	LdSt,
		SmallVectorImpl< const MachineOperand * > &	BaseOps,
		int64_t &	Offset,
		bool &	OffsetIsScalable,
		unsigned &	Width,
		const TargetRegisterInfo *	TRI
	)		const

final

◆ getMIRFormatter()

const MIRFormatter * llvm::SIInstrInfo::getMIRFormatter ( ) const

inlineoverride

Definition at line 1180 of file SIInstrInfo.h.

◆ getMovOpcode()

unsigned SIInstrInfo::getMovOpcode ( const TargetRegisterClass * DstRC ) const

Definition at line 1281 of file SIInstrInfo.cpp.

References llvm::SIRegisterInfo::isAGPRClass(), and llvm::SIRegisterInfo::isSGPRClass().

◆ getNamedImmOperand()

int64_t llvm::SIInstrInfo::getNamedImmOperand	(	const MachineInstr &	MI,
		unsigned	OpName
	)		const

inline

Get required immediate operand.

Definition at line 1037 of file SIInstrInfo.h.

References llvm::AMDGPU::getNamedOperandIdx(), Idx, and MI.

Referenced by legalizeOperands().

◆ getNamedOperand() [1/2]

LLVM_READONLY const MachineOperand * llvm::SIInstrInfo::getNamedOperand	(	const MachineInstr &	MI,
		unsigned	OpName
	)		const

inline

Definition at line 1031 of file SIInstrInfo.h.

References getNamedOperand(), and MI.

◆ getNamedOperand() [2/2]

MachineOperand * SIInstrInfo::getNamedOperand	(	MachineInstr &	MI,
		unsigned	OperandName
	)		const

Returns the operand named Op.

If MI does not have an operand named Op, this function returns nullptr.

Definition at line 7466 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), Idx, and MI.

Referenced by buildShrunkInst(), canShrink(), convertToThreeAddress(), expandMovDPP64(), FoldImmediate(), getMemOperandsWithOffsetWidth(), getNamedOperand(), hasModifiersSet(), isSGPRStackAccess(), isStackAccess(), legalizeOperands(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), swapSourceModifiers(), and verifyInstruction().

◆ getNumWaitStates()

unsigned SIInstrInfo::getNumWaitStates ( const MachineInstr & MI )

static

Return the number of wait states that result from executing this instruction.

Definition at line 1866 of file SIInstrInfo.cpp.

References MI.

Referenced by llvm::GCNHazardRecognizer::AdvanceCycle().

◆ getOpRegClass()

const TargetRegisterClass * SIInstrInfo::getOpRegClass	(	const MachineInstr &	MI,
		unsigned	OpNo
	)		const

Return the correct register class for OpNo.

For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.

Definition at line 4950 of file SIInstrInfo.cpp.

References adjustAllocatableRegClass(), llvm::get(), llvm::MCInstrDesc::getNumOperands(), MI, MRI, and llvm::MCInstrDesc::operands().

Referenced by expandPostRAPseudo(), getMemOperandsWithOffsetWidth(), getOpSize(), legalizeOperands(), and verifyInstruction().

◆ getOpSize() [1/2]

unsigned llvm::SIInstrInfo::getOpSize	(	const MachineInstr &	MI,
		unsigned	OpNo
	)		const

inline

This form should usually be preferred since it handles operands with unknown register classes.

Definition at line 935 of file SIInstrInfo.h.

References getOpRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isReg(), MI, and SubReg.

◆ getOpSize() [2/2]

unsigned llvm::SIInstrInfo::getOpSize	(	uint16_t	Opcode,
		unsigned	OpNo
	)		const

inline

Return the size in bytes of the operand OpNo on the given.

Definition at line 921 of file SIInstrInfo.h.

References assert(), llvm::get(), llvm::SIRegisterInfo::getRegClass(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.

Referenced by enforceOperandRCAlignment(), FoldImmediate(), getMemOperandsWithOffsetWidth(), and isInlineConstant().

◆ getPreferredSelectRegClass()

const TargetRegisterClass * SIInstrInfo::getPreferredSelectRegClass ( unsigned Size ) const

Definition at line 1125 of file SIInstrInfo.cpp.

◆ getRegClass()

const TargetRegisterClass * SIInstrInfo::getRegClass	(	const MCInstrDesc &	TID,
		unsigned	OpNum,
		const TargetRegisterInfo *	TRI,
		const MachineFunction &	MF
	)		const

override

Definition at line 4920 of file SIInstrInfo.cpp.

References adjustAllocatableRegClass(), llvm::SIInstrFlags::DS, llvm::SIInstrFlags::FLAT, llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineFunction::getRegInfo(), llvm::AMDGPU::hasNamedOperand(), llvm::MCInstrDesc::Opcode, llvm::MCInstrDesc::operands(), and llvm::MCInstrDesc::TSFlags.

◆ getRegisterInfo()

const SIRegisterInfo & llvm::SIInstrInfo::getRegisterInfo ( ) const

inline

Definition at line 179 of file SIInstrInfo.h.

◆ getSchedModel()

const TargetSchedModel & llvm::SIInstrInfo::getSchedModel ( ) const

inline

Definition at line 1188 of file SIInstrInfo.h.

Referenced by llvm::GCNSubtarget::adjustSchedDependency(), and llvm::GCNSchedStage::getScheduleMetrics().

◆ getScratchRsrcWords23()

uint64_t SIInstrInfo::getScratchRsrcWords23 ( ) const

Definition at line 7500 of file SIInstrInfo.cpp.

References getDefaultRsrcDataFormat(), llvm::GCNSubtarget::getGeneration(), llvm::GCNSubtarget::getMaxPrivateElementSize(), llvm::AMDGPUSubtarget::getWavefrontSize(), llvm::AMDGPUSubtarget::GFX9, llvm::Log2_32(), llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT, llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT, llvm::AMDGPU::RSRC_TID_ENABLE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > SIInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 7790 of file SIInstrInfo.cpp.

References MO_ABS32_HI, MO_ABS32_LO, MO_GOTPCREL, MO_GOTPCREL32_HI, MO_GOTPCREL32_LO, MO_REL32_HI, and MO_REL32_LO.

◆ getSerializableMachineMemOperandTargetFlags()

ArrayRef< std::pair< MachineMemOperand::Flags, const char * > > SIInstrInfo::getSerializableMachineMemOperandTargetFlags ( ) const

override

Definition at line 7805 of file SIInstrInfo.cpp.

References llvm::MONoClobber.

◆ getSerializableTargetIndices()

ArrayRef< std::pair< int, const char * > > SIInstrInfo::getSerializableTargetIndices ( ) const

override

Definition at line 7745 of file SIInstrInfo.cpp.

References llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2, and llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3.

◆ getSubtarget()

const GCNSubtarget & llvm::SIInstrInfo::getSubtarget ( ) const

inline

Definition at line 183 of file SIInstrInfo.h.

◆ getVALUOp()

unsigned SIInstrInfo::getVALUOp ( const MachineInstr & MI ) const

Definition at line 4803 of file SIInstrInfo.cpp.

References llvm::GCNSubtarget::hasAddNoCarry(), llvm::GCNSubtarget::hasDLInsts(), llvm::SIRegisterInfo::isAGPR(), llvm_unreachable, MI, and MRI.

Referenced by moveToVALU().

◆ hasAnyModifiersSet()

bool SIInstrInfo::hasAnyModifiersSet ( const MachineInstr & MI ) const

Definition at line 3901 of file SIInstrInfo.cpp.

References llvm::any_of(), hasModifiersSet(), MI, ModifierOpNames, and Name.

Referenced by FoldImmediate().

◆ hasDivergentBranch()

bool SIInstrInfo::hasDivergentBranch ( const MachineBasicBlock * MBB ) const

Return whether the block terminate with divergent branch.

Note this only work before lowering the pseudo control flow instructions.

Definition at line 2501 of file SIInstrInfo.cpp.

References MBB, MI, and llvm::MachineBasicBlock::terminators().

◆ hasFPClamp() [1/2]

static bool llvm::SIInstrInfo::hasFPClamp ( const MachineInstr & MI )

inlinestatic

Definition at line 748 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp, and MI.

◆ hasFPClamp() [2/2]

bool llvm::SIInstrInfo::hasFPClamp ( uint16_t Opcode ) const

inline

Definition at line 752 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp, and llvm::get().

◆ hasIntClamp()

static bool llvm::SIInstrInfo::hasIntClamp ( const MachineInstr & MI )

inlinestatic

Definition at line 756 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IntClamp, and MI.

◆ hasModifiers()

bool SIInstrInfo::hasModifiers ( unsigned Opcode ) const

Return true if this instruction has any modifiers.

e.g. src[012]_mod, omod, clamp.

Definition at line 3888 of file SIInstrInfo.cpp.

References llvm::AMDGPU::hasNamedOperand().

◆ hasModifiersSet()

bool SIInstrInfo::hasModifiersSet	(	const MachineInstr &	MI,
		unsigned	OpName
	)		const

Definition at line 3895 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), getNamedOperand(), and MI.

Referenced by canShrink(), and hasAnyModifiersSet().

◆ hasUnwantedEffectsWhenEXECEmpty()

bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const

Whether we must prevent this instruction from executing with EXEC = 0.

Definition at line 3660 of file SIInstrInfo.cpp.

References isEXP(), isSMRD(), MI, and modifiesModeRegister().

◆ hasVALU32BitEncoding()

bool SIInstrInfo::hasVALU32BitEncoding ( unsigned Opcode ) const

Return true if this 64-bit VALU instruction has a 32-bit encoding.

This function will return false if you pass it a 32-bit instruction.

Definition at line 3876 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getVOPe32(), llvm::GCNSubtarget::hasGFX90AInsts(), and pseudoToMCOpcode().

Referenced by canShrink().

◆ hasVGPRUses()

bool llvm::SIInstrInfo::hasVGPRUses ( const MachineInstr & MI ) const

inline

Definition at line 800 of file SIInstrInfo.h.

References llvm::any_of(), llvm::MachineFunction::getRegInfo(), MI, and MRI.

◆ insertBranch()

unsigned SIInstrInfo::insertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		ArrayRef< MachineOperand >	Cond,
		const DebugLoc &	DL,
		int *	BytesAdded = `nullptr`
	)		const

override

Definition at line 2774 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), Cond, DL, fixImplicitOperands(), llvm::get(), llvm::MachineInstr::getOperand(), llvm::GCNSubtarget::hasOffset3fBug(), isImm(), isUndef(), MBB, preserveCondRegFlags(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsUndef(), and TBB.

◆ insertEQ()

Register SIInstrInfo::insertEQ	(	MachineBasicBlock *	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	SrcReg,
		int	Value
	)		const

Definition at line 1255 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MBB, and MRI.

◆ insertIndirectBranch()

void SIInstrInfo::insertIndirectBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock &	NewDestBB,
		MachineBasicBlock &	RestoreBB,
		const DebugLoc &	DL,
		int64_t	BrOffset,
		RegScavenger *	RS
	)		const

override

Definition at line 2511 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addSym(), assert(), llvm::BuildMI(), llvm::MCSymbolRefExpr::create(), llvm::MCConstantExpr::create(), llvm::MCBinaryExpr::createAnd(), llvm::MCBinaryExpr::createAShr(), llvm::MCBinaryExpr::createSub(), llvm::RegState::Define, DL, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::get(), llvm::MachineFunction::getContext(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::getSymbol(), I, MBB, MO_FAR_BRANCH_OFFSET, MRI, llvm::Offset, llvm::MachineBasicBlock::pred_size(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::MachineInstr::setPostInstrSymbol(), llvm::RegScavenger::setRegUsed(), llvm::MCSymbol::setVariableValue(), and TRI.

◆ insertNE()

Register SIInstrInfo::insertNE	(	MachineBasicBlock *	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	SrcReg,
		int	Value
	)		const

Definition at line 1268 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), DL, llvm::get(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), I, MBB, and MRI.

◆ insertNoop()

void SIInstrInfo::insertNoop	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI
	)		const

override

Definition at line 1832 of file SIInstrInfo.cpp.

References insertNoops(), MBB, and MI.

◆ insertNoops()

void SIInstrInfo::insertNoops	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	Quantity
	)		const

override

Definition at line 1837 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), Arg, llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), MBB, and MI.

Referenced by insertNoop().

◆ insertReturn()

void SIInstrInfo::insertReturn ( MachineBasicBlock & MBB ) const

Definition at line 1848 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::get(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), Info, MBB, and llvm::MachineBasicBlock::succ_empty().

◆ insertSelect()

void SIInstrInfo::insertSelect	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	DstReg,
		ArrayRef< MachineOperand >	Cond,
		Register	TrueReg,
		Register	FalseReg
	)		const

override

◆ insertVectorSelect()

void SIInstrInfo::insertVectorSelect	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	DstReg,
		ArrayRef< MachineOperand >	Cond,
		Register	TrueReg,
		Register	FalseReg
	)		const

◆ isAlwaysGDS()

bool SIInstrInfo::isAlwaysGDS ( uint16_t Opcode ) const

Definition at line 3643 of file SIInstrInfo.cpp.

◆ isAsmOnlyOpcode()

bool SIInstrInfo::isAsmOnlyOpcode ( int MCOp ) const

Check if this instruction should only be used by assembler.

Return true if this opcode should not be used by codegen.

Definition at line 8024 of file SIInstrInfo.cpp.

Referenced by pseudoToMCOpcode().

◆ isAtomic() [1/2]

static bool llvm::SIInstrInfo::isAtomic ( const MachineInstr & MI )

inlinestatic

Definition at line 587 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsAtomicNoRet, llvm::SIInstrFlags::IsAtomicRet, and MI.

Referenced by getInstructionUniformity(), and isValidClauseInst().

◆ isAtomic() [2/2]

bool llvm::SIInstrInfo::isAtomic ( uint16_t Opcode ) const

inline

Definition at line 592 of file SIInstrInfo.h.

References llvm::get(), llvm::SIInstrFlags::IsAtomicNoRet, and llvm::SIInstrFlags::IsAtomicRet.

◆ isAtomicNoRet() [1/2]

static bool llvm::SIInstrInfo::isAtomicNoRet ( const MachineInstr & MI )

inlinestatic

Definition at line 571 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsAtomicNoRet, and MI.

◆ isAtomicNoRet() [2/2]

bool llvm::SIInstrInfo::isAtomicNoRet ( uint16_t Opcode ) const

inline

Definition at line 575 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::IsAtomicNoRet.

◆ isAtomicRet() [1/2]

static bool llvm::SIInstrInfo::isAtomicRet ( const MachineInstr & MI )

inlinestatic

Definition at line 579 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsAtomicRet, and MI.

◆ isAtomicRet() [2/2]

bool llvm::SIInstrInfo::isAtomicRet ( uint16_t Opcode ) const

inline

Definition at line 583 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::IsAtomicRet.

◆ isBasicBlockPrologue()

bool SIInstrInfo::isBasicBlockPrologue ( const MachineInstr & MI ) const

override

Definition at line 7814 of file SIInstrInfo.cpp.

References MI.

◆ isBranchOffsetInRange()

bool SIInstrInfo::isBranchOffsetInRange	(	unsigned	BranchOpc,
		int64_t	BrOffset
	)		const

override

Definition at line 2474 of file SIInstrInfo.cpp.

References assert(), BranchOffsetBits, and llvm::isIntN().

◆ isBufferSMRD()

bool SIInstrInfo::isBufferSMRD ( const MachineInstr & MI ) const

Definition at line 7887 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), llvm::SIRegisterInfo::getRegClass(), llvm::TargetRegisterClass::hasSubClassEq(), Idx, isSMRD(), and MI.

◆ isDisableWQM() [1/2]

static bool llvm::SIInstrInfo::isDisableWQM ( const MachineInstr & MI )

inlinestatic

Definition at line 605 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM, and MI.

◆ isDisableWQM() [2/2]

bool llvm::SIInstrInfo::isDisableWQM ( uint16_t Opcode ) const

inline

Definition at line 609 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM, and llvm::get().

◆ isDOT() [1/2]

static bool llvm::SIInstrInfo::isDOT ( const MachineInstr & MI )

inlinestatic

Definition at line 674 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsDOT, and MI.

◆ isDOT() [2/2]

bool llvm::SIInstrInfo::isDOT ( uint16_t Opcode ) const

inline

Definition at line 690 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::IsDOT.

◆ isDPP() [1/2]

static bool llvm::SIInstrInfo::isDPP ( const MachineInstr & MI )

inlinestatic

Definition at line 629 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP, and MI.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isDPP() [2/2]

bool llvm::SIInstrInfo::isDPP ( uint16_t Opcode ) const

inline

Definition at line 633 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP, and llvm::get().

◆ isDS() [1/2]

static bool llvm::SIInstrInfo::isDS ( const MachineInstr & MI )

inlinestatic

Definition at line 492 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS, and MI.

Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), isOperandLegal(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldRunLdsBranchVmemWARHazardFixup(), and verifyInstruction().

◆ isDS() [2/2]

bool llvm::SIInstrInfo::isDS ( uint16_t Opcode ) const

inline

Definition at line 496 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS, and llvm::get().

◆ isDualSourceBlendEXP()

static bool llvm::SIInstrInfo::isDualSourceBlendEXP ( const MachineInstr & MI )

inlinestatic

Definition at line 559 of file SIInstrInfo.h.

References llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND0, llvm::AMDGPU::Exp::ET_DUAL_SRC_BLEND1, isEXP(), and MI.

◆ isEXP() [1/2]

static bool llvm::SIInstrInfo::isEXP ( const MachineInstr & MI )

inlinestatic

Definition at line 555 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP, and MI.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), hasUnwantedEffectsWhenEXECEmpty(), isDualSourceBlendEXP(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isEXP() [2/2]

bool llvm::SIInstrInfo::isEXP ( uint16_t Opcode ) const

inline

Definition at line 567 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP, and llvm::get().

◆ isFixedSize() [1/2]

static bool llvm::SIInstrInfo::isFixedSize ( const MachineInstr & MI )

inlinestatic

Definition at line 740 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE, and MI.

Referenced by getInstSizeInBytes().

◆ isFixedSize() [2/2]

bool llvm::SIInstrInfo::isFixedSize ( uint16_t Opcode ) const

inline

Definition at line 744 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE, and llvm::get().

◆ isFLAT() [1/2]

static bool llvm::SIInstrInfo::isFLAT ( const MachineInstr & MI )

inlinestatic

Definition at line 518 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT, and MI.

Referenced by areMemAccessesTriviallyDisjoint(), breaksVMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), getInstructionUniformity(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isLdsDma(), isVMEMClauseInst(), legalizeOperands(), mayAccessFlatAddressSpace(), mayWriteLDSThroughDMA(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and verifyInstruction().

◆ isFLAT() [2/2]

bool llvm::SIInstrInfo::isFLAT ( uint16_t Opcode ) const

inline

Definition at line 551 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT, and llvm::get().

◆ isFLATGlobal() [1/2]

static bool llvm::SIInstrInfo::isFLATGlobal ( const MachineInstr & MI )

inlinestatic

Definition at line 534 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatGlobal, and MI.

◆ isFLATGlobal() [2/2]

bool llvm::SIInstrInfo::isFLATGlobal ( uint16_t Opcode ) const

inline

Definition at line 538 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatGlobal, and llvm::get().

◆ isFLATScratch() [1/2]

static bool llvm::SIInstrInfo::isFLATScratch ( const MachineInstr & MI )

inlinestatic

Definition at line 542 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatScratch, and MI.

Referenced by llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), and llvm::SIRegisterInfo::needsFrameBaseReg().

◆ isFLATScratch() [2/2]

bool llvm::SIInstrInfo::isFLATScratch ( uint16_t Opcode ) const

inline

Definition at line 546 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatScratch, and llvm::get().

◆ isFoldableCopy()

bool SIInstrInfo::isFoldableCopy ( const MachineInstr & MI )

static

Definition at line 2997 of file SIInstrInfo.cpp.

References MI.

Referenced by getFoldableImm().

◆ isFPAtomic() [1/2]

static bool llvm::SIInstrInfo::isFPAtomic ( const MachineInstr & MI )

inlinestatic

Definition at line 776 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPAtomic, and MI.

◆ isFPAtomic() [2/2]

bool llvm::SIInstrInfo::isFPAtomic ( uint16_t Opcode ) const

inline

Definition at line 780 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPAtomic, and llvm::get().

◆ isGather4() [1/2]

static bool llvm::SIInstrInfo::isGather4 ( const MachineInstr & MI )

inlinestatic

Definition at line 510 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4, and MI.

Referenced by verifyInstruction().

◆ isGather4() [2/2]

bool llvm::SIInstrInfo::isGather4 ( uint16_t Opcode ) const

inline

Definition at line 514 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4, and llvm::get().

◆ isHighLatencyDef()

bool SIInstrInfo::isHighLatencyDef ( int Opc ) const

override

Definition at line 7530 of file SIInstrInfo.cpp.

References llvm::get(), isFLAT(), isMIMG(), isMTBUF(), and isMUBUF().

Referenced by llvm::SIScheduleDAGMI::schedule().

◆ isIgnorableUse()

bool SIInstrInfo::isIgnorableUse ( const MachineOperand & MO ) const

override

Definition at line 166 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), isVALU(), and resultDependsOnExec().

◆ isImmOperandLegal()

bool SIInstrInfo::isImmOperandLegal	(	const MachineInstr &	MI,
		unsigned	OpNo,
		const MachineOperand &	MO
	)		const

◆ isInlineConstant() [1/8]

bool llvm::SIInstrInfo::isInlineConstant ( const APFloat & Imm ) const

inline

Definition at line 820 of file SIInstrInfo.h.

References isInlineConstant().

◆ isInlineConstant() [2/8]

bool SIInstrInfo::isInlineConstant ( const APInt & Imm ) const

Definition at line 3726 of file SIInstrInfo.cpp.

References llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPU::isInlinableLiteral16(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), and llvm_unreachable.

Referenced by convertToThreeAddress(), expandPostRAPseudo(), FoldImmediate(), getInstSizeInBytes(), isImmOperandLegal(), isInlineConstant(), isOperandLegal(), legalizeOperandsVOP3(), AMDGPURegBankCombinerHelper::matchFPMinMaxToMed3(), usesConstantBus(), and verifyInstruction().

◆ isInlineConstant() [3/8]

bool llvm::SIInstrInfo::isInlineConstant	(	const MachineInstr &	MI,
		const MachineOperand &	UseMO,
		const MachineOperand &	DefMO
	)		const

inline

returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.

Definition at line 840 of file SIInstrInfo.h.

References assert(), llvm::MachineOperand::getParent(), isInlineConstant(), and MI.

◆ isInlineConstant() [4/8]

bool llvm::SIInstrInfo::isInlineConstant	(	const MachineInstr &	MI,
		unsigned	OpIdx
	)		const

inline

returns true if the operand OpIdx in MI is a valid inline immediate.

Definition at line 853 of file SIInstrInfo.h.

References isInlineConstant(), and MI.

◆ isInlineConstant() [5/8]

bool llvm::SIInstrInfo::isInlineConstant	(	const MachineInstr &	MI,
		unsigned	OpIdx,
		const MachineOperand &	MO
	)		const

inline

Definition at line 858 of file SIInstrInfo.h.

References assert(), getOpSize(), isInlineConstant(), MI, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, and Size.

◆ isInlineConstant() [6/8]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand & MO ) const

inline

Definition at line 875 of file SIInstrInfo.h.

References llvm::MachineInstr::getOperandNo(), llvm::MachineOperand::getParent(), and isInlineConstant().

◆ isInlineConstant() [7/8]

bool llvm::SIInstrInfo::isInlineConstant	(	const MachineOperand &	MO,
		const MCOperandInfo &	OpInfo
	)		const

inline

Definition at line 833 of file SIInstrInfo.h.

References isInlineConstant(), and llvm::MCOperandInfo::OperandType.

◆ isInlineConstant() [8/8]

bool SIInstrInfo::isInlineConstant	(	const MachineOperand &	MO,
		uint8_t	OperandType
	)		const

Definition at line 3746 of file SIInstrInfo.cpp.

◆ isKillTerminator()

bool SIInstrInfo::isKillTerminator ( unsigned Opcode )

static

Definition at line 7856 of file SIInstrInfo.cpp.

◆ isLDSDIR() [1/2]

static bool llvm::SIInstrInfo::isLDSDIR ( const MachineInstr & MI )

inlinestatic

Definition at line 694 of file SIInstrInfo.h.

References llvm::SIInstrFlags::LDSDIR, and MI.

◆ isLDSDIR() [2/2]

bool llvm::SIInstrInfo::isLDSDIR ( uint16_t Opcode ) const

inline

Definition at line 698 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::LDSDIR.

◆ isLegalFLATOffset()

bool SIInstrInfo::isLegalFLATOffset	(	int64_t	Offset,
		unsigned	AddrSpace,
		uint64_t	FlatVariant
	)		const

Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.

If Signed, this is for an instruction that interprets the offset as signed.

Definition at line 7930 of file SIInstrInfo.cpp.

References llvm::SIInstrFlags::FLAT, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::SIInstrFlags::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), llvm::AMDGPUAS::GLOBAL_ADDRESS, llvm::GCNSubtarget::hasFlatInstOffsets(), llvm::GCNSubtarget::hasFlatSegmentOffsetBug(), llvm::GCNSubtarget::hasNegativeScratchOffsetBug(), llvm::GCNSubtarget::hasNegativeUnalignedScratchOffsetBug(), llvm::isIntN(), N, and llvm::Offset.

Referenced by llvm::SITargetLowering::isLegalGlobalAddressingMode(), and splitFlatOffset().

◆ isLegalMUBUFImmOffset()

static bool llvm::SIInstrInfo::isLegalMUBUFImmOffset ( unsigned Imm )

inlinestatic

Definition at line 1131 of file SIInstrInfo.h.

Referenced by llvm::SIFrameLowering::allocateScavengingFrameIndexesNearIncomingSP(), llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIRegisterInfo::isFrameOffsetLegal(), llvm::SIRegisterInfo::needsFrameBaseReg(), and llvm::SIRegisterInfo::resolveFrameIndex().

◆ isLegalRegOperand()

bool SIInstrInfo::isLegalRegOperand	(	const MachineRegisterInfo &	MRI,
		const MCOperandInfo &	OpInfo,
		const MachineOperand &	MO
	)		const

Check if MO (a register operand) is a legal register for the given operand description.

Definition at line 5055 of file SIInstrInfo.cpp.

References llvm::TargetRegisterClass::contains(), llvm::SIRegisterInfo::getLargestLegalSuperClass(), llvm::MachineOperand::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::TargetRegisterClass::hasSuperClassEq(), llvm::MachineOperand::isReg(), MRI, and llvm::MCOperandInfo::RegClass.

Referenced by isLegalVSrcOperand(), isOperandLegal(), and legalizeOperandsVOP2().

◆ isLegalVSrcOperand()

bool SIInstrInfo::isLegalVSrcOperand	(	const MachineRegisterInfo &	MRI,
		const MCOperandInfo &	OpInfo,
		const MachineOperand &	MO
	)		const

Check if MO would be a valid operand for the given operand definition OpInfo.

Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).

Definition at line 5082 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isTargetIndex(), and MRI.

◆ isLoadFromStackSlot()

unsigned SIInstrInfo::isLoadFromStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

Definition at line 7556 of file SIInstrInfo.cpp.

References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and MI.

◆ isLowLatencyInstruction()

bool SIInstrInfo::isLowLatencyInstruction ( const MachineInstr & MI ) const

Definition at line 7524 of file SIInstrInfo.cpp.

References isSMRD(), and MI.

Referenced by llvm::SIScheduleDAGMI::schedule().

◆ isMAI() [1/2]

static bool llvm::SIInstrInfo::isMAI ( const MachineInstr & MI )

inlinestatic

Definition at line 661 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsMAI, and MI.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), isImmOperandLegal(), isMFMA(), isXDL(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and pseudoToMCOpcode().

◆ isMAI() [2/2]

bool llvm::SIInstrInfo::isMAI ( uint16_t Opcode ) const

inline

Definition at line 665 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::IsMAI.

◆ isMFMA()

static bool llvm::SIInstrInfo::isMFMA ( const MachineInstr & MI )

inlinestatic

Definition at line 669 of file SIInstrInfo.h.

References isMAI(), and MI.

Referenced by isMFMAorWMMA(), and llvm::GCNHazardRecognizer::ShouldPreferAnother().

◆ isMFMAorWMMA()

static bool llvm::SIInstrInfo::isMFMAorWMMA ( const MachineInstr & MI )

inlinestatic

Definition at line 686 of file SIInstrInfo.h.

References isMFMA(), isWMMA(), and MI.

◆ isMIMG() [1/2]

static bool llvm::SIInstrInfo::isMIMG ( const MachineInstr & MI )

inlinestatic

Definition at line 502 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::MIMG.

Referenced by getInstSizeInBytes(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isOperandLegal(), isVMEM(), legalizeOperands(), and verifyInstruction().

◆ isMIMG() [2/2]

bool llvm::SIInstrInfo::isMIMG ( uint16_t Opcode ) const

inline

Definition at line 506 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::MIMG.

◆ isMTBUF() [1/2]

static bool llvm::SIInstrInfo::isMTBUF ( const MachineInstr & MI )

inlinestatic

Definition at line 474 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::MTBUF.

Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOperandsWithOffsetWidth(), isHighLatencyDef(), isVMEM(), and legalizeOperands().

◆ isMTBUF() [2/2]

bool llvm::SIInstrInfo::isMTBUF ( uint16_t Opcode ) const

inline

Definition at line 478 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::MTBUF.

◆ isMUBUF() [1/2]

static bool llvm::SIInstrInfo::isMUBUF ( const MachineInstr & MI )

inlinestatic

Definition at line 466 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::MUBUF.

Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), getMemOperandsWithOffsetWidth(), llvm::SIRegisterInfo::getScratchInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isHighLatencyDef(), isLdsDma(), isLoadFromStackSlot(), isStoreToStackSlot(), isVMEM(), legalizeOperands(), mayWriteLDSThroughDMA(), and llvm::SIRegisterInfo::needsFrameBaseReg().

◆ isMUBUF() [2/2]

bool llvm::SIInstrInfo::isMUBUF ( uint16_t Opcode ) const

inline

Definition at line 470 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::MUBUF.

◆ isNonUniformBranchInstr()

bool SIInstrInfo::isNonUniformBranchInstr ( MachineInstr & Instr ) const

Definition at line 7671 of file SIInstrInfo.cpp.

◆ isOperandLegal()

bool SIInstrInfo::isOperandLegal	(	const MachineInstr &	MI,
		unsigned	OpIdx,
		const MachineOperand *	MO = `nullptr`
	)		const

Check if MO is a legal operand if it was the OpIdx Operand for MI.

Definition at line 5093 of file SIInstrInfo.cpp.

References assert(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasMAIInsts(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), llvm::SIRegisterInfo::isAGPR(), isDS(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isInlineConstant(), isLegalRegOperand(), isMIMG(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVALU(), isVOP3(), MI, MRI, llvm::AMDGPU::OPERAND_KIMM32, llvm::MCOI::OPERAND_UNKNOWN, llvm::MCInstrDesc::operands(), llvm::MCOperandInfo::OperandType, llvm::MCOperandInfo::RegClass, and usesConstantBus().

Referenced by commuteInstructionImpl(), convertToThreeAddress(), and legalizeOperandsVOP3().

◆ isPacked() [1/2]

static bool llvm::SIInstrInfo::isPacked ( const MachineInstr & MI )

inlinestatic

Definition at line 418 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsPacked, and MI.

◆ isPacked() [2/2]

bool llvm::SIInstrInfo::isPacked ( uint16_t Opcode ) const

inline

Definition at line 422 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::IsPacked.

◆ isReallyTriviallyReMaterializable()

bool SIInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr & MI ) const

override

Definition at line 108 of file SIInstrInfo.cpp.

References isSALU(), isSDWA(), isVOP1(), isVOP2(), isVOP3(), and MI.

◆ isSALU() [1/2]

static bool llvm::SIInstrInfo::isSALU ( const MachineInstr & MI )

inlinestatic

Definition at line 354 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SALU.

Referenced by getInstSizeInBytes(), isReallyTriviallyReMaterializable(), mayReadEXEC(), and shouldReadExec().

◆ isSALU() [2/2]

bool llvm::SIInstrInfo::isSALU ( uint16_t Opcode ) const

inline

Definition at line 358 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SALU.

◆ isScalarStore() [1/2]

static bool llvm::SIInstrInfo::isScalarStore ( const MachineInstr & MI )

inlinestatic

Returns: true if this is an s_store_dword* instruction. This is more specific than isSMEM && mayStore.

Definition at line 732 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SCALAR_STORE.

◆ isScalarStore() [2/2]

bool llvm::SIInstrInfo::isScalarStore ( uint16_t Opcode ) const

inline

Definition at line 736 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SCALAR_STORE.

◆ isScalarUnit()

static bool llvm::SIInstrInfo::isScalarUnit ( const MachineInstr & MI )

inlinestatic

Definition at line 710 of file SIInstrInfo.h.

References MI, llvm::SIInstrFlags::SALU, and llvm::SIInstrFlags::SMRD.

◆ isSchedulingBoundary()

bool SIInstrInfo::isSchedulingBoundary	(	const MachineInstr &	MI,
		const MachineBasicBlock *	MBB,
		const MachineFunction &	MF
	)		const

override

Definition at line 3612 of file SIInstrInfo.cpp.

References changesVGPRIndexingMode(), and MI.

◆ isSDWA() [1/2]

static bool llvm::SIInstrInfo::isSDWA ( const MachineInstr & MI )

inlinestatic

Definition at line 450 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SDWA.

Referenced by isReallyTriviallyReMaterializable(), and verifyInstruction().

◆ isSDWA() [2/2]

bool llvm::SIInstrInfo::isSDWA ( uint16_t Opcode ) const

inline

Definition at line 454 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SDWA.

◆ isSegmentSpecificFLAT() [1/2]

static bool llvm::SIInstrInfo::isSegmentSpecificFLAT ( const MachineInstr & MI )

inlinestatic

Definition at line 524 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatGlobal, llvm::SIInstrFlags::FlatScratch, and MI.

Referenced by areMemAccessesTriviallyDisjoint(), legalizeOperandsFLAT(), moveFlatAddrToVGPR(), and shouldRunLdsBranchVmemWARHazardFixup().

◆ isSegmentSpecificFLAT() [2/2]

bool llvm::SIInstrInfo::isSegmentSpecificFLAT ( uint16_t Opcode ) const

inline

Definition at line 529 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FlatGlobal, llvm::SIInstrFlags::FlatScratch, and llvm::get().

◆ isSGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isSGPRSpill ( const MachineInstr & MI )

inlinestatic

Definition at line 621 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SGPRSpill.

Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isSGPRSpill() [2/2]

bool llvm::SIInstrInfo::isSGPRSpill ( uint16_t Opcode ) const

inline

Definition at line 625 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SGPRSpill.

◆ isSGPRStackAccess()

unsigned SIInstrInfo::isSGPRStackAccess	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

Definition at line 7548 of file SIInstrInfo.cpp.

References Addr, assert(), getNamedOperand(), llvm::MachineOperand::getReg(), and MI.

Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isSMRD() [1/2]

static bool llvm::SIInstrInfo::isSMRD ( const MachineInstr & MI )

inlinestatic

Definition at line 482 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SMRD.

Referenced by areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), breaksSMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), getMemOperandsWithOffsetWidth(), hasUnwantedEffectsWhenEXECEmpty(), isBufferSMRD(), isLowLatencyInstruction(), isSMEMClauseInst(), legalizeOperands(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().

◆ isSMRD() [2/2]

bool llvm::SIInstrInfo::isSMRD ( uint16_t Opcode ) const

inline

Definition at line 486 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SMRD.

◆ isSOP1() [1/2]

static bool llvm::SIInstrInfo::isSOP1 ( const MachineInstr & MI )

inlinestatic

Definition at line 378 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOP1.

◆ isSOP1() [2/2]

bool llvm::SIInstrInfo::isSOP1 ( uint16_t Opcode ) const

inline

Definition at line 382 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SOP1.

◆ isSOP2() [1/2]

static bool llvm::SIInstrInfo::isSOP2 ( const MachineInstr & MI )

inlinestatic

Definition at line 386 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOP2.

Referenced by verifyInstruction().

◆ isSOP2() [2/2]

bool llvm::SIInstrInfo::isSOP2 ( uint16_t Opcode ) const

inline

Definition at line 390 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SOP2.

◆ isSOPC() [1/2]

static bool llvm::SIInstrInfo::isSOPC ( const MachineInstr & MI )

inlinestatic

Definition at line 394 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOPC.

Referenced by verifyInstruction().

◆ isSOPC() [2/2]

bool llvm::SIInstrInfo::isSOPC ( uint16_t Opcode ) const

inline

Definition at line 398 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SOPC.

◆ isSOPK() [1/2]

static bool llvm::SIInstrInfo::isSOPK ( const MachineInstr & MI )

inlinestatic

Definition at line 402 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOPK.

Referenced by verifyInstruction().

◆ isSOPK() [2/2]

bool llvm::SIInstrInfo::isSOPK ( uint16_t Opcode ) const

inline

Definition at line 406 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SOPK.

◆ isSOPP() [1/2]

static bool llvm::SIInstrInfo::isSOPP ( const MachineInstr & MI )

inlinestatic

Definition at line 410 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOPP.

◆ isSOPP() [2/2]

bool llvm::SIInstrInfo::isSOPP ( uint16_t Opcode ) const

inline

Definition at line 414 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SOPP.

◆ isStackAccess()

unsigned SIInstrInfo::isStackAccess	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

Definition at line 7535 of file SIInstrInfo.cpp.

References Addr, assert(), getNamedOperand(), llvm::MachineOperand::getReg(), MI, and llvm::AMDGPUAS::PRIVATE_ADDRESS.

Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isStoreToStackSlot()

unsigned SIInstrInfo::isStoreToStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

Definition at line 7570 of file SIInstrInfo.cpp.

References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and MI.

◆ isTRANS() [1/2]

static bool llvm::SIInstrInfo::isTRANS ( const MachineInstr & MI )

inlinestatic

Definition at line 637 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::TRANS.

◆ isTRANS() [2/2]

bool llvm::SIInstrInfo::isTRANS ( uint16_t Opcode ) const

inline

Definition at line 641 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::TRANS.

◆ isVALU() [1/2]

static bool llvm::SIInstrInfo::isVALU ( const MachineInstr & MI )

inlinestatic

Definition at line 362 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VALU.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), isIgnorableUse(), isLdsDma(), isOperandLegal(), mayWriteLDSThroughDMA(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldReadExec(), and verifyInstruction().

◆ isVALU() [2/2]

bool llvm::SIInstrInfo::isVALU ( uint16_t Opcode ) const

inline

Definition at line 366 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VALU.

◆ isVGPRCopy()

bool llvm::SIInstrInfo::isVGPRCopy ( const MachineInstr & MI ) const

inline

Definition at line 792 of file SIInstrInfo.h.

References assert(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::isSGPRReg(), MI, and MRI.

Referenced by FoldImmediate().

◆ isVGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isVGPRSpill ( const MachineInstr & MI )

inlinestatic

Definition at line 613 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VGPRSpill.

Referenced by isLoadFromStackSlot(), isStoreToStackSlot(), and verifyInstruction().

◆ isVGPRSpill() [2/2]

bool llvm::SIInstrInfo::isVGPRSpill ( uint16_t Opcode ) const

inline

Definition at line 617 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VGPRSpill.

◆ isVINTERP() [1/2]

static bool llvm::SIInstrInfo::isVINTERP ( const MachineInstr & MI )

inlinestatic

Definition at line 702 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VINTERP.

◆ isVINTERP() [2/2]

bool llvm::SIInstrInfo::isVINTERP ( uint16_t Opcode ) const

inline

Definition at line 706 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VINTERP.

◆ isVINTRP() [1/2]

static bool llvm::SIInstrInfo::isVINTRP ( const MachineInstr & MI )

inlinestatic

Definition at line 653 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VINTRP.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isVINTRP() [2/2]

bool llvm::SIInstrInfo::isVINTRP ( uint16_t Opcode ) const

inline

Definition at line 657 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VINTRP.

◆ isVMEM() [1/2]

static bool llvm::SIInstrInfo::isVMEM ( const MachineInstr & MI )

inlinestatic

Definition at line 370 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), isMUBUF(), and MI.

Referenced by breaksVMEMSoftClause(), llvm::GCNHazardRecognizer::getHazardType(), isVMEMClauseInst(), isVMEMLoad(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and shouldRunLdsBranchVmemWARHazardFixup().

◆ isVMEM() [2/2]

bool llvm::SIInstrInfo::isVMEM ( uint16_t Opcode ) const

inline

Definition at line 374 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), and isMUBUF().

◆ isVOP1() [1/2]

static bool llvm::SIInstrInfo::isVOP1 ( const MachineInstr & MI )

inlinestatic

Definition at line 426 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOP1.

Referenced by isReallyTriviallyReMaterializable().

◆ isVOP1() [2/2]

bool llvm::SIInstrInfo::isVOP1 ( uint16_t Opcode ) const

inline

Definition at line 430 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VOP1.

◆ isVOP2() [1/2]

static bool llvm::SIInstrInfo::isVOP2 ( const MachineInstr & MI )

inlinestatic

Definition at line 434 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOP2.

Referenced by isReallyTriviallyReMaterializable(), legalizeOperands(), and verifyInstruction().

◆ isVOP2() [2/2]

bool llvm::SIInstrInfo::isVOP2 ( uint16_t Opcode ) const

inline

Definition at line 438 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VOP2.

◆ isVOP3() [1/2]

static bool llvm::SIInstrInfo::isVOP3 ( const MachineInstr & MI )

inlinestatic

Definition at line 442 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOP3.

Referenced by isImmOperandLegal(), isOperandLegal(), isReallyTriviallyReMaterializable(), legalizeOperands(), and verifyInstruction().

◆ isVOP3() [2/2]

bool llvm::SIInstrInfo::isVOP3 ( uint16_t Opcode ) const

inline

Definition at line 446 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VOP3.

◆ isVOP3P() [1/2]

static bool llvm::SIInstrInfo::isVOP3P ( const MachineInstr & MI )

inlinestatic

Definition at line 645 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOP3P.

◆ isVOP3P() [2/2]

bool llvm::SIInstrInfo::isVOP3P ( uint16_t Opcode ) const

inline

Definition at line 649 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VOP3P.

◆ isVOPC() [1/2]

static bool llvm::SIInstrInfo::isVOPC ( const MachineInstr & MI )

inlinestatic

Definition at line 458 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VOPC.

Referenced by legalizeOperands(), and verifyInstruction().

◆ isVOPC() [2/2]

bool llvm::SIInstrInfo::isVOPC ( uint16_t Opcode ) const

inline

Definition at line 462 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::VOPC.

◆ isWave32()

bool llvm::SIInstrInfo::isWave32 ( ) const

Definition at line 8310 of file SIInstrInfo.cpp.

References llvm::GCNSubtarget::isWave32().

◆ isWMMA() [1/2]

static bool llvm::SIInstrInfo::isWMMA ( const MachineInstr & MI )

inlinestatic

Definition at line 678 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsWMMA, and MI.

Referenced by convertToThreeAddress(), and isMFMAorWMMA().

◆ isWMMA() [2/2]

bool llvm::SIInstrInfo::isWMMA ( uint16_t Opcode ) const

inline

Definition at line 682 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::IsWMMA.

◆ isWQM() [1/2]

static bool llvm::SIInstrInfo::isWQM ( const MachineInstr & MI )

inlinestatic

Definition at line 597 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::WQM.

◆ isWQM() [2/2]

bool llvm::SIInstrInfo::isWQM ( uint16_t Opcode ) const

inline

Definition at line 601 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::WQM.

◆ legalizeGenericOperand()

void SIInstrInfo::legalizeGenericOperand	(	MachineBasicBlock &	InsertMBB,
		MachineBasicBlock::iterator	I,
		const TargetRegisterClass *	DstRC,
		MachineOperand &	Op,
		MachineRegisterInfo &	MRI,
		const DebugLoc &	DL
	)		const

Definition at line 5545 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), DL, FoldImmediate(), llvm::get(), llvm::SIRegisterInfo::getRegClassForReg(), I, llvm::RegState::Implicit, llvm::SIRegisterInfo::isSGPRClass(), and MRI.

Referenced by legalizeOperands().

◆ legalizeOperands()

MachineBasicBlock * SIInstrInfo::legalizeOperands	(	MachineInstr &	MI,
		MachineDominatorTree *	MDT = `nullptr`
	)		const

Legalize all operands in this instruction.

This function may create new instructions and control-flow around MI. If present, MDT is updated.

Returns: A new basic block that contains MI if new blocks were created.

Definition at line 5829 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::RegState::Dead, DL, E, llvm::MachineBasicBlock::end(), extractRsrcPtr(), llvm::get(), llvm::AMDGPU::getAddr64Inst(), llvm::Function::getCallingConv(), llvm::MachineInstr::getDebugLoc(), llvm::SIRegisterInfo::getEquivalentAGPRClass(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFunction(), llvm::GCNSubtarget::getGeneration(), llvm::AMDGPU::getIfAddr64Inst(), getNamedImmOperand(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), getOpRegClass(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::GCNSubtarget::hasAddr64(), llvm::SIRegisterInfo::hasVectorRegisters(), llvm::SIRegisterInfo::hasVGPRs(), I, llvm::SIRegisterInfo::isAGPRClass(), isFLAT(), llvm::AMDGPU::isGraphics(), isMIMG(), isMTBUF(), isMUBUF(), llvm::SIRegisterInfo::isSGPRClass(), isSMRD(), isVOP2(), isVOP3(), isVOPC(), llvm::RegState::Kill, legalizeGenericOperand(), legalizeOperandsFLAT(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), loadSRsrcFromVGPR(), MBB, MI, MRI, llvm::Offset, readlaneVGPRToSGPR(), llvm::MachineOperand::setReg(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by FoldImmediate(), and moveToVALU().

◆ legalizeOperandsFLAT()

void SIInstrInfo::legalizeOperandsFLAT	(	MachineRegisterInfo &	MRI,
		MachineInstr &	MI
	)		const

Definition at line 5527 of file SIInstrInfo.cpp.

References getNamedOperand(), llvm::MachineOperand::getReg(), isSegmentSpecificFLAT(), llvm::SIRegisterInfo::isSGPRClass(), MI, moveFlatAddrToVGPR(), MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().

Referenced by legalizeOperands().

◆ legalizeOperandsSMRD()

void SIInstrInfo::legalizeOperandsSMRD	(	MachineRegisterInfo &	MRI,
		MachineInstr &	MI
	)		const

Definition at line 5427 of file SIInstrInfo.cpp.

References getNamedOperand(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::isSGPRClass(), MI, MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().

Referenced by legalizeOperands().

◆ legalizeOperandsVOP2()

void SIInstrInfo::legalizeOperandsVOP2	(	MachineRegisterInfo &	MRI,
		MachineInstr &	MI
	)		const

Legalize operands in MI by either commuting it or inserting a copy of src1.

Definition at line 5188 of file SIInstrInfo.cpp.

Referenced by legalizeOperands().

◆ legalizeOperandsVOP3()

void SIInstrInfo::legalizeOperandsVOP3	(	MachineRegisterInfo &	MRI,
		MachineInstr &	MI
	)		const

Fix operands in MI to satisfy constant bus requirements.

Definition at line 5299 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::count(), DL, llvm::get(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::SIRegisterInfo::hasAGPRs(), llvm::GCNSubtarget::hasVOP3Literal(), Idx, llvm::detail::DenseSetImpl< ValueT, MapTy, ValueInfoT >::insert(), isInlineConstant(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), legalizeOpWithMove(), MI, and MRI.

Referenced by legalizeOperands().

◆ legalizeOpWithMove()

void SIInstrInfo::legalizeOpWithMove	(	MachineInstr &	MI,
		unsigned	OpIdx
	)		const

Legalize the OpIndex operand of this instruction by inserting a MOV.

For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1

If the operand being legalized is a register, then a COPY will be used instead of MOV.

Definition at line 4967 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getVGPR64Class(), I, llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), MBB, MI, MRI, and Size.

Referenced by legalizeOperandsVOP2(), and legalizeOperandsVOP3().

◆ loadRegFromStackSlot()

void SIInstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		Register	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		Register	VReg
	)		const

override

Definition at line 1777 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), getAGPRSpillRestoreOpcode(), getAVSpillRestoreOpcode(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getSGPRSpillRestoreOpcode(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVGPRSpillRestoreOpcode(), llvm::RegState::Implicit, llvm::SIRegisterInfo::isAGPRClass(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isVectorSuperClass(), llvm::Register::isVirtual(), MBB, MI, llvm::MachineMemOperand::MOLoad, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::TargetStackID::SGPRSpill, llvm::SIRegisterInfo::spillSGPRToVGPR(), and TRI.

◆ materializeImmediate()

void SIInstrInfo::materializeImmediate	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		Register	DestReg,
		int64_t	Value
	)		const

Definition at line 1068 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), Builder, llvm::BuildMI(), DL, llvm::get(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::TargetRegisterClass::hasSuperClassEq(), Idx, llvm::SIRegisterInfo::isSGPRClass(), MBB, MI, MRI, and llvm::ArrayRef< T >::size().

Referenced by convertNonUniformLoopRegion().

◆ mayAccessFlatAddressSpace()

bool SIInstrInfo::mayAccessFlatAddressSpace ( const MachineInstr & MI ) const

Definition at line 7657 of file SIInstrInfo.cpp.

References llvm::AMDGPUAS::FLAT_ADDRESS, isFLAT(), and MI.

◆ mayReadEXEC()

bool SIInstrInfo::mayReadEXEC	(	const MachineRegisterInfo &	MRI,
		const MachineInstr &	MI
	)		const

Returns true if the instruction could potentially depend on the value of exec.

If false, exec dependencies may safely be ignored.

Definition at line 3701 of file SIInstrInfo.cpp.

References isSALU(), llvm::SIRegisterInfo::isSGPRReg(), llvm::isTargetSpecificOpcode(), MI, and MRI.

◆ modifiesModeRegister()

bool SIInstrInfo::modifiesModeRegister ( const MachineInstr & MI )

static

Return true if the instruction modifies the mode register.q.

Definition at line 3653 of file SIInstrInfo.cpp.

References llvm::is_contained(), and MI.

Referenced by hasUnwantedEffectsWhenEXECEmpty().

◆ moveFlatAddrToVGPR()

bool SIInstrInfo::moveFlatAddrToVGPR ( MachineInstr & Inst ) const

Change SADDR form of a FLAT Inst to its VADDR form if saddr operand was moved to VGPR.

Returns: true if succeeded.

Definition at line 5446 of file SIInstrInfo.cpp.

References assert(), llvm::MachineInstr::eraseFromParent(), llvm::get(), llvm::AMDGPU::getFlatScratchInstSVfromSS(), llvm::AMDGPU::getGlobalVaddrOp(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getMF(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isImm(), isSegmentSpecificFLAT(), llvm::SIRegisterInfo::isSGPRReg(), MRI, llvm::MachineInstr::removeOperand(), llvm::MachineInstr::setDesc(), llvm::MachineInstr::tieOperands(), and llvm::MachineInstr::untieRegOperand().

Referenced by legalizeOperandsFLAT().

◆ moveToVALU()

MachineBasicBlock * SIInstrInfo::moveToVALU	(	MachineInstr &	MI,
		MachineDominatorTree *	MDT = `nullptr`
	)		const

Replace this instruction's opcode with the equivalent VALU opcode.

This function will also move the users of MI to the VALU if necessary. If present, MDT is updated.

Definition at line 6155 of file SIInstrInfo.cpp.

◆ optimizeCompareInstr()

bool SIInstrInfo::optimizeCompareInstr	(	MachineInstr &	CmpInstr,
		Register	SrcReg,
		Register	SrcReg2,
		int64_t	CmpMask,
		int64_t	CmpValue,
		const MachineRegisterInfo *	MRI
	)		const

override

◆ pseudoToMCOpcode()

int SIInstrInfo::pseudoToMCOpcode ( int Opcode ) const

Return a target-specific opcode if Opcode is a pseudo instruction.

Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.

Definition at line 8044 of file SIInstrInfo.cpp.

References llvm::SIInstrFlags::D16Buf, llvm::get(), llvm::GCNSubtarget::getGeneration(), llvm::AMDGPU::getMCOpcode(), llvm::AMDGPU::getMFMAEarlyClobberOp(), llvm::AMDGPUSubtarget::GFX10, llvm::AMDGPUSubtarget::GFX9, llvm::GCNSubtarget::hasGFX90AInsts(), llvm::GCNSubtarget::hasGFX940Insts(), llvm::GCNSubtarget::hasUnpackedD16VMem(), isAsmOnlyOpcode(), isMAI(), llvm::SIInstrFlags::renamedInGFX9, llvm::SIInstrFlags::SDWA, subtargetEncodingFamily(), and TSFlags.

Referenced by commuteOpcode(), convertToThreeAddress(), FoldImmediate(), getMCOpcodeFromPseudo(), llvm::GCNSubtarget::hasMadF16(), and hasVALU32BitEncoding().

◆ readlaneVGPRToSGPR()

Register SIInstrInfo::readlaneVGPRToSGPR	(	Register	SrcReg,
		MachineInstr &	UseMI,
		MachineRegisterInfo &	MRI
	)		const

Copy a value from a VGPR (SrcReg) to SGPR.

This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.

Returns: The SGPR register that SrcReg was copied to.

Definition at line 5385 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::get(), llvm::SIRegisterInfo::getEquivalentSGPRClass(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::SIRegisterInfo::getSubRegFromChannel(), llvm::SIRegisterInfo::hasAGPRs(), MRI, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and UseMI.

Referenced by legalizeOperands(), legalizeOperandsFLAT(), and legalizeOperandsSMRD().

◆ removeBranch()

unsigned SIInstrInfo::removeBranch	(	MachineBasicBlock &	MBB,
		int *	BytesRemoved = `nullptr`
	)		const

override

Definition at line 2748 of file SIInstrInfo.cpp.

References getInstSizeInBytes(), llvm::make_early_inc_range(), MBB, MI, and llvm::MachineBasicBlock::terminators().

◆ removeModOperands()

void SIInstrInfo::removeModOperands ( MachineInstr & MI ) const

Definition at line 3021 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), Idx, MI, ModifierOpNames, Name, and llvm::reverse().

Referenced by FoldImmediate().

◆ reverseBranchCondition()

bool SIInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

override

Definition at line 2834 of file SIInstrInfo.cpp.

References Cond, and isImm().

◆ shouldClusterMemOps()

bool SIInstrInfo::shouldClusterMemOps	(	ArrayRef< const MachineOperand * >	BaseOps1,
		ArrayRef< const MachineOperand * >	BaseOps2,
		unsigned	NumLoads,
		unsigned	NumBytes
	)		const

override

Definition at line 481 of file SIInstrInfo.cpp.

References llvm::ArrayRef< T >::empty(), llvm::ArrayRef< T >::front(), and memOpsHaveSameBasePtr().

◆ shouldScheduleLoadsNear()

bool SIInstrInfo::shouldScheduleLoadsNear	(	SDNode *	Load0,
		SDNode *	Load1,
		int64_t	Offset0,
		int64_t	Offset1,
		unsigned	NumLoads
	)		const

override

Definition at line 524 of file SIInstrInfo.cpp.

References assert().

◆ sopkIsZext() [1/2]

static bool llvm::SIInstrInfo::sopkIsZext ( const MachineInstr & MI )

inlinestatic

Definition at line 722 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::SOPK_ZEXT.

Referenced by verifyInstruction().

◆ sopkIsZext() [2/2]

bool llvm::SIInstrInfo::sopkIsZext ( uint16_t Opcode ) const

inline

Definition at line 726 of file SIInstrInfo.h.

References llvm::get(), and llvm::SIInstrFlags::SOPK_ZEXT.

◆ splitFlatOffset()

std::pair< int64_t, int64_t > SIInstrInfo::splitFlatOffset	(	int64_t	COffsetVal,
		unsigned	AddrSpace,
		uint64_t	FlatVariant
	)		const

Split COffsetVal into {immediate offset field, remainder offset} values.

Definition at line 7957 of file SIInstrInfo.cpp.

References assert(), D, llvm::SIInstrFlags::FLAT, llvm::SIInstrFlags::FlatScratch, llvm::AMDGPU::getNumFlatOffsetBits(), llvm::GCNSubtarget::hasNegativeScratchOffsetBug(), llvm::GCNSubtarget::hasNegativeUnalignedScratchOffsetBug(), and isLegalFLATOffset().

◆ storeRegToStackSlot()

void SIInstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		Register	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI,
		Register	VReg
	)		const

override

Definition at line 1578 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), DL, llvm::MachineBasicBlock::findDebugLoc(), llvm::get(), getAGPRSpillSaveOpcode(), getAVSpillSaveOpcode(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), getSGPRSpillSaveOpcode(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVGPRSpillSaveOpcode(), llvm::RegState::Implicit, llvm::SIRegisterInfo::isAGPRClass(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isVectorSuperClass(), llvm::Register::isVirtual(), MBB, MI, llvm::MachineMemOperand::MOStore, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::SIMachineFunctionInfo::setHasSpilledVGPRs(), llvm::TargetStackID::SGPRSpill, llvm::SIRegisterInfo::spillSGPRToVGPR(), and TRI.

◆ swapSourceModifiers()

bool SIInstrInfo::swapSourceModifiers	(	MachineInstr &	MI,
		MachineOperand &	Src0,
		unsigned	Src0OpName,
		MachineOperand &	Src1,
		unsigned	Src1OpName
	)		const

protected

Definition at line 2348 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), MI, and llvm::MachineOperand::setImm().

Referenced by commuteInstructionImpl().

◆ usesConstantBus()

bool SIInstrInfo::usesConstantBus	(	const MachineRegisterInfo &	MRI,
		const MachineOperand &	MO,
		const MCOperandInfo &	OpInfo
	)		const

Returns true if this operand uses the constant bus.

Definition at line 4022 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::MachineOperand::isUse(), llvm::Register::isVirtual(), and MRI.

Referenced by isOperandLegal(), and verifyInstruction().

◆ usesFPDPRounding() [1/2]

static bool llvm::SIInstrInfo::usesFPDPRounding ( const MachineInstr & MI )

inlinestatic

Definition at line 768 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPDPRounding, and MI.

◆ usesFPDPRounding() [2/2]

bool llvm::SIInstrInfo::usesFPDPRounding ( uint16_t Opcode ) const

inline

Definition at line 772 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPDPRounding, and llvm::get().

◆ usesLGKM_CNT()

static bool llvm::SIInstrInfo::usesLGKM_CNT ( const MachineInstr & MI )

inlinestatic

Definition at line 718 of file SIInstrInfo.h.

References llvm::SIInstrFlags::LGKM_CNT, and MI.

◆ usesVM_CNT()

static bool llvm::SIInstrInfo::usesVM_CNT ( const MachineInstr & MI )

inlinestatic

Definition at line 714 of file SIInstrInfo.h.

References MI, and llvm::SIInstrFlags::VM_CNT.

◆ verifyInstruction()

bool SIInstrInfo::verifyInstruction	(	const MachineInstr &	MI,
		StringRef &	ErrInfo
	)		const

override

Definition at line 4102 of file SIInstrInfo.cpp.

Referenced by llvm::AMDGPUAsmPrinter::emitInstruction().

The documentation for this class was generated from the following files:

lib/Target/AMDGPU/SIInstrInfo.h
lib/Target/AMDGPU/SIInstrInfo.cpp

Public Types

Public Member Functions

Static Public Member Functions

Protected Member Functions

Detailed Description

Member Enumeration Documentation

◆ TargetOperandFlags

Constructor & Destructor Documentation

◆ SIInstrInfo()

Member Function Documentation

◆ analyzeBranch()

◆ analyzeBranchImpl()

◆ analyzeCompare()

◆ areLoadsFromSameBasePtr()

◆ areMemAccessesTriviallyDisjoint()

◆ buildExtractSubReg()

◆ buildExtractSubRegOrImm()

◆ buildShrunkInst()

◆ canInsertSelect()

◆ canShrink()

◆ commuteInstructionImpl()

◆ commuteOpcode() [1/2]

◆ commuteOpcode() [2/2]

◆ convertNonUniformIfRegion()

◆ convertNonUniformLoopRegion()

◆ convertToThreeAddress()

◆ copyPhysReg()

◆ createPHIDestinationCopy()

◆ createPHISourceCopy()

◆ CreateTargetMIHazardRecognizer()

◆ CreateTargetPostRAHazardRecognizer() [1/2]

◆ CreateTargetPostRAHazardRecognizer() [2/2]

◆ decomposeMachineOperandsTargetFlags()

◆ doesNotReadTiedSource() [1/2]

◆ doesNotReadTiedSource() [2/2]

◆ enforceOperandRCAlignment()

◆ expandMovDPP64()

◆ expandPostRAPseudo()

◆ findCommutedOpIndices() [1/2]

◆ findCommutedOpIndices() [2/2]

◆ fixImplicitOperands()

◆ FoldImmediate()

◆ foldMemoryOperandImpl()

◆ getAddNoCarry() [1/2]

◆ getAddNoCarry() [2/2]

◆ getBranchDestBlock()

◆ getClampMask()

◆ getDefaultRsrcDataFormat()

◆ getDSShaderTypeValue()

◆ getGenericInstructionUniformity()

◆ getIndirectGPRIDXPseudo()

◆ getIndirectRegWriteMovRelPseudo()

◆ getInstBundleSize()

◆ getInstrLatency()

◆ getInstructionUniformity()

◆ getInstSizeInBytes()

◆ getKillTerminatorFromPseudo()

◆ getMachineCSELookAheadLimit()

◆ getMCOpcodeFromPseudo()

◆ getMemOperandsWithOffsetWidth()

◆ getMIRFormatter()

◆ getMovOpcode()

◆ getNamedImmOperand()

◆ getNamedOperand() [1/2]

◆ getNamedOperand() [2/2]

◆ getNumWaitStates()

◆ getOpRegClass()

◆ getOpSize() [1/2]

◆ getOpSize() [2/2]

◆ getPreferredSelectRegClass()

◆ getRegClass()

◆ getRegisterInfo()

◆ getSchedModel()

◆ getScratchRsrcWords23()

◆ getSerializableDirectMachineOperandTargetFlags()

◆ getSerializableMachineMemOperandTargetFlags()

◆ getSerializableTargetIndices()

◆ getSubtarget()

◆ getVALUOp()

◆ hasAnyModifiersSet()