#include "Target/AMDGPU/SIInstrInfo.h"

Inheritance diagram for llvm::SIInstrInfo:

Collaboration diagram for llvm::SIInstrInfo:

Public Types
enum	TargetOperandFlags { MO_MASK = 0xf, MO_NONE = 0, MO_GOTPCREL = 1, MO_GOTPCREL32 = 2, MO_GOTPCREL32_LO = 2, MO_GOTPCREL32_HI = 3, MO_REL32 = 4, MO_REL32_LO = 4, MO_REL32_HI = 5, MO_LONG_BRANCH_FORWARD = 6, MO_LONG_BRANCH_BACKWARD = 7, MO_ABS32_LO = 8, MO_ABS32_HI = 9 }

Public Member Functions
unsigned	buildExtractSubReg (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass SuperRC, unsigned SubIdx, const TargetRegisterClass SubRC) const

MachineOperand	buildExtractSubRegOrImm (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass SuperRC, unsigned SubIdx, const TargetRegisterClass SubRC) const

	SIInstrInfo (const GCNSubtarget &ST)

const SIRegisterInfo &	getRegisterInfo () const

bool	isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override

bool	areLoadsFromSameBasePtr (SDNode Load1, SDNode Load2, int64_t &Offset1, int64_t &Offset2) const override

bool	getMemOperandWithOffset (const MachineInstr &LdSt, const MachineOperand &BaseOp, int64_t &Offset, const TargetRegisterInfo TRI) const final

bool	shouldClusterMemOps (const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const override

bool	shouldScheduleLoadsNear (SDNode Load0, SDNode Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override

void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override

unsigned	calculateLDSSpillAddress (MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const

void	materializeImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const

const TargetRegisterClass *	getPreferredSelectRegClass (unsigned Size) const

unsigned	insertNE (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const

unsigned	insertEQ (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const

void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI) const override

void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass RC, const TargetRegisterInfo TRI) const override

bool	expandPostRAPseudo (MachineInstr &MI) const override

unsigned	getMovOpcode (const TargetRegisterClass *DstRC) const

LLVM_READONLY int	commuteOpcode (unsigned Opc) const

LLVM_READONLY int	commuteOpcode (const MachineInstr &MI) const

bool	findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override

bool	findCommutedOpIndices (MCInstrDesc Desc, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const

bool	isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override

MachineBasicBlock *	getBranchDestBlock (const MachineInstr &MI) const override

unsigned	insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override

bool	analyzeBranchImpl (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const

bool	analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock &TBB, MachineBasicBlock &FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override

unsigned	removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override

unsigned	insertBranch (MachineBasicBlock &MBB, MachineBasicBlock TBB, MachineBasicBlock FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override

bool	reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override

bool	canInsertSelect (const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override

void	insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override

void	insertVectorSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const

unsigned	getAddressSpaceForPseudoSourceKind (unsigned Kind) const override

bool	areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override

bool	isFoldableCopy (const MachineInstr &MI) const

bool	FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final

unsigned	getMachineCSELookAheadLimit () const override

MachineInstr *	convertToThreeAddress (MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override

bool	isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override

bool	isSALU (uint16_t Opcode) const

bool	isVALU (uint16_t Opcode) const

bool	isVMEM (uint16_t Opcode) const

bool	isSOP1 (uint16_t Opcode) const

bool	isSOP2 (uint16_t Opcode) const

bool	isSOPC (uint16_t Opcode) const

bool	isSOPK (uint16_t Opcode) const

bool	isSOPP (uint16_t Opcode) const

bool	isPacked (uint16_t Opcode) const

bool	isVOP1 (uint16_t Opcode) const

bool	isVOP2 (uint16_t Opcode) const

bool	isVOP3 (uint16_t Opcode) const

bool	isSDWA (uint16_t Opcode) const

bool	isVOPC (uint16_t Opcode) const

bool	isMUBUF (uint16_t Opcode) const

bool	isMTBUF (uint16_t Opcode) const

bool	isSMRD (uint16_t Opcode) const

bool	isBufferSMRD (const MachineInstr &MI) const

bool	isDS (uint16_t Opcode) const

bool	isAlwaysGDS (uint16_t Opcode) const

bool	isMIMG (uint16_t Opcode) const

bool	isGather4 (uint16_t Opcode) const

bool	isFLAT (uint16_t Opcode) const

bool	isEXP (uint16_t Opcode) const

bool	isWQM (uint16_t Opcode) const

bool	isDisableWQM (uint16_t Opcode) const

bool	isVGPRSpill (uint16_t Opcode) const

bool	isSGPRSpill (uint16_t Opcode) const

bool	isDPP (uint16_t Opcode) const

bool	isVOP3P (uint16_t Opcode) const

bool	isVINTRP (uint16_t Opcode) const

bool	isMAI (uint16_t Opcode) const

bool	isDOT (uint16_t Opcode) const

bool	sopkIsZext (uint16_t Opcode) const

bool	isScalarStore (uint16_t Opcode) const

bool	isFixedSize (uint16_t Opcode) const

bool	hasFPClamp (uint16_t Opcode) const

uint64_t	getClampMask (const MachineInstr &MI) const

bool	usesFPDPRounding (uint16_t Opcode) const

bool	isFPAtomic (uint16_t Opcode) const

bool	isVGPRCopy (const MachineInstr &MI) const

bool	hasVGPRUses (const MachineInstr &MI) const

bool	hasUnwantedEffectsWhenEXECEmpty (const MachineInstr &MI) const
	Whether we must prevent this instruction from executing with EXEC = 0. More...

bool	mayReadEXEC (const MachineRegisterInfo &MRI, const MachineInstr &MI) const
	Returns true if the instruction could potentially depend on the value of exec. More...

bool	isInlineConstant (const APInt &Imm) const

bool	isInlineConstant (const MachineOperand &MO, uint8_t OperandType) const

bool	isInlineConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const

bool	isInlineConstant (const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
	`returns` true if `UseMO` is substituted with `DefMO` in `MI` it would be an inline immediate. More...

bool	isInlineConstant (const MachineInstr &MI, unsigned OpIdx) const
	`returns` true if the operand `OpIdx` in `MI` is a valid inline immediate. More...

bool	isInlineConstant (const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const

bool	isInlineConstant (const MachineOperand &MO) const

bool	isLiteralConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const

bool	isLiteralConstant (const MachineInstr &MI, int OpIdx) const

bool	isLiteralConstantLike (const MachineOperand &MO, const MCOperandInfo &OpInfo) const

bool	isImmOperandLegal (const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const

bool	hasVALU32BitEncoding (unsigned Opcode) const
	Return true if this 64-bit VALU instruction has a 32-bit encoding. More...

bool	usesConstantBus (const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
	Returns true if this operand uses the constant bus. More...

bool	hasModifiers (unsigned Opcode) const
	Return true if this instruction has any modifiers. More...

bool	hasModifiersSet (const MachineInstr &MI, unsigned OpName) const

bool	hasAnyModifiersSet (const MachineInstr &MI) const

bool	canShrink (const MachineInstr &MI, const MachineRegisterInfo &MRI) const

MachineInstr *	buildShrunkInst (MachineInstr &MI, unsigned NewOpcode) const

bool	verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override

unsigned	getVALUOp (const MachineInstr &MI) const

const TargetRegisterClass *	getOpRegClass (const MachineInstr &MI, unsigned OpNo) const
	Return the correct register class for `OpNo`. More...

unsigned	getOpSize (uint16_t Opcode, unsigned OpNo) const
	Return the size in bytes of the operand OpNo on the given. More...

unsigned	getOpSize (const MachineInstr &MI, unsigned OpNo) const
	This form should usually be preferred since it handles operands with unknown register classes. More...

void	legalizeOpWithMove (MachineInstr &MI, unsigned OpIdx) const
	Legalize the `OpIndex` operand of this instruction by inserting a MOV. More...

bool	isOperandLegal (const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
	Check if `MO` is a legal operand if it was the `OpIdx` Operand for `MI`. More...

bool	isLegalVSrcOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
	Check if `MO` would be a valid operand for the given operand definition `OpInfo`. More...

bool	isLegalRegOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
	Check if `MO` (a register operand) is a legal register for the given operand description. More...

void	legalizeOperandsVOP2 (MachineRegisterInfo &MRI, MachineInstr &MI) const
	Legalize operands in `MI` by either commuting it or inserting a copy of src1. More...

void	legalizeOperandsVOP3 (MachineRegisterInfo &MRI, MachineInstr &MI) const
	Fix operands in `MI` to satisfy constant bus requirements. More...

unsigned	readlaneVGPRToSGPR (unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
	Copy a value from a VGPR (`SrcReg`) to SGPR. More...

void	legalizeOperandsSMRD (MachineRegisterInfo &MRI, MachineInstr &MI) const

void	legalizeGenericOperand (MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const

void	legalizeOperands (MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
	Legalize all operands in this instruction. More...

void	moveToVALU (MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
	Replace this instruction's opcode with the equivalent VALU opcode. More...

void	insertWaitStates (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const

void	insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override

void	insertReturn (MachineBasicBlock &MBB) const

LLVM_READONLY MachineOperand *	getNamedOperand (MachineInstr &MI, unsigned OperandName) const
	Returns the operand named `Op`. More...

LLVM_READONLY const MachineOperand *	getNamedOperand (const MachineInstr &MI, unsigned OpName) const

int64_t	getNamedImmOperand (const MachineInstr &MI, unsigned OpName) const
	Get required immediate operand. More...

uint64_t	getDefaultRsrcDataFormat () const

uint64_t	getScratchRsrcWords23 () const

bool	isLowLatencyInstruction (const MachineInstr &MI) const

bool	isHighLatencyInstruction (const MachineInstr &MI) const

const MCInstrDesc &	getMCOpcodeFromPseudo (unsigned Opcode) const
	Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode. More...

unsigned	isStackAccess (const MachineInstr &MI, int &FrameIndex) const

unsigned	isSGPRStackAccess (const MachineInstr &MI, int &FrameIndex) const

unsigned	isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override

unsigned	isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override

unsigned	getInstBundleSize (const MachineInstr &MI) const

unsigned	getInstSizeInBytes (const MachineInstr &MI) const override

bool	mayAccessFlatAddressSpace (const MachineInstr &MI) const

bool	isNonUniformBranchInstr (MachineInstr &Instr) const

void	convertNonUniformIfRegion (MachineBasicBlock IfEntry, MachineBasicBlock IfEnd) const

void	convertNonUniformLoopRegion (MachineBasicBlock LoopEntry, MachineBasicBlock LoopEnd) const

std::pair< unsigned, unsigned >	decomposeMachineOperandsTargetFlags (unsigned TF) const override

ArrayRef< std::pair< int, const char * > >	getSerializableTargetIndices () const override

ArrayRef< std::pair< unsigned, const char * > >	getSerializableDirectMachineOperandTargetFlags () const override

ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const InstrItineraryData II, const ScheduleDAG DAG) const override
	This is used by the post-RA scheduler (SchedulePostRAList.cpp). More...

ScheduleHazardRecognizer *	CreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const override
	This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass. More...

bool	isBasicBlockPrologue (const MachineInstr &MI) const override

MachineInstr *	createPHIDestinationCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register Dst) const override

MachineInstr *	createPHISourceCopy (MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, const DebugLoc &DL, Register Src, Register SrcSubReg, Register Dst) const override

bool	isWave32 () const

MachineInstrBuilder	getAddNoCarry (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) const
	Return a partially built integer add instruction without carry. More...

MachineInstrBuilder	getAddNoCarry (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, Register DestReg, RegScavenger &RS) const

const MCInstrDesc &	getKillTerminatorFromPseudo (unsigned Opcode) const

bool	isLegalFLATOffset (int64_t Offset, unsigned AddrSpace, bool Signed) const
	Returns if `Offset` is legal for the subtarget as the offset to a FLAT encoded instruction. More...

int	pseudoToMCOpcode (int Opcode) const
	Return a target-specific opcode if Opcode is a pseudo instruction. More...

const TargetRegisterClass *	getRegClass (const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const override

void	fixImplicitOperands (MachineInstr &MI) const

Static Public Member Functions
static bool	isSALU (const MachineInstr &MI)

static bool	isVALU (const MachineInstr &MI)

static bool	isVMEM (const MachineInstr &MI)

static bool	isSOP1 (const MachineInstr &MI)

static bool	isSOP2 (const MachineInstr &MI)

static bool	isSOPC (const MachineInstr &MI)

static bool	isSOPK (const MachineInstr &MI)

static bool	isSOPP (const MachineInstr &MI)

static bool	isPacked (const MachineInstr &MI)

static bool	isVOP1 (const MachineInstr &MI)

static bool	isVOP2 (const MachineInstr &MI)

static bool	isVOP3 (const MachineInstr &MI)

static bool	isSDWA (const MachineInstr &MI)

static bool	isVOPC (const MachineInstr &MI)

static bool	isMUBUF (const MachineInstr &MI)

static bool	isMTBUF (const MachineInstr &MI)

static bool	isSMRD (const MachineInstr &MI)

static bool	isDS (const MachineInstr &MI)

static bool	isMIMG (const MachineInstr &MI)

static bool	isGather4 (const MachineInstr &MI)

static bool	isFLAT (const MachineInstr &MI)

static bool	isSegmentSpecificFLAT (const MachineInstr &MI)

static bool	isFLATScratch (const MachineInstr &MI)

static bool	isEXP (const MachineInstr &MI)

static bool	isWQM (const MachineInstr &MI)

static bool	isDisableWQM (const MachineInstr &MI)

static bool	isVGPRSpill (const MachineInstr &MI)

static bool	isSGPRSpill (const MachineInstr &MI)

static bool	isDPP (const MachineInstr &MI)

static bool	isVOP3P (const MachineInstr &MI)

static bool	isVINTRP (const MachineInstr &MI)

static bool	isMAI (const MachineInstr &MI)

static bool	isDOT (const MachineInstr &MI)

static bool	isScalarUnit (const MachineInstr &MI)

static bool	usesVM_CNT (const MachineInstr &MI)

static bool	usesLGKM_CNT (const MachineInstr &MI)

static bool	sopkIsZext (const MachineInstr &MI)

static bool	isScalarStore (const MachineInstr &MI)

static bool	isFixedSize (const MachineInstr &MI)

static bool	hasFPClamp (const MachineInstr &MI)

static bool	hasIntClamp (const MachineInstr &MI)

static bool	usesFPDPRounding (const MachineInstr &MI)

static bool	isFPAtomic (const MachineInstr &MI)

static unsigned	getNumWaitStates (const MachineInstr &MI)
	Return the number of wait states that result from executing this instruction. More...

static bool	isKillTerminator (unsigned Opcode)

static bool	isLegalMUBUFImmOffset (unsigned Imm)

Protected Member Functions
bool	swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const

MachineInstr *	commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override

Detailed Description

Definition at line 45 of file SIInstrInfo.h.

Member Enumeration Documentation

◆ TargetOperandFlags

enum llvm::SIInstrInfo::TargetOperandFlags

Enumerator
MO_MASK
MO_NONE
MO_GOTPCREL
MO_GOTPCREL32
MO_GOTPCREL32_LO
MO_GOTPCREL32_HI
MO_REL32
MO_REL32_LO
MO_REL32_HI
MO_LONG_BRANCH_FORWARD
MO_LONG_BRANCH_BACKWARD
MO_ABS32_LO
MO_ABS32_HI

Definition at line 145 of file SIInstrInfo.h.

Constructor & Destructor Documentation

◆ SIInstrInfo()

SIInstrInfo::SIInstrInfo ( const GCNSubtarget & ST )

explicit

Definition at line 86 of file SIInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool SIInstrInfo::analyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify = `false`
	)		const

override

Definition at line 1892 of file SIInstrInfo.cpp.

References analyzeBranchImpl(), E, llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), I, and llvm_unreachable.

Referenced by commuteOpcode(), and isFunctionEntryBlock().

◆ analyzeBranchImpl()

bool SIInstrInfo::analyzeBranchImpl	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify
	)		const

Definition at line 1849 of file SIInstrInfo.cpp.

References llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), I, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by analyzeBranch(), and commuteOpcode().

◆ areLoadsFromSameBasePtr()

bool SIInstrInfo::areLoadsFromSameBasePtr	(	SDNode *	Load1,
		SDNode *	Load2,
		int64_t &	Offset1,
		int64_t &	Offset2
	)		const

override

Definition at line 144 of file SIInstrInfo.cpp.

References assert(), llvm::dyn_cast(), llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), isDS(), llvm::SDNode::isMachineOpcode(), isMTBUF(), isMUBUF(), isSMRD(), and nodesHaveSameOperandValue().

Referenced by getRegisterInfo().

◆ areMemAccessesTriviallyDisjoint()

bool SIInstrInfo::areMemAccessesTriviallyDisjoint	(	const MachineInstr &	MIa,
		const MachineInstr &	MIb,
		AliasAnalysis *	AA = `nullptr`
	)		const

override

Definition at line 2491 of file SIInstrInfo.cpp.

References assert(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), isDS(), isFLAT(), isMTBUF(), isMUBUF(), isSegmentSpecificFLAT(), isSMRD(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().

Referenced by commuteOpcode().

◆ buildExtractSubReg()

unsigned SIInstrInfo::buildExtractSubReg	(	MachineBasicBlock::iterator	MI,
		MachineRegisterInfo &	MRI,
		MachineOperand &	SuperReg,
		const TargetRegisterClass *	SuperRC,
		unsigned	SubIdx,
		const TargetRegisterClass *	SubRC
	)		const

Definition at line 3774 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and SubReg.

Referenced by buildExtractSubRegOrImm(), and extractRsrcPtr().

◆ buildExtractSubRegOrImm()

MachineOperand SIInstrInfo::buildExtractSubRegOrImm	(	MachineBasicBlock::iterator	MI,
		MachineRegisterInfo &	MRI,
		MachineOperand &	SuperReg,
		const TargetRegisterClass *	SuperRC,
		unsigned	SubIdx,
		const TargetRegisterClass *	SubRC
	)		const

Definition at line 3806 of file SIInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), assert(), buildExtractSubReg(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), llvm_unreachable, llvm::MachineInstr::RemoveOperand(), and SubReg.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter(), and moveToVALU().

◆ buildShrunkInst()

MachineInstr * SIInstrInfo::buildShrunkInst	(	MachineInstr &	MI,
		unsigned	NewOpcode
	)		const

Definition at line 3007 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), copyFlagsToImplicitVCC(), llvm::MachineInstr::getDebugLoc(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), and llvm::MachineOperand::getReg().

Referenced by isLiteralConstant(), and updateOperand().

◆ calculateLDSSpillAddress()

unsigned SIInstrInfo::calculateLDSSpillAddress	(	MachineBasicBlock &	MBB,
		MachineInstr &	MI,
		RegScavenger *	RS,
		unsigned	TmpReg,
		unsigned	FrameOffset,
		unsigned	Size
	)		const

Parameters

Definition at line 1239 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegScavenger::enterBasicBlock(), llvm::MachineBasicBlock::findDebugLoc(), llvm::SIRegisterInfo::findUnusedRegister(), llvm::MachineBasicBlock::front(), llvm::MachineFunction::front(), getAddNoCarry(), llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::SIMachineFunctionInfo::getMaxFlatWorkGroupSize(), llvm::MachineBasicBlock::getParent(), llvm::SIMachineFunctionInfo::getPreloadedReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::SIMachineFunctionInfo::getTIDReg(), llvm::SIMachineFunctionInfo::hasCalculatedTID(), llvm::MachineBasicBlock::isLiveIn(), llvm::AMDGPU::isShader(), llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR, llvm::SI::KernelInputOffsets::NGROUPS_Y, llvm::SI::KernelInputOffsets::NGROUPS_Z, Reg, llvm::RegScavenger::scavengeRegister(), llvm::SIMachineFunctionInfo::setTIDReg(), llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::WavefrontSize, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y, and llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z.

Referenced by getRegisterInfo().

◆ canInsertSelect()

bool SIInstrInfo::canInsertSelect	(	const MachineBasicBlock &	MBB,
		ArrayRef< MachineOperand >	Cond,
		unsigned	TrueReg,
		unsigned	FalseReg,
		int &	CondCycles,
		int &	TrueCycles,
		int &	FalseCycles
	)		const

override

Definition at line 2065 of file SIInstrInfo.cpp.

References assert(), llvm::TargetRegisterClass::getID(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPU::getRegBitWidth(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::hasVGPRs(), llvm::SIRegisterInfo::isSGPRClass(), and MRI.

Referenced by commuteOpcode().

◆ canShrink()

bool SIInstrInfo::canShrink	(	const MachineInstr &	MI,
		const MachineRegisterInfo &	MRI
	)		const

Definition at line 2936 of file SIInstrInfo.cpp.

References getNamedOperand(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getReg(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isReg(), and llvm::SIRegisterInfo::isVGPR().

Referenced by findSingleRegDef(), and isLiteralConstant().

◆ commuteInstructionImpl()

MachineInstr * SIInstrInfo::commuteInstructionImpl	(	MachineInstr &	MI,
		bool	NewMI,
		unsigned	OpIdx0,
		unsigned	OpIdx1
	)		const

overrideprotected

Definition at line 1614 of file SIInstrInfo.cpp.

References assert(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteOpcode(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::MachineInstr::setDesc(), swapRegAndNonRegOperand(), and swapSourceModifiers().

◆ commuteOpcode() [1/2]

int SIInstrInfo::commuteOpcode ( unsigned Opc ) const

Definition at line 733 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getCommuteOrig(), llvm::AMDGPU::getCommuteRev(), and pseudoToMCOpcode().

Referenced by commuteInstructionImpl(), commuteOpcode(), getRegisterInfo(), and legalizeOperandsVOP2().

◆ commuteOpcode() [2/2]

LLVM_READONLY int llvm::SIInstrInfo::commuteOpcode ( const MachineInstr & MI ) const

inline

◆ convertNonUniformIfRegion()

void SIInstrInfo::convertNonUniformIfRegion	(	MachineBasicBlock *	IfEntry,
		MachineBasicBlock *	IfEnd
	)		const

Definition at line 5968 of file SIInstrInfo.cpp.

References add(), llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCID::Branch, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::MachineBasicBlock::getFirstNonPHI(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), and llvm::MachineBasicBlock::insert().

Referenced by containsNewBackedge(), and getMCOpcodeFromPseudo().

◆ convertNonUniformLoopRegion()

void SIInstrInfo::convertNonUniformLoopRegion	(	MachineBasicBlock *	LoopEntry,
		MachineBasicBlock *	LoopEnd
	)		const

◆ convertToThreeAddress()

MachineInstr * SIInstrInfo::convertToThreeAddress	(	MachineFunction::iterator &	MBB,
		MachineInstr &	MI,
		LiveVariables *	LV
	)		const

override

◆ copyPhysReg()

void SIInstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc
	)		const

override

Definition at line 524 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), contains(), llvm::tgtok::Def, llvm::RegState::Define, E, llvm::RegScavenger::enterBasicBlock(), llvm::RegScavenger::FindUnusedReg(), llvm::RegScavenger::forward(), llvm::SIRegisterInfo::getHWRegIndex(), llvm::getKillRegState(), llvm::MachineBasicBlock::getParent(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineOperand::getReg(), llvm::SIRegisterInfo::getRegPressureLimit(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::SIRegisterInfo::hasAGPRs(), llvm::SIRegisterInfo::hasVGPRs(), I, llvm::RegState::Implicit, llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::RegState::Kill, llvm::report_fatal_error(), reportIllegalCopy(), llvm::RegScavenger::scavengeRegister(), llvm::MachineOperand::setIsKill(), llvm::RegScavenger::setRegUsed(), and llvm::ArrayRef< T >::size().

Referenced by getRegisterInfo().

◆ createPHIDestinationCopy()

MachineInstr * SIInstrInfo::createPHIDestinationCopy	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	InsPt,
		const DebugLoc &	DL,
		Register	Src,
		Register	Dst
	)		const

override

Definition at line 6414 of file SIInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHIDestinationCopy(), and llvm::MachineBasicBlock::end().

Referenced by getMCOpcodeFromPseudo().

◆ createPHISourceCopy()

MachineInstr * SIInstrInfo::createPHISourceCopy	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	InsPt,
		const DebugLoc &	DL,
		Register	Src,
		Register	SrcSubReg,
		Register	Dst
	)		const

override

Definition at line 6429 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::TargetInstrInfo::createPHISourceCopy(), llvm::MachineBasicBlock::end(), and llvm::RegState::Implicit.

Referenced by getMCOpcodeFromPseudo().

◆ CreateTargetPostRAHazardRecognizer() [1/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer	(	const InstrItineraryData *	II,
		const ScheduleDAG *	DAG
	)		const

override

This is used by the post-RA scheduler (SchedulePostRAList.cpp).

The post-RA version of misched uses CreateTargetMIHazardRecognizer.

Definition at line 6054 of file SIInstrInfo.cpp.

References llvm::ScheduleDAG::MF.

Referenced by getMCOpcodeFromPseudo().

◆ CreateTargetPostRAHazardRecognizer() [2/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const MachineFunction & MF ) const

override

This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.

Definition at line 6062 of file SIInstrInfo.cpp.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > SIInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned TF ) const

override

Definition at line 6067 of file SIInstrInfo.cpp.

References MO_MASK.

Referenced by getMCOpcodeFromPseudo().

◆ expandPostRAPseudo()

bool SIInstrInfo::expandPostRAPseudo ( MachineInstr & MI ) const

override

Definition at line 1382 of file SIInstrInfo.cpp.

References add(), llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MIBundleBuilder::append(), assert(), llvm::MIBundleBuilder::begin(), llvm::BuildMI(), llvm::RegState::Define, llvm::MachineInstr::eraseFromParent(), llvm::TargetInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::hasUnmodeledSideEffects(), I, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::GCNSubtarget::isWave32(), llvm::MachineInstr::mayLoad(), Reg, llvm::MachineInstr::setDesc(), SubReg, and llvm::RegState::Undef.

Referenced by getRegisterInfo().

◆ findCommutedOpIndices() [1/2]

bool SIInstrInfo::findCommutedOpIndices	(	MachineInstr &	MI,
		unsigned &	SrcOpIdx1,
		unsigned &	SrcOpIdx2
	)		const

override

Definition at line 1666 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc().

Referenced by commuteOpcode(), gwsIntrinToOpcode(), and tryAddToFoldList().

◆ findCommutedOpIndices() [2/2]

bool SIInstrInfo::findCommutedOpIndices	(	MCInstrDesc	Desc,
		unsigned &	SrcOpIdx0,
		unsigned &	SrcOpIdx1
	)		const

Definition at line 1671 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getOpcode(), and llvm::MCInstrDesc::isCommutable().

◆ fixImplicitOperands()

void SIInstrInfo::fixImplicitOperands ( MachineInstr & MI ) const

Definition at line 6145 of file SIInstrInfo.cpp.

References llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getSubtarget(), llvm::MachineInstr::implicit_operands(), llvm::MachineOperand::isReg(), llvm::GCNSubtarget::isWave32(), and llvm::MachineOperand::setReg().

Referenced by llvm::SITargetLowering::finalizeLowering(), getRegClass(), insertSelect(), legalizeOperandsVOP2(), and moveToVALU().

◆ FoldImmediate()

bool SIInstrInfo::FoldImmediate	(	MachineInstr &	UseMI,
		MachineInstr &	DefMI,
		unsigned	Reg,
		MachineRegisterInfo *	MRI
	)		const

final

Definition at line 2254 of file SIInstrInfo.cpp.

Referenced by commuteOpcode(), and legalizeGenericOperand().

◆ getAddNoCarry() [1/2]

MachineInstrBuilder SIInstrInfo::getAddNoCarry	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		unsigned	DestReg
	)		const

Return a partially built integer add instruction without carry.

Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.

Definition at line 6092 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), and llvm::MachineRegisterInfo::setRegAllocationHint().

Referenced by calculateLDSSpillAddress(), getBufferStoreFormatOpcode(), and getMCOpcodeFromPseudo().

◆ getAddNoCarry() [2/2]

MachineInstrBuilder SIInstrInfo::getAddNoCarry	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		Register	DestReg,
		RegScavenger &	RS
	)		const

Definition at line 6107 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegState::Dead, llvm::RegState::Define, I, llvm::Register::isValid(), and llvm::RegScavenger::scavengeRegister().

◆ getAddressSpaceForPseudoSourceKind()

unsigned SIInstrInfo::getAddressSpaceForPseudoSourceKind ( unsigned Kind ) const

override

Definition at line 2223 of file SIInstrInfo.cpp.

References AMDGPUAS::CONSTANT_ADDRESS, llvm::PseudoSourceValue::ConstantPool, llvm::PseudoSourceValue::ExternalSymbolCallEntry, llvm::PseudoSourceValue::FixedStack, AMDGPUAS::FLAT_ADDRESS, llvm::PseudoSourceValue::GlobalValueCallEntry, llvm::PseudoSourceValue::GOT, llvm::PseudoSourceValue::JumpTable, AMDGPUAS::PRIVATE_ADDRESS, llvm::PseudoSourceValue::Stack, and llvm::PseudoSourceValue::TargetCustom.

Referenced by commuteOpcode().

◆ getBranchDestBlock()

MachineBasicBlock * SIInstrInfo::getBranchDestBlock ( const MachineInstr & MI ) const

override

Definition at line 1704 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by commuteOpcode().

◆ getClampMask()

uint64_t llvm::SIInstrInfo::getClampMask ( const MachineInstr & MI ) const

inline

Definition at line 639 of file SIInstrInfo.h.

References llvm::SIInstrFlags::ClampHi, llvm::SIInstrFlags::ClampLo, llvm::SIInstrFlags::FPClamp, llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::IntClamp, and llvm::MCInstrDesc::TSFlags.

◆ getDefaultRsrcDataFormat()

uint64_t SIInstrInfo::getDefaultRsrcDataFormat ( ) const

Definition at line 5764 of file SIInstrInfo.cpp.

References llvm::AMDGPUSubtarget::GFX10, llvm::AMDGPU::RSRC_DATA_FORMAT, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by extractRsrcPtr(), getNamedImmOperand(), getScratchRsrcWords23(), isStackPtrRelative(), and llvm::SITargetLowering::wrapAddr64Rsrc().

◆ getInstBundleSize()

unsigned SIInstrInfo::getInstBundleSize ( const MachineInstr & MI ) const

Definition at line 5871 of file SIInstrInfo.cpp.

References assert(), E, getInstSizeInBytes(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), I, llvm::MachineBasicBlock::instr_end(), and Size.

Referenced by getInstSizeInBytes(), and getMCOpcodeFromPseudo().

◆ getInstSizeInBytes()

unsigned SIInstrInfo::getInstSizeInBytes ( const MachineInstr & MI ) const

override

Definition at line 5883 of file SIInstrInfo.cpp.

References llvm::ISD::EH_LABEL, getInstBundleSize(), llvm::TargetMachine::getMCAsmInfo(), getMCOpcodeFromPseudo(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, isFixedSize(), isLiteralConstantLike(), isMIMG(), isSALU(), isVALU(), isVOP3(), llvm::AMDGPUISD::KILL, and llvm::MCInstrDesc::OpInfo.

Referenced by addRegsToSet(), getInstBundleSize(), getMCOpcodeFromPseudo(), llvm::SITargetLowering::getPrefLoopAlignment(), removeBranch(), and llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ getKillTerminatorFromPseudo()

const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo ( unsigned Opcode ) const

Definition at line 6134 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by getMCOpcodeFromPseudo(), and llvm::SITargetLowering::splitKillBlock().

◆ getMachineCSELookAheadLimit()

unsigned llvm::SIInstrInfo::getMachineCSELookAheadLimit ( ) const

inlineoverride

Definition at line 314 of file SIInstrInfo.h.

References convertToThreeAddress(), and isSchedulingBoundary().

◆ getMCOpcodeFromPseudo()

const MCInstrDesc& llvm::SIInstrInfo::getMCOpcodeFromPseudo ( unsigned Opcode ) const

inline

Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.

Definition at line 922 of file SIInstrInfo.h.

References convertNonUniformIfRegion(), convertNonUniformLoopRegion(), createPHIDestinationCopy(), createPHISourceCopy(), CreateTargetPostRAHazardRecognizer(), decomposeMachineOperandsTargetFlags(), getAddNoCarry(), getInstBundleSize(), getInstSizeInBytes(), getKillTerminatorFromPseudo(), getSerializableDirectMachineOperandTargetFlags(), getSerializableTargetIndices(), isBasicBlockPrologue(), isKillTerminator(), isLoadFromStackSlot(), isNonUniformBranchInstr(), isSGPRStackAccess(), isStackAccess(), isStoreToStackSlot(), isWave32(), mayAccessFlatAddressSpace(), and pseudoToMCOpcode().

Referenced by getInstSizeInBytes().

◆ getMemOperandWithOffset()

bool SIInstrInfo::getMemOperandWithOffset	(	const MachineInstr &	LdSt,
		const MachineOperand *&	BaseOp,
		int64_t &	Offset,
		const TargetRegisterInfo *	TRI
	)		const

final

◆ getMovOpcode()

unsigned SIInstrInfo::getMovOpcode ( const TargetRegisterClass * DstRC ) const

Definition at line 966 of file SIInstrInfo.cpp.

References llvm::SIRegisterInfo::hasAGPRs(), and llvm::SIRegisterInfo::isSGPRClass().

Referenced by getRegisterInfo().

◆ getNamedImmOperand()

int64_t llvm::SIInstrInfo::getNamedImmOperand	(	const MachineInstr &	MI,
		unsigned	OpName
	)		const

inline

Get required immediate operand.

Definition at line 909 of file SIInstrInfo.h.

References getDefaultRsrcDataFormat(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getScratchRsrcWords23(), isHighLatencyInstruction(), and isLowLatencyInstruction().

Referenced by findSingleRegDef(), and legalizeOperands().

◆ getNamedOperand() [1/2]

MachineOperand * SIInstrInfo::getNamedOperand	(	MachineInstr &	MI,
		unsigned	OperandName
	)		const

Returns the operand named Op.

If MI does not have an operand named Op, this function returns nullptr.

Definition at line 5755 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by addRegsToSet(), buildMUBUFOffsetLoadStore(), buildShrunkInst(), canShrink(), convertToThreeAddress(), llvm::createSIModeRegisterPass(), llvm::SITargetLowering::emitGWSMemViolTestLoop(), emitIndirectDst(), emitIndirectSrc(), findSingleRegDef(), fixupGlobalSaddr(), FoldImmediate(), getDPPOp(), getHWReg(), getMemOperandWithOffset(), getNamedOperand(), getOpSize(), getOrNonExecReg(), hasAnyNonFlatUseOfReg(), hasModifiersSet(), isIdentityValue(), isSafeToFoldImmIntoCopy(), isSGPRStackAccess(), isStackAccess(), legalizeOperands(), legalizeOperandsSMRD(), loadM0FromVGPR(), optimizeVcndVcmpPair(), setM0ToIndexFromSGPR(), shouldClusterMemOps(), swapSourceModifiers(), tryConstantFoldOp(), tryFoldInst(), and verifyInstruction().

◆ getNamedOperand() [2/2]

LLVM_READONLY const MachineOperand* llvm::SIInstrInfo::getNamedOperand	(	const MachineInstr &	MI,
		unsigned	OpName
	)		const

inline

Definition at line 903 of file SIInstrInfo.h.

References getNamedOperand().

◆ getNumWaitStates()

unsigned SIInstrInfo::getNumWaitStates ( const MachineInstr & MI )

static

Return the number of wait states that result from executing this instruction.

Definition at line 1373 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by llvm::GCNHazardRecognizer::AdvanceCycle(), getOpSize(), and getWaitStatesSince().

◆ getOpRegClass()

const TargetRegisterClass * SIInstrInfo::getOpRegClass	(	const MachineInstr &	MI,
		unsigned	OpNo
	)		const

Return the correct register class for OpNo.

For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.

Definition at line 3729 of file SIInstrInfo.cpp.

References llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isVariadic(), llvm::Register::isVirtualRegister(), MRI, llvm::MCInstrDesc::OpInfo, Reg, and llvm::MCOperandInfo::RegClass.

Referenced by getMemOperandWithOffset(), getOpSize(), hoistAndMergeSGPRInits(), isLiteralConstant(), legalizeOperands(), moveToVALU(), and verifyInstruction().

◆ getOpSize() [1/2]

unsigned llvm::SIInstrInfo::getOpSize	(	uint16_t	Opcode,
		unsigned	OpNo
	)		const

inline

Return the size in bytes of the operand OpNo on the given.

Definition at line 796 of file SIInstrInfo.h.

References assert(), llvm::SIRegisterInfo::getRegClass(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.

Referenced by isInlineConstant(), and matchSwap().

◆ getOpSize() [2/2]

unsigned llvm::SIInstrInfo::getOpSize	(	const MachineInstr &	MI,
		unsigned	OpNo
	)		const

inline

This form should usually be preferred since it handles operands with unknown register classes.

Definition at line 810 of file SIInstrInfo.h.

References assert(), getNamedOperand(), getNumWaitStates(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), insertNoop(), insertReturn(), insertWaitStates(), isLegalRegOperand(), isLegalVSrcOperand(), isOperandLegal(), llvm::MachineOperand::isReg(), legalizeGenericOperand(), legalizeOperands(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), legalizeOpWithMove(), LLVM_READONLY, moveToVALU(), readlaneVGPRToSGPR(), and SubReg.

◆ getPreferredSelectRegClass()

const TargetRegisterClass * SIInstrInfo::getPreferredSelectRegClass ( unsigned Size ) const

Definition at line 808 of file SIInstrInfo.cpp.

Referenced by createBBSelectReg(), and getRegisterInfo().

◆ getRegClass()

const TargetRegisterClass* llvm::SIInstrInfo::getRegClass	(	const MCInstrDesc &	TID,
		unsigned	OpNum,
		const TargetRegisterInfo *	TRI,
		const MachineFunction &	MF
	)		const

inlineoverride

Definition at line 1011 of file SIInstrInfo.h.

References fixImplicitOperands(), llvm::MCInstrDesc::getNumOperands(), llvm::SIRegisterInfo::getRegClass(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by getOpSize().

◆ getRegisterInfo()

const SIRegisterInfo& llvm::SIInstrInfo::getRegisterInfo ( ) const

inline

Definition at line 171 of file SIInstrInfo.h.

References areLoadsFromSameBasePtr(), calculateLDSSpillAddress(), commuteOpcode(), copyPhysReg(), expandPostRAPseudo(), llvm::ISD::FrameIndex, getMemOperandWithOffset(), getMovOpcode(), getPreferredSelectRegClass(), I, insertEQ(), insertNE(), isReallyTriviallyReMaterializable(), LLVM_READONLY, loadRegFromStackSlot(), materializeImmediate(), shouldClusterMemOps(), shouldScheduleLoadsNear(), Size, storeRegToStackSlot(), and TRI.

Referenced by buildEpilogReload(), llvm::SIFrameLowering::emitEntryFunctionPrologue(), emitIndirectDst(), emitIndirectSrc(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::GCNSubtarget::getRegisterInfo(), hasAnyNonFlatUseOfReg(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), isVRegCompatibleReg(), matchSwap(), setM0ToIndexFromSGPR(), tryAddToFoldList(), and tryConstantFoldOp().

◆ getScratchRsrcWords23()

uint64_t SIInstrInfo::getScratchRsrcWords23 ( ) const

Definition at line 5786 of file SIInstrInfo.cpp.

References getDefaultRsrcDataFormat(), llvm::AMDGPUSubtarget::GFX9, llvm::Log2_32(), llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT, llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT, llvm::AMDGPU::RSRC_TID_ENABLE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::SIFrameLowering::emitEntryFunctionPrologue(), and getNamedImmOperand().

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > SIInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const

override

Definition at line 6072 of file SIInstrInfo.cpp.

References llvm::makeArrayRef(), MO_ABS32_HI, MO_ABS32_LO, MO_GOTPCREL, MO_GOTPCREL32_HI, MO_GOTPCREL32_LO, MO_REL32_HI, and MO_REL32_LO.

Referenced by getMCOpcodeFromPseudo().

◆ getSerializableTargetIndices()

ArrayRef< std::pair< int, const char * > > SIInstrInfo::getSerializableTargetIndices ( ) const

override

Definition at line 6041 of file SIInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2, and llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3.

Referenced by getMCOpcodeFromPseudo().

◆ getVALUOp()

unsigned SIInstrInfo::getVALUOp ( const MachineInstr & MI ) const

Definition at line 3649 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isReg(), llvm_unreachable, MRI, and llvm::SIInstrFlags::WQM.

Referenced by isLiteralConstant(), and moveToVALU().

◆ hasAnyModifiersSet()

bool SIInstrInfo::hasAnyModifiersSet ( const MachineInstr & MI ) const

Definition at line 2928 of file SIInstrInfo.cpp.

References hasModifiersSet().

Referenced by FoldImmediate(), and isLiteralConstant().

◆ hasFPClamp() [1/2]

static bool llvm::SIInstrInfo::hasFPClamp ( const MachineInstr & MI )

inlinestatic

Definition at line 627 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

◆ hasFPClamp() [2/2]

bool llvm::SIInstrInfo::hasFPClamp ( uint16_t Opcode ) const

inline

Definition at line 631 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp.

◆ hasIntClamp()

static bool llvm::SIInstrInfo::hasIntClamp ( const MachineInstr & MI )

inlinestatic

Definition at line 635 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::IntClamp, and llvm::MCInstrDesc::TSFlags.

◆ hasModifiers()

bool SIInstrInfo::hasModifiers ( unsigned Opcode ) const

Return true if this instruction has any modifiers.

e.g. src[012]_mod, omod, clamp.

Definition at line 2914 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

Referenced by isLiteralConstant().

◆ hasModifiersSet()

bool SIInstrInfo::hasModifiersSet	(	const MachineInstr &	MI,
		unsigned	OpName
	)		const

Definition at line 2922 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), and getNamedOperand().

Referenced by canShrink(), findSingleRegDef(), hasAnyModifiersSet(), isLiteralConstant(), and optimizeVcndVcmpPair().

◆ hasUnwantedEffectsWhenEXECEmpty()

bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr & MI ) const

Whether we must prevent this instruction from executing with EXEC = 0.

Definition at line 2698 of file SIInstrInfo.cpp.

References llvm::AMDGPUISD::DS_ORDERED_COUNT, llvm::SIInstrFlags::EXP, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::isCall(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::isReturn(), isSMRD(), and llvm::MachineInstr::mayStore().

Referenced by hasVGPRUses().

◆ hasVALU32BitEncoding()

bool SIInstrInfo::hasVALU32BitEncoding ( unsigned Opcode ) const

Return true if this 64-bit VALU instruction has a 32-bit encoding.

This function will return false if you pass it a 32-bit instruction.

Definition at line 2906 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getVOPe32(), and pseudoToMCOpcode().

Referenced by canShrink(), isIdentityValue(), and isLiteralConstant().

◆ hasVGPRUses()

bool llvm::SIInstrInfo::hasVGPRUses ( const MachineInstr & MI ) const

inline

Definition at line 671 of file SIInstrInfo.h.

References llvm::any_of(), llvm::MachineInstr::explicit_uses(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), hasUnwantedEffectsWhenEXECEmpty(), isInlineConstant(), llvm::SIRegisterInfo::isVGPR(), mayReadEXEC(), and MRI.

◆ insertBranch()

unsigned SIInstrInfo::insertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		ArrayRef< MachineOperand >	Cond,
		const DebugLoc &	DL,
		int *	BytesAdded = `nullptr`
	)		const

override

Definition at line 1993 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::MachineInstr::getOperand(), isUndef(), preserveCondRegFlags(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsUndef(), and llvm::ArrayRef< T >::size().

Referenced by commuteOpcode().

◆ insertEQ()

unsigned SIInstrInfo::insertEQ	(	MachineBasicBlock *	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		unsigned	SrcReg,
		int	Value
	)		const

Definition at line 940 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MRI, and Reg.

Referenced by getRegisterInfo(), and removeExternalCFGEdges().

◆ insertIndirectBranch()

unsigned SIInstrInfo::insertIndirectBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock &	NewDestBB,
		const DebugLoc &	DL,
		int64_t	BrOffset,
		RegScavenger *	RS = `nullptr`
	)		const

override

◆ insertNE()

unsigned SIInstrInfo::insertNE	(	MachineBasicBlock *	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		unsigned	SrcReg,
		int	Value
	)		const

Definition at line 953 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::SIRegisterInfo::getBoolRC(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MRI, and Reg.

Referenced by getRegisterInfo(), and isFunctionEntryBlock().

◆ insertNoop()

void SIInstrInfo::insertNoop	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI
	)		const

override

Definition at line 1350 of file SIInstrInfo.cpp.

References insertWaitStates().

Referenced by getOpSize().

◆ insertReturn()

void SIInstrInfo::insertReturn ( MachineBasicBlock & MBB ) const

Definition at line 1355 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), Info, llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::SIMachineFunctionInfo::returnsVoid(), and llvm::MachineBasicBlock::succ_empty().

Referenced by containsNewBackedge(), and getOpSize().

◆ insertSelect()

void SIInstrInfo::insertSelect	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		unsigned	DstReg,
		ArrayRef< MachineOperand >	Cond,
		unsigned	TrueReg,
		unsigned	FalseReg
	)		const

override

Definition at line 2105 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), fixImplicitOperands(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), MRI, preserveCondRegFlags(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MCID::Select, and std::swap().

Referenced by commuteOpcode().

◆ insertVectorSelect()

void SIInstrInfo::insertVectorSelect	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		const DebugLoc &	DL,
		unsigned	DstReg,
		ArrayRef< MachineOperand >	Cond,
		unsigned	TrueReg,
		unsigned	FalseReg
	)		const

Definition at line 812 of file SIInstrInfo.cpp.

Referenced by commuteOpcode().

◆ insertWaitStates()

void SIInstrInfo::insertWaitStates	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		int	Count
	)		const

Definition at line 1334 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), Arg, llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().

Referenced by getOpSize(), and insertNoop().

◆ isAlwaysGDS()

bool SIInstrInfo::isAlwaysGDS ( uint16_t Opcode ) const

Definition at line 2688 of file SIInstrInfo.cpp.

References llvm::AMDGPUISD::DS_ORDERED_COUNT.

Referenced by isDS(), and isSendMsgTraceDataOrGDS().

◆ isBasicBlockPrologue()

bool SIInstrInfo::isBasicBlockPrologue ( const MachineInstr & MI ) const

override

Definition at line 6086 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::isTerminator(), and llvm::MachineInstr::modifiesRegister().

Referenced by getMCOpcodeFromPseudo().

◆ isBranchOffsetInRange()

bool SIInstrInfo::isBranchOffsetInRange	(	unsigned	BranchOpc,
		int64_t	BrOffset
	)		const

override

Definition at line 1688 of file SIInstrInfo.cpp.

References assert(), BranchOffsetBits, and llvm::isIntN().

Referenced by commuteOpcode().

◆ isBufferSMRD()

bool SIInstrInfo::isBufferSMRD ( const MachineInstr & MI ) const

Definition at line 6159 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), isSMRD(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by addRegsToSet(), and isSMRD().

◆ isDisableWQM() [1/2]

static bool llvm::SIInstrInfo::isDisableWQM ( const MachineInstr & MI )

inlinestatic

Definition at line 525 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

◆ isDisableWQM() [2/2]

bool llvm::SIInstrInfo::isDisableWQM ( uint16_t Opcode ) const

inline

Definition at line 529 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM.

◆ isDOT() [1/2]

static bool llvm::SIInstrInfo::isDOT ( const MachineInstr & MI )

inlinestatic

Definition at line 581 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::IsDOT, and llvm::MCInstrDesc::TSFlags.

◆ isDOT() [2/2]

bool llvm::SIInstrInfo::isDOT ( uint16_t Opcode ) const

inline

Definition at line 585 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsDOT.

◆ isDPP() [1/2]

static bool llvm::SIInstrInfo::isDPP ( const MachineInstr & MI )

inlinestatic

Definition at line 549 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isDPP() [2/2]

bool llvm::SIInstrInfo::isDPP ( uint16_t Opcode ) const

inline

Definition at line 553 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP.

◆ isDS() [1/2]

static bool llvm::SIInstrInfo::isDS ( const MachineInstr & MI )

inlinestatic

Definition at line 462 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::GCNSubtarget::getMaxNumVGPRs(), getMemOperandWithOffset(), isSendMsgTraceDataOrGDS(), and shouldClusterMemOps().

◆ isDS() [2/2]

bool llvm::SIInstrInfo::isDS ( uint16_t Opcode ) const

inline

Definition at line 466 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS, and isAlwaysGDS().

◆ isEXP() [1/2]

static bool llvm::SIInstrInfo::isEXP ( const MachineInstr & MI )

inlinestatic

Definition at line 509 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by hasDataDependencyPred().

◆ isEXP() [2/2]

bool llvm::SIInstrInfo::isEXP ( uint16_t Opcode ) const

inline

Definition at line 513 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP.

◆ isFixedSize() [1/2]

static bool llvm::SIInstrInfo::isFixedSize ( const MachineInstr & MI )

inlinestatic

Definition at line 619 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by getInstSizeInBytes().

◆ isFixedSize() [2/2]

bool llvm::SIInstrInfo::isFixedSize ( uint16_t Opcode ) const

inline

Definition at line 623 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE.

◆ isFLAT() [1/2]

static bool llvm::SIInstrInfo::isFLAT ( const MachineInstr & MI )

inlinestatic

Definition at line 488 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areMemAccessesTriviallyDisjoint(), llvm::GCNHazardRecognizer::getHazardType(), llvm::GCNSubtarget::getMaxNumVGPRs(), getMemOperandWithOffset(), hasAnyNonFlatUseOfReg(), isVMEMClauseInst(), mayAccessFlatAddressSpace(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldClusterMemOps(), and verifyInstruction().

◆ isFLAT() [2/2]

bool llvm::SIInstrInfo::isFLAT ( uint16_t Opcode ) const

inline

Definition at line 505 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT.

◆ isFLATScratch()

static bool llvm::SIInstrInfo::isFLATScratch ( const MachineInstr & MI )

inlinestatic

Definition at line 500 of file SIInstrInfo.h.

References isSegmentSpecificFLAT().

Referenced by frameIndexMayFold().

◆ isFoldableCopy()

bool SIInstrInfo::isFoldableCopy ( const MachineInstr & MI ) const

Definition at line 2200 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), and llvm::MachineInstr::getOpcode().

Referenced by commuteOpcode(), findSingleRegDef(), and tryToFoldACImm().

◆ isFPAtomic() [1/2]

static bool llvm::SIInstrInfo::isFPAtomic ( const MachineInstr & MI )

inlinestatic

Definition at line 655 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPAtomic, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet().

◆ isFPAtomic() [2/2]

bool llvm::SIInstrInfo::isFPAtomic ( uint16_t Opcode ) const

inline

Definition at line 659 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPAtomic.

◆ isGather4() [1/2]

static bool llvm::SIInstrInfo::isGather4 ( const MachineInstr & MI )

inlinestatic

Definition at line 480 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::SITargetLowering::PostISelFolding(), and verifyInstruction().

◆ isGather4() [2/2]

bool llvm::SIInstrInfo::isGather4 ( uint16_t Opcode ) const

inline

Definition at line 484 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4.

◆ isHighLatencyInstruction()

bool SIInstrInfo::isHighLatencyInstruction ( const MachineInstr & MI ) const

Definition at line 5816 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), isMIMG(), isMTBUF(), and isMUBUF().

Referenced by getNamedImmOperand(), and llvm::SIScheduleDAGMI::schedule().

◆ isImmOperandLegal()

bool SIInstrInfo::isImmOperandLegal	(	const MachineInstr &	MI,
		unsigned	OpNo,
		const MachineOperand &	MO
	)		const

Definition at line 2873 of file SIInstrInfo.cpp.

References assert(), llvm::MachineInstr::getDesc(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getSubtarget(), llvm::GCNSubtarget::hasMFMAInlineLiteralBug(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isInlineConstant(), isMAI(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVOP3(), llvm::SIRegisterInfo::opCanUseInlineConstant(), llvm::SIRegisterInfo::opCanUseLiteralConstant(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by isLiteralConstant(), and isOperandLegal().

◆ isInlineConstant() [1/7]

bool SIInstrInfo::isInlineConstant ( const APInt & Imm ) const

◆ isInlineConstant() [2/7]

bool SIInstrInfo::isInlineConstant	(	const MachineOperand &	MO,
		uint8_t	OperandType
	)		const

Definition at line 2779 of file SIInstrInfo.cpp.

◆ isInlineConstant() [3/7]

bool llvm::SIInstrInfo::isInlineConstant	(	const MachineOperand &	MO,
		const MCOperandInfo &	OpInfo
	)		const

inline

Definition at line 690 of file SIInstrInfo.h.

References isInlineConstant(), and llvm::MCOperandInfo::OperandType.

◆ isInlineConstant() [4/7]

bool llvm::SIInstrInfo::isInlineConstant	(	const MachineInstr &	MI,
		const MachineOperand &	UseMO,
		const MachineOperand &	DefMO
	)		const

inline

returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.

Definition at line 697 of file SIInstrInfo.h.

References assert(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperandNo(), llvm::MachineOperand::getParent(), isInlineConstant(), MI, llvm::MCInstrDesc::NumOperands, and llvm::MCInstrDesc::OpInfo.

◆ isInlineConstant() [5/7]

bool llvm::SIInstrInfo::isInlineConstant	(	const MachineInstr &	MI,
		unsigned	OpIdx
	)		const

inline

returns true if the operand OpIdx in MI is a valid inline immediate.

Definition at line 711 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), isInlineConstant(), llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

◆ isInlineConstant() [6/7]

bool llvm::SIInstrInfo::isInlineConstant	(	const MachineInstr &	MI,
		unsigned	OpIdx,
		const MachineOperand &	MO
	)		const

inline

Definition at line 716 of file SIInstrInfo.h.

References assert(), llvm::MachineInstr::getDesc(), getOpSize(), llvm::MachineInstr::isCopy(), isInlineConstant(), llvm::MCInstrDesc::NumOperands, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

◆ isInlineConstant() [7/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand & MO ) const

inline

Definition at line 733 of file SIInstrInfo.h.

References llvm::MachineInstr::getOperandNo(), llvm::MachineOperand::getParent(), and isInlineConstant().

◆ isKillTerminator()

bool SIInstrInfo::isKillTerminator ( unsigned Opcode )

static

Definition at line 6124 of file SIInstrInfo.cpp.

Referenced by getMCOpcodeFromPseudo(), and isSimpleIf().

◆ isLegalFLATOffset()

bool SIInstrInfo::isLegalFLATOffset	(	int64_t	Offset,
		unsigned	AddrSpace,
		bool	Signed
	)		const

Returns if Offset is legal for the subtarget as the offset to a FLAT encoded instruction.

If Signed, this is for an instruction that interprets the offset as signed.

Definition at line 6172 of file SIInstrInfo.cpp.

References AMDGPUAS::FLAT_ADDRESS, and llvm::AMDGPUSubtarget::GFX10.

Referenced by isLegalMUBUFImmOffset(), llvm::AMDGPUInstructionSelector::select(), and llvm::AMDGPUTargetLowering::SelectFlatOffset().

◆ isLegalMUBUFImmOffset()

static bool llvm::SIInstrInfo::isLegalMUBUFImmOffset ( unsigned Imm )

inlinestatic

Definition at line 996 of file SIInstrInfo.h.

References isLegalFLATOffset(), pseudoToMCOpcode(), and Signed.

Referenced by isStackPtrRelative(), and selectSGPRVectorRegClassID().

◆ isLegalRegOperand()

bool SIInstrInfo::isLegalRegOperand	(	const MachineRegisterInfo &	MRI,
		const MCOperandInfo &	OpInfo,
		const MachineOperand &	MO
	)		const

Check if MO (a register operand) is a legal register for the given operand description.

Definition at line 3835 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::SIRegisterInfo::getSubRegClass(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::MachineOperand::isReg(), llvm::Register::isVirtualRegister(), Reg, llvm::MCOperandInfo::RegClass, and TRI.

Referenced by getOpSize(), isLegalVSrcOperand(), isOperandLegal(), and legalizeOperandsVOP2().

◆ isLegalVSrcOperand()

bool SIInstrInfo::isLegalVSrcOperand	(	const MachineRegisterInfo &	MRI,
		const MCOperandInfo &	OpInfo,
		const MachineOperand &	MO
	)		const

Check if MO would be a valid operand for the given operand definition OpInfo.

Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).

Definition at line 3862 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTargetIndex().

Referenced by getOpSize().

◆ isLiteralConstant() [1/2]

bool llvm::SIInstrInfo::isLiteralConstant	(	const MachineOperand &	MO,
		const MCOperandInfo &	OpInfo
	)		const

inline

Definition at line 738 of file SIInstrInfo.h.

References llvm::MachineOperand::isImm(), isInlineConstant(), and llvm::MCOperandInfo::OperandType.

◆ isLiteralConstant() [2/2]

bool llvm::SIInstrInfo::isLiteralConstant	(	const MachineInstr &	MI,
		int	OpIdx
	)		const

inline

Definition at line 743 of file SIInstrInfo.h.

References buildShrunkInst(), canShrink(), llvm::MachineInstr::getOperand(), getOpRegClass(), getVALUOp(), hasAnyModifiersSet(), hasModifiers(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isInlineConstant(), isLiteralConstantLike(), usesConstantBus(), and verifyInstruction().

◆ isLiteralConstantLike()

bool SIInstrInfo::isLiteralConstantLike	(	const MachineOperand &	MO,
		const MCOperandInfo &	OpInfo
	)		const

Definition at line 2840 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getType(), isInlineConstant(), llvm_unreachable, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_FrameIndex, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_Immediate, llvm::MachineOperand::MO_MachineBasicBlock, llvm::MachineOperand::MO_MCSymbol, and llvm::MachineOperand::MO_Register.

Referenced by getInstSizeInBytes(), isLiteralConstant(), isOperandLegal(), legalizeOperandsVOP2(), and legalizeOperandsVOP3().

◆ isLoadFromStackSlot()

unsigned SIInstrInfo::isLoadFromStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

Definition at line 5843 of file SIInstrInfo.cpp.

References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and llvm::MachineInstr::mayLoad().

Referenced by getMCOpcodeFromPseudo().

◆ isLowLatencyInstruction()

bool SIInstrInfo::isLowLatencyInstruction ( const MachineInstr & MI ) const

Definition at line 5810 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isSMRD().

Referenced by getNamedImmOperand(), llvm::SIScheduleDAGMI::schedule(), and llvm::SIScheduleDAGMI::SIScheduleDAGMI().

◆ isMAI() [1/2]

static bool llvm::SIInstrInfo::isMAI ( const MachineInstr & MI )

inlinestatic

Definition at line 573 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::IsMAI, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), llvm::GCNHazardRecognizer::getHazardType(), llvm::GCNSubtarget::getMaxNumVGPRs(), isImmOperandLegal(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isMAI() [2/2]

bool llvm::SIInstrInfo::isMAI ( uint16_t Opcode ) const

inline

Definition at line 577 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsMAI.

◆ isMIMG() [1/2]

static bool llvm::SIInstrInfo::isMIMG ( const MachineInstr & MI )

inlinestatic

Definition at line 472 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::MIMG, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), getInstSizeInBytes(), isHighLatencyInstruction(), isVMEM(), legalizeOperands(), llvm::SITargetLowering::PostISelFolding(), and verifyInstruction().

◆ isMIMG() [2/2]

bool llvm::SIInstrInfo::isMIMG ( uint16_t Opcode ) const

inline

Definition at line 476 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MIMG.

◆ isMTBUF() [1/2]

static bool llvm::SIInstrInfo::isMTBUF ( const MachineInstr & MI )

inlinestatic

Definition at line 444 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::MTBUF, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOperandWithOffset(), isHighLatencyInstruction(), isVMEM(), legalizeOperands(), and shouldClusterMemOps().

◆ isMTBUF() [2/2]

bool llvm::SIInstrInfo::isMTBUF ( uint16_t Opcode ) const

inline

Definition at line 448 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MTBUF.

◆ isMUBUF() [1/2]

static bool llvm::SIInstrInfo::isMUBUF ( const MachineInstr & MI )

inlinestatic

Definition at line 436 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::MUBUF, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), frameIndexMayFold(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), getMemOperandWithOffset(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isHighLatencyInstruction(), isLoadFromStackSlot(), isStoreToStackSlot(), isVMEM(), legalizeOperands(), and shouldClusterMemOps().

◆ isMUBUF() [2/2]

bool llvm::SIInstrInfo::isMUBUF ( uint16_t Opcode ) const

inline

Definition at line 440 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MUBUF.

◆ isNonUniformBranchInstr()

bool SIInstrInfo::isNonUniformBranchInstr ( MachineInstr & Instr ) const

Definition at line 5964 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by getMCOpcodeFromPseudo().

◆ isOperandLegal()

bool SIInstrInfo::isOperandLegal	(	const MachineInstr &	MI,
		unsigned	OpIdx,
		const MachineOperand *	MO = `nullptr`
	)		const

Check if MO is a legal operand if it was the OpIdx Operand for MI.

Definition at line 3873 of file SIInstrInfo.cpp.

References assert(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::count(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::insert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isLegalRegOperand(), isLiteralConstantLike(), llvm::MachineOperand::isReg(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVALU(), isVOP3(), MRI, llvm::AMDGPU::OPERAND_KIMM32, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, and usesConstantBus().

Referenced by commuteInstructionImpl(), convertToThreeAddress(), getDPPOp(), getOpSize(), legalizeOperandsVOP3(), tryAddToFoldList(), tryChangeVGPRtoSGPRinCopy(), and tryToFoldACImm().

◆ isPacked() [1/2]

static bool llvm::SIInstrInfo::isPacked ( const MachineInstr & MI )

inlinestatic

Definition at line 388 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::IsPacked, and llvm::MCInstrDesc::TSFlags.

◆ isPacked() [2/2]

bool llvm::SIInstrInfo::isPacked ( uint16_t Opcode ) const

inline

Definition at line 392 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsPacked.

◆ isReallyTriviallyReMaterializable()

bool SIInstrInfo::isReallyTriviallyReMaterializable	(	const MachineInstr &	MI,
		AliasAnalysis *	AA
	)		const

override

Definition at line 128 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), and llvm::MachineInstr::getOpcode().

Referenced by getRegisterInfo().

◆ isSALU() [1/2]

static bool llvm::SIInstrInfo::isSALU ( const MachineInstr & MI )

inlinestatic

Definition at line 324 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SALU, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), getInstSizeInBytes(), llvm::GCNSubtarget::getMaxNumVGPRs(), mayReadEXEC(), and shouldReadExec().

◆ isSALU() [2/2]

bool llvm::SIInstrInfo::isSALU ( uint16_t Opcode ) const

inline

Definition at line 328 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SALU.

◆ isScalarStore() [1/2]

static bool llvm::SIInstrInfo::isScalarStore ( const MachineInstr & MI )

inlinestatic

Returns: true if this is an s_store_dword* instruction. This is more specific than than isSMEM && mayStore.

Definition at line 611 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SCALAR_STORE, and llvm::MCInstrDesc::TSFlags.

◆ isScalarStore() [2/2]

bool llvm::SIInstrInfo::isScalarStore ( uint16_t Opcode ) const

inline

Definition at line 615 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SCALAR_STORE.

◆ isScalarUnit()

static bool llvm::SIInstrInfo::isScalarUnit ( const MachineInstr & MI )

inlinestatic

Definition at line 589 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SALU, llvm::SIInstrFlags::SMRD, and llvm::MCInstrDesc::TSFlags.

◆ isSchedulingBoundary()

bool SIInstrInfo::isSchedulingBoundary	(	const MachineInstr &	MI,
		const MachineBasicBlock *	MBB,
		const MachineFunction &	MF
	)		const

override

Definition at line 2672 of file SIInstrInfo.cpp.

References changesVGPRIndexingMode(), llvm::MachineInstr::getOpcode(), llvm::TargetInstrInfo::isSchedulingBoundary(), and llvm::MachineInstr::modifiesRegister().

Referenced by getMachineCSELookAheadLimit().

◆ isSDWA() [1/2]

static bool llvm::SIInstrInfo::isSDWA ( const MachineInstr & MI )

inlinestatic

Definition at line 420 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SDWA, and llvm::MCInstrDesc::TSFlags.

Referenced by findSingleRegDef(), isUseSafeToFold(), and verifyInstruction().

◆ isSDWA() [2/2]

bool llvm::SIInstrInfo::isSDWA ( uint16_t Opcode ) const

inline

Definition at line 424 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SDWA.

◆ isSegmentSpecificFLAT()

static bool llvm::SIInstrInfo::isSegmentSpecificFLAT ( const MachineInstr & MI )

inlinestatic

Definition at line 494 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT, llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::LGKM_CNT, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areMemAccessesTriviallyDisjoint(), and isFLATScratch().

◆ isSGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isSGPRSpill ( const MachineInstr & MI )

inlinestatic

Definition at line 541 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SGPRSpill, and llvm::MCInstrDesc::TSFlags.

Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isSGPRSpill() [2/2]

bool llvm::SIInstrInfo::isSGPRSpill ( uint16_t Opcode ) const

inline

Definition at line 545 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SGPRSpill.

◆ isSGPRStackAccess()

unsigned SIInstrInfo::isSGPRStackAccess	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

Definition at line 5835 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::getIndex(), getNamedOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isFI().

Referenced by getMCOpcodeFromPseudo(), isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isSMRD() [1/2]

static bool llvm::SIInstrInfo::isSMRD ( const MachineInstr & MI )

inlinestatic

◆ isSMRD() [2/2]

bool llvm::SIInstrInfo::isSMRD ( uint16_t Opcode ) const

inline

Definition at line 456 of file SIInstrInfo.h.

References isBufferSMRD(), and llvm::SIInstrFlags::SMRD.

◆ isSOP1() [1/2]

static bool llvm::SIInstrInfo::isSOP1 ( const MachineInstr & MI )

inlinestatic

Definition at line 348 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOP1, and llvm::MCInstrDesc::TSFlags.

◆ isSOP1() [2/2]

bool llvm::SIInstrInfo::isSOP1 ( uint16_t Opcode ) const

inline

Definition at line 352 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOP1.

◆ isSOP2() [1/2]

static bool llvm::SIInstrInfo::isSOP2 ( const MachineInstr & MI )

inlinestatic

Definition at line 356 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOP2, and llvm::MCInstrDesc::TSFlags.

Referenced by verifyInstruction().

◆ isSOP2() [2/2]

bool llvm::SIInstrInfo::isSOP2 ( uint16_t Opcode ) const

inline

Definition at line 360 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOP2.

◆ isSOPC() [1/2]

static bool llvm::SIInstrInfo::isSOPC ( const MachineInstr & MI )

inlinestatic

Definition at line 364 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOPC, and llvm::MCInstrDesc::TSFlags.

Referenced by verifyInstruction().

◆ isSOPC() [2/2]

bool llvm::SIInstrInfo::isSOPC ( uint16_t Opcode ) const

inline

Definition at line 368 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPC.

◆ isSOPK() [1/2]

static bool llvm::SIInstrInfo::isSOPK ( const MachineInstr & MI )

inlinestatic

Definition at line 372 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOPK, and llvm::MCInstrDesc::TSFlags.

Referenced by verifyInstruction().

◆ isSOPK() [2/2]

bool llvm::SIInstrInfo::isSOPK ( uint16_t Opcode ) const

inline

Definition at line 376 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPK.

◆ isSOPP() [1/2]

static bool llvm::SIInstrInfo::isSOPP ( const MachineInstr & MI )

inlinestatic

Definition at line 380 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOPP, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet().

◆ isSOPP() [2/2]

bool llvm::SIInstrInfo::isSOPP ( uint16_t Opcode ) const

inline

Definition at line 384 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPP.

◆ isStackAccess()

unsigned SIInstrInfo::isStackAccess	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

Definition at line 5822 of file SIInstrInfo.cpp.

References assert(), getAddrSpace(), llvm::MachineOperand::getIndex(), getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), and AMDGPUAS::PRIVATE_ADDRESS.

Referenced by getMCOpcodeFromPseudo(), isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isStoreToStackSlot()

unsigned SIInstrInfo::isStoreToStackSlot	(	const MachineInstr &	MI,
		int &	FrameIndex
	)		const

override

Definition at line 5857 of file SIInstrInfo.cpp.

References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and llvm::MachineInstr::mayStore().

Referenced by getMCOpcodeFromPseudo().

◆ isVALU() [1/2]

static bool llvm::SIInstrInfo::isVALU ( const MachineInstr & MI )

inlinestatic

Definition at line 332 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VALU.

Referenced by addRegsToSet(), llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), llvm::GCNSubtarget::getMaxNumVGPRs(), isOperandLegal(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and shouldReadExec().

◆ isVALU() [2/2]

bool llvm::SIInstrInfo::isVALU ( uint16_t Opcode ) const

inline

Definition at line 336 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VALU.

◆ isVGPRCopy()

bool llvm::SIInstrInfo::isVGPRCopy ( const MachineInstr & MI ) const

inline

Definition at line 663 of file SIInstrInfo.h.

References assert(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isCopy(), and llvm::SIRegisterInfo::isSGPRReg().

Referenced by FoldImmediate().

◆ isVGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isVGPRSpill ( const MachineInstr & MI )

inlinestatic

Definition at line 533 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VGPRSpill.

Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isVGPRSpill() [2/2]

bool llvm::SIInstrInfo::isVGPRSpill ( uint16_t Opcode ) const

inline

Definition at line 537 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VGPRSpill.

◆ isVINTRP() [1/2]

static bool llvm::SIInstrInfo::isVINTRP ( const MachineInstr & MI )

inlinestatic

Definition at line 565 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VINTRP.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isVINTRP() [2/2]

bool llvm::SIInstrInfo::isVINTRP ( uint16_t Opcode ) const

inline

Definition at line 569 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VINTRP.

◆ isVMEM() [1/2]

static bool llvm::SIInstrInfo::isVMEM ( const MachineInstr & MI )

inlinestatic

Definition at line 340 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), and isMUBUF().

Referenced by addRegsToSet(), callWaitsOnFunctionReturn(), llvm::GCNHazardRecognizer::getHazardType(), llvm::GCNSubtarget::getMaxNumVGPRs(), isVMEMClauseInst(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isVMEM() [2/2]

bool llvm::SIInstrInfo::isVMEM ( uint16_t Opcode ) const

inline

Definition at line 344 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), and isMUBUF().

◆ isVOP1() [1/2]

static bool llvm::SIInstrInfo::isVOP1 ( const MachineInstr & MI )

inlinestatic

Definition at line 396 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOP1.

Referenced by foldImmediates(), isIdentityValue(), and verifyInstruction().

◆ isVOP1() [2/2]

bool llvm::SIInstrInfo::isVOP1 ( uint16_t Opcode ) const

inline

Definition at line 400 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP1.

◆ isVOP2() [1/2]

static bool llvm::SIInstrInfo::isVOP2 ( const MachineInstr & MI )

inlinestatic

Definition at line 404 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOP2.

Referenced by foldImmediates(), isIdentityValue(), legalizeOperands(), and verifyInstruction().

◆ isVOP2() [2/2]

bool llvm::SIInstrInfo::isVOP2 ( uint16_t Opcode ) const

inline

Definition at line 408 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP2.

◆ isVOP3() [1/2]

static bool llvm::SIInstrInfo::isVOP3 ( const MachineInstr & MI )

inlinestatic

Definition at line 412 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOP3.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), getInstSizeInBytes(), isIdentityValue(), isImmOperandLegal(), isOperandLegal(), legalizeOperands(), and verifyInstruction().

◆ isVOP3() [2/2]

bool llvm::SIInstrInfo::isVOP3 ( uint16_t Opcode ) const

inline

Definition at line 416 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP3.

◆ isVOP3P() [1/2]

static bool llvm::SIInstrInfo::isVOP3P ( const MachineInstr & MI )

inlinestatic

Definition at line 557 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOP3P.

◆ isVOP3P() [2/2]

bool llvm::SIInstrInfo::isVOP3P ( uint16_t Opcode ) const

inline

Definition at line 561 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP3P.

◆ isVOPC() [1/2]

static bool llvm::SIInstrInfo::isVOPC ( const MachineInstr & MI )

inlinestatic

Definition at line 428 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOPC.

Referenced by addRegsToSet(), findSingleRegDef(), foldImmediates(), legalizeOperands(), and verifyInstruction().

◆ isVOPC() [2/2]

bool llvm::SIInstrInfo::isVOPC ( uint16_t Opcode ) const

inline

Definition at line 432 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOPC.

◆ isWave32()

bool llvm::SIInstrInfo::isWave32 ( ) const

Definition at line 6449 of file SIInstrInfo.cpp.

Referenced by getMCOpcodeFromPseudo().

◆ isWQM() [1/2]

static bool llvm::SIInstrInfo::isWQM ( const MachineInstr & MI )

inlinestatic

Definition at line 517 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::WQM.

◆ isWQM() [2/2]

bool llvm::SIInstrInfo::isWQM ( uint16_t Opcode ) const

inline

Definition at line 521 of file SIInstrInfo.h.

References llvm::SIInstrFlags::WQM.

◆ legalizeGenericOperand()

void SIInstrInfo::legalizeGenericOperand	(	MachineBasicBlock &	InsertMBB,
		MachineBasicBlock::iterator	I,
		const TargetRegisterClass *	DstRC,
		MachineOperand &	Op,
		MachineRegisterInfo &	MRI,
		const DebugLoc &	DL
	)		const

◆ legalizeOperands()

void SIInstrInfo::legalizeOperands	(	MachineInstr &	MI,
		MachineDominatorTree *	MDT = `nullptr`
	)		const

Legalize all operands in this instruction.

This function may create new instructions and control-flow around MI. If present, MDT is updated.

Definition at line 4435 of file SIInstrInfo.cpp.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter(), FoldImmediate(), getOpSize(), and moveToVALU().

◆ legalizeOperandsSMRD()

void SIInstrInfo::legalizeOperandsSMRD	(	MachineRegisterInfo &	MRI,
		MachineInstr &	MI
	)		const

Definition at line 4177 of file SIInstrInfo.cpp.

References getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), MI, MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().

Referenced by getOpSize(), and legalizeOperands().

◆ legalizeOperandsVOP2()

void SIInstrInfo::legalizeOperandsVOP2	(	MachineRegisterInfo &	MRI,
		MachineInstr &	MI
	)		const

Legalize operands in MI by either commuting it or inserting a copy of src1.

Definition at line 3936 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), commuteOpcode(), llvm::MachineRegisterInfo::createVirtualRegister(), findImplicitSGPRRead(), fixImplicitOperands(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isCommutable(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), isLegalRegOperand(), isLiteralConstantLike(), llvm::MachineOperand::isReg(), legalizeOpWithMove(), llvm_unreachable, MI, llvm::MCInstrDesc::OpInfo, Reg, llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setSubReg().

Referenced by getOpSize(), and legalizeOperands().

◆ legalizeOperandsVOP3()

void SIInstrInfo::legalizeOperandsVOP3	(	MachineRegisterInfo &	MRI,
		MachineInstr &	MI
	)		const

Fix operands in MI to satisfy constant bus requirements.

Definition at line 4048 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::count(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::getDebugLoc(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::insert(), isLiteralConstantLike(), isOperandLegal(), llvm::MachineOperand::isReg(), legalizeOpWithMove(), MI, and Reg.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), getOpSize(), and legalizeOperands().

◆ legalizeOpWithMove()

void SIInstrInfo::legalizeOpWithMove	(	MachineInstr &	MI,
		unsigned	OpIdx
	)		const

Legalize the OpIndex operand of this instruction by inserting a MOV.

For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1

If the operand being legalized is a register, then a COPY will be used instead of MOV.

Definition at line 3746 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), I, llvm::MachineOperand::isReg(), MI, MRI, Reg, Size, and TRI.

Referenced by getOpSize(), legalizeOperandsVOP2(), and legalizeOperandsVOP3().

◆ loadRegFromStackSlot()

void SIInstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const

override

Definition at line 1177 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, llvm::MachineBasicBlock::findDebugLoc(), getAGPRSpillRestoreOpcode(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), getSGPRSpillRestoreOpcode(), llvm::TargetRegisterInfo::getSpillSize(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVGPRSpillRestoreOpcode(), llvm::SIRegisterInfo::hasAGPRs(), llvm::GCNSubtarget::hasScalarStores(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isSGPRClass(), llvm::Register::isVirtualRegister(), llvm::MachineMemOperand::MOLoad, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::TargetStackID::SGPRSpill, Size, and llvm::SIRegisterInfo::spillSGPRToVGPR().

Referenced by getRegisterInfo().

◆ materializeImmediate()

void SIInstrInfo::materializeImmediate	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		const DebugLoc &	DL,
		unsigned	DestReg,
		int64_t	Value
	)		const

Definition at line 751 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::SIRegisterInfo::isSGPRClass(), MRI, and llvm::ArrayRef< T >::size().

Referenced by containsNewBackedge(), convertNonUniformLoopRegion(), getRegisterInfo(), and removeExternalCFGEdges().

◆ mayAccessFlatAddressSpace()

bool SIInstrInfo::mayAccessFlatAddressSpace ( const MachineInstr & MI ) const

Definition at line 5950 of file SIInstrInfo.cpp.

References AMDGPUAS::FLAT_ADDRESS, isFLAT(), llvm::MachineInstr::memoperands(), and llvm::MachineInstr::memoperands_empty().

Referenced by getMCOpcodeFromPseudo().

◆ mayReadEXEC()

bool SIInstrInfo::mayReadEXEC	(	const MachineRegisterInfo &	MRI,
		const MachineInstr &	MI
	)		const

Returns true if the instruction could potentially depend on the value of exec.

If false, exec dependencies may safely be ignored.

Definition at line 2734 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::isCall(), llvm::MachineInstr::isCopyLike(), llvm::MachineInstr::isMetaInstruction(), isSALU(), llvm::SIRegisterInfo::isSGPRReg(), llvm::isTargetSpecificOpcode(), and llvm::MachineInstr::readsRegister().

Referenced by hasVGPRUses().

◆ moveToVALU()

void SIInstrInfo::moveToVALU	(	MachineInstr &	MI,
		MachineDominatorTree *	MDT = `nullptr`
	)		const

Replace this instruction's opcode with the equivalent VALU opcode.

This function will also move the users of MI to the VALU if necessary. If present, MDT is updated.

Definition at line 4728 of file SIInstrInfo.cpp.

Referenced by getOpSize(), and hoistAndMergeSGPRInits().

◆ pseudoToMCOpcode()

int SIInstrInfo::pseudoToMCOpcode ( int Opcode ) const

Return a target-specific opcode if Opcode is a pseudo instruction.

Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.

Definition at line 6219 of file SIInstrInfo.cpp.

References llvm::SIInstrFlags::D16Buf, llvm::AMDGPU::getMCOpcode(), llvm::AMDGPUSubtarget::GFX10, GFX80, llvm::AMDGPUSubtarget::GFX9, GFX9, llvm::SIInstrFlags::renamedInGFX9, llvm::SIInstrFlags::SDWA, SDWA, SDWA10, SDWA9, and subtargetEncodingFamily().

Referenced by commuteOpcode(), convertToThreeAddress(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), findSingleRegDef(), FoldImmediate(), getMCOpcodeFromPseudo(), getPermuteMask(), hasVALU32BitEncoding(), and isLegalMUBUFImmOffset().

◆ readlaneVGPRToSGPR()

unsigned SIInstrInfo::readlaneVGPRToSGPR	(	unsigned	SrcReg,
		MachineInstr &	UseMI,
		MachineRegisterInfo &	MRI
	)		const

Copy a value from a VGPR (SrcReg) to SGPR.

This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.

Returns: The SGPR register that SrcReg was copied to.

Definition at line 4135 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and UseMI.

Referenced by getOpSize(), legalizeOperands(), and legalizeOperandsSMRD().

◆ removeBranch()

unsigned SIInstrInfo::removeBranch	(	MachineBasicBlock &	MBB,
		int *	BytesRemoved = `nullptr`
	)		const

override

Definition at line 1961 of file SIInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), getInstSizeInBytes(), and I.

Referenced by commuteOpcode(), and isFunctionEntryBlock().

◆ reverseBranchCondition()

bool SIInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > & Cond ) const

override

Definition at line 2051 of file SIInstrInfo.cpp.

References llvm::SmallVectorBase::size().

Referenced by commuteOpcode().

◆ shouldClusterMemOps()

bool SIInstrInfo::shouldClusterMemOps	(	const MachineOperand &	BaseOp1,
		const MachineOperand &	BaseOp2,
		unsigned	NumLoads
	)		const

override

◆ shouldScheduleLoadsNear()

bool SIInstrInfo::shouldScheduleLoadsNear	(	SDNode *	Load0,
		SDNode *	Load1,
		int64_t	Offset0,
		int64_t	Offset1,
		unsigned	NumLoads
	)		const

override

Definition at line 497 of file SIInstrInfo.cpp.

References assert().

Referenced by getRegisterInfo().

◆ sopkIsZext() [1/2]

static bool llvm::SIInstrInfo::sopkIsZext ( const MachineInstr & MI )

inlinestatic

Definition at line 601 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOPK_ZEXT, and llvm::MCInstrDesc::TSFlags.

Referenced by shrinkScalarCompare(), and verifyInstruction().

◆ sopkIsZext() [2/2]

bool llvm::SIInstrInfo::sopkIsZext ( uint16_t Opcode ) const

inline

Definition at line 605 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPK_ZEXT.

◆ storeRegToStackSlot()

void SIInstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MI,
		unsigned	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const

override

Definition at line 1043 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, llvm::MachineBasicBlock::findDebugLoc(), getAGPRSpillSaveOpcode(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), getSGPRSpillSaveOpcode(), llvm::TargetRegisterInfo::getSpillSize(), llvm::SIMachineFunctionInfo::getStackPtrOffsetReg(), getVGPRSpillSaveOpcode(), llvm::SIRegisterInfo::hasAGPRs(), llvm::GCNSubtarget::hasScalarStores(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isSGPRClass(), llvm::Register::isVirtualRegister(), llvm::MachineMemOperand::MOStore, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::SIMachineFunctionInfo::setHasSpilledVGPRs(), llvm::TargetStackID::SGPRSpill, Size, and llvm::SIRegisterInfo::spillSGPRToVGPR().

Referenced by getRegisterInfo().

◆ swapSourceModifiers()

bool SIInstrInfo::swapSourceModifiers	(	MachineInstr &	MI,
		MachineOperand &	Src0,
		unsigned	Src0OpName,
		MachineOperand &	Src1,
		unsigned	Src1OpName
	)		const

protected

Definition at line 1570 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), and llvm::MachineOperand::setImm().

Referenced by commuteInstructionImpl().

◆ usesConstantBus()

bool SIInstrInfo::usesConstantBus	(	const MachineRegisterInfo &	MRI,
		const MachineOperand &	MO,
		const MCOperandInfo &	OpInfo
	)		const

Returns true if this operand uses the constant bus.

Definition at line 3048 of file SIInstrInfo.cpp.

References contains(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::MachineOperand::isUse(), and llvm::Register::isVirtualRegister().

Referenced by isLiteralConstant(), isOperandLegal(), and verifyInstruction().

◆ usesFPDPRounding() [1/2]

static bool llvm::SIInstrInfo::usesFPDPRounding ( const MachineInstr & MI )

inlinestatic

Definition at line 647 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPDPRounding, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::createSIModeRegisterPass().

◆ usesFPDPRounding() [2/2]

bool llvm::SIInstrInfo::usesFPDPRounding ( uint16_t Opcode ) const

inline

Definition at line 651 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPDPRounding.

◆ usesLGKM_CNT()

static bool llvm::SIInstrInfo::usesLGKM_CNT ( const MachineInstr & MI )

inlinestatic

Definition at line 597 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::LGKM_CNT, and llvm::MCInstrDesc::TSFlags.

◆ usesVM_CNT()

static bool llvm::SIInstrInfo::usesVM_CNT ( const MachineInstr & MI )

inlinestatic

Definition at line 593 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VM_CNT.

◆ verifyInstruction()

bool SIInstrInfo::verifyInstruction	(	const MachineInstr &	MI,
		StringRef &	ErrInfo
	)		const

override

Definition at line 3138 of file SIInstrInfo.cpp.

Referenced by isLiteralConstant().

The documentation for this class was generated from the following files:

lib/Target/AMDGPU/SIInstrInfo.h
lib/Target/AMDGPU/SIInstrInfo.cpp

Public Types

Public Member Functions

Static Public Member Functions

Protected Member Functions

Detailed Description

Member Enumeration Documentation

◆ TargetOperandFlags

Constructor & Destructor Documentation

◆ SIInstrInfo()

Member Function Documentation

◆ analyzeBranch()

◆ analyzeBranchImpl()

◆ areLoadsFromSameBasePtr()

◆ areMemAccessesTriviallyDisjoint()

◆ buildExtractSubReg()

◆ buildExtractSubRegOrImm()

◆ buildShrunkInst()

◆ calculateLDSSpillAddress()

◆ canInsertSelect()

◆ canShrink()

◆ commuteInstructionImpl()

◆ commuteOpcode() [1/2]

◆ commuteOpcode() [2/2]

◆ convertNonUniformIfRegion()

◆ convertNonUniformLoopRegion()

◆ convertToThreeAddress()

◆ copyPhysReg()

◆ createPHIDestinationCopy()

◆ createPHISourceCopy()

◆ CreateTargetPostRAHazardRecognizer() [1/2]

◆ CreateTargetPostRAHazardRecognizer() [2/2]

◆ decomposeMachineOperandsTargetFlags()

◆ expandPostRAPseudo()

◆ findCommutedOpIndices() [1/2]

◆ findCommutedOpIndices() [2/2]

◆ fixImplicitOperands()

◆ FoldImmediate()

◆ getAddNoCarry() [1/2]

◆ getAddNoCarry() [2/2]

◆ getAddressSpaceForPseudoSourceKind()

◆ getBranchDestBlock()

◆ getClampMask()

◆ getDefaultRsrcDataFormat()

◆ getInstBundleSize()

◆ getInstSizeInBytes()

◆ getKillTerminatorFromPseudo()

◆ getMachineCSELookAheadLimit()

◆ getMCOpcodeFromPseudo()

◆ getMemOperandWithOffset()

◆ getMovOpcode()

◆ getNamedImmOperand()

◆ getNamedOperand() [1/2]

◆ getNamedOperand() [2/2]

◆ getNumWaitStates()

◆ getOpRegClass()

◆ getOpSize() [1/2]

◆ getOpSize() [2/2]

◆ getPreferredSelectRegClass()

◆ getRegClass()

◆ getRegisterInfo()

◆ getScratchRsrcWords23()

◆ getSerializableDirectMachineOperandTargetFlags()

◆ getSerializableTargetIndices()

◆ getVALUOp()

◆ hasAnyModifiersSet()

◆ hasFPClamp() [1/2]

◆ hasFPClamp() [2/2]

◆ hasIntClamp()

◆ hasModifiers()

◆ hasModifiersSet()

◆ hasUnwantedEffectsWhenEXECEmpty()

◆ hasVALU32BitEncoding()

◆ hasVGPRUses()

◆ insertBranch()

◆ insertEQ()

◆ insertIndirectBranch()

◆ insertNE()

◆ insertNoop()

◆ insertReturn()

◆ insertSelect()