LLVM  9.0.0svn
Public Types | Public Member Functions | Static Public Member Functions | Protected Member Functions | List of all members
llvm::SIInstrInfo Class Referencefinal

#include "Target/AMDGPU/SIInstrInfo.h"

Inheritance diagram for llvm::SIInstrInfo:
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Public Types

enum  TargetOperandFlags {
  MO_MASK = 0x7, MO_NONE = 0, MO_GOTPCREL = 1, MO_GOTPCREL32 = 2,
  MO_GOTPCREL32_LO = 2, MO_GOTPCREL32_HI = 3, MO_REL32 = 4, MO_REL32_LO = 4,
  MO_REL32_HI = 5
}
 

Public Member Functions

unsigned buildExtractSubReg (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
 
MachineOperand buildExtractSubRegOrImm (MachineBasicBlock::iterator MI, MachineRegisterInfo &MRI, MachineOperand &SuperReg, const TargetRegisterClass *SuperRC, unsigned SubIdx, const TargetRegisterClass *SubRC) const
 
 SIInstrInfo (const GCNSubtarget &ST)
 
const SIRegisterInfo & getRegisterInfo () const
 
bool isReallyTriviallyReMaterializable (const MachineInstr &MI, AliasAnalysis *AA) const override
 
bool areLoadsFromSameBasePtr (SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override
 
bool getMemOperandWithOffset (const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, const TargetRegisterInfo *TRI) const final
 
bool shouldClusterMemOps (const MachineOperand &BaseOp1, const MachineOperand &BaseOp2, unsigned NumLoads) const override
 
bool shouldScheduleLoadsNear (SDNode *Load0, SDNode *Load1, int64_t Offset0, int64_t Offset1, unsigned NumLoads) const override
 
void copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
 
unsigned calculateLDSSpillAddress (MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg, unsigned Offset, unsigned Size) const
 
void materializeImmediate (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, int64_t Value) const
 
const TargetRegisterClass * getPreferredSelectRegClass (unsigned Size) const
 
unsigned insertNE (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
 
unsigned insertEQ (MachineBasicBlock *MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned SrcReg, int Value) const
 
void storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
void loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
 
bool expandPostRAPseudo (MachineInstr &MI) const override
 
unsigned getMovOpcode (const TargetRegisterClass *DstRC) const
 
LLVM_READONLY int commuteOpcode (unsigned Opc) const
 
LLVM_READONLY int commuteOpcode (const MachineInstr &MI) const
 
bool findCommutedOpIndices (MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override
 
bool findCommutedOpIndices (MCInstrDesc Desc, unsigned &SrcOpIdx0, unsigned &SrcOpIdx1) const
 
bool isBranchOffsetInRange (unsigned BranchOpc, int64_t BrOffset) const override
 
MachineBasicBlock * getBranchDestBlock (const MachineInstr &MI) const override
 
unsigned insertIndirectBranch (MachineBasicBlock &MBB, MachineBasicBlock &NewDestBB, const DebugLoc &DL, int64_t BrOffset, RegScavenger *RS=nullptr) const override
 
bool analyzeBranchImpl (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const
 
bool analyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const override
 
unsigned removeBranch (MachineBasicBlock &MBB, int *BytesRemoved=nullptr) const override
 
unsigned insertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef< MachineOperand > Cond, const DebugLoc &DL, int *BytesAdded=nullptr) const override
 
bool reverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
 
bool canInsertSelect (const MachineBasicBlock &MBB, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const override
 
void insertSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const override
 
void insertVectorSelect (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DstReg, ArrayRef< MachineOperand > Cond, unsigned TrueReg, unsigned FalseReg) const
 
unsigned getAddressSpaceForPseudoSourceKind (unsigned Kind) const override
 
bool areMemAccessesTriviallyDisjoint (const MachineInstr &MIa, const MachineInstr &MIb, AliasAnalysis *AA=nullptr) const override
 
bool isFoldableCopy (const MachineInstr &MI) const
 
bool FoldImmediate (MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, MachineRegisterInfo *MRI) const final
 
unsigned getMachineCSELookAheadLimit () const override
 
MachineInstr * convertToThreeAddress (MachineFunction::iterator &MBB, MachineInstr &MI, LiveVariables *LV) const override
 
bool isSchedulingBoundary (const MachineInstr &MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
 
bool isSALU (uint16_t Opcode) const
 
bool isVALU (uint16_t Opcode) const
 
bool isVMEM (uint16_t Opcode) const
 
bool isSOP1 (uint16_t Opcode) const
 
bool isSOP2 (uint16_t Opcode) const
 
bool isSOPC (uint16_t Opcode) const
 
bool isSOPK (uint16_t Opcode) const
 
bool isSOPP (uint16_t Opcode) const
 
bool isPacked (uint16_t Opcode) const
 
bool isVOP1 (uint16_t Opcode) const
 
bool isVOP2 (uint16_t Opcode) const
 
bool isVOP3 (uint16_t Opcode) const
 
bool isSDWA (uint16_t Opcode) const
 
bool isVOPC (uint16_t Opcode) const
 
bool isMUBUF (uint16_t Opcode) const
 
bool isMTBUF (uint16_t Opcode) const
 
bool isSMRD (uint16_t Opcode) const
 
bool isBufferSMRD (const MachineInstr &MI) const
 
bool isDS (uint16_t Opcode) const
 
bool isAlwaysGDS (uint16_t Opcode) const
 
bool isMIMG (uint16_t Opcode) const
 
bool isGather4 (uint16_t Opcode) const
 
bool isFLAT (uint16_t Opcode) const
 
bool isEXP (uint16_t Opcode) const
 
bool isWQM (uint16_t Opcode) const
 
bool isDisableWQM (uint16_t Opcode) const
 
bool isVGPRSpill (uint16_t Opcode) const
 
bool isSGPRSpill (uint16_t Opcode) const
 
bool isDPP (uint16_t Opcode) const
 
bool isVOP3P (uint16_t Opcode) const
 
bool isVINTRP (uint16_t Opcode) const
 
bool sopkIsZext (uint16_t Opcode) const
 
bool isScalarStore (uint16_t Opcode) const
 
bool isFixedSize (uint16_t Opcode) const
 
bool hasFPClamp (uint16_t Opcode) const
 
uint64_t getClampMask (const MachineInstr &MI) const
 
bool usesFPDPRounding (uint16_t Opcode) const
 
bool isVGPRCopy (const MachineInstr &MI) const
 
bool hasUnwantedEffectsWhenEXECEmpty (const MachineInstr &MI) const
 Whether we must prevent this instruction from executing with EXEC = 0. More...
 
bool mayReadEXEC (const MachineRegisterInfo &MRI, const MachineInstr &MI) const
 Returns true if the instruction could potentially depend on the value of exec. More...
 
bool isInlineConstant (const APInt &Imm) const
 
bool isInlineConstant (const MachineOperand &MO, uint8_t OperandType) const
 
bool isInlineConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isInlineConstant (const MachineInstr &MI, const MachineOperand &UseMO, const MachineOperand &DefMO) const
 returns true if UseMO is substituted with DefMO in MI it would be an inline immediate. More...
 
bool isInlineConstant (const MachineInstr &MI, unsigned OpIdx) const
 returns true if the operand OpIdx in MI is a valid inline immediate. More...
 
bool isInlineConstant (const MachineInstr &MI, unsigned OpIdx, const MachineOperand &MO) const
 
bool isInlineConstant (const MachineOperand &MO) const
 
bool isLiteralConstant (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isLiteralConstant (const MachineInstr &MI, int OpIdx) const
 
bool isLiteralConstantLike (const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 
bool isImmOperandLegal (const MachineInstr &MI, unsigned OpNo, const MachineOperand &MO) const
 
bool hasVALU32BitEncoding (unsigned Opcode) const
 Return true if this 64-bit VALU instruction has a 32-bit encoding. More...
 
bool usesConstantBus (const MachineRegisterInfo &MRI, const MachineOperand &MO, const MCOperandInfo &OpInfo) const
 Returns true if this operand uses the constant bus. More...
 
bool hasModifiers (unsigned Opcode) const
 Return true if this instruction has any modifiers. More...
 
bool hasModifiersSet (const MachineInstr &MI, unsigned OpName) const
 
bool hasAnyModifiersSet (const MachineInstr &MI) const
 
bool canShrink (const MachineInstr &MI, const MachineRegisterInfo &MRI) const
 
MachineInstr * buildShrunkInst (MachineInstr &MI, unsigned NewOpcode) const
 
bool verifyInstruction (const MachineInstr &MI, StringRef &ErrInfo) const override
 
unsigned getVALUOp (const MachineInstr &MI) const
 
const TargetRegisterClass * getOpRegClass (const MachineInstr &MI, unsigned OpNo) const
 Return the correct register class for OpNo. More...
 
unsigned getOpSize (uint16_t Opcode, unsigned OpNo) const
 Return the size in bytes of the operand OpNo on the given. More...
 
unsigned getOpSize (const MachineInstr &MI, unsigned OpNo) const
 This form should usually be preferred since it handles operands with unknown register classes. More...
 
void legalizeOpWithMove (MachineInstr &MI, unsigned OpIdx) const
 Legalize the OpIndex operand of this instruction by inserting a MOV. More...
 
bool isOperandLegal (const MachineInstr &MI, unsigned OpIdx, const MachineOperand *MO=nullptr) const
 Check if MO is a legal operand if it was the OpIdx Operand for MI. More...
 
bool isLegalVSrcOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
 Check if MO would be a valid operand for the given operand definition OpInfo. More...
 
bool isLegalRegOperand (const MachineRegisterInfo &MRI, const MCOperandInfo &OpInfo, const MachineOperand &MO) const
 Check if MO (a register operand) is a legal register for the given operand description. More...
 
void legalizeOperandsVOP2 (MachineRegisterInfo &MRI, MachineInstr &MI) const
 Legalize operands in MI by either commuting it or inserting a copy of src1. More...
 
void legalizeOperandsVOP3 (MachineRegisterInfo &MRI, MachineInstr &MI) const
 Fix operands in MI to satisfy constant bus requirements. More...
 
unsigned readlaneVGPRToSGPR (unsigned SrcReg, MachineInstr &UseMI, MachineRegisterInfo &MRI) const
 Copy a value from a VGPR (SrcReg) to SGPR. More...
 
void legalizeOperandsSMRD (MachineRegisterInfo &MRI, MachineInstr &MI) const
 
void legalizeGenericOperand (MachineBasicBlock &InsertMBB, MachineBasicBlock::iterator I, const TargetRegisterClass *DstRC, MachineOperand &Op, MachineRegisterInfo &MRI, const DebugLoc &DL) const
 
void legalizeOperands (MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
 Legalize all operands in this instruction. More...
 
void moveToVALU (MachineInstr &MI, MachineDominatorTree *MDT=nullptr) const
 Replace this instruction's opcode with the equivalent VALU opcode. More...
 
void insertWaitStates (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, int Count) const
 
void insertNoop (MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override
 
void insertReturn (MachineBasicBlock &MBB) const
 
LLVM_READONLY MachineOperand * getNamedOperand (MachineInstr &MI, unsigned OperandName) const
 Returns the operand named Op. More...
 
LLVM_READONLY const MachineOperand * getNamedOperand (const MachineInstr &MI, unsigned OpName) const
 
int64_t getNamedImmOperand (const MachineInstr &MI, unsigned OpName) const
 Get required immediate operand. More...
 
uint64_t getDefaultRsrcDataFormat () const
 
uint64_t getScratchRsrcWords23 () const
 
bool isLowLatencyInstruction (const MachineInstr &MI) const
 
bool isHighLatencyInstruction (const MachineInstr &MI) const
 
const MCInstrDesc & getMCOpcodeFromPseudo (unsigned Opcode) const
 Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode. More...
 
unsigned isStackAccess (const MachineInstr &MI, int &FrameIndex) const
 
unsigned isSGPRStackAccess (const MachineInstr &MI, int &FrameIndex) const
 
unsigned isLoadFromStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned isStoreToStackSlot (const MachineInstr &MI, int &FrameIndex) const override
 
unsigned getInstBundleSize (const MachineInstr &MI) const
 
unsigned getInstSizeInBytes (const MachineInstr &MI) const override
 
bool mayAccessFlatAddressSpace (const MachineInstr &MI) const
 
bool isNonUniformBranchInstr (MachineInstr &Instr) const
 
void convertNonUniformIfRegion (MachineBasicBlock *IfEntry, MachineBasicBlock *IfEnd) const
 
void convertNonUniformLoopRegion (MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const
 
std::pair< unsigned, unsigned > decomposeMachineOperandsTargetFlags (unsigned TF) const override
 
ArrayRef< std::pair< int, const char * > > getSerializableTargetIndices () const override
 
ArrayRef< std::pair< unsigned, const char * > > getSerializableDirectMachineOperandTargetFlags () const override
 
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer (const InstrItineraryData *II, const ScheduleDAG *DAG) const override
 This is used by the post-RA scheduler (SchedulePostRAList.cpp). More...
 
ScheduleHazardRecognizer * CreateTargetPostRAHazardRecognizer (const MachineFunction &MF) const override
 This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass. More...
 
bool isBasicBlockPrologue (const MachineInstr &MI) const override
 
MachineInstrBuilder getAddNoCarry (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, unsigned DestReg) const
 Return a partially built integer add instruction without carry. More...
 
const MCInstrDesc & getKillTerminatorFromPseudo (unsigned Opcode) const
 
int pseudoToMCOpcode (int Opcode) const
 Return a target-specific opcode if Opcode is a pseudo instruction. More...
 

Static Public Member Functions

static bool isSALU (const MachineInstr &MI)
 
static bool isVALU (const MachineInstr &MI)
 
static bool isVMEM (const MachineInstr &MI)
 
static bool isSOP1 (const MachineInstr &MI)
 
static bool isSOP2 (const MachineInstr &MI)
 
static bool isSOPC (const MachineInstr &MI)
 
static bool isSOPK (const MachineInstr &MI)
 
static bool isSOPP (const MachineInstr &MI)
 
static bool isPacked (const MachineInstr &MI)
 
static bool isVOP1 (const MachineInstr &MI)
 
static bool isVOP2 (const MachineInstr &MI)
 
static bool isVOP3 (const MachineInstr &MI)
 
static bool isSDWA (const MachineInstr &MI)
 
static bool isVOPC (const MachineInstr &MI)
 
static bool isMUBUF (const MachineInstr &MI)
 
static bool isMTBUF (const MachineInstr &MI)
 
static bool isSMRD (const MachineInstr &MI)
 
static bool isDS (const MachineInstr &MI)
 
static bool isMIMG (const MachineInstr &MI)
 
static bool isGather4 (const MachineInstr &MI)
 
static bool isFLAT (const MachineInstr &MI)
 
static bool isSegmentSpecificFLAT (const MachineInstr &MI)
 
static bool isEXP (const MachineInstr &MI)
 
static bool isWQM (const MachineInstr &MI)
 
static bool isDisableWQM (const MachineInstr &MI)
 
static bool isVGPRSpill (const MachineInstr &MI)
 
static bool isSGPRSpill (const MachineInstr &MI)
 
static bool isDPP (const MachineInstr &MI)
 
static bool isVOP3P (const MachineInstr &MI)
 
static bool isVINTRP (const MachineInstr &MI)
 
static bool isScalarUnit (const MachineInstr &MI)
 
static bool usesVM_CNT (const MachineInstr &MI)
 
static bool usesLGKM_CNT (const MachineInstr &MI)
 
static bool sopkIsZext (const MachineInstr &MI)
 
static bool isScalarStore (const MachineInstr &MI)
 
static bool isFixedSize (const MachineInstr &MI)
 
static bool hasFPClamp (const MachineInstr &MI)
 
static bool hasIntClamp (const MachineInstr &MI)
 
static bool usesFPDPRounding (const MachineInstr &MI)
 
static unsigned getNumWaitStates (const MachineInstr &MI)
 Return the number of wait states that result from executing this instruction. More...
 
static bool isKillTerminator (unsigned Opcode)
 
static bool isLegalMUBUFImmOffset (unsigned Imm)
 

Protected Member Functions

bool swapSourceModifiers (MachineInstr &MI, MachineOperand &Src0, unsigned Src0OpName, MachineOperand &Src1, unsigned Src1OpName) const
 
MachineInstr * commuteInstructionImpl (MachineInstr &MI, bool NewMI, unsigned OpIdx0, unsigned OpIdx1) const override
 

Detailed Description

Definition at line 45 of file SIInstrInfo.h.

Member Enumeration Documentation

◆ TargetOperandFlags

enum llvm::SIInstrInfo::TargetOperandFlags
Enumerator
MO_MASK 
MO_NONE 
MO_GOTPCREL 
MO_GOTPCREL32 
MO_GOTPCREL32_LO 
MO_GOTPCREL32_HI 
MO_REL32 
MO_REL32_LO 
MO_REL32_HI 

Definition at line 145 of file SIInstrInfo.h.

Constructor & Destructor Documentation

◆ SIInstrInfo()

SIInstrInfo::SIInstrInfo ( const GCNSubtarget &  ST)
explicit

Definition at line 86 of file SIInstrInfo.cpp.

Member Function Documentation

◆ analyzeBranch()

bool SIInstrInfo::analyzeBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify = false 
) const
override

Definition at line 1684 of file SIInstrInfo.cpp.

References analyzeBranchImpl(), E, llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), I, and llvm_unreachable.

Referenced by commuteOpcode(), and isFunctionEntryBlock().

◆ analyzeBranchImpl()

bool SIInstrInfo::analyzeBranchImpl ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
MachineBasicBlock *&  TBB,
MachineBasicBlock *&  FBB,
SmallVectorImpl< MachineOperand > &  Cond,
bool  AllowModify 
) const

Definition at line 1641 of file SIInstrInfo.cpp.

References llvm::MachineOperand::CreateImm(), llvm::MachineBasicBlock::end(), I, and llvm::SmallVectorTemplateBase< T >::push_back().

Referenced by analyzeBranch(), and commuteOpcode().

◆ areLoadsFromSameBasePtr()

bool SIInstrInfo::areLoadsFromSameBasePtr ( SDNode *  Load1,
SDNode *  Load2,
int64_t &  Offset1,
int64_t &  Offset2 
) const
override

Definition at line 144 of file SIInstrInfo.cpp.

References assert(), llvm::dyn_cast(), llvm::SDNode::getMachineOpcode(), llvm::AMDGPU::getNamedOperandIdx(), getNumOperandsNoGlue(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), isDS(), llvm::SDNode::isMachineOpcode(), isMTBUF(), isMUBUF(), isSMRD(), and nodesHaveSameOperandValue().

Referenced by getRegisterInfo().

◆ areMemAccessesTriviallyDisjoint()

bool SIInstrInfo::areMemAccessesTriviallyDisjoint ( const MachineInstr &  MIa,
const MachineInstr &  MIb,
AliasAnalysis *  AA = nullptr 
) const
override

Definition at line 2266 of file SIInstrInfo.cpp.

References assert(), llvm::MachineInstr::hasOrderedMemoryRef(), llvm::MachineInstr::hasUnmodeledSideEffects(), isDS(), isFLAT(), isMTBUF(), isMUBUF(), isSegmentSpecificFLAT(), isSMRD(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().

Referenced by commuteOpcode().

◆ buildExtractSubReg()

unsigned SIInstrInfo::buildExtractSubReg ( MachineBasicBlock::iterator  MI,
MachineRegisterInfo &  MRI,
MachineOperand &  SuperReg,
const TargetRegisterClass *  SuperRC,
unsigned  SubIdx,
const TargetRegisterClass *  SubRC 
) const

Definition at line 3502 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), and SubReg.

Referenced by buildExtractSubRegOrImm(), and extractRsrcPtr().

◆ buildExtractSubRegOrImm()

MachineOperand SIInstrInfo::buildExtractSubRegOrImm ( MachineBasicBlock::iterator  MI,
MachineRegisterInfo &  MRI,
MachineOperand &  SuperReg,
const TargetRegisterClass *  SuperRC,
unsigned  SubIdx,
const TargetRegisterClass *  SubRC 
) const

Definition at line 3534 of file SIInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), assert(), buildExtractSubReg(), llvm::MachineOperand::CreateImm(), llvm::MachineOperand::CreateReg(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isImm(), llvm_unreachable, llvm::MachineInstr::RemoveOperand(), and SubReg.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter(), and moveToVALU().

◆ buildShrunkInst()

MachineInstr * SIInstrInfo::buildShrunkInst ( MachineInstr &  MI,
unsigned  NewOpcode 
) const

Definition at line 2764 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), assert(), llvm::BuildMI(), copyFlagsToImplicitVCC(), llvm::MachineInstr::getDebugLoc(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), and llvm::MachineOperand::getReg().

Referenced by isLiteralConstant(), and updateOperand().

◆ calculateLDSSpillAddress()

unsigned SIInstrInfo::calculateLDSSpillAddress ( MachineBasicBlock &  MBB,
MachineInstr &  MI,
RegScavenger *  RS,
unsigned  TmpReg,
unsigned  FrameOffset,
unsigned  Size 
) const
Parameters

Definition at line 1057 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineBasicBlock::addLiveIn(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::RegScavenger::enterBasicBlock(), llvm::MachineBasicBlock::findDebugLoc(), llvm::SIRegisterInfo::findUnusedRegister(), llvm::MachineBasicBlock::front(), llvm::MachineFunction::front(), getAddNoCarry(), llvm::Function::getCallingConv(), llvm::MachineFunction::getFunction(), llvm::MachineFunction::getInfo(), llvm::AMDGPUMachineFunction::getLDSSize(), llvm::SIMachineFunctionInfo::getMaxFlatWorkGroupSize(), llvm::MachineBasicBlock::getParent(), llvm::SIMachineFunctionInfo::getPreloadedReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), llvm::SIMachineFunctionInfo::getTIDReg(), llvm::SIMachineFunctionInfo::hasCalculatedTID(), llvm::MachineBasicBlock::isLiveIn(), llvm::AMDGPU::isShader(), llvm::AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR, llvm::SI::KernelInputOffsets::NGROUPS_Y, llvm::SI::KernelInputOffsets::NGROUPS_Z, Reg, llvm::RegScavenger::scavengeRegister(), llvm::SIMachineFunctionInfo::setTIDReg(), llvm::AMDGPU::HSAMD::Kernel::CodeProps::Key::WavefrontSize, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_X, llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Y, and llvm::AMDGPUFunctionArgInfo::WORKGROUP_ID_Z.

Referenced by getRegisterInfo().

◆ canInsertSelect()

bool SIInstrInfo::canInsertSelect ( const MachineBasicBlock &  MBB,
ArrayRef< MachineOperand >  Cond,
unsigned  TrueReg,
unsigned  FalseReg,
int &  CondCycles,
int &  TrueCycles,
int &  FalseCycles 
) const
override

Definition at line 1853 of file SIInstrInfo.cpp.

References assert(), llvm::TargetRegisterClass::getID(), llvm::MachineBasicBlock::getParent(), llvm::AMDGPU::getRegBitWidth(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::isSGPRClass(), and MRI.

Referenced by commuteOpcode().

◆ canShrink()

bool SIInstrInfo::canShrink ( const MachineInstr &  MI,
const MachineRegisterInfo &  MRI 
) const

Definition at line 2693 of file SIInstrInfo.cpp.

References getNamedOperand(), llvm::MachineInstr::getOpcode(), llvm::MachineOperand::getReg(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isReg(), and llvm::SIRegisterInfo::isVGPR().

Referenced by findSingleRegDef(), and isLiteralConstant().

◆ commuteInstructionImpl()

MachineInstr * SIInstrInfo::commuteInstructionImpl ( MachineInstr &  MI,
bool  NewMI,
unsigned  OpIdx0,
unsigned  OpIdx1 
) const
overrideprotected

Definition at line 1406 of file SIInstrInfo.cpp.

References assert(), llvm::TargetInstrInfo::commuteInstructionImpl(), commuteOpcode(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::MachineInstr::setDesc(), swapRegAndNonRegOperand(), and swapSourceModifiers().

◆ commuteOpcode() [1/2]

int SIInstrInfo::commuteOpcode ( unsigned  Opc) const

Definition at line 615 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getCommuteOrig(), llvm::AMDGPU::getCommuteRev(), and pseudoToMCOpcode().

Referenced by commuteInstructionImpl(), commuteOpcode(), getRegisterInfo(), and legalizeOperandsVOP2().

◆ commuteOpcode() [2/2]

LLVM_READONLY int llvm::SIInstrInfo::commuteOpcode ( const MachineInstr &  MI) const
inline

Definition at line 235 of file SIInstrInfo.h.

References analyzeBranch(), analyzeBranchImpl(), areMemAccessesTriviallyDisjoint(), canInsertSelect(), commuteOpcode(), DefMI, findCommutedOpIndices(), FoldImmediate(), getAddressSpaceForPseudoSourceKind(), getBranchDestBlock(), llvm::MachineInstr::getOpcode(), insertBranch(), insertIndirectBranch(), insertSelect(), insertVectorSelect(), isBranchOffsetInRange(), isFoldableCopy(), removeBranch(), reverseBranchCondition(), and UseMI.

◆ convertNonUniformIfRegion()

void SIInstrInfo::convertNonUniformIfRegion ( MachineBasicBlock *  IfEntry,
MachineBasicBlock *  IfEnd 
) const

Definition at line 5607 of file SIInstrInfo.cpp.

References add(), llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MCID::Branch, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::MachineBasicBlock::getFirstNonPHI(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), and llvm::MachineBasicBlock::insert().

Referenced by containsNewBackedge(), and getMCOpcodeFromPseudo().

◆ convertNonUniformLoopRegion()

void SIInstrInfo::convertNonUniformLoopRegion ( MachineBasicBlock *  LoopEntry,
MachineBasicBlock *  LoopEnd 
) const

Definition at line 5632 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::MachineBasicBlock::begin(), llvm::MCID::Branch, llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), E, llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineBasicBlock::insert(), materializeImmediate(), llvm::MachineBasicBlock::pred_begin(), and llvm::MachineBasicBlock::pred_end().

Referenced by containsNewBackedge(), and getMCOpcodeFromPseudo().

◆ convertToThreeAddress()

MachineInstr * SIInstrInfo::convertToThreeAddress ( MachineFunction::iterator &  MBB,
MachineInstr &  MI,
LiveVariables *  LV 
) const
override

Definition at line 2329 of file SIInstrInfo.cpp.

References add(), llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineInstr::getDebugLoc(), getFoldableImm(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), isInlineConstant(), isOperandLegal(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRReg(), LLVM_FALLTHROUGH, and pseudoToMCOpcode().

Referenced by getMachineCSELookAheadLimit().

◆ copyPhysReg()

void SIInstrInfo::copyPhysReg ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc &  DL,
unsigned  DestReg,
unsigned  SrcReg,
bool  KillSrc 
) const
override

Definition at line 507 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), contains(), llvm::RegState::Define, llvm::SIRegisterInfo::getHWRegIndex(), llvm::getKillRegState(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::RegState::Implicit, llvm::SIRegisterInfo::isSGPRClass(), reportIllegalCopy(), and llvm::ArrayRef< T >::size().

Referenced by getRegisterInfo().

◆ CreateTargetPostRAHazardRecognizer() [1/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const InstrItineraryData *  II,
const ScheduleDAG *  DAG 
) const
override

This is used by the post-RA scheduler (SchedulePostRAList.cpp).

The post-RA version of misched uses CreateTargetMIHazardRecognizer.

Definition at line 5693 of file SIInstrInfo.cpp.

References llvm::ScheduleDAG::MF.

Referenced by getMCOpcodeFromPseudo().

◆ CreateTargetPostRAHazardRecognizer() [2/2]

ScheduleHazardRecognizer * SIInstrInfo::CreateTargetPostRAHazardRecognizer ( const MachineFunction &  MF) const
override

This is the hazard recognizer used at -O0 by the PostRAHazardRecognizer pass.

Definition at line 5701 of file SIInstrInfo.cpp.

◆ decomposeMachineOperandsTargetFlags()

std::pair< unsigned, unsigned > SIInstrInfo::decomposeMachineOperandsTargetFlags ( unsigned  TF) const
override

Definition at line 5706 of file SIInstrInfo.cpp.

References MO_MASK.

Referenced by getMCOpcodeFromPseudo().

◆ expandPostRAPseudo()

bool SIInstrInfo::expandPostRAPseudo ( MachineInstr &  MI) const
override

Definition at line 1200 of file SIInstrInfo.cpp.

References add(), llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MIBundleBuilder::append(), assert(), llvm::MIBundleBuilder::begin(), llvm::BuildMI(), llvm::RegState::Define, llvm::MachineInstr::eraseFromParent(), llvm::TargetInstrInfo::expandPostRAPseudo(), llvm::finalizeBundle(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineOperand::getImm(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getTargetFlags(), I, llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::MachineOperand::isFPImm(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineInstr::mayLoad(), MO_NONE, Reg, llvm::MachineInstr::setDesc(), SubReg, and llvm::RegState::Undef.

Referenced by getRegisterInfo().

◆ findCommutedOpIndices() [1/2]

bool SIInstrInfo::findCommutedOpIndices ( MachineInstr &  MI,
unsigned &  SrcOpIdx1,
unsigned &  SrcOpIdx2 
) const
override

Definition at line 1458 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc().

Referenced by commuteOpcode(), and tryAddToFoldList().

◆ findCommutedOpIndices() [2/2]

bool SIInstrInfo::findCommutedOpIndices ( MCInstrDesc  Desc,
unsigned &  SrcOpIdx0,
unsigned &  SrcOpIdx1 
) const

Definition at line 1463 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), llvm::MCInstrDesc::getOpcode(), and llvm::MCInstrDesc::isCommutable().

◆ FoldImmediate()

bool SIInstrInfo::FoldImmediate ( MachineInstr &  UseMI,
MachineInstr &  DefMI,
unsigned  Reg,
MachineRegisterInfo *  MRI 
) const
final

Definition at line 2039 of file SIInstrInfo.cpp.

References llvm::MachineInstr::addImplicitDefUseOperands(), assert(), llvm::MachineOperand::ChangeToImmediate(), llvm::tgtok::Def, llvm::MachineInstr::eraseFromParent(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), hasAnyModifiersSet(), llvm::MachineRegisterInfo::hasOneNonDBGUse(), llvm::MachineRegisterInfo::hasOneUse(), llvm::MachineOperand::isImm(), isInlineConstant(), llvm::MachineOperand::isKill(), llvm::MachineInstr::isMoveImmediate(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::SIRegisterInfo::isVGPR(), isVGPRCopy(), pseudoToMCOpcode(), Reg, removeModOperands(), llvm::MachineInstr::RemoveOperand(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and llvm::MachineInstr::untieRegOperand().

Referenced by commuteOpcode(), and legalizeGenericOperand().

◆ getAddNoCarry()

MachineInstrBuilder SIInstrInfo::getAddNoCarry ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
unsigned  DestReg 
) const

Return a partially built integer add instruction without carry.

Caller must add source operands. For pre-GFX9 it will generate unused carry destination operand. TODO: After GFX9 it should return a no-carry operation.

Definition at line 5729 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), and llvm::MachineRegisterInfo::setRegAllocationHint().

Referenced by calculateLDSSpillAddress(), and getMCOpcodeFromPseudo().

◆ getAddressSpaceForPseudoSourceKind()

unsigned SIInstrInfo::getAddressSpaceForPseudoSourceKind ( unsigned  Kind) const
override

Definition at line 2008 of file SIInstrInfo.cpp.

References AMDGPUAS::CONSTANT_ADDRESS, llvm::PseudoSourceValue::ConstantPool, llvm::PseudoSourceValue::ExternalSymbolCallEntry, llvm::PseudoSourceValue::FixedStack, AMDGPUAS::FLAT_ADDRESS, llvm::PseudoSourceValue::GlobalValueCallEntry, llvm::PseudoSourceValue::GOT, llvm::PseudoSourceValue::JumpTable, AMDGPUAS::PRIVATE_ADDRESS, llvm::PseudoSourceValue::Stack, and llvm::PseudoSourceValue::TargetCustom.

Referenced by commuteOpcode().

◆ getBranchDestBlock()

MachineBasicBlock * SIInstrInfo::getBranchDestBlock ( const MachineInstr &  MI) const
override

Definition at line 1496 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by commuteOpcode().

◆ getClampMask()

uint64_t llvm::SIInstrInfo::getClampMask ( const MachineInstr &  MI) const
inline

Definition at line 612 of file SIInstrInfo.h.

References llvm::SIInstrFlags::ClampHi, llvm::SIInstrFlags::ClampLo, llvm::SIInstrFlags::FPClamp, llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::IntClamp, and llvm::MCInstrDesc::TSFlags.

◆ getDefaultRsrcDataFormat()

uint64_t SIInstrInfo::getDefaultRsrcDataFormat ( ) const

Definition at line 5403 of file SIInstrInfo.cpp.

References llvm::AMDGPUSubtarget::GFX10, llvm::AMDGPU::RSRC_DATA_FORMAT, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by extractRsrcPtr(), getNamedImmOperand(), getScratchRsrcWords23(), isStackPtrRelative(), and llvm::SITargetLowering::wrapAddr64Rsrc().

◆ getInstBundleSize()

unsigned SIInstrInfo::getInstBundleSize ( const MachineInstr &  MI) const

Definition at line 5510 of file SIInstrInfo.cpp.

References assert(), E, getInstSizeInBytes(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getParent(), I, llvm::MachineBasicBlock::instr_end(), and Size.

Referenced by getInstSizeInBytes(), and getMCOpcodeFromPseudo().

◆ getInstSizeInBytes()

unsigned SIInstrInfo::getInstSizeInBytes ( const MachineInstr &  MI) const
override

Definition at line 5522 of file SIInstrInfo.cpp.

References llvm::ISD::EH_LABEL, getInstBundleSize(), llvm::TargetMachine::getMCAsmInfo(), getMCOpcodeFromPseudo(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MCInstrDesc::getSize(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::getSymbolName(), llvm::MachineFunction::getTarget(), llvm::ISD::INLINEASM, llvm::ISD::INLINEASM_BR, isFixedSize(), isLiteralConstantLike(), isMIMG(), isSALU(), isVALU(), isVOP3(), llvm::AMDGPUISD::KILL, and llvm::MCInstrDesc::OpInfo.

Referenced by addRegsToSet(), getInstBundleSize(), getMCOpcodeFromPseudo(), llvm::SITargetLowering::getPrefLoopAlignment(), removeBranch(), and llvm::AMDGPUAsmPrinter::runOnMachineFunction().

◆ getKillTerminatorFromPseudo()

const MCInstrDesc & SIInstrInfo::getKillTerminatorFromPseudo ( unsigned  Opcode) const

Definition at line 5754 of file SIInstrInfo.cpp.

References llvm_unreachable.

Referenced by getMCOpcodeFromPseudo(), and llvm::SITargetLowering::splitKillBlock().

◆ getMachineCSELookAheadLimit()

unsigned llvm::SIInstrInfo::getMachineCSELookAheadLimit ( ) const
inlineoverride

Definition at line 308 of file SIInstrInfo.h.

References convertToThreeAddress(), and isSchedulingBoundary().

◆ getMCOpcodeFromPseudo()

const MCInstrDesc& llvm::SIInstrInfo::getMCOpcodeFromPseudo ( unsigned  Opcode) const
inline

Return the descriptor of the target-specific machine instruction that corresponds to the specified pseudo or native opcode.

Definition at line 879 of file SIInstrInfo.h.

References convertNonUniformIfRegion(), convertNonUniformLoopRegion(), CreateTargetPostRAHazardRecognizer(), decomposeMachineOperandsTargetFlags(), getAddNoCarry(), getInstBundleSize(), getInstSizeInBytes(), getKillTerminatorFromPseudo(), getSerializableDirectMachineOperandTargetFlags(), getSerializableTargetIndices(), isBasicBlockPrologue(), isKillTerminator(), isLoadFromStackSlot(), isNonUniformBranchInstr(), isSGPRStackAccess(), isStackAccess(), isStoreToStackSlot(), mayAccessFlatAddressSpace(), and pseudoToMCOpcode().

Referenced by getInstSizeInBytes().

◆ getMemOperandWithOffset()

bool SIInstrInfo::getMemOperandWithOffset ( const MachineInstr &  LdSt,
const MachineOperand *&  BaseOp,
int64_t &  Offset,
const TargetRegisterInfo *  TRI 
) const
final

Definition at line 259 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), getOpRegClass(), llvm::TargetRegisterInfo::getRegSizeInBits(), isDS(), isFLAT(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), isSMRD(), isStride64(), llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().

Referenced by getRegisterInfo(), offsetsDoNotOverlap(), and llvm::SIScheduleDAGMI::schedule().

◆ getMovOpcode()

unsigned SIInstrInfo::getMovOpcode ( const TargetRegisterClass *  DstRC) const

Definition at line 838 of file SIInstrInfo.cpp.

References llvm::SIRegisterInfo::isSGPRClass().

Referenced by getRegisterInfo().

◆ getNamedImmOperand()

int64_t llvm::SIInstrInfo::getNamedImmOperand ( const MachineInstr &  MI,
unsigned  OpName 
) const
inline

Get required immediate operand.

Definition at line 866 of file SIInstrInfo.h.

References getDefaultRsrcDataFormat(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getScratchRsrcWords23(), isHighLatencyInstruction(), and isLowLatencyInstruction().

Referenced by findSingleRegDef(), and legalizeOperands().

◆ getNamedOperand() [1/2]

MachineOperand * SIInstrInfo::getNamedOperand ( MachineInstr &  MI,
unsigned  OperandName 
) const

Returns the operand named Op.

If MI does not have an operand named Op, this function returns nullptr.

Definition at line 5394 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by addRegsToSet(), buildMUBUFOffsetLoadStore(), buildShrunkInst(), canShrink(), convertToThreeAddress(), llvm::createSIModeRegisterPass(), emitIndirectDst(), emitIndirectSrc(), findSingleRegDef(), fixupGlobalSaddr(), FoldImmediate(), getDPPOp(), getHWReg(), getMemOperandWithOffset(), getNamedOperand(), getOpSize(), getOrNonExecReg(), hasAnyNonFlatUseOfReg(), hasModifiersSet(), isIdentityValue(), isSafeToFoldImmIntoCopy(), isSGPRStackAccess(), isStackAccess(), legalizeOperands(), legalizeOperandsSMRD(), loadM0FromVGPR(), optimizeVcndVcmpPair(), setM0ToIndexFromSGPR(), shouldClusterMemOps(), swapSourceModifiers(), tryConstantFoldOp(), tryFoldInst(), and verifyInstruction().

◆ getNamedOperand() [2/2]

LLVM_READONLY const MachineOperand* llvm::SIInstrInfo::getNamedOperand ( const MachineInstr &  MI,
unsigned  OpName 
) const
inline

Definition at line 860 of file SIInstrInfo.h.

References getNamedOperand().

◆ getNumWaitStates()

unsigned SIInstrInfo::getNumWaitStates ( const MachineInstr &  MI)
static

Return the number of wait states that result from executing this instruction.

Definition at line 1191 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), and llvm::MachineInstr::getOperand().

Referenced by llvm::GCNHazardRecognizer::AdvanceCycle(), getOpSize(), and getWaitStatesSince().

◆ getOpRegClass()

const TargetRegisterClass * SIInstrInfo::getOpRegClass ( const MachineInstr &  MI,
unsigned  OpNo 
) const

Return the correct register class for OpNo.

For target-specific instructions, this will return the register class that has been defined in tablegen. For generic instructions, like REG_SEQUENCE it will return the register class of its machine operand. to infer the correct register class base on the other operands.

Definition at line 3457 of file SIInstrInfo.cpp.

References llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineInstr::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), MRI, llvm::MCInstrDesc::OpInfo, Reg, and llvm::MCOperandInfo::RegClass.

Referenced by getMemOperandWithOffset(), getOpSize(), hoistAndMergeSGPRInits(), isLiteralConstant(), legalizeOperands(), moveToVALU(), and verifyInstruction().

◆ getOpSize() [1/2]

unsigned llvm::SIInstrInfo::getOpSize ( uint16_t  Opcode,
unsigned  OpNo 
) const
inline

Return the size in bytes of the operand OpNo on the given.

Definition at line 753 of file SIInstrInfo.h.

References assert(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, and llvm::MCOperandInfo::RegClass.

Referenced by isInlineConstant(), and matchSwap().

◆ getOpSize() [2/2]

unsigned llvm::SIInstrInfo::getOpSize ( const MachineInstr &  MI,
unsigned  OpNo 
) const
inline

This form should usually be preferred since it handles operands with unknown register classes.

Definition at line 767 of file SIInstrInfo.h.

References assert(), getNamedOperand(), getNumWaitStates(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), insertNoop(), insertReturn(), insertWaitStates(), isLegalRegOperand(), isLegalVSrcOperand(), isOperandLegal(), llvm::MachineOperand::isReg(), legalizeGenericOperand(), legalizeOperands(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), legalizeOpWithMove(), LLVM_READONLY, moveToVALU(), readlaneVGPRToSGPR(), and SubReg.

◆ getPreferredSelectRegClass()

const TargetRegisterClass * SIInstrInfo::getPreferredSelectRegClass ( unsigned  Size) const

Definition at line 690 of file SIInstrInfo.cpp.

Referenced by createBBSelectReg(), and getRegisterInfo().

◆ getRegisterInfo()

const SIRegisterInfo& llvm::SIInstrInfo::getRegisterInfo ( ) const
inline

Definition at line 165 of file SIInstrInfo.h.

References areLoadsFromSameBasePtr(), calculateLDSSpillAddress(), commuteOpcode(), copyPhysReg(), expandPostRAPseudo(), llvm::ISD::FrameIndex, getMemOperandWithOffset(), getMovOpcode(), getPreferredSelectRegClass(), I, insertEQ(), insertNE(), isReallyTriviallyReMaterializable(), LLVM_READONLY, loadRegFromStackSlot(), materializeImmediate(), shouldClusterMemOps(), shouldScheduleLoadsNear(), Size, storeRegToStackSlot(), and TRI.

Referenced by llvm::SIFrameLowering::emitEntryFunctionPrologue(), emitIndirectDst(), emitIndirectSrc(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), getAllSGPRs(), llvm::GCNSubtarget::getRegisterInfo(), hasAnyNonFlatUseOfReg(), insertUndefLaneMask(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), matchSwap(), setM0ToIndexFromSGPR(), tryAddToFoldList(), and tryConstantFoldOp().

◆ getScratchRsrcWords23()

uint64_t SIInstrInfo::getScratchRsrcWords23 ( ) const

Definition at line 5425 of file SIInstrInfo.cpp.

References getDefaultRsrcDataFormat(), llvm::AMDGPUSubtarget::GFX9, llvm::Log2_32(), llvm::AMDGPU::RSRC_DATA_FORMAT, llvm::AMDGPU::RSRC_ELEMENT_SIZE_SHIFT, llvm::AMDGPU::RSRC_INDEX_STRIDE_SHIFT, llvm::AMDGPU::RSRC_TID_ENABLE, and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::SIFrameLowering::emitEntryFunctionPrologue(), and getNamedImmOperand().

◆ getSerializableDirectMachineOperandTargetFlags()

ArrayRef< std::pair< unsigned, const char * > > SIInstrInfo::getSerializableDirectMachineOperandTargetFlags ( ) const
override

Definition at line 5711 of file SIInstrInfo.cpp.

References llvm::makeArrayRef(), MO_GOTPCREL, MO_GOTPCREL32_HI, MO_GOTPCREL32_LO, MO_REL32_HI, and MO_REL32_LO.

Referenced by getMCOpcodeFromPseudo().

◆ getSerializableTargetIndices()

ArrayRef< std::pair< int, const char * > > SIInstrInfo::getSerializableTargetIndices ( ) const
override

Definition at line 5680 of file SIInstrInfo.cpp.

References llvm::makeArrayRef(), llvm::AMDGPU::TI_CONSTDATA_START, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD0, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD1, llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD2, and llvm::AMDGPU::TI_SCRATCH_RSRC_DWORD3.

Referenced by getMCOpcodeFromPseudo().

◆ getVALUOp()

unsigned SIInstrInfo::getVALUOp ( const MachineInstr &  MI) const

Definition at line 3381 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isReg(), llvm_unreachable, and llvm::SIInstrFlags::WQM.

Referenced by isLiteralConstant(), and moveToVALU().

◆ hasAnyModifiersSet()

bool SIInstrInfo::hasAnyModifiersSet ( const MachineInstr &  MI) const

Definition at line 2685 of file SIInstrInfo.cpp.

References hasModifiersSet().

Referenced by FoldImmediate(), and isLiteralConstant().

◆ hasFPClamp() [1/2]

static bool llvm::SIInstrInfo::hasFPClamp ( const MachineInstr &  MI)
inlinestatic

Definition at line 600 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

◆ hasFPClamp() [2/2]

bool llvm::SIInstrInfo::hasFPClamp ( uint16_t  Opcode) const
inline

Definition at line 604 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPClamp.

◆ hasIntClamp()

static bool llvm::SIInstrInfo::hasIntClamp ( const MachineInstr &  MI)
inlinestatic

Definition at line 608 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::IntClamp, and llvm::MCInstrDesc::TSFlags.

◆ hasModifiers()

bool SIInstrInfo::hasModifiers ( unsigned  Opcode) const

Return true if this instruction has any modifiers.

e.g. src[012]_mod, omod, clamp.

Definition at line 2671 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getNamedOperandIdx().

Referenced by isLiteralConstant().

◆ hasModifiersSet()

bool SIInstrInfo::hasModifiersSet ( const MachineInstr &  MI,
unsigned  OpName 
) const

Definition at line 2679 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), and getNamedOperand().

Referenced by canShrink(), findSingleRegDef(), hasAnyModifiersSet(), isLiteralConstant(), and optimizeVcndVcmpPair().

◆ hasUnwantedEffectsWhenEXECEmpty()

bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty ( const MachineInstr &  MI) const

Whether we must prevent this instruction from executing with EXEC = 0.

Definition at line 2472 of file SIInstrInfo.cpp.

References llvm::AMDGPUISD::DS_ORDERED_COUNT, llvm::SIInstrFlags::EXP, llvm::MachineInstr::getOpcode(), llvm::MachineInstr::isCall(), llvm::MachineInstr::isInlineAsm(), isSMRD(), and llvm::MachineInstr::mayStore().

Referenced by isVGPRCopy().

◆ hasVALU32BitEncoding()

bool SIInstrInfo::hasVALU32BitEncoding ( unsigned  Opcode) const

Return true if this 64-bit VALU instruction has a 32-bit encoding.

This function will return false if you pass it a 32-bit instruction.

Definition at line 2663 of file SIInstrInfo.cpp.

References llvm::AMDGPU::getVOPe32(), and pseudoToMCOpcode().

Referenced by canShrink(), isIdentityValue(), and isLiteralConstant().

◆ insertBranch()

unsigned SIInstrInfo::insertBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock *  TBB,
MachineBasicBlock *  FBB,
ArrayRef< MachineOperand >  Cond,
const DebugLoc &  DL,
int *  BytesAdded = nullptr 
) const
override

Definition at line 1781 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addMBB(), assert(), llvm::BuildMI(), llvm::ArrayRef< T >::empty(), llvm::MachineInstr::getOperand(), isUndef(), preserveCondRegFlags(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setIsUndef(), and llvm::ArrayRef< T >::size().

Referenced by commuteOpcode().

◆ insertEQ()

unsigned SIInstrInfo::insertEQ ( MachineBasicBlock *  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
unsigned  SrcReg,
int  Value 
) const

Definition at line 812 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MRI, and Reg.

Referenced by getRegisterInfo(), and removeExternalCFGEdges().

◆ insertIndirectBranch()

unsigned SIInstrInfo::insertIndirectBranch ( MachineBasicBlock &  MBB,
MachineBasicBlock &  NewDestBB,
const DebugLoc &  DL,
int64_t  BrOffset,
RegScavenger *  RS = nullptr 
) const
override

Definition at line 1507 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearVirtRegs(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Define, llvm::MachineBasicBlock::empty(), llvm::MachineBasicBlock::end(), llvm::RegScavenger::enterBasicBlockEnd(), llvm::MachineBasicBlock::getParent(), I, MRI, llvm::MachineBasicBlock::pred_size(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::RegScavenger::scavengeRegisterBackwards(), llvm::RegScavenger::setRegUsed(), llvm::AMDGPU::TF_LONG_BRANCH_BACKWARD, and llvm::AMDGPU::TF_LONG_BRANCH_FORWARD.

Referenced by commuteOpcode().

◆ insertNE()

unsigned SIInstrInfo::insertNE ( MachineBasicBlock *  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
unsigned  SrcReg,
int  Value 
) const

Definition at line 825 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), MRI, and Reg.

Referenced by getRegisterInfo(), and isFunctionEntryBlock().

◆ insertNoop()

void SIInstrInfo::insertNoop ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI 
) const
override

Definition at line 1168 of file SIInstrInfo.cpp.

References insertWaitStates().

Referenced by getOpSize().

◆ insertReturn()

void SIInstrInfo::insertReturn ( MachineBasicBlock &  MBB) const

Definition at line 1173 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), assert(), llvm::BuildMI(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineBasicBlock::getParent(), Info, llvm::AMDGPUMachineFunction::isEntryFunction(), llvm::SIMachineFunctionInfo::returnsVoid(), and llvm::MachineBasicBlock::succ_empty().

Referenced by containsNewBackedge(), and getOpSize().

◆ insertSelect()

void SIInstrInfo::insertSelect ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
unsigned  DstReg,
ArrayRef< MachineOperand >  Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const
override

Definition at line 1893 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), MRI, preserveCondRegFlags(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MCID::Select, and std::swap().

Referenced by commuteOpcode().

◆ insertVectorSelect()

void SIInstrInfo::insertVectorSelect ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I,
const DebugLoc &  DL,
unsigned  DstReg,
ArrayRef< MachineOperand >  Cond,
unsigned  TrueReg,
unsigned  FalseReg 
) const

Definition at line 694 of file SIInstrInfo.cpp.

Referenced by commuteOpcode().

◆ insertWaitStates()

void SIInstrInfo::insertWaitStates ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
int  Count 
) const

Definition at line 1152 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), Arg, llvm::BuildMI(), and llvm::MachineBasicBlock::findDebugLoc().

Referenced by getOpSize(), and insertNoop().

◆ isAlwaysGDS()

bool SIInstrInfo::isAlwaysGDS ( uint16_t  Opcode) const

Definition at line 2462 of file SIInstrInfo.cpp.

References llvm::AMDGPUISD::DS_ORDERED_COUNT.

Referenced by isDS(), and isSendMsgTraceDataOrGDS().

◆ isBasicBlockPrologue()

bool SIInstrInfo::isBasicBlockPrologue ( const MachineInstr &  MI) const
override

Definition at line 5723 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::isTerminator(), and llvm::MachineInstr::modifiesRegister().

Referenced by getMCOpcodeFromPseudo().

◆ isBranchOffsetInRange()

bool SIInstrInfo::isBranchOffsetInRange ( unsigned  BranchOpc,
int64_t  BrOffset 
) const
override

Definition at line 1480 of file SIInstrInfo.cpp.

References assert(), BranchOffsetBits, and llvm::isIntN().

Referenced by commuteOpcode().

◆ isBufferSMRD()

bool SIInstrInfo::isBufferSMRD ( const MachineInstr &  MI) const

Definition at line 5765 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), isSMRD(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by addRegsToSet(), and isSMRD().

◆ isDisableWQM() [1/2]

static bool llvm::SIInstrInfo::isDisableWQM ( const MachineInstr &  MI)
inlinestatic

Definition at line 514 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

◆ isDisableWQM() [2/2]

bool llvm::SIInstrInfo::isDisableWQM ( uint16_t  Opcode) const
inline

Definition at line 518 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DisableWQM.

◆ isDPP() [1/2]

static bool llvm::SIInstrInfo::isDPP ( const MachineInstr &  MI)
inlinestatic

Definition at line 538 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isDPP() [2/2]

bool llvm::SIInstrInfo::isDPP ( uint16_t  Opcode) const
inline

Definition at line 542 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DPP.

◆ isDS() [1/2]

static bool llvm::SIInstrInfo::isDS ( const MachineInstr &  MI)
inlinestatic

Definition at line 456 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::GCNSubtarget::getMaxNumVGPRs(), getMemOperandWithOffset(), isSendMsgTraceDataOrGDS(), and shouldClusterMemOps().

◆ isDS() [2/2]

bool llvm::SIInstrInfo::isDS ( uint16_t  Opcode) const
inline

Definition at line 460 of file SIInstrInfo.h.

References llvm::SIInstrFlags::DS, and isAlwaysGDS().

◆ isEXP() [1/2]

static bool llvm::SIInstrInfo::isEXP ( const MachineInstr &  MI)
inlinestatic

Definition at line 498 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by hasDataDependencyPred().

◆ isEXP() [2/2]

bool llvm::SIInstrInfo::isEXP ( uint16_t  Opcode) const
inline

Definition at line 502 of file SIInstrInfo.h.

References llvm::SIInstrFlags::EXP.

◆ isFixedSize() [1/2]

static bool llvm::SIInstrInfo::isFixedSize ( const MachineInstr &  MI)
inlinestatic

Definition at line 592 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by getInstSizeInBytes().

◆ isFixedSize() [2/2]

bool llvm::SIInstrInfo::isFixedSize ( uint16_t  Opcode) const
inline

Definition at line 596 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FIXED_SIZE.

◆ isFLAT() [1/2]

static bool llvm::SIInstrInfo::isFLAT ( const MachineInstr &  MI)
inlinestatic

Definition at line 482 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areMemAccessesTriviallyDisjoint(), llvm::GCNHazardRecognizer::getHazardType(), llvm::GCNSubtarget::getMaxNumVGPRs(), getMemOperandWithOffset(), hasAnyNonFlatUseOfReg(), isVMEMClauseInst(), mayAccessFlatAddressSpace(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldClusterMemOps(), and verifyInstruction().

◆ isFLAT() [2/2]

bool llvm::SIInstrInfo::isFLAT ( uint16_t  Opcode) const
inline

Definition at line 494 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT.

◆ isFoldableCopy()

bool SIInstrInfo::isFoldableCopy ( const MachineInstr &  MI) const

Definition at line 1987 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), and llvm::MachineInstr::getOpcode().

Referenced by commuteOpcode(), and findSingleRegDef().

◆ isGather4() [1/2]

static bool llvm::SIInstrInfo::isGather4 ( const MachineInstr &  MI)
inlinestatic

Definition at line 474 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::SITargetLowering::PostISelFolding(), and verifyInstruction().

◆ isGather4() [2/2]

bool llvm::SIInstrInfo::isGather4 ( uint16_t  Opcode) const
inline

Definition at line 478 of file SIInstrInfo.h.

References llvm::SIInstrFlags::Gather4.

◆ isHighLatencyInstruction()

bool SIInstrInfo::isHighLatencyInstruction ( const MachineInstr &  MI) const

Definition at line 5455 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), isMIMG(), isMTBUF(), and isMUBUF().

Referenced by getNamedImmOperand(), and llvm::SIScheduleDAGMI::schedule().

◆ isImmOperandLegal()

bool SIInstrInfo::isImmOperandLegal ( const MachineInstr &  MI,
unsigned  OpNo,
const MachineOperand &  MO 
) const

Definition at line 2636 of file SIInstrInfo.cpp.

References assert(), llvm::MachineInstr::getDesc(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getSubtarget(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isInlineConstant(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVOP3(), llvm::SIRegisterInfo::opCanUseInlineConstant(), llvm::SIRegisterInfo::opCanUseLiteralConstant(), llvm::MCOI::OPERAND_IMMEDIATE, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.

Referenced by isLiteralConstant(), and isOperandLegal().

◆ isInlineConstant() [1/7]

bool SIInstrInfo::isInlineConstant ( const APInt &  Imm) const

Definition at line 2528 of file SIInstrInfo.cpp.

References llvm::APInt::getBitWidth(), llvm::APInt::getSExtValue(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::AMDGPU::isInlinableLiteral16(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), and llvm_unreachable.

Referenced by bitOpWithConstantIsReducible(), convertToThreeAddress(), llvm::createR600ISelDag(), FoldImmediate(), getSplatConstantFP(), isImmOperandLegal(), isInlineConstant(), isInlineConstantIfFolded(), isKImmOperand(), isKImmOrKUImmOperand(), isKUImmOperand(), isLiteralConstant(), isLiteralConstantLike(), isReverseInlineImm(), isVGPRCopy(), usesConstantBus(), and verifyInstruction().

◆ isInlineConstant() [2/7]

bool SIInstrInfo::isInlineConstant ( const MachineOperand &  MO,
uint8_t  OperandType 
) const

Definition at line 2548 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::AMDGPUSubtarget::has16BitInsts(), llvm::AMDGPUSubtarget::hasInv2PiInlineImm(), llvm::MachineOperand::isImm(), llvm::AMDGPU::isInlinableLiteral16(), llvm::AMDGPU::isInlinableLiteral32(), llvm::AMDGPU::isInlinableLiteral64(), llvm::AMDGPU::isInlinableLiteralV216(), llvm::isInt< 16 >(), llvm::isUInt< 16 >(), llvm_unreachable, llvm::AMDGPU::OPERAND_REG_IMM_FP16, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_FP64, llvm::AMDGPU::OPERAND_REG_IMM_INT16, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::AMDGPU::OPERAND_REG_IMM_V2FP16, llvm::AMDGPU::OPERAND_REG_IMM_V2INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_V2INT16, llvm::AMDGPU::OPERAND_SRC_FIRST, and llvm::AMDGPU::OPERAND_SRC_LAST.

◆ isInlineConstant() [3/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand &  MO,
const MCOperandInfo &  OpInfo 
) const
inline

Definition at line 647 of file SIInstrInfo.h.

References isInlineConstant(), and llvm::MCOperandInfo::OperandType.

◆ isInlineConstant() [4/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr &  MI,
const MachineOperand &  UseMO,
const MachineOperand &  DefMO 
) const
inline

returns true if UseMO is substituted with DefMO in MI it would be an inline immediate.

Definition at line 654 of file SIInstrInfo.h.

References assert(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperandNo(), llvm::MachineOperand::getParent(), isInlineConstant(), MI, llvm::MCInstrDesc::NumOperands, and llvm::MCInstrDesc::OpInfo.

◆ isInlineConstant() [5/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr &  MI,
unsigned  OpIdx 
) const
inline

returns true if the operand OpIdx in MI is a valid inline immediate.

Definition at line 668 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), isInlineConstant(), llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

◆ isInlineConstant() [6/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineInstr &  MI,
unsigned  OpIdx,
const MachineOperand &  MO 
) const
inline

Definition at line 673 of file SIInstrInfo.h.

References assert(), llvm::MachineInstr::getDesc(), getOpSize(), llvm::MachineInstr::isCopy(), isInlineConstant(), llvm::MCInstrDesc::NumOperands, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_IMM_INT64, llvm::MCOperandInfo::OperandType, and llvm::MCInstrDesc::OpInfo.

◆ isInlineConstant() [7/7]

bool llvm::SIInstrInfo::isInlineConstant ( const MachineOperand &  MO) const
inline

Definition at line 690 of file SIInstrInfo.h.

References llvm::MachineInstr::getOperandNo(), llvm::MachineOperand::getParent(), and isInlineConstant().

◆ isKillTerminator()

bool SIInstrInfo::isKillTerminator ( unsigned  Opcode)
static

Definition at line 5744 of file SIInstrInfo.cpp.

Referenced by getMCOpcodeFromPseudo(), and isSimpleIf().

◆ isLegalMUBUFImmOffset()

static bool llvm::SIInstrInfo::isLegalMUBUFImmOffset ( unsigned  Imm)
inlinestatic

Definition at line 934 of file SIInstrInfo.h.

References pseudoToMCOpcode().

Referenced by getConstantValue(), and isStackPtrRelative().

◆ isLegalRegOperand()

bool SIInstrInfo::isLegalRegOperand ( const MachineRegisterInfo &  MRI,
const MCOperandInfo &  OpInfo,
const MachineOperand &  MO 
) const

Check if MO (a register operand) is a legal register for the given operand description.

Definition at line 3563 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::getSubReg(), llvm::SIRegisterInfo::getSubRegClass(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::isVirtualRegister(), Reg, llvm::MCOperandInfo::RegClass, and TRI.

Referenced by getOpSize(), isLegalVSrcOperand(), isOperandLegal(), and legalizeOperandsVOP2().

◆ isLegalVSrcOperand()

bool SIInstrInfo::isLegalVSrcOperand ( const MachineRegisterInfo &  MRI,
const MCOperandInfo &  OpInfo,
const MachineOperand &  MO 
) const

Check if MO would be a valid operand for the given operand definition OpInfo.

Note this does not attempt to validate constant bus restrictions (e.g. literal constant usage).

Definition at line 3591 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isLegalRegOperand(), llvm::MachineOperand::isReg(), and llvm::MachineOperand::isTargetIndex().

Referenced by getOpSize().

◆ isLiteralConstant() [1/2]

bool llvm::SIInstrInfo::isLiteralConstant ( const MachineOperand &  MO,
const MCOperandInfo &  OpInfo 
) const
inline

Definition at line 695 of file SIInstrInfo.h.

References llvm::MachineOperand::isImm(), isInlineConstant(), and llvm::MCOperandInfo::OperandType.

◆ isLiteralConstant() [2/2]

bool llvm::SIInstrInfo::isLiteralConstant ( const MachineInstr &  MI,
int  OpIdx 
) const
inline

Definition at line 700 of file SIInstrInfo.h.

References buildShrunkInst(), canShrink(), llvm::MachineInstr::getOperand(), getOpRegClass(), getVALUOp(), hasAnyModifiersSet(), hasModifiers(), hasModifiersSet(), hasVALU32BitEncoding(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isInlineConstant(), isLiteralConstantLike(), usesConstantBus(), and verifyInstruction().

◆ isLiteralConstantLike()

bool SIInstrInfo::isLiteralConstantLike ( const MachineOperand &  MO,
const MCOperandInfo &  OpInfo 
) const

Definition at line 2603 of file SIInstrInfo.cpp.

References llvm::MachineOperand::getType(), isInlineConstant(), llvm_unreachable, llvm::MachineOperand::MO_ExternalSymbol, llvm::MachineOperand::MO_FrameIndex, llvm::MachineOperand::MO_GlobalAddress, llvm::MachineOperand::MO_Immediate, llvm::MachineOperand::MO_MachineBasicBlock, llvm::MachineOperand::MO_MCSymbol, and llvm::MachineOperand::MO_Register.

Referenced by getInstSizeInBytes(), isLiteralConstant(), isOperandLegal(), legalizeOperandsVOP2(), and legalizeOperandsVOP3().

◆ isLoadFromStackSlot()

unsigned SIInstrInfo::isLoadFromStackSlot ( const MachineInstr &  MI,
int &  FrameIndex 
) const
override

Definition at line 5482 of file SIInstrInfo.cpp.

References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and llvm::MachineInstr::mayLoad().

Referenced by getMCOpcodeFromPseudo().

◆ isLowLatencyInstruction()

bool SIInstrInfo::isLowLatencyInstruction ( const MachineInstr &  MI) const

Definition at line 5449 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and isSMRD().

Referenced by getNamedImmOperand(), llvm::SIScheduleDAGMI::schedule(), and llvm::SIScheduleDAGMI::SIScheduleDAGMI().

◆ isMIMG() [1/2]

static bool llvm::SIInstrInfo::isMIMG ( const MachineInstr &  MI)
inlinestatic

Definition at line 466 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::MIMG, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), getInstSizeInBytes(), isHighLatencyInstruction(), isVMEM(), legalizeOperands(), llvm::SITargetLowering::PostISelFolding(), and verifyInstruction().

◆ isMIMG() [2/2]

bool llvm::SIInstrInfo::isMIMG ( uint16_t  Opcode) const
inline

Definition at line 470 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MIMG.

◆ isMTBUF() [1/2]

static bool llvm::SIInstrInfo::isMTBUF ( const MachineInstr &  MI)
inlinestatic

Definition at line 438 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::MTBUF, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), getMemOperandWithOffset(), isHighLatencyInstruction(), isVMEM(), legalizeOperands(), and shouldClusterMemOps().

◆ isMTBUF() [2/2]

bool llvm::SIInstrInfo::isMTBUF ( uint16_t  Opcode) const
inline

Definition at line 442 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MTBUF.

◆ isMUBUF() [1/2]

static bool llvm::SIInstrInfo::isMUBUF ( const MachineInstr &  MI)
inlinestatic

Definition at line 430 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::MUBUF, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), getMemOperandWithOffset(), llvm::SIRegisterInfo::getMUBUFInstrOffset(), llvm::SIRegisterInfo::isFrameOffsetLegal(), isHighLatencyInstruction(), isLoadFromStackSlot(), isStoreToStackSlot(), isVMEM(), legalizeOperands(), and shouldClusterMemOps().

◆ isMUBUF() [2/2]

bool llvm::SIInstrInfo::isMUBUF ( uint16_t  Opcode) const
inline

Definition at line 434 of file SIInstrInfo.h.

References llvm::SIInstrFlags::MUBUF.

◆ isNonUniformBranchInstr()

bool SIInstrInfo::isNonUniformBranchInstr ( MachineInstr &  Instr) const

Definition at line 5603 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by getMCOpcodeFromPseudo().

◆ isOperandLegal()

bool SIInstrInfo::isOperandLegal ( const MachineInstr &  MI,
unsigned  OpIdx,
const MachineOperand *  MO = nullptr 
) const

Check if MO is a legal operand if it was the OpIdx Operand for MI.

Definition at line 3602 of file SIInstrInfo.cpp.

References assert(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::count(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::getSubReg(), llvm::MachineFunction::getSubtarget(), llvm::GCNSubtarget::hasVOP3Literal(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::insert(), llvm::MachineOperand::isFI(), llvm::MachineOperand::isImm(), isImmOperandLegal(), isLegalRegOperand(), isLiteralConstantLike(), llvm::MachineOperand::isReg(), llvm::AMDGPU::isSISrcOperand(), llvm::MachineOperand::isTargetIndex(), isVALU(), isVOP3(), MRI, llvm::AMDGPU::OPERAND_KIMM32, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::MCOperandInfo::RegClass, and usesConstantBus().

Referenced by commuteInstructionImpl(), convertToThreeAddress(), getDPPOp(), getOpSize(), tryAddToFoldList(), and tryChangeVGPRtoSGPRinCopy().

◆ isPacked() [1/2]

static bool llvm::SIInstrInfo::isPacked ( const MachineInstr &  MI)
inlinestatic

Definition at line 382 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::IsPacked, and llvm::MCInstrDesc::TSFlags.

◆ isPacked() [2/2]

bool llvm::SIInstrInfo::isPacked ( uint16_t  Opcode) const
inline

Definition at line 386 of file SIInstrInfo.h.

References llvm::SIInstrFlags::IsPacked.

◆ isReallyTriviallyReMaterializable()

bool SIInstrInfo::isReallyTriviallyReMaterializable ( const MachineInstr &  MI,
AliasAnalysis *  AA 
) const
override

Definition at line 128 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), and llvm::MachineInstr::getOpcode().

Referenced by getRegisterInfo().

◆ isSALU() [1/2]

static bool llvm::SIInstrInfo::isSALU ( const MachineInstr &  MI)
inlinestatic

Definition at line 318 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SALU, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), getInstSizeInBytes(), mayReadEXEC(), and shouldReadExec().

◆ isSALU() [2/2]

bool llvm::SIInstrInfo::isSALU ( uint16_t  Opcode) const
inline

Definition at line 322 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SALU.

◆ isScalarStore() [1/2]

static bool llvm::SIInstrInfo::isScalarStore ( const MachineInstr &  MI)
inlinestatic
Returns
true if this is an s_store_dword* instruction. This is more specific than than isSMEM && mayStore.

Definition at line 584 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SCALAR_STORE, and llvm::MCInstrDesc::TSFlags.

◆ isScalarStore() [2/2]

bool llvm::SIInstrInfo::isScalarStore ( uint16_t  Opcode) const
inline

Definition at line 588 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SCALAR_STORE.

◆ isScalarUnit()

static bool llvm::SIInstrInfo::isScalarUnit ( const MachineInstr &  MI)
inlinestatic

Definition at line 562 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SALU, llvm::SIInstrFlags::SMRD, and llvm::MCInstrDesc::TSFlags.

◆ isSchedulingBoundary()

bool SIInstrInfo::isSchedulingBoundary ( const MachineInstr &  MI,
const MachineBasicBlock *  MBB,
const MachineFunction &  MF 
) const
override

Definition at line 2447 of file SIInstrInfo.cpp.

References changesVGPRIndexingMode(), llvm::MachineInstr::getOpcode(), llvm::TargetInstrInfo::isSchedulingBoundary(), and llvm::MachineInstr::modifiesRegister().

Referenced by getMachineCSELookAheadLimit().

◆ isSDWA() [1/2]

static bool llvm::SIInstrInfo::isSDWA ( const MachineInstr &  MI)
inlinestatic

Definition at line 414 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SDWA, and llvm::MCInstrDesc::TSFlags.

Referenced by findSingleRegDef(), isUseSafeToFold(), and verifyInstruction().

◆ isSDWA() [2/2]

bool llvm::SIInstrInfo::isSDWA ( uint16_t  Opcode) const
inline

Definition at line 418 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SDWA.

◆ isSegmentSpecificFLAT()

static bool llvm::SIInstrInfo::isSegmentSpecificFLAT ( const MachineInstr &  MI)
inlinestatic

Definition at line 488 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FLAT, llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::LGKM_CNT, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), and areMemAccessesTriviallyDisjoint().

◆ isSGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isSGPRSpill ( const MachineInstr &  MI)
inlinestatic

Definition at line 530 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SGPRSpill, and llvm::MCInstrDesc::TSFlags.

Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isSGPRSpill() [2/2]

bool llvm::SIInstrInfo::isSGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 534 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SGPRSpill.

◆ isSGPRStackAccess()

unsigned SIInstrInfo::isSGPRStackAccess ( const MachineInstr &  MI,
int &  FrameIndex 
) const

Definition at line 5474 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::getIndex(), getNamedOperand(), llvm::MachineOperand::getReg(), and llvm::MachineOperand::isFI().

Referenced by getMCOpcodeFromPseudo(), isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isSMRD() [1/2]

static bool llvm::SIInstrInfo::isSMRD ( const MachineInstr &  MI)
inlinestatic

Definition at line 446 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SMRD, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet(), areLoadsFromSameBasePtr(), areMemAccessesTriviallyDisjoint(), llvm::GCNHazardRecognizer::getHazardType(), llvm::GCNSubtarget::getMaxNumVGPRs(), getMemOperandWithOffset(), hasUnwantedEffectsWhenEXECEmpty(), isBufferSMRD(), isLowLatencyInstruction(), isSMEMClauseInst(), legalizeOperands(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), shouldClusterMemOps(), shouldReadExec(), and verifyInstruction().

◆ isSMRD() [2/2]

bool llvm::SIInstrInfo::isSMRD ( uint16_t  Opcode) const
inline

Definition at line 450 of file SIInstrInfo.h.

References isBufferSMRD(), and llvm::SIInstrFlags::SMRD.

◆ isSOP1() [1/2]

static bool llvm::SIInstrInfo::isSOP1 ( const MachineInstr &  MI)
inlinestatic

Definition at line 342 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOP1, and llvm::MCInstrDesc::TSFlags.

◆ isSOP1() [2/2]

bool llvm::SIInstrInfo::isSOP1 ( uint16_t  Opcode) const
inline

Definition at line 346 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOP1.

◆ isSOP2() [1/2]

static bool llvm::SIInstrInfo::isSOP2 ( const MachineInstr &  MI)
inlinestatic

Definition at line 350 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOP2, and llvm::MCInstrDesc::TSFlags.

Referenced by verifyInstruction().

◆ isSOP2() [2/2]

bool llvm::SIInstrInfo::isSOP2 ( uint16_t  Opcode) const
inline

Definition at line 354 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOP2.

◆ isSOPC() [1/2]

static bool llvm::SIInstrInfo::isSOPC ( const MachineInstr &  MI)
inlinestatic

Definition at line 358 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOPC, and llvm::MCInstrDesc::TSFlags.

Referenced by verifyInstruction().

◆ isSOPC() [2/2]

bool llvm::SIInstrInfo::isSOPC ( uint16_t  Opcode) const
inline

Definition at line 362 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPC.

◆ isSOPK() [1/2]

static bool llvm::SIInstrInfo::isSOPK ( const MachineInstr &  MI)
inlinestatic

Definition at line 366 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOPK, and llvm::MCInstrDesc::TSFlags.

Referenced by verifyInstruction().

◆ isSOPK() [2/2]

bool llvm::SIInstrInfo::isSOPK ( uint16_t  Opcode) const
inline

Definition at line 370 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPK.

◆ isSOPP() [1/2]

static bool llvm::SIInstrInfo::isSOPP ( const MachineInstr &  MI)
inlinestatic

Definition at line 374 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOPP, and llvm::MCInstrDesc::TSFlags.

Referenced by addRegsToSet().

◆ isSOPP() [2/2]

bool llvm::SIInstrInfo::isSOPP ( uint16_t  Opcode) const
inline

Definition at line 378 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPP.

◆ isStackAccess()

unsigned SIInstrInfo::isStackAccess ( const MachineInstr &  MI,
int &  FrameIndex 
) const

Definition at line 5461 of file SIInstrInfo.cpp.

References assert(), getAddrSpace(), llvm::MachineOperand::getIndex(), getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_empty(), and AMDGPUAS::PRIVATE_ADDRESS.

Referenced by getMCOpcodeFromPseudo(), isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isStoreToStackSlot()

unsigned SIInstrInfo::isStoreToStackSlot ( const MachineInstr &  MI,
int &  FrameIndex 
) const
override

Definition at line 5496 of file SIInstrInfo.cpp.

References isMUBUF(), isSGPRSpill(), isSGPRStackAccess(), isStackAccess(), isVGPRSpill(), and llvm::MachineInstr::mayStore().

Referenced by getMCOpcodeFromPseudo().

◆ isVALU() [1/2]

static bool llvm::SIInstrInfo::isVALU ( const MachineInstr &  MI)
inlinestatic

Definition at line 326 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VALU.

Referenced by addRegsToSet(), llvm::GCNHazardRecognizer::getHazardType(), getInstSizeInBytes(), isOperandLegal(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and shouldReadExec().

◆ isVALU() [2/2]

bool llvm::SIInstrInfo::isVALU ( uint16_t  Opcode) const
inline

Definition at line 330 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VALU.

◆ isVGPRCopy()

bool llvm::SIInstrInfo::isVGPRCopy ( const MachineInstr &  MI) const
inline

Definition at line 628 of file SIInstrInfo.h.

References assert(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), hasUnwantedEffectsWhenEXECEmpty(), llvm::MachineInstr::isCopy(), isInlineConstant(), llvm::SIRegisterInfo::isSGPRReg(), and mayReadEXEC().

Referenced by FoldImmediate().

◆ isVGPRSpill() [1/2]

static bool llvm::SIInstrInfo::isVGPRSpill ( const MachineInstr &  MI)
inlinestatic

Definition at line 522 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VGPRSpill.

Referenced by isLoadFromStackSlot(), and isStoreToStackSlot().

◆ isVGPRSpill() [2/2]

bool llvm::SIInstrInfo::isVGPRSpill ( uint16_t  Opcode) const
inline

Definition at line 526 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VGPRSpill.

◆ isVINTRP() [1/2]

static bool llvm::SIInstrInfo::isVINTRP ( const MachineInstr &  MI)
inlinestatic

Definition at line 554 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VINTRP.

Referenced by llvm::GCNHazardRecognizer::getHazardType(), and llvm::GCNHazardRecognizer::PreEmitNoopsCommon().

◆ isVINTRP() [2/2]

bool llvm::SIInstrInfo::isVINTRP ( uint16_t  Opcode) const
inline

Definition at line 558 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VINTRP.

◆ isVMEM() [1/2]

static bool llvm::SIInstrInfo::isVMEM ( const MachineInstr &  MI)
inlinestatic

Definition at line 334 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), and isMUBUF().

Referenced by addRegsToSet(), llvm::GCNHazardRecognizer::getHazardType(), llvm::GCNSubtarget::getMaxNumVGPRs(), isVMEMClauseInst(), llvm::GCNHazardRecognizer::PreEmitNoopsCommon(), and readsVCCZ().

◆ isVMEM() [2/2]

bool llvm::SIInstrInfo::isVMEM ( uint16_t  Opcode) const
inline

Definition at line 338 of file SIInstrInfo.h.

References isMIMG(), isMTBUF(), and isMUBUF().

◆ isVOP1() [1/2]

static bool llvm::SIInstrInfo::isVOP1 ( const MachineInstr &  MI)
inlinestatic

Definition at line 390 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOP1.

Referenced by foldImmediates(), isIdentityValue(), and verifyInstruction().

◆ isVOP1() [2/2]

bool llvm::SIInstrInfo::isVOP1 ( uint16_t  Opcode) const
inline

Definition at line 394 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP1.

◆ isVOP2() [1/2]

static bool llvm::SIInstrInfo::isVOP2 ( const MachineInstr &  MI)
inlinestatic

Definition at line 398 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOP2.

Referenced by foldImmediates(), isIdentityValue(), legalizeOperands(), and verifyInstruction().

◆ isVOP2() [2/2]

bool llvm::SIInstrInfo::isVOP2 ( uint16_t  Opcode) const
inline

Definition at line 402 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP2.

◆ isVOP3() [1/2]

static bool llvm::SIInstrInfo::isVOP3 ( const MachineInstr &  MI)
inlinestatic

Definition at line 406 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOP3.

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), getInstSizeInBytes(), isIdentityValue(), isImmOperandLegal(), isOperandLegal(), legalizeOperands(), and verifyInstruction().

◆ isVOP3() [2/2]

bool llvm::SIInstrInfo::isVOP3 ( uint16_t  Opcode) const
inline

Definition at line 410 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP3.

◆ isVOP3P() [1/2]

static bool llvm::SIInstrInfo::isVOP3P ( const MachineInstr &  MI)
inlinestatic

Definition at line 546 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOP3P.

◆ isVOP3P() [2/2]

bool llvm::SIInstrInfo::isVOP3P ( uint16_t  Opcode) const
inline

Definition at line 550 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOP3P.

◆ isVOPC() [1/2]

static bool llvm::SIInstrInfo::isVOPC ( const MachineInstr &  MI)
inlinestatic

Definition at line 422 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VOPC.

Referenced by findSingleRegDef(), foldImmediates(), legalizeOperands(), and verifyInstruction().

◆ isVOPC() [2/2]

bool llvm::SIInstrInfo::isVOPC ( uint16_t  Opcode) const
inline

Definition at line 426 of file SIInstrInfo.h.

References llvm::SIInstrFlags::VOPC.

◆ isWQM() [1/2]

static bool llvm::SIInstrInfo::isWQM ( const MachineInstr &  MI)
inlinestatic

Definition at line 506 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::WQM.

◆ isWQM() [2/2]

bool llvm::SIInstrInfo::isWQM ( uint16_t  Opcode) const
inline

Definition at line 510 of file SIInstrInfo.h.

References llvm::SIInstrFlags::WQM.

◆ legalizeGenericOperand()

void SIInstrInfo::legalizeGenericOperand ( MachineBasicBlock &  InsertMBB,
MachineBasicBlock::iterator  I,
const TargetRegisterClass *  DstRC,
MachineOperand &  Op,
MachineRegisterInfo &  MRI,
const DebugLoc &  DL 
) const

Definition at line 3888 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::tgtok::Def, FoldImmediate(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineRegisterInfo::getVRegDef(), llvm::MachineInstr::isMoveImmediate(), llvm::MachineOperand::setReg(), and llvm::MachineOperand::setSubReg().

Referenced by getOpSize(), legalizeOperands(), and moveToVALU().

◆ legalizeOperands()

void SIInstrInfo::legalizeOperands ( MachineInstr &  MI,
MachineDominatorTree *  MDT = nullptr 
) const

Legalize all operands in this instruction.

This function may create new instructions and control-flow around MI. If present, MDT is updated.

Definition at line 4103 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), assert(), llvm::BuildMI(), llvm::MachineInstrBuilder::cloneMemRefs(), llvm::MachineRegisterInfo::createVirtualRegister(), E, extractRsrcPtr(), llvm::AMDGPU::getAddr64Inst(), llvm::Function::getCallingConv(), llvm::MachineInstr::getDebugLoc(), llvm::MachineBasicBlock::getFirstTerminator(), llvm::MachineFunction::getFunction(), llvm::AMDGPU::getIfAddr64Inst(), llvm::MachineOperand::getMBB(), getNamedImmOperand(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::MachineFunction::getSubtarget(), I, isMIMG(), isMTBUF(), isMUBUF(), llvm::MachineOperand::isReg(), llvm::AMDGPU::isShader(), isSMRD(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP2(), isVOP3(), isVOPC(), legalizeGenericOperand(), legalizeOperandsSMRD(), legalizeOperandsVOP2(), legalizeOperandsVOP3(), loadSRsrcFromVGPR(), MI, MRI, readlaneVGPRToSGPR(), llvm::MachineInstr::removeFromParent(), llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), and llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS.

Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter(), getOpSize(), and moveToVALU().

◆ legalizeOperandsSMRD()

void SIInstrInfo::legalizeOperandsSMRD ( MachineRegisterInfo &  MRI,
MachineInstr &  MI 
) const

Definition at line 3869 of file SIInstrInfo.cpp.

References getNamedOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), MI, MRI, readlaneVGPRToSGPR(), and llvm::MachineOperand::setReg().

Referenced by getOpSize(), and legalizeOperands().

◆ legalizeOperandsVOP2()

void SIInstrInfo::legalizeOperandsVOP2 ( MachineRegisterInfo &  MRI,
MachineInstr &  MI 
) const

Legalize operands in MI by either commuting it or inserting a copy of src1.

Definition at line 3665 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), commuteOpcode(), llvm::MachineRegisterInfo::createVirtualRegister(), findImplicitSGPRRead(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isCommutable(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isKill(), isLegalRegOperand(), isLiteralConstantLike(), llvm::MachineOperand::isReg(), legalizeOpWithMove(), llvm_unreachable, MI, llvm::MCInstrDesc::OpInfo, Reg, llvm::MachineInstr::setDesc(), and llvm::MachineOperand::setSubReg().

Referenced by getOpSize(), and legalizeOperands().

◆ legalizeOperandsVOP3()

void SIInstrInfo::legalizeOperandsVOP3 ( MachineRegisterInfo &  MRI,
MachineInstr &  MI 
) const

Fix operands in MI to satisfy constant bus requirements.

Definition at line 3775 of file SIInstrInfo.cpp.

References llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::count(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::detail::DenseSetImpl< ValueT, SmallDenseMap< ValueT, detail::DenseSetEmpty, InlineBuckets, ValueInfoT, detail::DenseSetPair< ValueT > >, ValueInfoT >::insert(), isLiteralConstantLike(), llvm::MachineOperand::isReg(), and legalizeOpWithMove().

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection(), getOpSize(), and legalizeOperands().

◆ legalizeOpWithMove()

void SIInstrInfo::legalizeOpWithMove ( MachineInstr &  MI,
unsigned  OpIdx 
) const

Legalize the OpIndex operand of this instruction by inserting a MOV.

For example: ADD_I32_e32 VGPR0, 15 to MOV VGPR1, 15 ADD_I32_e32 VGPR0, VGPR1

If the operand being legalized is a register, then a COPY will be used instead of MOV.

Definition at line 3474 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::BuildMI(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineBasicBlock::findDebugLoc(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineFunction::getRegInfo(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), I, llvm::MachineOperand::isReg(), MI, MRI, Reg, Size, and TRI.

Referenced by getOpSize(), legalizeOperandsVOP2(), and legalizeOperandsVOP3().

◆ loadRegFromStackSlot()

void SIInstrInfo::loadRegFromStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
unsigned  DestReg,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI 
) const
override

Definition at line 1000 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::RegState::Dead, llvm::MachineBasicBlock::findDebugLoc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), getSGPRSpillRestoreOpcode(), llvm::TargetRegisterInfo::getSpillSize(), getVGPRSpillRestoreOpcode(), llvm::GCNSubtarget::hasScalarStores(), llvm::SIRegisterInfo::hasVGPRs(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isSGPRClass(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineMemOperand::MOLoad, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::SIStackID::SGPR_SPILL, and Size.

Referenced by getRegisterInfo().

◆ materializeImmediate()

void SIInstrInfo::materializeImmediate ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
const DebugLoc &  DL,
unsigned  DestReg,
int64_t  Value 
) const

Definition at line 633 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::BuildMI(), llvm::MachineBasicBlock::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), llvm::SIRegisterInfo::getRegSplitParts(), llvm::SIRegisterInfo::isSGPRClass(), MRI, and llvm::ArrayRef< T >::size().

Referenced by containsNewBackedge(), convertNonUniformLoopRegion(), getRegisterInfo(), and removeExternalCFGEdges().

◆ mayAccessFlatAddressSpace()

bool SIInstrInfo::mayAccessFlatAddressSpace ( const MachineInstr &  MI) const

Definition at line 5589 of file SIInstrInfo.cpp.

References AMDGPUAS::FLAT_ADDRESS, isFLAT(), llvm::MachineInstr::memoperands(), and llvm::MachineInstr::memoperands_empty().

Referenced by getMCOpcodeFromPseudo().

◆ mayReadEXEC()

bool SIInstrInfo::mayReadEXEC ( const MachineRegisterInfo &  MRI,
const MachineInstr &  MI 
) const

Returns true if the instruction could potentially depend on the value of exec.

If false, exec dependencies may safely be ignored.

Definition at line 2503 of file SIInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::isCall(), llvm::MachineInstr::isCopyLike(), llvm::MachineInstr::isMetaInstruction(), isSALU(), llvm::SIRegisterInfo::isSGPRReg(), llvm::isTargetSpecificOpcode(), and llvm::MachineInstr::readsRegister().

Referenced by isVGPRCopy().

◆ moveToVALU()

void SIInstrInfo::moveToVALU ( MachineInstr &  MI,
MachineDominatorTree *  MDT = nullptr 
) const

Replace this instruction's opcode with the equivalent VALU opcode.

This function will also move the users of MI to the VALU if necessary. If present, MDT is updated.

Definition at line 4386 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstr::addImplicitDefUseOperands(), llvm::MachineInstr::addOperand(), llvm::MachineInstrBuilder::addReg(), assert(), buildExtractSubRegOrImm(), llvm::BuildMI(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::MachineOperand::CreateImm(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::RegState::Dead, llvm::RegState::Define, E, llvm::SetVector< T, Vector, Set >::empty(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::eraseFromParent(), findImplicitSGPRRead(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), getVALUOp(), I, llvm::SetVector< T, Vector, Set >::insert(), llvm::MachineInstr::isCopy(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isImm(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::RegState::Kill, legalizeGenericOperand(), legalizeOperands(), llvm_unreachable, llvm::make_range(), MI, MRI, llvm::MCInstrDesc::OpInfo, llvm::SetVector< T, Vector, Set >::pop_back_val(), Reg, llvm::MCOperandInfo::RegClass, llvm::MachineInstr::RemoveOperand(), llvm::MachineRegisterInfo::replaceRegWith(), llvm::MachineInstr::setDesc(), llvm::MachineOperand::setReg(), Size, llvm::MachineRegisterInfo::use_begin(), llvm::MachineRegisterInfo::use_end(), UseMI, llvm::AMDGPUSubtarget::VOLCANIC_ISLANDS, and llvm::SIInstrFlags::WQM.

Referenced by getOpSize(), and hoistAndMergeSGPRInits().

◆ pseudoToMCOpcode()

int SIInstrInfo::pseudoToMCOpcode ( int  Opcode) const

Return a target-specific opcode if Opcode is a pseudo instruction.

Return -1 if the target-specific opcode for the pseudo instruction does not exist. If Opcode is not a pseudo instruction, this is identity.

Definition at line 5806 of file SIInstrInfo.cpp.

References llvm::SIInstrFlags::D16Buf, llvm::AMDGPU::getMCOpcode(), llvm::AMDGPUSubtarget::GFX10, GFX80, llvm::AMDGPUSubtarget::GFX9, GFX9, llvm::SIInstrFlags::renamedInGFX9, llvm::SIInstrFlags::SDWA, SDWA, SDWA10, SDWA9, and subtargetEncodingFamily().

Referenced by commuteOpcode(), convertToThreeAddress(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), findSingleRegDef(), FoldImmediate(), getMCOpcodeFromPseudo(), getPermuteMask(), hasVALU32BitEncoding(), and isLegalMUBUFImmOffset().

◆ readlaneVGPRToSGPR()

unsigned SIInstrInfo::readlaneVGPRToSGPR ( unsigned  SrcReg,
MachineInstr &  UseMI,
MachineRegisterInfo &  MRI 
) const

Copy a value from a VGPR (SrcReg) to SGPR.

This function can only be used when it is know that the value in SrcReg is same across all threads in the wave.

Returns
The SGPR register that SrcReg was copied to.

Definition at line 3836 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getParent(), llvm::MachineRegisterInfo::getRegClass(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and UseMI.

Referenced by getOpSize(), legalizeOperands(), and legalizeOperandsSMRD().

◆ removeBranch()

unsigned SIInstrInfo::removeBranch ( MachineBasicBlock &  MBB,
int *  BytesRemoved = nullptr 
) const
override

Definition at line 1749 of file SIInstrInfo.cpp.

References llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::getFirstTerminator(), getInstSizeInBytes(), and I.

Referenced by commuteOpcode(), and isFunctionEntryBlock().

◆ reverseBranchCondition()

bool SIInstrInfo::reverseBranchCondition ( SmallVectorImpl< MachineOperand > &  Cond) const
override

Definition at line 1839 of file SIInstrInfo.cpp.

References llvm::SmallVectorBase::size().

Referenced by commuteOpcode().

◆ shouldClusterMemOps()

bool SIInstrInfo::shouldClusterMemOps ( const MachineOperand &  BaseOp1,
const MachineOperand &  BaseOp2,
unsigned  NumLoads 
) const
override

Definition at line 412 of file SIInstrInfo.cpp.

References getNamedOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getParent(), llvm::MachineInstr::getParent(), llvm::SIRegisterInfo::getPhysRegClass(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineFunction::getRegInfo(), isDS(), isFLAT(), isMTBUF(), isMUBUF(), isSMRD(), llvm::TargetRegisterInfo::isVirtualRegister(), memOpsHaveSameBasePtr(), MRI, and Reg.

Referenced by getRegisterInfo().

◆ shouldScheduleLoadsNear()

bool SIInstrInfo::shouldScheduleLoadsNear ( SDNode *  Load0,
SDNode *  Load1,
int64_t  Offset0,
int64_t  Offset1,
unsigned  NumLoads 
) const
override

Definition at line 480 of file SIInstrInfo.cpp.

References assert().

Referenced by getRegisterInfo().

◆ sopkIsZext() [1/2]

static bool llvm::SIInstrInfo::sopkIsZext ( const MachineInstr &  MI)
inlinestatic

Definition at line 574 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::SOPK_ZEXT, and llvm::MCInstrDesc::TSFlags.

Referenced by shrinkScalarCompare(), and verifyInstruction().

◆ sopkIsZext() [2/2]

bool llvm::SIInstrInfo::sopkIsZext ( uint16_t  Opcode) const
inline

Definition at line 578 of file SIInstrInfo.h.

References llvm::SIInstrFlags::SOPK_ZEXT.

◆ storeRegToStackSlot()

void SIInstrInfo::storeRegToStackSlot ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  MI,
unsigned  SrcReg,
bool  isKill,
int  FrameIndex,
const TargetRegisterClass *  RC,
const TargetRegisterInfo *  TRI 
) const
override

Definition at line 892 of file SIInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::RegState::Dead, llvm::MachineBasicBlock::findDebugLoc(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::SIMachineFunctionInfo::getFrameOffsetReg(), llvm::MachineFunction::getInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineFunction::getRegInfo(), llvm::SIMachineFunctionInfo::getScratchRSrcReg(), getSGPRSpillSaveOpcode(), llvm::TargetRegisterInfo::getSpillSize(), getVGPRSpillSaveOpcode(), llvm::GCNSubtarget::hasScalarStores(), llvm::SIRegisterInfo::hasVGPRs(), llvm::RegState::Implicit, llvm::RegState::ImplicitDefine, llvm::SIRegisterInfo::isSGPRClass(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::MachineMemOperand::MOStore, MRI, llvm::SIMachineFunctionInfo::setHasSpilledSGPRs(), llvm::SIMachineFunctionInfo::setHasSpilledVGPRs(), llvm::SIStackID::SGPR_SPILL, and Size.

Referenced by getRegisterInfo().

◆ swapSourceModifiers()

bool SIInstrInfo::swapSourceModifiers ( MachineInstr &  MI,
MachineOperand &  Src0,
unsigned  Src0OpName,
MachineOperand &  Src1,
unsigned  Src1OpName 
) const
protected

Definition at line 1362 of file SIInstrInfo.cpp.

References assert(), llvm::MachineOperand::getImm(), getNamedOperand(), and llvm::MachineOperand::setImm().

Referenced by commuteInstructionImpl().

◆ usesConstantBus()

bool SIInstrInfo::usesConstantBus ( const MachineRegisterInfo &  MRI,
const MachineOperand &  MO,
const MCOperandInfo &  OpInfo 
) const

Returns true if this operand uses the constant bus.

Definition at line 2804 of file SIInstrInfo.cpp.

References contains(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getRegClass(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), isInlineConstant(), llvm::MachineOperand::isReg(), llvm::SIRegisterInfo::isSGPRClass(), llvm::MachineOperand::isUse(), and llvm::TargetRegisterInfo::isVirtualRegister().

Referenced by isLiteralConstant(), isOperandLegal(), and verifyInstruction().

◆ usesFPDPRounding() [1/2]

static bool llvm::SIInstrInfo::usesFPDPRounding ( const MachineInstr &  MI)
inlinestatic

Definition at line 620 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPDPRounding, llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::createSIModeRegisterPass().

◆ usesFPDPRounding() [2/2]

bool llvm::SIInstrInfo::usesFPDPRounding ( uint16_t  Opcode) const
inline

Definition at line 624 of file SIInstrInfo.h.

References llvm::SIInstrFlags::FPDPRounding.

◆ usesLGKM_CNT()

static bool llvm::SIInstrInfo::usesLGKM_CNT ( const MachineInstr &  MI)
inlinestatic

Definition at line 570 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::SIInstrFlags::LGKM_CNT, and llvm::MCInstrDesc::TSFlags.

◆ usesVM_CNT()

static bool llvm::SIInstrInfo::usesVM_CNT ( const MachineInstr &  MI)
inlinestatic

Definition at line 566 of file SIInstrInfo.h.

References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::TSFlags, and llvm::SIInstrFlags::VM_CNT.

◆ verifyInstruction()

bool SIInstrInfo::verifyInstruction ( const MachineInstr &  MI,
StringRef &  ErrInfo 
) const
override

Definition at line 2892 of file SIInstrInfo.cpp.

References llvm::all_of(), llvm::AMDGPU::MIMGInfo::BaseOpcode, compareMachineOp(), llvm::TargetRegisterClass::contains(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates, llvm::countPopulation(), DC, llvm::SIInstrFlags::DPP, llvm::AMDGPU::DPP::DPP_LAST, llvm::AMDGPU::DPP::DPP_UNUSED1, llvm::AMDGPU::DPP::DPP_UNUSED2, llvm::AMDGPU::DPP::DPP_UNUSED3, llvm::AMDGPU::DPP::DPP_UNUSED4_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED4_LAST, llvm::AMDGPU::DPP::DPP_UNUSED5_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED5_LAST, llvm::AMDGPU::DPP::DPP_UNUSED6_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED6_LAST, llvm::AMDGPU::DPP::DPP_UNUSED7_FIRST, llvm::AMDGPU::DPP::DPP_UNUSED7_LAST, E, findImplicitSGPRRead(), llvm::MachineInstr::findTiedOperandIdx(), llvm::AMDGPU::getBasicFromSDWAOp(), llvm::GCNSubtarget::getConstantBusLimit(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::AMDGPU::getMIMGBaseOpcodeInfo(), llvm::AMDGPU::getMIMGDimInfoByEncoding(), llvm::AMDGPU::getMIMGInfo(), getNamedOperand(), llvm::AMDGPU::getNamedOperandIdx(), llvm::MachineInstr::getNumExplicitOperands(), llvm::MCInstrDesc::getNumImplicitUses(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), getOpRegClass(), llvm::MachineBasicBlock::getParent(), llvm::MachineInstr::getParent(), llvm::MachineOperand::getReg(), llvm::MachineInstr::getRegClassConstraint(), llvm::SIRegisterInfo::getRegClassForReg(), llvm::MachineFunction::getRegInfo(), llvm::TargetRegisterInfo::getRegSizeInBits(), llvm::MachineFunction::getSubtarget(), llvm::MachineRegisterInfo::getTargetRegisterInfo(), llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::MachineInstr::hasRegisterImplicitUseOperand(), llvm::AMDGPUSubtarget::hasSDWA(), llvm::GCNSubtarget::hasSDWAOmod(), llvm::GCNSubtarget::hasSDWAOutModsVOPC(), llvm::GCNSubtarget::hasSDWAScalar(), llvm::GCNSubtarget::hasSDWASdst(), llvm::GCNSubtarget::hasUnpackedD16VMem(), llvm::SIRegisterInfo::hasVGPRs(), llvm::GCNSubtarget::hasVOP3Literal(), I, Info, llvm::MCInstrDesc::isBranch(), llvm::MachineOperand::isFI(), isFLAT(), llvm::MachineOperand::isFPImm(), isGather4(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), llvm::MachineInstr::isInlineAsm(), isInlineConstant(), llvm::isInt< 16 >(), isMIMG(), llvm::TargetRegisterInfo::isPhysicalRegister(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isRegTiedToUseOperand(), isSDWA(), isSMRD(), isSOP2(), isSOPC(), isSOPK(), isSubRegOf(), llvm::MachineOperand::isTied(), llvm::isUInt< 16 >(), llvm::MachineOperand::isUse(), llvm::MCInstrDesc::isVariadic(), llvm::TargetRegisterInfo::isVirtualRegister(), isVOP1(), isVOP2(), isVOP3(), isVOPC(), LLVM_FALLTHROUGH, llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip, llvm::MachineInstr::mayStore(), llvm::InlineAsm::MIOp_FirstOperand, MRI, llvm::AMDGPU::MIMGDimInfo::NumCoords, llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs, llvm::AMDGPU::MIMGDimInfo::NumGradients, llvm::MCOI::OPERAND_IMMEDIATE, llvm::AMDGPU::OPERAND_KIMM32, llvm::AMDGPU::OPERAND_REG_IMM_FP32, llvm::AMDGPU::OPERAND_REG_IMM_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP16, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP32, llvm::AMDGPU::OPERAND_REG_INLINE_C_FP64, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT16, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT32, llvm::AMDGPU::OPERAND_REG_INLINE_C_INT64, llvm::MCOI::OPERAND_REGISTER, llvm::MCOperandInfo::OperandType, llvm::MCInstrDesc::OpInfo, llvm::SmallVectorTemplateBase< T, bool >::push_back(), Reg, llvm::MCOperandInfo::RegClass, shouldReadExec(), sopkIsZext(), llvm::AMDGPU::SDWA::UNUSED_PRESERVE, and usesConstantBus().

Referenced by isLiteralConstant().

The documentation for this class was generated from the following files:
Generated on Sun May 26 2019 00:50:15 for LLVM by   doxygen 1.8.13