34 cl::desc(
"Use TargetSchedModel for latency lookup"));
37 cl::desc(
"Use InstrItineraryData for latency lookup"));
41 cl::desc(
"Force the use of resource intervals in the schedule model"));
58 ResourceFactors.
resize(NumRes);
60 for (
unsigned Idx = 0;
Idx < NumRes; ++
Idx) {
63 ResourceLCM = std::lcm(ResourceLCM, NumUnits);
65 MicroOpFactor = ResourceLCM / SchedModel.
IssueWidth;
66 for (
unsigned Idx = 0;
Idx < NumRes; ++
Idx) {
68 ResourceFactors[
Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
79 return SC->BeginGroup;
105 return SC->NumMicroOps;
107 return MI->isTransient() ? 0 : 1;
115 return Cycles >= 0 ? Cycles : 1000;
123 unsigned SchedClass =
MI->getDesc().getSchedClass();
132 assert(++NIter < 6 &&
"Variants are nested deeper than the magic number");
147 for (
unsigned i = 0; i != DefOperIdx; ++i) {
163 for (
unsigned i = 0; i != UseOperIdx; ++i) {
189 if (OperLatency >= 0)
207 if (DefIdx < SCDesc->NumWriteLatencyEntries) {
222 if (Advance > 0 && (
unsigned)Advance >
Latency)
232 errs() <<
"DefIdx " << DefIdx <<
" exceeds machine model writes for "
233 << *
DefMI <<
" (Try with MCSchedModel.CompleteModel set to false)";
244TargetSchedModel::computeInstrLatency(
const MCSchedClassDesc &SCDesc)
const {
248unsigned TargetSchedModel::computeInstrLatency(
unsigned Opcode)
const {
254unsigned TargetSchedModel::computeInstrLatency(
const MCInst &Inst)
const {
257 return computeInstrLatency(Inst.
getOpcode());
262 bool UseDefaultDefLatency)
const {
272 return computeInstrLatency(*SCDesc);
295 return computeInstrLatency(
DefMI);
315 unsigned SchedClass =
MI->getDesc().getSchedClass();
MachineInstrBuilder & UseMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx)
Find the use index of this operand.
static unsigned capLatency(int Cycles)
static cl::opt< bool > EnableSchedModel("schedmodel", cl::Hidden, cl::init(true), cl::desc("Use TargetSchedModel for latency lookup"))
static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx)
Find the def index of this operand.
static cl::opt< bool > ForceEnableIntervals("sched-model-force-enable-intervals", cl::Hidden, cl::init(false), cl::desc("Force the use of resource intervals in the schedule model"))
static cl::opt< bool > EnableSchedItins("scheditins", cl::Hidden, cl::init(true), cl::desc("Use InstrItineraryData for latency lookup"))
int getNumMicroOps(unsigned ItinClassIndx) const
Return the number of micro-ops that the given class decodes to.
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
bool isEmpty() const
Returns true if there are no itineraries.
Instances of this class represent a single low-level machine instruction.
unsigned getOpcode() const
unsigned getSchedClass() const
Return the scheduling class for this instruction.
ArrayRef< MCOperandInfo > operands() const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Representation of each machine instruction.
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
const MachineOperand & getOperand(unsigned i) const
MachineOperand class - Representation of each machine instruction operand.
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Register getReg() const
getReg - Returns the register number.
Wrapper class representing virtual and physical registers.
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
bool mustEndGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if current group must end.
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model.
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
bool mustBeginGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if new group must begin.
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
double computeReciprocalThroughput(const MachineInstr *MI) const
Compute the reciprocal throughput of the given instruction.
unsigned getNumMicroOps(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return the number of issue slots required for this MI.
const InstrItineraryData * getInstrItineraries() const
bool enableIntervals() const
bool hasInstrItineraries() const
Return true if this machine model includes cycle-to-cycle itinerary data.
TargetSubtargetInfo - Generic base class for all target subtargets.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Summarize the scheduling resources required for an instruction of a particular scheduling class.
uint16_t NumReadAdvanceEntries
bool isOutOfOrder() const
Return true if machine supports out of order execution.
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
unsigned getNumProcResourceKinds() const
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
Specify the latency in cpu cycles for a particular scheduling class and def index.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...