LLVM  15.0.0git
TargetSchedule.cpp
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1 //===- llvm/Target/TargetSchedule.cpp - Sched Machine Model ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements a wrapper around MCSchedModel that allows the interface
10 // to benefit from information currently only available in TargetInstrInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
20 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCSchedule.h"
26 #include <algorithm>
27 #include <cassert>
28 #include <cstdint>
29 
30 using namespace llvm;
31 
32 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
33  cl::desc("Use TargetSchedModel for latency lookup"));
34 
35 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
36  cl::desc("Use InstrItineraryData for latency lookup"));
37 
39  return EnableSchedModel && SchedModel.hasInstrSchedModel();
40 }
41 
43  return EnableSchedItins && !InstrItins.isEmpty();
44 }
45 
46 static unsigned gcd(unsigned Dividend, unsigned Divisor) {
47  // Dividend and Divisor will be naturally swapped as needed.
48  while (Divisor) {
49  unsigned Rem = Dividend % Divisor;
50  Dividend = Divisor;
51  Divisor = Rem;
52  };
53  return Dividend;
54 }
55 
56 static unsigned lcm(unsigned A, unsigned B) {
57  unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
58  assert((LCM >= A && LCM >= B) && "LCM overflow");
59  return LCM;
60 }
61 
63  STI = TSInfo;
64  SchedModel = TSInfo->getSchedModel();
65  TII = TSInfo->getInstrInfo();
66  STI->initInstrItins(InstrItins);
67 
68  unsigned NumRes = SchedModel.getNumProcResourceKinds();
69  ResourceFactors.resize(NumRes);
70  ResourceLCM = SchedModel.IssueWidth;
71  for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
72  unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
73  if (NumUnits > 0)
74  ResourceLCM = lcm(ResourceLCM, NumUnits);
75  }
76  MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
77  for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
78  unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
79  ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
80  }
81 }
82 
83 /// Returns true only if instruction is specified as single issue.
85  const MCSchedClassDesc *SC) const {
86  if (hasInstrSchedModel()) {
87  if (!SC)
89  if (SC->isValid())
90  return SC->BeginGroup;
91  }
92  return false;
93 }
94 
96  const MCSchedClassDesc *SC) const {
97  if (hasInstrSchedModel()) {
98  if (!SC)
100  if (SC->isValid())
101  return SC->EndGroup;
102  }
103  return false;
104 }
105 
107  const MCSchedClassDesc *SC) const {
108  if (hasInstrItineraries()) {
109  int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
110  return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
111  }
112  if (hasInstrSchedModel()) {
113  if (!SC)
115  if (SC->isValid())
116  return SC->NumMicroOps;
117  }
118  return MI->isTransient() ? 0 : 1;
119 }
120 
121 // The machine model may explicitly specify an invalid latency, which
122 // effectively means infinite latency. Since users of the TargetSchedule API
123 // don't know how to handle this, we convert it to a very large latency that is
124 // easy to distinguish when debugging the DAG but won't induce overflow.
125 static unsigned capLatency(int Cycles) {
126  return Cycles >= 0 ? Cycles : 1000;
127 }
128 
129 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
130 /// evaluation of predicates that depend on instruction operands or flags.
133  // Get the definition's scheduling class descriptor from this machine model.
134  unsigned SchedClass = MI->getDesc().getSchedClass();
135  const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
136  if (!SCDesc->isValid())
137  return SCDesc;
138 
139 #ifndef NDEBUG
140  unsigned NIter = 0;
141 #endif
142  while (SCDesc->isVariant()) {
143  assert(++NIter < 6 && "Variants are nested deeper than the magic number");
144 
145  SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
146  SCDesc = SchedModel.getSchedClassDesc(SchedClass);
147  }
148  return SCDesc;
149 }
150 
151 /// Find the def index of this operand. This index maps to the machine model and
152 /// is independent of use operands. Def operands may be reordered with uses or
153 /// merged with uses without affecting the def index (e.g. before/after
154 /// regalloc). However, an instruction's def operands must never be reordered
155 /// with respect to each other.
156 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
157  unsigned DefIdx = 0;
158  for (unsigned i = 0; i != DefOperIdx; ++i) {
159  const MachineOperand &MO = MI->getOperand(i);
160  if (MO.isReg() && MO.isDef())
161  ++DefIdx;
162  }
163  return DefIdx;
164 }
165 
166 /// Find the use index of this operand. This is independent of the instruction's
167 /// def operands.
168 ///
169 /// Note that uses are not determined by the operand's isUse property, which
170 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
171 /// a "use". The machine model allows an operand to be both a Def and Use.
172 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
173  unsigned UseIdx = 0;
174  for (unsigned i = 0; i != UseOperIdx; ++i) {
175  const MachineOperand &MO = MI->getOperand(i);
176  if (MO.isReg() && MO.readsReg() && !MO.isDef())
177  ++UseIdx;
178  }
179  return UseIdx;
180 }
181 
182 // Top-level API for clients that know the operand indices.
184  const MachineInstr *DefMI, unsigned DefOperIdx,
185  const MachineInstr *UseMI, unsigned UseOperIdx) const {
186 
188  return TII->defaultDefLatency(SchedModel, *DefMI);
189 
190  if (hasInstrItineraries()) {
191  int OperLatency = 0;
192  if (UseMI) {
193  OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
194  *UseMI, UseOperIdx);
195  }
196  else {
197  unsigned DefClass = DefMI->getDesc().getSchedClass();
198  OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
199  }
200  if (OperLatency >= 0)
201  return OperLatency;
202 
203  // No operand latency was found.
204  unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
205 
206  // Expected latency is the max of the stage latency and itinerary props.
207  // Rather than directly querying InstrItins stage latency, we call a TII
208  // hook to allow subtargets to specialize latency. This hook is only
209  // applicable to the InstrItins model. InstrSchedModel should model all
210  // special cases without TII hooks.
211  InstrLatency =
212  std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
213  return InstrLatency;
214  }
215  // hasInstrSchedModel()
216  const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
217  unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
218  if (DefIdx < SCDesc->NumWriteLatencyEntries) {
219  // Lookup the definition's write latency in SubtargetInfo.
220  const MCWriteLatencyEntry *WLEntry =
221  STI->getWriteLatencyEntry(SCDesc, DefIdx);
222  unsigned WriteID = WLEntry->WriteResourceID;
223  unsigned Latency = capLatency(WLEntry->Cycles);
224  if (!UseMI)
225  return Latency;
226 
227  // Lookup the use's latency adjustment in SubtargetInfo.
228  const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
229  if (UseDesc->NumReadAdvanceEntries == 0)
230  return Latency;
231  unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
232  int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
233  if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
234  return 0;
235  return Latency - Advance;
236  }
237  // If DefIdx does not exist in the model (e.g. implicit defs), then return
238  // unit latency (defaultDefLatency may be too conservative).
239 #ifndef NDEBUG
240  if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
241  && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
242  && SchedModel.isComplete()) {
243  errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
244  << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
245  llvm_unreachable("incomplete machine model");
246  }
247 #endif
248  // FIXME: Automatically giving all implicit defs defaultDefLatency is
249  // undesirable. We should only do it for defs that are known to the MC
250  // desc like flags. Truly implicit defs should get 1 cycle latency.
251  return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
252 }
253 
254 unsigned
255 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
256  return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc));
257 }
258 
259 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
260  assert(hasInstrSchedModel() && "Only call this function with a SchedModel");
261  unsigned SCIdx = TII->get(Opcode).getSchedClass();
262  return capLatency(SchedModel.computeInstrLatency(*STI, SCIdx));
263 }
264 
265 unsigned TargetSchedModel::computeInstrLatency(const MCInst &Inst) const {
266  if (hasInstrSchedModel())
267  return capLatency(SchedModel.computeInstrLatency(*STI, *TII, Inst));
268  return computeInstrLatency(Inst.getOpcode());
269 }
270 
271 unsigned
272 TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
273  bool UseDefaultDefLatency) const {
274  // For the itinerary model, fall back to the old subtarget hook.
275  // Allow subtargets to compute Bundle latencies outside the machine model.
276  if (hasInstrItineraries() || MI->isBundle() ||
277  (!hasInstrSchedModel() && !UseDefaultDefLatency))
278  return TII->getInstrLatency(&InstrItins, *MI);
279 
280  if (hasInstrSchedModel()) {
281  const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
282  if (SCDesc->isValid())
283  return computeInstrLatency(*SCDesc);
284  }
285  return TII->defaultDefLatency(SchedModel, *MI);
286 }
287 
288 unsigned TargetSchedModel::
289 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
290  const MachineInstr *DepMI) const {
291  if (!SchedModel.isOutOfOrder())
292  return 1;
293 
294  // Out-of-order processor can dispatch WAW dependencies in the same cycle.
295 
296  // Treat predication as a data dependency for out-of-order cpus. In-order
297  // cpus do not need to treat predicated writes specially.
298  //
299  // TODO: The following hack exists because predication passes do not
300  // correctly append imp-use operands, and readsReg() strangely returns false
301  // for predicated defs.
302  Register Reg = DefMI->getOperand(DefOperIdx).getReg();
303  const MachineFunction &MF = *DefMI->getMF();
305  if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
306  return computeInstrLatency(DefMI);
307 
308  // If we have a per operand scheduling model, check if this def is writing
309  // an unbuffered resource. If so, it treated like an in-order cpu.
310  if (hasInstrSchedModel()) {
311  const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
312  if (SCDesc->isValid()) {
313  for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
314  *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
315  if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
316  return 1;
317  }
318  }
319  }
320  return 0;
321 }
322 
323 double
325  if (hasInstrItineraries()) {
326  unsigned SchedClass = MI->getDesc().getSchedClass();
327  return MCSchedModel::getReciprocalThroughput(SchedClass,
329  }
330 
331  if (hasInstrSchedModel())
333 
334  return 0.0;
335 }
336 
337 double
339  unsigned SchedClass = TII->get(Opcode).getSchedClass();
340  if (hasInstrItineraries())
341  return MCSchedModel::getReciprocalThroughput(SchedClass,
343  if (hasInstrSchedModel()) {
344  const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass);
345  if (SCDesc.isValid() && !SCDesc.isVariant())
346  return MCSchedModel::getReciprocalThroughput(*STI, SCDesc);
347  }
348 
349  return 0.0;
350 }
351 
352 double
354  if (hasInstrSchedModel())
355  return SchedModel.getReciprocalThroughput(*STI, *TII, MI);
356  return computeReciprocalThroughput(MI.getOpcode());
357 }
358 
i
i
Definition: README.txt:29
llvm::TargetSchedModel::mustEndGroup
bool mustEndGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if current group must end.
Definition: TargetSchedule.cpp:95
llvm::MCSubtargetInfo::getWriteProcResEnd
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
Definition: MCSubtargetInfo.h:171
llvm::MCWriteLatencyEntry::Cycles
int16_t Cycles
Definition: MCSchedule.h:78
llvm::MCProcResourceDesc::BufferSize
int BufferSize
Definition: MCSchedule.h:48
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:104
MachineInstr.h
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
EnableSchedModel
static cl::opt< bool > EnableSchedModel("schedmodel", cl::Hidden, cl::init(true), cl::desc("Use TargetSchedModel for latency lookup"))
UseMI
MachineInstrBuilder & UseMI
Definition: AArch64ExpandPseudoInsts.cpp:103
llvm::Latency
@ Latency
Definition: SIMachineScheduler.h:34
MCInstrDesc.h
llvm::TargetSubtargetInfo::resolveSchedClass
virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant p...
Definition: TargetSubtargetInfo.h:141
llvm::InstrItineraryData::getNumMicroOps
int getNumMicroOps(unsigned ItinClassIndx) const
Return the number of micro-ops that the given class decodes to.
Definition: MCInstrItineraries.h:228
llvm::MCSubtargetInfo::getSchedModel
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
Definition: MCSubtargetInfo.h:163
llvm::MCSchedClassDesc::NumReadAdvanceEntries
uint16_t NumReadAdvanceEntries
Definition: MCSchedule.h:125
llvm::TargetSubtargetInfo::getInstrInfo
virtual const TargetInstrInfo * getInstrInfo() const
Definition: TargetSubtargetInfo.h:93
llvm::MCInstrDesc::getSchedClass
unsigned getSchedClass() const
Return the scheduling class for this instruction.
Definition: MCInstrDesc.h:618
ErrorHandling.h
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MCProcResourceDesc::NumUnits
unsigned NumUnits
Definition: MCSchedule.h:33
llvm::TargetSubtargetInfo::getRegisterInfo
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
Definition: TargetSubtargetInfo.h:125
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:234
llvm::TargetSchedModel::computeOutputLatency
unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *DepMI) const
Output dependency latency of a pair of defs of the same register.
Definition: TargetSchedule.cpp:289
llvm::MachineInstr::getDesc
const MCInstrDesc & getDesc() const
Returns the target instruction descriptor of this MachineInstr.
Definition: MachineInstr.h:488
llvm::MCSchedModel::isOutOfOrder
bool isOutOfOrder() const
Return true if machine supports out of order execution.
Definition: MCSchedule.h:333
TargetInstrInfo.h
llvm::MachineInstr::getMF
const MachineFunction * getMF() const
Return the function that contains the basic block that this instruction belongs to.
Definition: MachineInstr.cpp:636
llvm::max
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
Definition: FileCheck.cpp:337
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:893
llvm::MCWriteProcResEntry
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Definition: MCSchedule.h:63
llvm::MCInst
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
llvm::TargetSchedModel::getInstrItineraries
const InstrItineraryData * getInstrItineraries() const
Definition: TargetSchedule.h:82
llvm::InstrItineraryData::getOperandCycle
int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const
Return the cycle for the given class and operand.
Definition: MCInstrItineraries.h:167
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1622
llvm::MCSchedClassDesc::isValid
bool isValid() const
Definition: MCSchedule.h:127
llvm::MCSchedModel::getNumProcResourceKinds
unsigned getNumProcResourceKinds() const
Definition: MCSchedule.h:335
llvm::TargetSchedModel::init
void init(const TargetSubtargetInfo *TSInfo)
Initialize the machine model for instruction scheduling.
Definition: TargetSchedule.cpp:62
CommandLine.h
MCInstrItineraries.h
llvm::MachineOperand::isImplicit
bool isImplicit() const
Definition: MachineOperand.h:379
lcm
static unsigned lcm(unsigned A, unsigned B)
Definition: TargetSchedule.cpp:56
llvm::PPCISD::SC
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
Definition: PPCISelLowering.h:418
llvm::MachineInstr::getOperand
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:501
llvm::MCSchedClassDesc
Summarize the scheduling resources required for an instruction of a particular scheduling class.
Definition: MCSchedule.h:109
llvm::TargetInstrInfo::getNumMicroOps
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr &MI) const
Return the number of u-operations the given machine instruction will be decoded to on the target cpu.
Definition: TargetInstrInfo.cpp:1119
B
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::TargetSchedModel::hasInstrItineraries
bool hasInstrItineraries() const
Return true if this machine model includes cycle-to-cycle itinerary data.
Definition: TargetSchedule.cpp:42
llvm::TargetSchedModel::computeReciprocalThroughput
double computeReciprocalThroughput(const MachineInstr *MI) const
Compute the reciprocal throughput of the given instruction.
Definition: TargetSchedule.cpp:324
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void resize(size_type N)
Definition: SmallVector.h:619
llvm::MCSubtargetInfo::getWriteLatencyEntry
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
Definition: MCSubtargetInfo.h:176
llvm::TargetInstrInfo::defaultDefLatency
unsigned defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr &DefMI) const
Return the default expected latency for a def based on its opcode.
Definition: TargetInstrInfo.cpp:1135
llvm::MCSchedModel::computeInstrLatency
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
Definition: MCSchedule.cpp:40
llvm::MCOperandInfo::isOptionalDef
bool isOptionalDef() const
Set if this operand is a optional def.
Definition: MCInstrDesc.h:112
llvm::TargetSchedModel::resolveSchedClass
const MCSchedClassDesc * resolveSchedClass(const MachineInstr *MI) const
Return the MCSchedClassDesc for this instruction.
Definition: TargetSchedule.cpp:132
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const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:656
findDefIdx
static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx)
Find the def index of this operand.
Definition: TargetSchedule.cpp:156
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static unsigned capLatency(int Cycles)
Definition: TargetSchedule.cpp:125
llvm::cl::opt< bool >
TargetSchedule.h
MCSchedule.h
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bool isReg() const
isReg - Tests if this is a MO_Register operand.
Definition: MachineOperand.h:320
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
uint64_t
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unsigned IssueWidth
Definition: MCSchedule.h:256
llvm::TargetInstrInfo::isPredicated
virtual bool isPredicated(const MachineInstr &MI) const
Returns true if the instruction is already predicated.
Definition: TargetInstrInfo.h:1435
llvm::MCWriteLatencyEntry
Specify the latency in cpu cycles for a particular scheduling class and def index.
Definition: MCSchedule.h:77
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initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
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const MCOperandInfo * OpInfo
Definition: MCInstrDesc.h:208
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:359
llvm::TargetSchedModel::computeOperandLatency
unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOperIdx, const MachineInstr *UseMI, unsigned UseOperIdx) const
Compute operand latency based on the available machine model.
Definition: TargetSchedule.cpp:183
EnableSchedItins
static cl::opt< bool > EnableSchedItins("scheditins", cl::Hidden, cl::init(true), cl::desc("Use InstrItineraryData for latency lookup"))
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bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
Definition: MachineInstr.h:1346
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void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
Definition: MCSubtargetInfo.cpp:333
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Definition: MachineFunction.h:257
llvm::MCSubtargetInfo::getWriteProcResBegin
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
Definition: MCSubtargetInfo.h:167
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
TargetSubtargetInfo.h
llvm::MachineOperand::isDef
bool isDef() const
Definition: MachineOperand.h:374
llvm::MCSchedModel::isComplete
bool isComplete() const
Return true if this machine model data for all instructions with a scheduling class (itinerary class ...
Definition: MCSchedule.h:330
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:60
llvm::TargetSchedModel::getNumMicroOps
unsigned getNumMicroOps(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return the number of issue slots required for this MI.
Definition: TargetSchedule.cpp:106
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineOperand::readsReg
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
Definition: MachineOperand.h:457
llvm::MCSchedClassDesc::isVariant
bool isVariant() const
Definition: MCSchedule.h:130
llvm::MCSchedModel::getProcResource
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Definition: MCSchedule.h:339
gcd
static unsigned gcd(unsigned Dividend, unsigned Divisor)
Definition: TargetSchedule.cpp:46
llvm::MCInst::getOpcode
unsigned getOpcode() const
Definition: MCInst.h:198
llvm::TargetInstrInfo::getInstrLatency
virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr &MI, unsigned *PredCost=nullptr) const
Compute the instruction latency of a given instruction.
Definition: TargetInstrInfo.cpp:1150
llvm::TargetSchedModel::mustBeginGroup
bool mustBeginGroup(const MachineInstr *MI, const MCSchedClassDesc *SC=nullptr) const
Return true if new group must begin.
Definition: TargetSchedule.cpp:84
llvm::MCSchedModel::getReciprocalThroughput
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Definition: MCSchedule.cpp:88
llvm::MCSubtargetInfo::getReadAdvanceCycles
int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, unsigned WriteResID) const
Definition: MCSubtargetInfo.h:184
findUseIdx
static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx)
Find the use index of this operand.
Definition: TargetSchedule.cpp:172
DefMI
MachineInstrBuilder MachineInstrBuilder & DefMI
Definition: AArch64ExpandPseudoInsts.cpp:104
llvm::TargetInstrInfo::getOperandLatency
virtual int getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const
Definition: TargetInstrInfo.cpp:1088
llvm::MCSchedModel::getSchedClassDesc
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
Definition: MCSchedule.h:346
llvm::MachineInstr::isTransient
bool isTransient() const
Return true if this is a transient instruction that is either very likely to be eliminated during reg...
Definition: MachineInstr.h:1319
MachineOperand.h
llvm::MCInstrInfo::get
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
llvm::MCSchedModel::hasInstrSchedModel
bool hasInstrSchedModel() const
Does this machine model include instruction-level scheduling.
Definition: MCSchedule.h:320
llvm::cl::desc
Definition: CommandLine.h:405
llvm::MCWriteLatencyEntry::WriteResourceID
uint16_t WriteResourceID
Definition: MCSchedule.h:79
raw_ostream.h
MachineFunction.h
llvm::InstrItineraryData::isEmpty
bool isEmpty() const
Returns true if there are no itineraries.
Definition: MCInstrItineraries.h:126
llvm::TargetSchedModel::hasInstrSchedModel
bool hasInstrSchedModel() const
Return true if this machine model includes an instruction-level scheduling model.
Definition: TargetSchedule.cpp:38