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42 if (Implies.
test(FE.Value))
51 if (FE.Implies.getAsBitset().test(
Value)) {
61 "Feature flags should start with '+' or '-'");
81 errs() <<
"'" << Feature <<
"' is not a recognized feature for this target"
82 <<
" (ignoring feature)\n";
91 MaxLen =
std::max(MaxLen, std::strlen(
I.Key));
100 static bool PrintOnce =
false;
110 errs() <<
"Available CPUs for this target:\n\n";
111 for (
auto &CPU : CPUTable)
112 errs() <<
format(
" %-*s - Select the %s processor.\n", MaxCPULen, CPU.Key,
117 errs() <<
"Available features for this target:\n\n";
118 for (
auto &Feature : FeatTable)
119 errs() <<
format(
" %-*s - %s.\n", MaxFeatLen, Feature.Key, Feature.Desc);
122 errs() <<
"Use +feature to enable a feature, or -feature to disable it.\n"
123 "For example, llc -mcpu=mycpu -mattr=+feature1,-feature2\n";
132 static bool PrintOnce =
false;
138 errs() <<
"Available CPUs for this target:\n\n";
139 for (
auto &CPU : CPUTable)
140 errs() <<
"\t" << CPU.Key <<
"\n";
143 errs() <<
"Use -mcpu or -mtune to specify the target's processor.\n"
144 "For example, clang --target=aarch64-unknown-linux-gui "
145 "-mcpu=cortex-a35\n";
165 Help(ProcDesc, ProcFeatures);
168 else if (!CPU.
empty()) {
176 errs() <<
"'" << CPU <<
"' is not a recognized processor for this target"
177 <<
" (ignoring processor)\n";
181 if (!TuneCPU.
empty()) {
188 }
else if (TuneCPU != CPU) {
189 errs() <<
"'" << TuneCPU <<
"' is not a recognized processor for this "
190 <<
"target (ignoring processor)\n";
195 for (
const std::string &Feature : Features.
getFeatures()) {
197 if (Feature ==
"+help")
198 Help(ProcDesc, ProcFeatures);
199 else if (Feature ==
"+cpuhelp")
210 FeatureBits =
getFeatures(CPU, TuneCPU,
FS, ProcDesc, ProcFeatures);
211 FeatureString = std::string(
FS);
213 if (!TuneCPU.
empty())
221 FeatureBits =
getFeatures(CPU, TuneCPU,
FS, ProcDesc, ProcFeatures);
222 FeatureString = std::string(
FS);
234 ProcFeatures(PF), ProcDesc(
PD), WriteProcResTable(WPR),
235 WriteLatencyTable(WL), ReadAdvanceTable(
RA), Stages(IS),
236 OperandCycles(
OC), ForwardingPaths(
FP) {
241 FeatureBits.
flip(FB);
258 for (
unsigned I = 0,
E = FB.
size();
I <
E;
I++) {
273 if (FeatureBits.
test(FeatureEntry->
Value)) {
278 FeatureBits.
set(FeatureEntry->
Value);
285 errs() <<
"'" << Feature <<
"' is not a recognized feature for this target"
286 <<
" (ignoring feature)\n";
300 for (std::string
F :
T.getFeatures()) {
306 return (FeatureBits &
All) == Set;
311 "Processor machine model table is not sorted");
319 <<
"' is not a recognized processor for this target"
320 <<
" (ignoring processor)\n";
364 unsigned NumStridedMemAccesses,
365 unsigned NumPrefetches,
366 bool HasCall)
const {
virtual bool enableWritePrefetching() const
virtual Optional< unsigned > getCacheSize(unsigned Level) const
Return the cache size in bytes for the given level of cache.
const FeatureBitset & getAsBitset() const
This is an optimization pass for GlobalISel generic memory operations.
virtual unsigned getCacheLineSize() const
Return the target cache line size in bytes.
unsigned Value
K-V integer value.
static void ApplyFeatureFlag(FeatureBitset &Bits, StringRef Feature, ArrayRef< SubtargetFeatureKV > FeatureTable)
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
auto lower_bound(R &&Range, T &&Value)
Provide wrappers to std::lower_bound which take ranges instead of having to pass begin/end explicitly...
Triple - Helper class for working with autoconf configuration names.
static void Help(ArrayRef< SubtargetSubTypeKV > CPUTable, ArrayRef< SubtargetFeatureKV > FeatTable)
Display help for feature and mcpu choices.
InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const
Get scheduling itinerary of a CPU.
Container class for subtarget features.
Expected< ExpressionValue > max(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
static size_t getLongestEntryLength(ArrayRef< T > Table)
Return the length of the longest entry in the table.
static StringRef StripFlag(StringRef Feature)
Return string stripped of flag.
bool empty() const
empty - Check if the array is empty.
const MCSchedModel * SchedModel
virtual unsigned getMaxPrefetchIterationsAhead() const
Return the maximum prefetch distance in terms of loop iterations.
virtual unsigned getPrefetchDistance() const
Return the preferred prefetch distance in terms of instructions.
static void SetImpliedBits(FeatureBitset &Bits, const FeatureBitset &Implies, ArrayRef< SubtargetFeatureKV > FeatureTable)
For each feature that is (transitively) implied by this feature, set it.
static bool isEnabled(StringRef Feature)
Return true if enable flag; '+'.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
(vector float) vec_cmpeq(*A, *B) C
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Manages the enabling and disabling of subtarget specific features.
const MCSchedModel & getSchedModelForCPU(StringRef CPU) const
Get the machine model of a CPU.
Used to provide key value pairs for feature and CPU bit flags.
FeatureBitset ApplyFeatureFlag(StringRef FS)
Apply a feature flag and return the re-computed feature bits, including all feature bits implied by t...
FeatureBitset ToggleFeature(uint64_t FB)
Toggle a feature and return the re-computed feature bits.
constexpr FeatureBitset & flip(unsigned I)
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Specify the latency in cpu cycles for a particular scheduling class and def index.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU, StringRef FS)
Initialize the scheduling model and feature bits.
FeatureBitset ClearFeatureBitsTransitively(const FeatureBitset &FB)
constexpr size_t size() const
SI optimize exec mask operations pre RA
Used to provide key value pairs for feature and CPU bit flags.
FeatureBitArray Implies
K-V bit mask.
virtual unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
Return the minimum stride necessary to trigger software prefetching.
static const T * Find(StringRef S, ArrayRef< T > A)
Find KV in array using binary search.
void initInstrItins(InstrItineraryData &InstrItins) const
Initialize an InstrItineraryData instance.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
StringRef - Represent a constant reference to a string, i.e.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
constexpr FeatureBitset & reset(unsigned I)
FeatureBitset SetFeatureBitsTransitively(const FeatureBitset &FB)
Set/clear additional feature bits, including all other bits they imply.
These values represent a non-pipelined step in the execution of an instruction.
static const MCSchedModel & GetDefaultSchedModel()
Returns the default initialized model.
static void cpuHelp(ArrayRef< SubtargetSubTypeKV > CPUTable)
Display help for mcpu choices only.
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
static void ClearImpliedBits(FeatureBitset &Bits, unsigned Value, ArrayRef< SubtargetFeatureKV > FeatureTable)
For each feature that (transitively) implies this feature, clear it.
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
Machine model for scheduling, bundling, and heuristics.
static bool hasFlag(StringRef Feature)
Determine if a feature has a flag; '+' or '-'.
bool checkFeatures(StringRef FS) const
Check whether the subtarget features are enabled/disabled as per the provided string,...
static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS, ArrayRef< SubtargetSubTypeKV > ProcDesc, ArrayRef< SubtargetFeatureKV > ProcFeatures)
FeatureBitArray Implies
K-V bit mask.
constexpr bool test(unsigned I) const
FeatureBitArray TuneImplies
K-V bit mask.
void setDefaultFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS)
Set the features to the default for the given CPU and TuneCPU, with ano appended feature string.
virtual Optional< unsigned > getCacheAssociativity(unsigned Level) const
Return the cache associatvity for the given level of cache.
LLVM Value Representation.
Itinerary data supplied by a subtarget to be used by a target.