Go to the documentation of this file.
18 #include <type_traits>
22 static_assert(std::is_pod<MCSchedModel>::value,
23 "We shouldn't have a static constructor here");
25 DefaultMicroOpBufferSize,
26 DefaultLoopMicroOpBufferSize,
29 DefaultMispredictPenalty,
44 DefIdx != DefEnd; ++DefIdx) {
57 unsigned SchedClass)
const {
69 const MCInst &Inst)
const {
98 double Temp = NumUnits * 1.0 /
I->Cycles;
112 const MCInst &Inst)
const {
139 for (;
I !=
E; ++
I) {
155 unsigned WriteResourceID) {
161 if (
E.WriteResourceID != WriteResourceID)
163 DelayCycles =
std::min(DelayCycles,
E.Cycles);
const MCWriteProcResEntry * getWriteProcResEnd(const MCSchedClassDesc *SC) const
This class represents lattice values for constants.
uint16_t NumWriteLatencyEntries
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget's CPU.
unsigned getSchedClass() const
Return the scheduling class for this instruction.
static unsigned getForwardingDelayCycles(ArrayRef< MCReadAdvanceEntry > Entries, unsigned WriteResourceIdx=0)
Returns the maximum forwarding delay for register reads dependent on writes of scheduling class Write...
Identify one of the processor resource kinds consumed by a particular scheduling class for the specif...
Instances of this class represent a single low-level machine instruction.
const InstrStage * endStage(unsigned ItinClassIndx) const
Return the last+1 stage of the itinerary.
constexpr bool hasValue() const
virtual unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const
Resolve a variant scheduling class for the given MCInst and CPU.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Summarize the scheduling resources required for an instruction of a particular scheduling class.
const MCWriteLatencyEntry * getWriteLatencyEntry(const MCSchedClassDesc *SC, unsigned DefIdx) const
static const MCSchedModel Default
static int computeInstrLatency(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Returns the latency value for the scheduling class.
unsigned countPopulation(T Value)
Count the number of set bits in a value.
Specify the latency in cpu cycles for a particular scheduling class and def index.
const MCWriteProcResEntry * getWriteProcResBegin(const MCSchedClassDesc *SC) const
Return an iterator at the first process resource consumed by the given scheduling class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
unsigned getProcessorID() const
Expected< ExpressionValue > min(const ExpressionValue &Lhs, const ExpressionValue &Rhs)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
These values represent a non-pipelined step in the execution of an instruction.
Interface to description of machine instruction set.
const MCProcResourceDesc * getProcResource(unsigned ProcResourceIdx) const
Specify the number of cycles allowed after instruction issue before a particular use operand reads it...
unsigned getOpcode() const
Machine model for scheduling, bundling, and heuristics.
static double getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc)
Align max(MaybeAlign Lhs, Align Rhs)
const MCSchedClassDesc * getSchedClassDesc(unsigned SchedClassIdx) const
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
const InstrStage * beginStage(unsigned ItinClassIndx) const
Return the first stage of the itinerary.
APFloat abs(APFloat X)
Returns the absolute value of the argument.
Generic base class for all target subtargets.
static const unsigned DefaultIssueWidth
Itinerary data supplied by a subtarget to be used by a target.
constexpr const T & getValue() const LLVM_LVALUE_FUNCTION